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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Copyright (C) 2015-2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2023 Intel Corporation
5 */
6#include <linux/module.h>
7#include <linux/stringify.h>
8#include "iwl-config.h"
9#include "iwl-prph.h"
10#include "fw/api/txq.h"
11
12/* Highest firmware API version supported */
13#define IWL_22000_UCODE_API_MAX 77
14
15/* Lowest firmware API version supported */
16#define IWL_22000_UCODE_API_MIN 50
17
18/* NVM versions */
19#define IWL_22000_NVM_VERSION 0x0a1d
20
21/* Memory offsets and lengths */
22#define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */
23#define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */
24#define IWL_22000_DCCM2_OFFSET 0x880000
25#define IWL_22000_DCCM2_LEN 0x8000
26#define IWL_22000_SMEM_OFFSET 0x400000
27#define IWL_22000_SMEM_LEN 0xD0000
28
29#define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0"
30#define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0"
31#define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0"
32#define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0"
33#define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0"
34#define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0"
35#define IWL_CC_A_FW_PRE "iwlwifi-cc-a0"
36
37#define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \
38 IWL_QU_B_HR_B_FW_PRE "-" __stringify(api) ".ucode"
39#define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \
40 IWL_QUZ_A_HR_B_FW_PRE "-" __stringify(api) ".ucode"
41#define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \
42 IWL_QUZ_A_JF_B_FW_PRE "-" __stringify(api) ".ucode"
43#define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \
44 IWL_QU_C_HR_B_FW_PRE "-" __stringify(api) ".ucode"
45#define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \
46 IWL_QU_B_JF_B_FW_PRE "-" __stringify(api) ".ucode"
47#define IWL_CC_A_MODULE_FIRMWARE(api) \
48 IWL_CC_A_FW_PRE "-" __stringify(api) ".ucode"
49
50static const struct iwl_base_params iwl_22000_base_params = {
51 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
52 .num_of_queues = 512,
53 .max_tfd_queue_size = 256,
54 .shadow_ram_support = true,
55 .led_compensation = 57,
56 .wd_timeout = IWL_LONG_WD_TIMEOUT,
57 .max_event_log_size = 512,
58 .shadow_reg_enable = true,
59 .pcie_l1_allowed = true,
60};
61
62const struct iwl_ht_params iwl_22000_ht_params = {
63 .stbc = true,
64 .ldpc = true,
65 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
66 BIT(NL80211_BAND_6GHZ),
67};
68
69#define IWL_DEVICE_22000_COMMON \
70 .ucode_api_min = IWL_22000_UCODE_API_MIN, \
71 .led_mode = IWL_LED_RF_STATE, \
72 .nvm_hw_section_num = 10, \
73 .non_shared_ant = ANT_B, \
74 .dccm_offset = IWL_22000_DCCM_OFFSET, \
75 .dccm_len = IWL_22000_DCCM_LEN, \
76 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \
77 .dccm2_len = IWL_22000_DCCM2_LEN, \
78 .smem_offset = IWL_22000_SMEM_OFFSET, \
79 .smem_len = IWL_22000_SMEM_LEN, \
80 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \
81 .apmg_not_supported = true, \
82 .trans.mq_rx_supported = true, \
83 .vht_mu_mimo_supported = true, \
84 .mac_addr_from_csr = 0x380, \
85 .ht_params = &iwl_22000_ht_params, \
86 .nvm_ver = IWL_22000_NVM_VERSION, \
87 .trans.rf_id = true, \
88 .trans.gen2 = true, \
89 .nvm_type = IWL_NVM_EXT, \
90 .dbgc_supported = true, \
91 .min_umac_error_event_table = 0x400000, \
92 .d3_debug_data_base_addr = 0x401000, \
93 .d3_debug_data_length = 60 * 1024, \
94 .mon_smem_regs = { \
95 .write_ptr = { \
96 .addr = LDBG_M2S_BUF_WPTR, \
97 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \
98 }, \
99 .cycle_cnt = { \
100 .addr = LDBG_M2S_BUF_WRAP_CNT, \
101 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \
102 }, \
103 }
104
105#define IWL_DEVICE_22500 \
106 IWL_DEVICE_22000_COMMON, \
107 .ucode_api_max = IWL_22000_UCODE_API_MAX, \
108 .trans.device_family = IWL_DEVICE_FAMILY_22000, \
109 .trans.base_params = &iwl_22000_base_params, \
110 .gp2_reg_addr = 0xa02c68, \
111 .mon_dram_regs = { \
112 .write_ptr = { \
113 .addr = MON_BUFF_WRPTR_VER2, \
114 .mask = 0xffffffff, \
115 }, \
116 .cycle_cnt = { \
117 .addr = MON_BUFF_CYCLE_CNT_VER2, \
118 .mask = 0xffffffff, \
119 }, \
120 }
121
122const struct iwl_cfg_trans_params iwl_qu_trans_cfg = {
123 .mq_rx_supported = true,
124 .rf_id = true,
125 .gen2 = true,
126 .device_family = IWL_DEVICE_FAMILY_22000,
127 .base_params = &iwl_22000_base_params,
128 .integrated = true,
129 .xtal_latency = 500,
130 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
131};
132
133const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = {
134 .mq_rx_supported = true,
135 .rf_id = true,
136 .gen2 = true,
137 .device_family = IWL_DEVICE_FAMILY_22000,
138 .base_params = &iwl_22000_base_params,
139 .integrated = true,
140 .xtal_latency = 1820,
141 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US,
142};
143
144const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = {
145 .mq_rx_supported = true,
146 .rf_id = true,
147 .gen2 = true,
148 .device_family = IWL_DEVICE_FAMILY_22000,
149 .base_params = &iwl_22000_base_params,
150 .integrated = true,
151 .xtal_latency = 12000,
152 .low_latency_xtal = true,
153 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
154};
155
156/*
157 * If the device doesn't support HE, no need to have that many buffers.
158 * 22000 devices can split multiple frames into a single RB, so fewer are
159 * needed; AX210 cannot (but use smaller RBs by default) - these sizes
160 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with
161 * additional overhead to account for processing time.
162 */
163#define IWL_NUM_RBDS_NON_HE 512
164#define IWL_NUM_RBDS_22000_HE 2048
165
166/*
167 * All JF radio modules are part of the 9000 series, but the MAC part
168 * looks more like 22000. That's why this device is here, but called
169 * 9560 nevertheless.
170 */
171const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = {
172 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
173 IWL_DEVICE_22500,
174 .num_rbds = IWL_NUM_RBDS_NON_HE,
175};
176
177const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = {
178 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE,
179 IWL_DEVICE_22500,
180 .num_rbds = IWL_NUM_RBDS_NON_HE,
181};
182
183const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = {
184 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE,
185 IWL_DEVICE_22500,
186 /*
187 * This device doesn't support receiving BlockAck with a large bitmap
188 * so we need to restrict the size of transmitted aggregation to the
189 * HT size; mac80211 would otherwise pick the HE max (256) by default.
190 */
191 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
192 .num_rbds = IWL_NUM_RBDS_NON_HE,
193};
194
195const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = {
196 .device_family = IWL_DEVICE_FAMILY_22000,
197 .base_params = &iwl_22000_base_params,
198 .mq_rx_supported = true,
199 .rf_id = true,
200 .gen2 = true,
201 .bisr_workaround = 1,
202};
203
204const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101";
205const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz";
206const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
207const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203";
208const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz";
209
210const char iwl_ax200_killer_1650w_name[] =
211 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)";
212const char iwl_ax200_killer_1650x_name[] =
213 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)";
214const char iwl_ax201_killer_1650s_name[] =
215 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)";
216const char iwl_ax201_killer_1650i_name[] =
217 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)";
218
219const struct iwl_cfg iwl_qu_b0_hr1_b0 = {
220 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
221 IWL_DEVICE_22500,
222 /*
223 * This device doesn't support receiving BlockAck with a large bitmap
224 * so we need to restrict the size of transmitted aggregation to the
225 * HT size; mac80211 would otherwise pick the HE max (256) by default.
226 */
227 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
228 .tx_with_siso_diversity = true,
229 .num_rbds = IWL_NUM_RBDS_22000_HE,
230};
231
232const struct iwl_cfg iwl_qu_b0_hr_b0 = {
233 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
234 IWL_DEVICE_22500,
235 /*
236 * This device doesn't support receiving BlockAck with a large bitmap
237 * so we need to restrict the size of transmitted aggregation to the
238 * HT size; mac80211 would otherwise pick the HE max (256) by default.
239 */
240 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
241 .num_rbds = IWL_NUM_RBDS_22000_HE,
242};
243
244const struct iwl_cfg iwl_ax201_cfg_qu_hr = {
245 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
246 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
247 IWL_DEVICE_22500,
248 /*
249 * This device doesn't support receiving BlockAck with a large bitmap
250 * so we need to restrict the size of transmitted aggregation to the
251 * HT size; mac80211 would otherwise pick the HE max (256) by default.
252 */
253 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
254 .num_rbds = IWL_NUM_RBDS_22000_HE,
255};
256
257const struct iwl_cfg iwl_qu_c0_hr1_b0 = {
258 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
259 IWL_DEVICE_22500,
260 /*
261 * This device doesn't support receiving BlockAck with a large bitmap
262 * so we need to restrict the size of transmitted aggregation to the
263 * HT size; mac80211 would otherwise pick the HE max (256) by default.
264 */
265 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
266 .tx_with_siso_diversity = true,
267 .num_rbds = IWL_NUM_RBDS_22000_HE,
268};
269
270const struct iwl_cfg iwl_qu_c0_hr_b0 = {
271 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
272 IWL_DEVICE_22500,
273 /*
274 * This device doesn't support receiving BlockAck with a large bitmap
275 * so we need to restrict the size of transmitted aggregation to the
276 * HT size; mac80211 would otherwise pick the HE max (256) by default.
277 */
278 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
279 .num_rbds = IWL_NUM_RBDS_22000_HE,
280};
281
282const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = {
283 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
284 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
285 IWL_DEVICE_22500,
286 /*
287 * This device doesn't support receiving BlockAck with a large bitmap
288 * so we need to restrict the size of transmitted aggregation to the
289 * HT size; mac80211 would otherwise pick the HE max (256) by default.
290 */
291 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
292 .num_rbds = IWL_NUM_RBDS_22000_HE,
293};
294
295const struct iwl_cfg iwl_quz_a0_hr1_b0 = {
296 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
297 IWL_DEVICE_22500,
298 /*
299 * This device doesn't support receiving BlockAck with a large bitmap
300 * so we need to restrict the size of transmitted aggregation to the
301 * HT size; mac80211 would otherwise pick the HE max (256) by default.
302 */
303 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
304 .tx_with_siso_diversity = true,
305 .num_rbds = IWL_NUM_RBDS_22000_HE,
306};
307
308const struct iwl_cfg iwl_ax201_cfg_quz_hr = {
309 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
310 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
311 IWL_DEVICE_22500,
312 /*
313 * This device doesn't support receiving BlockAck with a large bitmap
314 * so we need to restrict the size of transmitted aggregation to the
315 * HT size; mac80211 would otherwise pick the HE max (256) by default.
316 */
317 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
318 .num_rbds = IWL_NUM_RBDS_22000_HE,
319};
320
321const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = {
322 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
323 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
324 IWL_DEVICE_22500,
325 /*
326 * This device doesn't support receiving BlockAck with a large bitmap
327 * so we need to restrict the size of transmitted aggregation to the
328 * HT size; mac80211 would otherwise pick the HE max (256) by default.
329 */
330 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
331 .num_rbds = IWL_NUM_RBDS_22000_HE,
332};
333
334const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = {
335 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
336 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
337 IWL_DEVICE_22500,
338 /*
339 * This device doesn't support receiving BlockAck with a large bitmap
340 * so we need to restrict the size of transmitted aggregation to the
341 * HT size; mac80211 would otherwise pick the HE max (256) by default.
342 */
343 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
344 .num_rbds = IWL_NUM_RBDS_22000_HE,
345};
346
347const struct iwl_cfg iwl_ax200_cfg_cc = {
348 .fw_name_pre = IWL_CC_A_FW_PRE,
349 IWL_DEVICE_22500,
350 /*
351 * This device doesn't support receiving BlockAck with a large bitmap
352 * so we need to restrict the size of transmitted aggregation to the
353 * HT size; mac80211 would otherwise pick the HE max (256) by default.
354 */
355 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
356 .num_rbds = IWL_NUM_RBDS_22000_HE,
357};
358
359const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = {
360 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
361 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
362 IWL_DEVICE_22500,
363 /*
364 * This device doesn't support receiving BlockAck with a large bitmap
365 * so we need to restrict the size of transmitted aggregation to the
366 * HT size; mac80211 would otherwise pick the HE max (256) by default.
367 */
368 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
369 .num_rbds = IWL_NUM_RBDS_22000_HE,
370};
371
372const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = {
373 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
374 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
375 IWL_DEVICE_22500,
376 /*
377 * This device doesn't support receiving BlockAck with a large bitmap
378 * so we need to restrict the size of transmitted aggregation to the
379 * HT size; mac80211 would otherwise pick the HE max (256) by default.
380 */
381 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
382 .num_rbds = IWL_NUM_RBDS_22000_HE,
383};
384
385const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = {
386 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
387 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
388 IWL_DEVICE_22500,
389 /*
390 * This device doesn't support receiving BlockAck with a large bitmap
391 * so we need to restrict the size of transmitted aggregation to the
392 * HT size; mac80211 would otherwise pick the HE max (256) by default.
393 */
394 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
395 .num_rbds = IWL_NUM_RBDS_22000_HE,
396};
397
398const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = {
399 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
400 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
401 IWL_DEVICE_22500,
402 /*
403 * This device doesn't support receiving BlockAck with a large bitmap
404 * so we need to restrict the size of transmitted aggregation to the
405 * HT size; mac80211 would otherwise pick the HE max (256) by default.
406 */
407 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
408 .num_rbds = IWL_NUM_RBDS_22000_HE,
409};
410
411const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = {
412 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
413 IWL_DEVICE_22500,
414 /*
415 * This device doesn't support receiving BlockAck with a large bitmap
416 * so we need to restrict the size of transmitted aggregation to the
417 * HT size; mac80211 would otherwise pick the HE max (256) by default.
418 */
419 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
420 .num_rbds = IWL_NUM_RBDS_22000_HE,
421};
422
423MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
424MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
425MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
426MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
427MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
428MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Copyright (C) 2015-2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2022 Intel Corporation
5 */
6#include <linux/module.h>
7#include <linux/stringify.h>
8#include "iwl-config.h"
9#include "iwl-prph.h"
10#include "fw/api/txq.h"
11
12/* Highest firmware API version supported */
13#define IWL_22000_UCODE_API_MAX 72
14
15/* Lowest firmware API version supported */
16#define IWL_22000_UCODE_API_MIN 39
17
18/* NVM versions */
19#define IWL_22000_NVM_VERSION 0x0a1d
20
21/* Memory offsets and lengths */
22#define IWL_22000_DCCM_OFFSET 0x800000 /* LMAC1 */
23#define IWL_22000_DCCM_LEN 0x10000 /* LMAC1 */
24#define IWL_22000_DCCM2_OFFSET 0x880000
25#define IWL_22000_DCCM2_LEN 0x8000
26#define IWL_22000_SMEM_OFFSET 0x400000
27#define IWL_22000_SMEM_LEN 0xD0000
28
29#define IWL_QU_B_HR_B_FW_PRE "iwlwifi-Qu-b0-hr-b0-"
30#define IWL_QNJ_B_HR_B_FW_PRE "iwlwifi-QuQnj-b0-hr-b0-"
31#define IWL_QU_C_HR_B_FW_PRE "iwlwifi-Qu-c0-hr-b0-"
32#define IWL_QU_B_JF_B_FW_PRE "iwlwifi-Qu-b0-jf-b0-"
33#define IWL_QU_C_JF_B_FW_PRE "iwlwifi-Qu-c0-jf-b0-"
34#define IWL_QUZ_A_HR_B_FW_PRE "iwlwifi-QuZ-a0-hr-b0-"
35#define IWL_QUZ_A_JF_B_FW_PRE "iwlwifi-QuZ-a0-jf-b0-"
36#define IWL_QNJ_B_JF_B_FW_PRE "iwlwifi-QuQnj-b0-jf-b0-"
37#define IWL_CC_A_FW_PRE "iwlwifi-cc-a0-"
38#define IWL_SO_A_JF_B_FW_PRE "iwlwifi-so-a0-jf-b0-"
39#define IWL_SO_A_HR_B_FW_PRE "iwlwifi-so-a0-hr-b0-"
40#define IWL_SO_A_GF_A_FW_PRE "iwlwifi-so-a0-gf-a0-"
41#define IWL_TY_A_GF_A_FW_PRE "iwlwifi-ty-a0-gf-a0-"
42#define IWL_SO_A_GF4_A_FW_PRE "iwlwifi-so-a0-gf4-a0-"
43#define IWL_SO_A_MR_A_FW_PRE "iwlwifi-so-a0-mr-a0-"
44#define IWL_SNJ_A_GF4_A_FW_PRE "iwlwifi-SoSnj-a0-gf4-a0-"
45#define IWL_SNJ_A_GF_A_FW_PRE "iwlwifi-SoSnj-a0-gf-a0-"
46#define IWL_SNJ_A_HR_B_FW_PRE "iwlwifi-SoSnj-a0-hr-b0-"
47#define IWL_SNJ_A_JF_B_FW_PRE "iwlwifi-SoSnj-a0-jf-b0-"
48#define IWL_MA_A_HR_B_FW_PRE "iwlwifi-ma-a0-hr-b0-"
49#define IWL_MA_A_GF_A_FW_PRE "iwlwifi-ma-a0-gf-a0-"
50#define IWL_MA_A_GF4_A_FW_PRE "iwlwifi-ma-a0-gf4-a0-"
51#define IWL_MA_A_MR_A_FW_PRE "iwlwifi-ma-a0-mr-a0-"
52#define IWL_MA_A_FM_A_FW_PRE "iwlwifi-ma-a0-fm-a0-"
53#define IWL_SNJ_A_MR_A_FW_PRE "iwlwifi-SoSnj-a0-mr-a0-"
54#define IWL_BZ_A_HR_B_FW_PRE "iwlwifi-bz-a0-hr-b0-"
55#define IWL_BZ_A_GF_A_FW_PRE "iwlwifi-bz-a0-gf-a0-"
56#define IWL_BZ_A_GF4_A_FW_PRE "iwlwifi-bz-a0-gf4-a0-"
57#define IWL_BZ_A_MR_A_FW_PRE "iwlwifi-bz-a0-mr-a0-"
58#define IWL_BZ_A_FM_A_FW_PRE "iwlwifi-bz-a0-fm-a0-"
59#define IWL_BZ_A_FM4_A_FW_PRE "iwlwifi-bz-a0-fm4-a0-"
60#define IWL_GL_A_FM_A_FW_PRE "iwlwifi-gl-a0-fm-a0-"
61#define IWL_GL_B_FM_B_FW_PRE "iwlwifi-gl-b0-fm-b0-"
62#define IWL_BZ_Z_GF_A_FW_PRE "iwlwifi-bz-z0-gf-a0-"
63#define IWL_BNJ_A_FM_A_FW_PRE "iwlwifi-BzBnj-a0-fm-a0-"
64#define IWL_BNJ_A_FM4_A_FW_PRE "iwlwifi-BzBnj-a0-fm4-a0-"
65#define IWL_BNJ_A_GF_A_FW_PRE "iwlwifi-BzBnj-a0-gf-a0-"
66#define IWL_BNJ_A_GF4_A_FW_PRE "iwlwifi-BzBnj-a0-gf4-a0-"
67#define IWL_BNJ_A_HR_B_FW_PRE "iwlwifi-BzBnj-a0-hr-b0-"
68#define IWL_BNJ_B_FM_B_FW_PRE "iwlwifi-BzBnj-b0-fm-b0-"
69
70
71#define IWL_QU_B_HR_B_MODULE_FIRMWARE(api) \
72 IWL_QU_B_HR_B_FW_PRE __stringify(api) ".ucode"
73#define IWL_QNJ_B_HR_B_MODULE_FIRMWARE(api) \
74 IWL_QNJ_B_HR_B_FW_PRE __stringify(api) ".ucode"
75#define IWL_QUZ_A_HR_B_MODULE_FIRMWARE(api) \
76 IWL_QUZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
77#define IWL_QUZ_A_JF_B_MODULE_FIRMWARE(api) \
78 IWL_QUZ_A_JF_B_FW_PRE __stringify(api) ".ucode"
79#define IWL_QU_C_HR_B_MODULE_FIRMWARE(api) \
80 IWL_QU_C_HR_B_FW_PRE __stringify(api) ".ucode"
81#define IWL_QU_B_JF_B_MODULE_FIRMWARE(api) \
82 IWL_QU_B_JF_B_FW_PRE __stringify(api) ".ucode"
83#define IWL_QNJ_B_JF_B_MODULE_FIRMWARE(api) \
84 IWL_QNJ_B_JF_B_FW_PRE __stringify(api) ".ucode"
85#define IWL_CC_A_MODULE_FIRMWARE(api) \
86 IWL_CC_A_FW_PRE __stringify(api) ".ucode"
87#define IWL_SO_A_JF_B_MODULE_FIRMWARE(api) \
88 IWL_SO_A_JF_B_FW_PRE __stringify(api) ".ucode"
89#define IWL_SO_A_HR_B_MODULE_FIRMWARE(api) \
90 IWL_SO_A_HR_B_FW_PRE __stringify(api) ".ucode"
91#define IWL_SO_A_GF_A_MODULE_FIRMWARE(api) \
92 IWL_SO_A_GF_A_FW_PRE __stringify(api) ".ucode"
93#define IWL_TY_A_GF_A_MODULE_FIRMWARE(api) \
94 IWL_TY_A_GF_A_FW_PRE __stringify(api) ".ucode"
95#define IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(api) \
96 IWL_SNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
97#define IWL_SNJ_A_GF_A_MODULE_FIRMWARE(api) \
98 IWL_SNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
99#define IWL_SNJ_A_HR_B_MODULE_FIRMWARE(api) \
100 IWL_SNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
101#define IWL_SNJ_A_JF_B_MODULE_FIRMWARE(api) \
102 IWL_SNJ_A_JF_B_FW_PRE __stringify(api) ".ucode"
103#define IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(api) \
104 IWL_MA_A_HR_B_FW_PRE __stringify(api) ".ucode"
105#define IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(api) \
106 IWL_MA_A_GF_A_FW_PRE __stringify(api) ".ucode"
107#define IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(api) \
108 IWL_MA_A_GF4_A_FW_PRE __stringify(api) ".ucode"
109#define IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(api) \
110 IWL_MA_A_MR_A_FW_PRE __stringify(api) ".ucode"
111#define IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(api) \
112 IWL_MA_A_FM_A_FW_PRE __stringify(api) ".ucode"
113#define IWL_SNJ_A_MR_A_MODULE_FIRMWARE(api) \
114 IWL_SNJ_A_MR_A_FW_PRE __stringify(api) ".ucode"
115#define IWL_BZ_A_HR_B_MODULE_FIRMWARE(api) \
116 IWL_BZ_A_HR_B_FW_PRE __stringify(api) ".ucode"
117#define IWL_BZ_A_GF_A_MODULE_FIRMWARE(api) \
118 IWL_BZ_A_GF_A_FW_PRE __stringify(api) ".ucode"
119#define IWL_BZ_A_GF4_A_MODULE_FIRMWARE(api) \
120 IWL_BZ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
121#define IWL_BZ_A_MR_A_MODULE_FIRMWARE(api) \
122 IWL_BZ_A_MR_A_FW_PRE __stringify(api) ".ucode"
123#define IWL_BZ_A_FM_A_MODULE_FIRMWARE(api) \
124 IWL_BZ_A_FM_A_FW_PRE __stringify(api) ".ucode"
125#define IWL_BZ_A_FM4_A_MODULE_FIRMWARE(api) \
126 IWL_BZ_A_FM4_A_FW_PRE __stringify(api) ".ucode"
127#define IWL_GL_A_FM_A_MODULE_FIRMWARE(api) \
128 IWL_GL_A_FM_A_FW_PRE __stringify(api) ".ucode"
129#define IWL_GL_B_FM_B_MODULE_FIRMWARE(api) \
130 IWL_GL_B_FM_B_FW_PRE __stringify(api) ".ucode"
131#define IWL_BNJ_A_FM_A_MODULE_FIRMWARE(api) \
132 IWL_BNJ_A_FM_A_FW_PRE __stringify(api) ".ucode"
133#define IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(api) \
134 IWL_BNJ_A_FM4_A_FW_PRE __stringify(api) ".ucode"
135#define IWL_BNJ_A_GF_A_MODULE_FIRMWARE(api) \
136 IWL_BNJ_A_GF_A_FW_PRE __stringify(api) ".ucode"
137#define IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(api) \
138 IWL_BNJ_A_GF4_A_FW_PRE __stringify(api) ".ucode"
139#define IWL_BNJ_A_HR_B_MODULE_FIRMWARE(api) \
140 IWL_BNJ_A_HR_B_FW_PRE __stringify(api) ".ucode"
141#define IWL_BNJ_B_FM_B_MODULE_FIRMWARE(api) \
142 IWL_BNJ_B_FM_B_FW_PRE __stringify(api) ".ucode"
143
144static const struct iwl_base_params iwl_22000_base_params = {
145 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
146 .num_of_queues = 512,
147 .max_tfd_queue_size = 256,
148 .shadow_ram_support = true,
149 .led_compensation = 57,
150 .wd_timeout = IWL_LONG_WD_TIMEOUT,
151 .max_event_log_size = 512,
152 .shadow_reg_enable = true,
153 .pcie_l1_allowed = true,
154};
155
156static const struct iwl_base_params iwl_ax210_base_params = {
157 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K,
158 .num_of_queues = 512,
159 .max_tfd_queue_size = 65536,
160 .shadow_ram_support = true,
161 .led_compensation = 57,
162 .wd_timeout = IWL_LONG_WD_TIMEOUT,
163 .max_event_log_size = 512,
164 .shadow_reg_enable = true,
165 .pcie_l1_allowed = true,
166};
167
168static const struct iwl_ht_params iwl_22000_ht_params = {
169 .stbc = true,
170 .ldpc = true,
171 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
172 BIT(NL80211_BAND_6GHZ),
173};
174
175static const struct iwl_ht_params iwl_gl_a_ht_params = {
176 .stbc = false, /* we explicitly disable STBC for GL step A */
177 .ldpc = true,
178 .ht40_bands = BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ) |
179 BIT(NL80211_BAND_6GHZ),
180};
181
182#define IWL_DEVICE_22000_COMMON \
183 .ucode_api_max = IWL_22000_UCODE_API_MAX, \
184 .ucode_api_min = IWL_22000_UCODE_API_MIN, \
185 .led_mode = IWL_LED_RF_STATE, \
186 .nvm_hw_section_num = 10, \
187 .non_shared_ant = ANT_B, \
188 .dccm_offset = IWL_22000_DCCM_OFFSET, \
189 .dccm_len = IWL_22000_DCCM_LEN, \
190 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \
191 .dccm2_len = IWL_22000_DCCM2_LEN, \
192 .smem_offset = IWL_22000_SMEM_OFFSET, \
193 .smem_len = IWL_22000_SMEM_LEN, \
194 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \
195 .apmg_not_supported = true, \
196 .trans.mq_rx_supported = true, \
197 .vht_mu_mimo_supported = true, \
198 .mac_addr_from_csr = 0x380, \
199 .ht_params = &iwl_22000_ht_params, \
200 .nvm_ver = IWL_22000_NVM_VERSION, \
201 .trans.use_tfh = true, \
202 .trans.rf_id = true, \
203 .trans.gen2 = true, \
204 .nvm_type = IWL_NVM_EXT, \
205 .dbgc_supported = true, \
206 .min_umac_error_event_table = 0x400000, \
207 .d3_debug_data_base_addr = 0x401000, \
208 .d3_debug_data_length = 60 * 1024, \
209 .mon_smem_regs = { \
210 .write_ptr = { \
211 .addr = LDBG_M2S_BUF_WPTR, \
212 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \
213 }, \
214 .cycle_cnt = { \
215 .addr = LDBG_M2S_BUF_WRAP_CNT, \
216 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \
217 }, \
218 }
219
220#define IWL_DEVICE_22500 \
221 IWL_DEVICE_22000_COMMON, \
222 .trans.device_family = IWL_DEVICE_FAMILY_22000, \
223 .trans.base_params = &iwl_22000_base_params, \
224 .gp2_reg_addr = 0xa02c68, \
225 .mon_dram_regs = { \
226 .write_ptr = { \
227 .addr = MON_BUFF_WRPTR_VER2, \
228 .mask = 0xffffffff, \
229 }, \
230 .cycle_cnt = { \
231 .addr = MON_BUFF_CYCLE_CNT_VER2, \
232 .mask = 0xffffffff, \
233 }, \
234 }
235
236#define IWL_DEVICE_AX210 \
237 IWL_DEVICE_22000_COMMON, \
238 .trans.umac_prph_offset = 0x300000, \
239 .trans.device_family = IWL_DEVICE_FAMILY_AX210, \
240 .trans.base_params = &iwl_ax210_base_params, \
241 .min_txq_size = 128, \
242 .gp2_reg_addr = 0xd02c68, \
243 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE, \
244 .mon_dram_regs = { \
245 .write_ptr = { \
246 .addr = DBGC_CUR_DBGBUF_STATUS, \
247 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \
248 }, \
249 .cycle_cnt = { \
250 .addr = DBGC_DBGBUF_WRAP_AROUND, \
251 .mask = 0xffffffff, \
252 }, \
253 .cur_frag = { \
254 .addr = DBGC_CUR_DBGBUF_STATUS, \
255 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \
256 }, \
257 }
258
259#define IWL_DEVICE_BZ_COMMON \
260 .ucode_api_max = IWL_22000_UCODE_API_MAX, \
261 .ucode_api_min = IWL_22000_UCODE_API_MIN, \
262 .led_mode = IWL_LED_RF_STATE, \
263 .nvm_hw_section_num = 10, \
264 .non_shared_ant = ANT_B, \
265 .dccm_offset = IWL_22000_DCCM_OFFSET, \
266 .dccm_len = IWL_22000_DCCM_LEN, \
267 .dccm2_offset = IWL_22000_DCCM2_OFFSET, \
268 .dccm2_len = IWL_22000_DCCM2_LEN, \
269 .smem_offset = IWL_22000_SMEM_OFFSET, \
270 .smem_len = IWL_22000_SMEM_LEN, \
271 .apmg_not_supported = true, \
272 .trans.mq_rx_supported = true, \
273 .vht_mu_mimo_supported = true, \
274 .mac_addr_from_csr = 0x30, \
275 .nvm_ver = IWL_22000_NVM_VERSION, \
276 .trans.use_tfh = true, \
277 .trans.rf_id = true, \
278 .trans.gen2 = true, \
279 .nvm_type = IWL_NVM_EXT, \
280 .dbgc_supported = true, \
281 .min_umac_error_event_table = 0x400000, \
282 .d3_debug_data_base_addr = 0x401000, \
283 .d3_debug_data_length = 60 * 1024, \
284 .mon_smem_regs = { \
285 .write_ptr = { \
286 .addr = LDBG_M2S_BUF_WPTR, \
287 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \
288 }, \
289 .cycle_cnt = { \
290 .addr = LDBG_M2S_BUF_WRAP_CNT, \
291 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \
292 }, \
293 }, \
294 .trans.umac_prph_offset = 0x300000, \
295 .trans.device_family = IWL_DEVICE_FAMILY_BZ, \
296 .trans.base_params = &iwl_ax210_base_params, \
297 .min_txq_size = 128, \
298 .gp2_reg_addr = 0xd02c68, \
299 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \
300 .mon_dram_regs = { \
301 .write_ptr = { \
302 .addr = DBGC_CUR_DBGBUF_STATUS, \
303 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \
304 }, \
305 .cycle_cnt = { \
306 .addr = DBGC_DBGBUF_WRAP_AROUND, \
307 .mask = 0xffffffff, \
308 }, \
309 .cur_frag = { \
310 .addr = DBGC_CUR_DBGBUF_STATUS, \
311 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \
312 }, \
313 }, \
314 .mon_dbgi_regs = { \
315 .write_ptr = { \
316 .addr = DBGI_SRAM_FIFO_POINTERS, \
317 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \
318 }, \
319 }
320
321#define IWL_DEVICE_BZ \
322 IWL_DEVICE_BZ_COMMON, \
323 .ht_params = &iwl_22000_ht_params
324
325#define IWL_DEVICE_GL_A \
326 IWL_DEVICE_BZ_COMMON, \
327 .ht_params = &iwl_gl_a_ht_params
328
329const struct iwl_cfg_trans_params iwl_qnj_trans_cfg = {
330 .mq_rx_supported = true,
331 .use_tfh = true,
332 .rf_id = true,
333 .gen2 = true,
334 .device_family = IWL_DEVICE_FAMILY_22000,
335 .base_params = &iwl_22000_base_params,
336};
337
338const struct iwl_cfg_trans_params iwl_qu_trans_cfg = {
339 .mq_rx_supported = true,
340 .use_tfh = true,
341 .rf_id = true,
342 .gen2 = true,
343 .device_family = IWL_DEVICE_FAMILY_22000,
344 .base_params = &iwl_22000_base_params,
345 .integrated = true,
346 .xtal_latency = 500,
347 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
348};
349
350const struct iwl_cfg_trans_params iwl_qu_medium_latency_trans_cfg = {
351 .mq_rx_supported = true,
352 .use_tfh = true,
353 .rf_id = true,
354 .gen2 = true,
355 .device_family = IWL_DEVICE_FAMILY_22000,
356 .base_params = &iwl_22000_base_params,
357 .integrated = true,
358 .xtal_latency = 1820,
359 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_1820US,
360};
361
362const struct iwl_cfg_trans_params iwl_qu_long_latency_trans_cfg = {
363 .mq_rx_supported = true,
364 .use_tfh = true,
365 .rf_id = true,
366 .gen2 = true,
367 .device_family = IWL_DEVICE_FAMILY_22000,
368 .base_params = &iwl_22000_base_params,
369 .integrated = true,
370 .xtal_latency = 12000,
371 .low_latency_xtal = true,
372 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
373};
374
375const struct iwl_cfg_trans_params iwl_snj_trans_cfg = {
376 .mq_rx_supported = true,
377 .use_tfh = true,
378 .rf_id = true,
379 .gen2 = true,
380 .device_family = IWL_DEVICE_FAMILY_AX210,
381 .base_params = &iwl_ax210_base_params,
382 .umac_prph_offset = 0x300000,
383};
384
385const struct iwl_cfg_trans_params iwl_so_trans_cfg = {
386 .mq_rx_supported = true,
387 .use_tfh = true,
388 .rf_id = true,
389 .gen2 = true,
390 .device_family = IWL_DEVICE_FAMILY_AX210,
391 .base_params = &iwl_ax210_base_params,
392 .umac_prph_offset = 0x300000,
393 .integrated = true,
394 /* TODO: the following values need to be checked */
395 .xtal_latency = 500,
396 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
397};
398
399const struct iwl_cfg_trans_params iwl_so_long_latency_trans_cfg = {
400 .mq_rx_supported = true,
401 .use_tfh = true,
402 .rf_id = true,
403 .gen2 = true,
404 .device_family = IWL_DEVICE_FAMILY_AX210,
405 .base_params = &iwl_ax210_base_params,
406 .umac_prph_offset = 0x300000,
407 .integrated = true,
408 .low_latency_xtal = true,
409 .xtal_latency = 12000,
410 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
411};
412
413const struct iwl_cfg_trans_params iwl_so_long_latency_imr_trans_cfg = {
414 .mq_rx_supported = true,
415 .use_tfh = true,
416 .rf_id = true,
417 .gen2 = true,
418 .device_family = IWL_DEVICE_FAMILY_AX210,
419 .base_params = &iwl_ax210_base_params,
420 .umac_prph_offset = 0x300000,
421 .integrated = true,
422 .low_latency_xtal = true,
423 .xtal_latency = 12000,
424 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
425 .imr_enabled = true,
426};
427
428/*
429 * If the device doesn't support HE, no need to have that many buffers.
430 * 22000 devices can split multiple frames into a single RB, so fewer are
431 * needed; AX210 cannot (but use smaller RBs by default) - these sizes
432 * were picked according to 8 MSDUs inside 256 A-MSDUs in an A-MPDU, with
433 * additional overhead to account for processing time.
434 */
435#define IWL_NUM_RBDS_NON_HE 512
436#define IWL_NUM_RBDS_22000_HE 2048
437#define IWL_NUM_RBDS_AX210_HE 4096
438
439/*
440 * All JF radio modules are part of the 9000 series, but the MAC part
441 * looks more like 22000. That's why this device is here, but called
442 * 9560 nevertheless.
443 */
444const struct iwl_cfg iwl9560_qu_b0_jf_b0_cfg = {
445 .fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
446 IWL_DEVICE_22500,
447 .num_rbds = IWL_NUM_RBDS_NON_HE,
448};
449
450const struct iwl_cfg iwl9560_qu_c0_jf_b0_cfg = {
451 .fw_name_pre = IWL_QU_C_JF_B_FW_PRE,
452 IWL_DEVICE_22500,
453 .num_rbds = IWL_NUM_RBDS_NON_HE,
454};
455
456const struct iwl_cfg iwl9560_quz_a0_jf_b0_cfg = {
457 .fw_name_pre = IWL_QUZ_A_JF_B_FW_PRE,
458 IWL_DEVICE_22500,
459 /*
460 * This device doesn't support receiving BlockAck with a large bitmap
461 * so we need to restrict the size of transmitted aggregation to the
462 * HT size; mac80211 would otherwise pick the HE max (256) by default.
463 */
464 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
465 .num_rbds = IWL_NUM_RBDS_NON_HE,
466};
467
468const struct iwl_cfg iwl9560_qnj_b0_jf_b0_cfg = {
469 .fw_name_pre = IWL_QNJ_B_JF_B_FW_PRE,
470 IWL_DEVICE_22500,
471 /*
472 * This device doesn't support receiving BlockAck with a large bitmap
473 * so we need to restrict the size of transmitted aggregation to the
474 * HT size; mac80211 would otherwise pick the HE max (256) by default.
475 */
476 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
477 .num_rbds = IWL_NUM_RBDS_NON_HE,
478};
479
480const struct iwl_cfg_trans_params iwl_ax200_trans_cfg = {
481 .device_family = IWL_DEVICE_FAMILY_22000,
482 .base_params = &iwl_22000_base_params,
483 .mq_rx_supported = true,
484 .use_tfh = true,
485 .rf_id = true,
486 .gen2 = true,
487 .bisr_workaround = 1,
488};
489
490const struct iwl_cfg_trans_params iwl_ma_trans_cfg = {
491 .device_family = IWL_DEVICE_FAMILY_AX210,
492 .base_params = &iwl_ax210_base_params,
493 .mq_rx_supported = true,
494 .use_tfh = true,
495 .rf_id = true,
496 .gen2 = true,
497 .integrated = true,
498 .umac_prph_offset = 0x300000
499};
500
501const struct iwl_cfg_trans_params iwl_bz_trans_cfg = {
502 .device_family = IWL_DEVICE_FAMILY_BZ,
503 .base_params = &iwl_ax210_base_params,
504 .mq_rx_supported = true,
505 .use_tfh = true,
506 .rf_id = true,
507 .gen2 = true,
508 .integrated = true,
509 .umac_prph_offset = 0x300000,
510 .xtal_latency = 12000,
511 .low_latency_xtal = true,
512 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
513};
514
515const char iwl_ax101_name[] = "Intel(R) Wi-Fi 6 AX101";
516const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz";
517const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
518const char iwl_ax203_name[] = "Intel(R) Wi-Fi 6 AX203";
519const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz";
520const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz";
521const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz";
522const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz";
523const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz";
524const char iwl_bz_name[] = "Intel(R) TBD Bz device";
525
526const char iwl_ax200_killer_1650w_name[] =
527 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)";
528const char iwl_ax200_killer_1650x_name[] =
529 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)";
530const char iwl_ax201_killer_1650s_name[] =
531 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)";
532const char iwl_ax201_killer_1650i_name[] =
533 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)";
534const char iwl_ax210_killer_1675w_name[] =
535 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)";
536const char iwl_ax210_killer_1675x_name[] =
537 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)";
538const char iwl_ax211_killer_1675s_name[] =
539 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)";
540const char iwl_ax211_killer_1675i_name[] =
541 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)";
542const char iwl_ax411_killer_1690s_name[] =
543 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireless Network Adapter (411D2W)";
544const char iwl_ax411_killer_1690i_name[] =
545 "Killer(R) Wi-Fi 6E AX1690i 160MHz Wireless Network Adapter (411NGW)";
546
547const struct iwl_cfg iwl_qu_b0_hr1_b0 = {
548 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
549 IWL_DEVICE_22500,
550 /*
551 * This device doesn't support receiving BlockAck with a large bitmap
552 * so we need to restrict the size of transmitted aggregation to the
553 * HT size; mac80211 would otherwise pick the HE max (256) by default.
554 */
555 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
556 .tx_with_siso_diversity = true,
557 .num_rbds = IWL_NUM_RBDS_22000_HE,
558};
559
560const struct iwl_cfg iwl_qu_b0_hr_b0 = {
561 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
562 IWL_DEVICE_22500,
563 /*
564 * This device doesn't support receiving BlockAck with a large bitmap
565 * so we need to restrict the size of transmitted aggregation to the
566 * HT size; mac80211 would otherwise pick the HE max (256) by default.
567 */
568 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
569 .num_rbds = IWL_NUM_RBDS_22000_HE,
570};
571
572const struct iwl_cfg iwl_ax201_cfg_qu_hr = {
573 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
574 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
575 IWL_DEVICE_22500,
576 /*
577 * This device doesn't support receiving BlockAck with a large bitmap
578 * so we need to restrict the size of transmitted aggregation to the
579 * HT size; mac80211 would otherwise pick the HE max (256) by default.
580 */
581 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
582 .num_rbds = IWL_NUM_RBDS_22000_HE,
583};
584
585const struct iwl_cfg iwl_qu_c0_hr1_b0 = {
586 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
587 IWL_DEVICE_22500,
588 /*
589 * This device doesn't support receiving BlockAck with a large bitmap
590 * so we need to restrict the size of transmitted aggregation to the
591 * HT size; mac80211 would otherwise pick the HE max (256) by default.
592 */
593 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
594 .tx_with_siso_diversity = true,
595 .num_rbds = IWL_NUM_RBDS_22000_HE,
596};
597
598const struct iwl_cfg iwl_qu_c0_hr_b0 = {
599 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
600 IWL_DEVICE_22500,
601 /*
602 * This device doesn't support receiving BlockAck with a large bitmap
603 * so we need to restrict the size of transmitted aggregation to the
604 * HT size; mac80211 would otherwise pick the HE max (256) by default.
605 */
606 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
607 .num_rbds = IWL_NUM_RBDS_22000_HE,
608};
609
610const struct iwl_cfg iwl_ax201_cfg_qu_c0_hr_b0 = {
611 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
612 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
613 IWL_DEVICE_22500,
614 /*
615 * This device doesn't support receiving BlockAck with a large bitmap
616 * so we need to restrict the size of transmitted aggregation to the
617 * HT size; mac80211 would otherwise pick the HE max (256) by default.
618 */
619 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
620 .num_rbds = IWL_NUM_RBDS_22000_HE,
621};
622
623const struct iwl_cfg iwl_quz_a0_hr1_b0 = {
624 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
625 IWL_DEVICE_22500,
626 /*
627 * This device doesn't support receiving BlockAck with a large bitmap
628 * so we need to restrict the size of transmitted aggregation to the
629 * HT size; mac80211 would otherwise pick the HE max (256) by default.
630 */
631 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
632 .tx_with_siso_diversity = true,
633 .num_rbds = IWL_NUM_RBDS_22000_HE,
634};
635
636const struct iwl_cfg iwl_ax201_cfg_quz_hr = {
637 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
638 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
639 IWL_DEVICE_22500,
640 /*
641 * This device doesn't support receiving BlockAck with a large bitmap
642 * so we need to restrict the size of transmitted aggregation to the
643 * HT size; mac80211 would otherwise pick the HE max (256) by default.
644 */
645 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
646 .num_rbds = IWL_NUM_RBDS_22000_HE,
647};
648
649const struct iwl_cfg iwl_ax1650s_cfg_quz_hr = {
650 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
651 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
652 IWL_DEVICE_22500,
653 /*
654 * This device doesn't support receiving BlockAck with a large bitmap
655 * so we need to restrict the size of transmitted aggregation to the
656 * HT size; mac80211 would otherwise pick the HE max (256) by default.
657 */
658 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
659 .num_rbds = IWL_NUM_RBDS_22000_HE,
660};
661
662const struct iwl_cfg iwl_ax1650i_cfg_quz_hr = {
663 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
664 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
665 IWL_DEVICE_22500,
666 /*
667 * This device doesn't support receiving BlockAck with a large bitmap
668 * so we need to restrict the size of transmitted aggregation to the
669 * HT size; mac80211 would otherwise pick the HE max (256) by default.
670 */
671 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
672 .num_rbds = IWL_NUM_RBDS_22000_HE,
673};
674
675const struct iwl_cfg iwl_ax200_cfg_cc = {
676 .fw_name_pre = IWL_CC_A_FW_PRE,
677 IWL_DEVICE_22500,
678 /*
679 * This device doesn't support receiving BlockAck with a large bitmap
680 * so we need to restrict the size of transmitted aggregation to the
681 * HT size; mac80211 would otherwise pick the HE max (256) by default.
682 */
683 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
684 .num_rbds = IWL_NUM_RBDS_22000_HE,
685};
686
687const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0 = {
688 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
689 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
690 IWL_DEVICE_22500,
691 /*
692 * This device doesn't support receiving BlockAck with a large bitmap
693 * so we need to restrict the size of transmitted aggregation to the
694 * HT size; mac80211 would otherwise pick the HE max (256) by default.
695 */
696 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
697 .num_rbds = IWL_NUM_RBDS_22000_HE,
698};
699
700const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = {
701 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
702 .fw_name_pre = IWL_QU_B_HR_B_FW_PRE,
703 IWL_DEVICE_22500,
704 /*
705 * This device doesn't support receiving BlockAck with a large bitmap
706 * so we need to restrict the size of transmitted aggregation to the
707 * HT size; mac80211 would otherwise pick the HE max (256) by default.
708 */
709 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
710 .num_rbds = IWL_NUM_RBDS_22000_HE,
711};
712
713const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = {
714 .name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201NGW)",
715 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
716 IWL_DEVICE_22500,
717 /*
718 * This device doesn't support receiving BlockAck with a large bitmap
719 * so we need to restrict the size of transmitted aggregation to the
720 * HT size; mac80211 would otherwise pick the HE max (256) by default.
721 */
722 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
723 .num_rbds = IWL_NUM_RBDS_22000_HE,
724};
725
726const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = {
727 .name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201D2W)",
728 .fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
729 IWL_DEVICE_22500,
730 /*
731 * This device doesn't support receiving BlockAck with a large bitmap
732 * so we need to restrict the size of transmitted aggregation to the
733 * HT size; mac80211 would otherwise pick the HE max (256) by default.
734 */
735 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
736 .num_rbds = IWL_NUM_RBDS_22000_HE,
737};
738
739const struct iwl_cfg iwl_qnj_b0_hr_b0_cfg = {
740 .fw_name_pre = IWL_QNJ_B_HR_B_FW_PRE,
741 IWL_DEVICE_22500,
742 /*
743 * This device doesn't support receiving BlockAck with a large bitmap
744 * so we need to restrict the size of transmitted aggregation to the
745 * HT size; mac80211 would otherwise pick the HE max (256) by default.
746 */
747 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
748 .num_rbds = IWL_NUM_RBDS_22000_HE,
749};
750
751const struct iwl_cfg iwlax210_2ax_cfg_so_jf_b0 = {
752 .name = "Intel(R) Wireless-AC 9560 160MHz",
753 .fw_name_pre = IWL_SO_A_JF_B_FW_PRE,
754 IWL_DEVICE_AX210,
755 .num_rbds = IWL_NUM_RBDS_NON_HE,
756};
757
758const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0 = {
759 .name = iwl_ax211_name,
760 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
761 .uhb_supported = true,
762 IWL_DEVICE_AX210,
763 .num_rbds = IWL_NUM_RBDS_AX210_HE,
764};
765
766const struct iwl_cfg iwlax211_2ax_cfg_so_gf_a0_long = {
767 .name = iwl_ax211_name,
768 .fw_name_pre = IWL_SO_A_GF_A_FW_PRE,
769 .uhb_supported = true,
770 IWL_DEVICE_AX210,
771 .num_rbds = IWL_NUM_RBDS_AX210_HE,
772 .trans.xtal_latency = 12000,
773 .trans.low_latency_xtal = true,
774};
775
776const struct iwl_cfg iwlax210_2ax_cfg_ty_gf_a0 = {
777 .name = "Intel(R) Wi-Fi 6 AX210 160MHz",
778 .fw_name_pre = IWL_TY_A_GF_A_FW_PRE,
779 .uhb_supported = true,
780 IWL_DEVICE_AX210,
781 .num_rbds = IWL_NUM_RBDS_AX210_HE,
782};
783
784const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0 = {
785 .name = iwl_ax411_name,
786 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
787 .uhb_supported = true,
788 IWL_DEVICE_AX210,
789 .num_rbds = IWL_NUM_RBDS_AX210_HE,
790};
791
792const struct iwl_cfg iwlax411_2ax_cfg_so_gf4_a0_long = {
793 .name = iwl_ax411_name,
794 .fw_name_pre = IWL_SO_A_GF4_A_FW_PRE,
795 .uhb_supported = true,
796 IWL_DEVICE_AX210,
797 .num_rbds = IWL_NUM_RBDS_AX210_HE,
798 .trans.xtal_latency = 12000,
799 .trans.low_latency_xtal = true,
800};
801
802const struct iwl_cfg iwlax411_2ax_cfg_sosnj_gf4_a0 = {
803 .name = iwl_ax411_name,
804 .fw_name_pre = IWL_SNJ_A_GF4_A_FW_PRE,
805 .uhb_supported = true,
806 IWL_DEVICE_AX210,
807 .num_rbds = IWL_NUM_RBDS_AX210_HE,
808};
809
810const struct iwl_cfg iwlax211_cfg_snj_gf_a0 = {
811 .name = iwl_ax211_name,
812 .fw_name_pre = IWL_SNJ_A_GF_A_FW_PRE,
813 .uhb_supported = true,
814 IWL_DEVICE_AX210,
815 .num_rbds = IWL_NUM_RBDS_AX210_HE,
816};
817
818const struct iwl_cfg iwl_cfg_snj_hr_b0 = {
819 .fw_name_pre = IWL_SNJ_A_HR_B_FW_PRE,
820 .uhb_supported = true,
821 IWL_DEVICE_AX210,
822 .num_rbds = IWL_NUM_RBDS_AX210_HE,
823};
824
825const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = {
826 .fw_name_pre = IWL_SNJ_A_JF_B_FW_PRE,
827 .uhb_supported = true,
828 IWL_DEVICE_AX210,
829 .num_rbds = IWL_NUM_RBDS_AX210_HE,
830};
831
832const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = {
833 .fw_name_pre = IWL_MA_A_HR_B_FW_PRE,
834 .uhb_supported = true,
835 IWL_DEVICE_AX210,
836 .num_rbds = IWL_NUM_RBDS_AX210_HE,
837};
838
839const struct iwl_cfg iwl_cfg_ma_a0_gf_a0 = {
840 .fw_name_pre = IWL_MA_A_GF_A_FW_PRE,
841 .uhb_supported = true,
842 IWL_DEVICE_AX210,
843 .num_rbds = IWL_NUM_RBDS_AX210_HE,
844};
845
846const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = {
847 .fw_name_pre = IWL_MA_A_GF4_A_FW_PRE,
848 .uhb_supported = true,
849 IWL_DEVICE_AX210,
850 .num_rbds = IWL_NUM_RBDS_AX210_HE,
851};
852
853const struct iwl_cfg iwl_cfg_ma_a0_mr_a0 = {
854 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
855 .uhb_supported = true,
856 IWL_DEVICE_AX210,
857 .num_rbds = IWL_NUM_RBDS_AX210_HE,
858};
859
860const struct iwl_cfg iwl_cfg_ma_a0_ms_a0 = {
861 .fw_name_pre = IWL_MA_A_MR_A_FW_PRE,
862 .uhb_supported = false,
863 IWL_DEVICE_AX210,
864 .num_rbds = IWL_NUM_RBDS_AX210_HE,
865};
866
867const struct iwl_cfg iwl_cfg_so_a0_ms_a0 = {
868 .fw_name_pre = IWL_SO_A_MR_A_FW_PRE,
869 .uhb_supported = false,
870 IWL_DEVICE_AX210,
871 .num_rbds = IWL_NUM_RBDS_AX210_HE,
872};
873
874const struct iwl_cfg iwl_cfg_ma_a0_fm_a0 = {
875 .fw_name_pre = IWL_MA_A_FM_A_FW_PRE,
876 .uhb_supported = true,
877 IWL_DEVICE_AX210,
878 .num_rbds = IWL_NUM_RBDS_AX210_HE,
879};
880
881const struct iwl_cfg iwl_cfg_snj_a0_mr_a0 = {
882 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
883 .uhb_supported = true,
884 IWL_DEVICE_AX210,
885 .num_rbds = IWL_NUM_RBDS_AX210_HE,
886};
887
888const struct iwl_cfg iwl_cfg_snj_a0_ms_a0 = {
889 .fw_name_pre = IWL_SNJ_A_MR_A_FW_PRE,
890 .uhb_supported = false,
891 IWL_DEVICE_AX210,
892 .num_rbds = IWL_NUM_RBDS_AX210_HE,
893};
894
895const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = {
896 .fw_name_pre = IWL_SO_A_HR_B_FW_PRE,
897 IWL_DEVICE_AX210,
898 .num_rbds = IWL_NUM_RBDS_AX210_HE,
899};
900
901const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = {
902 .fw_name_pre = IWL_QUZ_A_HR_B_FW_PRE,
903 IWL_DEVICE_22500,
904 /*
905 * This device doesn't support receiving BlockAck with a large bitmap
906 * so we need to restrict the size of transmitted aggregation to the
907 * HT size; mac80211 would otherwise pick the HE max (256) by default.
908 */
909 .max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
910 .num_rbds = IWL_NUM_RBDS_22000_HE,
911};
912
913const struct iwl_cfg iwl_cfg_bz_a0_hr_b0 = {
914 .fw_name_pre = IWL_BZ_A_HR_B_FW_PRE,
915 .uhb_supported = true,
916 IWL_DEVICE_BZ,
917 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
918 .num_rbds = IWL_NUM_RBDS_AX210_HE,
919};
920
921const struct iwl_cfg iwl_cfg_bz_a0_gf_a0 = {
922 .fw_name_pre = IWL_BZ_A_GF_A_FW_PRE,
923 .uhb_supported = true,
924 IWL_DEVICE_BZ,
925 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
926 .num_rbds = IWL_NUM_RBDS_AX210_HE,
927};
928
929const struct iwl_cfg iwl_cfg_bz_a0_gf4_a0 = {
930 .fw_name_pre = IWL_BZ_A_GF4_A_FW_PRE,
931 .uhb_supported = true,
932 IWL_DEVICE_BZ,
933 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
934 .num_rbds = IWL_NUM_RBDS_AX210_HE,
935};
936
937const struct iwl_cfg iwl_cfg_bz_a0_mr_a0 = {
938 .fw_name_pre = IWL_BZ_A_MR_A_FW_PRE,
939 .uhb_supported = true,
940 IWL_DEVICE_BZ,
941 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
942 .num_rbds = IWL_NUM_RBDS_AX210_HE,
943};
944
945const struct iwl_cfg iwl_cfg_bz_a0_fm_a0 = {
946 .fw_name_pre = IWL_BZ_A_FM_A_FW_PRE,
947 .uhb_supported = true,
948 IWL_DEVICE_BZ,
949 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
950 .num_rbds = IWL_NUM_RBDS_AX210_HE,
951};
952
953const struct iwl_cfg iwl_cfg_bz_a0_fm4_a0 = {
954 .fw_name_pre = IWL_BZ_A_FM4_A_FW_PRE,
955 .uhb_supported = true,
956 IWL_DEVICE_BZ,
957 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
958 .num_rbds = IWL_NUM_RBDS_AX210_HE,
959};
960
961const struct iwl_cfg iwl_cfg_gl_a0_fm_a0 = {
962 .fw_name_pre = IWL_GL_A_FM_A_FW_PRE,
963 .uhb_supported = true,
964 IWL_DEVICE_GL_A,
965 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
966 .num_rbds = IWL_NUM_RBDS_AX210_HE,
967};
968
969const struct iwl_cfg iwl_cfg_gl_b0_fm_b0 = {
970 .fw_name_pre = IWL_GL_B_FM_B_FW_PRE,
971 .uhb_supported = true,
972 IWL_DEVICE_BZ,
973 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
974 .num_rbds = IWL_NUM_RBDS_AX210_HE,
975};
976
977const struct iwl_cfg iwl_cfg_bz_z0_gf_a0 = {
978 .fw_name_pre = IWL_BZ_Z_GF_A_FW_PRE,
979 .uhb_supported = true,
980 IWL_DEVICE_BZ,
981 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
982 .num_rbds = IWL_NUM_RBDS_AX210_HE,
983};
984
985const struct iwl_cfg iwl_cfg_bnj_a0_fm_a0 = {
986 .fw_name_pre = IWL_BNJ_A_FM_A_FW_PRE,
987 .uhb_supported = true,
988 IWL_DEVICE_BZ,
989 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
990 .num_rbds = IWL_NUM_RBDS_AX210_HE,
991};
992
993const struct iwl_cfg iwl_cfg_bnj_a0_fm4_a0 = {
994 .fw_name_pre = IWL_BNJ_A_FM4_A_FW_PRE,
995 .uhb_supported = true,
996 IWL_DEVICE_BZ,
997 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
998 .num_rbds = IWL_NUM_RBDS_AX210_HE,
999};
1000
1001const struct iwl_cfg iwl_cfg_bnj_a0_gf_a0 = {
1002 .fw_name_pre = IWL_BNJ_A_GF_A_FW_PRE,
1003 .uhb_supported = true,
1004 IWL_DEVICE_BZ,
1005 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1006 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1007};
1008
1009const struct iwl_cfg iwl_cfg_bnj_a0_gf4_a0 = {
1010 .fw_name_pre = IWL_BNJ_A_GF4_A_FW_PRE,
1011 .uhb_supported = true,
1012 IWL_DEVICE_BZ,
1013 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1014 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1015};
1016
1017const struct iwl_cfg iwl_cfg_bnj_a0_hr_b0 = {
1018 .fw_name_pre = IWL_BNJ_A_HR_B_FW_PRE,
1019 .uhb_supported = true,
1020 IWL_DEVICE_BZ,
1021 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
1022 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1023};
1024
1025const struct iwl_cfg iwl_cfg_bnj_b0_fm_b0 = {
1026 .fw_name_pre = IWL_BNJ_B_FM_B_FW_PRE,
1027 .uhb_supported = true,
1028 IWL_DEVICE_BZ,
1029 .features = IWL_TX_CSUM_NETIF_FLAGS_BZ | NETIF_F_RXCSUM,
1030 .num_rbds = IWL_NUM_RBDS_AX210_HE,
1031};
1032MODULE_FIRMWARE(IWL_QU_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1033MODULE_FIRMWARE(IWL_QNJ_B_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1034MODULE_FIRMWARE(IWL_QU_C_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1035MODULE_FIRMWARE(IWL_QU_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1036MODULE_FIRMWARE(IWL_QUZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1037MODULE_FIRMWARE(IWL_QUZ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1038MODULE_FIRMWARE(IWL_QNJ_B_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1039MODULE_FIRMWARE(IWL_CC_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1040MODULE_FIRMWARE(IWL_SO_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1041MODULE_FIRMWARE(IWL_SO_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1042MODULE_FIRMWARE(IWL_SO_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1043MODULE_FIRMWARE(IWL_TY_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1044MODULE_FIRMWARE(IWL_SNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1045MODULE_FIRMWARE(IWL_SNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1046MODULE_FIRMWARE(IWL_SNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1047MODULE_FIRMWARE(IWL_SNJ_A_JF_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1048MODULE_FIRMWARE(IWL_MA_A_HR_B_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1049MODULE_FIRMWARE(IWL_MA_A_GF_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1050MODULE_FIRMWARE(IWL_MA_A_GF4_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1051MODULE_FIRMWARE(IWL_MA_A_MR_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1052MODULE_FIRMWARE(IWL_MA_A_FM_A_FW_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1053MODULE_FIRMWARE(IWL_SNJ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1054MODULE_FIRMWARE(IWL_BZ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1055MODULE_FIRMWARE(IWL_BZ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1056MODULE_FIRMWARE(IWL_BZ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1057MODULE_FIRMWARE(IWL_BZ_A_MR_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1058MODULE_FIRMWARE(IWL_BZ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1059MODULE_FIRMWARE(IWL_GL_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1060MODULE_FIRMWARE(IWL_BNJ_A_FM_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1061MODULE_FIRMWARE(IWL_BNJ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1062MODULE_FIRMWARE(IWL_BNJ_A_GF_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1063MODULE_FIRMWARE(IWL_BNJ_A_GF4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1064MODULE_FIRMWARE(IWL_BNJ_A_HR_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1065MODULE_FIRMWARE(IWL_BZ_A_FM4_A_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1066MODULE_FIRMWARE(IWL_GL_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));
1067MODULE_FIRMWARE(IWL_BNJ_B_FM_B_MODULE_FIRMWARE(IWL_22000_UCODE_API_MAX));