1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2# Copyright (C) 2022-2023 Renesas Electronics Corp.
  3%YAML 1.2
  4---
  5$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: Renesas R-Car Gen4 PCIe Endpoint
  9
 10maintainers:
 11  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
 12
 13allOf:
 14  - $ref: snps,dw-pcie-ep.yaml#
 15
 16properties:
 17  compatible:
 18    items:
 19      - const: renesas,r8a779f0-pcie-ep   # R-Car S4-8
 20      - const: renesas,rcar-gen4-pcie-ep  # R-Car Gen4
 21
 22  reg:
 23    maxItems: 7
 24
 25  reg-names:
 26    items:
 27      - const: dbi
 28      - const: dbi2
 29      - const: atu
 30      - const: dma
 31      - const: app
 32      - const: phy
 33      - const: addr_space
 34
 35  interrupts:
 36    maxItems: 3
 37
 38  interrupt-names:
 39    items:
 40      - const: dma
 41      - const: sft_ce
 42      - const: app
 43
 44  clocks:
 45    maxItems: 2
 46
 47  clock-names:
 48    items:
 49      - const: core
 50      - const: ref
 51
 52  power-domains:
 53    maxItems: 1
 54
 55  resets:
 56    maxItems: 1
 57
 58  reset-names:
 59    items:
 60      - const: pwr
 61
 62  max-link-speed:
 63    maximum: 4
 64
 65  num-lanes:
 66    maximum: 4
 67
 68  max-functions:
 69    maximum: 2
 70
 71required:
 72  - compatible
 73  - reg
 74  - reg-names
 75  - interrupts
 76  - interrupt-names
 77  - clocks
 78  - clock-names
 79  - power-domains
 80  - resets
 81  - reset-names
 82
 83unevaluatedProperties: false
 84
 85examples:
 86  - |
 87    #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
 88    #include <dt-bindings/interrupt-controller/arm-gic.h>
 89    #include <dt-bindings/power/r8a779f0-sysc.h>
 90
 91    soc {
 92        #address-cells = <2>;
 93        #size-cells = <2>;
 94
 95        pcie0_ep: pcie-ep@e65d0000 {
 96            compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";
 97            reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
 98                  <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
 99                  <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
100                  <0 0xfe000000 0 0x400000>;
101            reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
102            interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
103                         <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
104                         <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
105            interrupt-names = "dma", "sft_ce", "app";
106            clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
107            clock-names = "core", "ref";
108            power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
109            resets = <&cpg 624>;
110            reset-names = "pwr";
111            max-link-speed = <4>;
112            num-lanes = <2>;
113            max-functions = /bits/ 8 <2>;
114        };
115    };