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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#ifndef __RTW8822C_H__
6#define __RTW8822C_H__
7
8#include <asm/byteorder.h>
9
10struct rtw8822cu_efuse {
11 u8 res0[0x30]; /* 0x120 */
12 u8 vid[2]; /* 0x150 */
13 u8 pid[2];
14 u8 res1[3];
15 u8 mac_addr[ETH_ALEN]; /* 0x157 */
16 u8 res2[0x3d];
17};
18
19struct rtw8822cs_efuse {
20 u8 res0[0x4a]; /* 0x120 */
21 u8 mac_addr[ETH_ALEN]; /* 0x16a */
22} __packed;
23
24struct rtw8822ce_efuse {
25 u8 mac_addr[ETH_ALEN]; /* 0x120 */
26 u8 vender_id[2];
27 u8 device_id[2];
28 u8 sub_vender_id[2];
29 u8 sub_device_id[2];
30 u8 pmc[2];
31 u8 exp_device_cap[2];
32 u8 msi_cap;
33 u8 ltr_cap; /* 0x133 */
34 u8 exp_link_control[2];
35 u8 link_cap[4];
36 u8 link_control[2];
37 u8 serial_number[8];
38 u8 res0:2; /* 0x144 */
39 u8 ltr_en:1;
40 u8 res1:2;
41 u8 obff:2;
42 u8 res2:3;
43 u8 obff_cap:2;
44 u8 res3:4;
45 u8 class_code[3];
46 u8 res4;
47 u8 pci_pm_L1_2_supp:1;
48 u8 pci_pm_L1_1_supp:1;
49 u8 aspm_pm_L1_2_supp:1;
50 u8 aspm_pm_L1_1_supp:1;
51 u8 L1_pm_substates_supp:1;
52 u8 res5:3;
53 u8 port_common_mode_restore_time;
54 u8 port_t_power_on_scale:2;
55 u8 res6:1;
56 u8 port_t_power_on_value:5;
57 u8 res7;
58};
59
60struct rtw8822c_efuse {
61 __le16 rtl_id;
62 u8 res0[0x0e];
63
64 /* power index for four RF paths */
65 struct rtw_txpwr_idx txpwr_idx_table[4];
66
67 u8 channel_plan; /* 0xb8 */
68 u8 xtal_k;
69 u8 res1;
70 u8 iqk_lck;
71 u8 res2[5]; /* 0xbc */
72 u8 rf_board_option;
73 u8 rf_feature_option;
74 u8 rf_bt_setting;
75 u8 eeprom_version;
76 u8 eeprom_customer_id;
77 u8 tx_bb_swing_setting_2g;
78 u8 tx_bb_swing_setting_5g;
79 u8 tx_pwr_calibrate_rate;
80 u8 rf_antenna_option; /* 0xc9 */
81 u8 rfe_option;
82 u8 country_code[2];
83 u8 res3[3];
84 u8 path_a_thermal; /* 0xd0 */
85 u8 path_b_thermal;
86 u8 res4[2];
87 u8 rx_gain_gap_2g_ofdm;
88 u8 res5;
89 u8 rx_gain_gap_2g_cck;
90 u8 res6;
91 u8 rx_gain_gap_5gl;
92 u8 res7;
93 u8 rx_gain_gap_5gm;
94 u8 res8;
95 u8 rx_gain_gap_5gh;
96 u8 res9;
97 u8 res10[0x42];
98 union {
99 struct rtw8822ce_efuse e;
100 struct rtw8822cu_efuse u;
101 struct rtw8822cs_efuse s;
102 };
103};
104
105enum rtw8822c_dpk_agc_phase {
106 RTW_DPK_GAIN_CHECK,
107 RTW_DPK_GAIN_LARGE,
108 RTW_DPK_GAIN_LESS,
109 RTW_DPK_GL_LARGE,
110 RTW_DPK_GL_LESS,
111 RTW_DPK_LOSS_CHECK,
112 RTW_DPK_AGC_OUT,
113};
114
115enum rtw8822c_dpk_one_shot_action {
116 RTW_DPK_CAL_PWR,
117 RTW_DPK_GAIN_LOSS,
118 RTW_DPK_DO_DPK,
119 RTW_DPK_DPK_ON,
120 RTW_DPK_DAGC,
121 RTW_DPK_ACTION_MAX
122};
123
124void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev,
125 const struct rtw_table *tbl);
126
127extern const struct rtw_chip_info rtw8822c_hw_spec;
128
129#define RTW_DECL_TABLE_DPK(name) \
130const struct rtw_table name ## _tbl = { \
131 .data = name, \
132 .size = ARRAY_SIZE(name), \
133 .parse = rtw8822c_parse_tbl_dpk, \
134}
135
136#define DACK_PATH_8822C 2
137#define DACK_REG_8822C 16
138#define DACK_RF_8822C 1
139#define DACK_SN_8822C 100
140
141/* phy status page0 */
142#define GET_PHY_STAT_P0_PWDB_A(phy_stat) \
143 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
144#define GET_PHY_STAT_P0_PWDB_B(phy_stat) \
145 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
146#define GET_PHY_STAT_P0_GAIN_A(phy_stat) \
147 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
148#define GET_PHY_STAT_P0_CHANNEL(phy_stat) \
149 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
150#define GET_PHY_STAT_P0_GAIN_B(phy_stat) \
151 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
152
153/* phy status page1 */
154#define GET_PHY_STAT_P1_PWDB_A(phy_stat) \
155 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
156#define GET_PHY_STAT_P1_PWDB_B(phy_stat) \
157 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
158#define GET_PHY_STAT_P1_L_RXSC(phy_stat) \
159 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
160#define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \
161 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
162#define GET_PHY_STAT_P1_CHANNEL(phy_stat) \
163 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
164#define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \
165 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
166#define GET_PHY_STAT_P1_RXEVM_B(phy_stat) \
167 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
168#define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \
169 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
170#define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat) \
171 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
172#define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \
173 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
174#define GET_PHY_STAT_P1_RXSNR_B(phy_stat) \
175 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
176
177#define RTW8822C_EDCCA_MAX 0x7f
178#define REG_ANAPARLDO_POW_MAC 0x0029
179#define BIT_LDOE25_PON BIT(0)
180#define XCAP_MASK GENMASK(6, 0)
181#define CFO_TRK_ENABLE_TH 20
182#define CFO_TRK_STOP_TH 10
183#define CFO_TRK_ADJ_TH 10
184
185#define REG_TXDFIR0 0x808
186#define REG_DFIRBW 0x810
187#define REG_ANTMAP0 0x820
188#define BIT_ANT_PATH GENMASK(1, 0)
189#define REG_ANTMAP 0x824
190#define REG_EDCCA_DECISION 0x844
191#define BIT_EDCCA_OPTION GENMASK(30, 29)
192#define REG_DYMPRITH 0x86c
193#define REG_DYMENTH0 0x870
194#define REG_DYMENTH 0x874
195#define REG_SBD 0x88c
196#define BITS_SUBTUNE GENMASK(15, 12)
197#define REG_DYMTHMIN 0x8a4
198
199#define REG_TXBWCTL 0x9b0
200#define REG_TXCLK 0x9b4
201
202#define REG_SCOTRK 0xc30
203#define REG_MRCM 0xc38
204#define REG_AGCSWSH 0xc44
205#define REG_ANTWTPD 0xc54
206#define REG_PT_CHSMO 0xcbc
207#define BIT_PT_OPT BIT(21)
208
209#define REG_ORITXCODE 0x1800
210#define BIT_PATH_EN BIT(31)
211#define REG_3WIRE 0x180c
212#define BIT_DIS_SHARERX_TXGAT BIT(27)
213#define BIT_3WIRE_TX_EN BIT(0)
214#define BIT_3WIRE_RX_EN BIT(1)
215#define BIT_3WIRE_EN GENMASK(1, 0)
216#define BIT_3WIRE_PI_ON BIT(28)
217#define REG_ANAPAR_A 0x1830
218#define BIT_ANAPAR_UPDATE BIT(29)
219#define REG_RFTXEN_GCK_A 0x1864
220#define BIT_RFTXEN_GCK_FORCE_ON BIT(31)
221#define REG_DIS_SHARE_RX_A 0x186c
222#define BIT_TX_SCALE_0DB BIT(7)
223#define REG_RXAGCCTL0 0x18ac
224#define BITS_RXAGC_CCK GENMASK(15, 12)
225#define BITS_RXAGC_OFDM GENMASK(8, 4)
226#define REG_DCKA_I_0 0x18bc
227#define REG_DCKA_I_1 0x18c0
228#define REG_DCKA_Q_0 0x18d8
229#define REG_DCKA_Q_1 0x18dc
230
231#define REG_CCKSB 0x1a00
232#define BIT_BBMODE GENMASK(2, 1)
233#define REG_RXCCKSEL 0x1a04
234#define REG_BGCTRL 0x1a14
235#define BITS_RX_IQ_WEIGHT (BIT(8) | BIT(9))
236#define REG_TXF0 0x1a20
237#define REG_TXF1 0x1a24
238#define REG_TXF2 0x1a28
239#define REG_CCANRX 0x1a2c
240#define BIT_CCK_FA_RST (BIT(14) | BIT(15))
241#define BIT_OFDM_FA_RST (BIT(12) | BIT(13))
242#define REG_CCK_FACNT 0x1a5c
243#define REG_CCKTXONLY 0x1a80
244#define BIT_BB_CCK_CHECK_EN BIT(18)
245#define REG_TXF3 0x1a98
246#define REG_TXF4 0x1a9c
247#define REG_TXF5 0x1aa0
248#define REG_TXF6 0x1aac
249#define REG_TXF7 0x1ab0
250#define REG_CCK_SOURCE 0x1abc
251#define BIT_NBI_EN BIT(30)
252
253#define REG_NCTL0 0x1b00
254#define BIT_SEL_PATH GENMASK(2, 1)
255#define BIT_SUBPAGE GENMASK(3, 0)
256#define REG_DPD_CTL0_S0 0x1b04
257#define BIT_GS_PWSF GENMASK(27, 0)
258#define REG_DPD_CTL1_S0 0x1b08
259#define BIT_DPD_EN BIT(31)
260#define BIT_PS_EN BIT(7)
261#define REG_IQKSTAT 0x1b10
262#define REG_IQK_CTL1 0x1b20
263#define BIT_TX_CFIR GENMASK(31, 30)
264#define BIT_CFIR_EN GENMASK(26, 24)
265#define BIT_BYPASS_DPD BIT(25)
266
267#define REG_TX_TONE_IDX 0x1b2c
268#define REG_DPD_LUT0 0x1b44
269#define BIT_GLOSS_DB GENMASK(14, 12)
270#define REG_DPD_CTL0_S1 0x1b5c
271#define REG_DPD_CTL1_S1 0x1b60
272#define REG_DPD_AGC 0x1b67
273#define REG_TABLE_SEL 0x1b98
274#define BIT_I_GAIN GENMASK(19, 16)
275#define BIT_GAIN_RST BIT(15)
276#define BIT_Q_GAIN_SEL GENMASK(14, 12)
277#define BIT_Q_GAIN GENMASK(11, 0)
278#define REG_TX_GAIN_SET 0x1b9c
279#define BIT_GAPK_RPT_IDX GENMASK(11, 8)
280#define REG_DPD_CTL0 0x1bb4
281#define REG_SINGLE_TONE_SW 0x1bb8
282#define BIT_IRQ_TEST_MODE BIT(20)
283#define REG_R_CONFIG 0x1bcc
284#define BIT_INNER_LB BIT(21)
285#define BIT_IQ_SWITCH GENMASK(5, 0)
286#define BIT_2G_SWING 0x2d
287#define BIT_5G_SWING 0x36
288#define REG_RXSRAM_CTL 0x1bd4
289#define BIT_RPT_EN BIT(21)
290#define BIT_RPT_SEL GENMASK(20, 16)
291#define BIT_DPD_CLK GENMASK(7, 4)
292#define REG_DPD_CTL11 0x1be4
293#define REG_DPD_CTL12 0x1be8
294#define REG_DPD_CTL15 0x1bf4
295#define REG_DPD_CTL16 0x1bf8
296#define REG_STAT_RPT 0x1bfc
297#define BIT_RPT_DGAIN GENMASK(27, 16)
298#define BIT_GAPK_RPT0 GENMASK(3, 0)
299#define BIT_GAPK_RPT1 GENMASK(7, 4)
300#define BIT_GAPK_RPT2 GENMASK(11, 8)
301#define BIT_GAPK_RPT3 GENMASK(15, 12)
302#define BIT_GAPK_RPT4 GENMASK(19, 16)
303#define BIT_GAPK_RPT5 GENMASK(23, 20)
304#define BIT_GAPK_RPT6 GENMASK(27, 24)
305#define BIT_GAPK_RPT7 GENMASK(31, 28)
306
307#define REG_TXANT 0x1c28
308#define REG_IQK_CTRL 0x1c38
309#define REG_ENCCK 0x1c3c
310#define BIT_CCK_BLK_EN BIT(1)
311#define BIT_CCK_OFDM_BLK_EN (BIT(0) | BIT(1))
312#define REG_CCAMSK 0x1c80
313#define REG_RSTB 0x1c90
314#define BIT_RSTB_3WIRE BIT(8)
315#define REG_CH_DELAY_EXTR2 0x1cd0
316#define BIT_TST_IQK2SET_SRC BIT(31)
317#define BIT_EN_IOQ_IQK_DPK BIT(30)
318#define BIT_IQK_DPK_RESET_SRC BIT(29)
319#define BIT_IQK_DPK_CLOCK_SRC BIT(28)
320
321#define REG_RX_BREAK 0x1d2c
322#define BIT_COM_RX_GCK_EN BIT(31)
323#define REG_RXFNCTL 0x1d30
324#define REG_CCA_OFF 0x1d58
325#define BIT_CCA_ON_BY_PW GENMASK(11, 3)
326#define REG_RXIGI 0x1d70
327
328#define REG_ENFN 0x1e24
329#define BIT_IQK_DPK_EN BIT(17)
330#define REG_TXANTSEG 0x1e28
331#define BIT_ANTSEG GENMASK(3, 0)
332#define REG_TXLGMAP 0x1e2c
333#define REG_CCKPATH 0x1e5c
334#define REG_TX_FIFO 0x1e70
335#define BIT_STOP_TX GENMASK(3, 0)
336#define REG_CNT_CTRL 0x1eb4
337#define BIT_ALL_CNT_RST BIT(25)
338
339#define REG_OFDM_FACNT 0x2d00
340#define REG_OFDM_FACNT1 0x2d04
341#define REG_OFDM_FACNT2 0x2d08
342#define REG_OFDM_FACNT3 0x2d0c
343#define REG_OFDM_FACNT4 0x2d10
344#define REG_OFDM_FACNT5 0x2d20
345#define REG_RPT_CIP 0x2d9c
346#define BIT_RPT_CIP_STATUS GENMASK(7, 0)
347#define REG_OFDM_TXCNT 0x2de0
348
349#define REG_ORITXCODE2 0x4100
350#define REG_3WIRE2 0x410c
351#define REG_ANAPAR_B 0x4130
352#define REG_RFTXEN_GCK_B 0x4164
353#define REG_DIS_SHARE_RX_B 0x416c
354#define BIT_EXT_TIA_BW BIT(1)
355#define REG_RXAGCCTL 0x41ac
356#define REG_DCKB_I_0 0x41bc
357#define REG_DCKB_I_1 0x41c0
358#define REG_DCKB_Q_0 0x41d8
359#define REG_DCKB_Q_1 0x41dc
360
361#define RF_MODE_TRXAGC 0x00
362#define BIT_RF_MODE GENMASK(19, 16)
363#define BIT_RXAGC GENMASK(9, 5)
364#define BIT_TXAGC GENMASK(4, 0)
365#define RF_RXAGC_OFFSET 0x19
366#define RF_BW_TRXBB 0x1a
367#define BIT_TX_CCK_IND BIT(16)
368#define BIT_BW_TXBB GENMASK(14, 12)
369#define BIT_BW_RXBB GENMASK(11, 10)
370#define BIT_DBG_CCK_CCA BIT(1)
371#define RF_TX_GAIN_OFFSET 0x55
372#define BIT_BB_GAIN GENMASK(18, 14)
373#define BIT_RF_GAIN GENMASK(4, 2)
374#define RF_TX_GAIN 0x56
375#define BIT_GAIN_TXBB GENMASK(4, 0)
376#define RF_IDAC 0x58
377#define BIT_TX_MODE GENMASK(19, 8)
378#define RF_TX_RESULT 0x5f
379#define BIT_GAIN_TX_PAD_H GENMASK(11, 8)
380#define BIT_GAIN_TX_PAD_L GENMASK(7, 4)
381#define RF_PA 0x60
382#define RF_PABIAS_2G_MASK GENMASK(15, 12)
383#define RF_PABIAS_5G_MASK GENMASK(19, 16)
384#define RF_TXA_LB_SW 0x63
385#define BIT_TXA_LB_ATT GENMASK(15, 14)
386#define BIT_LB_SW GENMASK(13, 12)
387#define BIT_LB_ATT GENMASK(4, 2)
388#define RF_RXG_GAIN 0x87
389#define BIT_RXG_GAIN BIT(18)
390#define RF_RXA_MIX_GAIN 0x8a
391#define BIT_RXA_MIX_GAIN GENMASK(4, 3)
392#define RF_EXT_TIA_BW 0x8f
393#define BIT_PW_EXT_TIA BIT(1)
394#define RF_DIS_BYPASS_TXBB 0x9e
395#define BIT_TXBB BIT(10)
396#define BIT_TIA_BYPASS BIT(5)
397#define RF_DEBUG 0xde
398#define BIT_DE_PWR_TRIM BIT(19)
399#define BIT_DE_TX_GAIN BIT(16)
400#define BIT_DE_TRXBW BIT(2)
401
402#define PPG_THERMAL_B 0x1b0
403#define RF_THEMAL_MASK GENMASK(19, 16)
404#define PPG_2GH_TXAB 0x1d2
405#define PPG_2G_A_MASK GENMASK(3, 0)
406#define PPG_2G_B_MASK GENMASK(7, 4)
407#define PPG_2GL_TXAB 0x1d4
408#define PPG_PABIAS_2GB 0x1d5
409#define PPG_PABIAS_2GA 0x1d6
410#define PPG_PABIAS_MASK GENMASK(3, 0)
411#define PPG_PABIAS_5GB 0x1d7
412#define PPG_PABIAS_5GA 0x1d8
413#define PPG_5G_MASK GENMASK(4, 0)
414#define PPG_5GH1_TXB 0x1db
415#define PPG_5GH1_TXA 0x1dc
416#define PPG_5GM2_TXB 0x1df
417#define PPG_5GM2_TXA 0x1e0
418#define PPG_5GM1_TXB 0x1e3
419#define PPG_5GM1_TXA 0x1e4
420#define PPG_5GL2_TXB 0x1e7
421#define PPG_5GL2_TXA 0x1e8
422#define PPG_5GL1_TXB 0x1eb
423#define PPG_5GL1_TXA 0x1ec
424#define PPG_2GM_TXAB 0x1ee
425#define PPG_THERMAL_A 0x1ef
426#endif
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#ifndef __RTW8822C_H__
6#define __RTW8822C_H__
7
8#include <asm/byteorder.h>
9
10struct rtw8822cu_efuse {
11 u8 res0[0x30]; /* 0x120 */
12 u8 vid[2]; /* 0x150 */
13 u8 pid[2];
14 u8 res1[3];
15 u8 mac_addr[ETH_ALEN]; /* 0x157 */
16 u8 res2[0x3d];
17} __packed;
18
19struct rtw8822cs_efuse {
20 u8 res0[0x4a]; /* 0x120 */
21 u8 mac_addr[ETH_ALEN]; /* 0x16a */
22} __packed;
23
24struct rtw8822ce_efuse {
25 u8 mac_addr[ETH_ALEN]; /* 0x120 */
26 u8 vender_id[2];
27 u8 device_id[2];
28 u8 sub_vender_id[2];
29 u8 sub_device_id[2];
30 u8 pmc[2];
31 u8 exp_device_cap[2];
32 u8 msi_cap;
33 u8 ltr_cap; /* 0x133 */
34 u8 exp_link_control[2];
35 u8 link_cap[4];
36 u8 link_control[2];
37 u8 serial_number[8];
38 u8 res0:2; /* 0x144 */
39 u8 ltr_en:1;
40 u8 res1:2;
41 u8 obff:2;
42 u8 res2_1:1;
43 u8 res2_2:2;
44 u8 obff_cap:2;
45 u8 res3:4;
46 u8 class_code[3];
47 u8 res4;
48 u8 pci_pm_L1_2_supp:1;
49 u8 pci_pm_L1_1_supp:1;
50 u8 aspm_pm_L1_2_supp:1;
51 u8 aspm_pm_L1_1_supp:1;
52 u8 L1_pm_substates_supp:1;
53 u8 res5:3;
54 u8 port_common_mode_restore_time;
55 u8 port_t_power_on_scale:2;
56 u8 res6:1;
57 u8 port_t_power_on_value:5;
58 u8 res7;
59} __packed;
60
61struct rtw8822c_efuse {
62 __le16 rtl_id;
63 u8 res0[4];
64 u8 usb_mode;
65 u8 res1[0x09];
66
67 /* power index for four RF paths */
68 struct rtw_txpwr_idx txpwr_idx_table[4];
69
70 u8 channel_plan; /* 0xb8 */
71 u8 xtal_k;
72 u8 res2;
73 u8 iqk_lck;
74 u8 res3[5]; /* 0xbc */
75 u8 rf_board_option;
76 u8 rf_feature_option;
77 u8 rf_bt_setting;
78 u8 eeprom_version;
79 u8 eeprom_customer_id;
80 u8 tx_bb_swing_setting_2g;
81 u8 tx_bb_swing_setting_5g;
82 u8 tx_pwr_calibrate_rate;
83 u8 rf_antenna_option; /* 0xc9 */
84 u8 rfe_option;
85 u8 country_code[2];
86 u8 res4[3];
87 u8 path_a_thermal; /* 0xd0 */
88 u8 path_b_thermal;
89 u8 res5[2];
90 u8 rx_gain_gap_2g_ofdm;
91 u8 res6;
92 u8 rx_gain_gap_2g_cck;
93 u8 res7;
94 u8 rx_gain_gap_5gl;
95 u8 res8;
96 u8 rx_gain_gap_5gm;
97 u8 res9;
98 u8 rx_gain_gap_5gh;
99 u8 res10;
100 u8 res11[0x42];
101 union {
102 struct rtw8822ce_efuse e;
103 struct rtw8822cu_efuse u;
104 struct rtw8822cs_efuse s;
105 };
106} __packed;
107
108enum rtw8822c_dpk_agc_phase {
109 RTW_DPK_GAIN_CHECK,
110 RTW_DPK_GAIN_LARGE,
111 RTW_DPK_GAIN_LESS,
112 RTW_DPK_GL_LARGE,
113 RTW_DPK_GL_LESS,
114 RTW_DPK_LOSS_CHECK,
115 RTW_DPK_AGC_OUT,
116};
117
118enum rtw8822c_dpk_one_shot_action {
119 RTW_DPK_CAL_PWR,
120 RTW_DPK_GAIN_LOSS,
121 RTW_DPK_DO_DPK,
122 RTW_DPK_DPK_ON,
123 RTW_DPK_DAGC,
124 RTW_DPK_ACTION_MAX
125};
126
127void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev,
128 const struct rtw_table *tbl);
129
130extern const struct rtw_chip_info rtw8822c_hw_spec;
131
132#define RTW_DECL_TABLE_DPK(name) \
133const struct rtw_table name ## _tbl = { \
134 .data = name, \
135 .size = ARRAY_SIZE(name), \
136 .parse = rtw8822c_parse_tbl_dpk, \
137}
138
139#define DACK_PATH_8822C 2
140#define DACK_REG_8822C 16
141#define DACK_RF_8822C 1
142#define DACK_SN_8822C 100
143
144/* phy status page0 */
145#define GET_PHY_STAT_P0_PWDB_A(phy_stat) \
146 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
147#define GET_PHY_STAT_P0_PWDB_B(phy_stat) \
148 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
149#define GET_PHY_STAT_P0_GAIN_A(phy_stat) \
150 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
151#define GET_PHY_STAT_P0_CHANNEL(phy_stat) \
152 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
153#define GET_PHY_STAT_P0_GAIN_B(phy_stat) \
154 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
155
156/* phy status page1 */
157#define GET_PHY_STAT_P1_PWDB_A(phy_stat) \
158 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
159#define GET_PHY_STAT_P1_PWDB_B(phy_stat) \
160 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
161#define GET_PHY_STAT_P1_L_RXSC(phy_stat) \
162 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
163#define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \
164 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
165#define GET_PHY_STAT_P1_CHANNEL(phy_stat) \
166 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16))
167#define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \
168 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
169#define GET_PHY_STAT_P1_RXEVM_B(phy_stat) \
170 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
171#define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \
172 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
173#define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat) \
174 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
175#define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \
176 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
177#define GET_PHY_STAT_P1_RXSNR_B(phy_stat) \
178 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
179
180#define RTW8822C_EDCCA_MAX 0x7f
181#define REG_ANAPARLDO_POW_MAC 0x0029
182#define BIT_LDOE25_PON BIT(0)
183#define XCAP_MASK GENMASK(6, 0)
184#define CFO_TRK_ENABLE_TH 20
185#define CFO_TRK_STOP_TH 10
186#define CFO_TRK_ADJ_TH 10
187
188#define REG_TXDFIR0 0x808
189#define REG_DFIRBW 0x810
190#define REG_ANTMAP0 0x820
191#define BIT_ANT_PATH GENMASK(1, 0)
192#define REG_ANTMAP 0x824
193#define REG_EDCCA_DECISION 0x844
194#define BIT_EDCCA_OPTION GENMASK(30, 29)
195#define REG_DYMPRITH 0x86c
196#define REG_DYMENTH0 0x870
197#define REG_DYMENTH 0x874
198#define REG_SBD 0x88c
199#define BITS_SUBTUNE GENMASK(15, 12)
200#define REG_DYMTHMIN 0x8a4
201
202#define REG_TXBWCTL 0x9b0
203#define REG_TXCLK 0x9b4
204
205#define REG_SCOTRK 0xc30
206#define REG_MRCM 0xc38
207#define REG_AGCSWSH 0xc44
208#define REG_ANTWTPD 0xc54
209#define REG_PT_CHSMO 0xcbc
210#define BIT_PT_OPT BIT(21)
211
212#define REG_ORITXCODE 0x1800
213#define BIT_PATH_EN BIT(31)
214#define REG_3WIRE 0x180c
215#define BIT_DIS_SHARERX_TXGAT BIT(27)
216#define BIT_3WIRE_TX_EN BIT(0)
217#define BIT_3WIRE_RX_EN BIT(1)
218#define BIT_3WIRE_EN GENMASK(1, 0)
219#define BIT_3WIRE_PI_ON BIT(28)
220#define REG_ANAPAR_A 0x1830
221#define BIT_ANAPAR_UPDATE BIT(29)
222#define REG_RFTXEN_GCK_A 0x1864
223#define BIT_RFTXEN_GCK_FORCE_ON BIT(31)
224#define REG_DIS_SHARE_RX_A 0x186c
225#define BIT_TX_SCALE_0DB BIT(7)
226#define REG_RXAGCCTL0 0x18ac
227#define BITS_RXAGC_CCK GENMASK(15, 12)
228#define BITS_RXAGC_OFDM GENMASK(8, 4)
229#define REG_DCKA_I_0 0x18bc
230#define REG_DCKA_I_1 0x18c0
231#define REG_DCKA_Q_0 0x18d8
232#define REG_DCKA_Q_1 0x18dc
233
234#define REG_CCKSB 0x1a00
235#define BIT_BBMODE GENMASK(2, 1)
236#define REG_RXCCKSEL 0x1a04
237#define REG_BGCTRL 0x1a14
238#define BITS_RX_IQ_WEIGHT (BIT(8) | BIT(9))
239#define REG_TXF0 0x1a20
240#define REG_TXF1 0x1a24
241#define REG_TXF2 0x1a28
242#define REG_CCANRX 0x1a2c
243#define BIT_CCK_FA_RST (BIT(14) | BIT(15))
244#define BIT_OFDM_FA_RST (BIT(12) | BIT(13))
245#define REG_CCK_FACNT 0x1a5c
246#define REG_CCKTXONLY 0x1a80
247#define BIT_BB_CCK_CHECK_EN BIT(18)
248#define REG_TXF3 0x1a98
249#define REG_TXF4 0x1a9c
250#define REG_TXF5 0x1aa0
251#define REG_TXF6 0x1aac
252#define REG_TXF7 0x1ab0
253#define REG_CCK_SOURCE 0x1abc
254#define BIT_NBI_EN BIT(30)
255
256#define REG_NCTL0 0x1b00
257#define BIT_SEL_PATH GENMASK(2, 1)
258#define BIT_SUBPAGE GENMASK(3, 0)
259#define REG_DPD_CTL0_S0 0x1b04
260#define BIT_GS_PWSF GENMASK(27, 0)
261#define REG_DPD_CTL1_S0 0x1b08
262#define BIT_DPD_EN BIT(31)
263#define BIT_PS_EN BIT(7)
264#define REG_IQKSTAT 0x1b10
265#define REG_IQK_CTL1 0x1b20
266#define BIT_TX_CFIR GENMASK(31, 30)
267#define BIT_CFIR_EN GENMASK(26, 24)
268#define BIT_BYPASS_DPD BIT(25)
269
270#define REG_TX_TONE_IDX 0x1b2c
271#define REG_DPD_LUT0 0x1b44
272#define BIT_GLOSS_DB GENMASK(14, 12)
273#define REG_DPD_CTL0_S1 0x1b5c
274#define REG_DPD_CTL1_S1 0x1b60
275#define REG_DPD_AGC 0x1b67
276#define REG_TABLE_SEL 0x1b98
277#define BIT_I_GAIN GENMASK(19, 16)
278#define BIT_GAIN_RST BIT(15)
279#define BIT_Q_GAIN_SEL GENMASK(14, 12)
280#define BIT_Q_GAIN GENMASK(11, 0)
281#define REG_TX_GAIN_SET 0x1b9c
282#define BIT_GAPK_RPT_IDX GENMASK(11, 8)
283#define REG_DPD_CTL0 0x1bb4
284#define REG_SINGLE_TONE_SW 0x1bb8
285#define BIT_IRQ_TEST_MODE BIT(20)
286#define REG_R_CONFIG 0x1bcc
287#define BIT_INNER_LB BIT(21)
288#define BIT_IQ_SWITCH GENMASK(5, 0)
289#define BIT_2G_SWING 0x2d
290#define BIT_5G_SWING 0x36
291#define REG_RXSRAM_CTL 0x1bd4
292#define BIT_RPT_EN BIT(21)
293#define BIT_RPT_SEL GENMASK(20, 16)
294#define BIT_DPD_CLK GENMASK(7, 4)
295#define REG_DPD_CTL11 0x1be4
296#define REG_DPD_CTL12 0x1be8
297#define REG_DPD_CTL15 0x1bf4
298#define REG_DPD_CTL16 0x1bf8
299#define REG_STAT_RPT 0x1bfc
300#define BIT_RPT_DGAIN GENMASK(27, 16)
301#define BIT_GAPK_RPT0 GENMASK(3, 0)
302#define BIT_GAPK_RPT1 GENMASK(7, 4)
303#define BIT_GAPK_RPT2 GENMASK(11, 8)
304#define BIT_GAPK_RPT3 GENMASK(15, 12)
305#define BIT_GAPK_RPT4 GENMASK(19, 16)
306#define BIT_GAPK_RPT5 GENMASK(23, 20)
307#define BIT_GAPK_RPT6 GENMASK(27, 24)
308#define BIT_GAPK_RPT7 GENMASK(31, 28)
309
310#define REG_TXANT 0x1c28
311#define REG_IQK_CTRL 0x1c38
312#define REG_ENCCK 0x1c3c
313#define BIT_CCK_BLK_EN BIT(1)
314#define BIT_CCK_OFDM_BLK_EN (BIT(0) | BIT(1))
315#define REG_CCAMSK 0x1c80
316#define REG_RSTB 0x1c90
317#define BIT_RSTB_3WIRE BIT(8)
318#define REG_CH_DELAY_EXTR2 0x1cd0
319#define BIT_TST_IQK2SET_SRC BIT(31)
320#define BIT_EN_IOQ_IQK_DPK BIT(30)
321#define BIT_IQK_DPK_RESET_SRC BIT(29)
322#define BIT_IQK_DPK_CLOCK_SRC BIT(28)
323
324#define REG_RX_BREAK 0x1d2c
325#define BIT_COM_RX_GCK_EN BIT(31)
326#define REG_RXFNCTL 0x1d30
327#define REG_CCA_OFF 0x1d58
328#define BIT_CCA_ON_BY_PW GENMASK(11, 3)
329#define REG_RXIGI 0x1d70
330
331#define REG_ENFN 0x1e24
332#define BIT_IQK_DPK_EN BIT(17)
333#define REG_TXANTSEG 0x1e28
334#define BIT_ANTSEG GENMASK(3, 0)
335#define REG_TXLGMAP 0x1e2c
336#define REG_CCKPATH 0x1e5c
337#define REG_TX_FIFO 0x1e70
338#define BIT_STOP_TX GENMASK(3, 0)
339#define REG_CNT_CTRL 0x1eb4
340#define BIT_ALL_CNT_RST BIT(25)
341
342#define REG_OFDM_FACNT 0x2d00
343#define REG_OFDM_FACNT1 0x2d04
344#define REG_OFDM_FACNT2 0x2d08
345#define REG_OFDM_FACNT3 0x2d0c
346#define REG_OFDM_FACNT4 0x2d10
347#define REG_OFDM_FACNT5 0x2d20
348#define REG_RPT_CIP 0x2d9c
349#define BIT_RPT_CIP_STATUS GENMASK(7, 0)
350#define REG_OFDM_TXCNT 0x2de0
351
352#define REG_ORITXCODE2 0x4100
353#define REG_3WIRE2 0x410c
354#define REG_ANAPAR_B 0x4130
355#define REG_RFTXEN_GCK_B 0x4164
356#define REG_DIS_SHARE_RX_B 0x416c
357#define BIT_EXT_TIA_BW BIT(1)
358#define REG_RXAGCCTL 0x41ac
359#define REG_DCKB_I_0 0x41bc
360#define REG_DCKB_I_1 0x41c0
361#define REG_DCKB_Q_0 0x41d8
362#define REG_DCKB_Q_1 0x41dc
363
364#define RF_MODE_TRXAGC 0x00
365#define BIT_RF_MODE GENMASK(19, 16)
366#define BIT_RXAGC GENMASK(9, 5)
367#define BIT_TXAGC GENMASK(4, 0)
368#define RF_RXAGC_OFFSET 0x19
369#define RF_BW_TRXBB 0x1a
370#define BIT_TX_CCK_IND BIT(16)
371#define BIT_BW_TXBB GENMASK(14, 12)
372#define BIT_BW_RXBB GENMASK(11, 10)
373#define BIT_DBG_CCK_CCA BIT(1)
374#define RF_TX_GAIN_OFFSET 0x55
375#define BIT_BB_GAIN GENMASK(18, 14)
376#define BIT_RF_GAIN GENMASK(4, 2)
377#define RF_TX_GAIN 0x56
378#define BIT_GAIN_TXBB GENMASK(4, 0)
379#define RF_IDAC 0x58
380#define BIT_TX_MODE GENMASK(19, 8)
381#define RF_TX_RESULT 0x5f
382#define BIT_GAIN_TX_PAD_H GENMASK(11, 8)
383#define BIT_GAIN_TX_PAD_L GENMASK(7, 4)
384#define RF_PA 0x60
385#define RF_PABIAS_2G_MASK GENMASK(15, 12)
386#define RF_PABIAS_5G_MASK GENMASK(19, 16)
387#define RF_TXA_LB_SW 0x63
388#define BIT_TXA_LB_ATT GENMASK(15, 14)
389#define BIT_LB_SW GENMASK(13, 12)
390#define BIT_LB_ATT GENMASK(4, 2)
391#define RF_RXG_GAIN 0x87
392#define BIT_RXG_GAIN BIT(18)
393#define RF_RXA_MIX_GAIN 0x8a
394#define BIT_RXA_MIX_GAIN GENMASK(4, 3)
395#define RF_EXT_TIA_BW 0x8f
396#define BIT_PW_EXT_TIA BIT(1)
397#define RF_DIS_BYPASS_TXBB 0x9e
398#define BIT_TXBB BIT(10)
399#define BIT_TIA_BYPASS BIT(5)
400#define RF_DEBUG 0xde
401#define BIT_DE_PWR_TRIM BIT(19)
402#define BIT_DE_TX_GAIN BIT(16)
403#define BIT_DE_TRXBW BIT(2)
404
405#define PPG_THERMAL_B 0x1b0
406#define RF_THEMAL_MASK GENMASK(19, 16)
407#define PPG_2GH_TXAB 0x1d2
408#define PPG_2G_A_MASK GENMASK(3, 0)
409#define PPG_2G_B_MASK GENMASK(7, 4)
410#define PPG_2GL_TXAB 0x1d4
411#define PPG_PABIAS_2GB 0x1d5
412#define PPG_PABIAS_2GA 0x1d6
413#define PPG_PABIAS_MASK GENMASK(3, 0)
414#define PPG_PABIAS_5GB 0x1d7
415#define PPG_PABIAS_5GA 0x1d8
416#define PPG_5G_MASK GENMASK(4, 0)
417#define PPG_5GH1_TXB 0x1db
418#define PPG_5GH1_TXA 0x1dc
419#define PPG_5GM2_TXB 0x1df
420#define PPG_5GM2_TXA 0x1e0
421#define PPG_5GM1_TXB 0x1e3
422#define PPG_5GM1_TXA 0x1e4
423#define PPG_5GL2_TXB 0x1e7
424#define PPG_5GL2_TXA 0x1e8
425#define PPG_5GL1_TXB 0x1eb
426#define PPG_5GL1_TXA 0x1ec
427#define PPG_2GM_TXAB 0x1ee
428#define PPG_THERMAL_A 0x1ef
429#endif