1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2/* Copyright(c) 2018-2019  Realtek Corporation
   3 */
   4
   5#include "main.h"
   6#include "coex.h"
   7#include "fw.h"
   8#include "tx.h"
   9#include "rx.h"
  10#include "phy.h"
  11#include "rtw8821c.h"
  12#include "rtw8821c_table.h"
  13#include "mac.h"
  14#include "reg.h"
  15#include "debug.h"
  16#include "bf.h"
  17#include "regd.h"
  18
  19static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
  20static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
  21					-20, -24, -28, -31, -34, -37, -40, -44};
  22
  23static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse,
  24				    struct rtw8821c_efuse *map)
  25{
  26	ether_addr_copy(efuse->addr, map->e.mac_addr);
  27}
  28
  29static void rtw8821cu_efuse_parsing(struct rtw_efuse *efuse,
  30				    struct rtw8821c_efuse *map)
  31{
  32	ether_addr_copy(efuse->addr, map->u.mac_addr);
  33}
  34
  35static void rtw8821cs_efuse_parsing(struct rtw_efuse *efuse,
  36				    struct rtw8821c_efuse *map)
  37{
  38	ether_addr_copy(efuse->addr, map->s.mac_addr);
  39}
  40
  41enum rtw8821ce_rf_set {
  42	SWITCH_TO_BTG,
  43	SWITCH_TO_WLG,
  44	SWITCH_TO_WLA,
  45	SWITCH_TO_BT,
  46};
  47
  48static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
  49{
  50	struct rtw_hal *hal = &rtwdev->hal;
  51	struct rtw_efuse *efuse = &rtwdev->efuse;
  52	struct rtw8821c_efuse *map;
  53	int i;
  54
  55	map = (struct rtw8821c_efuse *)log_map;
  56
  57	efuse->rfe_option = map->rfe_option & 0x1f;
  58	efuse->rf_board_option = map->rf_board_option;
  59	efuse->crystal_cap = map->xtal_k;
  60	efuse->pa_type_2g = map->pa_type;
  61	efuse->pa_type_5g = map->pa_type;
  62	efuse->lna_type_2g = map->lna_type_2g[0];
  63	efuse->lna_type_5g = map->lna_type_5g[0];
  64	efuse->channel_plan = map->channel_plan;
  65	efuse->country_code[0] = map->country_code[0];
  66	efuse->country_code[1] = map->country_code[1];
  67	efuse->bt_setting = map->rf_bt_setting;
  68	efuse->regd = map->rf_board_option & 0x7;
  69	efuse->thermal_meter[0] = map->thermal_meter;
  70	efuse->thermal_meter_k = map->thermal_meter;
  71	efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
  72	efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
  73
  74	hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0;
  75
  76	switch (efuse->rfe_option) {
  77	case 0x2:
  78	case 0x4:
  79	case 0x7:
  80	case 0xa:
  81	case 0xc:
  82	case 0xf:
  83		hal->rfe_btg = true;
  84		break;
  85	}
  86
  87	for (i = 0; i < 4; i++)
  88		efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
  89
  90	if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4)
  91		efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g;
  92
  93	switch (rtw_hci_type(rtwdev)) {
  94	case RTW_HCI_TYPE_PCIE:
  95		rtw8821ce_efuse_parsing(efuse, map);
  96		break;
  97	case RTW_HCI_TYPE_USB:
  98		rtw8821cu_efuse_parsing(efuse, map);
  99		break;
 100	case RTW_HCI_TYPE_SDIO:
 101		rtw8821cs_efuse_parsing(efuse, map);
 102		break;
 103	default:
 104		/* unsupported now */
 105		return -ENOTSUPP;
 106	}
 107
 108	return 0;
 109}
 110
 111static const u32 rtw8821c_txscale_tbl[] = {
 112	0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
 113	0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
 114	0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
 115	0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
 116};
 117
 118static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev)
 119{
 120	u8 i = 0;
 121	u32 swing, table_value;
 122
 123	swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000);
 124	for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) {
 125		table_value = rtw8821c_txscale_tbl[i];
 126		if (swing == table_value)
 127			break;
 128	}
 129
 130	return i;
 131}
 132
 133static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev)
 134{
 135	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 136	u8 swing_idx = rtw8821c_get_swing_index(rtwdev);
 137
 138	if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl))
 139		dm_info->default_ofdm_index = 24;
 140	else
 141		dm_info->default_ofdm_index = swing_idx;
 142
 143	ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]);
 144	dm_info->delta_power_index[RF_PATH_A] = 0;
 145	dm_info->delta_power_index_last[RF_PATH_A] = 0;
 146	dm_info->pwr_trk_triggered = false;
 147	dm_info->pwr_trk_init_trigger = true;
 148	dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
 149}
 150
 151static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev)
 152{
 153	rtw_bf_phy_init(rtwdev);
 154	/* Grouping bitmap parameters */
 155	rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF);
 156}
 157
 158static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
 159{
 160	struct rtw_hal *hal = &rtwdev->hal;
 161	u8 crystal_cap, val;
 162
 163	/* power on BB/RF domain */
 164	val = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
 165	val |= BIT_FEN_PCIEA;
 166	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
 167
 168	/* toggle BB reset */
 169	val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
 170	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
 171	val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
 172	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
 173	val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
 174	rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
 175
 176	rtw_write8(rtwdev, REG_RF_CTRL,
 177		   BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
 178	usleep_range(10, 11);
 179	rtw_write8(rtwdev, REG_WLRF1 + 3,
 180		   BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
 181	usleep_range(10, 11);
 182
 183	/* pre init before header files config */
 184	rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
 185
 186	rtw_phy_load_tables(rtwdev);
 187
 188	crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
 189	rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
 190	rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
 191	rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0);
 192
 193	/* post init after header files config */
 194	rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
 195	hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);
 196	hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD);
 197	hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);
 198
 199	rtw_phy_init(rtwdev);
 200	rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
 201
 202	rtw8821c_pwrtrack_init(rtwdev);
 203
 204	rtw8821c_phy_bf_init(rtwdev);
 205}
 206
 207static int rtw8821c_mac_init(struct rtw_dev *rtwdev)
 208{
 209	u32 value32;
 210	u16 pre_txcnt;
 211
 212	/* protocol configuration */
 213	rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
 214	rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
 215	pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
 216	rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
 217	rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
 218	value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
 219		  (WLAN_MAX_AGG_PKT_LIMIT << 16) |
 220		  (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
 221	rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
 222	rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
 223		    WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
 224	rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
 225	rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
 226	rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
 227	rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
 228	rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5));
 229
 230	/* EDCA configuration */
 231	rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
 232	rtw_write16(rtwdev, REG_TXPAUSE, 0);
 233	rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
 234	rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
 235	rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
 236	rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
 237	rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
 238	rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
 239	rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
 240
 241	/* Set beacon cotnrol - enable TSF and other related functions */
 242	rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
 243
 244	/* Set send beacon related registers */
 245	rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
 246	rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
 247	rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
 248	rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
 249
 250	/* WMAC configuration */
 251	rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
 252	rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
 253	rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
 254	rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
 255	rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
 256	rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
 257	rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40);
 258	rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1));
 259	rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL,
 260		       BIT_DIS_CHK_VHTSIGB_CRC);
 261	rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
 262	rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
 263
 264	return 0;
 265}
 266
 267static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
 268{
 269	u8 ldo_pwr;
 270
 271	ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
 272	ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7);
 273	rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
 274}
 275
 276static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set)
 277{
 278	u32 reg;
 279
 280	rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST);
 281	rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN);
 282
 283	reg = rtw_read32(rtwdev, REG_RFECTL);
 284	switch (rf_set) {
 285	case SWITCH_TO_BTG:
 286		reg |= B_BTG_SWITCH;
 287		reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH |
 288			 B_WLA_SWITCH);
 289		rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA);
 290		rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA);
 291		break;
 292	case SWITCH_TO_WLG:
 293		reg |= B_WL_SWITCH | B_WLG_SWITCH;
 294		reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH);
 295		rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA);
 296		rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA);
 297		break;
 298	case SWITCH_TO_WLA:
 299		reg |= B_WL_SWITCH | B_WLA_SWITCH;
 300		reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH);
 301		break;
 302	case SWITCH_TO_BT:
 303	default:
 304		break;
 305	}
 306
 307	rtw_write32(rtwdev, REG_RFECTL, reg);
 308}
 309
 310static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
 311{
 312	struct rtw_hal *hal = &rtwdev->hal;
 313	u32 rf_reg18;
 314
 315	rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
 316
 317	rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
 318		      RF18_BW_MASK);
 319
 320	rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
 321	rf_reg18 |= (channel & RF18_CHANNEL_MASK);
 322
 323	if (channel >= 100 && channel <= 140)
 324		rf_reg18 |= RF18_RFSI_GE;
 325	else if (channel > 140)
 326		rf_reg18 |= RF18_RFSI_GT;
 327
 328	switch (bw) {
 329	case RTW_CHANNEL_WIDTH_5:
 330	case RTW_CHANNEL_WIDTH_10:
 331	case RTW_CHANNEL_WIDTH_20:
 332	default:
 333		rf_reg18 |= RF18_BW_20M;
 334		break;
 335	case RTW_CHANNEL_WIDTH_40:
 336		rf_reg18 |= RF18_BW_40M;
 337		break;
 338	case RTW_CHANNEL_WIDTH_80:
 339		rf_reg18 |= RF18_BW_80M;
 340		break;
 341	}
 342
 343	if (channel <= 14) {
 344		if (hal->rfe_btg)
 345			rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG);
 346		else
 347			rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG);
 348		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1);
 349		rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf);
 350	} else {
 351		rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA);
 352		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0);
 353	}
 354
 355	rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
 356
 357	rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
 358	rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
 359}
 360
 361static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
 362{
 363	if (bw == RTW_CHANNEL_WIDTH_40) {
 364		/* RX DFIR for BW40 */
 365		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
 366		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
 367		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
 368		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
 369	} else if (bw == RTW_CHANNEL_WIDTH_80) {
 370		/* RX DFIR for BW80 */
 371		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
 372		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
 373		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
 374		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1);
 375	} else {
 376		/* RX DFIR for BW20, BW10 and BW5 */
 377		rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
 378		rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
 379		rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
 380		rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
 381	}
 382}
 383
 384static void rtw8821c_cck_tx_filter_srrc(struct rtw_dev *rtwdev, u8 channel, u8 bw)
 385{
 386	struct rtw_hal *hal = &rtwdev->hal;
 387
 388	if (channel == 14) {
 389		rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c);
 390		rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
 391		rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
 392		rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
 393
 394		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002);
 395		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e);
 396		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
 397		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c);
 398		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
 399		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e);
 400		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
 401		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c);
 402		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
 403		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000);
 404	} else if (channel == 13 ||
 405		   (channel == 11 && bw == RTW_CHANNEL_WIDTH_40)) {
 406		rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xf8fe);
 407		rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x64b80c1c);
 408		rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x8810);
 409		rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x01235667);
 410
 411		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002);
 412		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e);
 413		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027);
 414		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c);
 415		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027);
 416		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e);
 417		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00029);
 418		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c);
 419		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00026);
 420		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000);
 421	} else {
 422		rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c);
 423		rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
 424				 hal->ch_param[0]);
 425		rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
 426				 hal->ch_param[1] & MASKLWORD);
 427		rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
 428				 hal->ch_param[2]);
 429
 430		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002);
 431		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e);
 432		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
 433		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c);
 434		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
 435		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e);
 436		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
 437		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c);
 438		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
 439		rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000);
 440	}
 441}
 442
 443static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
 444				    u8 primary_ch_idx)
 445{
 446	struct rtw_hal *hal = &rtwdev->hal;
 447	u32 val32;
 448
 449	if (channel <= 14) {
 450		rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
 451		rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
 452		rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
 453		rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
 454
 455		rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0);
 456		rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
 457
 458		if (rtw_regd_srrc(rtwdev)) {
 459			rtw8821c_cck_tx_filter_srrc(rtwdev, channel, bw);
 460			goto set_bw;
 461		}
 462
 463		/* CCK TX filter parameters for default case */
 464		if (channel == 14) {
 465			rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
 466			rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
 467			rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
 468		} else {
 469			rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
 470					 hal->ch_param[0]);
 471			rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
 472					 hal->ch_param[1] & MASKLWORD);
 473			rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
 474					 hal->ch_param[2]);
 475		}
 476	} else if (channel > 35) {
 477		rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
 478		rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
 479		rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
 480		rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
 481
 482		if (channel >= 36 && channel <= 64)
 483			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1);
 484		else if (channel >= 100 && channel <= 144)
 485			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2);
 486		else if (channel >= 149)
 487			rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3);
 488
 489		if (channel >= 36 && channel <= 48)
 490			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
 491		else if (channel >= 52 && channel <= 64)
 492			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
 493		else if (channel >= 100 && channel <= 116)
 494			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
 495		else if (channel >= 118 && channel <= 177)
 496			rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
 497	}
 498
 499set_bw:
 500	switch (bw) {
 501	case RTW_CHANNEL_WIDTH_20:
 502	default:
 503		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
 504		val32 &= 0xffcffc00;
 505		val32 |= 0x10010000;
 506		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
 507
 508		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
 509		break;
 510	case RTW_CHANNEL_WIDTH_40:
 511		if (primary_ch_idx == 1)
 512			rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
 513		else
 514			rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
 515
 516		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
 517		val32 &= 0xff3ff300;
 518		val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) |
 519			 RTW_CHANNEL_WIDTH_40;
 520		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
 521
 522		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
 523		break;
 524	case RTW_CHANNEL_WIDTH_80:
 525		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
 526		val32 &= 0xfcffcf00;
 527		val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) |
 528			 RTW_CHANNEL_WIDTH_80;
 529		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
 530
 531		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
 532		break;
 533	case RTW_CHANNEL_WIDTH_5:
 534		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
 535		val32 &= 0xefcefc00;
 536		val32 |= 0x200240;
 537		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
 538
 539		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
 540		rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
 541		break;
 542	case RTW_CHANNEL_WIDTH_10:
 543		val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
 544		val32 &= 0xefcefc00;
 545		val32 |= 0x300380;
 546		rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
 547
 548		rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
 549		rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
 550		break;
 551	}
 552}
 553
 554static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel)
 555{
 556	struct rtw_efuse efuse = rtwdev->efuse;
 557	u8 tx_bb_swing;
 558	u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
 559
 560	tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g :
 561				      efuse.tx_bb_swing_setting_5g;
 562	if (tx_bb_swing > 9)
 563		tx_bb_swing = 0;
 564
 565	return swing2setting[(tx_bb_swing / 3)];
 566}
 567
 568static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel,
 569					  u8 bw, u8 primary_ch_idx)
 570{
 571	rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
 572			 rtw8821c_get_bb_swing(rtwdev, channel));
 573	rtw8821c_pwrtrack_init(rtwdev);
 574}
 575
 576static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
 577				 u8 primary_chan_idx)
 578{
 579	rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
 580	rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx);
 581	rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
 582	rtw8821c_set_channel_rf(rtwdev, channel, bw);
 583	rtw8821c_set_channel_rxdfir(rtwdev, bw);
 584}
 585
 586static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx)
 587{
 588	struct rtw_efuse *efuse = &rtwdev->efuse;
 589	const s8 *lna_gain_table;
 590	int lna_gain_table_size;
 591	s8 rx_pwr_all = 0;
 592	s8 lna_gain = 0;
 593
 594	if (efuse->rfe_option == 0) {
 595		lna_gain_table = lna_gain_table_0;
 596		lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0);
 597	} else {
 598		lna_gain_table = lna_gain_table_1;
 599		lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1);
 600	}
 601
 602	if (lna_idx >= lna_gain_table_size) {
 603		rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx);
 604		return -120;
 605	}
 606
 607	lna_gain = lna_gain_table[lna_idx];
 608	rx_pwr_all = lna_gain - 2 * vga_idx;
 609
 610	return rx_pwr_all;
 611}
 612
 613static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
 614				   struct rtw_rx_pkt_stat *pkt_stat)
 615{
 616	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 617	s8 rx_power;
 618	u8 lna_idx = 0;
 619	u8 vga_idx = 0;
 620
 621	vga_idx = GET_PHY_STAT_P0_VGA(phy_status);
 622	lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) |
 623		  FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status));
 624	rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx);
 625
 626	pkt_stat->rx_power[RF_PATH_A] = rx_power;
 627	pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
 628	dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
 629	pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
 630	pkt_stat->signal_power = rx_power;
 631}
 632
 633static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
 634				   struct rtw_rx_pkt_stat *pkt_stat)
 635{
 636	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 637	u8 rxsc, bw;
 638	s8 min_rx_power = -120;
 639
 640	if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
 641		rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
 642	else
 643		rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
 644
 645	if (rxsc >= 1 && rxsc <= 8)
 646		bw = RTW_CHANNEL_WIDTH_20;
 647	else if (rxsc >= 9 && rxsc <= 12)
 648		bw = RTW_CHANNEL_WIDTH_40;
 649	else if (rxsc >= 13)
 650		bw = RTW_CHANNEL_WIDTH_80;
 651	else
 652		bw = GET_PHY_STAT_P1_RF_MODE(phy_status);
 653
 654	pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
 655	pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
 656	dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
 657	pkt_stat->bw = bw;
 658	pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
 659				     min_rx_power);
 660}
 661
 662static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
 663			     struct rtw_rx_pkt_stat *pkt_stat)
 664{
 665	u8 page;
 666
 667	page = *phy_status & 0xf;
 668
 669	switch (page) {
 670	case 0:
 671		query_phy_status_page0(rtwdev, phy_status, pkt_stat);
 672		break;
 673	case 1:
 674		query_phy_status_page1(rtwdev, phy_status, pkt_stat);
 675		break;
 676	default:
 677		rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
 678		return;
 679	}
 680}
 681
 682static void rtw8821c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
 683				   struct rtw_rx_pkt_stat *pkt_stat,
 684				   struct ieee80211_rx_status *rx_status)
 685{
 686	struct ieee80211_hdr *hdr;
 687	u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
 688	u8 *phy_status = NULL;
 689
 690	memset(pkt_stat, 0, sizeof(*pkt_stat));
 691
 692	pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
 693	pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
 694	pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
 695	pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&
 696			      GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE;
 697	pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
 698	pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
 699	pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
 700	pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
 701	pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
 702	pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
 703	pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
 704	pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
 705
 706	/* drv_info_sz is in unit of 8-bytes */
 707	pkt_stat->drv_info_sz *= 8;
 708
 709	/* c2h cmd pkt's rx/phy status is not interested */
 710	if (pkt_stat->is_c2h)
 711		return;
 712
 713	hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
 714				       pkt_stat->drv_info_sz);
 715	if (pkt_stat->phy_status) {
 716		phy_status = rx_desc + desc_sz + pkt_stat->shift;
 717		query_phy_status(rtwdev, phy_status, pkt_stat);
 718	}
 719
 720	rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
 721}
 722
 723static void
 724rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
 725{
 726	struct rtw_hal *hal = &rtwdev->hal;
 727	static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
 728	static u32 phy_pwr_idx;
 729	u8 rate, rate_idx, pwr_index, shift;
 730	int j;
 731
 732	for (j = 0; j < rtw_rate_size[rs]; j++) {
 733		rate = rtw_rate_section[rs][j];
 734		pwr_index = hal->tx_pwr_tbl[path][rate];
 735		shift = rate & 0x3;
 736		phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
 737		if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) {
 738			rate_idx = rate & 0xfc;
 739			rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
 740				    phy_pwr_idx);
 741			phy_pwr_idx = 0;
 742		}
 743	}
 744}
 745
 746static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev)
 747{
 748	struct rtw_hal *hal = &rtwdev->hal;
 749	int rs, path;
 750
 751	for (path = 0; path < hal->rf_path_num; path++) {
 752		for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
 753			if (rs == RTW_RATE_SECTION_HT_2S ||
 754			    rs == RTW_RATE_SECTION_VHT_2S)
 755				continue;
 756			rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs);
 757		}
 758	}
 759}
 760
 761static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev)
 762{
 763	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 764	u32 cck_enable;
 765	u32 cck_fa_cnt;
 766	u32 ofdm_fa_cnt;
 767	u32 crc32_cnt;
 768	u32 cca32_cnt;
 769
 770	cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);
 771	cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK);
 772	ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM);
 773
 774	dm_info->cck_fa_cnt = cck_fa_cnt;
 775	dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
 776	dm_info->total_fa_cnt = ofdm_fa_cnt;
 777	if (cck_enable)
 778		dm_info->total_fa_cnt += cck_fa_cnt;
 779
 780	crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK);
 781	dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
 782	dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
 783
 784	crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM);
 785	dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
 786	dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
 787
 788	crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT);
 789	dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
 790	dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
 791
 792	crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT);
 793	dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
 794	dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
 795
 796	cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM);
 797	dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt);
 798	dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
 799	if (cck_enable) {
 800		cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK);
 801		dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt);
 802		dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
 803	}
 804
 805	rtw_write32_set(rtwdev, REG_FAS, BIT(17));
 806	rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
 807	rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15));
 808	rtw_write32_set(rtwdev, REG_RXDESC, BIT(15));
 809	rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
 810	rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
 811}
 812
 813static void rtw8821c_do_iqk(struct rtw_dev *rtwdev)
 814{
 815	static int do_iqk_cnt;
 816	struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
 817	u32 rf_reg, iqk_fail_mask;
 818	int counter;
 819	bool reload;
 820
 821	if (rtw_is_assoc(rtwdev))
 822		para.segment_iqk = 1;
 823
 824	rtw_fw_do_iqk(rtwdev, &para);
 825
 826	for (counter = 0; counter < 300; counter++) {
 827		rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
 828		if (rf_reg == 0xabcde)
 829			break;
 830		msleep(20);
 831	}
 832	rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
 833
 834	reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
 835	iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
 836	rtw_dbg(rtwdev, RTW_DBG_PHY,
 837		"iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
 838		counter, reload, ++do_iqk_cnt, iqk_fail_mask);
 839}
 840
 841static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev)
 842{
 843	rtw8821c_do_iqk(rtwdev);
 844}
 845
 846/* for coex */
 847static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev)
 848{
 849	/* enable TBTT nterrupt */
 850	rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
 851
 852	/* BT report packet sample rate */
 853	rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
 854
 855	/* enable BT counter statistics */
 856	rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE);
 857
 858	/* enable PTA (3-wire function form BT side) */
 859	rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
 860	rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
 861
 862	/* enable PTA (tx/rx signal form WiFi side) */
 863	rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
 864	/* wl tx signal to PTA not case EDCCA */
 865	rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
 866	/* GNT_BT=1 while select both */
 867	rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
 868
 869	/* beacon queue always hi-pri  */
 870	rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE,
 871			BCN_PRI_EN);
 872}
 873
 874static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type,
 875					 u8 pos_type)
 876{
 877	struct rtw_coex *coex = &rtwdev->coex;
 878	struct rtw_coex_dm *coex_dm = &coex->dm;
 879	struct rtw_coex_rfe *coex_rfe = &coex->rfe;
 880	u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type;
 881	bool polarity_inverse;
 882	u8 regval = 0;
 883
 884	if (switch_status == coex_dm->cur_switch_status)
 885		return;
 886
 887	if (coex_rfe->wlg_at_btg) {
 888		ctrl_type = COEX_SWITCH_CTRL_BY_BBSW;
 889
 890		if (coex_rfe->ant_switch_polarity)
 891			pos_type = COEX_SWITCH_TO_WLA;
 892		else
 893			pos_type = COEX_SWITCH_TO_WLG_BT;
 894	}
 895
 896	coex_dm->cur_switch_status = switch_status;
 897
 898	if (coex_rfe->ant_switch_diversity &&
 899	    ctrl_type == COEX_SWITCH_CTRL_BY_BBSW)
 900		ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV;
 901
 902	polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
 903
 904	switch (ctrl_type) {
 905	default:
 906	case COEX_SWITCH_CTRL_BY_BBSW:
 907		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
 908		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
 909		/* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
 910		rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
 911				DPDT_CTRL_PIN);
 912
 913		if (pos_type == COEX_SWITCH_TO_WLG_BT) {
 914			if (coex_rfe->rfe_module_type != 0x4 &&
 915			    coex_rfe->rfe_module_type != 0x2)
 916				regval = 0x3;
 917			else
 918				regval = (!polarity_inverse ? 0x2 : 0x1);
 919		} else if (pos_type == COEX_SWITCH_TO_WLG) {
 920			regval = (!polarity_inverse ? 0x2 : 0x1);
 921		} else {
 922			regval = (!polarity_inverse ? 0x1 : 0x2);
 923		}
 924
 925		rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
 926				 regval);
 927		break;
 928	case COEX_SWITCH_CTRL_BY_PTA:
 929		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
 930		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
 931		/* PTA,  DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
 932		rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
 933				PTA_CTRL_PIN);
 934
 935		regval = (!polarity_inverse ? 0x2 : 0x1);
 936		rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
 937				 regval);
 938		break;
 939	case COEX_SWITCH_CTRL_BY_ANTDIV:
 940		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
 941		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
 942		rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
 943				ANTDIC_CTRL_PIN);
 944		break;
 945	case COEX_SWITCH_CTRL_BY_MAC:
 946		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
 947
 948		regval = (!polarity_inverse ? 0x0 : 0x1);
 949		rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA,
 950				regval);
 951		break;
 952	case COEX_SWITCH_CTRL_BY_FW:
 953		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
 954		rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
 955		break;
 956	case COEX_SWITCH_CTRL_BY_BT:
 957		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
 958		rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
 959		break;
 960	}
 961
 962	if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) {
 963		rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
 964		rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
 965	} else {
 966		rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
 967		rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
 968	}
 969}
 970
 971static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
 972{}
 973
 974static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
 975{
 976	rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN);
 977	rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN);
 978	rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN);
 979	rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS);
 980	rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT);
 981	rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT);
 982}
 983
 984static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
 985{
 986	struct rtw_coex *coex = &rtwdev->coex;
 987	struct rtw_coex_rfe *coex_rfe = &coex->rfe;
 988	struct rtw_efuse *efuse = &rtwdev->efuse;
 989
 990	coex_rfe->rfe_module_type = efuse->rfe_option;
 991	coex_rfe->ant_switch_polarity = 0;
 992	coex_rfe->ant_switch_exist = true;
 993	coex_rfe->wlg_at_btg = false;
 994
 995	switch (coex_rfe->rfe_module_type) {
 996	case 0:
 997	case 8:
 998	case 1:
 999	case 9:  /* 1-Ant, Main, WLG */
1000	default: /* 2-Ant, DPDT, WLG */
1001		break;
1002	case 2:
1003	case 10: /* 1-Ant, Main, BTG */
1004	case 7:
1005	case 15: /* 2-Ant, DPDT, BTG */
1006		coex_rfe->wlg_at_btg = true;
1007		break;
1008	case 3:
1009	case 11: /* 1-Ant, Aux, WLG */
1010		coex_rfe->ant_switch_polarity = 1;
1011		break;
1012	case 4:
1013	case 12: /* 1-Ant, Aux, BTG */
1014		coex_rfe->wlg_at_btg = true;
1015		coex_rfe->ant_switch_polarity = 1;
1016		break;
1017	case 5:
1018	case 13: /* 2-Ant, no switch, WLG */
1019	case 6:
1020	case 14: /* 2-Ant, no antenna switch, WLG */
1021		coex_rfe->ant_switch_exist = false;
1022		break;
1023	}
1024}
1025
1026static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
1027{
1028	struct rtw_coex *coex = &rtwdev->coex;
1029	struct rtw_coex_dm *coex_dm = &coex->dm;
1030	struct rtw_efuse *efuse = &rtwdev->efuse;
1031	bool share_ant = efuse->share_ant;
1032
1033	if (share_ant)
1034		return;
1035
1036	if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
1037		return;
1038
1039	coex_dm->cur_wl_pwr_lvl = wl_pwr;
1040}
1041
1042static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1043{}
1044
1045static void
1046rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
1047			    s8 pwr_idx_offset_lower,
1048			    s8 *txagc_idx, u8 *swing_idx)
1049{
1050	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1051	s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A];
1052	u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
1053	u8 swing_lower_bound = 0;
1054	u8 max_pwr_idx_offset = 0xf;
1055	s8 agc_index = 0;
1056	u8 swing_index = dm_info->default_ofdm_index;
1057
1058	pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset);
1059	pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15);
1060
1061	if (delta_pwr_idx >= 0) {
1062		if (delta_pwr_idx <= pwr_idx_offset) {
1063			agc_index = delta_pwr_idx;
1064			swing_index = dm_info->default_ofdm_index;
1065		} else if (delta_pwr_idx > pwr_idx_offset) {
1066			agc_index = pwr_idx_offset;
1067			swing_index = dm_info->default_ofdm_index +
1068					delta_pwr_idx - pwr_idx_offset;
1069			swing_index = min_t(u8, swing_index, swing_upper_bound);
1070		}
1071	} else if (delta_pwr_idx < 0) {
1072		if (delta_pwr_idx >= pwr_idx_offset_lower) {
1073			agc_index = delta_pwr_idx;
1074			swing_index = dm_info->default_ofdm_index;
1075		} else if (delta_pwr_idx < pwr_idx_offset_lower) {
1076			if (dm_info->default_ofdm_index >
1077				(pwr_idx_offset_lower - delta_pwr_idx))
1078				swing_index = dm_info->default_ofdm_index +
1079					delta_pwr_idx - pwr_idx_offset_lower;
1080			else
1081				swing_index = swing_lower_bound;
1082
1083			agc_index = pwr_idx_offset_lower;
1084		}
1085	}
1086
1087	if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) {
1088		rtw_warn(rtwdev, "swing index overflow\n");
1089		swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1;
1090	}
1091
1092	*txagc_idx = agc_index;
1093	*swing_idx = swing_index;
1094}
1095
1096static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
1097				      s8 pwr_idx_offset_lower)
1098{
1099	s8 txagc_idx;
1100	u8 swing_idx;
1101
1102	rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower,
1103				    &txagc_idx, &swing_idx);
1104	rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx);
1105	rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
1106			 rtw8821c_txscale_tbl[swing_idx]);
1107}
1108
1109static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev)
1110{
1111	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1112	u8 pwr_idx_offset, tx_pwr_idx;
1113	s8 pwr_idx_offset_lower;
1114	u8 channel = rtwdev->hal.current_channel;
1115	u8 band_width = rtwdev->hal.current_band_width;
1116	u8 regd = rtw_regd_get(rtwdev);
1117	u8 tx_rate = dm_info->tx_rate;
1118	u8 max_pwr_idx = rtwdev->chip->max_power_index;
1119
1120	tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate,
1121						band_width, channel, regd);
1122
1123	tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx);
1124
1125	pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1126	pwr_idx_offset_lower = 0 - tx_pwr_idx;
1127
1128	rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower);
1129}
1130
1131static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev)
1132{
1133	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1134	struct rtw_swing_table swing_table;
1135	u8 thermal_value, delta;
1136
1137	rtw_phy_config_swing_table(rtwdev, &swing_table);
1138
1139	if (rtwdev->efuse.thermal_meter[0] == 0xff)
1140		return;
1141
1142	thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1143
1144	rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1145
1146	if (dm_info->pwr_trk_init_trigger)
1147		dm_info->pwr_trk_init_trigger = false;
1148	else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1149						   RF_PATH_A))
1150		goto iqk;
1151
1152	delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1153
1154	delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);
1155
1156	dm_info->delta_power_index[RF_PATH_A] =
1157		rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A,
1158					    RF_PATH_A, delta);
1159	if (dm_info->delta_power_index[RF_PATH_A] ==
1160			dm_info->delta_power_index_last[RF_PATH_A])
1161		goto iqk;
1162	else
1163		dm_info->delta_power_index_last[RF_PATH_A] =
1164			dm_info->delta_power_index[RF_PATH_A];
1165	rtw8821c_pwrtrack_set(rtwdev);
1166
1167iqk:
1168	if (rtw_phy_pwrtrack_need_iqk(rtwdev))
1169		rtw8821c_do_iqk(rtwdev);
1170}
1171
1172static void rtw8821c_pwr_track(struct rtw_dev *rtwdev)
1173{
1174	struct rtw_efuse *efuse = &rtwdev->efuse;
1175	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1176
1177	if (efuse->power_track_type != 0)
1178		return;
1179
1180	if (!dm_info->pwr_trk_triggered) {
1181		rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1182			     GENMASK(17, 16), 0x03);
1183		dm_info->pwr_trk_triggered = true;
1184		return;
1185	}
1186
1187	rtw8821c_phy_pwrtrack(rtwdev);
1188	dm_info->pwr_trk_triggered = false;
1189}
1190
1191static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev,
1192				       struct rtw_vif *vif,
1193				       struct rtw_bfee *bfee, bool enable)
1194{
1195	if (enable)
1196		rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
1197	else
1198		rtw_bf_remove_bfee_su(rtwdev, bfee);
1199}
1200
1201static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
1202				       struct rtw_vif *vif,
1203				       struct rtw_bfee *bfee, bool enable)
1204{
1205	if (enable)
1206		rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
1207	else
1208		rtw_bf_remove_bfee_mu(rtwdev, bfee);
1209}
1210
1211static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
1212				    struct rtw_bfee *bfee, bool enable)
1213{
1214	if (bfee->role == RTW_BFEE_SU)
1215		rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
1216	else if (bfee->role == RTW_BFEE_MU)
1217		rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
1218	else
1219		rtw_warn(rtwdev, "wrong bfee role\n");
1220}
1221
1222static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1223{
1224	struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1225	u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13};
1226	u8 cck_n_rx;
1227
1228	rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
1229		dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
1230
1231	if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
1232		return;
1233
1234	cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) &&
1235		    rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1;
1236	rtw_dbg(rtwdev, RTW_DBG_PHY,
1237		"is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n",
1238		rtw_is_assoc(rtwdev), new_lvl, cck_n_rx,
1239		dm_info->cck_pd_default + new_lvl * 2,
1240		pd[new_lvl], dm_info->cck_fa_avg);
1241
1242	dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1243
1244	dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1245	rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1246	rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1247			 dm_info->cck_pd_default + new_lvl * 2);
1248}
1249
1250static void rtw8821c_fill_txdesc_checksum(struct rtw_dev *rtwdev,
1251					  struct rtw_tx_pkt_info *pkt_info,
1252					  u8 *txdesc)
1253{
1254	fill_txdesc_checksum_common(txdesc, 16);
1255}
1256
1257static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = {
1258	{0x0086,
1259	 RTW_PWR_CUT_ALL_MSK,
1260	 RTW_PWR_INTF_SDIO_MSK,
1261	 RTW_PWR_ADDR_SDIO,
1262	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1263	{0x0086,
1264	 RTW_PWR_CUT_ALL_MSK,
1265	 RTW_PWR_INTF_SDIO_MSK,
1266	 RTW_PWR_ADDR_SDIO,
1267	 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1268	{0x004A,
1269	 RTW_PWR_CUT_ALL_MSK,
1270	 RTW_PWR_INTF_USB_MSK,
1271	 RTW_PWR_ADDR_MAC,
1272	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1273	{0x0005,
1274	 RTW_PWR_CUT_ALL_MSK,
1275	 RTW_PWR_INTF_ALL_MSK,
1276	 RTW_PWR_ADDR_MAC,
1277	 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1278	{0x0300,
1279	 RTW_PWR_CUT_ALL_MSK,
1280	 RTW_PWR_INTF_PCI_MSK,
1281	 RTW_PWR_ADDR_MAC,
1282	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1283	{0x0301,
1284	 RTW_PWR_CUT_ALL_MSK,
1285	 RTW_PWR_INTF_PCI_MSK,
1286	 RTW_PWR_ADDR_MAC,
1287	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1288	{0xFFFF,
1289	 RTW_PWR_CUT_ALL_MSK,
1290	 RTW_PWR_INTF_ALL_MSK,
1291	 0,
1292	 RTW_PWR_CMD_END, 0, 0},
1293};
1294
1295static struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = {
1296	{0x0020,
1297	 RTW_PWR_CUT_ALL_MSK,
1298	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1299	 RTW_PWR_ADDR_MAC,
1300	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1301	{0x0001,
1302	 RTW_PWR_CUT_ALL_MSK,
1303	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1304	 RTW_PWR_ADDR_MAC,
1305	 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
1306	{0x0000,
1307	 RTW_PWR_CUT_ALL_MSK,
1308	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1309	 RTW_PWR_ADDR_MAC,
1310	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1311	{0x0005,
1312	 RTW_PWR_CUT_ALL_MSK,
1313	 RTW_PWR_INTF_ALL_MSK,
1314	 RTW_PWR_ADDR_MAC,
1315	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1316	{0x0075,
1317	 RTW_PWR_CUT_ALL_MSK,
1318	 RTW_PWR_INTF_PCI_MSK,
1319	 RTW_PWR_ADDR_MAC,
1320	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1321	{0x0006,
1322	 RTW_PWR_CUT_ALL_MSK,
1323	 RTW_PWR_INTF_ALL_MSK,
1324	 RTW_PWR_ADDR_MAC,
1325	 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1326	{0x0075,
1327	 RTW_PWR_CUT_ALL_MSK,
1328	 RTW_PWR_INTF_PCI_MSK,
1329	 RTW_PWR_ADDR_MAC,
1330	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1331	{0x0006,
1332	 RTW_PWR_CUT_ALL_MSK,
1333	 RTW_PWR_INTF_ALL_MSK,
1334	 RTW_PWR_ADDR_MAC,
1335	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1336	{0x0005,
1337	 RTW_PWR_CUT_ALL_MSK,
1338	 RTW_PWR_INTF_ALL_MSK,
1339	 RTW_PWR_ADDR_MAC,
1340	 RTW_PWR_CMD_WRITE, BIT(7), 0},
1341	{0x0005,
1342	 RTW_PWR_CUT_ALL_MSK,
1343	 RTW_PWR_INTF_ALL_MSK,
1344	 RTW_PWR_ADDR_MAC,
1345	 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1346	{0x10C3,
1347	 RTW_PWR_CUT_ALL_MSK,
1348	 RTW_PWR_INTF_USB_MSK,
1349	 RTW_PWR_ADDR_MAC,
1350	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1351	{0x0005,
1352	 RTW_PWR_CUT_ALL_MSK,
1353	 RTW_PWR_INTF_ALL_MSK,
1354	 RTW_PWR_ADDR_MAC,
1355	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1356	{0x0005,
1357	 RTW_PWR_CUT_ALL_MSK,
1358	 RTW_PWR_INTF_ALL_MSK,
1359	 RTW_PWR_ADDR_MAC,
1360	 RTW_PWR_CMD_POLLING, BIT(0), 0},
1361	{0x0020,
1362	 RTW_PWR_CUT_ALL_MSK,
1363	 RTW_PWR_INTF_ALL_MSK,
1364	 RTW_PWR_ADDR_MAC,
1365	 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1366	{0x0074,
1367	 RTW_PWR_CUT_ALL_MSK,
1368	 RTW_PWR_INTF_PCI_MSK,
1369	 RTW_PWR_ADDR_MAC,
1370	 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1371	{0x0022,
1372	 RTW_PWR_CUT_ALL_MSK,
1373	 RTW_PWR_INTF_PCI_MSK,
1374	 RTW_PWR_ADDR_MAC,
1375	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1376	{0x0062,
1377	 RTW_PWR_CUT_ALL_MSK,
1378	 RTW_PWR_INTF_PCI_MSK,
1379	 RTW_PWR_ADDR_MAC,
1380	 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1381	 (BIT(7) | BIT(6) | BIT(5))},
1382	{0x0061,
1383	 RTW_PWR_CUT_ALL_MSK,
1384	 RTW_PWR_INTF_PCI_MSK,
1385	 RTW_PWR_ADDR_MAC,
1386	 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1387	{0x007C,
1388	 RTW_PWR_CUT_ALL_MSK,
1389	 RTW_PWR_INTF_ALL_MSK,
1390	 RTW_PWR_ADDR_MAC,
1391	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1392	{0xFFFF,
1393	 RTW_PWR_CUT_ALL_MSK,
1394	 RTW_PWR_INTF_ALL_MSK,
1395	 0,
1396	 RTW_PWR_CMD_END, 0, 0},
1397};
1398
1399static struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = {
1400	{0x0093,
1401	 RTW_PWR_CUT_ALL_MSK,
1402	 RTW_PWR_INTF_ALL_MSK,
1403	 RTW_PWR_ADDR_MAC,
1404	 RTW_PWR_CMD_WRITE, BIT(3), 0},
1405	{0x001F,
1406	 RTW_PWR_CUT_ALL_MSK,
1407	 RTW_PWR_INTF_ALL_MSK,
1408	 RTW_PWR_ADDR_MAC,
1409	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1410	{0x0049,
1411	 RTW_PWR_CUT_ALL_MSK,
1412	 RTW_PWR_INTF_ALL_MSK,
1413	 RTW_PWR_ADDR_MAC,
1414	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1415	{0x0006,
1416	 RTW_PWR_CUT_ALL_MSK,
1417	 RTW_PWR_INTF_ALL_MSK,
1418	 RTW_PWR_ADDR_MAC,
1419	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1420	{0x0002,
1421	 RTW_PWR_CUT_ALL_MSK,
1422	 RTW_PWR_INTF_ALL_MSK,
1423	 RTW_PWR_ADDR_MAC,
1424	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1425	{0x10C3,
1426	 RTW_PWR_CUT_ALL_MSK,
1427	 RTW_PWR_INTF_USB_MSK,
1428	 RTW_PWR_ADDR_MAC,
1429	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1430	{0x0005,
1431	 RTW_PWR_CUT_ALL_MSK,
1432	 RTW_PWR_INTF_ALL_MSK,
1433	 RTW_PWR_ADDR_MAC,
1434	 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1435	{0x0005,
1436	 RTW_PWR_CUT_ALL_MSK,
1437	 RTW_PWR_INTF_ALL_MSK,
1438	 RTW_PWR_ADDR_MAC,
1439	 RTW_PWR_CMD_POLLING, BIT(1), 0},
1440	{0x0020,
1441	 RTW_PWR_CUT_ALL_MSK,
1442	 RTW_PWR_INTF_ALL_MSK,
1443	 RTW_PWR_ADDR_MAC,
1444	 RTW_PWR_CMD_WRITE, BIT(3), 0},
1445	{0x0000,
1446	 RTW_PWR_CUT_ALL_MSK,
1447	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1448	 RTW_PWR_ADDR_MAC,
1449	 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1450	{0xFFFF,
1451	 RTW_PWR_CUT_ALL_MSK,
1452	 RTW_PWR_INTF_ALL_MSK,
1453	 0,
1454	 RTW_PWR_CMD_END, 0, 0},
1455};
1456
1457static struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = {
1458	{0x0007,
1459	 RTW_PWR_CUT_ALL_MSK,
1460	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1461	 RTW_PWR_ADDR_MAC,
1462	 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1463	{0x0067,
1464	 RTW_PWR_CUT_ALL_MSK,
1465	 RTW_PWR_INTF_ALL_MSK,
1466	 RTW_PWR_ADDR_MAC,
1467	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1468	{0x0005,
1469	 RTW_PWR_CUT_ALL_MSK,
1470	 RTW_PWR_INTF_PCI_MSK,
1471	 RTW_PWR_ADDR_MAC,
1472	 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1473	{0x004A,
1474	 RTW_PWR_CUT_ALL_MSK,
1475	 RTW_PWR_INTF_USB_MSK,
1476	 RTW_PWR_ADDR_MAC,
1477	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1478	{0x0067,
1479	 RTW_PWR_CUT_ALL_MSK,
1480	 RTW_PWR_INTF_SDIO_MSK,
1481	 RTW_PWR_ADDR_MAC,
1482	 RTW_PWR_CMD_WRITE, BIT(5), 0},
1483	{0x0067,
1484	 RTW_PWR_CUT_ALL_MSK,
1485	 RTW_PWR_INTF_SDIO_MSK,
1486	 RTW_PWR_ADDR_MAC,
1487	 RTW_PWR_CMD_WRITE, BIT(4), 0},
1488	{0x004F,
1489	 RTW_PWR_CUT_ALL_MSK,
1490	 RTW_PWR_INTF_SDIO_MSK,
1491	 RTW_PWR_ADDR_MAC,
1492	 RTW_PWR_CMD_WRITE, BIT(0), 0},
1493	{0x0067,
1494	 RTW_PWR_CUT_ALL_MSK,
1495	 RTW_PWR_INTF_SDIO_MSK,
1496	 RTW_PWR_ADDR_MAC,
1497	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1498	{0x0046,
1499	 RTW_PWR_CUT_ALL_MSK,
1500	 RTW_PWR_INTF_SDIO_MSK,
1501	 RTW_PWR_ADDR_MAC,
1502	 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1503	{0x0067,
1504	 RTW_PWR_CUT_ALL_MSK,
1505	 RTW_PWR_INTF_SDIO_MSK,
1506	 RTW_PWR_ADDR_MAC,
1507	 RTW_PWR_CMD_WRITE, BIT(2), 0},
1508	{0x0046,
1509	 RTW_PWR_CUT_ALL_MSK,
1510	 RTW_PWR_INTF_SDIO_MSK,
1511	 RTW_PWR_ADDR_MAC,
1512	 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1513	{0x0062,
1514	 RTW_PWR_CUT_ALL_MSK,
1515	 RTW_PWR_INTF_SDIO_MSK,
1516	 RTW_PWR_ADDR_MAC,
1517	 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1518	{0x0081,
1519	 RTW_PWR_CUT_ALL_MSK,
1520	 RTW_PWR_INTF_ALL_MSK,
1521	 RTW_PWR_ADDR_MAC,
1522	 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1523	{0x0005,
1524	 RTW_PWR_CUT_ALL_MSK,
1525	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1526	 RTW_PWR_ADDR_MAC,
1527	 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1528	{0x0086,
1529	 RTW_PWR_CUT_ALL_MSK,
1530	 RTW_PWR_INTF_SDIO_MSK,
1531	 RTW_PWR_ADDR_SDIO,
1532	 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1533	{0x0086,
1534	 RTW_PWR_CUT_ALL_MSK,
1535	 RTW_PWR_INTF_SDIO_MSK,
1536	 RTW_PWR_ADDR_SDIO,
1537	 RTW_PWR_CMD_POLLING, BIT(1), 0},
1538	{0x0090,
1539	 RTW_PWR_CUT_ALL_MSK,
1540	 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK,
1541	 RTW_PWR_ADDR_MAC,
1542	 RTW_PWR_CMD_WRITE, BIT(1), 0},
1543	{0x0044,
1544	 RTW_PWR_CUT_ALL_MSK,
1545	 RTW_PWR_INTF_SDIO_MSK,
1546	 RTW_PWR_ADDR_SDIO,
1547	 RTW_PWR_CMD_WRITE, 0xFF, 0},
1548	{0x0040,
1549	 RTW_PWR_CUT_ALL_MSK,
1550	 RTW_PWR_INTF_SDIO_MSK,
1551	 RTW_PWR_ADDR_SDIO,
1552	 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1553	{0x0041,
1554	 RTW_PWR_CUT_ALL_MSK,
1555	 RTW_PWR_INTF_SDIO_MSK,
1556	 RTW_PWR_ADDR_SDIO,
1557	 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1558	{0x0042,
1559	 RTW_PWR_CUT_ALL_MSK,
1560	 RTW_PWR_INTF_SDIO_MSK,
1561	 RTW_PWR_ADDR_SDIO,
1562	 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1563	{0xFFFF,
1564	 RTW_PWR_CUT_ALL_MSK,
1565	 RTW_PWR_INTF_ALL_MSK,
1566	 0,
1567	 RTW_PWR_CMD_END, 0, 0},
1568};
1569
1570static const struct rtw_pwr_seq_cmd *card_enable_flow_8821c[] = {
1571	trans_carddis_to_cardemu_8821c,
1572	trans_cardemu_to_act_8821c,
1573	NULL
1574};
1575
1576static const struct rtw_pwr_seq_cmd *card_disable_flow_8821c[] = {
1577	trans_act_to_cardemu_8821c,
1578	trans_cardemu_to_carddis_8821c,
1579	NULL
1580};
1581
1582static const struct rtw_intf_phy_para usb2_param_8821c[] = {
1583	{0xFFFF, 0x00,
1584	 RTW_IP_SEL_PHY,
1585	 RTW_INTF_PHY_CUT_ALL,
1586	 RTW_INTF_PHY_PLATFORM_ALL},
1587};
1588
1589static const struct rtw_intf_phy_para usb3_param_8821c[] = {
1590	{0xFFFF, 0x0000,
1591	 RTW_IP_SEL_PHY,
1592	 RTW_INTF_PHY_CUT_ALL,
1593	 RTW_INTF_PHY_PLATFORM_ALL},
1594};
1595
1596static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = {
1597	{0x0009, 0x6380,
1598	 RTW_IP_SEL_PHY,
1599	 RTW_INTF_PHY_CUT_ALL,
1600	 RTW_INTF_PHY_PLATFORM_ALL},
1601	{0xFFFF, 0x0000,
1602	 RTW_IP_SEL_PHY,
1603	 RTW_INTF_PHY_CUT_ALL,
1604	 RTW_INTF_PHY_PLATFORM_ALL},
1605};
1606
1607static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = {
1608	{0xFFFF, 0x0000,
1609	 RTW_IP_SEL_PHY,
1610	 RTW_INTF_PHY_CUT_ALL,
1611	 RTW_INTF_PHY_PLATFORM_ALL},
1612};
1613
1614static const struct rtw_intf_phy_para_table phy_para_table_8821c = {
1615	.usb2_para	= usb2_param_8821c,
1616	.usb3_para	= usb3_param_8821c,
1617	.gen1_para	= pcie_gen1_param_8821c,
1618	.gen2_para	= pcie_gen2_param_8821c,
1619	.n_usb2_para	= ARRAY_SIZE(usb2_param_8821c),
1620	.n_usb3_para	= ARRAY_SIZE(usb2_param_8821c),
1621	.n_gen1_para	= ARRAY_SIZE(pcie_gen1_param_8821c),
1622	.n_gen2_para	= ARRAY_SIZE(pcie_gen2_param_8821c),
1623};
1624
1625static const struct rtw_rfe_def rtw8821c_rfe_defs[] = {
1626	[0] = RTW_DEF_RFE(8821c, 0, 0),
1627	[2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1628	[4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1629	[6] = RTW_DEF_RFE(8821c, 0, 0),
1630};
1631
1632static struct rtw_hw_reg rtw8821c_dig[] = {
1633	[0] = { .addr = 0xc50, .mask = 0x7f },
1634};
1635
1636static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = {
1637	.ctrl = LTECOEX_ACCESS_CTRL,
1638	.wdata = LTECOEX_WRITE_DATA,
1639	.rdata = LTECOEX_READ_DATA,
1640};
1641
1642static struct rtw_page_table page_table_8821c[] = {
1643	/* not sure what [0] stands for */
1644	{16, 16, 16, 14, 1},
1645	{16, 16, 16, 14, 1},
1646	{16, 16, 0, 0, 1},
1647	{16, 16, 16, 0, 1},
1648	{16, 16, 16, 14, 1},
1649};
1650
1651static struct rtw_rqpn rqpn_table_8821c[] = {
1652	/* not sure what [0] stands for */
1653	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1654	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1655	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1656	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1657	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1658	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1659	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1660	 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
1661	 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1662	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1663	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1664	 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1665	{RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1666	 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1667	 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1668};
1669
1670static struct rtw_prioq_addrs prioq_addrs_8821c = {
1671	.prio[RTW_DMA_MAPPING_EXTRA] = {
1672		.rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
1673	},
1674	.prio[RTW_DMA_MAPPING_LOW] = {
1675		.rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
1676	},
1677	.prio[RTW_DMA_MAPPING_NORMAL] = {
1678		.rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
1679	},
1680	.prio[RTW_DMA_MAPPING_HIGH] = {
1681		.rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
1682	},
1683	.wsize = true,
1684};
1685
1686static struct rtw_chip_ops rtw8821c_ops = {
 
 
1687	.phy_set_param		= rtw8821c_phy_set_param,
1688	.read_efuse		= rtw8821c_read_efuse,
1689	.query_rx_desc		= rtw8821c_query_rx_desc,
1690	.set_channel		= rtw8821c_set_channel,
1691	.mac_init		= rtw8821c_mac_init,
1692	.read_rf		= rtw_phy_read_rf,
1693	.write_rf		= rtw_phy_write_rf_reg_sipi,
1694	.set_antenna		= NULL,
1695	.set_tx_power_index	= rtw8821c_set_tx_power_index,
1696	.cfg_ldo25		= rtw8821c_cfg_ldo25,
1697	.false_alarm_statistics	= rtw8821c_false_alarm_statistics,
1698	.phy_calibration	= rtw8821c_phy_calibration,
1699	.cck_pd_set		= rtw8821c_phy_cck_pd_set,
1700	.pwr_track		= rtw8821c_pwr_track,
1701	.config_bfee		= rtw8821c_bf_config_bfee,
1702	.set_gid_table		= rtw_bf_set_gid_table,
1703	.cfg_csi_rate		= rtw_bf_cfg_csi_rate,
1704	.fill_txdesc_checksum	= rtw8821c_fill_txdesc_checksum,
1705
1706	.coex_set_init		= rtw8821c_coex_cfg_init,
1707	.coex_set_ant_switch	= rtw8821c_coex_cfg_ant_switch,
1708	.coex_set_gnt_fix	= rtw8821c_coex_cfg_gnt_fix,
1709	.coex_set_gnt_debug	= rtw8821c_coex_cfg_gnt_debug,
1710	.coex_set_rfe_type	= rtw8821c_coex_cfg_rfe_type,
1711	.coex_set_wl_tx_power	= rtw8821c_coex_cfg_wl_tx_power,
1712	.coex_set_wl_rx_gain	= rtw8821c_coex_cfg_wl_rx_gain,
1713};
1714
1715/* rssi in percentage % (dbm = % - 100) */
1716static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40};
1717static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101};
1718
1719/* Shared-Antenna Coex Table */
1720static const struct coex_table_para table_sant_8821c[] = {
1721	{0x55555555, 0x55555555}, /* case-0 */
1722	{0x55555555, 0x55555555},
1723	{0x66555555, 0x66555555},
1724	{0xaaaaaaaa, 0xaaaaaaaa},
1725	{0x5a5a5a5a, 0x5a5a5a5a},
1726	{0xfafafafa, 0xfafafafa}, /* case-5 */
1727	{0x6a5a5555, 0xaaaaaaaa},
1728	{0x6a5a56aa, 0x6a5a56aa},
1729	{0x6a5a5a5a, 0x6a5a5a5a},
1730	{0x66555555, 0x5a5a5a5a},
1731	{0x66555555, 0x6a5a5a5a}, /* case-10 */
1732	{0x66555555, 0xaaaaaaaa},
1733	{0x66555555, 0x6a5a5aaa},
1734	{0x66555555, 0x6aaa6aaa},
1735	{0x66555555, 0x6a5a5aaa},
1736	{0x66555555, 0xaaaaaaaa}, /* case-15 */
1737	{0xffff55ff, 0xfafafafa},
1738	{0xffff55ff, 0x6afa5afa},
1739	{0xaaffffaa, 0xfafafafa},
1740	{0xaa5555aa, 0x5a5a5a5a},
1741	{0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1742	{0xaa5555aa, 0xaaaaaaaa},
1743	{0xffffffff, 0x55555555},
1744	{0xffffffff, 0x5a5a5a5a},
1745	{0xffffffff, 0x5a5a5a5a},
1746	{0xffffffff, 0x5a5a5aaa}, /* case-25 */
1747	{0x55555555, 0x5a5a5a5a},
1748	{0x55555555, 0xaaaaaaaa},
1749	{0x66555555, 0x6a5a6a5a},
1750	{0x66556655, 0x66556655},
1751	{0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1752	{0xffffffff, 0x5aaa5aaa},
1753	{0x56555555, 0x5a5a5aaa}
1754};
1755
1756/* Non-Shared-Antenna Coex Table */
1757static const struct coex_table_para table_nsant_8821c[] = {
1758	{0xffffffff, 0xffffffff}, /* case-100 */
1759	{0xffff55ff, 0xfafafafa},
1760	{0x66555555, 0x66555555},
1761	{0xaaaaaaaa, 0xaaaaaaaa},
1762	{0x5a5a5a5a, 0x5a5a5a5a},
1763	{0xffffffff, 0xffffffff}, /* case-105 */
1764	{0x5afa5afa, 0x5afa5afa},
1765	{0x55555555, 0xfafafafa},
1766	{0x66555555, 0xfafafafa},
1767	{0x66555555, 0x5a5a5a5a},
1768	{0x66555555, 0x6a5a5a5a}, /* case-110 */
1769	{0x66555555, 0xaaaaaaaa},
1770	{0xffff55ff, 0xfafafafa},
1771	{0xffff55ff, 0x5afa5afa},
1772	{0xffff55ff, 0xaaaaaaaa},
1773	{0xffff55ff, 0xffff55ff}, /* case-115 */
1774	{0xaaffffaa, 0x5afa5afa},
1775	{0xaaffffaa, 0xaaaaaaaa},
1776	{0xffffffff, 0xfafafafa},
1777	{0xffff55ff, 0xfafafafa},
1778	{0xffffffff, 0xaaaaaaaa}, /* case-120 */
1779	{0xffff55ff, 0x5afa5afa},
1780	{0xffff55ff, 0x5afa5afa},
1781	{0x55ff55ff, 0x55ff55ff}
1782};
1783
1784/* Shared-Antenna TDMA */
1785static const struct coex_tdma_para tdma_sant_8821c[] = {
1786	{ {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1787	{ {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1788	{ {0x61, 0x3a, 0x03, 0x11, 0x11} },
1789	{ {0x61, 0x35, 0x03, 0x11, 0x11} },
1790	{ {0x61, 0x20, 0x03, 0x11, 0x11} },
1791	{ {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1792	{ {0x61, 0x45, 0x03, 0x11, 0x10} },
1793	{ {0x61, 0x35, 0x03, 0x11, 0x10} },
1794	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1795	{ {0x61, 0x20, 0x03, 0x11, 0x10} },
1796	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1797	{ {0x61, 0x08, 0x03, 0x11, 0x15} },
1798	{ {0x61, 0x08, 0x03, 0x10, 0x14} },
1799	{ {0x51, 0x08, 0x03, 0x10, 0x54} },
1800	{ {0x51, 0x08, 0x03, 0x10, 0x55} },
1801	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1802	{ {0x51, 0x45, 0x03, 0x10, 0x50} },
1803	{ {0x51, 0x3a, 0x03, 0x11, 0x50} },
1804	{ {0x51, 0x30, 0x03, 0x10, 0x50} },
1805	{ {0x51, 0x21, 0x03, 0x10, 0x50} },
1806	{ {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1807	{ {0x51, 0x4a, 0x03, 0x10, 0x50} },
1808	{ {0x51, 0x08, 0x03, 0x30, 0x54} },
1809	{ {0x55, 0x08, 0x03, 0x10, 0x54} },
1810	{ {0x65, 0x10, 0x03, 0x11, 0x10} },
1811	{ {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1812	{ {0x51, 0x21, 0x03, 0x10, 0x50} },
1813	{ {0x61, 0x08, 0x03, 0x11, 0x11} }
1814};
1815
1816/* Non-Shared-Antenna TDMA */
1817static const struct coex_tdma_para tdma_nsant_8821c[] = {
1818	{ {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1819	{ {0x61, 0x45, 0x03, 0x11, 0x11} },
1820	{ {0x61, 0x25, 0x03, 0x11, 0x11} },
1821	{ {0x61, 0x35, 0x03, 0x11, 0x11} },
1822	{ {0x61, 0x20, 0x03, 0x11, 0x11} },
1823	{ {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1824	{ {0x61, 0x45, 0x03, 0x11, 0x10} },
1825	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1826	{ {0x61, 0x30, 0x03, 0x11, 0x10} },
1827	{ {0x61, 0x20, 0x03, 0x11, 0x10} },
1828	{ {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1829	{ {0x61, 0x10, 0x03, 0x11, 0x11} },
1830	{ {0x61, 0x08, 0x03, 0x10, 0x14} },
1831	{ {0x51, 0x08, 0x03, 0x10, 0x54} },
1832	{ {0x51, 0x08, 0x03, 0x10, 0x55} },
1833	{ {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1834	{ {0x51, 0x45, 0x03, 0x10, 0x50} },
1835	{ {0x51, 0x3a, 0x03, 0x10, 0x50} },
1836	{ {0x51, 0x30, 0x03, 0x10, 0x50} },
1837	{ {0x51, 0x21, 0x03, 0x10, 0x50} },
1838	{ {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1839	{ {0x51, 0x10, 0x03, 0x10, 0x50} }
1840};
1841
1842static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} };
1843
1844/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
1845static const struct coex_rf_para rf_para_tx_8821c[] = {
1846	{0, 0, false, 7},  /* for normal */
1847	{0, 20, false, 7}, /* for WL-CPT */
1848	{8, 17, true, 4},
1849	{7, 18, true, 4},
1850	{6, 19, true, 4},
1851	{5, 20, true, 4}
1852};
1853
1854static const struct coex_rf_para rf_para_rx_8821c[] = {
1855	{0, 0, false, 7},  /* for normal */
1856	{0, 20, false, 7}, /* for WL-CPT */
1857	{3, 24, true, 5},
1858	{2, 26, true, 5},
1859	{1, 27, true, 5},
1860	{0, 28, true, 5}
1861};
1862
1863static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c));
1864
1865static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = {
1866	{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1867	 11, 11, 12, 12, 12, 12, 12},
1868	{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1869	 11, 12, 12, 12, 12, 12, 12, 12},
1870	{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1871	 11, 12, 12, 12, 12, 12, 12},
1872};
1873
1874static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = {
1875	{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1876	 12, 12, 12, 12, 12, 12, 12},
1877	{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1878	 12, 12, 12, 12, 12, 12, 12, 12},
1879	{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1880	 11, 12, 12, 12, 12, 12, 12, 12},
1881};
1882
1883static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = {
1884	{0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1885	 11, 11, 12, 12, 12, 12, 12},
1886	{0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1887	 11, 12, 12, 12, 12, 12, 12, 12},
1888	{0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1889	 11, 12, 12, 12, 12, 12, 12},
1890};
1891
1892static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = {
1893	{0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1894	 12, 12, 12, 12, 12, 12, 12},
1895	{0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1896	 12, 12, 12, 12, 12, 12, 12, 12},
1897	{0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1898	 11, 12, 12, 12, 12, 12, 12, 12},
1899};
1900
1901static const u8 rtw8821c_pwrtrk_2gb_n[] = {
1902	0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1903	4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
1904};
1905
1906static const u8 rtw8821c_pwrtrk_2gb_p[] = {
1907	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1908	5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
1909};
1910
1911static const u8 rtw8821c_pwrtrk_2ga_n[] = {
1912	0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1913	4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
1914};
1915
1916static const u8 rtw8821c_pwrtrk_2ga_p[] = {
1917	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1918	5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
1919};
1920
1921static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = {
1922	0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1923	4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
1924};
1925
1926static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = {
1927	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1928	5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
1929};
1930
1931static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = {
1932	0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1933	4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
1934};
1935
1936static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = {
1937	0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1938	5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
1939};
1940
1941static const struct rtw_pwr_track_tbl rtw8821c_rtw_pwr_track_tbl = {
1942	.pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0],
1943	.pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1],
1944	.pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2],
1945	.pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0],
1946	.pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1],
1947	.pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2],
1948	.pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0],
1949	.pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1],
1950	.pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2],
1951	.pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0],
1952	.pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1],
1953	.pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2],
1954	.pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n,
1955	.pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p,
1956	.pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n,
1957	.pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p,
1958	.pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n,
1959	.pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p,
1960	.pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n,
1961	.pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p,
1962};
1963
 
 
 
 
 
 
 
1964static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = {
1965	{0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1966	{0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1967	{0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1968	{0, 0, RTW_REG_DOMAIN_NL},
1969	{0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1970	{0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1971	{0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1972	{0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1973	{0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1974	{0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1975	{0, 0, RTW_REG_DOMAIN_NL},
1976	{0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1977	{0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1978	{0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1979	{0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1980	{0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A},
1981	{0, 0, RTW_REG_DOMAIN_NL},
1982	{0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1983	{0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1984	{0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1985	{0xc50,  MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1986	{0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1987};
1988
1989const struct rtw_chip_info rtw8821c_hw_spec = {
1990	.ops = &rtw8821c_ops,
1991	.id = RTW_CHIP_TYPE_8821C,
1992	.fw_name = "rtw88/rtw8821c_fw.bin",
1993	.wlan_cpu = RTW_WCPU_11AC,
1994	.tx_pkt_desc_sz = 48,
1995	.tx_buf_desc_sz = 16,
1996	.rx_pkt_desc_sz = 24,
1997	.rx_buf_desc_sz = 8,
1998	.phy_efuse_size = 512,
1999	.log_efuse_size = 512,
2000	.ptct_efuse_size = 96,
2001	.txff_size = 65536,
2002	.rxff_size = 16384,
2003	.rsvd_drv_pg_num = 8,
2004	.txgi_factor = 1,
2005	.is_pwr_by_rate_dec = true,
2006	.max_power_index = 0x3f,
2007	.csi_buf_pg_num = 0,
2008	.band = RTW_BAND_2G | RTW_BAND_5G,
2009	.page_size = TX_PAGE_SIZE,
2010	.dig_min = 0x1c,
 
 
 
 
2011	.ht_supported = true,
2012	.vht_supported = true,
2013	.lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
2014	.sys_func_en = 0xD8,
2015	.pwr_on_seq = card_enable_flow_8821c,
2016	.pwr_off_seq = card_disable_flow_8821c,
2017	.page_table = page_table_8821c,
2018	.rqpn_table = rqpn_table_8821c,
2019	.prioq_addrs = &prioq_addrs_8821c,
2020	.intf_table = &phy_para_table_8821c,
2021	.dig = rtw8821c_dig,
2022	.rf_base_addr = {0x2800, 0x2c00},
2023	.rf_sipi_addr = {0xc90, 0xe90},
2024	.ltecoex_addr = &rtw8821c_ltecoex_addr,
2025	.mac_tbl = &rtw8821c_mac_tbl,
2026	.agc_tbl = &rtw8821c_agc_tbl,
2027	.bb_tbl = &rtw8821c_bb_tbl,
2028	.rf_tbl = {&rtw8821c_rf_a_tbl},
2029	.rfe_defs = rtw8821c_rfe_defs,
2030	.rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs),
2031	.rx_ldpc = false,
2032	.pwr_track_tbl = &rtw8821c_rtw_pwr_track_tbl,
2033	.iqk_threshold = 8,
2034	.bfer_su_max_num = 2,
2035	.bfer_mu_max_num = 1,
2036	.ampdu_density = IEEE80211_HT_MPDU_DENSITY_2,
2037	.max_scan_ie_len = IEEE80211_MAX_DATA_LEN,
2038
2039	.coex_para_ver = 0x19092746,
2040	.bt_desired_ver = 0x46,
2041	.scbd_support = true,
2042	.new_scbd10_def = false,
2043	.ble_hid_profile_support = false,
2044	.wl_mimo_ps_support = false,
2045	.pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
2046	.bt_rssi_type = COEX_BTRSSI_RATIO,
2047	.ant_isolation = 15,
2048	.rssi_tolerance = 2,
2049	.wl_rssi_step = wl_rssi_step_8821c,
2050	.bt_rssi_step = bt_rssi_step_8821c,
2051	.table_sant_num = ARRAY_SIZE(table_sant_8821c),
2052	.table_sant = table_sant_8821c,
2053	.table_nsant_num = ARRAY_SIZE(table_nsant_8821c),
2054	.table_nsant = table_nsant_8821c,
2055	.tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c),
2056	.tdma_sant = tdma_sant_8821c,
2057	.tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c),
2058	.tdma_nsant = tdma_nsant_8821c,
2059	.wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c),
2060	.wl_rf_para_tx = rf_para_tx_8821c,
2061	.wl_rf_para_rx = rf_para_rx_8821c,
2062	.bt_afh_span_bw20 = 0x24,
2063	.bt_afh_span_bw40 = 0x36,
2064	.afh_5g_num = ARRAY_SIZE(afh_5g_8821c),
2065	.afh_5g = afh_5g_8821c,
2066
2067	.coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c),
2068	.coex_info_hw_regs = coex_info_hw_regs_8821c,
2069};
2070EXPORT_SYMBOL(rtw8821c_hw_spec);
2071
2072MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin");
2073
2074MODULE_AUTHOR("Realtek Corporation");
2075MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver");
2076MODULE_LICENSE("Dual BSD/GPL");