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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#include <linux/module.h>
6#include "main.h"
7#include "coex.h"
8#include "fw.h"
9#include "tx.h"
10#include "rx.h"
11#include "phy.h"
12#include "rtw8723d.h"
13#include "rtw8723d_table.h"
14#include "mac.h"
15#include "reg.h"
16#include "debug.h"
17
18static const struct rtw_hw_reg rtw8723d_txagc[] = {
19 [DESC_RATE1M] = { .addr = 0xe08, .mask = 0x0000ff00 },
20 [DESC_RATE2M] = { .addr = 0x86c, .mask = 0x0000ff00 },
21 [DESC_RATE5_5M] = { .addr = 0x86c, .mask = 0x00ff0000 },
22 [DESC_RATE11M] = { .addr = 0x86c, .mask = 0xff000000 },
23 [DESC_RATE6M] = { .addr = 0xe00, .mask = 0x000000ff },
24 [DESC_RATE9M] = { .addr = 0xe00, .mask = 0x0000ff00 },
25 [DESC_RATE12M] = { .addr = 0xe00, .mask = 0x00ff0000 },
26 [DESC_RATE18M] = { .addr = 0xe00, .mask = 0xff000000 },
27 [DESC_RATE24M] = { .addr = 0xe04, .mask = 0x000000ff },
28 [DESC_RATE36M] = { .addr = 0xe04, .mask = 0x0000ff00 },
29 [DESC_RATE48M] = { .addr = 0xe04, .mask = 0x00ff0000 },
30 [DESC_RATE54M] = { .addr = 0xe04, .mask = 0xff000000 },
31 [DESC_RATEMCS0] = { .addr = 0xe10, .mask = 0x000000ff },
32 [DESC_RATEMCS1] = { .addr = 0xe10, .mask = 0x0000ff00 },
33 [DESC_RATEMCS2] = { .addr = 0xe10, .mask = 0x00ff0000 },
34 [DESC_RATEMCS3] = { .addr = 0xe10, .mask = 0xff000000 },
35 [DESC_RATEMCS4] = { .addr = 0xe14, .mask = 0x000000ff },
36 [DESC_RATEMCS5] = { .addr = 0xe14, .mask = 0x0000ff00 },
37 [DESC_RATEMCS6] = { .addr = 0xe14, .mask = 0x00ff0000 },
38 [DESC_RATEMCS7] = { .addr = 0xe14, .mask = 0xff000000 },
39};
40
41#define WLAN_TXQ_RPT_EN 0x1F
42#define WLAN_SLOT_TIME 0x09
43#define WLAN_RL_VAL 0x3030
44#define WLAN_BAR_VAL 0x0201ffff
45#define BIT_MASK_TBTT_HOLD 0x00000fff
46#define BIT_SHIFT_TBTT_HOLD 8
47#define BIT_MASK_TBTT_SETUP 0x000000ff
48#define BIT_SHIFT_TBTT_SETUP 0
49#define BIT_MASK_TBTT_MASK ((BIT_MASK_TBTT_HOLD << BIT_SHIFT_TBTT_HOLD) | \
50 (BIT_MASK_TBTT_SETUP << BIT_SHIFT_TBTT_SETUP))
51#define TBTT_TIME(s, h)((((s) & BIT_MASK_TBTT_SETUP) << BIT_SHIFT_TBTT_SETUP) |\
52 (((h) & BIT_MASK_TBTT_HOLD) << BIT_SHIFT_TBTT_HOLD))
53#define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80)
54#define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x64)
55#define WLAN_PIFS_VAL 0
56#define WLAN_AGG_BRK_TIME 0x16
57#define WLAN_NAV_PROT_LEN 0x0040
58#define WLAN_SPEC_SIFS 0x100a
59#define WLAN_RX_PKT_LIMIT 0x17
60#define WLAN_MAX_AGG_NR 0x0A
61#define WLAN_AMPDU_MAX_TIME 0x1C
62#define WLAN_ANT_SEL 0x82
63#define WLAN_LTR_IDLE_LAT 0x90039003
64#define WLAN_LTR_ACT_LAT 0x883c883c
65#define WLAN_LTR_CTRL1 0xCB004010
66#define WLAN_LTR_CTRL2 0x01233425
67
68static void rtw8723d_lck(struct rtw_dev *rtwdev)
69{
70 u32 lc_cal;
71 u8 val_ctx, rf_val;
72 int ret;
73
74 val_ctx = rtw_read8(rtwdev, REG_CTX);
75 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0)
76 rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE);
77 else
78 rtw_write8(rtwdev, REG_TXPAUSE, 0xFF);
79 lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
80
81 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal | BIT_LCK);
82
83 ret = read_poll_timeout(rtw_read_rf, rf_val, rf_val != 0x1,
84 10000, 1000000, false,
85 rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK);
86 if (ret)
87 rtw_warn(rtwdev, "failed to poll LCK status bit\n");
88
89 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal);
90 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0)
91 rtw_write8(rtwdev, REG_CTX, val_ctx);
92 else
93 rtw_write8(rtwdev, REG_TXPAUSE, 0x00);
94}
95
96static const u32 rtw8723d_ofdm_swing_table[] = {
97 0x0b40002d, 0x0c000030, 0x0cc00033, 0x0d800036, 0x0e400039, 0x0f00003c,
98 0x10000040, 0x11000044, 0x12000048, 0x1300004c, 0x14400051, 0x15800056,
99 0x16c0005b, 0x18000060, 0x19800066, 0x1b00006c, 0x1c800072, 0x1e400079,
100 0x20000080, 0x22000088, 0x24000090, 0x26000098, 0x288000a2, 0x2ac000ab,
101 0x2d4000b5, 0x300000c0, 0x32c000cb, 0x35c000d7, 0x390000e4, 0x3c8000f2,
102 0x40000100, 0x43c0010f, 0x47c0011f, 0x4c000130, 0x50800142, 0x55400155,
103 0x5a400169, 0x5fc0017f, 0x65400195, 0x6b8001ae, 0x71c001c7, 0x788001e2,
104 0x7f8001fe,
105};
106
107static const u32 rtw8723d_cck_swing_table[] = {
108 0x0CD, 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158,
109 0x16C, 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263,
110 0x287, 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F,
111 0x47F, 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C,
112 0x7FF,
113};
114
115#define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_ofdm_swing_table)
116#define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_cck_swing_table)
117
118static void rtw8723d_pwrtrack_init(struct rtw_dev *rtwdev)
119{
120 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
121 u8 path;
122
123 dm_info->default_ofdm_index = RTW_DEF_OFDM_SWING_INDEX;
124
125 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
126 ewma_thermal_init(&dm_info->avg_thermal[path]);
127 dm_info->delta_power_index[path] = 0;
128 }
129 dm_info->pwr_trk_triggered = false;
130 dm_info->pwr_trk_init_trigger = true;
131 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
132 dm_info->txagc_remnant_cck = 0;
133 dm_info->txagc_remnant_ofdm = 0;
134}
135
136static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev)
137{
138 u8 xtal_cap;
139 u32 val32;
140
141 /* power on BB/RF domain */
142 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN,
143 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
144 rtw_write8_set(rtwdev, REG_RF_CTRL,
145 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
146 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80);
147
148 rtw_phy_load_tables(rtwdev);
149
150 /* post init after header files config */
151 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF);
152 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, BIT_HIQ_NO_LMT_EN_ROOT);
153 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN);
154
155 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;
156 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,
157 xtal_cap | (xtal_cap << 6));
158 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN);
159 if ((rtwdev->efuse.afe >> 4) == 14) {
160 rtw_write32_set(rtwdev, REG_AFE_CTRL3, BIT_XTAL_GMP_BIT4);
161 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BITS_PLL);
162 rtw_write32_set(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA1);
163 rtw_write32_clr(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA0);
164 }
165
166 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
167 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
168 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL);
169 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL);
170 rtw_write8(rtwdev, REG_ATIMWND, 0x2);
171 rtw_write8(rtwdev, REG_BCN_CTRL,
172 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT);
173 val32 = rtw_read32(rtwdev, REG_TBTT_PROHIBIT);
174 val32 &= ~BIT_MASK_TBTT_MASK;
175 val32 |= WLAN_TBTT_TIME_STOP_BCN;
176 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, val32);
177 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL);
178 rtw_write8(rtwdev, REG_AGGR_BREAK_TIME, WLAN_AGG_BRK_TIME);
179 rtw_write16(rtwdev, REG_NAV_PROT_LEN, WLAN_NAV_PROT_LEN);
180 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS);
181 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS);
182 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS);
183 rtw_write8(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU);
184 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT);
185 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR);
186 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME);
187 rtw_write8(rtwdev, REG_LEDCFG2, WLAN_ANT_SEL);
188
189 rtw_write32(rtwdev, REG_LTR_IDLE_LATENCY, WLAN_LTR_IDLE_LAT);
190 rtw_write32(rtwdev, REG_LTR_ACTIVE_LATENCY, WLAN_LTR_ACT_LAT);
191 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC, WLAN_LTR_CTRL1);
192 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC + 4, WLAN_LTR_CTRL2);
193
194 rtw_phy_init(rtwdev);
195 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
196
197 rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN);
198
199 rtw8723d_lck(rtwdev);
200
201 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
202 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);
203
204 rtw8723d_pwrtrack_init(rtwdev);
205}
206
207static void rtw8723de_efuse_parsing(struct rtw_efuse *efuse,
208 struct rtw8723d_efuse *map)
209{
210 ether_addr_copy(efuse->addr, map->e.mac_addr);
211}
212
213static void rtw8723du_efuse_parsing(struct rtw_efuse *efuse,
214 struct rtw8723d_efuse *map)
215{
216 ether_addr_copy(efuse->addr, map->u.mac_addr);
217}
218
219static void rtw8723ds_efuse_parsing(struct rtw_efuse *efuse,
220 struct rtw8723d_efuse *map)
221{
222 ether_addr_copy(efuse->addr, map->s.mac_addr);
223}
224
225static int rtw8723d_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
226{
227 struct rtw_efuse *efuse = &rtwdev->efuse;
228 struct rtw8723d_efuse *map;
229 int i;
230
231 map = (struct rtw8723d_efuse *)log_map;
232
233 efuse->rfe_option = 0;
234 efuse->rf_board_option = map->rf_board_option;
235 efuse->crystal_cap = map->xtal_k;
236 efuse->pa_type_2g = map->pa_type;
237 efuse->lna_type_2g = map->lna_type_2g[0];
238 efuse->channel_plan = map->channel_plan;
239 efuse->country_code[0] = map->country_code[0];
240 efuse->country_code[1] = map->country_code[1];
241 efuse->bt_setting = map->rf_bt_setting;
242 efuse->regd = map->rf_board_option & 0x7;
243 efuse->thermal_meter[0] = map->thermal_meter;
244 efuse->thermal_meter_k = map->thermal_meter;
245 efuse->afe = map->afe;
246
247 for (i = 0; i < 4; i++)
248 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
249
250 switch (rtw_hci_type(rtwdev)) {
251 case RTW_HCI_TYPE_PCIE:
252 rtw8723de_efuse_parsing(efuse, map);
253 break;
254 case RTW_HCI_TYPE_USB:
255 rtw8723du_efuse_parsing(efuse, map);
256 break;
257 case RTW_HCI_TYPE_SDIO:
258 rtw8723ds_efuse_parsing(efuse, map);
259 break;
260 default:
261 /* unsupported now */
262 return -ENOTSUPP;
263 }
264
265 return 0;
266}
267
268static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
269 struct rtw_rx_pkt_stat *pkt_stat)
270{
271 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
272 s8 min_rx_power = -120;
273 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status);
274
275 pkt_stat->rx_power[RF_PATH_A] = pwdb - 97;
276 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
277 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
278 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
279 min_rx_power);
280 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
281}
282
283static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
284 struct rtw_rx_pkt_stat *pkt_stat)
285{
286 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
287 u8 rxsc, bw;
288 s8 min_rx_power = -120;
289 s8 rx_evm;
290
291 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
292 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
293 else
294 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
295
296 if (GET_PHY_STAT_P1_RF_MODE(phy_status) == 0)
297 bw = RTW_CHANNEL_WIDTH_20;
298 else if ((rxsc == 1) || (rxsc == 2))
299 bw = RTW_CHANNEL_WIDTH_20;
300 else
301 bw = RTW_CHANNEL_WIDTH_40;
302
303 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
304 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
305 pkt_stat->bw = bw;
306 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
307 min_rx_power);
308 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
309 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
310 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
311
312 dm_info->curr_rx_rate = pkt_stat->rate;
313 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
314 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1;
315 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1;
316
317 rx_evm = clamp_t(s8, -pkt_stat->rx_evm[RF_PATH_A] >> 1, 0, 64);
318 rx_evm &= 0x3F; /* 64->0: second path of 1SS rate is 64 */
319 dm_info->rx_evm_dbm[RF_PATH_A] = rx_evm;
320}
321
322static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
323 struct rtw_rx_pkt_stat *pkt_stat)
324{
325 u8 page;
326
327 page = *phy_status & 0xf;
328
329 switch (page) {
330 case 0:
331 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
332 break;
333 case 1:
334 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
335 break;
336 default:
337 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
338 return;
339 }
340}
341
342static void rtw8723d_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
343 struct rtw_rx_pkt_stat *pkt_stat,
344 struct ieee80211_rx_status *rx_status)
345{
346 struct ieee80211_hdr *hdr;
347 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
348 u8 *phy_status = NULL;
349
350 memset(pkt_stat, 0, sizeof(*pkt_stat));
351
352 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
353 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
354 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
355 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&
356 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE;
357 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
358 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
359 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
360 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
361 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
362 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
363 pkt_stat->ppdu_cnt = 0;
364 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
365
366 /* drv_info_sz is in unit of 8-bytes */
367 pkt_stat->drv_info_sz *= 8;
368
369 /* c2h cmd pkt's rx/phy status is not interested */
370 if (pkt_stat->is_c2h)
371 return;
372
373 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
374 pkt_stat->drv_info_sz);
375 if (pkt_stat->phy_status) {
376 phy_status = rx_desc + desc_sz + pkt_stat->shift;
377 query_phy_status(rtwdev, phy_status, pkt_stat);
378 }
379
380 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
381}
382
383static bool rtw8723d_check_spur_ov_thres(struct rtw_dev *rtwdev,
384 u8 channel, u32 thres)
385{
386 u32 freq;
387 bool ret = false;
388
389 if (channel == 13)
390 freq = FREQ_CH13;
391 else if (channel == 14)
392 freq = FREQ_CH14;
393 else
394 return false;
395
396 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE);
397 rtw_write32(rtwdev, REG_PSDFN, freq);
398 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq);
399
400 msleep(30);
401 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres)
402 ret = true;
403
404 rtw_write32(rtwdev, REG_PSDFN, freq);
405 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE);
406
407 return ret;
408}
409
410static void rtw8723d_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch)
411{
412 if (!notch) {
413 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);
414 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
415 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
416 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
417 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
418 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
419 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
420 return;
421 }
422
423 switch (channel) {
424 case 13:
425 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);
426 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
427 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000);
428 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
429 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
430 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
431 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
432 break;
433 case 14:
434 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);
435 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
436 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
437 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
438 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
439 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000);
440 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
441 break;
442 default:
443 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
444 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
445 break;
446 }
447}
448
449static void rtw8723d_spur_cal(struct rtw_dev *rtwdev, u8 channel)
450{
451 bool notch;
452
453 if (channel < 13) {
454 rtw8723d_cfg_notch(rtwdev, channel, false);
455 return;
456 }
457
458 notch = rtw8723d_check_spur_ov_thres(rtwdev, channel, SPUR_THRES);
459 rtw8723d_cfg_notch(rtwdev, channel, notch);
460}
461
462static void rtw8723d_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
463{
464 u32 rf_cfgch_a, rf_cfgch_b;
465
466 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
467 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK);
468
469 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK;
470 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK;
471 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK);
472 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK);
473
474 rf_cfgch_a &= ~RFCFGCH_BW_MASK;
475 switch (bw) {
476 case RTW_CHANNEL_WIDTH_20:
477 rf_cfgch_a |= RFCFGCH_BW_20M;
478 break;
479 case RTW_CHANNEL_WIDTH_40:
480 rf_cfgch_a |= RFCFGCH_BW_40M;
481 break;
482 default:
483 break;
484 }
485
486 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a);
487 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b);
488
489 rtw8723d_spur_cal(rtwdev, channel);
490}
491
492static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR] = {
493 [0] = {
494 { .len = 4, .reg = 0xA24, .val = 0x64B80C1C },
495 { .len = 4, .reg = 0xA28, .val = 0x00008810 },
496 { .len = 4, .reg = 0xAAC, .val = 0x01235667 },
497 },
498 [1] = {
499 { .len = 4, .reg = 0xA24, .val = 0x0000B81C },
500 { .len = 4, .reg = 0xA28, .val = 0x00000000 },
501 { .len = 4, .reg = 0xAAC, .val = 0x00003667 },
502 },
503};
504
505static void rtw8723d_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
506 u8 primary_ch_idx)
507{
508 const struct rtw_backup_info *cck_dfir;
509 int i;
510
511 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1];
512
513 for (i = 0; i < CCK_DFIR_NR; i++, cck_dfir++)
514 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val);
515
516 switch (bw) {
517 case RTW_CHANNEL_WIDTH_20:
518 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);
519 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);
520 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 1);
521 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa);
522 break;
523 case RTW_CHANNEL_WIDTH_40:
524 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);
525 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);
526 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0);
527 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND,
528 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0));
529 break;
530 default:
531 break;
532 }
533}
534
535static void rtw8723d_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
536 u8 primary_chan_idx)
537{
538 rtw8723d_set_channel_rf(rtwdev, channel, bw);
539 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
540 rtw8723d_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
541}
542
543#define BIT_CFENDFORM BIT(9)
544#define BIT_WMAC_TCR_ERR0 BIT(12)
545#define BIT_WMAC_TCR_ERR1 BIT(13)
546#define BIT_TCR_CFG (BIT_CFENDFORM | BIT_WMAC_TCR_ERR0 | \
547 BIT_WMAC_TCR_ERR1)
548#define WLAN_RX_FILTER0 0xFFFF
549#define WLAN_RX_FILTER1 0x400
550#define WLAN_RX_FILTER2 0xFFFF
551#define WLAN_RCR_CFG 0x700060CE
552
553static int rtw8723d_mac_init(struct rtw_dev *rtwdev)
554{
555 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
556 rtw_write32(rtwdev, REG_TCR, BIT_TCR_CFG);
557
558 rtw_write16(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
559 rtw_write16(rtwdev, REG_RXFLTMAP1, WLAN_RX_FILTER1);
560 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
561 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
562
563 rtw_write32(rtwdev, REG_INT_MIG, 0);
564 rtw_write32(rtwdev, REG_MCUTST_1, 0x0);
565
566 rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA);
567 rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0);
568
569 return 0;
570}
571
572static void rtw8723d_shutdown(struct rtw_dev *rtwdev)
573{
574 rtw_write16_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS);
575}
576
577static void rtw8723d_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
578{
579 u8 ldo_pwr;
580
581 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
582 if (enable) {
583 ldo_pwr &= ~BIT_MASK_LDO25_VOLTAGE;
584 ldo_pwr |= (BIT_LDO25_VOLTAGE_V25 << 4) | BIT_LDO25_EN;
585 } else {
586 ldo_pwr &= ~BIT_LDO25_EN;
587 }
588 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
589}
590
591static void
592rtw8723d_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
593{
594 struct rtw_hal *hal = &rtwdev->hal;
595 const struct rtw_hw_reg *txagc;
596 u8 rate, pwr_index;
597 int j;
598
599 for (j = 0; j < rtw_rate_size[rs]; j++) {
600 rate = rtw_rate_section[rs][j];
601 pwr_index = hal->tx_pwr_tbl[path][rate];
602
603 if (rate >= ARRAY_SIZE(rtw8723d_txagc)) {
604 rtw_warn(rtwdev, "rate 0x%x isn't supported\n", rate);
605 continue;
606 }
607 txagc = &rtw8723d_txagc[rate];
608 if (!txagc->addr) {
609 rtw_warn(rtwdev, "rate 0x%x isn't defined\n", rate);
610 continue;
611 }
612
613 rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index);
614 }
615}
616
617static void rtw8723d_set_tx_power_index(struct rtw_dev *rtwdev)
618{
619 struct rtw_hal *hal = &rtwdev->hal;
620 int rs, path;
621
622 for (path = 0; path < hal->rf_path_num; path++) {
623 for (rs = 0; rs <= RTW_RATE_SECTION_HT_1S; rs++)
624 rtw8723d_set_tx_power_index_by_rate(rtwdev, path, rs);
625 }
626}
627
628static void rtw8723d_efuse_grant(struct rtw_dev *rtwdev, bool on)
629{
630 if (on) {
631 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
632
633 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR);
634 rtw_write16_set(rtwdev, REG_SYS_CLKR, BIT_LOADER_CLK_EN | BIT_ANA8M);
635 } else {
636 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
637 }
638}
639
640static void rtw8723d_false_alarm_statistics(struct rtw_dev *rtwdev)
641{
642 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
643 u32 cck_fa_cnt;
644 u32 ofdm_fa_cnt;
645 u32 crc32_cnt;
646 u32 val32;
647
648 /* hold counter */
649 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1);
650 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1);
651 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1);
652 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1);
653
654 cck_fa_cnt = rtw_read32_mask(rtwdev, REG_CCK_FA_LSB_11N, MASKBYTE0);
655 cck_fa_cnt += rtw_read32_mask(rtwdev, REG_CCK_FA_MSB_11N, MASKBYTE3) << 8;
656
657 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE1_11N);
658 ofdm_fa_cnt = u32_get_bits(val32, BIT_MASK_OFDM_FF_CNT);
659 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_SF_CNT);
660 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE2_11N);
661 dm_info->ofdm_cca_cnt = u32_get_bits(val32, BIT_MASK_OFDM_CCA_CNT);
662 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_PF_CNT);
663 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE3_11N);
664 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_RI_CNT);
665 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_CRC_CNT);
666 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE4_11N);
667 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_MNS_CNT);
668
669 dm_info->cck_fa_cnt = cck_fa_cnt;
670 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
671 dm_info->total_fa_cnt = cck_fa_cnt + ofdm_fa_cnt;
672
673 dm_info->cck_err_cnt = rtw_read32(rtwdev, REG_IGI_C_11N);
674 dm_info->cck_ok_cnt = rtw_read32(rtwdev, REG_IGI_D_11N);
675 crc32_cnt = rtw_read32(rtwdev, REG_OFDM_CRC32_CNT_11N);
676 dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_ERR);
677 dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_OK);
678 crc32_cnt = rtw_read32(rtwdev, REG_HT_CRC32_CNT_11N);
679 dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_ERR);
680 dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_OK);
681 dm_info->vht_err_cnt = 0;
682 dm_info->vht_ok_cnt = 0;
683
684 val32 = rtw_read32(rtwdev, REG_CCK_CCA_CNT_11N);
685 dm_info->cck_cca_cnt = (u32_get_bits(val32, BIT_MASK_CCK_FA_MSB) << 8) |
686 u32_get_bits(val32, BIT_MASK_CCK_FA_LSB);
687 dm_info->total_cca_cnt = dm_info->cck_cca_cnt + dm_info->ofdm_cca_cnt;
688
689 /* reset counter */
690 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1);
691 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0);
692 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1);
693 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0);
694 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0);
695 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0);
696 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0);
697 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2);
698 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0);
699 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2);
700 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1);
701 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0);
702}
703
704static const u32 iqk_adda_regs[] = {
705 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c,
706 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec
707};
708
709static const u32 iqk_mac8_regs[] = {0x522, 0x550, 0x551};
710static const u32 iqk_mac32_regs[] = {0x40};
711
712static const u32 iqk_bb_regs[] = {
713 0xc04, 0xc08, 0x874, 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0xa04
714};
715
716#define IQK_ADDA_REG_NUM ARRAY_SIZE(iqk_adda_regs)
717#define IQK_MAC8_REG_NUM ARRAY_SIZE(iqk_mac8_regs)
718#define IQK_MAC32_REG_NUM ARRAY_SIZE(iqk_mac32_regs)
719#define IQK_BB_REG_NUM ARRAY_SIZE(iqk_bb_regs)
720
721struct iqk_backup_regs {
722 u32 adda[IQK_ADDA_REG_NUM];
723 u8 mac8[IQK_MAC8_REG_NUM];
724 u32 mac32[IQK_MAC32_REG_NUM];
725 u32 bb[IQK_BB_REG_NUM];
726
727 u32 lte_path;
728 u32 lte_gnt;
729
730 u32 bb_sel_btg;
731 u8 btg_sel;
732
733 u8 igia;
734 u8 igib;
735};
736
737static void rtw8723d_iqk_backup_regs(struct rtw_dev *rtwdev,
738 struct iqk_backup_regs *backup)
739{
740 int i;
741
742 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
743 backup->adda[i] = rtw_read32(rtwdev, iqk_adda_regs[i]);
744
745 for (i = 0; i < IQK_MAC8_REG_NUM; i++)
746 backup->mac8[i] = rtw_read8(rtwdev, iqk_mac8_regs[i]);
747 for (i = 0; i < IQK_MAC32_REG_NUM; i++)
748 backup->mac32[i] = rtw_read32(rtwdev, iqk_mac32_regs[i]);
749
750 for (i = 0; i < IQK_BB_REG_NUM; i++)
751 backup->bb[i] = rtw_read32(rtwdev, iqk_bb_regs[i]);
752
753 backup->igia = rtw_read32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0);
754 backup->igib = rtw_read32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0);
755
756 backup->bb_sel_btg = rtw_read32(rtwdev, REG_BB_SEL_BTG);
757}
758
759static void rtw8723d_iqk_restore_regs(struct rtw_dev *rtwdev,
760 const struct iqk_backup_regs *backup)
761{
762 int i;
763
764 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
765 rtw_write32(rtwdev, iqk_adda_regs[i], backup->adda[i]);
766
767 for (i = 0; i < IQK_MAC8_REG_NUM; i++)
768 rtw_write8(rtwdev, iqk_mac8_regs[i], backup->mac8[i]);
769 for (i = 0; i < IQK_MAC32_REG_NUM; i++)
770 rtw_write32(rtwdev, iqk_mac32_regs[i], backup->mac32[i]);
771
772 for (i = 0; i < IQK_BB_REG_NUM; i++)
773 rtw_write32(rtwdev, iqk_bb_regs[i], backup->bb[i]);
774
775 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
776 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, backup->igia);
777
778 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50);
779 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, backup->igib);
780
781 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x01008c00);
782 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x01008c00);
783}
784
785static void rtw8723d_iqk_backup_path_ctrl(struct rtw_dev *rtwdev,
786 struct iqk_backup_regs *backup)
787{
788 backup->btg_sel = rtw_read8(rtwdev, REG_BTG_SEL);
789 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] original 0x67 = 0x%x\n",
790 backup->btg_sel);
791}
792
793static void rtw8723d_iqk_config_path_ctrl(struct rtw_dev *rtwdev)
794{
795 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1);
796 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] set 0x67 = 0x%x\n",
797 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
798}
799
800static void rtw8723d_iqk_restore_path_ctrl(struct rtw_dev *rtwdev,
801 const struct iqk_backup_regs *backup)
802{
803 rtw_write8(rtwdev, REG_BTG_SEL, backup->btg_sel);
804 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] restore 0x67 = 0x%x\n",
805 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
806}
807
808static void rtw8723d_iqk_backup_lte_path_gnt(struct rtw_dev *rtwdev,
809 struct iqk_backup_regs *backup)
810{
811 backup->lte_path = rtw_read32(rtwdev, REG_LTECOEX_PATH_CONTROL);
812 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0038);
813 mdelay(1);
814 backup->lte_gnt = rtw_read32(rtwdev, REG_LTECOEX_READ_DATA);
815 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] OriginalGNT = 0x%x\n",
816 backup->lte_gnt);
817}
818
819static void rtw8723d_iqk_config_lte_path_gnt(struct rtw_dev *rtwdev)
820{
821 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, 0x0000ff00);
822 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc0020038);
823 rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL, BIT_LTE_MUX_CTRL_PATH, 0x1);
824}
825
826static void rtw8723d_iqk_restore_lte_path_gnt(struct rtw_dev *rtwdev,
827 const struct iqk_backup_regs *bak)
828{
829 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, bak->lte_gnt);
830 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc00f0038);
831 rtw_write32(rtwdev, REG_LTECOEX_PATH_CONTROL, bak->lte_path);
832}
833
834struct rtw_8723d_iqk_cfg {
835 const char *name;
836 u32 val_bb_sel_btg;
837 u32 reg_lutwe;
838 u32 val_txiqk_pi;
839 u32 reg_padlut;
840 u32 reg_gaintx;
841 u32 reg_bspad;
842 u32 val_wlint;
843 u32 val_wlsel;
844 u32 val_iqkpts;
845};
846
847static const struct rtw_8723d_iqk_cfg iqk_tx_cfg[PATH_NR] = {
848 [PATH_S1] = {
849 .name = "S1",
850 .val_bb_sel_btg = 0x99000000,
851 .reg_lutwe = RF_LUTWE,
852 .val_txiqk_pi = 0x8214019f,
853 .reg_padlut = RF_LUTDBG,
854 .reg_gaintx = RF_GAINTX,
855 .reg_bspad = RF_BSPAD,
856 .val_wlint = 0xe0d,
857 .val_wlsel = 0x60d,
858 .val_iqkpts = 0xfa000000,
859 },
860 [PATH_S0] = {
861 .name = "S0",
862 .val_bb_sel_btg = 0x99000280,
863 .reg_lutwe = RF_LUTWE2,
864 .val_txiqk_pi = 0x8214018a,
865 .reg_padlut = RF_TXADBG,
866 .reg_gaintx = RF_TRXIQ,
867 .reg_bspad = RF_TXATANK,
868 .val_wlint = 0xe6d,
869 .val_wlsel = 0x66d,
870 .val_iqkpts = 0xf9000000,
871 },
872};
873
874static u8 rtw8723d_iqk_check_tx_failed(struct rtw_dev *rtwdev,
875 const struct rtw_8723d_iqk_cfg *iqk_cfg)
876{
877 s32 tx_x, tx_y;
878 u32 tx_fail;
879
880 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n",
881 rtw_read32(rtwdev, REG_IQK_RES_RY));
882 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n",
883 rtw_read32(rtwdev, REG_IQK_RES_TX),
884 rtw_read32(rtwdev, REG_IQK_RES_TY));
885 rtw_dbg(rtwdev, RTW_DBG_RFK,
886 "[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
887 rtw_read32(rtwdev, 0xe90),
888 rtw_read32(rtwdev, 0xe98));
889
890 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL);
891 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
892 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
893
894 if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR)
895 return IQK_TX_OK;
896
897 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s TXIQK is failed\n",
898 iqk_cfg->name);
899
900 return 0;
901}
902
903static u8 rtw8723d_iqk_check_rx_failed(struct rtw_dev *rtwdev,
904 const struct rtw_8723d_iqk_cfg *iqk_cfg)
905{
906 s32 rx_x, rx_y;
907 u32 rx_fail;
908
909 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n",
910 rtw_read32(rtwdev, REG_IQK_RES_RX),
911 rtw_read32(rtwdev, REG_IQK_RES_RY));
912
913 rtw_dbg(rtwdev, RTW_DBG_RFK,
914 "[IQK] 0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",
915 rtw_read32(rtwdev, 0xea0),
916 rtw_read32(rtwdev, 0xea8));
917
918 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL);
919 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
920 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
921 rx_y = abs(iqkxy_to_s32(rx_y));
922
923 if (!rx_fail && rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER &&
924 rx_y < IQK_RX_Y_LMT)
925 return IQK_RX_OK;
926
927 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s RXIQK STEP2 is failed\n",
928 iqk_cfg->name);
929
930 return 0;
931}
932
933static void rtw8723d_iqk_one_shot(struct rtw_dev *rtwdev, bool tx,
934 const struct rtw_8723d_iqk_cfg *iqk_cfg)
935{
936 u32 pts = (tx ? iqk_cfg->val_iqkpts : 0xf9000000);
937
938 /* enter IQK mode */
939 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);
940 rtw8723d_iqk_config_lte_path_gnt(rtwdev);
941
942 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0054);
943 mdelay(1);
944 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] GNT_BT @%s %sIQK1 = 0x%x\n",
945 iqk_cfg->name, tx ? "TX" : "RX",
946 rtw_read32(rtwdev, REG_LTECOEX_READ_DATA));
947 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x948 @%s %sIQK1 = 0x%x\n",
948 iqk_cfg->name, tx ? "TX" : "RX",
949 rtw_read32(rtwdev, REG_BB_SEL_BTG));
950
951 /* One shot, LOK & IQK */
952 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, pts);
953 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000);
954
955 if (!check_hw_ready(rtwdev, REG_IQK_RES_RY, BIT_IQK_DONE, 1))
956 rtw_warn(rtwdev, "%s %s IQK isn't done\n", iqk_cfg->name,
957 tx ? "TX" : "RX");
958}
959
960static void rtw8723d_iqk_txrx_path_post(struct rtw_dev *rtwdev,
961 const struct rtw_8723d_iqk_cfg *iqk_cfg,
962 const struct iqk_backup_regs *backup)
963{
964 rtw8723d_iqk_restore_lte_path_gnt(rtwdev, backup);
965 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg);
966
967 /* leave IQK mode */
968 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
969 mdelay(1);
970 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x0);
971 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, BIT(0), 0x0);
972 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, BIT(0), 0x0);
973}
974
975static u8 rtw8723d_iqk_tx_path(struct rtw_dev *rtwdev,
976 const struct rtw_8723d_iqk_cfg *iqk_cfg,
977 const struct iqk_backup_regs *backup)
978{
979 u8 status;
980
981 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s TXIQK!!\n", iqk_cfg->name);
982 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s TXIQK = 0x%x\n",
983 iqk_cfg->name,
984 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
985
986 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg);
987 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
988 mdelay(1);
989 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000);
990 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00004);
991 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005d);
992 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xBFFE0);
993 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
994
995 /* IQK setting */
996 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x08008c0c);
997 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
998 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, iqk_cfg->val_txiqk_pi);
999 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160200);
1000 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
1001 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
1002
1003 /* LOK setting */
1004 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911);
1005
1006 /* PA, PAD setting */
1007 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1);
1008 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0);
1009 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x1E0, 0x3);
1010 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXIQGEN, 0x1F, 0xf);
1011
1012 /* LOK setting for 8723D */
1013 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x10, 0x1);
1014 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_bspad, 0x1, 0x1);
1015
1016 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint);
1017 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel);
1018
1019 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s TXIQK = 0x%x\n",
1020 iqk_cfg->name,
1021 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK));
1022 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s TXIQK = 0x%x\n",
1023 iqk_cfg->name,
1024 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK));
1025
1026 rtw8723d_iqk_one_shot(rtwdev, true, iqk_cfg);
1027 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg);
1028
1029 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup);
1030
1031 return status;
1032}
1033
1034static u8 rtw8723d_iqk_rx_path(struct rtw_dev *rtwdev,
1035 const struct rtw_8723d_iqk_cfg *iqk_cfg,
1036 const struct iqk_backup_regs *backup)
1037{
1038 u32 tx_x, tx_y;
1039 u8 status;
1040
1041 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK Step1!!\n",
1042 iqk_cfg->name);
1043 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK1 = 0x%x\n",
1044 iqk_cfg->name,
1045 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
1046 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg);
1047
1048 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
1049
1050 /* IQK setting */
1051 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
1052 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
1053
1054 /* path IQK setting */
1055 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);
1056 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
1057 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
1058 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
1059 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82160000);
1060 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160000);
1061
1062 /* LOK setting */
1063 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911);
1064
1065 /* RXIQK mode */
1066 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000);
1067 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00006);
1068 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f);
1069 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xa7ffb);
1070 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
1071
1072 /* PA/PAD=0 */
1073 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1);
1074 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0);
1075 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint);
1076 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel);
1077
1078 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1@ path %s RXIQK1 = 0x%x\n",
1079 iqk_cfg->name,
1080 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK));
1081 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2@ path %s RXIQK1 = 0x%x\n",
1082 iqk_cfg->name,
1083 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK));
1084
1085 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg);
1086 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg);
1087
1088 if (!status)
1089 goto restore;
1090
1091 /* second round */
1092 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
1093 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
1094
1095 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y));
1096 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n",
1097 rtw_read32(rtwdev, REG_TXIQK_11N),
1098 BIT_SET_TXIQK_11N(tx_x, tx_y));
1099
1100 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK STEP2!!\n",
1101 iqk_cfg->name);
1102 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK2 = 0x%x\n",
1103 iqk_cfg->name,
1104 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
1105
1106 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
1107 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c);
1108 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c);
1109 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
1110 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
1111 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82170000);
1112 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28171400);
1113
1114 /* LOK setting */
1115 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1);
1116
1117 /* RXIQK mode */
1118 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
1119 mdelay(1);
1120 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x80000, 0x1);
1121 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00007);
1122 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f);
1123 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xb3fdb);
1124 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
1125
1126 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s RXIQK2 = 0x%x\n",
1127 iqk_cfg->name,
1128 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK));
1129 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s RXIQK2 = 0x%x\n",
1130 iqk_cfg->name,
1131 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK));
1132
1133 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg);
1134 status |= rtw8723d_iqk_check_rx_failed(rtwdev, iqk_cfg);
1135
1136restore:
1137 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup);
1138
1139 return status;
1140}
1141
1142static
1143void rtw8723d_iqk_fill_s1_matrix(struct rtw_dev *rtwdev, const s32 result[])
1144{
1145 s32 oldval_1;
1146 s32 x, y;
1147 s32 tx1_a, tx1_a_ext;
1148 s32 tx1_c, tx1_c_ext;
1149
1150 if (result[IQK_S1_TX_X] == 0)
1151 return;
1152
1153 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
1154 BIT_MASK_TXIQ_ELM_D);
1155
1156 x = iqkxy_to_s32(result[IQK_S1_TX_X]);
1157 tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext);
1158 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
1159 BIT_MASK_TXIQ_ELM_A, tx1_a);
1160 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,
1161 BIT_MASK_OFDM0_EXT_A, tx1_a_ext);
1162
1163 y = iqkxy_to_s32(result[IQK_S1_TX_Y]);
1164 tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext);
1165 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
1166 BIT_SET_TXIQ_ELM_C1(tx1_c));
1167 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
1168 BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c));
1169 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,
1170 BIT_MASK_OFDM0_EXT_C, tx1_c_ext);
1171
1172 rtw_dbg(rtwdev, RTW_DBG_RFK,
1173 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n",
1174 x, tx1_a, oldval_1);
1175 rtw_dbg(rtwdev, RTW_DBG_RFK,
1176 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c);
1177
1178 if (result[IQK_S1_RX_X] == 0)
1179 return;
1180
1181 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_X,
1182 result[IQK_S1_RX_X]);
1183 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_Y1,
1184 BIT_SET_RXIQ_S1_Y1(result[IQK_S1_RX_Y]));
1185 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2,
1186 BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y]));
1187}
1188
1189static
1190void rtw8723d_iqk_fill_s0_matrix(struct rtw_dev *rtwdev, const s32 result[])
1191{
1192 s32 oldval_0;
1193 s32 x, y;
1194 s32 tx0_a, tx0_a_ext;
1195 s32 tx0_c, tx0_c_ext;
1196
1197 if (result[IQK_S0_TX_X] == 0)
1198 return;
1199
1200 oldval_0 = rtw_read32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0);
1201
1202 x = iqkxy_to_s32(result[IQK_S0_TX_X]);
1203 tx0_a = iqk_mult(x, oldval_0, &tx0_a_ext);
1204
1205 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, tx0_a);
1206 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, tx0_a_ext);
1207
1208 y = iqkxy_to_s32(result[IQK_S0_TX_Y]);
1209 tx0_c = iqk_mult(y, oldval_0, &tx0_c_ext);
1210
1211 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, tx0_c);
1212 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, tx0_c_ext);
1213
1214 if (result[IQK_S0_RX_X] == 0)
1215 return;
1216
1217 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_X_S0,
1218 result[IQK_S0_RX_X]);
1219 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_Y_S0,
1220 result[IQK_S0_RX_Y]);
1221}
1222
1223static void rtw8723d_iqk_path_adda_on(struct rtw_dev *rtwdev)
1224{
1225 int i;
1226
1227 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1228 rtw_write32(rtwdev, iqk_adda_regs[i], 0x03c00016);
1229}
1230
1231static void rtw8723d_iqk_config_mac(struct rtw_dev *rtwdev)
1232{
1233 rtw_write8(rtwdev, REG_TXPAUSE, 0xff);
1234}
1235
1236static
1237void rtw8723d_iqk_rf_standby(struct rtw_dev *rtwdev, enum rtw_rf_path path)
1238{
1239 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path-%s standby mode!\n",
1240 path == RF_PATH_A ? "S1" : "S0");
1241
1242 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
1243 mdelay(1);
1244 rtw_write_rf(rtwdev, path, RF_MODE, RFREG_MASK, 0x10000);
1245 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);
1246}
1247
1248static
1249bool rtw8723d_iqk_similarity_cmp(struct rtw_dev *rtwdev, s32 result[][IQK_NR],
1250 u8 c1, u8 c2)
1251{
1252 u32 i, j, diff;
1253 u32 bitmap = 0;
1254 u8 candidate[PATH_NR] = {IQK_ROUND_INVALID, IQK_ROUND_INVALID};
1255 bool ret = true;
1256
1257 s32 tmp1, tmp2;
1258
1259 for (i = 0; i < IQK_NR; i++) {
1260 tmp1 = iqkxy_to_s32(result[c1][i]);
1261 tmp2 = iqkxy_to_s32(result[c2][i]);
1262
1263 diff = abs(tmp1 - tmp2);
1264
1265 if (diff <= MAX_TOLERANCE)
1266 continue;
1267
1268 if ((i == IQK_S1_RX_X || i == IQK_S0_RX_X) && !bitmap) {
1269 if (result[c1][i] + result[c1][i + 1] == 0)
1270 candidate[i / IQK_SX_NR] = c2;
1271 else if (result[c2][i] + result[c2][i + 1] == 0)
1272 candidate[i / IQK_SX_NR] = c1;
1273 else
1274 bitmap |= BIT(i);
1275 } else {
1276 bitmap |= BIT(i);
1277 }
1278 }
1279
1280 if (bitmap != 0)
1281 goto check_sim;
1282
1283 for (i = 0; i < PATH_NR; i++) {
1284 if (candidate[i] == IQK_ROUND_INVALID)
1285 continue;
1286
1287 for (j = i * IQK_SX_NR; j < i * IQK_SX_NR + 2; j++)
1288 result[IQK_ROUND_HYBRID][j] = result[candidate[i]][j];
1289 ret = false;
1290 }
1291
1292 return ret;
1293
1294check_sim:
1295 for (i = 0; i < IQK_NR; i++) {
1296 j = i & ~1; /* 2 bits are a pair for IQ[X, Y] */
1297 if (bitmap & GENMASK(j + 1, j))
1298 continue;
1299
1300 result[IQK_ROUND_HYBRID][i] = result[c1][i];
1301 }
1302
1303 return false;
1304}
1305
1306static
1307void rtw8723d_iqk_precfg_path(struct rtw_dev *rtwdev, enum rtw8723d_path path)
1308{
1309 if (path == PATH_S0) {
1310 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_A);
1311 rtw8723d_iqk_path_adda_on(rtwdev);
1312 }
1313
1314 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);
1315 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
1316 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
1317
1318 if (path == PATH_S1) {
1319 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_B);
1320 rtw8723d_iqk_path_adda_on(rtwdev);
1321 }
1322}
1323
1324static
1325void rtw8723d_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t,
1326 const struct iqk_backup_regs *backup)
1327{
1328 u32 i;
1329 u8 s1_ok, s0_ok;
1330
1331 rtw_dbg(rtwdev, RTW_DBG_RFK,
1332 "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t);
1333
1334 rtw8723d_iqk_path_adda_on(rtwdev);
1335 rtw8723d_iqk_config_mac(rtwdev);
1336 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf);
1337 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05611);
1338 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4);
1339 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204200);
1340 rtw8723d_iqk_precfg_path(rtwdev, PATH_S1);
1341
1342 for (i = 0; i < PATH_IQK_RETRY; i++) {
1343 s1_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup);
1344 if (s1_ok == IQK_TX_OK) {
1345 rtw_dbg(rtwdev, RTW_DBG_RFK,
1346 "[IQK] path S1 Tx IQK Success!!\n");
1347 result[t][IQK_S1_TX_X] =
1348 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
1349 result[t][IQK_S1_TX_Y] =
1350 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
1351 break;
1352 }
1353
1354 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Tx IQK Fail!!\n");
1355 result[t][IQK_S1_TX_X] = 0x100;
1356 result[t][IQK_S1_TX_Y] = 0x0;
1357 }
1358
1359 for (i = 0; i < PATH_IQK_RETRY; i++) {
1360 s1_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup);
1361 if (s1_ok == (IQK_TX_OK | IQK_RX_OK)) {
1362 rtw_dbg(rtwdev, RTW_DBG_RFK,
1363 "[IQK] path S1 Rx IQK Success!!\n");
1364 result[t][IQK_S1_RX_X] =
1365 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
1366 result[t][IQK_S1_RX_Y] =
1367 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
1368 break;
1369 }
1370
1371 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Rx IQK Fail!!\n");
1372 result[t][IQK_S1_RX_X] = 0x100;
1373 result[t][IQK_S1_RX_Y] = 0x0;
1374 }
1375
1376 if (s1_ok == 0x0)
1377 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 IQK is failed!!\n");
1378
1379 rtw8723d_iqk_precfg_path(rtwdev, PATH_S0);
1380
1381 for (i = 0; i < PATH_IQK_RETRY; i++) {
1382 s0_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup);
1383 if (s0_ok == IQK_TX_OK) {
1384 rtw_dbg(rtwdev, RTW_DBG_RFK,
1385 "[IQK] path S0 Tx IQK Success!!\n");
1386 result[t][IQK_S0_TX_X] =
1387 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
1388 result[t][IQK_S0_TX_Y] =
1389 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
1390 break;
1391 }
1392
1393 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Tx IQK Fail!!\n");
1394 result[t][IQK_S0_TX_X] = 0x100;
1395 result[t][IQK_S0_TX_Y] = 0x0;
1396 }
1397
1398 for (i = 0; i < PATH_IQK_RETRY; i++) {
1399 s0_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup);
1400 if (s0_ok == (IQK_TX_OK | IQK_RX_OK)) {
1401 rtw_dbg(rtwdev, RTW_DBG_RFK,
1402 "[IQK] path S0 Rx IQK Success!!\n");
1403
1404 result[t][IQK_S0_RX_X] =
1405 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
1406 result[t][IQK_S0_RX_Y] =
1407 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
1408 break;
1409 }
1410
1411 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Rx IQK Fail!!\n");
1412 result[t][IQK_S0_RX_X] = 0x100;
1413 result[t][IQK_S0_RX_Y] = 0x0;
1414 }
1415
1416 if (s0_ok == 0x0)
1417 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 IQK is failed!!\n");
1418
1419 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
1420 mdelay(1);
1421
1422 rtw_dbg(rtwdev, RTW_DBG_RFK,
1423 "[IQK] back to BB mode, load original value!\n");
1424}
1425
1426static void rtw8723d_phy_calibration(struct rtw_dev *rtwdev)
1427{
1428 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1429 s32 result[IQK_ROUND_SIZE][IQK_NR];
1430 struct iqk_backup_regs backup;
1431 u8 i, j;
1432 u8 final_candidate = IQK_ROUND_INVALID;
1433 bool good;
1434
1435 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!!!\n");
1436
1437 memset(result, 0, sizeof(result));
1438
1439 rtw8723d_iqk_backup_path_ctrl(rtwdev, &backup);
1440 rtw8723d_iqk_backup_lte_path_gnt(rtwdev, &backup);
1441 rtw8723d_iqk_backup_regs(rtwdev, &backup);
1442
1443 for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) {
1444 rtw8723d_iqk_config_path_ctrl(rtwdev);
1445 rtw8723d_iqk_config_lte_path_gnt(rtwdev);
1446
1447 rtw8723d_iqk_one_round(rtwdev, result, i, &backup);
1448
1449 if (i > IQK_ROUND_0)
1450 rtw8723d_iqk_restore_regs(rtwdev, &backup);
1451 rtw8723d_iqk_restore_lte_path_gnt(rtwdev, &backup);
1452 rtw8723d_iqk_restore_path_ctrl(rtwdev, &backup);
1453
1454 for (j = IQK_ROUND_0; j < i; j++) {
1455 good = rtw8723d_iqk_similarity_cmp(rtwdev, result, j, i);
1456
1457 if (good) {
1458 final_candidate = j;
1459 rtw_dbg(rtwdev, RTW_DBG_RFK,
1460 "[IQK] cmp %d:%d final_candidate is %x\n",
1461 j, i, final_candidate);
1462 goto iqk_done;
1463 }
1464 }
1465 }
1466
1467 if (final_candidate == IQK_ROUND_INVALID) {
1468 s32 reg_tmp = 0;
1469
1470 for (i = 0; i < IQK_NR; i++)
1471 reg_tmp += result[IQK_ROUND_HYBRID][i];
1472
1473 if (reg_tmp != 0) {
1474 final_candidate = IQK_ROUND_HYBRID;
1475 } else {
1476 WARN(1, "IQK is failed\n");
1477 goto out;
1478 }
1479 }
1480
1481iqk_done:
1482 rtw8723d_iqk_fill_s1_matrix(rtwdev, result[final_candidate]);
1483 rtw8723d_iqk_fill_s0_matrix(rtwdev, result[final_candidate]);
1484
1485 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X];
1486 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y];
1487 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X];
1488 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y];
1489 dm_info->iqk.done = true;
1490
1491out:
1492 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg);
1493
1494 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n",
1495 final_candidate);
1496
1497 for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++)
1498 rtw_dbg(rtwdev, RTW_DBG_RFK,
1499 "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n",
1500 i,
1501 result[i][0], result[i][1], result[i][2], result[i][3],
1502 result[i][4], result[i][5], result[i][6], result[i][7],
1503 final_candidate == i ? "(final candidate)" : "");
1504
1505 rtw_dbg(rtwdev, RTW_DBG_RFK,
1506 "[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n",
1507 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE),
1508 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N),
1509 rtw_read32(rtwdev, REG_A_RXIQI),
1510 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N));
1511 rtw_dbg(rtwdev, RTW_DBG_RFK,
1512 "[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n",
1513 rtw_read32(rtwdev, REG_TXIQ_AB_S0),
1514 rtw_read32(rtwdev, REG_TXIQ_CD_S0),
1515 rtw_read32(rtwdev, REG_RXIQ_AB_S0));
1516
1517 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] finished\n");
1518}
1519
1520static void rtw8723d_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1521{
1522 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1523 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13};
1524 u8 cck_n_rx;
1525
1526 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
1527 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
1528
1529 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
1530 return;
1531
1532 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) &&
1533 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1;
1534 rtw_dbg(rtwdev, RTW_DBG_PHY,
1535 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n",
1536 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx,
1537 dm_info->cck_pd_default + new_lvl * 2,
1538 pd[new_lvl], dm_info->cck_fa_avg);
1539
1540 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1541
1542 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1543 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1544 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1545 dm_info->cck_pd_default + new_lvl * 2);
1546}
1547
1548/* for coex */
1549static void rtw8723d_coex_cfg_init(struct rtw_dev *rtwdev)
1550{
1551 /* enable TBTT nterrupt */
1552 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
1553
1554 /* BT report packet sample rate */
1555 /* 0x790[5:0]=0x5 */
1556 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
1557
1558 /* enable BT counter statistics */
1559 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
1560
1561 /* enable PTA (3-wire function form BT side) */
1562 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
1563 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
1564
1565 /* enable PTA (tx/rx signal form WiFi side) */
1566 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
1567}
1568
1569static void rtw8723d_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
1570{
1571}
1572
1573static void rtw8723d_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
1574{
1575 rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0);
1576 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0);
1577 rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0);
1578 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0);
1579 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0);
1580 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0);
1581 rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0);
1582 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0);
1583}
1584
1585static void rtw8723d_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
1586{
1587 struct rtw_efuse *efuse = &rtwdev->efuse;
1588 struct rtw_coex *coex = &rtwdev->coex;
1589 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1590 bool aux = efuse->bt_setting & BIT(6);
1591
1592 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
1593 coex_rfe->ant_switch_polarity = 0;
1594 coex_rfe->ant_switch_exist = false;
1595 coex_rfe->ant_switch_with_bt = false;
1596 coex_rfe->ant_switch_diversity = false;
1597 coex_rfe->wlg_at_btg = true;
1598
1599 /* decide antenna at main or aux */
1600 if (efuse->share_ant) {
1601 if (aux)
1602 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x80);
1603 else
1604 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x200);
1605 } else {
1606 if (aux)
1607 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x280);
1608 else
1609 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x0);
1610 }
1611
1612 /* disable LTE coex in wifi side */
1613 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
1614 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
1615 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
1616}
1617
1618static void rtw8723d_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
1619{
1620 struct rtw_coex *coex = &rtwdev->coex;
1621 struct rtw_coex_dm *coex_dm = &coex->dm;
1622 static const u8 wl_tx_power[] = {0xb2, 0x90};
1623 u8 pwr;
1624
1625 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
1626 return;
1627
1628 coex_dm->cur_wl_pwr_lvl = wl_pwr;
1629
1630 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power))
1631 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1;
1632
1633 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl];
1634
1635 rtw_write8(rtwdev, REG_ANA_PARAM1 + 3, pwr);
1636}
1637
1638static void rtw8723d_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1639{
1640 struct rtw_coex *coex = &rtwdev->coex;
1641 struct rtw_coex_dm *coex_dm = &coex->dm;
1642 /* WL Rx Low gain on */
1643 static const u32 wl_rx_low_gain_on[] = {
1644 0xec120101, 0xeb130101, 0xce140101, 0xcd150101, 0xcc160101,
1645 0xcb170101, 0xca180101, 0x8d190101, 0x8c1a0101, 0x8b1b0101,
1646 0x4f1c0101, 0x4e1d0101, 0x4d1e0101, 0x4c1f0101, 0x0e200101,
1647 0x0d210101, 0x0c220101, 0x0b230101, 0xcf240001, 0xce250001,
1648 0xcd260001, 0xcc270001, 0x8f280001
1649 };
1650 /* WL Rx Low gain off */
1651 static const u32 wl_rx_low_gain_off[] = {
1652 0xec120101, 0xeb130101, 0xea140101, 0xe9150101, 0xe8160101,
1653 0xe7170101, 0xe6180101, 0xe5190101, 0xe41a0101, 0xe31b0101,
1654 0xe21c0101, 0xe11d0101, 0xe01e0101, 0x861f0101, 0x85200101,
1655 0x84210101, 0x83220101, 0x82230101, 0x81240101, 0x80250101,
1656 0x44260101, 0x43270101, 0x42280101
1657 };
1658 u8 i;
1659
1660 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
1661 return;
1662
1663 coex_dm->cur_wl_rx_low_gain_en = low_gain;
1664
1665 if (coex_dm->cur_wl_rx_low_gain_en) {
1666 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++)
1667 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_on[i]);
1668 } else {
1669 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++)
1670 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_off[i]);
1671 }
1672}
1673
1674static u8 rtw8723d_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev)
1675{
1676 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1677 u8 tx_rate = dm_info->tx_rate;
1678 u8 limit_ofdm = 30;
1679
1680 switch (tx_rate) {
1681 case DESC_RATE1M...DESC_RATE5_5M:
1682 case DESC_RATE11M:
1683 break;
1684 case DESC_RATE6M...DESC_RATE48M:
1685 limit_ofdm = 36;
1686 break;
1687 case DESC_RATE54M:
1688 limit_ofdm = 34;
1689 break;
1690 case DESC_RATEMCS0...DESC_RATEMCS2:
1691 limit_ofdm = 38;
1692 break;
1693 case DESC_RATEMCS3...DESC_RATEMCS4:
1694 limit_ofdm = 36;
1695 break;
1696 case DESC_RATEMCS5...DESC_RATEMCS7:
1697 limit_ofdm = 34;
1698 break;
1699 default:
1700 rtw_warn(rtwdev, "pwrtrack unhandled tx_rate 0x%x\n", tx_rate);
1701 break;
1702 }
1703
1704 return limit_ofdm;
1705}
1706
1707static void rtw8723d_set_iqk_matrix_by_result(struct rtw_dev *rtwdev,
1708 u32 ofdm_swing, u8 rf_path)
1709{
1710 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1711 s32 ele_A, ele_D, ele_C;
1712 s32 ele_A_ext, ele_C_ext, ele_D_ext;
1713 s32 iqk_result_x;
1714 s32 iqk_result_y;
1715 s32 value32;
1716
1717 switch (rf_path) {
1718 default:
1719 case RF_PATH_A:
1720 iqk_result_x = dm_info->iqk.result.s1_x;
1721 iqk_result_y = dm_info->iqk.result.s1_y;
1722 break;
1723 case RF_PATH_B:
1724 iqk_result_x = dm_info->iqk.result.s0_x;
1725 iqk_result_y = dm_info->iqk.result.s0_y;
1726 break;
1727 }
1728
1729 /* new element D */
1730 ele_D = OFDM_SWING_D(ofdm_swing);
1731 iqk_mult(iqk_result_x, ele_D, &ele_D_ext);
1732 /* new element A */
1733 iqk_result_x = iqkxy_to_s32(iqk_result_x);
1734 ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext);
1735 /* new element C */
1736 iqk_result_y = iqkxy_to_s32(iqk_result_y);
1737 ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext);
1738
1739 switch (rf_path) {
1740 case RF_PATH_A:
1741 default:
1742 /* write new elements A, C, D, and element B is always 0 */
1743 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D);
1744 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32);
1745 value32 = BIT_SET_TXIQ_ELM_C1(ele_C);
1746 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
1747 value32);
1748 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1749 value32 &= ~BIT_MASK_OFDM0_EXTS;
1750 value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext);
1751 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1752 break;
1753
1754 case RF_PATH_B:
1755 /* write new elements A, C, D, and element B is always 0 */
1756 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, ele_D);
1757 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, ele_C);
1758 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, ele_A);
1759
1760 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0,
1761 ele_D_ext);
1762 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0,
1763 ele_A_ext);
1764 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0,
1765 ele_C_ext);
1766 break;
1767 }
1768}
1769
1770static void rtw8723d_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index,
1771 u8 rf_path)
1772{
1773 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1774 s32 value32;
1775 u32 ofdm_swing;
1776
1777 if (ofdm_index >= RTW_OFDM_SWING_TABLE_SIZE)
1778 ofdm_index = RTW_OFDM_SWING_TABLE_SIZE - 1;
1779 else if (ofdm_index < 0)
1780 ofdm_index = 0;
1781
1782 ofdm_swing = rtw8723d_ofdm_swing_table[ofdm_index];
1783
1784 if (dm_info->iqk.done) {
1785 rtw8723d_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path);
1786 return;
1787 }
1788
1789 switch (rf_path) {
1790 case RF_PATH_A:
1791 default:
1792 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing);
1793 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
1794 0x00);
1795 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1796 value32 &= ~BIT_MASK_OFDM0_EXTS;
1797 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1798 break;
1799
1800 case RF_PATH_B:
1801 /* image S1:c80 to S0:Cd0 and Cd4 */
1802 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0,
1803 OFDM_SWING_A(ofdm_swing));
1804 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_B_S0,
1805 OFDM_SWING_B(ofdm_swing));
1806 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0,
1807 OFDM_SWING_C(ofdm_swing));
1808 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0,
1809 OFDM_SWING_D(ofdm_swing));
1810 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0);
1811 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0);
1812 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0);
1813 break;
1814 }
1815}
1816
1817static void rtw8723d_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx,
1818 s8 txagc_idx)
1819{
1820 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1821
1822 dm_info->txagc_remnant_ofdm = txagc_idx;
1823
1824 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A);
1825 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_B);
1826}
1827
1828static void rtw8723d_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx,
1829 s8 txagc_idx)
1830{
1831 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1832
1833 dm_info->txagc_remnant_cck = txagc_idx;
1834
1835 rtw_write32_mask(rtwdev, 0xab4, 0x000007FF,
1836 rtw8723d_cck_swing_table[swing_idx]);
1837}
1838
1839static void rtw8723d_pwrtrack_set(struct rtw_dev *rtwdev, u8 path)
1840{
1841 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1842 struct rtw_hal *hal = &rtwdev->hal;
1843 u8 limit_ofdm;
1844 u8 limit_cck = 40;
1845 s8 final_ofdm_swing_index;
1846 s8 final_cck_swing_index;
1847
1848 limit_ofdm = rtw8723d_pwrtrack_get_limit_ofdm(rtwdev);
1849
1850 final_ofdm_swing_index = RTW_DEF_OFDM_SWING_INDEX +
1851 dm_info->delta_power_index[path];
1852 final_cck_swing_index = RTW_DEF_CCK_SWING_INDEX +
1853 dm_info->delta_power_index[path];
1854
1855 if (final_ofdm_swing_index > limit_ofdm)
1856 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm,
1857 final_ofdm_swing_index - limit_ofdm);
1858 else if (final_ofdm_swing_index < 0)
1859 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, 0,
1860 final_ofdm_swing_index);
1861 else
1862 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0);
1863
1864 if (final_cck_swing_index > limit_cck)
1865 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, limit_cck,
1866 final_cck_swing_index - limit_cck);
1867 else if (final_cck_swing_index < 0)
1868 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, 0,
1869 final_cck_swing_index);
1870 else
1871 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0);
1872
1873 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel);
1874}
1875
1876static void rtw8723d_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path,
1877 u8 delta)
1878{
1879 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1880 const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl;
1881 const s8 *pwrtrk_xtal;
1882 s8 xtal_cap;
1883
1884 if (dm_info->thermal_avg[therm_path] >
1885 rtwdev->efuse.thermal_meter[therm_path])
1886 pwrtrk_xtal = tbl->pwrtrk_xtal_p;
1887 else
1888 pwrtrk_xtal = tbl->pwrtrk_xtal_n;
1889
1890 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;
1891 xtal_cap = clamp_t(s8, xtal_cap + pwrtrk_xtal[delta], 0, 0x3F);
1892 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,
1893 xtal_cap | (xtal_cap << 6));
1894}
1895
1896static void rtw8723d_phy_pwrtrack(struct rtw_dev *rtwdev)
1897{
1898 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1899 struct rtw_swing_table swing_table;
1900 u8 thermal_value, delta, path;
1901 bool do_iqk = false;
1902
1903 rtw_phy_config_swing_table(rtwdev, &swing_table);
1904
1905 if (rtwdev->efuse.thermal_meter[0] == 0xff)
1906 return;
1907
1908 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1909
1910 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1911
1912 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev);
1913
1914 if (do_iqk)
1915 rtw8723d_lck(rtwdev);
1916
1917 if (dm_info->pwr_trk_init_trigger)
1918 dm_info->pwr_trk_init_trigger = false;
1919 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1920 RF_PATH_A))
1921 goto iqk;
1922
1923 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1924
1925 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);
1926
1927 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1928 s8 delta_cur, delta_last;
1929
1930 delta_last = dm_info->delta_power_index[path];
1931 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table,
1932 path, RF_PATH_A, delta);
1933 if (delta_last == delta_cur)
1934 continue;
1935
1936 dm_info->delta_power_index[path] = delta_cur;
1937 rtw8723d_pwrtrack_set(rtwdev, path);
1938 }
1939
1940 rtw8723d_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta);
1941
1942iqk:
1943 if (do_iqk)
1944 rtw8723d_phy_calibration(rtwdev);
1945}
1946
1947static void rtw8723d_pwr_track(struct rtw_dev *rtwdev)
1948{
1949 struct rtw_efuse *efuse = &rtwdev->efuse;
1950 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1951
1952 if (efuse->power_track_type != 0)
1953 return;
1954
1955 if (!dm_info->pwr_trk_triggered) {
1956 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1957 GENMASK(17, 16), 0x03);
1958 dm_info->pwr_trk_triggered = true;
1959 return;
1960 }
1961
1962 rtw8723d_phy_pwrtrack(rtwdev);
1963 dm_info->pwr_trk_triggered = false;
1964}
1965
1966static void rtw8723d_fill_txdesc_checksum(struct rtw_dev *rtwdev,
1967 struct rtw_tx_pkt_info *pkt_info,
1968 u8 *txdesc)
1969{
1970 size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */
1971 __le16 chksum = 0;
1972 __le16 *data = (__le16 *)(txdesc);
1973 struct rtw_tx_desc *tx_desc = (struct rtw_tx_desc *)txdesc;
1974
1975 le32p_replace_bits(&tx_desc->w7, 0, RTW_TX_DESC_W7_TXDESC_CHECKSUM);
1976
1977 while (words--)
1978 chksum ^= *data++;
1979
1980 chksum = ~chksum;
1981
1982 le32p_replace_bits(&tx_desc->w7, __le16_to_cpu(chksum),
1983 RTW_TX_DESC_W7_TXDESC_CHECKSUM);
1984}
1985
1986static struct rtw_chip_ops rtw8723d_ops = {
1987 .phy_set_param = rtw8723d_phy_set_param,
1988 .read_efuse = rtw8723d_read_efuse,
1989 .query_rx_desc = rtw8723d_query_rx_desc,
1990 .set_channel = rtw8723d_set_channel,
1991 .mac_init = rtw8723d_mac_init,
1992 .shutdown = rtw8723d_shutdown,
1993 .read_rf = rtw_phy_read_rf_sipi,
1994 .write_rf = rtw_phy_write_rf_reg_sipi,
1995 .set_tx_power_index = rtw8723d_set_tx_power_index,
1996 .set_antenna = NULL,
1997 .cfg_ldo25 = rtw8723d_cfg_ldo25,
1998 .efuse_grant = rtw8723d_efuse_grant,
1999 .false_alarm_statistics = rtw8723d_false_alarm_statistics,
2000 .phy_calibration = rtw8723d_phy_calibration,
2001 .cck_pd_set = rtw8723d_phy_cck_pd_set,
2002 .pwr_track = rtw8723d_pwr_track,
2003 .config_bfee = NULL,
2004 .set_gid_table = NULL,
2005 .cfg_csi_rate = NULL,
2006 .fill_txdesc_checksum = rtw8723d_fill_txdesc_checksum,
2007
2008 .coex_set_init = rtw8723d_coex_cfg_init,
2009 .coex_set_ant_switch = NULL,
2010 .coex_set_gnt_fix = rtw8723d_coex_cfg_gnt_fix,
2011 .coex_set_gnt_debug = rtw8723d_coex_cfg_gnt_debug,
2012 .coex_set_rfe_type = rtw8723d_coex_cfg_rfe_type,
2013 .coex_set_wl_tx_power = rtw8723d_coex_cfg_wl_tx_power,
2014 .coex_set_wl_rx_gain = rtw8723d_coex_cfg_wl_rx_gain,
2015};
2016
2017/* Shared-Antenna Coex Table */
2018static const struct coex_table_para table_sant_8723d[] = {
2019 {0xffffffff, 0xffffffff}, /* case-0 */
2020 {0x55555555, 0x55555555},
2021 {0x66555555, 0x66555555},
2022 {0xaaaaaaaa, 0xaaaaaaaa},
2023 {0x5a5a5a5a, 0x5a5a5a5a},
2024 {0xfafafafa, 0xfafafafa}, /* case-5 */
2025 {0x6a5a5555, 0xaaaaaaaa},
2026 {0x6a5a56aa, 0x6a5a56aa},
2027 {0x6a5a5a5a, 0x6a5a5a5a},
2028 {0x66555555, 0x5a5a5a5a},
2029 {0x66555555, 0x6a5a5a5a}, /* case-10 */
2030 {0x66555555, 0x6a5a5aaa},
2031 {0x66555555, 0x5a5a5aaa},
2032 {0x66555555, 0x6aaa5aaa},
2033 {0x66555555, 0xaaaa5aaa},
2034 {0x66555555, 0xaaaaaaaa}, /* case-15 */
2035 {0xffff55ff, 0xfafafafa},
2036 {0xffff55ff, 0x6afa5afa},
2037 {0xaaffffaa, 0xfafafafa},
2038 {0xaa5555aa, 0x5a5a5a5a},
2039 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2040 {0xaa5555aa, 0xaaaaaaaa},
2041 {0xffffffff, 0x5a5a5a5a},
2042 {0xffffffff, 0x5a5a5a5a},
2043 {0xffffffff, 0x55555555},
2044 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
2045 {0x55555555, 0x5a5a5a5a},
2046 {0x55555555, 0xaaaaaaaa},
2047 {0x55555555, 0x6a5a6a5a},
2048 {0x66556655, 0x66556655},
2049 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2050 {0xffffffff, 0x5aaa5aaa},
2051 {0x56555555, 0x5a5a5aaa},
2052};
2053
2054/* Non-Shared-Antenna Coex Table */
2055static const struct coex_table_para table_nsant_8723d[] = {
2056 {0xffffffff, 0xffffffff}, /* case-100 */
2057 {0x55555555, 0x55555555},
2058 {0x66555555, 0x66555555},
2059 {0xaaaaaaaa, 0xaaaaaaaa},
2060 {0x5a5a5a5a, 0x5a5a5a5a},
2061 {0xfafafafa, 0xfafafafa}, /* case-105 */
2062 {0x5afa5afa, 0x5afa5afa},
2063 {0x55555555, 0xfafafafa},
2064 {0x66555555, 0xfafafafa},
2065 {0x66555555, 0x5a5a5a5a},
2066 {0x66555555, 0x6a5a5a5a}, /* case-110 */
2067 {0x66555555, 0xaaaaaaaa},
2068 {0xffff55ff, 0xfafafafa},
2069 {0xffff55ff, 0x5afa5afa},
2070 {0xffff55ff, 0xaaaaaaaa},
2071 {0xffff55ff, 0xffff55ff}, /* case-115 */
2072 {0xaaffffaa, 0x5afa5afa},
2073 {0xaaffffaa, 0xaaaaaaaa},
2074 {0xffffffff, 0xfafafafa},
2075 {0xffffffff, 0x5afa5afa},
2076 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
2077 {0x55ff55ff, 0x5afa5afa},
2078 {0x55ff55ff, 0xaaaaaaaa},
2079 {0x55ff55ff, 0x55ff55ff}
2080};
2081
2082/* Shared-Antenna TDMA */
2083static const struct coex_tdma_para tdma_sant_8723d[] = {
2084 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2085 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
2086 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2087 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2088 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2089 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2090 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2091 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2092 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2093 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2094 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2095 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2096 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2097 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2098 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2099 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2100 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2101 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2102 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2103 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2104 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2105 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
2106 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
2107 { {0x55, 0x08, 0x03, 0x10, 0x54} },
2108 { {0x65, 0x10, 0x03, 0x11, 0x10} },
2109 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2110 { {0x51, 0x08, 0x03, 0x10, 0x50} },
2111 { {0x61, 0x08, 0x03, 0x11, 0x11} }
2112};
2113
2114/* Non-Shared-Antenna TDMA */
2115static const struct coex_tdma_para tdma_nsant_8723d[] = {
2116 { {0x00, 0x00, 0x00, 0x00, 0x01} }, /* case-100 */
2117 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
2118 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2119 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2120 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2121 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2122 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2123 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2124 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2125 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2126 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2127 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2128 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2129 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2130 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2131 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2132 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2133 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2134 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2135 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2136 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
2137 { {0x51, 0x08, 0x03, 0x10, 0x50} }
2138};
2139
2140/* rssi in percentage % (dbm = % - 100) */
2141static const u8 wl_rssi_step_8723d[] = {60, 50, 44, 30};
2142static const u8 bt_rssi_step_8723d[] = {30, 30, 30, 30};
2143static const struct coex_5g_afh_map afh_5g_8723d[] = { {0, 0, 0} };
2144
2145static const struct rtw_hw_reg btg_reg_8723d = {
2146 .addr = REG_BTG_SEL, .mask = BIT_MASK_BTG_WL,
2147};
2148
2149/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
2150static const struct coex_rf_para rf_para_tx_8723d[] = {
2151 {0, 0, false, 7}, /* for normal */
2152 {0, 10, false, 7}, /* for WL-CPT */
2153 {1, 0, true, 4},
2154 {1, 2, true, 4},
2155 {1, 10, true, 4},
2156 {1, 15, true, 4}
2157};
2158
2159static const struct coex_rf_para rf_para_rx_8723d[] = {
2160 {0, 0, false, 7}, /* for normal */
2161 {0, 10, false, 7}, /* for WL-CPT */
2162 {1, 0, true, 5},
2163 {1, 2, true, 5},
2164 {1, 10, true, 5},
2165 {1, 15, true, 5}
2166};
2167
2168static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8723d[] = {
2169 {0x0005,
2170 RTW_PWR_CUT_ALL_MSK,
2171 RTW_PWR_INTF_ALL_MSK,
2172 RTW_PWR_ADDR_MAC,
2173 RTW_PWR_CMD_WRITE, BIT(3) | BIT(7), 0},
2174 {0x0086,
2175 RTW_PWR_CUT_ALL_MSK,
2176 RTW_PWR_INTF_SDIO_MSK,
2177 RTW_PWR_ADDR_SDIO,
2178 RTW_PWR_CMD_WRITE, BIT(0), 0},
2179 {0x0086,
2180 RTW_PWR_CUT_ALL_MSK,
2181 RTW_PWR_INTF_SDIO_MSK,
2182 RTW_PWR_ADDR_SDIO,
2183 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
2184 {0x004A,
2185 RTW_PWR_CUT_ALL_MSK,
2186 RTW_PWR_INTF_USB_MSK,
2187 RTW_PWR_ADDR_MAC,
2188 RTW_PWR_CMD_WRITE, BIT(0), 0},
2189 {0x0005,
2190 RTW_PWR_CUT_ALL_MSK,
2191 RTW_PWR_INTF_ALL_MSK,
2192 RTW_PWR_ADDR_MAC,
2193 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
2194 {0x0023,
2195 RTW_PWR_CUT_ALL_MSK,
2196 RTW_PWR_INTF_SDIO_MSK,
2197 RTW_PWR_ADDR_MAC,
2198 RTW_PWR_CMD_WRITE, BIT(4), 0},
2199 {0x0301,
2200 RTW_PWR_CUT_ALL_MSK,
2201 RTW_PWR_INTF_PCI_MSK,
2202 RTW_PWR_ADDR_MAC,
2203 RTW_PWR_CMD_WRITE, 0xFF, 0},
2204 {0xFFFF,
2205 RTW_PWR_CUT_ALL_MSK,
2206 RTW_PWR_INTF_ALL_MSK,
2207 0,
2208 RTW_PWR_CMD_END, 0, 0},
2209};
2210
2211static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8723d[] = {
2212 {0x0020,
2213 RTW_PWR_CUT_ALL_MSK,
2214 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
2215 RTW_PWR_ADDR_MAC,
2216 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2217 {0x0001,
2218 RTW_PWR_CUT_ALL_MSK,
2219 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
2220 RTW_PWR_ADDR_MAC,
2221 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
2222 {0x0000,
2223 RTW_PWR_CUT_ALL_MSK,
2224 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
2225 RTW_PWR_ADDR_MAC,
2226 RTW_PWR_CMD_WRITE, BIT(5), 0},
2227 {0x0005,
2228 RTW_PWR_CUT_ALL_MSK,
2229 RTW_PWR_INTF_ALL_MSK,
2230 RTW_PWR_ADDR_MAC,
2231 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
2232 {0x0075,
2233 RTW_PWR_CUT_ALL_MSK,
2234 RTW_PWR_INTF_PCI_MSK,
2235 RTW_PWR_ADDR_MAC,
2236 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2237 {0x0006,
2238 RTW_PWR_CUT_ALL_MSK,
2239 RTW_PWR_INTF_ALL_MSK,
2240 RTW_PWR_ADDR_MAC,
2241 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
2242 {0x0075,
2243 RTW_PWR_CUT_ALL_MSK,
2244 RTW_PWR_INTF_PCI_MSK,
2245 RTW_PWR_ADDR_MAC,
2246 RTW_PWR_CMD_WRITE, BIT(0), 0},
2247 {0x0006,
2248 RTW_PWR_CUT_ALL_MSK,
2249 RTW_PWR_INTF_ALL_MSK,
2250 RTW_PWR_ADDR_MAC,
2251 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2252 {0x0005,
2253 RTW_PWR_CUT_ALL_MSK,
2254 RTW_PWR_INTF_ALL_MSK,
2255 RTW_PWR_ADDR_MAC,
2256 RTW_PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0},
2257 {0x0005,
2258 RTW_PWR_CUT_ALL_MSK,
2259 RTW_PWR_INTF_ALL_MSK,
2260 RTW_PWR_ADDR_MAC,
2261 RTW_PWR_CMD_WRITE, BIT(7), 0},
2262 {0x0005,
2263 RTW_PWR_CUT_ALL_MSK,
2264 RTW_PWR_INTF_ALL_MSK,
2265 RTW_PWR_ADDR_MAC,
2266 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
2267 {0x0005,
2268 RTW_PWR_CUT_ALL_MSK,
2269 RTW_PWR_INTF_ALL_MSK,
2270 RTW_PWR_ADDR_MAC,
2271 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2272 {0x0005,
2273 RTW_PWR_CUT_ALL_MSK,
2274 RTW_PWR_INTF_ALL_MSK,
2275 RTW_PWR_ADDR_MAC,
2276 RTW_PWR_CMD_POLLING, BIT(0), 0},
2277 {0x0010,
2278 RTW_PWR_CUT_ALL_MSK,
2279 RTW_PWR_INTF_ALL_MSK,
2280 RTW_PWR_ADDR_MAC,
2281 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
2282 {0x0049,
2283 RTW_PWR_CUT_ALL_MSK,
2284 RTW_PWR_INTF_ALL_MSK,
2285 RTW_PWR_ADDR_MAC,
2286 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
2287 {0x0063,
2288 RTW_PWR_CUT_ALL_MSK,
2289 RTW_PWR_INTF_ALL_MSK,
2290 RTW_PWR_ADDR_MAC,
2291 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
2292 {0x0062,
2293 RTW_PWR_CUT_ALL_MSK,
2294 RTW_PWR_INTF_ALL_MSK,
2295 RTW_PWR_ADDR_MAC,
2296 RTW_PWR_CMD_WRITE, BIT(1), 0},
2297 {0x0058,
2298 RTW_PWR_CUT_ALL_MSK,
2299 RTW_PWR_INTF_ALL_MSK,
2300 RTW_PWR_ADDR_MAC,
2301 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2302 {0x005A,
2303 RTW_PWR_CUT_ALL_MSK,
2304 RTW_PWR_INTF_ALL_MSK,
2305 RTW_PWR_ADDR_MAC,
2306 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
2307 {0x0068,
2308 RTW_PWR_CUT_TEST_MSK,
2309 RTW_PWR_INTF_ALL_MSK,
2310 RTW_PWR_ADDR_MAC,
2311 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
2312 {0x0069,
2313 RTW_PWR_CUT_ALL_MSK,
2314 RTW_PWR_INTF_ALL_MSK,
2315 RTW_PWR_ADDR_MAC,
2316 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
2317 {0x001f,
2318 RTW_PWR_CUT_ALL_MSK,
2319 RTW_PWR_INTF_ALL_MSK,
2320 RTW_PWR_ADDR_MAC,
2321 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
2322 {0x0077,
2323 RTW_PWR_CUT_ALL_MSK,
2324 RTW_PWR_INTF_ALL_MSK,
2325 RTW_PWR_ADDR_MAC,
2326 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
2327 {0x001f,
2328 RTW_PWR_CUT_ALL_MSK,
2329 RTW_PWR_INTF_ALL_MSK,
2330 RTW_PWR_ADDR_MAC,
2331 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
2332 {0x0077,
2333 RTW_PWR_CUT_ALL_MSK,
2334 RTW_PWR_INTF_ALL_MSK,
2335 RTW_PWR_ADDR_MAC,
2336 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
2337 {0xFFFF,
2338 RTW_PWR_CUT_ALL_MSK,
2339 RTW_PWR_INTF_ALL_MSK,
2340 0,
2341 RTW_PWR_CMD_END, 0, 0},
2342};
2343
2344static const struct rtw_pwr_seq_cmd *card_enable_flow_8723d[] = {
2345 trans_carddis_to_cardemu_8723d,
2346 trans_cardemu_to_act_8723d,
2347 NULL
2348};
2349
2350static const struct rtw_pwr_seq_cmd trans_act_to_lps_8723d[] = {
2351 {0x0301,
2352 RTW_PWR_CUT_ALL_MSK,
2353 RTW_PWR_INTF_PCI_MSK,
2354 RTW_PWR_ADDR_MAC,
2355 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
2356 {0x0522,
2357 RTW_PWR_CUT_ALL_MSK,
2358 RTW_PWR_INTF_ALL_MSK,
2359 RTW_PWR_ADDR_MAC,
2360 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
2361 {0x05F8,
2362 RTW_PWR_CUT_ALL_MSK,
2363 RTW_PWR_INTF_ALL_MSK,
2364 RTW_PWR_ADDR_MAC,
2365 RTW_PWR_CMD_POLLING, 0xFF, 0},
2366 {0x05F9,
2367 RTW_PWR_CUT_ALL_MSK,
2368 RTW_PWR_INTF_ALL_MSK,
2369 RTW_PWR_ADDR_MAC,
2370 RTW_PWR_CMD_POLLING, 0xFF, 0},
2371 {0x05FA,
2372 RTW_PWR_CUT_ALL_MSK,
2373 RTW_PWR_INTF_ALL_MSK,
2374 RTW_PWR_ADDR_MAC,
2375 RTW_PWR_CMD_POLLING, 0xFF, 0},
2376 {0x05FB,
2377 RTW_PWR_CUT_ALL_MSK,
2378 RTW_PWR_INTF_ALL_MSK,
2379 RTW_PWR_ADDR_MAC,
2380 RTW_PWR_CMD_POLLING, 0xFF, 0},
2381 {0x0002,
2382 RTW_PWR_CUT_ALL_MSK,
2383 RTW_PWR_INTF_ALL_MSK,
2384 RTW_PWR_ADDR_MAC,
2385 RTW_PWR_CMD_WRITE, BIT(0), 0},
2386 {0x0002,
2387 RTW_PWR_CUT_ALL_MSK,
2388 RTW_PWR_INTF_ALL_MSK,
2389 RTW_PWR_ADDR_MAC,
2390 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US},
2391 {0x0002,
2392 RTW_PWR_CUT_ALL_MSK,
2393 RTW_PWR_INTF_ALL_MSK,
2394 RTW_PWR_ADDR_MAC,
2395 RTW_PWR_CMD_WRITE, BIT(1), 0},
2396 {0x0100,
2397 RTW_PWR_CUT_ALL_MSK,
2398 RTW_PWR_INTF_ALL_MSK,
2399 RTW_PWR_ADDR_MAC,
2400 RTW_PWR_CMD_WRITE, 0xFF, 0x03},
2401 {0x0101,
2402 RTW_PWR_CUT_ALL_MSK,
2403 RTW_PWR_INTF_ALL_MSK,
2404 RTW_PWR_ADDR_MAC,
2405 RTW_PWR_CMD_WRITE, BIT(1), 0},
2406 {0x0093,
2407 RTW_PWR_CUT_ALL_MSK,
2408 RTW_PWR_INTF_SDIO_MSK,
2409 RTW_PWR_ADDR_MAC,
2410 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
2411 {0x0553,
2412 RTW_PWR_CUT_ALL_MSK,
2413 RTW_PWR_INTF_ALL_MSK,
2414 RTW_PWR_ADDR_MAC,
2415 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
2416 {0xFFFF,
2417 RTW_PWR_CUT_ALL_MSK,
2418 RTW_PWR_INTF_ALL_MSK,
2419 0,
2420 RTW_PWR_CMD_END, 0, 0},
2421};
2422
2423static const struct rtw_pwr_seq_cmd trans_act_to_pre_carddis_8723d[] = {
2424 {0x0003,
2425 RTW_PWR_CUT_ALL_MSK,
2426 RTW_PWR_INTF_ALL_MSK,
2427 RTW_PWR_ADDR_MAC,
2428 RTW_PWR_CMD_WRITE, BIT(2), 0},
2429 {0x0080,
2430 RTW_PWR_CUT_ALL_MSK,
2431 RTW_PWR_INTF_ALL_MSK,
2432 RTW_PWR_ADDR_MAC,
2433 RTW_PWR_CMD_WRITE, 0xFF, 0},
2434 {0xFFFF,
2435 RTW_PWR_CUT_ALL_MSK,
2436 RTW_PWR_INTF_ALL_MSK,
2437 0,
2438 RTW_PWR_CMD_END, 0, 0},
2439};
2440
2441static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8723d[] = {
2442 {0x0002,
2443 RTW_PWR_CUT_ALL_MSK,
2444 RTW_PWR_INTF_ALL_MSK,
2445 RTW_PWR_ADDR_MAC,
2446 RTW_PWR_CMD_WRITE, BIT(0), 0},
2447 {0x0049,
2448 RTW_PWR_CUT_ALL_MSK,
2449 RTW_PWR_INTF_ALL_MSK,
2450 RTW_PWR_ADDR_MAC,
2451 RTW_PWR_CMD_WRITE, BIT(1), 0},
2452 {0x0006,
2453 RTW_PWR_CUT_ALL_MSK,
2454 RTW_PWR_INTF_ALL_MSK,
2455 RTW_PWR_ADDR_MAC,
2456 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2457 {0x0005,
2458 RTW_PWR_CUT_ALL_MSK,
2459 RTW_PWR_INTF_ALL_MSK,
2460 RTW_PWR_ADDR_MAC,
2461 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
2462 {0x0005,
2463 RTW_PWR_CUT_ALL_MSK,
2464 RTW_PWR_INTF_ALL_MSK,
2465 RTW_PWR_ADDR_MAC,
2466 RTW_PWR_CMD_POLLING, BIT(1), 0},
2467 {0x0010,
2468 RTW_PWR_CUT_ALL_MSK,
2469 RTW_PWR_INTF_ALL_MSK,
2470 RTW_PWR_ADDR_MAC,
2471 RTW_PWR_CMD_WRITE, BIT(6), 0},
2472 {0x0000,
2473 RTW_PWR_CUT_ALL_MSK,
2474 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
2475 RTW_PWR_ADDR_MAC,
2476 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
2477 {0x0020,
2478 RTW_PWR_CUT_ALL_MSK,
2479 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
2480 RTW_PWR_ADDR_MAC,
2481 RTW_PWR_CMD_WRITE, BIT(0), 0},
2482 {0xFFFF,
2483 RTW_PWR_CUT_ALL_MSK,
2484 RTW_PWR_INTF_ALL_MSK,
2485 0,
2486 RTW_PWR_CMD_END, 0, 0},
2487};
2488
2489static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8723d[] = {
2490 {0x0007,
2491 RTW_PWR_CUT_ALL_MSK,
2492 RTW_PWR_INTF_SDIO_MSK,
2493 RTW_PWR_ADDR_MAC,
2494 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
2495 {0x0005,
2496 RTW_PWR_CUT_ALL_MSK,
2497 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
2498 RTW_PWR_ADDR_MAC,
2499 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
2500 {0x0005,
2501 RTW_PWR_CUT_ALL_MSK,
2502 RTW_PWR_INTF_PCI_MSK,
2503 RTW_PWR_ADDR_MAC,
2504 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
2505 {0x0005,
2506 RTW_PWR_CUT_ALL_MSK,
2507 RTW_PWR_INTF_PCI_MSK,
2508 RTW_PWR_ADDR_MAC,
2509 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},
2510 {0x004A,
2511 RTW_PWR_CUT_ALL_MSK,
2512 RTW_PWR_INTF_USB_MSK,
2513 RTW_PWR_ADDR_MAC,
2514 RTW_PWR_CMD_WRITE, BIT(0), 1},
2515 {0x0023,
2516 RTW_PWR_CUT_ALL_MSK,
2517 RTW_PWR_INTF_SDIO_MSK,
2518 RTW_PWR_ADDR_MAC,
2519 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
2520 {0x0086,
2521 RTW_PWR_CUT_ALL_MSK,
2522 RTW_PWR_INTF_SDIO_MSK,
2523 RTW_PWR_ADDR_SDIO,
2524 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2525 {0x0086,
2526 RTW_PWR_CUT_ALL_MSK,
2527 RTW_PWR_INTF_SDIO_MSK,
2528 RTW_PWR_ADDR_SDIO,
2529 RTW_PWR_CMD_POLLING, BIT(1), 0},
2530 {0xFFFF,
2531 RTW_PWR_CUT_ALL_MSK,
2532 RTW_PWR_INTF_ALL_MSK,
2533 0,
2534 RTW_PWR_CMD_END, 0, 0},
2535};
2536
2537static const struct rtw_pwr_seq_cmd trans_act_to_post_carddis_8723d[] = {
2538 {0x001D,
2539 RTW_PWR_CUT_ALL_MSK,
2540 RTW_PWR_INTF_ALL_MSK,
2541 RTW_PWR_ADDR_MAC,
2542 RTW_PWR_CMD_WRITE, BIT(0), 0},
2543 {0x001D,
2544 RTW_PWR_CUT_ALL_MSK,
2545 RTW_PWR_INTF_ALL_MSK,
2546 RTW_PWR_ADDR_MAC,
2547 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2548 {0x001C,
2549 RTW_PWR_CUT_ALL_MSK,
2550 RTW_PWR_INTF_ALL_MSK,
2551 RTW_PWR_ADDR_MAC,
2552 RTW_PWR_CMD_WRITE, 0xFF, 0x0E},
2553 {0xFFFF,
2554 RTW_PWR_CUT_ALL_MSK,
2555 RTW_PWR_INTF_ALL_MSK,
2556 0,
2557 RTW_PWR_CMD_END, 0, 0},
2558};
2559
2560static const struct rtw_pwr_seq_cmd *card_disable_flow_8723d[] = {
2561 trans_act_to_lps_8723d,
2562 trans_act_to_pre_carddis_8723d,
2563 trans_act_to_cardemu_8723d,
2564 trans_cardemu_to_carddis_8723d,
2565 trans_act_to_post_carddis_8723d,
2566 NULL
2567};
2568
2569static const struct rtw_page_table page_table_8723d[] = {
2570 {12, 2, 2, 0, 1},
2571 {12, 2, 2, 0, 1},
2572 {12, 2, 2, 0, 1},
2573 {12, 2, 2, 0, 1},
2574 {12, 2, 2, 0, 1},
2575};
2576
2577static const struct rtw_rqpn rqpn_table_8723d[] = {
2578 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2579 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2580 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
2581 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2582 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2583 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
2584 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2585 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
2586 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2587 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2588 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2589 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2590 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2591 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2592 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
2593};
2594
2595static const struct rtw_prioq_addrs prioq_addrs_8723d = {
2596 .prio[RTW_DMA_MAPPING_EXTRA] = {
2597 .rsvd = REG_RQPN_NPQ + 2, .avail = REG_RQPN_NPQ + 3,
2598 },
2599 .prio[RTW_DMA_MAPPING_LOW] = {
2600 .rsvd = REG_RQPN + 1, .avail = REG_FIFOPAGE_CTRL_2 + 1,
2601 },
2602 .prio[RTW_DMA_MAPPING_NORMAL] = {
2603 .rsvd = REG_RQPN_NPQ, .avail = REG_RQPN_NPQ + 1,
2604 },
2605 .prio[RTW_DMA_MAPPING_HIGH] = {
2606 .rsvd = REG_RQPN, .avail = REG_FIFOPAGE_CTRL_2,
2607 },
2608 .wsize = false,
2609};
2610
2611static const struct rtw_intf_phy_para pcie_gen1_param_8723d[] = {
2612 {0x0008, 0x4a22,
2613 RTW_IP_SEL_PHY,
2614 RTW_INTF_PHY_CUT_ALL,
2615 RTW_INTF_PHY_PLATFORM_ALL},
2616 {0x0009, 0x1000,
2617 RTW_IP_SEL_PHY,
2618 ~(RTW_INTF_PHY_CUT_A | RTW_INTF_PHY_CUT_B),
2619 RTW_INTF_PHY_PLATFORM_ALL},
2620 {0xFFFF, 0x0000,
2621 RTW_IP_SEL_PHY,
2622 RTW_INTF_PHY_CUT_ALL,
2623 RTW_INTF_PHY_PLATFORM_ALL},
2624};
2625
2626static const struct rtw_intf_phy_para_table phy_para_table_8723d = {
2627 .gen1_para = pcie_gen1_param_8723d,
2628 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8723d),
2629};
2630
2631static const struct rtw_hw_reg rtw8723d_dig[] = {
2632 [0] = { .addr = 0xc50, .mask = 0x7f },
2633 [1] = { .addr = 0xc50, .mask = 0x7f },
2634};
2635
2636static const struct rtw_hw_reg rtw8723d_dig_cck[] = {
2637 [0] = { .addr = 0xa0c, .mask = 0x3f00 },
2638};
2639
2640static const struct rtw_rf_sipi_addr rtw8723d_rf_sipi_addr[] = {
2641 [RF_PATH_A] = { .hssi_1 = 0x820, .lssi_read = 0x8a0,
2642 .hssi_2 = 0x824, .lssi_read_pi = 0x8b8},
2643 [RF_PATH_B] = { .hssi_1 = 0x828, .lssi_read = 0x8a4,
2644 .hssi_2 = 0x82c, .lssi_read_pi = 0x8bc},
2645};
2646
2647static const struct rtw_ltecoex_addr rtw8723d_ltecoex_addr = {
2648 .ctrl = REG_LTECOEX_CTRL,
2649 .wdata = REG_LTECOEX_WRITE_DATA,
2650 .rdata = REG_LTECOEX_READ_DATA,
2651};
2652
2653static const struct rtw_rfe_def rtw8723d_rfe_defs[] = {
2654 [0] = { .phy_pg_tbl = &rtw8723d_bb_pg_tbl,
2655 .txpwr_lmt_tbl = &rtw8723d_txpwr_lmt_tbl,},
2656};
2657
2658static const u8 rtw8723d_pwrtrk_2gb_n[] = {
2659 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2660 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10
2661};
2662
2663static const u8 rtw8723d_pwrtrk_2gb_p[] = {
2664 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2665 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10
2666};
2667
2668static const u8 rtw8723d_pwrtrk_2ga_n[] = {
2669 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2670 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10
2671};
2672
2673static const u8 rtw8723d_pwrtrk_2ga_p[] = {
2674 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2675 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10
2676};
2677
2678static const u8 rtw8723d_pwrtrk_2g_cck_b_n[] = {
2679 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2680 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11
2681};
2682
2683static const u8 rtw8723d_pwrtrk_2g_cck_b_p[] = {
2684 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2685 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11
2686};
2687
2688static const u8 rtw8723d_pwrtrk_2g_cck_a_n[] = {
2689 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2690 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11
2691};
2692
2693static const u8 rtw8723d_pwrtrk_2g_cck_a_p[] = {
2694 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2695 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11
2696};
2697
2698static const s8 rtw8723d_pwrtrk_xtal_n[] = {
2699 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2700 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2701};
2702
2703static const s8 rtw8723d_pwrtrk_xtal_p[] = {
2704 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2705 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16
2706};
2707
2708static const struct rtw_pwr_track_tbl rtw8723d_rtw_pwr_track_tbl = {
2709 .pwrtrk_2gb_n = rtw8723d_pwrtrk_2gb_n,
2710 .pwrtrk_2gb_p = rtw8723d_pwrtrk_2gb_p,
2711 .pwrtrk_2ga_n = rtw8723d_pwrtrk_2ga_n,
2712 .pwrtrk_2ga_p = rtw8723d_pwrtrk_2ga_p,
2713 .pwrtrk_2g_cckb_n = rtw8723d_pwrtrk_2g_cck_b_n,
2714 .pwrtrk_2g_cckb_p = rtw8723d_pwrtrk_2g_cck_b_p,
2715 .pwrtrk_2g_ccka_n = rtw8723d_pwrtrk_2g_cck_a_n,
2716 .pwrtrk_2g_ccka_p = rtw8723d_pwrtrk_2g_cck_a_p,
2717 .pwrtrk_xtal_p = rtw8723d_pwrtrk_xtal_p,
2718 .pwrtrk_xtal_n = rtw8723d_pwrtrk_xtal_n,
2719};
2720
2721static const struct rtw_reg_domain coex_info_hw_regs_8723d[] = {
2722 {0x948, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2723 {0x67, BIT(7), RTW_REG_DOMAIN_MAC8},
2724 {0, 0, RTW_REG_DOMAIN_NL},
2725 {0x964, BIT(1), RTW_REG_DOMAIN_MAC8},
2726 {0x864, BIT(0), RTW_REG_DOMAIN_MAC8},
2727 {0xab7, BIT(5), RTW_REG_DOMAIN_MAC8},
2728 {0xa01, BIT(7), RTW_REG_DOMAIN_MAC8},
2729 {0, 0, RTW_REG_DOMAIN_NL},
2730 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2731 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2732 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2733 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2734 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2735 {0, 0, RTW_REG_DOMAIN_NL},
2736 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2737 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2738 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2739 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2740 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2741};
2742
2743const struct rtw_chip_info rtw8723d_hw_spec = {
2744 .ops = &rtw8723d_ops,
2745 .id = RTW_CHIP_TYPE_8723D,
2746 .fw_name = "rtw88/rtw8723d_fw.bin",
2747 .wlan_cpu = RTW_WCPU_11N,
2748 .tx_pkt_desc_sz = 40,
2749 .tx_buf_desc_sz = 16,
2750 .rx_pkt_desc_sz = 24,
2751 .rx_buf_desc_sz = 8,
2752 .phy_efuse_size = 512,
2753 .log_efuse_size = 512,
2754 .ptct_efuse_size = 96 + 1,
2755 .txff_size = 32768,
2756 .rxff_size = 16384,
2757 .rsvd_drv_pg_num = 8,
2758 .txgi_factor = 1,
2759 .is_pwr_by_rate_dec = true,
2760 .max_power_index = 0x3f,
2761 .csi_buf_pg_num = 0,
2762 .band = RTW_BAND_2G,
2763 .page_size = TX_PAGE_SIZE,
2764 .dig_min = 0x20,
2765 .ht_supported = true,
2766 .vht_supported = false,
2767 .lps_deep_mode_supported = 0,
2768 .sys_func_en = 0xFD,
2769 .pwr_on_seq = card_enable_flow_8723d,
2770 .pwr_off_seq = card_disable_flow_8723d,
2771 .page_table = page_table_8723d,
2772 .rqpn_table = rqpn_table_8723d,
2773 .prioq_addrs = &prioq_addrs_8723d,
2774 .intf_table = &phy_para_table_8723d,
2775 .dig = rtw8723d_dig,
2776 .dig_cck = rtw8723d_dig_cck,
2777 .rf_sipi_addr = {0x840, 0x844},
2778 .rf_sipi_read_addr = rtw8723d_rf_sipi_addr,
2779 .fix_rf_phy_num = 2,
2780 .ltecoex_addr = &rtw8723d_ltecoex_addr,
2781 .mac_tbl = &rtw8723d_mac_tbl,
2782 .agc_tbl = &rtw8723d_agc_tbl,
2783 .bb_tbl = &rtw8723d_bb_tbl,
2784 .rf_tbl = {&rtw8723d_rf_a_tbl},
2785 .rfe_defs = rtw8723d_rfe_defs,
2786 .rfe_defs_size = ARRAY_SIZE(rtw8723d_rfe_defs),
2787 .rx_ldpc = false,
2788 .pwr_track_tbl = &rtw8723d_rtw_pwr_track_tbl,
2789 .iqk_threshold = 8,
2790 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
2791 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN,
2792
2793 .coex_para_ver = 0x2007022f,
2794 .bt_desired_ver = 0x2f,
2795 .scbd_support = true,
2796 .new_scbd10_def = true,
2797 .ble_hid_profile_support = false,
2798 .wl_mimo_ps_support = false,
2799 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
2800 .bt_rssi_type = COEX_BTRSSI_RATIO,
2801 .ant_isolation = 15,
2802 .rssi_tolerance = 2,
2803 .wl_rssi_step = wl_rssi_step_8723d,
2804 .bt_rssi_step = bt_rssi_step_8723d,
2805 .table_sant_num = ARRAY_SIZE(table_sant_8723d),
2806 .table_sant = table_sant_8723d,
2807 .table_nsant_num = ARRAY_SIZE(table_nsant_8723d),
2808 .table_nsant = table_nsant_8723d,
2809 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8723d),
2810 .tdma_sant = tdma_sant_8723d,
2811 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8723d),
2812 .tdma_nsant = tdma_nsant_8723d,
2813 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8723d),
2814 .wl_rf_para_tx = rf_para_tx_8723d,
2815 .wl_rf_para_rx = rf_para_rx_8723d,
2816 .bt_afh_span_bw20 = 0x20,
2817 .bt_afh_span_bw40 = 0x30,
2818 .afh_5g_num = ARRAY_SIZE(afh_5g_8723d),
2819 .afh_5g = afh_5g_8723d,
2820 .btg_reg = &btg_reg_8723d,
2821
2822 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8723d),
2823 .coex_info_hw_regs = coex_info_hw_regs_8723d,
2824};
2825EXPORT_SYMBOL(rtw8723d_hw_spec);
2826
2827MODULE_FIRMWARE("rtw88/rtw8723d_fw.bin");
2828
2829MODULE_AUTHOR("Realtek Corporation");
2830MODULE_DESCRIPTION("Realtek 802.11n wireless 8723d driver");
2831MODULE_LICENSE("Dual BSD/GPL");
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#include <linux/module.h>
6#include "main.h"
7#include "coex.h"
8#include "fw.h"
9#include "tx.h"
10#include "rx.h"
11#include "phy.h"
12#include "rtw8723x.h"
13#include "rtw8723d.h"
14#include "rtw8723d_table.h"
15#include "mac.h"
16#include "reg.h"
17#include "debug.h"
18
19#define WLAN_SLOT_TIME 0x09
20#define WLAN_RL_VAL 0x3030
21#define WLAN_BAR_VAL 0x0201ffff
22#define BIT_MASK_TBTT_HOLD 0x00000fff
23#define BIT_SHIFT_TBTT_HOLD 8
24#define BIT_MASK_TBTT_SETUP 0x000000ff
25#define BIT_SHIFT_TBTT_SETUP 0
26#define BIT_MASK_TBTT_MASK ((BIT_MASK_TBTT_HOLD << BIT_SHIFT_TBTT_HOLD) | \
27 (BIT_MASK_TBTT_SETUP << BIT_SHIFT_TBTT_SETUP))
28#define TBTT_TIME(s, h)((((s) & BIT_MASK_TBTT_SETUP) << BIT_SHIFT_TBTT_SETUP) |\
29 (((h) & BIT_MASK_TBTT_HOLD) << BIT_SHIFT_TBTT_HOLD))
30#define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80)
31#define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x64)
32#define WLAN_PIFS_VAL 0
33#define WLAN_AGG_BRK_TIME 0x16
34#define WLAN_NAV_PROT_LEN 0x0040
35#define WLAN_SPEC_SIFS 0x100a
36#define WLAN_RX_PKT_LIMIT 0x17
37#define WLAN_MAX_AGG_NR 0x0A
38#define WLAN_AMPDU_MAX_TIME 0x1C
39#define WLAN_ANT_SEL 0x82
40#define WLAN_LTR_IDLE_LAT 0x90039003
41#define WLAN_LTR_ACT_LAT 0x883c883c
42#define WLAN_LTR_CTRL1 0xCB004010
43#define WLAN_LTR_CTRL2 0x01233425
44
45static const u32 rtw8723d_ofdm_swing_table[] = {
46 0x0b40002d, 0x0c000030, 0x0cc00033, 0x0d800036, 0x0e400039, 0x0f00003c,
47 0x10000040, 0x11000044, 0x12000048, 0x1300004c, 0x14400051, 0x15800056,
48 0x16c0005b, 0x18000060, 0x19800066, 0x1b00006c, 0x1c800072, 0x1e400079,
49 0x20000080, 0x22000088, 0x24000090, 0x26000098, 0x288000a2, 0x2ac000ab,
50 0x2d4000b5, 0x300000c0, 0x32c000cb, 0x35c000d7, 0x390000e4, 0x3c8000f2,
51 0x40000100, 0x43c0010f, 0x47c0011f, 0x4c000130, 0x50800142, 0x55400155,
52 0x5a400169, 0x5fc0017f, 0x65400195, 0x6b8001ae, 0x71c001c7, 0x788001e2,
53 0x7f8001fe,
54};
55
56static const u32 rtw8723d_cck_swing_table[] = {
57 0x0CD, 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158,
58 0x16C, 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263,
59 0x287, 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F,
60 0x47F, 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C,
61 0x7FF,
62};
63
64#define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_ofdm_swing_table)
65#define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_cck_swing_table)
66
67static void rtw8723d_pwrtrack_init(struct rtw_dev *rtwdev)
68{
69 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
70 u8 path;
71
72 dm_info->default_ofdm_index = RTW_DEF_OFDM_SWING_INDEX;
73
74 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
75 ewma_thermal_init(&dm_info->avg_thermal[path]);
76 dm_info->delta_power_index[path] = 0;
77 }
78 dm_info->pwr_trk_triggered = false;
79 dm_info->pwr_trk_init_trigger = true;
80 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
81 dm_info->txagc_remnant_cck = 0;
82 dm_info->txagc_remnant_ofdm[RF_PATH_A] = 0;
83}
84
85static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev)
86{
87 u8 xtal_cap;
88 u32 val32;
89
90 /* power on BB/RF domain */
91 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN,
92 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
93 rtw_write8_set(rtwdev, REG_RF_CTRL,
94 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
95 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80);
96
97 rtw_phy_load_tables(rtwdev);
98
99 /* post init after header files config */
100 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF);
101 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, BIT_HIQ_NO_LMT_EN_ROOT);
102 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN);
103
104 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;
105 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,
106 xtal_cap | (xtal_cap << 6));
107 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN);
108 if ((rtwdev->efuse.afe >> 4) == 14) {
109 rtw_write32_set(rtwdev, REG_AFE_CTRL3, BIT_XTAL_GMP_BIT4);
110 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BITS_PLL);
111 rtw_write32_set(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA1);
112 rtw_write32_clr(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA0);
113 }
114
115 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
116 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
117 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL);
118 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL);
119 rtw_write8(rtwdev, REG_ATIMWND, 0x2);
120 rtw_write8(rtwdev, REG_BCN_CTRL,
121 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT);
122 val32 = rtw_read32(rtwdev, REG_TBTT_PROHIBIT);
123 val32 &= ~BIT_MASK_TBTT_MASK;
124 val32 |= WLAN_TBTT_TIME_STOP_BCN;
125 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, val32);
126 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL);
127 rtw_write8(rtwdev, REG_AGGR_BREAK_TIME, WLAN_AGG_BRK_TIME);
128 rtw_write16(rtwdev, REG_NAV_PROT_LEN, WLAN_NAV_PROT_LEN);
129 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS);
130 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS);
131 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS);
132 rtw_write8(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU);
133 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT);
134 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR);
135 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME);
136 rtw_write8(rtwdev, REG_LEDCFG2, WLAN_ANT_SEL);
137
138 rtw_write32(rtwdev, REG_LTR_IDLE_LATENCY, WLAN_LTR_IDLE_LAT);
139 rtw_write32(rtwdev, REG_LTR_ACTIVE_LATENCY, WLAN_LTR_ACT_LAT);
140 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC, WLAN_LTR_CTRL1);
141 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC + 4, WLAN_LTR_CTRL2);
142
143 rtw_phy_init(rtwdev);
144 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
145
146 rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN);
147
148 rtw8723x_lck(rtwdev);
149
150 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
151 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);
152
153 rtw8723d_pwrtrack_init(rtwdev);
154}
155
156static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
157 struct rtw_rx_pkt_stat *pkt_stat)
158{
159 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
160 s8 min_rx_power = -120;
161 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status);
162
163 pkt_stat->rx_power[RF_PATH_A] = pwdb - 97;
164 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
165 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
166 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
167 min_rx_power);
168 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
169}
170
171static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
172 struct rtw_rx_pkt_stat *pkt_stat)
173{
174 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
175 u8 rxsc, bw;
176 s8 min_rx_power = -120;
177 s8 rx_evm;
178
179 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
180 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
181 else
182 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
183
184 if (GET_PHY_STAT_P1_RF_MODE(phy_status) == 0)
185 bw = RTW_CHANNEL_WIDTH_20;
186 else if ((rxsc == 1) || (rxsc == 2))
187 bw = RTW_CHANNEL_WIDTH_20;
188 else
189 bw = RTW_CHANNEL_WIDTH_40;
190
191 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
192 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
193 pkt_stat->bw = bw;
194 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
195 min_rx_power);
196 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
197 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
198 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
199
200 dm_info->curr_rx_rate = pkt_stat->rate;
201 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
202 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1;
203 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1;
204
205 rx_evm = clamp_t(s8, -pkt_stat->rx_evm[RF_PATH_A] >> 1, 0, 64);
206 rx_evm &= 0x3F; /* 64->0: second path of 1SS rate is 64 */
207 dm_info->rx_evm_dbm[RF_PATH_A] = rx_evm;
208}
209
210static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
211 struct rtw_rx_pkt_stat *pkt_stat)
212{
213 u8 page;
214
215 page = *phy_status & 0xf;
216
217 switch (page) {
218 case 0:
219 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
220 break;
221 case 1:
222 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
223 break;
224 default:
225 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
226 return;
227 }
228}
229
230static bool rtw8723d_check_spur_ov_thres(struct rtw_dev *rtwdev,
231 u8 channel, u32 thres)
232{
233 u32 freq;
234 bool ret = false;
235
236 if (channel == 13)
237 freq = FREQ_CH13;
238 else if (channel == 14)
239 freq = FREQ_CH14;
240 else
241 return false;
242
243 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE);
244 rtw_write32(rtwdev, REG_PSDFN, freq);
245 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq);
246
247 msleep(30);
248 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres)
249 ret = true;
250
251 rtw_write32(rtwdev, REG_PSDFN, freq);
252 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE);
253
254 return ret;
255}
256
257static void rtw8723d_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch)
258{
259 if (!notch) {
260 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);
261 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
262 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
263 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
264 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
265 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
266 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
267 return;
268 }
269
270 switch (channel) {
271 case 13:
272 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);
273 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
274 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000);
275 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
276 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
277 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
278 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
279 break;
280 case 14:
281 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);
282 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
283 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
284 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
285 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
286 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000);
287 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
288 break;
289 default:
290 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
291 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
292 break;
293 }
294}
295
296static void rtw8723d_spur_cal(struct rtw_dev *rtwdev, u8 channel)
297{
298 bool notch;
299
300 if (channel < 13) {
301 rtw8723d_cfg_notch(rtwdev, channel, false);
302 return;
303 }
304
305 notch = rtw8723d_check_spur_ov_thres(rtwdev, channel, SPUR_THRES);
306 rtw8723d_cfg_notch(rtwdev, channel, notch);
307}
308
309static void rtw8723d_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
310{
311 u32 rf_cfgch_a, rf_cfgch_b;
312
313 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
314 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK);
315
316 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK;
317 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK;
318 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK);
319 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK);
320
321 rf_cfgch_a &= ~RFCFGCH_BW_MASK;
322 switch (bw) {
323 case RTW_CHANNEL_WIDTH_20:
324 rf_cfgch_a |= RFCFGCH_BW_20M;
325 break;
326 case RTW_CHANNEL_WIDTH_40:
327 rf_cfgch_a |= RFCFGCH_BW_40M;
328 break;
329 default:
330 break;
331 }
332
333 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a);
334 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b);
335
336 rtw8723d_spur_cal(rtwdev, channel);
337}
338
339static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR] = {
340 [0] = {
341 { .len = 4, .reg = 0xA24, .val = 0x64B80C1C },
342 { .len = 4, .reg = 0xA28, .val = 0x00008810 },
343 { .len = 4, .reg = 0xAAC, .val = 0x01235667 },
344 },
345 [1] = {
346 { .len = 4, .reg = 0xA24, .val = 0x0000B81C },
347 { .len = 4, .reg = 0xA28, .val = 0x00000000 },
348 { .len = 4, .reg = 0xAAC, .val = 0x00003667 },
349 },
350};
351
352static void rtw8723d_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
353 u8 primary_ch_idx)
354{
355 const struct rtw_backup_info *cck_dfir;
356 int i;
357
358 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1];
359
360 for (i = 0; i < CCK_DFIR_NR; i++, cck_dfir++)
361 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val);
362
363 switch (bw) {
364 case RTW_CHANNEL_WIDTH_20:
365 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);
366 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);
367 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 1);
368 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa);
369 break;
370 case RTW_CHANNEL_WIDTH_40:
371 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);
372 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);
373 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0);
374 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND,
375 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0));
376 break;
377 default:
378 break;
379 }
380}
381
382static void rtw8723d_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
383 u8 primary_chan_idx)
384{
385 rtw8723d_set_channel_rf(rtwdev, channel, bw);
386 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
387 rtw8723d_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
388}
389
390static void rtw8723d_shutdown(struct rtw_dev *rtwdev)
391{
392 rtw_write16_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS);
393}
394
395struct rtw_8723d_iqk_cfg {
396 const char *name;
397 u32 val_bb_sel_btg;
398 u32 reg_lutwe;
399 u32 val_txiqk_pi;
400 u32 reg_padlut;
401 u32 reg_gaintx;
402 u32 reg_bspad;
403 u32 val_wlint;
404 u32 val_wlsel;
405 u32 val_iqkpts;
406};
407
408static const struct rtw_8723d_iqk_cfg iqk_tx_cfg[PATH_NR] = {
409 [PATH_S1] = {
410 .name = "S1",
411 .val_bb_sel_btg = 0x99000000,
412 .reg_lutwe = RF_LUTWE,
413 .val_txiqk_pi = 0x8214019f,
414 .reg_padlut = RF_LUTDBG,
415 .reg_gaintx = RF_GAINTX,
416 .reg_bspad = RF_BSPAD,
417 .val_wlint = 0xe0d,
418 .val_wlsel = 0x60d,
419 .val_iqkpts = 0xfa000000,
420 },
421 [PATH_S0] = {
422 .name = "S0",
423 .val_bb_sel_btg = 0x99000280,
424 .reg_lutwe = RF_LUTWE2,
425 .val_txiqk_pi = 0x8214018a,
426 .reg_padlut = RF_TXADBG,
427 .reg_gaintx = RF_TRXIQ,
428 .reg_bspad = RF_TXATANK,
429 .val_wlint = 0xe6d,
430 .val_wlsel = 0x66d,
431 .val_iqkpts = 0xf9000000,
432 },
433};
434
435static u8 rtw8723d_iqk_check_tx_failed(struct rtw_dev *rtwdev,
436 const struct rtw_8723d_iqk_cfg *iqk_cfg)
437{
438 s32 tx_x, tx_y;
439 u32 tx_fail;
440
441 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n",
442 rtw_read32(rtwdev, REG_IQK_RES_RY));
443 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n",
444 rtw_read32(rtwdev, REG_IQK_RES_TX),
445 rtw_read32(rtwdev, REG_IQK_RES_TY));
446 rtw_dbg(rtwdev, RTW_DBG_RFK,
447 "[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
448 rtw_read32(rtwdev, 0xe90),
449 rtw_read32(rtwdev, 0xe98));
450
451 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL);
452 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
453 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
454
455 if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR)
456 return IQK_TX_OK;
457
458 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s TXIQK is failed\n",
459 iqk_cfg->name);
460
461 return 0;
462}
463
464static u8 rtw8723d_iqk_check_rx_failed(struct rtw_dev *rtwdev,
465 const struct rtw_8723d_iqk_cfg *iqk_cfg)
466{
467 s32 rx_x, rx_y;
468 u32 rx_fail;
469
470 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n",
471 rtw_read32(rtwdev, REG_IQK_RES_RX),
472 rtw_read32(rtwdev, REG_IQK_RES_RY));
473
474 rtw_dbg(rtwdev, RTW_DBG_RFK,
475 "[IQK] 0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",
476 rtw_read32(rtwdev, 0xea0),
477 rtw_read32(rtwdev, 0xea8));
478
479 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL);
480 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
481 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
482 rx_y = abs(iqkxy_to_s32(rx_y));
483
484 if (!rx_fail && rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER &&
485 rx_y < IQK_RX_Y_LMT)
486 return IQK_RX_OK;
487
488 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s RXIQK STEP2 is failed\n",
489 iqk_cfg->name);
490
491 return 0;
492}
493
494#define IQK_LTE_WRITE_VAL_8723D 0x0000ff00
495
496static void rtw8723d_iqk_one_shot(struct rtw_dev *rtwdev, bool tx,
497 const struct rtw_8723d_iqk_cfg *iqk_cfg)
498{
499 u32 pts = (tx ? iqk_cfg->val_iqkpts : 0xf9000000);
500
501 /* enter IQK mode */
502 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);
503 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8723D);
504
505 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0054);
506 mdelay(1);
507 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] GNT_BT @%s %sIQK1 = 0x%x\n",
508 iqk_cfg->name, tx ? "TX" : "RX",
509 rtw_read32(rtwdev, REG_LTECOEX_READ_DATA));
510 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x948 @%s %sIQK1 = 0x%x\n",
511 iqk_cfg->name, tx ? "TX" : "RX",
512 rtw_read32(rtwdev, REG_BB_SEL_BTG));
513
514 /* One shot, LOK & IQK */
515 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, pts);
516 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000);
517
518 if (!check_hw_ready(rtwdev, REG_IQK_RES_RY, BIT_IQK_DONE, 1))
519 rtw_warn(rtwdev, "%s %s IQK isn't done\n", iqk_cfg->name,
520 tx ? "TX" : "RX");
521}
522
523static void rtw8723d_iqk_txrx_path_post(struct rtw_dev *rtwdev,
524 const struct rtw_8723d_iqk_cfg *iqk_cfg,
525 const struct rtw8723x_iqk_backup_regs *backup)
526{
527 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, backup);
528 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg);
529
530 /* leave IQK mode */
531 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
532 mdelay(1);
533 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x0);
534 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, BIT(0), 0x0);
535 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, BIT(0), 0x0);
536}
537
538static u8 rtw8723d_iqk_tx_path(struct rtw_dev *rtwdev,
539 const struct rtw_8723d_iqk_cfg *iqk_cfg,
540 const struct rtw8723x_iqk_backup_regs *backup)
541{
542 u8 status;
543
544 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s TXIQK!!\n", iqk_cfg->name);
545 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s TXIQK = 0x%x\n",
546 iqk_cfg->name,
547 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
548
549 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg);
550 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
551 mdelay(1);
552 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000);
553 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00004);
554 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005d);
555 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xBFFE0);
556 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
557
558 /* IQK setting */
559 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x08008c0c);
560 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
561 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, iqk_cfg->val_txiqk_pi);
562 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160200);
563 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
564 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
565
566 /* LOK setting */
567 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911);
568
569 /* PA, PAD setting */
570 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1);
571 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0);
572 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x1E0, 0x3);
573 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXIQGEN, 0x1F, 0xf);
574
575 /* LOK setting for 8723D */
576 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x10, 0x1);
577 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_bspad, 0x1, 0x1);
578
579 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint);
580 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel);
581
582 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s TXIQK = 0x%x\n",
583 iqk_cfg->name,
584 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK));
585 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s TXIQK = 0x%x\n",
586 iqk_cfg->name,
587 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK));
588
589 rtw8723d_iqk_one_shot(rtwdev, true, iqk_cfg);
590 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg);
591
592 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup);
593
594 return status;
595}
596
597static u8 rtw8723d_iqk_rx_path(struct rtw_dev *rtwdev,
598 const struct rtw_8723d_iqk_cfg *iqk_cfg,
599 const struct rtw8723x_iqk_backup_regs *backup)
600{
601 u32 tx_x, tx_y;
602 u8 status;
603
604 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK Step1!!\n",
605 iqk_cfg->name);
606 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK1 = 0x%x\n",
607 iqk_cfg->name,
608 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
609 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg);
610
611 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
612
613 /* IQK setting */
614 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
615 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
616
617 /* path IQK setting */
618 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);
619 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
620 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
621 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
622 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82160000);
623 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160000);
624
625 /* LOK setting */
626 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911);
627
628 /* RXIQK mode */
629 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000);
630 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00006);
631 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f);
632 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xa7ffb);
633 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
634
635 /* PA/PAD=0 */
636 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1);
637 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0);
638 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint);
639 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel);
640
641 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1@ path %s RXIQK1 = 0x%x\n",
642 iqk_cfg->name,
643 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK));
644 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2@ path %s RXIQK1 = 0x%x\n",
645 iqk_cfg->name,
646 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK));
647
648 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg);
649 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg);
650
651 if (!status)
652 goto restore;
653
654 /* second round */
655 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
656 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
657
658 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y));
659 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n",
660 rtw_read32(rtwdev, REG_TXIQK_11N),
661 BIT_SET_TXIQK_11N(tx_x, tx_y));
662
663 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK STEP2!!\n",
664 iqk_cfg->name);
665 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK2 = 0x%x\n",
666 iqk_cfg->name,
667 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
668
669 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
670 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c);
671 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c);
672 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
673 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
674 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82170000);
675 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28171400);
676
677 /* LOK setting */
678 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1);
679
680 /* RXIQK mode */
681 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
682 mdelay(1);
683 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x80000, 0x1);
684 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00007);
685 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f);
686 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xb3fdb);
687 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
688
689 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s RXIQK2 = 0x%x\n",
690 iqk_cfg->name,
691 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK));
692 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s RXIQK2 = 0x%x\n",
693 iqk_cfg->name,
694 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK));
695
696 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg);
697 status |= rtw8723d_iqk_check_rx_failed(rtwdev, iqk_cfg);
698
699restore:
700 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup);
701
702 return status;
703}
704
705static
706void rtw8723d_iqk_fill_s1_matrix(struct rtw_dev *rtwdev, const s32 result[])
707{
708 s32 oldval_1;
709 s32 x, y;
710 s32 tx1_a, tx1_a_ext;
711 s32 tx1_c, tx1_c_ext;
712
713 if (result[IQK_S1_TX_X] == 0)
714 return;
715
716 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
717 BIT_MASK_TXIQ_ELM_D);
718
719 x = iqkxy_to_s32(result[IQK_S1_TX_X]);
720 tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext);
721 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
722 BIT_MASK_TXIQ_ELM_A, tx1_a);
723 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,
724 BIT_MASK_OFDM0_EXT_A, tx1_a_ext);
725
726 y = iqkxy_to_s32(result[IQK_S1_TX_Y]);
727 tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext);
728 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
729 BIT_SET_TXIQ_ELM_C1(tx1_c));
730 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
731 BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c));
732 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,
733 BIT_MASK_OFDM0_EXT_C, tx1_c_ext);
734
735 rtw_dbg(rtwdev, RTW_DBG_RFK,
736 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n",
737 x, tx1_a, oldval_1);
738 rtw_dbg(rtwdev, RTW_DBG_RFK,
739 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c);
740
741 if (result[IQK_S1_RX_X] == 0)
742 return;
743
744 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_X,
745 result[IQK_S1_RX_X]);
746 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_Y1,
747 BIT_SET_RXIQ_S1_Y1(result[IQK_S1_RX_Y]));
748 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2,
749 BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y]));
750}
751
752static
753void rtw8723d_iqk_fill_s0_matrix(struct rtw_dev *rtwdev, const s32 result[])
754{
755 s32 oldval_0;
756 s32 x, y;
757 s32 tx0_a, tx0_a_ext;
758 s32 tx0_c, tx0_c_ext;
759
760 if (result[IQK_S0_TX_X] == 0)
761 return;
762
763 oldval_0 = rtw_read32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0);
764
765 x = iqkxy_to_s32(result[IQK_S0_TX_X]);
766 tx0_a = iqk_mult(x, oldval_0, &tx0_a_ext);
767
768 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, tx0_a);
769 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, tx0_a_ext);
770
771 y = iqkxy_to_s32(result[IQK_S0_TX_Y]);
772 tx0_c = iqk_mult(y, oldval_0, &tx0_c_ext);
773
774 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, tx0_c);
775 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, tx0_c_ext);
776
777 if (result[IQK_S0_RX_X] == 0)
778 return;
779
780 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_X_S0,
781 result[IQK_S0_RX_X]);
782 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_Y_S0,
783 result[IQK_S0_RX_Y]);
784}
785
786static void rtw8723d_iqk_config_mac(struct rtw_dev *rtwdev)
787{
788 rtw_write8(rtwdev, REG_TXPAUSE, 0xff);
789}
790
791static
792void rtw8723d_iqk_rf_standby(struct rtw_dev *rtwdev, enum rtw_rf_path path)
793{
794 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path-%s standby mode!\n",
795 path == RF_PATH_A ? "S1" : "S0");
796
797 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
798 mdelay(1);
799 rtw_write_rf(rtwdev, path, RF_MODE, RFREG_MASK, 0x10000);
800 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);
801}
802
803#define ADDA_ON_VAL_8723D 0x03c00016
804
805static
806void rtw8723d_iqk_precfg_path(struct rtw_dev *rtwdev, enum rtw8723x_path path)
807{
808 if (path == PATH_S0) {
809 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_A);
810 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8723D);
811 }
812
813 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);
814 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
815 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
816
817 if (path == PATH_S1) {
818 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_B);
819 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8723D);
820 }
821}
822
823static
824void rtw8723d_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t,
825 const struct rtw8723x_iqk_backup_regs *backup)
826{
827 u32 i;
828 u8 s1_ok, s0_ok;
829
830 rtw_dbg(rtwdev, RTW_DBG_RFK,
831 "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t);
832
833 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8723D);
834 rtw8723d_iqk_config_mac(rtwdev);
835 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf);
836 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05611);
837 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4);
838 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204200);
839 rtw8723d_iqk_precfg_path(rtwdev, PATH_S1);
840
841 for (i = 0; i < PATH_IQK_RETRY; i++) {
842 s1_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup);
843 if (s1_ok == IQK_TX_OK) {
844 rtw_dbg(rtwdev, RTW_DBG_RFK,
845 "[IQK] path S1 Tx IQK Success!!\n");
846 result[t][IQK_S1_TX_X] =
847 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
848 result[t][IQK_S1_TX_Y] =
849 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
850 break;
851 }
852
853 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Tx IQK Fail!!\n");
854 result[t][IQK_S1_TX_X] = 0x100;
855 result[t][IQK_S1_TX_Y] = 0x0;
856 }
857
858 for (i = 0; i < PATH_IQK_RETRY; i++) {
859 s1_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup);
860 if (s1_ok == (IQK_TX_OK | IQK_RX_OK)) {
861 rtw_dbg(rtwdev, RTW_DBG_RFK,
862 "[IQK] path S1 Rx IQK Success!!\n");
863 result[t][IQK_S1_RX_X] =
864 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
865 result[t][IQK_S1_RX_Y] =
866 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
867 break;
868 }
869
870 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Rx IQK Fail!!\n");
871 result[t][IQK_S1_RX_X] = 0x100;
872 result[t][IQK_S1_RX_Y] = 0x0;
873 }
874
875 if (s1_ok == 0x0)
876 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 IQK is failed!!\n");
877
878 rtw8723d_iqk_precfg_path(rtwdev, PATH_S0);
879
880 for (i = 0; i < PATH_IQK_RETRY; i++) {
881 s0_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup);
882 if (s0_ok == IQK_TX_OK) {
883 rtw_dbg(rtwdev, RTW_DBG_RFK,
884 "[IQK] path S0 Tx IQK Success!!\n");
885 result[t][IQK_S0_TX_X] =
886 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
887 result[t][IQK_S0_TX_Y] =
888 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
889 break;
890 }
891
892 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Tx IQK Fail!!\n");
893 result[t][IQK_S0_TX_X] = 0x100;
894 result[t][IQK_S0_TX_Y] = 0x0;
895 }
896
897 for (i = 0; i < PATH_IQK_RETRY; i++) {
898 s0_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup);
899 if (s0_ok == (IQK_TX_OK | IQK_RX_OK)) {
900 rtw_dbg(rtwdev, RTW_DBG_RFK,
901 "[IQK] path S0 Rx IQK Success!!\n");
902
903 result[t][IQK_S0_RX_X] =
904 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
905 result[t][IQK_S0_RX_Y] =
906 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
907 break;
908 }
909
910 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Rx IQK Fail!!\n");
911 result[t][IQK_S0_RX_X] = 0x100;
912 result[t][IQK_S0_RX_Y] = 0x0;
913 }
914
915 if (s0_ok == 0x0)
916 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 IQK is failed!!\n");
917
918 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
919 mdelay(1);
920
921 rtw_dbg(rtwdev, RTW_DBG_RFK,
922 "[IQK] back to BB mode, load original value!\n");
923}
924
925static void rtw8723d_phy_calibration(struct rtw_dev *rtwdev)
926{
927 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
928 s32 result[IQK_ROUND_SIZE][IQK_NR];
929 struct rtw8723x_iqk_backup_regs backup;
930 u8 i, j;
931 u8 final_candidate = IQK_ROUND_INVALID;
932 bool good;
933
934 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!!!\n");
935
936 memset(result, 0, sizeof(result));
937
938 rtw8723x_iqk_backup_path_ctrl(rtwdev, &backup);
939 rtw8723x_iqk_backup_lte_path_gnt(rtwdev, &backup);
940 rtw8723x_iqk_backup_regs(rtwdev, &backup);
941
942 for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) {
943 rtw8723x_iqk_config_path_ctrl(rtwdev);
944 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8723D);
945
946 rtw8723d_iqk_one_round(rtwdev, result, i, &backup);
947
948 if (i > IQK_ROUND_0)
949 rtw8723x_iqk_restore_regs(rtwdev, &backup);
950 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, &backup);
951 rtw8723x_iqk_restore_path_ctrl(rtwdev, &backup);
952
953 for (j = IQK_ROUND_0; j < i; j++) {
954 good = rtw8723x_iqk_similarity_cmp(rtwdev, result, j, i);
955
956 if (good) {
957 final_candidate = j;
958 rtw_dbg(rtwdev, RTW_DBG_RFK,
959 "[IQK] cmp %d:%d final_candidate is %x\n",
960 j, i, final_candidate);
961 goto iqk_done;
962 }
963 }
964 }
965
966 if (final_candidate == IQK_ROUND_INVALID) {
967 s32 reg_tmp = 0;
968
969 for (i = 0; i < IQK_NR; i++)
970 reg_tmp += result[IQK_ROUND_HYBRID][i];
971
972 if (reg_tmp != 0) {
973 final_candidate = IQK_ROUND_HYBRID;
974 } else {
975 WARN(1, "IQK is failed\n");
976 goto out;
977 }
978 }
979
980iqk_done:
981 rtw8723d_iqk_fill_s1_matrix(rtwdev, result[final_candidate]);
982 rtw8723d_iqk_fill_s0_matrix(rtwdev, result[final_candidate]);
983
984 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X];
985 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y];
986 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X];
987 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y];
988 dm_info->iqk.done = true;
989
990out:
991 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg);
992
993 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n",
994 final_candidate);
995
996 for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++)
997 rtw_dbg(rtwdev, RTW_DBG_RFK,
998 "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n",
999 i,
1000 result[i][0], result[i][1], result[i][2], result[i][3],
1001 result[i][4], result[i][5], result[i][6], result[i][7],
1002 final_candidate == i ? "(final candidate)" : "");
1003
1004 rtw_dbg(rtwdev, RTW_DBG_RFK,
1005 "[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n",
1006 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE),
1007 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N),
1008 rtw_read32(rtwdev, REG_A_RXIQI),
1009 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N));
1010 rtw_dbg(rtwdev, RTW_DBG_RFK,
1011 "[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n",
1012 rtw_read32(rtwdev, REG_TXIQ_AB_S0),
1013 rtw_read32(rtwdev, REG_TXIQ_CD_S0),
1014 rtw_read32(rtwdev, REG_RXIQ_AB_S0));
1015
1016 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] finished\n");
1017}
1018
1019static void rtw8723d_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1020{
1021 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1022 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13};
1023 u8 cck_n_rx;
1024
1025 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
1026 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
1027
1028 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
1029 return;
1030
1031 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) &&
1032 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1;
1033 rtw_dbg(rtwdev, RTW_DBG_PHY,
1034 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n",
1035 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx,
1036 dm_info->cck_pd_default + new_lvl * 2,
1037 pd[new_lvl], dm_info->cck_fa_avg);
1038
1039 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1040
1041 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1042 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1043 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1044 dm_info->cck_pd_default + new_lvl * 2);
1045}
1046
1047/* for coex */
1048static void rtw8723d_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
1049{
1050}
1051
1052static void rtw8723d_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
1053{
1054 rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0);
1055 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0);
1056 rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0);
1057 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0);
1058 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0);
1059 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0);
1060 rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0);
1061 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0);
1062}
1063
1064static void rtw8723d_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
1065{
1066 struct rtw_efuse *efuse = &rtwdev->efuse;
1067 struct rtw_coex *coex = &rtwdev->coex;
1068 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1069 bool aux = efuse->bt_setting & BIT(6);
1070
1071 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
1072 coex_rfe->ant_switch_polarity = 0;
1073 coex_rfe->ant_switch_exist = false;
1074 coex_rfe->ant_switch_with_bt = false;
1075 coex_rfe->ant_switch_diversity = false;
1076 coex_rfe->wlg_at_btg = true;
1077
1078 /* decide antenna at main or aux */
1079 if (efuse->share_ant) {
1080 if (aux)
1081 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x80);
1082 else
1083 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x200);
1084 } else {
1085 if (aux)
1086 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x280);
1087 else
1088 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x0);
1089 }
1090
1091 /* disable LTE coex in wifi side */
1092 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
1093 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
1094 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
1095}
1096
1097static void rtw8723d_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
1098{
1099 struct rtw_coex *coex = &rtwdev->coex;
1100 struct rtw_coex_dm *coex_dm = &coex->dm;
1101 static const u8 wl_tx_power[] = {0xb2, 0x90};
1102 u8 pwr;
1103
1104 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
1105 return;
1106
1107 coex_dm->cur_wl_pwr_lvl = wl_pwr;
1108
1109 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power))
1110 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1;
1111
1112 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl];
1113
1114 rtw_write8(rtwdev, REG_ANA_PARAM1 + 3, pwr);
1115}
1116
1117static void rtw8723d_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1118{
1119 struct rtw_coex *coex = &rtwdev->coex;
1120 struct rtw_coex_dm *coex_dm = &coex->dm;
1121 /* WL Rx Low gain on */
1122 static const u32 wl_rx_low_gain_on[] = {
1123 0xec120101, 0xeb130101, 0xce140101, 0xcd150101, 0xcc160101,
1124 0xcb170101, 0xca180101, 0x8d190101, 0x8c1a0101, 0x8b1b0101,
1125 0x4f1c0101, 0x4e1d0101, 0x4d1e0101, 0x4c1f0101, 0x0e200101,
1126 0x0d210101, 0x0c220101, 0x0b230101, 0xcf240001, 0xce250001,
1127 0xcd260001, 0xcc270001, 0x8f280001
1128 };
1129 /* WL Rx Low gain off */
1130 static const u32 wl_rx_low_gain_off[] = {
1131 0xec120101, 0xeb130101, 0xea140101, 0xe9150101, 0xe8160101,
1132 0xe7170101, 0xe6180101, 0xe5190101, 0xe41a0101, 0xe31b0101,
1133 0xe21c0101, 0xe11d0101, 0xe01e0101, 0x861f0101, 0x85200101,
1134 0x84210101, 0x83220101, 0x82230101, 0x81240101, 0x80250101,
1135 0x44260101, 0x43270101, 0x42280101
1136 };
1137 u8 i;
1138
1139 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
1140 return;
1141
1142 coex_dm->cur_wl_rx_low_gain_en = low_gain;
1143
1144 if (coex_dm->cur_wl_rx_low_gain_en) {
1145 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++)
1146 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_on[i]);
1147 } else {
1148 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++)
1149 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_off[i]);
1150 }
1151}
1152
1153static void rtw8723d_set_iqk_matrix_by_result(struct rtw_dev *rtwdev,
1154 u32 ofdm_swing, u8 rf_path)
1155{
1156 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1157 s32 ele_A, ele_D, ele_C;
1158 s32 ele_A_ext, ele_C_ext, ele_D_ext;
1159 s32 iqk_result_x;
1160 s32 iqk_result_y;
1161 s32 value32;
1162
1163 switch (rf_path) {
1164 default:
1165 case RF_PATH_A:
1166 iqk_result_x = dm_info->iqk.result.s1_x;
1167 iqk_result_y = dm_info->iqk.result.s1_y;
1168 break;
1169 case RF_PATH_B:
1170 iqk_result_x = dm_info->iqk.result.s0_x;
1171 iqk_result_y = dm_info->iqk.result.s0_y;
1172 break;
1173 }
1174
1175 /* new element D */
1176 ele_D = OFDM_SWING_D(ofdm_swing);
1177 iqk_mult(iqk_result_x, ele_D, &ele_D_ext);
1178 /* new element A */
1179 iqk_result_x = iqkxy_to_s32(iqk_result_x);
1180 ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext);
1181 /* new element C */
1182 iqk_result_y = iqkxy_to_s32(iqk_result_y);
1183 ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext);
1184
1185 switch (rf_path) {
1186 case RF_PATH_A:
1187 default:
1188 /* write new elements A, C, D, and element B is always 0 */
1189 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D);
1190 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32);
1191 value32 = BIT_SET_TXIQ_ELM_C1(ele_C);
1192 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
1193 value32);
1194 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1195 value32 &= ~BIT_MASK_OFDM0_EXTS;
1196 value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext);
1197 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1198 break;
1199
1200 case RF_PATH_B:
1201 /* write new elements A, C, D, and element B is always 0 */
1202 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, ele_D);
1203 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, ele_C);
1204 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, ele_A);
1205
1206 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0,
1207 ele_D_ext);
1208 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0,
1209 ele_A_ext);
1210 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0,
1211 ele_C_ext);
1212 break;
1213 }
1214}
1215
1216static void rtw8723d_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index,
1217 u8 rf_path)
1218{
1219 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1220 s32 value32;
1221 u32 ofdm_swing;
1222
1223 if (ofdm_index >= RTW_OFDM_SWING_TABLE_SIZE)
1224 ofdm_index = RTW_OFDM_SWING_TABLE_SIZE - 1;
1225 else if (ofdm_index < 0)
1226 ofdm_index = 0;
1227
1228 ofdm_swing = rtw8723d_ofdm_swing_table[ofdm_index];
1229
1230 if (dm_info->iqk.done) {
1231 rtw8723d_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path);
1232 return;
1233 }
1234
1235 switch (rf_path) {
1236 case RF_PATH_A:
1237 default:
1238 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing);
1239 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
1240 0x00);
1241 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1242 value32 &= ~BIT_MASK_OFDM0_EXTS;
1243 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1244 break;
1245
1246 case RF_PATH_B:
1247 /* image S1:c80 to S0:Cd0 and Cd4 */
1248 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0,
1249 OFDM_SWING_A(ofdm_swing));
1250 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_B_S0,
1251 OFDM_SWING_B(ofdm_swing));
1252 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0,
1253 OFDM_SWING_C(ofdm_swing));
1254 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0,
1255 OFDM_SWING_D(ofdm_swing));
1256 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0);
1257 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0);
1258 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0);
1259 break;
1260 }
1261}
1262
1263static void rtw8723d_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx,
1264 s8 txagc_idx)
1265{
1266 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1267
1268 dm_info->txagc_remnant_ofdm[RF_PATH_A] = txagc_idx;
1269
1270 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A);
1271 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_B);
1272}
1273
1274static void rtw8723d_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx,
1275 s8 txagc_idx)
1276{
1277 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1278
1279 dm_info->txagc_remnant_cck = txagc_idx;
1280
1281 rtw_write32_mask(rtwdev, 0xab4, 0x000007FF,
1282 rtw8723d_cck_swing_table[swing_idx]);
1283}
1284
1285static void rtw8723d_pwrtrack_set(struct rtw_dev *rtwdev, u8 path)
1286{
1287 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1288 struct rtw_hal *hal = &rtwdev->hal;
1289 u8 limit_ofdm;
1290 u8 limit_cck = 40;
1291 s8 final_ofdm_swing_index;
1292 s8 final_cck_swing_index;
1293
1294 limit_ofdm = rtw8723x_pwrtrack_get_limit_ofdm(rtwdev);
1295
1296 final_ofdm_swing_index = RTW_DEF_OFDM_SWING_INDEX +
1297 dm_info->delta_power_index[path];
1298 final_cck_swing_index = RTW_DEF_CCK_SWING_INDEX +
1299 dm_info->delta_power_index[path];
1300
1301 if (final_ofdm_swing_index > limit_ofdm)
1302 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm,
1303 final_ofdm_swing_index - limit_ofdm);
1304 else if (final_ofdm_swing_index < 0)
1305 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, 0,
1306 final_ofdm_swing_index);
1307 else
1308 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0);
1309
1310 if (final_cck_swing_index > limit_cck)
1311 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, limit_cck,
1312 final_cck_swing_index - limit_cck);
1313 else if (final_cck_swing_index < 0)
1314 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, 0,
1315 final_cck_swing_index);
1316 else
1317 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0);
1318
1319 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel);
1320}
1321
1322static void rtw8723d_phy_pwrtrack(struct rtw_dev *rtwdev)
1323{
1324 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1325 struct rtw_swing_table swing_table;
1326 u8 thermal_value, delta, path;
1327 bool do_iqk = false;
1328
1329 rtw_phy_config_swing_table(rtwdev, &swing_table);
1330
1331 if (rtwdev->efuse.thermal_meter[0] == 0xff)
1332 return;
1333
1334 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1335
1336 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1337
1338 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev);
1339
1340 if (do_iqk)
1341 rtw8723x_lck(rtwdev);
1342
1343 if (dm_info->pwr_trk_init_trigger)
1344 dm_info->pwr_trk_init_trigger = false;
1345 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1346 RF_PATH_A))
1347 goto iqk;
1348
1349 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1350
1351 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);
1352
1353 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1354 s8 delta_cur, delta_last;
1355
1356 delta_last = dm_info->delta_power_index[path];
1357 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table,
1358 path, RF_PATH_A, delta);
1359 if (delta_last == delta_cur)
1360 continue;
1361
1362 dm_info->delta_power_index[path] = delta_cur;
1363 rtw8723d_pwrtrack_set(rtwdev, path);
1364 }
1365
1366 rtw8723x_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta);
1367
1368iqk:
1369 if (do_iqk)
1370 rtw8723d_phy_calibration(rtwdev);
1371}
1372
1373static void rtw8723d_pwr_track(struct rtw_dev *rtwdev)
1374{
1375 struct rtw_efuse *efuse = &rtwdev->efuse;
1376 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1377
1378 if (efuse->power_track_type != 0)
1379 return;
1380
1381 if (!dm_info->pwr_trk_triggered) {
1382 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1383 GENMASK(17, 16), 0x03);
1384 dm_info->pwr_trk_triggered = true;
1385 return;
1386 }
1387
1388 rtw8723d_phy_pwrtrack(rtwdev);
1389 dm_info->pwr_trk_triggered = false;
1390}
1391
1392static const struct rtw_chip_ops rtw8723d_ops = {
1393 .power_on = rtw_power_on,
1394 .power_off = rtw_power_off,
1395 .phy_set_param = rtw8723d_phy_set_param,
1396 .read_efuse = rtw8723x_read_efuse,
1397 .query_phy_status = query_phy_status,
1398 .set_channel = rtw8723d_set_channel,
1399 .mac_init = rtw8723x_mac_init,
1400 .shutdown = rtw8723d_shutdown,
1401 .read_rf = rtw_phy_read_rf_sipi,
1402 .write_rf = rtw_phy_write_rf_reg_sipi,
1403 .set_tx_power_index = rtw8723x_set_tx_power_index,
1404 .set_antenna = NULL,
1405 .cfg_ldo25 = rtw8723x_cfg_ldo25,
1406 .efuse_grant = rtw8723x_efuse_grant,
1407 .false_alarm_statistics = rtw8723x_false_alarm_statistics,
1408 .phy_calibration = rtw8723d_phy_calibration,
1409 .cck_pd_set = rtw8723d_phy_cck_pd_set,
1410 .pwr_track = rtw8723d_pwr_track,
1411 .config_bfee = NULL,
1412 .set_gid_table = NULL,
1413 .cfg_csi_rate = NULL,
1414 .fill_txdesc_checksum = rtw8723x_fill_txdesc_checksum,
1415
1416 .coex_set_init = rtw8723x_coex_cfg_init,
1417 .coex_set_ant_switch = NULL,
1418 .coex_set_gnt_fix = rtw8723d_coex_cfg_gnt_fix,
1419 .coex_set_gnt_debug = rtw8723d_coex_cfg_gnt_debug,
1420 .coex_set_rfe_type = rtw8723d_coex_cfg_rfe_type,
1421 .coex_set_wl_tx_power = rtw8723d_coex_cfg_wl_tx_power,
1422 .coex_set_wl_rx_gain = rtw8723d_coex_cfg_wl_rx_gain,
1423};
1424
1425/* Shared-Antenna Coex Table */
1426static const struct coex_table_para table_sant_8723d[] = {
1427 {0xffffffff, 0xffffffff}, /* case-0 */
1428 {0x55555555, 0x55555555},
1429 {0x66555555, 0x66555555},
1430 {0xaaaaaaaa, 0xaaaaaaaa},
1431 {0x5a5a5a5a, 0x5a5a5a5a},
1432 {0xfafafafa, 0xfafafafa}, /* case-5 */
1433 {0x6a5a5555, 0xaaaaaaaa},
1434 {0x6a5a56aa, 0x6a5a56aa},
1435 {0x6a5a5a5a, 0x6a5a5a5a},
1436 {0x66555555, 0x5a5a5a5a},
1437 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1438 {0x66555555, 0x6a5a5aaa},
1439 {0x66555555, 0x5a5a5aaa},
1440 {0x66555555, 0x6aaa5aaa},
1441 {0x66555555, 0xaaaa5aaa},
1442 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1443 {0xffff55ff, 0xfafafafa},
1444 {0xffff55ff, 0x6afa5afa},
1445 {0xaaffffaa, 0xfafafafa},
1446 {0xaa5555aa, 0x5a5a5a5a},
1447 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1448 {0xaa5555aa, 0xaaaaaaaa},
1449 {0xffffffff, 0x5a5a5a5a},
1450 {0xffffffff, 0x5a5a5a5a},
1451 {0xffffffff, 0x55555555},
1452 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1453 {0x55555555, 0x5a5a5a5a},
1454 {0x55555555, 0xaaaaaaaa},
1455 {0x55555555, 0x6a5a6a5a},
1456 {0x66556655, 0x66556655},
1457 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1458 {0xffffffff, 0x5aaa5aaa},
1459 {0x56555555, 0x5a5a5aaa},
1460};
1461
1462/* Non-Shared-Antenna Coex Table */
1463static const struct coex_table_para table_nsant_8723d[] = {
1464 {0xffffffff, 0xffffffff}, /* case-100 */
1465 {0x55555555, 0x55555555},
1466 {0x66555555, 0x66555555},
1467 {0xaaaaaaaa, 0xaaaaaaaa},
1468 {0x5a5a5a5a, 0x5a5a5a5a},
1469 {0xfafafafa, 0xfafafafa}, /* case-105 */
1470 {0x5afa5afa, 0x5afa5afa},
1471 {0x55555555, 0xfafafafa},
1472 {0x66555555, 0xfafafafa},
1473 {0x66555555, 0x5a5a5a5a},
1474 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1475 {0x66555555, 0xaaaaaaaa},
1476 {0xffff55ff, 0xfafafafa},
1477 {0xffff55ff, 0x5afa5afa},
1478 {0xffff55ff, 0xaaaaaaaa},
1479 {0xffff55ff, 0xffff55ff}, /* case-115 */
1480 {0xaaffffaa, 0x5afa5afa},
1481 {0xaaffffaa, 0xaaaaaaaa},
1482 {0xffffffff, 0xfafafafa},
1483 {0xffffffff, 0x5afa5afa},
1484 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1485 {0x55ff55ff, 0x5afa5afa},
1486 {0x55ff55ff, 0xaaaaaaaa},
1487 {0x55ff55ff, 0x55ff55ff}
1488};
1489
1490/* Shared-Antenna TDMA */
1491static const struct coex_tdma_para tdma_sant_8723d[] = {
1492 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1493 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1494 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1495 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1496 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1497 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
1498 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1499 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1500 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1501 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1502 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1503 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1504 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1505 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1506 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1507 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1508 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1509 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1510 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1511 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1512 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1513 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1514 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
1515 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1516 { {0x65, 0x10, 0x03, 0x11, 0x10} },
1517 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1518 { {0x51, 0x08, 0x03, 0x10, 0x50} },
1519 { {0x61, 0x08, 0x03, 0x11, 0x11} }
1520};
1521
1522/* Non-Shared-Antenna TDMA */
1523static const struct coex_tdma_para tdma_nsant_8723d[] = {
1524 { {0x00, 0x00, 0x00, 0x00, 0x01} }, /* case-100 */
1525 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
1526 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1527 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1528 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1529 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1530 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1531 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1532 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1533 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1534 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1535 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1536 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1537 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1538 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1539 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1540 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1541 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1542 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1543 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1544 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
1545 { {0x51, 0x08, 0x03, 0x10, 0x50} }
1546};
1547
1548/* rssi in percentage % (dbm = % - 100) */
1549static const u8 wl_rssi_step_8723d[] = {60, 50, 44, 30};
1550static const u8 bt_rssi_step_8723d[] = {30, 30, 30, 30};
1551static const struct coex_5g_afh_map afh_5g_8723d[] = { {0, 0, 0} };
1552
1553static const struct rtw_hw_reg btg_reg_8723d = {
1554 .addr = REG_BTG_SEL, .mask = BIT_MASK_BTG_WL,
1555};
1556
1557/* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
1558static const struct coex_rf_para rf_para_tx_8723d[] = {
1559 {0, 0, false, 7}, /* for normal */
1560 {0, 10, false, 7}, /* for WL-CPT */
1561 {1, 0, true, 4},
1562 {1, 2, true, 4},
1563 {1, 10, true, 4},
1564 {1, 15, true, 4}
1565};
1566
1567static const struct coex_rf_para rf_para_rx_8723d[] = {
1568 {0, 0, false, 7}, /* for normal */
1569 {0, 10, false, 7}, /* for WL-CPT */
1570 {1, 0, true, 5},
1571 {1, 2, true, 5},
1572 {1, 10, true, 5},
1573 {1, 15, true, 5}
1574};
1575
1576static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8723d[] = {
1577 {0x0005,
1578 RTW_PWR_CUT_ALL_MSK,
1579 RTW_PWR_INTF_ALL_MSK,
1580 RTW_PWR_ADDR_MAC,
1581 RTW_PWR_CMD_WRITE, BIT(3) | BIT(7), 0},
1582 {0x0086,
1583 RTW_PWR_CUT_ALL_MSK,
1584 RTW_PWR_INTF_SDIO_MSK,
1585 RTW_PWR_ADDR_SDIO,
1586 RTW_PWR_CMD_WRITE, BIT(0), 0},
1587 {0x0086,
1588 RTW_PWR_CUT_ALL_MSK,
1589 RTW_PWR_INTF_SDIO_MSK,
1590 RTW_PWR_ADDR_SDIO,
1591 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1592 {0x004A,
1593 RTW_PWR_CUT_ALL_MSK,
1594 RTW_PWR_INTF_USB_MSK,
1595 RTW_PWR_ADDR_MAC,
1596 RTW_PWR_CMD_WRITE, BIT(0), 0},
1597 {0x0005,
1598 RTW_PWR_CUT_ALL_MSK,
1599 RTW_PWR_INTF_ALL_MSK,
1600 RTW_PWR_ADDR_MAC,
1601 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
1602 {0x0023,
1603 RTW_PWR_CUT_ALL_MSK,
1604 RTW_PWR_INTF_SDIO_MSK,
1605 RTW_PWR_ADDR_MAC,
1606 RTW_PWR_CMD_WRITE, BIT(4), 0},
1607 {0x0301,
1608 RTW_PWR_CUT_ALL_MSK,
1609 RTW_PWR_INTF_PCI_MSK,
1610 RTW_PWR_ADDR_MAC,
1611 RTW_PWR_CMD_WRITE, 0xFF, 0},
1612 {0xFFFF,
1613 RTW_PWR_CUT_ALL_MSK,
1614 RTW_PWR_INTF_ALL_MSK,
1615 0,
1616 RTW_PWR_CMD_END, 0, 0},
1617};
1618
1619static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8723d[] = {
1620 {0x0020,
1621 RTW_PWR_CUT_ALL_MSK,
1622 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1623 RTW_PWR_ADDR_MAC,
1624 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1625 {0x0001,
1626 RTW_PWR_CUT_ALL_MSK,
1627 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1628 RTW_PWR_ADDR_MAC,
1629 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
1630 {0x0000,
1631 RTW_PWR_CUT_ALL_MSK,
1632 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1633 RTW_PWR_ADDR_MAC,
1634 RTW_PWR_CMD_WRITE, BIT(5), 0},
1635 {0x0005,
1636 RTW_PWR_CUT_ALL_MSK,
1637 RTW_PWR_INTF_ALL_MSK,
1638 RTW_PWR_ADDR_MAC,
1639 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1640 {0x0075,
1641 RTW_PWR_CUT_ALL_MSK,
1642 RTW_PWR_INTF_PCI_MSK,
1643 RTW_PWR_ADDR_MAC,
1644 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1645 {0x0006,
1646 RTW_PWR_CUT_ALL_MSK,
1647 RTW_PWR_INTF_ALL_MSK,
1648 RTW_PWR_ADDR_MAC,
1649 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1650 {0x0075,
1651 RTW_PWR_CUT_ALL_MSK,
1652 RTW_PWR_INTF_PCI_MSK,
1653 RTW_PWR_ADDR_MAC,
1654 RTW_PWR_CMD_WRITE, BIT(0), 0},
1655 {0x0006,
1656 RTW_PWR_CUT_ALL_MSK,
1657 RTW_PWR_INTF_ALL_MSK,
1658 RTW_PWR_ADDR_MAC,
1659 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1660 {0x0005,
1661 RTW_PWR_CUT_ALL_MSK,
1662 RTW_PWR_INTF_ALL_MSK,
1663 RTW_PWR_ADDR_MAC,
1664 RTW_PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0},
1665 {0x0005,
1666 RTW_PWR_CUT_ALL_MSK,
1667 RTW_PWR_INTF_ALL_MSK,
1668 RTW_PWR_ADDR_MAC,
1669 RTW_PWR_CMD_WRITE, BIT(7), 0},
1670 {0x0005,
1671 RTW_PWR_CUT_ALL_MSK,
1672 RTW_PWR_INTF_ALL_MSK,
1673 RTW_PWR_ADDR_MAC,
1674 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1675 {0x0005,
1676 RTW_PWR_CUT_ALL_MSK,
1677 RTW_PWR_INTF_ALL_MSK,
1678 RTW_PWR_ADDR_MAC,
1679 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1680 {0x0005,
1681 RTW_PWR_CUT_ALL_MSK,
1682 RTW_PWR_INTF_ALL_MSK,
1683 RTW_PWR_ADDR_MAC,
1684 RTW_PWR_CMD_POLLING, BIT(0), 0},
1685 {0x0010,
1686 RTW_PWR_CUT_ALL_MSK,
1687 RTW_PWR_INTF_ALL_MSK,
1688 RTW_PWR_ADDR_MAC,
1689 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1690 {0x0049,
1691 RTW_PWR_CUT_ALL_MSK,
1692 RTW_PWR_INTF_ALL_MSK,
1693 RTW_PWR_ADDR_MAC,
1694 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1695 {0x0063,
1696 RTW_PWR_CUT_ALL_MSK,
1697 RTW_PWR_INTF_ALL_MSK,
1698 RTW_PWR_ADDR_MAC,
1699 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1700 {0x0062,
1701 RTW_PWR_CUT_ALL_MSK,
1702 RTW_PWR_INTF_ALL_MSK,
1703 RTW_PWR_ADDR_MAC,
1704 RTW_PWR_CMD_WRITE, BIT(1), 0},
1705 {0x0058,
1706 RTW_PWR_CUT_ALL_MSK,
1707 RTW_PWR_INTF_ALL_MSK,
1708 RTW_PWR_ADDR_MAC,
1709 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1710 {0x005A,
1711 RTW_PWR_CUT_ALL_MSK,
1712 RTW_PWR_INTF_ALL_MSK,
1713 RTW_PWR_ADDR_MAC,
1714 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1715 {0x0068,
1716 RTW_PWR_CUT_TEST_MSK,
1717 RTW_PWR_INTF_ALL_MSK,
1718 RTW_PWR_ADDR_MAC,
1719 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1720 {0x0069,
1721 RTW_PWR_CUT_ALL_MSK,
1722 RTW_PWR_INTF_ALL_MSK,
1723 RTW_PWR_ADDR_MAC,
1724 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1725 {0x001f,
1726 RTW_PWR_CUT_ALL_MSK,
1727 RTW_PWR_INTF_ALL_MSK,
1728 RTW_PWR_ADDR_MAC,
1729 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1730 {0x0077,
1731 RTW_PWR_CUT_ALL_MSK,
1732 RTW_PWR_INTF_ALL_MSK,
1733 RTW_PWR_ADDR_MAC,
1734 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1735 {0x001f,
1736 RTW_PWR_CUT_ALL_MSK,
1737 RTW_PWR_INTF_ALL_MSK,
1738 RTW_PWR_ADDR_MAC,
1739 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
1740 {0x0077,
1741 RTW_PWR_CUT_ALL_MSK,
1742 RTW_PWR_INTF_ALL_MSK,
1743 RTW_PWR_ADDR_MAC,
1744 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
1745 {0xFFFF,
1746 RTW_PWR_CUT_ALL_MSK,
1747 RTW_PWR_INTF_ALL_MSK,
1748 0,
1749 RTW_PWR_CMD_END, 0, 0},
1750};
1751
1752static const struct rtw_pwr_seq_cmd * const card_enable_flow_8723d[] = {
1753 trans_carddis_to_cardemu_8723d,
1754 trans_cardemu_to_act_8723d,
1755 NULL
1756};
1757
1758static const struct rtw_pwr_seq_cmd trans_act_to_lps_8723d[] = {
1759 {0x0301,
1760 RTW_PWR_CUT_ALL_MSK,
1761 RTW_PWR_INTF_PCI_MSK,
1762 RTW_PWR_ADDR_MAC,
1763 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
1764 {0x0522,
1765 RTW_PWR_CUT_ALL_MSK,
1766 RTW_PWR_INTF_ALL_MSK,
1767 RTW_PWR_ADDR_MAC,
1768 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
1769 {0x05F8,
1770 RTW_PWR_CUT_ALL_MSK,
1771 RTW_PWR_INTF_ALL_MSK,
1772 RTW_PWR_ADDR_MAC,
1773 RTW_PWR_CMD_POLLING, 0xFF, 0},
1774 {0x05F9,
1775 RTW_PWR_CUT_ALL_MSK,
1776 RTW_PWR_INTF_ALL_MSK,
1777 RTW_PWR_ADDR_MAC,
1778 RTW_PWR_CMD_POLLING, 0xFF, 0},
1779 {0x05FA,
1780 RTW_PWR_CUT_ALL_MSK,
1781 RTW_PWR_INTF_ALL_MSK,
1782 RTW_PWR_ADDR_MAC,
1783 RTW_PWR_CMD_POLLING, 0xFF, 0},
1784 {0x05FB,
1785 RTW_PWR_CUT_ALL_MSK,
1786 RTW_PWR_INTF_ALL_MSK,
1787 RTW_PWR_ADDR_MAC,
1788 RTW_PWR_CMD_POLLING, 0xFF, 0},
1789 {0x0002,
1790 RTW_PWR_CUT_ALL_MSK,
1791 RTW_PWR_INTF_ALL_MSK,
1792 RTW_PWR_ADDR_MAC,
1793 RTW_PWR_CMD_WRITE, BIT(0), 0},
1794 {0x0002,
1795 RTW_PWR_CUT_ALL_MSK,
1796 RTW_PWR_INTF_ALL_MSK,
1797 RTW_PWR_ADDR_MAC,
1798 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US},
1799 {0x0002,
1800 RTW_PWR_CUT_ALL_MSK,
1801 RTW_PWR_INTF_ALL_MSK,
1802 RTW_PWR_ADDR_MAC,
1803 RTW_PWR_CMD_WRITE, BIT(1), 0},
1804 {0x0100,
1805 RTW_PWR_CUT_ALL_MSK,
1806 RTW_PWR_INTF_ALL_MSK,
1807 RTW_PWR_ADDR_MAC,
1808 RTW_PWR_CMD_WRITE, 0xFF, 0x03},
1809 {0x0101,
1810 RTW_PWR_CUT_ALL_MSK,
1811 RTW_PWR_INTF_ALL_MSK,
1812 RTW_PWR_ADDR_MAC,
1813 RTW_PWR_CMD_WRITE, BIT(1), 0},
1814 {0x0093,
1815 RTW_PWR_CUT_ALL_MSK,
1816 RTW_PWR_INTF_SDIO_MSK,
1817 RTW_PWR_ADDR_MAC,
1818 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1819 {0x0553,
1820 RTW_PWR_CUT_ALL_MSK,
1821 RTW_PWR_INTF_ALL_MSK,
1822 RTW_PWR_ADDR_MAC,
1823 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1824 {0xFFFF,
1825 RTW_PWR_CUT_ALL_MSK,
1826 RTW_PWR_INTF_ALL_MSK,
1827 0,
1828 RTW_PWR_CMD_END, 0, 0},
1829};
1830
1831static const struct rtw_pwr_seq_cmd trans_act_to_pre_carddis_8723d[] = {
1832 {0x0003,
1833 RTW_PWR_CUT_ALL_MSK,
1834 RTW_PWR_INTF_ALL_MSK,
1835 RTW_PWR_ADDR_MAC,
1836 RTW_PWR_CMD_WRITE, BIT(2), 0},
1837 {0x0080,
1838 RTW_PWR_CUT_ALL_MSK,
1839 RTW_PWR_INTF_ALL_MSK,
1840 RTW_PWR_ADDR_MAC,
1841 RTW_PWR_CMD_WRITE, 0xFF, 0},
1842 {0xFFFF,
1843 RTW_PWR_CUT_ALL_MSK,
1844 RTW_PWR_INTF_ALL_MSK,
1845 0,
1846 RTW_PWR_CMD_END, 0, 0},
1847};
1848
1849static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8723d[] = {
1850 {0x0002,
1851 RTW_PWR_CUT_ALL_MSK,
1852 RTW_PWR_INTF_ALL_MSK,
1853 RTW_PWR_ADDR_MAC,
1854 RTW_PWR_CMD_WRITE, BIT(0), 0},
1855 {0x0049,
1856 RTW_PWR_CUT_ALL_MSK,
1857 RTW_PWR_INTF_ALL_MSK,
1858 RTW_PWR_ADDR_MAC,
1859 RTW_PWR_CMD_WRITE, BIT(1), 0},
1860 {0x0006,
1861 RTW_PWR_CUT_ALL_MSK,
1862 RTW_PWR_INTF_ALL_MSK,
1863 RTW_PWR_ADDR_MAC,
1864 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1865 {0x0005,
1866 RTW_PWR_CUT_ALL_MSK,
1867 RTW_PWR_INTF_ALL_MSK,
1868 RTW_PWR_ADDR_MAC,
1869 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1870 {0x0005,
1871 RTW_PWR_CUT_ALL_MSK,
1872 RTW_PWR_INTF_ALL_MSK,
1873 RTW_PWR_ADDR_MAC,
1874 RTW_PWR_CMD_POLLING, BIT(1), 0},
1875 {0x0010,
1876 RTW_PWR_CUT_ALL_MSK,
1877 RTW_PWR_INTF_ALL_MSK,
1878 RTW_PWR_ADDR_MAC,
1879 RTW_PWR_CMD_WRITE, BIT(6), 0},
1880 {0x0000,
1881 RTW_PWR_CUT_ALL_MSK,
1882 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1883 RTW_PWR_ADDR_MAC,
1884 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1885 {0x0020,
1886 RTW_PWR_CUT_ALL_MSK,
1887 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1888 RTW_PWR_ADDR_MAC,
1889 RTW_PWR_CMD_WRITE, BIT(0), 0},
1890 {0xFFFF,
1891 RTW_PWR_CUT_ALL_MSK,
1892 RTW_PWR_INTF_ALL_MSK,
1893 0,
1894 RTW_PWR_CMD_END, 0, 0},
1895};
1896
1897static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8723d[] = {
1898 {0x0007,
1899 RTW_PWR_CUT_ALL_MSK,
1900 RTW_PWR_INTF_SDIO_MSK,
1901 RTW_PWR_ADDR_MAC,
1902 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1903 {0x0005,
1904 RTW_PWR_CUT_ALL_MSK,
1905 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1906 RTW_PWR_ADDR_MAC,
1907 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1908 {0x0005,
1909 RTW_PWR_CUT_ALL_MSK,
1910 RTW_PWR_INTF_PCI_MSK,
1911 RTW_PWR_ADDR_MAC,
1912 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1913 {0x0005,
1914 RTW_PWR_CUT_ALL_MSK,
1915 RTW_PWR_INTF_PCI_MSK,
1916 RTW_PWR_ADDR_MAC,
1917 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},
1918 {0x004A,
1919 RTW_PWR_CUT_ALL_MSK,
1920 RTW_PWR_INTF_USB_MSK,
1921 RTW_PWR_ADDR_MAC,
1922 RTW_PWR_CMD_WRITE, BIT(0), 1},
1923 {0x0023,
1924 RTW_PWR_CUT_ALL_MSK,
1925 RTW_PWR_INTF_SDIO_MSK,
1926 RTW_PWR_ADDR_MAC,
1927 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1928 {0x0086,
1929 RTW_PWR_CUT_ALL_MSK,
1930 RTW_PWR_INTF_SDIO_MSK,
1931 RTW_PWR_ADDR_SDIO,
1932 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1933 {0x0086,
1934 RTW_PWR_CUT_ALL_MSK,
1935 RTW_PWR_INTF_SDIO_MSK,
1936 RTW_PWR_ADDR_SDIO,
1937 RTW_PWR_CMD_POLLING, BIT(1), 0},
1938 {0xFFFF,
1939 RTW_PWR_CUT_ALL_MSK,
1940 RTW_PWR_INTF_ALL_MSK,
1941 0,
1942 RTW_PWR_CMD_END, 0, 0},
1943};
1944
1945static const struct rtw_pwr_seq_cmd trans_act_to_post_carddis_8723d[] = {
1946 {0x001D,
1947 RTW_PWR_CUT_ALL_MSK,
1948 RTW_PWR_INTF_ALL_MSK,
1949 RTW_PWR_ADDR_MAC,
1950 RTW_PWR_CMD_WRITE, BIT(0), 0},
1951 {0x001D,
1952 RTW_PWR_CUT_ALL_MSK,
1953 RTW_PWR_INTF_ALL_MSK,
1954 RTW_PWR_ADDR_MAC,
1955 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1956 {0x001C,
1957 RTW_PWR_CUT_ALL_MSK,
1958 RTW_PWR_INTF_ALL_MSK,
1959 RTW_PWR_ADDR_MAC,
1960 RTW_PWR_CMD_WRITE, 0xFF, 0x0E},
1961 {0xFFFF,
1962 RTW_PWR_CUT_ALL_MSK,
1963 RTW_PWR_INTF_ALL_MSK,
1964 0,
1965 RTW_PWR_CMD_END, 0, 0},
1966};
1967
1968static const struct rtw_pwr_seq_cmd * const card_disable_flow_8723d[] = {
1969 trans_act_to_lps_8723d,
1970 trans_act_to_pre_carddis_8723d,
1971 trans_act_to_cardemu_8723d,
1972 trans_cardemu_to_carddis_8723d,
1973 trans_act_to_post_carddis_8723d,
1974 NULL
1975};
1976
1977static const struct rtw_page_table page_table_8723d[] = {
1978 {12, 2, 2, 0, 1},
1979 {12, 2, 2, 0, 1},
1980 {12, 2, 2, 0, 1},
1981 {12, 2, 2, 0, 1},
1982 {12, 2, 2, 0, 1},
1983};
1984
1985static const struct rtw_rqpn rqpn_table_8723d[] = {
1986 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1987 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1988 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1989 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1990 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1991 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1992 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1993 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
1994 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1995 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1996 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1997 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1998 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1999 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2000 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
2001};
2002
2003static const struct rtw_intf_phy_para pcie_gen1_param_8723d[] = {
2004 {0x0008, 0x4a22,
2005 RTW_IP_SEL_PHY,
2006 RTW_INTF_PHY_CUT_ALL,
2007 RTW_INTF_PHY_PLATFORM_ALL},
2008 {0x0009, 0x1000,
2009 RTW_IP_SEL_PHY,
2010 ~(RTW_INTF_PHY_CUT_A | RTW_INTF_PHY_CUT_B),
2011 RTW_INTF_PHY_PLATFORM_ALL},
2012 {0xFFFF, 0x0000,
2013 RTW_IP_SEL_PHY,
2014 RTW_INTF_PHY_CUT_ALL,
2015 RTW_INTF_PHY_PLATFORM_ALL},
2016};
2017
2018static const struct rtw_intf_phy_para_table phy_para_table_8723d = {
2019 .gen1_para = pcie_gen1_param_8723d,
2020 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8723d),
2021};
2022
2023static const u8 rtw8723d_pwrtrk_2gb_n[] = {
2024 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2025 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10
2026};
2027
2028static const u8 rtw8723d_pwrtrk_2gb_p[] = {
2029 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2030 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10
2031};
2032
2033static const u8 rtw8723d_pwrtrk_2ga_n[] = {
2034 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2035 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10
2036};
2037
2038static const u8 rtw8723d_pwrtrk_2ga_p[] = {
2039 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2040 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10
2041};
2042
2043static const u8 rtw8723d_pwrtrk_2g_cck_b_n[] = {
2044 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2045 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11
2046};
2047
2048static const u8 rtw8723d_pwrtrk_2g_cck_b_p[] = {
2049 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2050 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11
2051};
2052
2053static const u8 rtw8723d_pwrtrk_2g_cck_a_n[] = {
2054 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2055 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11
2056};
2057
2058static const u8 rtw8723d_pwrtrk_2g_cck_a_p[] = {
2059 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2060 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11
2061};
2062
2063static const s8 rtw8723d_pwrtrk_xtal_n[] = {
2064 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2065 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2066};
2067
2068static const s8 rtw8723d_pwrtrk_xtal_p[] = {
2069 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2070 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16
2071};
2072
2073static const struct rtw_pwr_track_tbl rtw8723d_rtw_pwr_track_tbl = {
2074 .pwrtrk_2gb_n = rtw8723d_pwrtrk_2gb_n,
2075 .pwrtrk_2gb_p = rtw8723d_pwrtrk_2gb_p,
2076 .pwrtrk_2ga_n = rtw8723d_pwrtrk_2ga_n,
2077 .pwrtrk_2ga_p = rtw8723d_pwrtrk_2ga_p,
2078 .pwrtrk_2g_cckb_n = rtw8723d_pwrtrk_2g_cck_b_n,
2079 .pwrtrk_2g_cckb_p = rtw8723d_pwrtrk_2g_cck_b_p,
2080 .pwrtrk_2g_ccka_n = rtw8723d_pwrtrk_2g_cck_a_n,
2081 .pwrtrk_2g_ccka_p = rtw8723d_pwrtrk_2g_cck_a_p,
2082 .pwrtrk_xtal_p = rtw8723d_pwrtrk_xtal_p,
2083 .pwrtrk_xtal_n = rtw8723d_pwrtrk_xtal_n,
2084};
2085
2086static const struct rtw_rfe_def rtw8723d_rfe_defs[] = {
2087 [0] = { .phy_pg_tbl = &rtw8723d_bb_pg_tbl,
2088 .txpwr_lmt_tbl = &rtw8723d_txpwr_lmt_tbl,
2089 .pwr_track_tbl = &rtw8723d_rtw_pwr_track_tbl, },
2090};
2091
2092static const struct rtw_reg_domain coex_info_hw_regs_8723d[] = {
2093 {0x948, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2094 {0x67, BIT(7), RTW_REG_DOMAIN_MAC8},
2095 {0, 0, RTW_REG_DOMAIN_NL},
2096 {0x964, BIT(1), RTW_REG_DOMAIN_MAC8},
2097 {0x864, BIT(0), RTW_REG_DOMAIN_MAC8},
2098 {0xab7, BIT(5), RTW_REG_DOMAIN_MAC8},
2099 {0xa01, BIT(7), RTW_REG_DOMAIN_MAC8},
2100 {0, 0, RTW_REG_DOMAIN_NL},
2101 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2102 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2103 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2104 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2105 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2106 {0, 0, RTW_REG_DOMAIN_NL},
2107 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2108 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2109 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2110 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2111 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2112};
2113
2114const struct rtw_chip_info rtw8723d_hw_spec = {
2115 .ops = &rtw8723d_ops,
2116 .id = RTW_CHIP_TYPE_8723D,
2117 .fw_name = "rtw88/rtw8723d_fw.bin",
2118 .wlan_cpu = RTW_WCPU_11N,
2119 .tx_pkt_desc_sz = 40,
2120 .tx_buf_desc_sz = 16,
2121 .rx_pkt_desc_sz = 24,
2122 .rx_buf_desc_sz = 8,
2123 .phy_efuse_size = 512,
2124 .log_efuse_size = 512,
2125 .ptct_efuse_size = 96 + 1,
2126 .txff_size = 32768,
2127 .rxff_size = 16384,
2128 .rsvd_drv_pg_num = 8,
2129 .txgi_factor = 1,
2130 .is_pwr_by_rate_dec = true,
2131 .max_power_index = 0x3f,
2132 .csi_buf_pg_num = 0,
2133 .band = RTW_BAND_2G,
2134 .page_size = TX_PAGE_SIZE,
2135 .dig_min = 0x20,
2136 .usb_tx_agg_desc_num = 1,
2137 .hw_feature_report = true,
2138 .c2h_ra_report_size = 7,
2139 .old_datarate_fb_limit = true,
2140 .ht_supported = true,
2141 .vht_supported = false,
2142 .lps_deep_mode_supported = 0,
2143 .sys_func_en = 0xFD,
2144 .pwr_on_seq = card_enable_flow_8723d,
2145 .pwr_off_seq = card_disable_flow_8723d,
2146 .page_table = page_table_8723d,
2147 .rqpn_table = rqpn_table_8723d,
2148 .prioq_addrs = &rtw8723x_common.prioq_addrs,
2149 .intf_table = &phy_para_table_8723d,
2150 .dig = rtw8723x_common.dig,
2151 .dig_cck = rtw8723x_common.dig_cck,
2152 .rf_sipi_addr = {0x840, 0x844},
2153 .rf_sipi_read_addr = rtw8723x_common.rf_sipi_addr,
2154 .fix_rf_phy_num = 2,
2155 .ltecoex_addr = &rtw8723x_common.ltecoex_addr,
2156 .mac_tbl = &rtw8723d_mac_tbl,
2157 .agc_tbl = &rtw8723d_agc_tbl,
2158 .bb_tbl = &rtw8723d_bb_tbl,
2159 .rf_tbl = {&rtw8723d_rf_a_tbl},
2160 .rfe_defs = rtw8723d_rfe_defs,
2161 .rfe_defs_size = ARRAY_SIZE(rtw8723d_rfe_defs),
2162 .rx_ldpc = false,
2163 .iqk_threshold = 8,
2164 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
2165 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN,
2166
2167 .coex_para_ver = 0x2007022f,
2168 .bt_desired_ver = 0x2f,
2169 .scbd_support = true,
2170 .new_scbd10_def = true,
2171 .ble_hid_profile_support = false,
2172 .wl_mimo_ps_support = false,
2173 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
2174 .bt_rssi_type = COEX_BTRSSI_RATIO,
2175 .ant_isolation = 15,
2176 .rssi_tolerance = 2,
2177 .wl_rssi_step = wl_rssi_step_8723d,
2178 .bt_rssi_step = bt_rssi_step_8723d,
2179 .table_sant_num = ARRAY_SIZE(table_sant_8723d),
2180 .table_sant = table_sant_8723d,
2181 .table_nsant_num = ARRAY_SIZE(table_nsant_8723d),
2182 .table_nsant = table_nsant_8723d,
2183 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8723d),
2184 .tdma_sant = tdma_sant_8723d,
2185 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8723d),
2186 .tdma_nsant = tdma_nsant_8723d,
2187 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8723d),
2188 .wl_rf_para_tx = rf_para_tx_8723d,
2189 .wl_rf_para_rx = rf_para_rx_8723d,
2190 .bt_afh_span_bw20 = 0x20,
2191 .bt_afh_span_bw40 = 0x30,
2192 .afh_5g_num = ARRAY_SIZE(afh_5g_8723d),
2193 .afh_5g = afh_5g_8723d,
2194 .btg_reg = &btg_reg_8723d,
2195
2196 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8723d),
2197 .coex_info_hw_regs = coex_info_hw_regs_8723d,
2198};
2199EXPORT_SYMBOL(rtw8723d_hw_spec);
2200
2201MODULE_FIRMWARE("rtw88/rtw8723d_fw.bin");
2202
2203MODULE_AUTHOR("Realtek Corporation");
2204MODULE_DESCRIPTION("Realtek 802.11n wireless 8723d driver");
2205MODULE_LICENSE("Dual BSD/GPL");