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1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#if !defined (_soc24_ENUM_HEADER)
24#define _soc24_ENUM_HEADER
25
26#ifndef _DRIVER_BUILD
27#ifndef GL_ZERO
28#define GL__ZERO BLEND_ZERO
29#define GL__ONE BLEND_ONE
30#define GL__SRC_COLOR BLEND_SRC_COLOR
31#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR
32#define GL__DST_COLOR BLEND_DST_COLOR
33#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR
34#define GL__SRC_ALPHA BLEND_SRC_ALPHA
35#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA
36#define GL__DST_ALPHA BLEND_DST_ALPHA
37#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA
38#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE
39#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR
40#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR
41#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA
42#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA
43#endif
44#endif
45
46
47/*
48 * CP_PERFMON_ENABLE_MODE enum
49 */
50
51typedef enum CP_PERFMON_ENABLE_MODE {
52CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000,
53CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001,
54CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002,
55CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003,
56} CP_PERFMON_ENABLE_MODE;
57
58/*
59 * CP_PERFMON_STATE enum
60 */
61
62typedef enum CP_PERFMON_STATE {
63CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
64CP_PERFMON_STATE_START_COUNTING = 0x00000001,
65CP_PERFMON_STATE_STOP_COUNTING = 0x00000002,
66CP_PERFMON_STATE_RESERVED_3 = 0x00000003,
67CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
68CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
69} CP_PERFMON_STATE;
70
71/*
72 * ENUM_NUM_SIMD_PER_CU enum
73 */
74
75typedef enum ENUM_NUM_SIMD_PER_CU {
76NUM_SIMD_PER_CU = 0x00000002,
77} ENUM_NUM_SIMD_PER_CU;
78
79/*
80 * GATCL1RequestType enum
81 */
82
83typedef enum GATCL1RequestType {
84GATCL1_TYPE_NORMAL = 0x00000000,
85GATCL1_TYPE_SHOOTDOWN = 0x00000001,
86GATCL1_TYPE_BYPASS = 0x00000002,
87} GATCL1RequestType;
88
89/*
90 * GL0V_CACHE_POLICIES enum
91 */
92
93typedef enum GL0V_CACHE_POLICIES {
94GL0V_CACHE_POLICY_MISS_LRU = 0x00000000,
95GL0V_CACHE_POLICY_MISS_EVICT = 0x00000001,
96GL0V_CACHE_POLICY_HIT_LRU = 0x00000002,
97GL0V_CACHE_POLICY_HIT_EVICT = 0x00000003,
98GL0V_CACHE_POLICY_MISS_INVAL = 0x00000004,
99} GL0V_CACHE_POLICIES;
100
101/*
102 * GL1_CACHE_POLICIES enum
103 */
104
105typedef enum GL1_CACHE_POLICIES {
106GL1_CACHE_POLICY_MISS_LRU = 0x00000000,
107GL1_CACHE_POLICY_MISS_EVICT = 0x00000001,
108GL1_CACHE_POLICY_HIT_LRU = 0x00000002,
109GL1_CACHE_POLICY_HIT_EVICT = 0x00000003,
110} GL1_CACHE_POLICIES;
111
112/*
113 * GL1_CACHE_STORE_POLICIES enum
114 */
115
116typedef enum GL1_CACHE_STORE_POLICIES {
117GL1_CACHE_STORE_POLICY_BYPASS = 0x00000000,
118} GL1_CACHE_STORE_POLICIES;
119
120/*
121 * GL2_CACHE_POLICIES enum
122 */
123
124typedef enum GL2_CACHE_POLICIES {
125GL2_CACHE_POLICY_LRU = 0x00000000,
126GL2_CACHE_POLICY_STREAM = 0x00000001,
127GL2_CACHE_POLICY_NOA = 0x00000002,
128GL2_CACHE_POLICY_BYPASS = 0x00000003,
129} GL2_CACHE_POLICIES;
130
131/*
132 * GL2_NACKS enum
133 */
134
135typedef enum GL2_NACKS {
136GL2_NACK_NO_FAULT = 0x00000000,
137GL2_NACK_PAGE_FAULT = 0x00000001,
138GL2_NACK_PROTECTION_FAULT = 0x00000002,
139GL2_NACK_DATA_ERROR = 0x00000003,
140} GL2_NACKS;
141
142/*
143 * GL2_OP enum
144 */
145
146typedef enum GL2_OP {
147GL2_OP_READ = 0x00000000,
148GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001,
149GL2_OP_ATOMIC_FMIN_RTN_32 = 0x00000002,
150GL2_OP_ATOMIC_FMAX_RTN_32 = 0x00000003,
151GL2_OP_ATOMIC_PK_ADD_FP16_RTN = 0x00000004,
152GL2_OP_ATOMIC_FADD_RTN_32 = 0x00000005,
153GL2_OP_ATOMIC_PK_ADD_BF16_RTN = 0x00000006,
154GL2_OP_ATOMIC_SWAP_RTN_32 = 0x00000007,
155GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008,
156GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
157GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a,
158GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b,
159GL2_OP_PROBE_FILTER = 0x0000000c,
160GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 0x0000000d,
161GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
162GL2_OP_ATOMIC_ADD_RTN_32 = 0x0000000f,
163GL2_OP_ATOMIC_SUB_RTN_32 = 0x00000010,
164GL2_OP_ATOMIC_SMIN_RTN_32 = 0x00000011,
165GL2_OP_ATOMIC_UMIN_RTN_32 = 0x00000012,
166GL2_OP_ATOMIC_SMAX_RTN_32 = 0x00000013,
167GL2_OP_ATOMIC_UMAX_RTN_32 = 0x00000014,
168GL2_OP_ATOMIC_AND_RTN_32 = 0x00000015,
169GL2_OP_ATOMIC_OR_RTN_32 = 0x00000016,
170GL2_OP_ATOMIC_XOR_RTN_32 = 0x00000017,
171GL2_OP_ATOMIC_INC_RTN_32 = 0x00000018,
172GL2_OP_ATOMIC_DEC_RTN_32 = 0x00000019,
173GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 0x0000001a,
174GL2_OP_ATOMIC_COND_SUB_RTN_32 = 0x0000001b,
175GL2_OP_UTC_PROBE = 0x0000001d,
176GL2_OP_LOAD_RESERVE = 0x0000001e,
177GL2_OP_WRITE = 0x00000020,
178GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021,
179GL2_OP_ATOMIC_FMIN_RTN_64 = 0x00000022,
180GL2_OP_ATOMIC_FMAX_RTN_64 = 0x00000023,
181GL2_OP_ATOMIC_SWAP_RTN_64 = 0x00000027,
182GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028,
183GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
184GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a,
185GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b,
186GL2_OP_ATOMIC_ADD_RTN_64 = 0x0000002f,
187GL2_OP_ATOMIC_SUB_RTN_64 = 0x00000030,
188GL2_OP_ATOMIC_SMIN_RTN_64 = 0x00000031,
189GL2_OP_ATOMIC_UMIN_RTN_64 = 0x00000032,
190GL2_OP_ATOMIC_SMAX_RTN_64 = 0x00000033,
191GL2_OP_ATOMIC_UMAX_RTN_64 = 0x00000034,
192GL2_OP_ATOMIC_AND_RTN_64 = 0x00000035,
193GL2_OP_ATOMIC_OR_RTN_64 = 0x00000036,
194GL2_OP_ATOMIC_XOR_RTN_64 = 0x00000037,
195GL2_OP_ATOMIC_INC_RTN_64 = 0x00000038,
196GL2_OP_ATOMIC_DEC_RTN_64 = 0x00000039,
197GL2_OP_WRITE_ZERO_SIZE = 0x0000003b,
198GL2_OP_GL2_INV = 0x0000003d,
199GL2_OP_ATOMIC_STORE_COND_RTN = 0x0000003e,
200GL2_OP_GL1_INV = 0x00000040,
201GL2_OP_ATOMIC_FCMPSWAP_32 = 0x00000041,
202GL2_OP_ATOMIC_FMIN_32 = 0x00000042,
203GL2_OP_ATOMIC_FMAX_32 = 0x00000043,
204GL2_OP_ATOMIC_PK_ADD_FP16 = 0x00000044,
205GL2_OP_ATOMIC_FADD_32 = 0x00000045,
206GL2_OP_ATOMIC_PK_ADD_BF16 = 0x00000046,
207GL2_OP_ATOMIC_SWAP_32 = 0x00000047,
208GL2_OP_ATOMIC_CMPSWAP_32 = 0x00000048,
209GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049,
210GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a,
211GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b,
212GL2_OP_ATOMIC_UMIN_8 = 0x0000004c,
213GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 0x0000004d,
214GL2_OP_ATOMIC_ADD_32 = 0x0000004f,
215GL2_OP_ATOMIC_SUB_32 = 0x00000050,
216GL2_OP_ATOMIC_SMIN_32 = 0x00000051,
217GL2_OP_ATOMIC_UMIN_32 = 0x00000052,
218GL2_OP_ATOMIC_SMAX_32 = 0x00000053,
219GL2_OP_ATOMIC_UMAX_32 = 0x00000054,
220GL2_OP_ATOMIC_AND_32 = 0x00000055,
221GL2_OP_ATOMIC_OR_32 = 0x00000056,
222GL2_OP_ATOMIC_XOR_32 = 0x00000057,
223GL2_OP_ATOMIC_INC_32 = 0x00000058,
224GL2_OP_ATOMIC_DEC_32 = 0x00000059,
225GL2_OP_NOP_RTN0 = 0x0000005b,
226GL2_OP_GL2_WB = 0x0000005d,
227GL2_OP_FORCE_EXISTING_DATA_TO_DECOMPRESS = 0x0000005e,
228GL2_OP_ATOMIC_FCMPSWAP_64 = 0x00000061,
229GL2_OP_ATOMIC_FMIN_64 = 0x00000062,
230GL2_OP_ATOMIC_FMAX_64 = 0x00000063,
231GL2_OP_ATOMIC_SWAP_64 = 0x00000067,
232GL2_OP_ATOMIC_CMPSWAP_64 = 0x00000068,
233GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069,
234GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a,
235GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b,
236GL2_OP_ATOMIC_ADD_64 = 0x0000006f,
237GL2_OP_ATOMIC_SUB_64 = 0x00000070,
238GL2_OP_ATOMIC_SMIN_64 = 0x00000071,
239GL2_OP_ATOMIC_UMIN_64 = 0x00000072,
240GL2_OP_ATOMIC_SMAX_64 = 0x00000073,
241GL2_OP_ATOMIC_UMAX_64 = 0x00000074,
242GL2_OP_ATOMIC_AND_64 = 0x00000075,
243GL2_OP_ATOMIC_OR_64 = 0x00000076,
244GL2_OP_ATOMIC_XOR_64 = 0x00000077,
245GL2_OP_ATOMIC_INC_64 = 0x00000078,
246GL2_OP_ATOMIC_DEC_64 = 0x00000079,
247GL2_OP_ATOMIC_UMAX_8 = 0x0000007a,
248GL2_OP_NOP_ACK = 0x0000007b,
249GL2_OP_GL2_WBINV = 0x0000007d,
250GL2_OP_READ_COMPRESSION_KEY = 0x0000007e,
251} GL2_OP;
252
253/*
254 * GL2_OP_MASKS enum
255 */
256
257typedef enum GL2_OP_MASKS {
258GL2_OP_MASK_FLUSH_DENROM = 0x00000008,
259GL2_OP_MASK_64 = 0x00000020,
260GL2_OP_MASK_NO_RTN = 0x00000040,
261} GL2_OP_MASKS;
262
263/*
264 * Hdp_SurfaceEndian enum
265 */
266
267typedef enum Hdp_SurfaceEndian {
268HDP_ENDIAN_NONE = 0x00000000,
269HDP_ENDIAN_8IN16 = 0x00000001,
270HDP_ENDIAN_8IN32 = 0x00000002,
271HDP_ENDIAN_8IN64 = 0x00000003,
272} Hdp_SurfaceEndian;
273
274/*
275 * MTYPE enum
276 */
277
278typedef enum MTYPE {
279MTYPE_C_RW_US = 0x00000000,
280MTYPE_RESERVED_1 = 0x00000001,
281MTYPE_C_RO_S = 0x00000002,
282MTYPE_UC = 0x00000003,
283MTYPE_C_RW_S = 0x00000004,
284MTYPE_RESERVED_5 = 0x00000005,
285MTYPE_C_RO_US = 0x00000006,
286MTYPE_RESERVED_7 = 0x00000007,
287} MTYPE;
288
289/*
290 * PERFMON_COUNTER_MODE enum
291 */
292
293typedef enum PERFMON_COUNTER_MODE {
294PERFMON_COUNTER_MODE_ACCUM = 0x00000000,
295PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001,
296PERFMON_COUNTER_MODE_MAX = 0x00000002,
297PERFMON_COUNTER_MODE_DIRTY = 0x00000003,
298PERFMON_COUNTER_MODE_SAMPLE = 0x00000004,
299PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
300PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
301PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007,
302PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008,
303PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009,
304PERFMON_COUNTER_MODE_RESERVED = 0x0000000f,
305} PERFMON_COUNTER_MODE;
306
307/*
308 * PERFMON_SPM_MODE enum
309 */
310
311typedef enum PERFMON_SPM_MODE {
312PERFMON_SPM_MODE_OFF = 0x00000000,
313PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001,
314PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002,
315PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003,
316PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004,
317PERFMON_SPM_MODE_RESERVED_5 = 0x00000005,
318PERFMON_SPM_MODE_RESERVED_6 = 0x00000006,
319PERFMON_SPM_MODE_RESERVED_7 = 0x00000007,
320PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008,
321PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009,
322PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a,
323} PERFMON_SPM_MODE;
324
325/*
326 * READ_COMPRESSION_MODE enum
327 */
328
329typedef enum READ_COMPRESSION_MODE {
330COMPRESSION_MODE_BYPASS_COMPRESSION = 0x00000000,
331COMPRESSION_MODE_READ_RAW_COMPRESSED_DATA = 0x00000001,
332COMPRESSION_MODE_READ_DECOMPRESSED = 0x00000002,
333} READ_COMPRESSION_MODE;
334
335/*
336 * ReadPolicy enum
337 */
338
339typedef enum ReadPolicy {
340CACHE_LRU_RD = 0x00000000,
341CACHE_STREAM_RD = 0x00000001,
342CACHE_NOA = 0x00000002,
343RESERVED_RDPOLICY = 0x00000003,
344} ReadPolicy;
345
346/*
347 * SCOPE enum
348 */
349
350typedef enum SCOPE {
351SCOPE_CU = 0x00000000,
352SCOPE_SE = 0x00000001,
353SCOPE_DEV = 0x00000002,
354SCOPE_SYS = 0x00000003,
355} SCOPE;
356
357/*
358 * SDMA_PERFMON_SEL enum
359 */
360
361typedef enum SDMA_PERFMON_SEL {
362SDMA_PERFMON_SEL_CYCLE = 0x00000000,
363SDMA_PERFMON_SEL_IDLE = 0x00000001,
364SDMA_PERFMON_SEL_REG_IDLE = 0x00000002,
365SDMA_PERFMON_SEL_RB_EMPTY = 0x00000003,
366SDMA_PERFMON_SEL_RB_FULL = 0x00000004,
367SDMA_PERFMON_SEL_RB_WPTR_WRAP = 0x00000005,
368SDMA_PERFMON_SEL_RB_RPTR_WRAP = 0x00000006,
369SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 0x00000007,
370SDMA_PERFMON_SEL_RB_RPTR_WB = 0x00000008,
371SDMA_PERFMON_SEL_RB_CMD_IDLE = 0x00000009,
372SDMA_PERFMON_SEL_RB_CMD_FULL = 0x0000000a,
373SDMA_PERFMON_SEL_IB_CMD_IDLE = 0x0000000b,
374SDMA_PERFMON_SEL_IB_CMD_FULL = 0x0000000c,
375SDMA_PERFMON_SEL_EX_IDLE = 0x0000000d,
376SDMA_PERFMON_SEL_SRBM_REG_SEND = 0x0000000e,
377SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
378SDMA_PERFMON_SEL_WR_BA_RTR = 0x00000010,
379SDMA_PERFMON_SEL_MC_WR_IDLE = 0x00000011,
380SDMA_PERFMON_SEL_MC_WR_COUNT = 0x00000012,
381SDMA_PERFMON_SEL_RD_BA_RTR = 0x00000013,
382SDMA_PERFMON_SEL_MC_RD_IDLE = 0x00000014,
383SDMA_PERFMON_SEL_MC_RD_COUNT = 0x00000015,
384SDMA_PERFMON_SEL_MC_RD_RET_STALL = 0x00000016,
385SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 0x00000017,
386SDMA_PERFMON_SEL_SEM_IDLE = 0x0000001a,
387SDMA_PERFMON_SEL_SEM_REQ_STALL = 0x0000001b,
388SDMA_PERFMON_SEL_SEM_REQ_COUNT = 0x0000001c,
389SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 0x0000001d,
390SDMA_PERFMON_SEL_SEM_RESP_FAIL = 0x0000001e,
391SDMA_PERFMON_SEL_SEM_RESP_PASS = 0x0000001f,
392SDMA_PERFMON_SEL_INT_IDLE = 0x00000020,
393SDMA_PERFMON_SEL_INT_REQ_STALL = 0x00000021,
394SDMA_PERFMON_SEL_INT_REQ_COUNT = 0x00000022,
395SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 0x00000023,
396SDMA_PERFMON_SEL_INT_RESP_RETRY = 0x00000024,
397SDMA_PERFMON_SEL_NUM_PACKET = 0x00000025,
398SDMA_PERFMON_SEL_CE_WREQ_IDLE = 0x00000027,
399SDMA_PERFMON_SEL_CE_WR_IDLE = 0x00000028,
400SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 0x00000029,
401SDMA_PERFMON_SEL_CE_RREQ_IDLE = 0x0000002a,
402SDMA_PERFMON_SEL_CE_OUT_IDLE = 0x0000002b,
403SDMA_PERFMON_SEL_CE_IN_IDLE = 0x0000002c,
404SDMA_PERFMON_SEL_CE_DST_IDLE = 0x0000002d,
405SDMA_PERFMON_SEL_CE_AFIFO_FULL = 0x00000030,
406SDMA_PERFMON_SEL_DUMMY_0 = 0x00000031,
407SDMA_PERFMON_SEL_DUMMY_1 = 0x00000032,
408SDMA_PERFMON_SEL_CE_INFO_FULL = 0x00000033,
409SDMA_PERFMON_SEL_CE_INFO1_FULL = 0x00000034,
410SDMA_PERFMON_SEL_CE_RD_STALL = 0x00000035,
411SDMA_PERFMON_SEL_CE_WR_STALL = 0x00000036,
412SDMA_PERFMON_SEL_QUEUE0_SELECT = 0x00000037,
413SDMA_PERFMON_SEL_QUEUE1_SELECT = 0x00000038,
414SDMA_PERFMON_SEL_QUEUE2_SELECT = 0x00000039,
415SDMA_PERFMON_SEL_QUEUE3_SELECT = 0x0000003a,
416SDMA_PERFMON_SEL_CTX_CHANGE = 0x0000003b,
417SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 0x0000003c,
418SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 0x0000003d,
419SDMA_PERFMON_SEL_DOORBELL = 0x0000003e,
420SDMA_PERFMON_SEL_MCU_L1_WR_VLD = 0x0000003f,
421SDMA_PERFMON_SEL_CE_L1_WR_VLD = 0x00000040,
422SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 0x00000041,
423SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 0x00000042,
424SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 0x00000043,
425SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 0x00000044,
426SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045,
427SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046,
428SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 0x00000047,
429SDMA_PERFMON_SEL_UTCL2_RET_ACK = 0x00000048,
430SDMA_PERFMON_SEL_UTCL2_FREE = 0x00000049,
431SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 0x0000004a,
432SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 0x0000004b,
433SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 0x0000004c,
434SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 0x0000004d,
435SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 0x0000004e,
436SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 0x0000004f,
437SDMA_PERFMON_SEL_GPUVM_INV_LOW = 0x00000050,
438SDMA_PERFMON_SEL_L1_WRL2_IDLE = 0x00000051,
439SDMA_PERFMON_SEL_L1_RDL2_IDLE = 0x00000052,
440SDMA_PERFMON_SEL_L1_WRMC_IDLE = 0x00000053,
441SDMA_PERFMON_SEL_L1_RDMC_IDLE = 0x00000054,
442SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 0x00000055,
443SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 0x00000056,
444SDMA_PERFMON_SEL_META_L2_REQ_SEND = 0x00000057,
445SDMA_PERFMON_SEL_L2_META_RET_VLD = 0x00000058,
446SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 0x00000059,
447SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a,
448SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b,
449SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c,
450SDMA_PERFMON_SEL_META_REQ_SEND = 0x0000005d,
451SDMA_PERFMON_SEL_META_RTN_VLD = 0x0000005e,
452SDMA_PERFMON_SEL_TLBI_SEND = 0x0000005f,
453SDMA_PERFMON_SEL_TLBI_RTN = 0x00000060,
454SDMA_PERFMON_SEL_GCR_SEND = 0x00000061,
455SDMA_PERFMON_SEL_GCR_RTN = 0x00000062,
456SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 0x00000063,
457SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 0x00000064,
458} SDMA_PERFMON_SEL;
459
460/*
461 * SDMA_PERF_SEL enum
462 */
463
464typedef enum SDMA_PERF_SEL {
465SDMA_PERF_SEL_CYCLE = 0x00000000,
466SDMA_PERF_SEL_IDLE = 0x00000001,
467SDMA_PERF_SEL_REG_IDLE = 0x00000002,
468SDMA_PERF_SEL_RB_EMPTY = 0x00000003,
469SDMA_PERF_SEL_RB_FULL = 0x00000004,
470SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005,
471SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006,
472SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007,
473SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008,
474SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009,
475SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a,
476SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b,
477SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c,
478SDMA_PERF_SEL_EX_IDLE = 0x0000000d,
479SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e,
480SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
481SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010,
482SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011,
483SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012,
484SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013,
485SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014,
486SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015,
487SDMA_PERF_SEL_SEM_IDLE = 0x00000018,
488SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019,
489SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a,
490SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b,
491SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c,
492SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d,
493SDMA_PERF_SEL_INT_IDLE = 0x0000001e,
494SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f,
495SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020,
496SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021,
497SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022,
498SDMA_PERF_SEL_NUM_PACKET = 0x00000023,
499SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025,
500SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026,
501SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027,
502SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028,
503SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029,
504SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a,
505SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b,
506SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e,
507SDMA_PERF_SEL_DUMMY_0 = 0x0000002f,
508SDMA_PERF_SEL_DUMMY_1 = 0x00000030,
509SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031,
510SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032,
511SDMA_PERF_SEL_CE_RD_STALL = 0x00000033,
512SDMA_PERF_SEL_CE_WR_STALL = 0x00000034,
513SDMA_PERF_SEL_QUEUE0_SELECT = 0x00000035,
514SDMA_PERF_SEL_QUEUE1_SELECT = 0x00000036,
515SDMA_PERF_SEL_QUEUE2_SELECT = 0x00000037,
516SDMA_PERF_SEL_QUEUE3_SELECT = 0x00000038,
517SDMA_PERF_SEL_CTX_CHANGE = 0x00000039,
518SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a,
519SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b,
520SDMA_PERF_SEL_DOORBELL = 0x0000003c,
521SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d,
522SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e,
523SDMA_PERF_SEL_MCU_L1_WR_VLD = 0x0000003f,
524SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040,
525SDMA_PERF_SEL_CPF_SDMA_INVREQ = 0x00000041,
526SDMA_PERF_SEL_SDMA_CPF_INVACK = 0x00000042,
527SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 0x00000043,
528SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 0x00000044,
529SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045,
530SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046,
531SDMA_PERF_SEL_UTCL2_RET_XNACK = 0x00000047,
532SDMA_PERF_SEL_UTCL2_RET_ACK = 0x00000048,
533SDMA_PERF_SEL_UTCL2_FREE = 0x00000049,
534SDMA_PERF_SEL_SDMA_UTCL2_SEND = 0x0000004a,
535SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004b,
536SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004c,
537SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004d,
538SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004e,
539SDMA_PERF_SEL_GPUVM_INV_HIGH = 0x0000004f,
540SDMA_PERF_SEL_GPUVM_INV_LOW = 0x00000050,
541SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000051,
542SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000052,
543SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000053,
544SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000054,
545SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000055,
546SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000056,
547SDMA_PERF_SEL_META_L2_REQ_SEND = 0x00000057,
548SDMA_PERF_SEL_L2_META_RET_VLD = 0x00000058,
549SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 0x00000059,
550SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a,
551SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b,
552SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c,
553SDMA_PERF_SEL_META_REQ_SEND = 0x0000005d,
554SDMA_PERF_SEL_META_RTN_VLD = 0x0000005e,
555SDMA_PERF_SEL_TLBI_SEND = 0x0000005f,
556SDMA_PERF_SEL_TLBI_RTN = 0x00000060,
557SDMA_PERF_SEL_GCR_SEND = 0x00000061,
558SDMA_PERF_SEL_GCR_RTN = 0x00000062,
559SDMA_PERF_SEL_CGCG_FENCE = 0x00000063,
560SDMA_PERF_SEL_CE_CH_WR_REQ = 0x00000064,
561SDMA_PERF_SEL_CE_CH_WR_RET = 0x00000065,
562SDMA_PERF_SEL_MCU_CH_WR_REQ = 0x00000066,
563SDMA_PERF_SEL_MCU_CH_WR_RET = 0x00000067,
564SDMA_PERF_SEL_CE_OR_MCU_CH_RD_REQ = 0x00000068,
565SDMA_PERF_SEL_CE_OR_MCU_CH_RD_RET = 0x00000069,
566SDMA_PERF_SEL_RB_CH_RD_REQ = 0x0000006a,
567SDMA_PERF_SEL_RB_CH_RD_RET = 0x0000006b,
568SDMA_PERF_SEL_IB_CH_RD_REQ = 0x0000006c,
569SDMA_PERF_SEL_IB_CH_RD_RET = 0x0000006d,
570SDMA_PERF_SEL_WPTR_CH_RD_REQ = 0x0000006e,
571SDMA_PERF_SEL_WPTR_CH_RD_RET = 0x0000006f,
572SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 0x00000070,
573SDMA_PERF_SEL_UTCL1_UTCL2_RET = 0x00000071,
574SDMA_PERF_SEL_CMD_OP_MATCH = 0x00000072,
575SDMA_PERF_SEL_CMD_OP_START = 0x00000073,
576SDMA_PERF_SEL_CMD_OP_END = 0x00000074,
577SDMA_PERF_SEL_CE_BUSY = 0x00000075,
578SDMA_PERF_SEL_CE_BUSY_START = 0x00000076,
579SDMA_PERF_SEL_CE_BUSY_END = 0x00000077,
580SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER = 0x00000078,
581SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_START = 0x00000079,
582SDMA_PERF_SEL_MCU_PERFCNT_TRIGGER_END = 0x0000007a,
583SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 0x0000007b,
584SDMA_PERF_SEL_CH_CE_WRRET_VALID = 0x0000007c,
585SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 0x0000007d,
586SDMA_PERF_SEL_CH_CE_RDRET_VALID = 0x0000007e,
587SDMA_PERF_SEL_QUEUE4_SELECT = 0x0000007f,
588SDMA_PERF_SEL_QUEUE5_SELECT = 0x00000080,
589SDMA_PERF_SEL_QUEUE6_SELECT = 0x00000081,
590SDMA_PERF_SEL_QUEUE7_SELECT = 0x00000082,
591} SDMA_PERF_SEL;
592
593/*
594 * SPM_PERFMON_STATE enum
595 */
596
597typedef enum SPM_PERFMON_STATE {
598STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
599STRM_PERFMON_STATE_START_COUNTING = 0x00000001,
600STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002,
601STRM_PERFMON_STATE_RESERVED_3 = 0x00000003,
602STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
603STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
604} SPM_PERFMON_STATE;
605
606/*
607 * TCC_MTYPE enum
608 */
609
610typedef enum TCC_MTYPE {
611MTYPE_NC = 0x00000000,
612MTYPE_WC = 0x00000001,
613MTYPE_CC = 0x00000002,
614} TCC_MTYPE;
615
616/*
617 * UTCL0FaultType enum
618 */
619
620typedef enum UTCL0FaultType {
621UTCL0_XNACK_SUCCESS = 0x00000000,
622UTCL0_XNACK_RETRY = 0x00000001,
623UTCL0_XNACK_PRT = 0x00000002,
624UTCL0_XNACK_NO_RETRY = 0x00000003,
625} UTCL0FaultType;
626
627/*
628 * UTCL0RequestType enum
629 */
630
631typedef enum UTCL0RequestType {
632UTCL0_TYPE_NORMAL = 0x00000000,
633UTCL0_TYPE_SHOOTDOWN = 0x00000001,
634UTCL0_TYPE_BYPASS = 0x00000002,
635} UTCL0RequestType;
636
637/*
638 * UTCL1FaultType enum
639 */
640
641typedef enum UTCL1FaultType {
642UTCL1_XNACK_SUCCESS = 0x00000000,
643UTCL1_XNACK_RETRY = 0x00000001,
644UTCL1_XNACK_PRT = 0x00000002,
645UTCL1_XNACK_NO_RETRY = 0x00000003,
646} UTCL1FaultType;
647
648/*
649 * UTCL1RequestType enum
650 */
651
652typedef enum UTCL1RequestType {
653UTCL1_TYPE_NORMAL = 0x00000000,
654UTCL1_TYPE_SHOOTDOWN = 0x00000001,
655UTCL1_TYPE_BYPASS = 0x00000002,
656} UTCL1RequestType;
657
658/*
659 * WRITE_COMPRESSION_MODE enum
660 */
661
662typedef enum WRITE_COMPRESSION_MODE {
663COMPRESSION_MODE_BYPASS_METADATA_CACHE = 0x00000000,
664COMPRESSION_MODE_COMPRESSION_ENABLED = 0x00000001,
665COMPRESSION_MODE_WRITE_COMPRESSION_DISABLED = 0x00000002,
666} WRITE_COMPRESSION_MODE;
667
668/*
669 * WritePolicy enum
670 */
671
672typedef enum WritePolicy {
673CACHE_LRU_WR = 0x00000000,
674CACHE_STREAM = 0x00000001,
675CACHE_NOA_WR = 0x00000002,
676CACHE_BYPASS = 0x00000003,
677} WritePolicy;
678
679/*
680 * COLOR_KEYER_ENABLE enum
681 */
682
683typedef enum COLOR_KEYER_ENABLE {
684COLOR_KEY_EN = 0x00000000,
685COLOR_KEY_DIS = 0x00000001,
686} COLOR_KEYER_ENABLE;
687
688/*
689 * COLOR_KEYER_MODE enum
690 */
691
692typedef enum COLOR_KEYER_MODE {
693FORCE_00 = 0x00000000,
694FORCE_FF = 0x00000001,
695RANGE_00 = 0x00000002,
696RANGE_FF = 0x00000003,
697} COLOR_KEYER_MODE;
698
699/*
700 * DENORM_TRUNCATE enum
701 */
702
703typedef enum DENORM_TRUNCATE {
704CNVC_ROUND = 0x00000000,
705CNVC_TRUNCATE = 0x00000001,
706} DENORM_TRUNCATE;
707
708/*
709 * FORMAT_CROSSBAR enum
710 */
711
712typedef enum FORMAT_CROSSBAR {
713FORMAT_CROSSBAR_R = 0x00000000,
714FORMAT_CROSSBAR_G = 0x00000001,
715FORMAT_CROSSBAR_B = 0x00000002,
716} FORMAT_CROSSBAR;
717
718/*
719 * LUMA_KEYER_ENABLE enum
720 */
721
722typedef enum LUMA_KEYER_ENABLE {
723LUMA_KEY_EN = 0x00000000,
724LUMA_KEY_DIS = 0x00000001,
725} LUMA_KEYER_ENABLE;
726
727/*
728 * PIX_EXPAND_MODE enum
729 */
730
731typedef enum PIX_EXPAND_MODE {
732PIX_DYNAMIC_EXPANSION = 0x00000000,
733PIX_ZERO_EXPANSION = 0x00000001,
734} PIX_EXPAND_MODE;
735
736/*
737 * PRE_CSC_MODE_ENUM enum
738 */
739
740typedef enum PRE_CSC_MODE_ENUM {
741PRE_CSC_BYPASS = 0x00000000,
742PRE_CSC_SET_A = 0x00000001,
743PRE_CSC_SET_B = 0x00000002,
744} PRE_CSC_MODE_ENUM;
745
746/*
747 * PRE_DEGAM_MODE enum
748 */
749
750typedef enum PRE_DEGAM_MODE {
751PRE_DEGAM_BYPASS = 0x00000000,
752PRE_DEGAM_ENABLE = 0x00000001,
753} PRE_DEGAM_MODE;
754
755/*
756 * PRE_DEGAM_SELECT enum
757 */
758
759typedef enum PRE_DEGAM_SELECT {
760PRE_DEGAM_SRGB = 0x00000000,
761PRE_DEGAM_GAMMA_22 = 0x00000001,
762PRE_DEGAM_GAMMA_24 = 0x00000002,
763PRE_DEGAM_GAMMA_26 = 0x00000003,
764PRE_DEGAM_BT2020 = 0x00000004,
765PRE_DEGAM_BT2100PQ = 0x00000005,
766PRE_DEGAM_BT2100HLG = 0x00000006,
767} PRE_DEGAM_SELECT;
768
769/*
770 * SURFACE_PIXEL_FORMAT enum
771 */
772
773typedef enum SURFACE_PIXEL_FORMAT {
774ARGB1555 = 0x00000001,
775RGBA5551 = 0x00000002,
776RGB565 = 0x00000003,
777BGR565 = 0x00000004,
778ARGB4444 = 0x00000005,
779RGBA4444 = 0x00000006,
780ARGB8888 = 0x00000008,
781RGBA8888 = 0x00000009,
782ARGB2101010 = 0x0000000a,
783RGBA1010102 = 0x0000000b,
784AYCrCb8888 = 0x0000000c,
785YCrCbA8888 = 0x0000000d,
786ACrYCb8888 = 0x0000000e,
787CrYCbA8888 = 0x0000000f,
788ARGB16161616_10MSB = 0x00000010,
789RGBA16161616_10MSB = 0x00000011,
790ARGB16161616_10LSB = 0x00000012,
791RGBA16161616_10LSB = 0x00000013,
792ARGB16161616_12MSB = 0x00000014,
793RGBA16161616_12MSB = 0x00000015,
794ARGB16161616_12LSB = 0x00000016,
795RGBA16161616_12LSB = 0x00000017,
796ARGB16161616_FLOAT = 0x00000018,
797RGBA16161616_FLOAT = 0x00000019,
798ARGB16161616_UNORM = 0x0000001a,
799RGBA16161616_UNORM = 0x0000001b,
800ARGB16161616_SNORM = 0x0000001c,
801RGBA16161616_SNORM = 0x0000001d,
802AYCrCb16161616_10MSB = 0x00000020,
803AYCrCb16161616_10LSB = 0x00000021,
804YCrCbA16161616_10MSB = 0x00000022,
805YCrCbA16161616_10LSB = 0x00000023,
806ACrYCb16161616_10MSB = 0x00000024,
807ACrYCb16161616_10LSB = 0x00000025,
808CrYCbA16161616_10MSB = 0x00000026,
809CrYCbA16161616_10LSB = 0x00000027,
810AYCrCb16161616_12MSB = 0x00000028,
811AYCrCb16161616_12LSB = 0x00000029,
812YCrCbA16161616_12MSB = 0x0000002a,
813YCrCbA16161616_12LSB = 0x0000002b,
814ACrYCb16161616_12MSB = 0x0000002c,
815ACrYCb16161616_12LSB = 0x0000002d,
816CrYCbA16161616_12MSB = 0x0000002e,
817CrYCbA16161616_12LSB = 0x0000002f,
818Y8_CrCb88_420_PLANAR = 0x00000040,
819Y8_CbCr88_420_PLANAR = 0x00000041,
820Y10_CrCb1010_420_PLANAR = 0x00000042,
821Y10_CbCr1010_420_PLANAR = 0x00000043,
822Y12_CrCb1212_420_PLANAR = 0x00000044,
823Y12_CbCr1212_420_PLANAR = 0x00000045,
824YCrYCb8888_422_PACKED = 0x00000048,
825YCbYCr8888_422_PACKED = 0x00000049,
826CrYCbY8888_422_PACKED = 0x0000004a,
827CbYCrY8888_422_PACKED = 0x0000004b,
828YCrYCb10101010_422_PACKED = 0x0000004c,
829YCbYCr10101010_422_PACKED = 0x0000004d,
830CrYCbY10101010_422_PACKED = 0x0000004e,
831CbYCrY10101010_422_PACKED = 0x0000004f,
832YCrYCb12121212_422_PACKED = 0x00000050,
833YCbYCr12121212_422_PACKED = 0x00000051,
834CrYCbY12121212_422_PACKED = 0x00000052,
835CbYCrY12121212_422_PACKED = 0x00000053,
836RGB111110_FIX = 0x00000070,
837BGR101111_FIX = 0x00000071,
838ACrYCb2101010 = 0x00000072,
839CrYCbA1010102 = 0x00000073,
840RGBE = 0x00000074,
841RGB111110_FLOAT = 0x00000076,
842BGR101111_FLOAT = 0x00000077,
843MONO_8 = 0x00000078,
844MONO_10MSB = 0x00000079,
845MONO_10LSB = 0x0000007a,
846MONO_12MSB = 0x0000007b,
847MONO_12LSB = 0x0000007c,
848MONO_16 = 0x0000007d,
849} SURFACE_PIXEL_FORMAT;
850
851/*
852 * XNORM enum
853 */
854
855typedef enum XNORM {
856XNORM_A = 0x00000000,
857XNORM_B = 0x00000001,
858} XNORM;
859
860/*
861 * CUR_ENABLE enum
862 */
863
864typedef enum CUR_ENABLE {
865CUR_DIS = 0x00000000,
866CUR_EN = 0x00000001,
867} CUR_ENABLE;
868
869/*
870 * CUR_EXPAND_MODE enum
871 */
872
873typedef enum CUR_EXPAND_MODE {
874CUR_DYNAMIC_EXPANSION = 0x00000000,
875CUR_ZERO_EXPANSION = 0x00000001,
876} CUR_EXPAND_MODE;
877
878/*
879 * CUR_INV_CLAMP enum
880 */
881
882typedef enum CUR_INV_CLAMP {
883CUR_CLAMP_DIS = 0x00000000,
884CUR_CLAMP_EN = 0x00000001,
885} CUR_INV_CLAMP;
886
887/*
888 * CUR_MATRIX_COEF_FORMAT_ENUM enum
889 */
890
891typedef enum CUR_MATRIX_COEF_FORMAT_ENUM {
892CUR_MATRIX_FIX_S2_13 = 0x00000000,
893CUR_MATRIX_FIX_S3_12 = 0x00000001,
894} CUR_MATRIX_COEF_FORMAT_ENUM;
895
896/*
897 * CUR_MODE enum
898 */
899
900typedef enum CUR_MODE {
901MONO_2BIT = 0x00000000,
902COLOR_24BIT_1BIT_AND = 0x00000001,
903COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002,
904COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003,
905COLOR_64BIT_FP_PREMULT = 0x00000004,
906COLOR_64BIT_FP_UNPREMULT = 0x00000005,
907} CUR_MODE;
908
909/*
910 * CUR_PENDING enum
911 */
912
913typedef enum CUR_PENDING {
914CUR_NOT_PENDING = 0x00000000,
915CUR_YES_PENDING = 0x00000001,
916} CUR_PENDING;
917
918/*
919 * CUR_ROM_EN enum
920 */
921
922typedef enum CUR_ROM_EN {
923CUR_FP_NO_ROM = 0x00000000,
924CUR_FP_USE_ROM = 0x00000001,
925} CUR_ROM_EN;
926
927/*
928 * COEF_RAM_SELECT_RD enum
929 */
930
931typedef enum COEF_RAM_SELECT_RD {
932COEF_RAM_SELECT_BACK = 0x00000000,
933COEF_RAM_SELECT_CURRENT = 0x00000001,
934} COEF_RAM_SELECT_RD;
935
936/*
937 * DSCL_MODE_SEL enum
938 */
939
940typedef enum DSCL_MODE_SEL {
941DSCL_MODE_SCALING_444_BYPASS = 0x00000000,
942DSCL_MODE_SCALING_444_RGB_ENABLE = 0x00000001,
943DSCL_MODE_SCALING_444_YCBCR_ENABLE = 0x00000002,
944DSCL_MODE_SCALING_YCBCR_ENABLE = 0x00000003,
945DSCL_MODE_LUMA_SCALING_BYPASS = 0x00000004,
946DSCL_MODE_CHROMA_SCALING_BYPASS = 0x00000005,
947DSCL_MODE_DSCL_BYPASS = 0x00000006,
948} DSCL_MODE_SEL;
949
950/*
951 * ISHARP_FMT_MODE_ENUM enum
952 */
953
954typedef enum ISHARP_FMT_MODE_ENUM {
955ISHARP_FMT_MODE_0 = 0x00000000,
956ISHARP_FMT_MODE_1 = 0x00000001,
957} ISHARP_FMT_MODE_ENUM;
958
959/*
960 * ISHARP_LBA_MODE_ENUM enum
961 */
962
963typedef enum ISHARP_LBA_MODE_ENUM {
964ISHARP_LBA_MODE_0 = 0x00000000,
965ISHARP_LBA_MODE_1 = 0x00000001,
966} ISHARP_LBA_MODE_ENUM;
967
968/*
969 * ISHARP_NOISEDET_MODE_ENUM enum
970 */
971
972typedef enum ISHARP_NOISEDET_MODE_ENUM {
973ISHARP_NOISEDET_MODE_0 = 0x00000000,
974ISHARP_NOISEDET_MODE_1 = 0x00000001,
975ISHARP_NOISEDET_MODE_2 = 0x00000002,
976ISHARP_NOISEDET_MODE_3 = 0x00000003,
977} ISHARP_NOISEDET_MODE_ENUM;
978
979/*
980 * LB_ALPHA_EN enum
981 */
982
983typedef enum LB_ALPHA_EN {
984LB_ALPHA_DISABLE = 0x00000000,
985LB_ALPHA_ENABLE = 0x00000001,
986} LB_ALPHA_EN;
987
988/*
989 * LB_INTERLEAVE_EN enum
990 */
991
992typedef enum LB_INTERLEAVE_EN {
993LB_INTERLEAVE_DISABLE = 0x00000000,
994LB_INTERLEAVE_ENABLE = 0x00000001,
995} LB_INTERLEAVE_EN;
996
997/*
998 * LB_MEMORY_CONFIG enum
999 */
1000
1001typedef enum LB_MEMORY_CONFIG {
1002LB_MEMORY_CONFIG_0 = 0x00000000,
1003LB_MEMORY_CONFIG_1 = 0x00000001,
1004LB_MEMORY_CONFIG_2 = 0x00000002,
1005LB_MEMORY_CONFIG_3 = 0x00000003,
1006} LB_MEMORY_CONFIG;
1007
1008/*
1009 * MATRIX_MODE_ENUM enum
1010 */
1011
1012typedef enum MATRIX_MODE_ENUM {
1013MATRIX_MODE_0 = 0x00000000,
1014MATRIX_MODE_1 = 0x00000001,
1015} MATRIX_MODE_ENUM;
1016
1017/*
1018 * OBUF_BYPASS_SEL enum
1019 */
1020
1021typedef enum OBUF_BYPASS_SEL {
1022OBUF_BYPASS_DIS = 0x00000000,
1023OBUF_BYPASS_EN = 0x00000001,
1024} OBUF_BYPASS_SEL;
1025
1026/*
1027 * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum
1028 */
1029
1030typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL {
1031OBUF_FULL_RECOUT = 0x00000000,
1032OBUF_HALF_RECOUT = 0x00000001,
1033} OBUF_IS_HALF_RECOUT_WIDTH_SEL;
1034
1035/*
1036 * OBUF_USE_FULL_BUFFER_SEL enum
1037 */
1038
1039typedef enum OBUF_USE_FULL_BUFFER_SEL {
1040OBUF_RECOUT = 0x00000000,
1041OBUF_FULL = 0x00000001,
1042} OBUF_USE_FULL_BUFFER_SEL;
1043
1044/*
1045 * SCL_2TAP_HARDCODE enum
1046 */
1047
1048typedef enum SCL_2TAP_HARDCODE {
1049SCL_COEF_2TAP_HARDCODE_OFF = 0x00000000,
1050SCL_COEF_2TAP_HARDCODE_ON = 0x00000001,
1051} SCL_2TAP_HARDCODE;
1052
1053/*
1054 * SCL_ALPHA_COEF enum
1055 */
1056
1057typedef enum SCL_ALPHA_COEF {
1058SCL_ALPHA_COEF_FIRST = 0x00000000,
1059SCL_ALPHA_COEF_SECOND = 0x00000001,
1060} SCL_ALPHA_COEF;
1061
1062/*
1063 * SCL_AUTOCAL_MODE enum
1064 */
1065
1066typedef enum SCL_AUTOCAL_MODE {
1067AUTOCAL_MODE_OFF = 0x00000000,
1068AUTOCAL_MODE_AUTOSCALE = 0x00000001,
1069AUTOCAL_MODE_AUTOCENTER = 0x00000002,
1070AUTOCAL_MODE_AUTOREPLICATE = 0x00000003,
1071} SCL_AUTOCAL_MODE;
1072
1073/*
1074 * SCL_BOUNDARY enum
1075 */
1076
1077typedef enum SCL_BOUNDARY {
1078SCL_BOUNDARY_EDGE = 0x00000000,
1079SCL_BOUNDARY_BLACK = 0x00000001,
1080} SCL_BOUNDARY;
1081
1082/*
1083 * SCL_CHROMA_COEF enum
1084 */
1085
1086typedef enum SCL_CHROMA_COEF {
1087SCL_CHROMA_COEF_FIRST = 0x00000000,
1088SCL_CHROMA_COEF_SECOND = 0x00000001,
1089} SCL_CHROMA_COEF;
1090
1091/*
1092 * SCL_COEF_FILTER_TYPE_SEL enum
1093 */
1094
1095typedef enum SCL_COEF_FILTER_TYPE_SEL {
1096SCL_COEF_LUMA_VERT_FILTER = 0x00000000,
1097SCL_COEF_LUMA_HORZ_FILTER = 0x00000001,
1098SCL_COEF_CHROMA_VERT_FILTER = 0x00000002,
1099SCL_COEF_CHROMA_HORZ_FILTER = 0x00000003,
1100SCL_COEF_SC_VERT_FILTER = 0x00000004,
1101SCL_COEF_SC_HORZ_FILTER = 0x00000005,
1102} SCL_COEF_FILTER_TYPE_SEL;
1103
1104/*
1105 * SCL_COEF_RAM_SEL enum
1106 */
1107
1108typedef enum SCL_COEF_RAM_SEL {
1109SCL_COEF_RAM_SEL_0 = 0x00000000,
1110SCL_COEF_RAM_SEL_1 = 0x00000001,
1111} SCL_COEF_RAM_SEL;
1112
1113/*
1114 * SCL_SHARP_EN enum
1115 */
1116
1117typedef enum SCL_SHARP_EN {
1118SCL_SHARP_DISABLE = 0x00000000,
1119SCL_SHARP_ENABLE = 0x00000001,
1120} SCL_SHARP_EN;
1121
1122/*******************************************************
1123 * CM Enums
1124 *******************************************************/
1125
1126/*
1127 * CMC_3DLUT_30BIT_ENUM enum
1128 */
1129
1130typedef enum CMC_3DLUT_30BIT_ENUM {
1131CMC_3DLUT_36BIT = 0x00000000,
1132CMC_3DLUT_30BIT = 0x00000001,
1133} CMC_3DLUT_30BIT_ENUM;
1134
1135/*
1136 * CMC_3DLUT_RAM_SEL enum
1137 */
1138
1139typedef enum CMC_3DLUT_RAM_SEL {
1140CMC_RAM0_ACCESS = 0x00000000,
1141CMC_RAM1_ACCESS = 0x00000001,
1142CMC_RAM2_ACCESS = 0x00000002,
1143CMC_RAM3_ACCESS = 0x00000003,
1144} CMC_3DLUT_RAM_SEL;
1145
1146/*
1147 * CMC_3DLUT_SIZE_ENUM enum
1148 */
1149
1150typedef enum CMC_3DLUT_SIZE_ENUM {
1151CMC_3DLUT_17CUBE = 0x00000000,
1152CMC_3DLUT_9CUBE = 0x00000001,
1153} CMC_3DLUT_SIZE_ENUM;
1154
1155/*
1156 * CMC_LUT_2_CONFIG_ENUM enum
1157 */
1158
1159typedef enum CMC_LUT_2_CONFIG_ENUM {
1160CMC_LUT_2CFG_NO_MEMORY = 0x00000000,
1161CMC_LUT_2CFG_MEMORY_A = 0x00000001,
1162CMC_LUT_2CFG_MEMORY_B = 0x00000002,
1163} CMC_LUT_2_CONFIG_ENUM;
1164
1165/*
1166 * CMC_LUT_2_MODE_ENUM enum
1167 */
1168
1169typedef enum CMC_LUT_2_MODE_ENUM {
1170CMC_LUT_2_MODE_BYPASS = 0x00000000,
1171CMC_LUT_2_MODE_RAMA_LUT = 0x00000001,
1172CMC_LUT_2_MODE_RAMB_LUT = 0x00000002,
1173} CMC_LUT_2_MODE_ENUM;
1174
1175/*
1176 * CMC_LUT_NUM_SEG enum
1177 */
1178
1179typedef enum CMC_LUT_NUM_SEG {
1180CMC_SEGMENTS_1 = 0x00000000,
1181CMC_SEGMENTS_2 = 0x00000001,
1182CMC_SEGMENTS_4 = 0x00000002,
1183CMC_SEGMENTS_8 = 0x00000003,
1184CMC_SEGMENTS_16 = 0x00000004,
1185CMC_SEGMENTS_32 = 0x00000005,
1186CMC_SEGMENTS_64 = 0x00000006,
1187CMC_SEGMENTS_128 = 0x00000007,
1188} CMC_LUT_NUM_SEG;
1189
1190/*
1191 * CMC_LUT_RAM_SEL enum
1192 */
1193
1194typedef enum CMC_LUT_RAM_SEL {
1195CMC_RAMA_ACCESS = 0x00000000,
1196CMC_RAMB_ACCESS = 0x00000001,
1197} CMC_LUT_RAM_SEL;
1198
1199/*
1200 * CM_BYPASS enum
1201 */
1202
1203typedef enum CM_BYPASS {
1204NON_BYPASS = 0x00000000,
1205BYPASS_EN = 0x00000001,
1206} CM_BYPASS;
1207
1208/*
1209 * CM_COEF_FORMAT_ENUM enum
1210 */
1211
1212typedef enum CM_COEF_FORMAT_ENUM {
1213FIX_S2_13 = 0x00000000,
1214FIX_S3_12 = 0x00000001,
1215} CM_COEF_FORMAT_ENUM;
1216
1217/*
1218 * CM_DATA_SIGNED enum
1219 */
1220
1221typedef enum CM_DATA_SIGNED {
1222UNSIGNED = 0x00000000,
1223SIGNED = 0x00000001,
1224} CM_DATA_SIGNED;
1225
1226/*
1227 * CM_EN enum
1228 */
1229
1230typedef enum CM_EN {
1231CM_DISABLE = 0x00000000,
1232CM_ENABLE = 0x00000001,
1233} CM_EN;
1234
1235/*
1236 * CM_GAMMA_LUT_MODE_ENUM enum
1237 */
1238
1239typedef enum CM_GAMMA_LUT_MODE_ENUM {
1240BYPASS = 0x00000000,
1241RESERVED_1 = 0x00000001,
1242RAM_LUT = 0x00000002,
1243RESERVED_3 = 0x00000003,
1244} CM_GAMMA_LUT_MODE_ENUM;
1245
1246/*
1247 * CM_GAMMA_LUT_PWL_DISABLE_ENUM enum
1248 */
1249
1250typedef enum CM_GAMMA_LUT_PWL_DISABLE_ENUM {
1251ENABLE_PWL = 0x00000000,
1252DISABLE_PWL = 0x00000001,
1253} CM_GAMMA_LUT_PWL_DISABLE_ENUM;
1254
1255/*
1256 * CM_GAMMA_LUT_SEL_ENUM enum
1257 */
1258
1259typedef enum CM_GAMMA_LUT_SEL_ENUM {
1260RAMA = 0x00000000,
1261RAMB = 0x00000001,
1262} CM_GAMMA_LUT_SEL_ENUM;
1263
1264/*
1265 * CM_LUT_2_CONFIG_ENUM enum
1266 */
1267
1268typedef enum CM_LUT_2_CONFIG_ENUM {
1269LUT_2CFG_NO_MEMORY = 0x00000000,
1270LUT_2CFG_MEMORY_A = 0x00000001,
1271LUT_2CFG_MEMORY_B = 0x00000002,
1272} CM_LUT_2_CONFIG_ENUM;
1273
1274/*
1275 * CM_LUT_2_MODE_ENUM enum
1276 */
1277
1278typedef enum CM_LUT_2_MODE_ENUM {
1279LUT_2_MODE_BYPASS = 0x00000000,
1280LUT_2_MODE_RAMA_LUT = 0x00000001,
1281LUT_2_MODE_RAMB_LUT = 0x00000002,
1282} CM_LUT_2_MODE_ENUM;
1283
1284/*
1285 * CM_LUT_4_CONFIG_ENUM enum
1286 */
1287
1288typedef enum CM_LUT_4_CONFIG_ENUM {
1289LUT_4CFG_NO_MEMORY = 0x00000000,
1290LUT_4CFG_ROM_A = 0x00000001,
1291LUT_4CFG_ROM_B = 0x00000002,
1292LUT_4CFG_MEMORY_A = 0x00000003,
1293LUT_4CFG_MEMORY_B = 0x00000004,
1294} CM_LUT_4_CONFIG_ENUM;
1295
1296/*
1297 * CM_LUT_4_MODE_ENUM enum
1298 */
1299
1300typedef enum CM_LUT_4_MODE_ENUM {
1301LUT_4_MODE_BYPASS = 0x00000000,
1302LUT_4_MODE_ROMA_LUT = 0x00000001,
1303LUT_4_MODE_ROMB_LUT = 0x00000002,
1304LUT_4_MODE_RAMA_LUT = 0x00000003,
1305LUT_4_MODE_RAMB_LUT = 0x00000004,
1306} CM_LUT_4_MODE_ENUM;
1307
1308/*
1309 * CM_LUT_CONFIG_MODE enum
1310 */
1311
1312typedef enum CM_LUT_CONFIG_MODE {
1313DIFFERENT_RGB = 0x00000000,
1314ALL_USE_R = 0x00000001,
1315} CM_LUT_CONFIG_MODE;
1316
1317/*
1318 * CM_LUT_NUM_SEG enum
1319 */
1320
1321typedef enum CM_LUT_NUM_SEG {
1322SEGMENTS_1 = 0x00000000,
1323SEGMENTS_2 = 0x00000001,
1324SEGMENTS_4 = 0x00000002,
1325SEGMENTS_8 = 0x00000003,
1326SEGMENTS_16 = 0x00000004,
1327SEGMENTS_32 = 0x00000005,
1328SEGMENTS_64 = 0x00000006,
1329SEGMENTS_128 = 0x00000007,
1330} CM_LUT_NUM_SEG;
1331
1332/*
1333 * CM_LUT_RAM_SEL enum
1334 */
1335
1336typedef enum CM_LUT_RAM_SEL {
1337RAMA_ACCESS = 0x00000000,
1338RAMB_ACCESS = 0x00000001,
1339} CM_LUT_RAM_SEL;
1340
1341/*
1342 * CM_LUT_READ_COLOR_SEL enum
1343 */
1344
1345typedef enum CM_LUT_READ_COLOR_SEL {
1346BLUE_LUT = 0x00000000,
1347GREEN_LUT = 0x00000001,
1348RED_LUT = 0x00000002,
1349} CM_LUT_READ_COLOR_SEL;
1350
1351/*
1352 * CM_LUT_READ_DBG enum
1353 */
1354
1355typedef enum CM_LUT_READ_DBG {
1356DISABLE_DEBUG = 0x00000000,
1357ENABLE_DEBUG = 0x00000001,
1358} CM_LUT_READ_DBG;
1359
1360/*
1361 * CM_PENDING enum
1362 */
1363
1364typedef enum CM_PENDING {
1365CM_NOT_PENDING = 0x00000000,
1366CM_YES_PENDING = 0x00000001,
1367} CM_PENDING;
1368
1369/*
1370 * CM_POST_CSC_MODE_ENUM enum
1371 */
1372
1373typedef enum CM_POST_CSC_MODE_ENUM {
1374BYPASS_POST_CSC = 0x00000000,
1375COEF_POST_CSC = 0x00000001,
1376COEF_POST_CSC_B = 0x00000002,
1377} CM_POST_CSC_MODE_ENUM;
1378
1379/*
1380 * CM_WRITE_BASE_ONLY enum
1381 */
1382
1383typedef enum CM_WRITE_BASE_ONLY {
1384WRITE_BOTH = 0x00000000,
1385WRITE_BASE_ONLY = 0x00000001,
1386} CM_WRITE_BASE_ONLY;
1387
1388/*******************************************************
1389 * DPP_TOP Enums
1390 *******************************************************/
1391
1392/*
1393 * CRC_CUR_SEL enum
1394 */
1395
1396typedef enum CRC_CUR_SEL {
1397CRC_CUR_0 = 0x00000000,
1398CRC_CUR_1 = 0x00000001,
1399} CRC_CUR_SEL;
1400
1401/*
1402 * CRC_INTERLACE_SEL enum
1403 */
1404
1405typedef enum CRC_INTERLACE_SEL {
1406CRC_INTERLACE_0 = 0x00000000,
1407CRC_INTERLACE_1 = 0x00000001,
1408CRC_INTERLACE_2 = 0x00000002,
1409CRC_INTERLACE_3 = 0x00000003,
1410} CRC_INTERLACE_SEL;
1411
1412/*
1413 * CRC_IN_PIX_SEL enum
1414 */
1415
1416typedef enum CRC_IN_PIX_SEL {
1417CRC_IN_PIX_0 = 0x00000000,
1418CRC_IN_PIX_1 = 0x00000001,
1419CRC_IN_PIX_2 = 0x00000002,
1420CRC_IN_PIX_3 = 0x00000003,
1421CRC_IN_PIX_4 = 0x00000004,
1422CRC_IN_PIX_5 = 0x00000005,
1423CRC_IN_PIX_6 = 0x00000006,
1424CRC_IN_PIX_7 = 0x00000007,
1425} CRC_IN_PIX_SEL;
1426
1427/*
1428 * CRC_SRC_SEL enum
1429 */
1430
1431typedef enum CRC_SRC_SEL {
1432CRC_SRC_0 = 0x00000000,
1433CRC_SRC_1 = 0x00000001,
1434CRC_SRC_2 = 0x00000002,
1435CRC_SRC_3 = 0x00000003,
1436} CRC_SRC_SEL;
1437
1438/*
1439 * CRC_STEREO_SEL enum
1440 */
1441
1442typedef enum CRC_STEREO_SEL {
1443CRC_STEREO_0 = 0x00000000,
1444CRC_STEREO_1 = 0x00000001,
1445CRC_STEREO_2 = 0x00000002,
1446CRC_STEREO_3 = 0x00000003,
1447} CRC_STEREO_SEL;
1448
1449/*
1450 * TEST_CLK_SEL enum
1451 */
1452
1453typedef enum TEST_CLK_SEL {
1454TEST_CLK_SEL_0 = 0x00000000,
1455TEST_CLK_SEL_1 = 0x00000001,
1456TEST_CLK_SEL_2 = 0x00000002,
1457TEST_CLK_SEL_3 = 0x00000003,
1458TEST_CLK_SEL_4 = 0x00000004,
1459TEST_CLK_SEL_5 = 0x00000005,
1460TEST_CLK_SEL_6 = 0x00000006,
1461TEST_CLK_SEL_7 = 0x00000007,
1462} TEST_CLK_SEL;
1463
1464/*******************************************************
1465 * DC_PERFMON Enums
1466 *******************************************************/
1467
1468/*
1469 * PERFCOUNTER_ACTIVE enum
1470 */
1471
1472typedef enum PERFCOUNTER_ACTIVE {
1473PERFCOUNTER_IS_IDLE = 0x00000000,
1474PERFCOUNTER_IS_ACTIVE = 0x00000001,
1475} PERFCOUNTER_ACTIVE;
1476
1477/*
1478 * PERFCOUNTER_CNT0_STATE enum
1479 */
1480
1481typedef enum PERFCOUNTER_CNT0_STATE {
1482PERFCOUNTER_CNT0_STATE_RESET = 0x00000000,
1483PERFCOUNTER_CNT0_STATE_START = 0x00000001,
1484PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002,
1485PERFCOUNTER_CNT0_STATE_HW = 0x00000003,
1486} PERFCOUNTER_CNT0_STATE;
1487
1488/*
1489 * PERFCOUNTER_CNT1_STATE enum
1490 */
1491
1492typedef enum PERFCOUNTER_CNT1_STATE {
1493PERFCOUNTER_CNT1_STATE_RESET = 0x00000000,
1494PERFCOUNTER_CNT1_STATE_START = 0x00000001,
1495PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002,
1496PERFCOUNTER_CNT1_STATE_HW = 0x00000003,
1497} PERFCOUNTER_CNT1_STATE;
1498
1499/*
1500 * PERFCOUNTER_CNT2_STATE enum
1501 */
1502
1503typedef enum PERFCOUNTER_CNT2_STATE {
1504PERFCOUNTER_CNT2_STATE_RESET = 0x00000000,
1505PERFCOUNTER_CNT2_STATE_START = 0x00000001,
1506PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002,
1507PERFCOUNTER_CNT2_STATE_HW = 0x00000003,
1508} PERFCOUNTER_CNT2_STATE;
1509
1510/*
1511 * PERFCOUNTER_CNT3_STATE enum
1512 */
1513
1514typedef enum PERFCOUNTER_CNT3_STATE {
1515PERFCOUNTER_CNT3_STATE_RESET = 0x00000000,
1516PERFCOUNTER_CNT3_STATE_START = 0x00000001,
1517PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002,
1518PERFCOUNTER_CNT3_STATE_HW = 0x00000003,
1519} PERFCOUNTER_CNT3_STATE;
1520
1521/*
1522 * PERFCOUNTER_CNT4_STATE enum
1523 */
1524
1525typedef enum PERFCOUNTER_CNT4_STATE {
1526PERFCOUNTER_CNT4_STATE_RESET = 0x00000000,
1527PERFCOUNTER_CNT4_STATE_START = 0x00000001,
1528PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002,
1529PERFCOUNTER_CNT4_STATE_HW = 0x00000003,
1530} PERFCOUNTER_CNT4_STATE;
1531
1532/*
1533 * PERFCOUNTER_CNT5_STATE enum
1534 */
1535
1536typedef enum PERFCOUNTER_CNT5_STATE {
1537PERFCOUNTER_CNT5_STATE_RESET = 0x00000000,
1538PERFCOUNTER_CNT5_STATE_START = 0x00000001,
1539PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002,
1540PERFCOUNTER_CNT5_STATE_HW = 0x00000003,
1541} PERFCOUNTER_CNT5_STATE;
1542
1543/*
1544 * PERFCOUNTER_CNT6_STATE enum
1545 */
1546
1547typedef enum PERFCOUNTER_CNT6_STATE {
1548PERFCOUNTER_CNT6_STATE_RESET = 0x00000000,
1549PERFCOUNTER_CNT6_STATE_START = 0x00000001,
1550PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002,
1551PERFCOUNTER_CNT6_STATE_HW = 0x00000003,
1552} PERFCOUNTER_CNT6_STATE;
1553
1554/*
1555 * PERFCOUNTER_CNT7_STATE enum
1556 */
1557
1558typedef enum PERFCOUNTER_CNT7_STATE {
1559PERFCOUNTER_CNT7_STATE_RESET = 0x00000000,
1560PERFCOUNTER_CNT7_STATE_START = 0x00000001,
1561PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002,
1562PERFCOUNTER_CNT7_STATE_HW = 0x00000003,
1563} PERFCOUNTER_CNT7_STATE;
1564
1565/*
1566 * PERFCOUNTER_CNTL_SEL enum
1567 */
1568
1569typedef enum PERFCOUNTER_CNTL_SEL {
1570PERFCOUNTER_CNTL_SEL_0 = 0x00000000,
1571PERFCOUNTER_CNTL_SEL_1 = 0x00000001,
1572PERFCOUNTER_CNTL_SEL_2 = 0x00000002,
1573PERFCOUNTER_CNTL_SEL_3 = 0x00000003,
1574PERFCOUNTER_CNTL_SEL_4 = 0x00000004,
1575PERFCOUNTER_CNTL_SEL_5 = 0x00000005,
1576PERFCOUNTER_CNTL_SEL_6 = 0x00000006,
1577PERFCOUNTER_CNTL_SEL_7 = 0x00000007,
1578} PERFCOUNTER_CNTL_SEL;
1579
1580/*
1581 * PERFCOUNTER_CNTOFF_START_DIS enum
1582 */
1583
1584typedef enum PERFCOUNTER_CNTOFF_START_DIS {
1585PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000,
1586PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001,
1587} PERFCOUNTER_CNTOFF_START_DIS;
1588
1589/*
1590 * PERFCOUNTER_COUNTED_VALUE_TYPE enum
1591 */
1592
1593typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
1594PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000,
1595PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001,
1596PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002,
1597} PERFCOUNTER_COUNTED_VALUE_TYPE;
1598
1599/*
1600 * PERFCOUNTER_CVALUE_SEL enum
1601 */
1602
1603typedef enum PERFCOUNTER_CVALUE_SEL {
1604PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000,
1605PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001,
1606PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002,
1607PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003,
1608PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004,
1609PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005,
1610PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006,
1611PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007,
1612} PERFCOUNTER_CVALUE_SEL;
1613
1614/*
1615 * PERFCOUNTER_HW_CNTL_SEL enum
1616 */
1617
1618typedef enum PERFCOUNTER_HW_CNTL_SEL {
1619PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000,
1620PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001,
1621} PERFCOUNTER_HW_CNTL_SEL;
1622
1623/*
1624 * PERFCOUNTER_HW_STOP1_SEL enum
1625 */
1626
1627typedef enum PERFCOUNTER_HW_STOP1_SEL {
1628PERFCOUNTER_HW_STOP1_0 = 0x00000000,
1629PERFCOUNTER_HW_STOP1_1 = 0x00000001,
1630} PERFCOUNTER_HW_STOP1_SEL;
1631
1632/*
1633 * PERFCOUNTER_HW_STOP2_SEL enum
1634 */
1635
1636typedef enum PERFCOUNTER_HW_STOP2_SEL {
1637PERFCOUNTER_HW_STOP2_0 = 0x00000000,
1638PERFCOUNTER_HW_STOP2_1 = 0x00000001,
1639} PERFCOUNTER_HW_STOP2_SEL;
1640
1641/*
1642 * PERFCOUNTER_INC_MODE enum
1643 */
1644
1645typedef enum PERFCOUNTER_INC_MODE {
1646PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000,
1647PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001,
1648PERFCOUNTER_INC_MODE_LSB = 0x00000002,
1649PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003,
1650PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004,
1651} PERFCOUNTER_INC_MODE;
1652
1653/*
1654 * PERFCOUNTER_INT_EN enum
1655 */
1656
1657typedef enum PERFCOUNTER_INT_EN {
1658PERFCOUNTER_INT_DISABLE = 0x00000000,
1659PERFCOUNTER_INT_ENABLE = 0x00000001,
1660} PERFCOUNTER_INT_EN;
1661
1662/*
1663 * PERFCOUNTER_INT_TYPE enum
1664 */
1665
1666typedef enum PERFCOUNTER_INT_TYPE {
1667PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000,
1668PERFCOUNTER_INT_TYPE_PULSE = 0x00000001,
1669} PERFCOUNTER_INT_TYPE;
1670
1671/*
1672 * PERFCOUNTER_OFF_MASK enum
1673 */
1674
1675typedef enum PERFCOUNTER_OFF_MASK {
1676PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000,
1677PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001,
1678} PERFCOUNTER_OFF_MASK;
1679
1680/*
1681 * PERFCOUNTER_RESTART_EN enum
1682 */
1683
1684typedef enum PERFCOUNTER_RESTART_EN {
1685PERFCOUNTER_RESTART_DISABLE = 0x00000000,
1686PERFCOUNTER_RESTART_ENABLE = 0x00000001,
1687} PERFCOUNTER_RESTART_EN;
1688
1689/*
1690 * PERFCOUNTER_RUNEN_MODE enum
1691 */
1692
1693typedef enum PERFCOUNTER_RUNEN_MODE {
1694PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000,
1695PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001,
1696} PERFCOUNTER_RUNEN_MODE;
1697
1698/*
1699 * PERFCOUNTER_STATE_SEL0 enum
1700 */
1701
1702typedef enum PERFCOUNTER_STATE_SEL0 {
1703PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000,
1704PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001,
1705} PERFCOUNTER_STATE_SEL0;
1706
1707/*
1708 * PERFCOUNTER_STATE_SEL1 enum
1709 */
1710
1711typedef enum PERFCOUNTER_STATE_SEL1 {
1712PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000,
1713PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001,
1714} PERFCOUNTER_STATE_SEL1;
1715
1716/*
1717 * PERFCOUNTER_STATE_SEL2 enum
1718 */
1719
1720typedef enum PERFCOUNTER_STATE_SEL2 {
1721PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000,
1722PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001,
1723} PERFCOUNTER_STATE_SEL2;
1724
1725/*
1726 * PERFCOUNTER_STATE_SEL3 enum
1727 */
1728
1729typedef enum PERFCOUNTER_STATE_SEL3 {
1730PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000,
1731PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001,
1732} PERFCOUNTER_STATE_SEL3;
1733
1734/*
1735 * PERFCOUNTER_STATE_SEL4 enum
1736 */
1737
1738typedef enum PERFCOUNTER_STATE_SEL4 {
1739PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000,
1740PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001,
1741} PERFCOUNTER_STATE_SEL4;
1742
1743/*
1744 * PERFCOUNTER_STATE_SEL5 enum
1745 */
1746
1747typedef enum PERFCOUNTER_STATE_SEL5 {
1748PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000,
1749PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001,
1750} PERFCOUNTER_STATE_SEL5;
1751
1752/*
1753 * PERFCOUNTER_STATE_SEL6 enum
1754 */
1755
1756typedef enum PERFCOUNTER_STATE_SEL6 {
1757PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000,
1758PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001,
1759} PERFCOUNTER_STATE_SEL6;
1760
1761/*
1762 * PERFCOUNTER_STATE_SEL7 enum
1763 */
1764
1765typedef enum PERFCOUNTER_STATE_SEL7 {
1766PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000,
1767PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001,
1768} PERFCOUNTER_STATE_SEL7;
1769
1770/*
1771 * PERFMON_CNTOFF_AND_OR enum
1772 */
1773
1774typedef enum PERFMON_CNTOFF_AND_OR {
1775PERFMON_CNTOFF_OR = 0x00000000,
1776PERFMON_CNTOFF_AND = 0x00000001,
1777} PERFMON_CNTOFF_AND_OR;
1778
1779/*
1780 * PERFMON_CNTOFF_INT_EN enum
1781 */
1782
1783typedef enum PERFMON_CNTOFF_INT_EN {
1784PERFMON_CNTOFF_INT_DISABLE = 0x00000000,
1785PERFMON_CNTOFF_INT_ENABLE = 0x00000001,
1786} PERFMON_CNTOFF_INT_EN;
1787
1788/*
1789 * PERFMON_CNTOFF_INT_TYPE enum
1790 */
1791
1792typedef enum PERFMON_CNTOFF_INT_TYPE {
1793PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000,
1794PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001,
1795} PERFMON_CNTOFF_INT_TYPE;
1796
1797/*
1798 * PERFMON_STATE enum
1799 */
1800
1801typedef enum PERFMON_STATE {
1802PERFMON_STATE_RESET = 0x00000000,
1803PERFMON_STATE_START = 0x00000001,
1804PERFMON_STATE_FREEZE = 0x00000002,
1805PERFMON_STATE_HW = 0x00000003,
1806} PERFMON_STATE;
1807
1808/*******************************************************
1809 * HUBP Enums
1810 *******************************************************/
1811
1812/*
1813 * BIGK_FRAGMENT_SIZE enum
1814 */
1815
1816typedef enum BIGK_FRAGMENT_SIZE {
1817VM_PG_SIZE_4KB = 0x00000000,
1818VM_PG_SIZE_8KB = 0x00000001,
1819VM_PG_SIZE_16KB = 0x00000002,
1820VM_PG_SIZE_32KB = 0x00000003,
1821VM_PG_SIZE_64KB = 0x00000004,
1822VM_PG_SIZE_128KB = 0x00000005,
1823VM_PG_SIZE_256KB = 0x00000006,
1824VM_PG_SIZE_512KB = 0x00000007,
1825VM_PG_SIZE_1MB = 0x00000008,
1826VM_PG_SIZE_2MB = 0x00000009,
1827VM_PG_SIZE_4MB = 0x0000000a,
1828VM_PG_SIZE_8MB = 0x0000000b,
1829VM_PG_SIZE_16MB = 0x0000000c,
1830VM_PG_SIZE_32MB = 0x0000000d,
1831VM_PG_SIZE_64MB = 0x0000000e,
1832VM_PG_SIZE_128MB = 0x0000000f,
1833} BIGK_FRAGMENT_SIZE;
1834
1835/*
1836 * CHUNK_SIZE enum
1837 */
1838
1839typedef enum CHUNK_SIZE {
1840CHUNK_SIZE_1KB = 0x00000000,
1841CHUNK_SIZE_2KB = 0x00000001,
1842CHUNK_SIZE_4KB = 0x00000002,
1843CHUNK_SIZE_8KB = 0x00000003,
1844CHUNK_SIZE_16KB = 0x00000004,
1845CHUNK_SIZE_32KB = 0x00000005,
1846CHUNK_SIZE_64KB = 0x00000006,
1847} CHUNK_SIZE;
1848
1849/*
1850 * DPTE_GROUP_SIZE enum
1851 */
1852
1853typedef enum DPTE_GROUP_SIZE {
1854DPTE_GROUP_SIZE_64B = 0x00000000,
1855DPTE_GROUP_SIZE_128B = 0x00000001,
1856DPTE_GROUP_SIZE_256B = 0x00000002,
1857DPTE_GROUP_SIZE_512B = 0x00000003,
1858DPTE_GROUP_SIZE_1024B = 0x00000004,
1859DPTE_GROUP_SIZE_2048B = 0x00000005,
1860} DPTE_GROUP_SIZE;
1861
1862/*
1863 * FORCE_ONE_ROW_FOR_FRAME enum
1864 */
1865
1866typedef enum FORCE_ONE_ROW_FOR_FRAME {
1867FORCE_ONE_ROW_FOR_FRAME_0 = 0x00000000,
1868FORCE_ONE_ROW_FOR_FRAME_1 = 0x00000001,
1869} FORCE_ONE_ROW_FOR_FRAME;
1870
1871/*
1872 * HUBP_BLANK_EN enum
1873 */
1874
1875typedef enum HUBP_BLANK_EN {
1876HUBP_BLANK_SW_DEASSERT = 0x00000000,
1877HUBP_BLANK_SW_ASSERT = 0x00000001,
1878} HUBP_BLANK_EN;
1879
1880/*
1881 * HUBP_IN_BLANK enum
1882 */
1883
1884typedef enum HUBP_IN_BLANK {
1885HUBP_IN_ACTIVE = 0x00000000,
1886HUBP_IN_VBLANK = 0x00000001,
1887} HUBP_IN_BLANK;
1888
1889/*
1890 * HUBP_MEASURE_WIN_MODE_DCFCLK enum
1891 */
1892
1893typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK {
1894HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0x00000000,
1895HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 0x00000001,
1896HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 0x00000002,
1897HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 0x00000003,
1898} HUBP_MEASURE_WIN_MODE_DCFCLK;
1899
1900/*
1901 * HUBP_NO_OUTSTANDING_REQ enum
1902 */
1903
1904typedef enum HUBP_NO_OUTSTANDING_REQ {
1905OUTSTANDING_REQ = 0x00000000,
1906NO_OUTSTANDING_REQ = 0x00000001,
1907} HUBP_NO_OUTSTANDING_REQ;
1908
1909/*
1910 * HUBP_SOFT_RESET enum
1911 */
1912
1913typedef enum HUBP_SOFT_RESET {
1914HUBP_SOFT_RESET_ON = 0x00000000,
1915HUBP_SOFT_RESET_OFF = 0x00000001,
1916} HUBP_SOFT_RESET;
1917
1918/*
1919 * HUBP_TTU_DISABLE enum
1920 */
1921
1922typedef enum HUBP_TTU_DISABLE {
1923HUBP_TTU_ENABLED = 0x00000000,
1924HUBP_TTU_DISABLED = 0x00000001,
1925} HUBP_TTU_DISABLE;
1926
1927/*
1928 * HUBP_VREADY_AT_OR_AFTER_VSYNC enum
1929 */
1930
1931typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC {
1932VREADY_BEFORE_VSYNC = 0x00000000,
1933VREADY_AT_OR_AFTER_VSYNC = 0x00000001,
1934} HUBP_VREADY_AT_OR_AFTER_VSYNC;
1935
1936/*
1937 * HUBP_VTG_SEL enum
1938 */
1939
1940typedef enum HUBP_VTG_SEL {
1941VTG_SEL_0 = 0x00000000,
1942VTG_SEL_1 = 0x00000001,
1943VTG_SEL_2 = 0x00000002,
1944VTG_SEL_3 = 0x00000003,
1945VTG_SEL_4 = 0x00000004,
1946VTG_SEL_5 = 0x00000005,
1947} HUBP_VTG_SEL;
1948
1949/*
1950 * H_MIRROR_EN enum
1951 */
1952
1953typedef enum H_MIRROR_EN {
1954HW_MIRRORING_DISABLE = 0x00000000,
1955HW_MIRRORING_ENABLE = 0x00000001,
1956} H_MIRROR_EN;
1957
1958/*
1959 * LEGACY_PIPE_INTERLEAVE enum
1960 */
1961
1962typedef enum LEGACY_PIPE_INTERLEAVE {
1963LEGACY_PIPE_INTERLEAVE_256B = 0x00000000,
1964LEGACY_PIPE_INTERLEAVE_512B = 0x00000001,
1965} LEGACY_PIPE_INTERLEAVE;
1966
1967/*
1968 * META_CHUNK_SIZE enum
1969 */
1970
1971typedef enum META_CHUNK_SIZE {
1972META_CHUNK_SIZE_1KB = 0x00000000,
1973META_CHUNK_SIZE_2KB = 0x00000001,
1974META_CHUNK_SIZE_4KB = 0x00000002,
1975META_CHUNK_SIZE_8KB = 0x00000003,
1976} META_CHUNK_SIZE;
1977
1978/*
1979 * META_LINEAR enum
1980 */
1981
1982typedef enum META_LINEAR {
1983META_SURF_TILED = 0x00000000,
1984META_SURF_LINEAR = 0x00000001,
1985} META_LINEAR;
1986
1987/*
1988 * MIN_CHUNK_SIZE enum
1989 */
1990
1991typedef enum MIN_CHUNK_SIZE {
1992NO_MIN_CHUNK_SIZE = 0x00000000,
1993MIN_CHUNK_SIZE_256B = 0x00000001,
1994MIN_CHUNK_SIZE_512B = 0x00000002,
1995MIN_CHUNK_SIZE_1024B = 0x00000003,
1996} MIN_CHUNK_SIZE;
1997
1998/*
1999 * MIN_META_CHUNK_SIZE enum
2000 */
2001
2002typedef enum MIN_META_CHUNK_SIZE {
2003NO_MIN_META_CHUNK_SIZE = 0x00000000,
2004MIN_META_CHUNK_SIZE_64B = 0x00000001,
2005MIN_META_CHUNK_SIZE_128B = 0x00000002,
2006MIN_META_CHUNK_SIZE_256B = 0x00000003,
2007} MIN_META_CHUNK_SIZE;
2008
2009/*
2010 * PIPE_ALIGNED enum
2011 */
2012
2013typedef enum PIPE_ALIGNED {
2014PIPE_UNALIGNED_SURF = 0x00000000,
2015PIPE_ALIGNED_SURF = 0x00000001,
2016} PIPE_ALIGNED;
2017
2018/*
2019 * PTE_BUFFER_MODE enum
2020 */
2021
2022typedef enum PTE_BUFFER_MODE {
2023PTE_BUFFER_MODE_0 = 0x00000000,
2024PTE_BUFFER_MODE_1 = 0x00000001,
2025} PTE_BUFFER_MODE;
2026
2027/*
2028 * PTE_ROW_HEIGHT_LINEAR enum
2029 */
2030
2031typedef enum PTE_ROW_HEIGHT_LINEAR {
2032PTE_ROW_HEIGHT_LINEAR_8L = 0x00000000,
2033PTE_ROW_HEIGHT_LINEAR_16L = 0x00000001,
2034PTE_ROW_HEIGHT_LINEAR_32L = 0x00000002,
2035PTE_ROW_HEIGHT_LINEAR_64L = 0x00000003,
2036PTE_ROW_HEIGHT_LINEAR_128L = 0x00000004,
2037PTE_ROW_HEIGHT_LINEAR_256L = 0x00000005,
2038PTE_ROW_HEIGHT_LINEAR_512L = 0x00000006,
2039PTE_ROW_HEIGHT_LINEAR_1024L = 0x00000007,
2040} PTE_ROW_HEIGHT_LINEAR;
2041
2042/*
2043 * ROTATION_ANGLE enum
2044 */
2045
2046typedef enum ROTATION_ANGLE {
2047ROTATE_0_DEGREES = 0x00000000,
2048ROTATE_90_DEGREES = 0x00000001,
2049ROTATE_180_DEGREES = 0x00000002,
2050ROTATE_270_DEGREES = 0x00000003,
2051} ROTATION_ANGLE;
2052
2053/*
2054 * SWATH_HEIGHT enum
2055 */
2056
2057typedef enum SWATH_HEIGHT {
2058SWATH_HEIGHT_1L = 0x00000000,
2059SWATH_HEIGHT_2L = 0x00000001,
2060SWATH_HEIGHT_4L = 0x00000002,
2061SWATH_HEIGHT_8L = 0x00000003,
2062SWATH_HEIGHT_16L = 0x00000004,
2063} SWATH_HEIGHT;
2064
2065/*
2066 * VMPG_SIZE enum
2067 */
2068
2069typedef enum VMPG_SIZE {
2070VMPG_SIZE_4KB = 0x00000000,
2071VMPG_SIZE_64KB = 0x00000001,
2072} VMPG_SIZE;
2073
2074/*
2075 * VM_GROUP_SIZE enum
2076 */
2077
2078typedef enum VM_GROUP_SIZE {
2079VM_GROUP_SIZE_64B = 0x00000000,
2080VM_GROUP_SIZE_128B = 0x00000001,
2081VM_GROUP_SIZE_256B = 0x00000002,
2082VM_GROUP_SIZE_512B = 0x00000003,
2083VM_GROUP_SIZE_1024B = 0x00000004,
2084VM_GROUP_SIZE_2048B = 0x00000005,
2085} VM_GROUP_SIZE;
2086
2087/*******************************************************
2088 * HUBPREQ Enums
2089 *******************************************************/
2090
2091/*
2092 * DFQ_MIN_FREE_ENTRIES enum
2093 */
2094
2095typedef enum DFQ_MIN_FREE_ENTRIES {
2096DFQ_MIN_FREE_ENTRIES_0 = 0x00000000,
2097DFQ_MIN_FREE_ENTRIES_1 = 0x00000001,
2098DFQ_MIN_FREE_ENTRIES_2 = 0x00000002,
2099DFQ_MIN_FREE_ENTRIES_3 = 0x00000003,
2100DFQ_MIN_FREE_ENTRIES_4 = 0x00000004,
2101DFQ_MIN_FREE_ENTRIES_5 = 0x00000005,
2102DFQ_MIN_FREE_ENTRIES_6 = 0x00000006,
2103DFQ_MIN_FREE_ENTRIES_7 = 0x00000007,
2104} DFQ_MIN_FREE_ENTRIES;
2105
2106/*
2107 * DFQ_NUM_ENTRIES enum
2108 */
2109
2110typedef enum DFQ_NUM_ENTRIES {
2111DFQ_NUM_ENTRIES_0 = 0x00000000,
2112DFQ_NUM_ENTRIES_1 = 0x00000001,
2113DFQ_NUM_ENTRIES_2 = 0x00000002,
2114DFQ_NUM_ENTRIES_3 = 0x00000003,
2115DFQ_NUM_ENTRIES_4 = 0x00000004,
2116DFQ_NUM_ENTRIES_5 = 0x00000005,
2117DFQ_NUM_ENTRIES_6 = 0x00000006,
2118DFQ_NUM_ENTRIES_7 = 0x00000007,
2119DFQ_NUM_ENTRIES_8 = 0x00000008,
2120} DFQ_NUM_ENTRIES;
2121
2122/*
2123 * DFQ_SIZE enum
2124 */
2125
2126typedef enum DFQ_SIZE {
2127DFQ_SIZE_0 = 0x00000000,
2128DFQ_SIZE_1 = 0x00000001,
2129DFQ_SIZE_2 = 0x00000002,
2130DFQ_SIZE_3 = 0x00000003,
2131DFQ_SIZE_4 = 0x00000004,
2132DFQ_SIZE_5 = 0x00000005,
2133DFQ_SIZE_6 = 0x00000006,
2134DFQ_SIZE_7 = 0x00000007,
2135} DFQ_SIZE;
2136
2137/*
2138 * DMDATA_VM_DONE enum
2139 */
2140
2141typedef enum DMDATA_VM_DONE {
2142DMDATA_VM_IS_NOT_DONE = 0x00000000,
2143DMDATA_VM_IS_DONE = 0x00000001,
2144} DMDATA_VM_DONE;
2145
2146/*
2147 * EXPANSION_MODE enum
2148 */
2149
2150typedef enum EXPANSION_MODE {
2151EXPANSION_MODE_ZERO = 0x00000000,
2152EXPANSION_MODE_CONSERVATIVE = 0x00000001,
2153EXPANSION_MODE_OPTIMAL = 0x00000002,
2154} EXPANSION_MODE;
2155
2156/*
2157 * FLIP_RATE enum
2158 */
2159
2160typedef enum FLIP_RATE {
2161FLIP_RATE_0 = 0x00000000,
2162FLIP_RATE_1 = 0x00000001,
2163FLIP_RATE_2 = 0x00000002,
2164FLIP_RATE_3 = 0x00000003,
2165FLIP_RATE_4 = 0x00000004,
2166FLIP_RATE_5 = 0x00000005,
2167FLIP_RATE_6 = 0x00000006,
2168FLIP_RATE_7 = 0x00000007,
2169} FLIP_RATE;
2170
2171/*
2172 * INT_MASK enum
2173 */
2174
2175typedef enum INT_MASK {
2176INT_DISABLED = 0x00000000,
2177INT_ENABLED = 0x00000001,
2178} INT_MASK;
2179
2180/*
2181 * PIPE_IN_FLUSH_URGENT enum
2182 */
2183
2184typedef enum PIPE_IN_FLUSH_URGENT {
2185PIPE_IN_FLUSH_URGENT_ENABLE = 0x00000000,
2186PIPE_IN_FLUSH_URGENT_DISABLE = 0x00000001,
2187} PIPE_IN_FLUSH_URGENT;
2188
2189/*
2190 * PRQ_MRQ_FLUSH_URGENT enum
2191 */
2192
2193typedef enum PRQ_MRQ_FLUSH_URGENT {
2194PRQ_MRQ_FLUSH_URGENT_ENABLE = 0x00000000,
2195PRQ_MRQ_FLUSH_URGENT_DISABLE = 0x00000001,
2196} PRQ_MRQ_FLUSH_URGENT;
2197
2198/*
2199 * ROW_TTU_MODE enum
2200 */
2201
2202typedef enum ROW_TTU_MODE {
2203END_OF_ROW_MODE = 0x00000000,
2204WATERMARK_MODE = 0x00000001,
2205} ROW_TTU_MODE;
2206
2207/*
2208 * SURFACE_DCC enum
2209 */
2210
2211typedef enum SURFACE_DCC {
2212SURFACE_IS_NOT_DCC = 0x00000000,
2213SURFACE_IS_DCC = 0x00000001,
2214} SURFACE_DCC;
2215
2216/*
2217 * SURFACE_DCC_IND_128B enum
2218 */
2219
2220typedef enum SURFACE_DCC_IND_128B {
2221SURFACE_DCC_IS_NOT_IND_128B = 0x00000000,
2222SURFACE_DCC_IS_IND_128B = 0x00000001,
2223} SURFACE_DCC_IND_128B;
2224
2225/*
2226 * SURFACE_DCC_IND_64B enum
2227 */
2228
2229typedef enum SURFACE_DCC_IND_64B {
2230SURFACE_DCC_IS_NOT_IND_64B = 0x00000000,
2231SURFACE_DCC_IS_IND_64B = 0x00000001,
2232} SURFACE_DCC_IND_64B;
2233
2234/*
2235 * SURFACE_DCC_IND_BLK enum
2236 */
2237
2238typedef enum SURFACE_DCC_IND_BLK {
2239SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0x00000000,
2240SURFACE_DCC_BLOCK_IS_IND_64B = 0x00000001,
2241SURFACE_DCC_BLOCK_IS_IND_128B = 0x00000002,
2242SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 0x00000003,
2243} SURFACE_DCC_IND_BLK;
2244
2245/*
2246 * SURFACE_FLIP_AWAY_INT_TYPE enum
2247 */
2248
2249typedef enum SURFACE_FLIP_AWAY_INT_TYPE {
2250SURFACE_FLIP_AWAY_INT_LEVEL = 0x00000000,
2251SURFACE_FLIP_AWAY_INT_PULSE = 0x00000001,
2252} SURFACE_FLIP_AWAY_INT_TYPE;
2253
2254/*
2255 * SURFACE_FLIP_EXEC_DEBUG_MODE enum
2256 */
2257
2258typedef enum SURFACE_FLIP_EXEC_DEBUG_MODE {
2259SURFACE_FLIP_EXEC_NORMAL_MODE = 0x00000000,
2260SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 0x00000001,
2261} SURFACE_FLIP_EXEC_DEBUG_MODE;
2262
2263/*
2264 * SURFACE_FLIP_INT_TYPE enum
2265 */
2266
2267typedef enum SURFACE_FLIP_INT_TYPE {
2268SURFACE_FLIP_INT_LEVEL = 0x00000000,
2269SURFACE_FLIP_INT_PULSE = 0x00000001,
2270} SURFACE_FLIP_INT_TYPE;
2271
2272/*
2273 * SURFACE_FLIP_IN_STEREOSYNC enum
2274 */
2275
2276typedef enum SURFACE_FLIP_IN_STEREOSYNC {
2277SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0x00000000,
2278SURFACE_FLIP_IN_STEREOSYNC_MODE = 0x00000001,
2279} SURFACE_FLIP_IN_STEREOSYNC;
2280
2281/*
2282 * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum
2283 */
2284
2285typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC {
2286FLIP_ANY_FRAME = 0x00000000,
2287FLIP_LEFT_EYE = 0x00000001,
2288FLIP_RIGHT_EYE = 0x00000002,
2289SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 0x00000003,
2290} SURFACE_FLIP_MODE_FOR_STEREOSYNC;
2291
2292/*
2293 * SURFACE_FLIP_STEREO_SELECT_DISABLE enum
2294 */
2295
2296typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE {
2297SURFACE_FLIP_STEREO_SELECT_ENABLED = 0x00000000,
2298SURFACE_FLIP_STEREO_SELECT_DISABLED = 0x00000001,
2299} SURFACE_FLIP_STEREO_SELECT_DISABLE;
2300
2301/*
2302 * SURFACE_FLIP_STEREO_SELECT_POLARITY enum
2303 */
2304
2305typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY {
2306SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0x00000000,
2307SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 0x00000001,
2308} SURFACE_FLIP_STEREO_SELECT_POLARITY;
2309
2310/*
2311 * SURFACE_FLIP_TYPE enum
2312 */
2313
2314typedef enum SURFACE_FLIP_TYPE {
2315SURFACE_V_FLIP = 0x00000000,
2316SURFACE_I_FLIP = 0x00000001,
2317} SURFACE_FLIP_TYPE;
2318
2319/*
2320 * SURFACE_FLIP_VUPDATE_SKIP_NUM enum
2321 */
2322
2323typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM {
2324SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0x00000000,
2325SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 0x00000001,
2326SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 0x00000002,
2327SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 0x00000003,
2328SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 0x00000004,
2329SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 0x00000005,
2330SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 0x00000006,
2331SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 0x00000007,
2332SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 0x00000008,
2333SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 0x00000009,
2334SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 0x0000000a,
2335SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 0x0000000b,
2336SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 0x0000000c,
2337SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 0x0000000d,
2338SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 0x0000000e,
2339SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 0x0000000f,
2340} SURFACE_FLIP_VUPDATE_SKIP_NUM;
2341
2342/*
2343 * SURFACE_INUSE_RAED_NO_LATCH enum
2344 */
2345
2346typedef enum SURFACE_INUSE_RAED_NO_LATCH {
2347SURFACE_INUSE_IS_LATCHED = 0x00000000,
2348SURFACE_INUSE_IS_NOT_LATCHED = 0x00000001,
2349} SURFACE_INUSE_RAED_NO_LATCH;
2350
2351/*
2352 * SURFACE_TMZ enum
2353 */
2354
2355typedef enum SURFACE_TMZ {
2356SURFACE_IS_NOT_TMZ = 0x00000000,
2357SURFACE_IS_TMZ = 0x00000001,
2358} SURFACE_TMZ;
2359
2360/*
2361 * SURFACE_UPDATE_LOCK enum
2362 */
2363
2364typedef enum SURFACE_UPDATE_LOCK {
2365SURFACE_UPDATE_IS_UNLOCKED = 0x00000000,
2366SURFACE_UPDATE_IS_LOCKED = 0x00000001,
2367} SURFACE_UPDATE_LOCK;
2368
2369/*******************************************************
2370 * HUBPRET Enums
2371 *******************************************************/
2372
2373/*
2374 * CROSSBAR_FOR_ALPHA enum
2375 */
2376
2377typedef enum CROSSBAR_FOR_ALPHA {
2378ALPHA_DATA_ONTO_ALPHA_PORT = 0x00000000,
2379Y_G_DATA_ONTO_ALPHA_PORT = 0x00000001,
2380CB_B_DATA_ONTO_ALPHA_PORT = 0x00000002,
2381CR_R_DATA_ONTO_ALPHA_PORT = 0x00000003,
2382} CROSSBAR_FOR_ALPHA;
2383
2384/*
2385 * CROSSBAR_FOR_CB_B enum
2386 */
2387
2388typedef enum CROSSBAR_FOR_CB_B {
2389ALPHA_DATA_ONTO_CB_B_PORT = 0x00000000,
2390Y_G_DATA_ONTO_CB_B_PORT = 0x00000001,
2391CB_B_DATA_ONTO_CB_B_PORT = 0x00000002,
2392CR_R_DATA_ONTO_CB_B_PORT = 0x00000003,
2393} CROSSBAR_FOR_CB_B;
2394
2395/*
2396 * CROSSBAR_FOR_CR_R enum
2397 */
2398
2399typedef enum CROSSBAR_FOR_CR_R {
2400ALPHA_DATA_ONTO_CR_R_PORT = 0x00000000,
2401Y_G_DATA_ONTO_CR_R_PORT = 0x00000001,
2402CB_B_DATA_ONTO_CR_R_PORT = 0x00000002,
2403CR_R_DATA_ONTO_CR_R_PORT = 0x00000003,
2404} CROSSBAR_FOR_CR_R;
2405
2406/*
2407 * CROSSBAR_FOR_Y_G enum
2408 */
2409
2410typedef enum CROSSBAR_FOR_Y_G {
2411ALPHA_DATA_ONTO_Y_G_PORT = 0x00000000,
2412Y_G_DATA_ONTO_Y_G_PORT = 0x00000001,
2413CB_B_DATA_ONTO_Y_G_PORT = 0x00000002,
2414CR_R_DATA_ONTO_Y_G_PORT = 0x00000003,
2415} CROSSBAR_FOR_Y_G;
2416
2417/*
2418 * DETILE_BUFFER_PACKER_ENABLE enum
2419 */
2420
2421typedef enum DETILE_BUFFER_PACKER_ENABLE {
2422DETILE_BUFFER_PACKER_IS_DISABLE = 0x00000000,
2423DETILE_BUFFER_PACKER_IS_ENABLE = 0x00000001,
2424} DETILE_BUFFER_PACKER_ENABLE;
2425
2426/*
2427 * MEM_PWR_DIS_MODE enum
2428 */
2429
2430typedef enum MEM_PWR_DIS_MODE {
2431MEM_POWER_DIS_MODE_ENABLE = 0x00000000,
2432MEM_POWER_DIS_MODE_DISABLE = 0x00000001,
2433} MEM_PWR_DIS_MODE;
2434
2435/*
2436 * MEM_PWR_FORCE_MODE enum
2437 */
2438
2439typedef enum MEM_PWR_FORCE_MODE {
2440MEM_POWER_FORCE_MODE_OFF = 0x00000000,
2441MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 0x00000001,
2442MEM_POWER_FORCE_MODE_DEEP_SLEEP = 0x00000002,
2443MEM_POWER_FORCE_MODE_SHUT_DOWN = 0x00000003,
2444} MEM_PWR_FORCE_MODE;
2445
2446/*
2447 * MEM_PWR_STATUS enum
2448 */
2449
2450typedef enum MEM_PWR_STATUS {
2451MEM_POWER_STATUS_ON = 0x00000000,
2452MEM_POWER_STATUS_LIGHT_SLEEP = 0x00000001,
2453MEM_POWER_STATUS_DEEP_SLEEP = 0x00000002,
2454MEM_POWER_STATUS_SHUT_DOWN = 0x00000003,
2455} MEM_PWR_STATUS;
2456
2457/*
2458 * PIPE_INT_MASK_MODE enum
2459 */
2460
2461typedef enum PIPE_INT_MASK_MODE {
2462PIPE_INT_MASK_MODE_DISABLE = 0x00000000,
2463PIPE_INT_MASK_MODE_ENABLE = 0x00000001,
2464} PIPE_INT_MASK_MODE;
2465
2466/*
2467 * PIPE_INT_TYPE_MODE enum
2468 */
2469
2470typedef enum PIPE_INT_TYPE_MODE {
2471PIPE_INT_TYPE_MODE_DISABLE = 0x00000000,
2472PIPE_INT_TYPE_MODE_ENABLE = 0x00000001,
2473} PIPE_INT_TYPE_MODE;
2474
2475/*
2476 * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum
2477 */
2478
2479typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE {
2480PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
2481PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
2482} PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE;
2483
2484/*******************************************************
2485 * CURSOR Enums
2486 *******************************************************/
2487
2488/*
2489 * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum
2490 */
2491
2492typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE {
2493CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
2494CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
2495CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002,
2496} CROB_MEM_PWR_LIGHT_SLEEP_MODE;
2497
2498/*
2499 * CURSOR_2X_MAGNIFY enum
2500 */
2501
2502typedef enum CURSOR_2X_MAGNIFY {
2503CURSOR_2X_MAGNIFY_IS_DISABLE = 0x00000000,
2504CURSOR_2X_MAGNIFY_IS_ENABLE = 0x00000001,
2505} CURSOR_2X_MAGNIFY;
2506
2507/*
2508 * CURSOR_ENABLE enum
2509 */
2510
2511typedef enum CURSOR_ENABLE {
2512CURSOR_IS_DISABLE = 0x00000000,
2513CURSOR_IS_ENABLE = 0x00000001,
2514} CURSOR_ENABLE;
2515
2516/*
2517 * CURSOR_LINES_PER_CHUNK enum
2518 */
2519
2520typedef enum CURSOR_LINES_PER_CHUNK {
2521CURSOR_LINE_PER_CHUNK_1 = 0x00000000,
2522CURSOR_LINE_PER_CHUNK_2 = 0x00000001,
2523CURSOR_LINE_PER_CHUNK_4 = 0x00000002,
2524CURSOR_LINE_PER_CHUNK_8 = 0x00000003,
2525CURSOR_LINE_PER_CHUNK_16 = 0x00000004,
2526} CURSOR_LINES_PER_CHUNK;
2527
2528/*
2529 * CURSOR_MODE enum
2530 */
2531
2532typedef enum CURSOR_MODE {
2533CURSOR_MONO_2BIT = 0x00000000,
2534CURSOR_COLOR_24BIT_1BIT_AND = 0x00000001,
2535CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002,
2536CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003,
2537CURSOR_COLOR_64BIT_FP_PREMULT = 0x00000004,
2538CURSOR_COLOR_64BIT_FP_UNPREMULT = 0x00000005,
2539} CURSOR_MODE;
2540
2541/*
2542 * CURSOR_PERFMON_LATENCY_MEASURE_EN enum
2543 */
2544
2545typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN {
2546CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0x00000000,
2547CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 0x00000001,
2548} CURSOR_PERFMON_LATENCY_MEASURE_EN;
2549
2550/*
2551 * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum
2552 */
2553
2554typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL {
2555CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0x00000000,
2556CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 0x00000001,
2557} CURSOR_PERFMON_LATENCY_MEASURE_SEL;
2558
2559/*
2560 * CURSOR_PITCH enum
2561 */
2562
2563typedef enum CURSOR_PITCH {
2564CURSOR_PITCH_64_PIXELS = 0x00000000,
2565CURSOR_PITCH_128_PIXELS = 0x00000001,
2566CURSOR_PITCH_256_PIXELS = 0x00000002,
2567} CURSOR_PITCH;
2568
2569/*
2570 * CURSOR_REQ_MODE enum
2571 */
2572
2573typedef enum CURSOR_REQ_MODE {
2574CURSOR_REQUEST_NORMALLY = 0x00000000,
2575CURSOR_REQUEST_EARLY = 0x00000001,
2576} CURSOR_REQ_MODE;
2577
2578/*
2579 * CURSOR_SNOOP enum
2580 */
2581
2582typedef enum CURSOR_SNOOP {
2583CURSOR_IS_NOT_SNOOP = 0x00000000,
2584CURSOR_IS_SNOOP = 0x00000001,
2585} CURSOR_SNOOP;
2586
2587/*
2588 * CURSOR_STEREO_EN enum
2589 */
2590
2591typedef enum CURSOR_STEREO_EN {
2592CURSOR_STEREO_IS_DISABLED = 0x00000000,
2593CURSOR_STEREO_IS_ENABLED = 0x00000001,
2594} CURSOR_STEREO_EN;
2595
2596/*
2597 * CURSOR_SURFACE_TMZ enum
2598 */
2599
2600typedef enum CURSOR_SURFACE_TMZ {
2601CURSOR_SURFACE_IS_NOT_TMZ = 0x00000000,
2602CURSOR_SURFACE_IS_TMZ = 0x00000001,
2603} CURSOR_SURFACE_TMZ;
2604
2605/*
2606 * CURSOR_SYSTEM enum
2607 */
2608
2609typedef enum CURSOR_SYSTEM {
2610CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0x00000000,
2611CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 0x00000001,
2612} CURSOR_SYSTEM;
2613
2614/*
2615 * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum
2616 */
2617
2618typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS {
2619CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0x00000000,
2620CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 0x00000001,
2621} CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS;
2622
2623/*
2624 * DMDATA_DONE enum
2625 */
2626
2627typedef enum DMDATA_DONE {
2628DMDATA_NOT_SENT_TO_DIG = 0x00000000,
2629DMDATA_SENT_TO_DIG = 0x00000001,
2630} DMDATA_DONE;
2631
2632/*
2633 * DMDATA_MODE enum
2634 */
2635
2636typedef enum DMDATA_MODE {
2637DMDATA_SOFTWARE_UPDATE_MODE = 0x00000000,
2638DMDATA_HARDWARE_UPDATE_MODE = 0x00000001,
2639} DMDATA_MODE;
2640
2641/*
2642 * DMDATA_QOS_MODE enum
2643 */
2644
2645typedef enum DMDATA_QOS_MODE {
2646DMDATA_QOS_LEVEL_FROM_TTU = 0x00000000,
2647DMDATA_QOS_LEVEL_FROM_SOFTWARE = 0x00000001,
2648} DMDATA_QOS_MODE;
2649
2650/*
2651 * DMDATA_REPEAT enum
2652 */
2653
2654typedef enum DMDATA_REPEAT {
2655DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0x00000000,
2656DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 0x00000001,
2657} DMDATA_REPEAT;
2658
2659/*
2660 * DMDATA_UNDERFLOW enum
2661 */
2662
2663typedef enum DMDATA_UNDERFLOW {
2664DMDATA_NOT_UNDERFLOW = 0x00000000,
2665DMDATA_UNDERFLOWED = 0x00000001,
2666} DMDATA_UNDERFLOW;
2667
2668/*
2669 * DMDATA_UNDERFLOW_CLEAR enum
2670 */
2671
2672typedef enum DMDATA_UNDERFLOW_CLEAR {
2673DMDATA_DONT_CLEAR = 0x00000000,
2674DMDATA_CLEAR_UNDERFLOW_STATUS = 0x00000001,
2675} DMDATA_UNDERFLOW_CLEAR;
2676
2677/*
2678 * DMDATA_UPDATED enum
2679 */
2680
2681typedef enum DMDATA_UPDATED {
2682DMDATA_NOT_UPDATED = 0x00000000,
2683DMDATA_WAS_UPDATED = 0x00000001,
2684} DMDATA_UPDATED;
2685
2686/*
2687 * HUBP_3DLUT_ADDRESSING_MODE enum
2688 */
2689
2690typedef enum HUBP_3DLUT_ADDRESSING_MODE {
2691HUBP_3DLUT_SW_LINEAR = 0x00000000,
2692HUBP_3DLUT_SIMPLE_LINEAR = 0x00000001,
2693} HUBP_3DLUT_ADDRESSING_MODE;
2694
2695/*******************************************************
2696 * HUBBUB_SDPIF Enums
2697 *******************************************************/
2698
2699/*
2700 * RESPONSE_STATUS enum
2701 */
2702
2703typedef enum RESPONSE_STATUS {
2704OKAY = 0x00000000,
2705EXOKAY = 0x00000001,
2706SLVERR = 0x00000002,
2707DECERR = 0x00000003,
2708EARLY = 0x00000004,
2709OKAY_NODATA = 0x00000005,
2710PROTVIOL = 0x00000006,
2711TRANSERR = 0x00000007,
2712CMPTO = 0x00000008,
2713CRS = 0x0000000c,
2714} RESPONSE_STATUS;
2715
2716/*******************************************************
2717 * HUBBUB_RET_PATH Enums
2718 *******************************************************/
2719
2720/*
2721 * DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE enum
2722 */
2723
2724typedef enum DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE {
2725DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
2726DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
2727DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002,
2728} DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE;
2729
2730/*
2731 * DCHUBBUB_MEM_PWR_DIS_MODE enum
2732 */
2733
2734typedef enum DCHUBBUB_MEM_PWR_DIS_MODE {
2735DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0x00000000,
2736DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 0x00000001,
2737} DCHUBBUB_MEM_PWR_DIS_MODE;
2738
2739/*
2740 * DCHUBBUB_MEM_PWR_MODE enum
2741 */
2742
2743typedef enum DCHUBBUB_MEM_PWR_MODE {
2744DCHUBBUB_MEM_POWER_MODE_OFF = 0x00000000,
2745DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 0x00000001,
2746DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 0x00000002,
2747DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 0x00000003,
2748} DCHUBBUB_MEM_PWR_MODE;
2749
2750/*******************************************************
2751 * MPC_CFG Enums
2752 *******************************************************/
2753
2754/*
2755 * MPC_CFG_3DLUT_FL_FORMAT enum
2756 */
2757
2758typedef enum MPC_CFG_3DLUT_FL_FORMAT {
2759MPC_CFG_3DLUT_FL_FORMAT_0 = 0x00000000,
2760MPC_CFG_3DLUT_FL_FORMAT_1 = 0x00000001,
2761MPC_CFG_3DLUT_FL_FORMAT_2 = 0x00000002,
2762} MPC_CFG_3DLUT_FL_FORMAT;
2763
2764/*
2765 * MPC_CFG_3DLUT_FL_MODE enum
2766 */
2767
2768typedef enum MPC_CFG_3DLUT_FL_MODE {
2769MPC_CFG_3DLUT_FL_MODE_0 = 0x00000000,
2770MPC_CFG_3DLUT_FL_MODE_1 = 0x00000001,
2771MPC_CFG_3DLUT_FL_MODE_2 = 0x00000002,
2772MPC_CFG_3DLUT_FL_MODE_3 = 0x00000003,
2773} MPC_CFG_3DLUT_FL_MODE;
2774
2775/*
2776 * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum
2777 */
2778
2779typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET {
2780MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2781MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2782} MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET;
2783
2784/*
2785 * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum
2786 */
2787
2788typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET {
2789MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2790MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2791} MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET;
2792
2793/*
2794 * MPC_CFG_ADR_VUPDATE_LOCK_SET enum
2795 */
2796
2797typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET {
2798MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2799MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2800} MPC_CFG_ADR_VUPDATE_LOCK_SET;
2801
2802/*
2803 * MPC_CFG_CFG_VUPDATE_LOCK_SET enum
2804 */
2805
2806typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET {
2807MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2808MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2809} MPC_CFG_CFG_VUPDATE_LOCK_SET;
2810
2811/*
2812 * MPC_CFG_CUR_VUPDATE_LOCK_SET enum
2813 */
2814
2815typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET {
2816MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2817MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2818} MPC_CFG_CUR_VUPDATE_LOCK_SET;
2819
2820/*
2821 * MPC_CFG_MPC_TEST_CLK_SEL enum
2822 */
2823
2824typedef enum MPC_CFG_MPC_TEST_CLK_SEL {
2825MPC_CFG_MPC_TEST_CLK_SEL_0 = 0x00000000,
2826MPC_CFG_MPC_TEST_CLK_SEL_1 = 0x00000001,
2827MPC_CFG_MPC_TEST_CLK_SEL_2 = 0x00000002,
2828MPC_CFG_MPC_TEST_CLK_SEL_3 = 0x00000003,
2829} MPC_CFG_MPC_TEST_CLK_SEL;
2830
2831/*
2832 * MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN enum
2833 */
2834
2835typedef enum MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN {
2836MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
2837MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
2838} MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN;
2839
2840/*
2841 * MPC_CRC_CALC_INTERLACE_MODE enum
2842 */
2843
2844typedef enum MPC_CRC_CALC_INTERLACE_MODE {
2845MPC_CRC_INTERLACE_MODE_TOP = 0x00000000,
2846MPC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
2847MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 0x00000002,
2848MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 0x00000003,
2849} MPC_CRC_CALC_INTERLACE_MODE;
2850
2851/*
2852 * MPC_CRC_CALC_MODE enum
2853 */
2854
2855typedef enum MPC_CRC_CALC_MODE {
2856MPC_CRC_ONE_SHOT_MODE = 0x00000000,
2857MPC_CRC_CONTINUOUS_MODE = 0x00000001,
2858} MPC_CRC_CALC_MODE;
2859
2860/*
2861 * MPC_CRC_CALC_STEREO_MODE enum
2862 */
2863
2864typedef enum MPC_CRC_CALC_STEREO_MODE {
2865MPC_CRC_STEREO_MODE_LEFT = 0x00000000,
2866MPC_CRC_STEREO_MODE_RIGHT = 0x00000001,
2867MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 0x00000002,
2868MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 0x00000003,
2869} MPC_CRC_CALC_STEREO_MODE;
2870
2871/*
2872 * MPC_CRC_SOURCE_SELECT enum
2873 */
2874
2875typedef enum MPC_CRC_SOURCE_SELECT {
2876MPC_CRC_SOURCE_SEL_DPP = 0x00000000,
2877MPC_CRC_SOURCE_SEL_OPP = 0x00000001,
2878MPC_CRC_SOURCE_SEL_DWB = 0x00000002,
2879MPC_CRC_SOURCE_SEL_OTHER = 0x00000003,
2880} MPC_CRC_SOURCE_SELECT;
2881
2882/*******************************************************
2883 * MPC_OCSC Enums
2884 *******************************************************/
2885
2886/*
2887 * MPC_OCSC_COEF_FORMAT enum
2888 */
2889
2890typedef enum MPC_OCSC_COEF_FORMAT {
2891MPC_OCSC_COEF_FORMAT_S2_13 = 0x00000000,
2892MPC_OCSC_COEF_FORMAT_S3_12 = 0x00000001,
2893} MPC_OCSC_COEF_FORMAT;
2894
2895/*
2896 * MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN enum
2897 */
2898
2899typedef enum MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN {
2900MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
2901MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
2902} MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN;
2903
2904/*
2905 * MPC_OUT_CSC_MODE enum
2906 */
2907
2908typedef enum MPC_OUT_CSC_MODE {
2909MPC_OUT_CSC_MODE_0 = 0x00000000,
2910MPC_OUT_CSC_MODE_1 = 0x00000001,
2911MPC_OUT_CSC_MODE_2 = 0x00000002,
2912MPC_OUT_CSC_MODE_RSV = 0x00000003,
2913} MPC_OUT_CSC_MODE;
2914
2915/*
2916 * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum
2917 */
2918
2919typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE {
2920MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0x00000000,
2921MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 0x00000001,
2922MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 0x00000002,
2923MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 0x00000003,
2924MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 0x00000004,
2925MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 0x00000005,
2926MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 0x00000006,
2927MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 0x00000007,
2928} MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE;
2929
2930/*
2931 * MPC_OUT_RATE_CONTROL_DISABLE_SET enum
2932 */
2933
2934typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET {
2935MPC_OUT_RATE_CONTROL_SET_ENABLE = 0x00000000,
2936MPC_OUT_RATE_CONTROL_SET_DISABLE = 0x00000001,
2937} MPC_OUT_RATE_CONTROL_DISABLE_SET;
2938
2939/*******************************************************
2940 * MPCC Enums
2941 *******************************************************/
2942
2943/*
2944 * MPCC_BG_COLOR_BPC enum
2945 */
2946
2947typedef enum MPCC_BG_COLOR_BPC {
2948MPCC_BG_COLOR_BPC_8bit = 0x00000000,
2949MPCC_BG_COLOR_BPC_9bit = 0x00000001,
2950MPCC_BG_COLOR_BPC_10bit = 0x00000002,
2951MPCC_BG_COLOR_BPC_11bit = 0x00000003,
2952MPCC_BG_COLOR_BPC_12bit = 0x00000004,
2953} MPCC_BG_COLOR_BPC;
2954
2955/*
2956 * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum
2957 */
2958
2959typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY {
2960MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000,
2961MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001,
2962} MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY;
2963
2964/*
2965 * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum
2966 */
2967
2968typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE {
2969MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0x00000000,
2970MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
2971MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 0x00000002,
2972MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 0x00000003,
2973} MPCC_CONTROL_MPCC_ALPHA_BLND_MODE;
2974
2975/*
2976 * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum
2977 */
2978
2979typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE {
2980MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0x00000000,
2981MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 0x00000001,
2982} MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE;
2983
2984/*
2985 * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum
2986 */
2987
2988typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE {
2989MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0x00000000,
2990MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 0x00000001,
2991} MPCC_CONTROL_MPCC_BOT_GAIN_MODE;
2992
2993/*
2994 * MPCC_CONTROL_MPCC_MODE enum
2995 */
2996
2997typedef enum MPCC_CONTROL_MPCC_MODE {
2998MPCC_CONTROL_MPCC_MODE_BYPASS = 0x00000000,
2999MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 0x00000001,
3000MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 0x00000002,
3001MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 0x00000003,
3002} MPCC_CONTROL_MPCC_MODE;
3003
3004/*
3005 * MPCC_SM_CONTROL_MPCC_SM_EN enum
3006 */
3007
3008typedef enum MPCC_SM_CONTROL_MPCC_SM_EN {
3009MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0x00000000,
3010MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 0x00000001,
3011} MPCC_SM_CONTROL_MPCC_SM_EN;
3012
3013/*
3014 * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum
3015 */
3016
3017typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT {
3018MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0x00000000,
3019MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 0x00000001,
3020} MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT;
3021
3022/*
3023 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum
3024 */
3025
3026typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL {
3027MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
3028MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
3029MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
3030MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
3031} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL;
3032
3033/*
3034 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum
3035 */
3036
3037typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL {
3038MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
3039MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
3040MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
3041MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
3042} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL;
3043
3044/*
3045 * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum
3046 */
3047
3048typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT {
3049MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0x00000000,
3050MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 0x00000001,
3051} MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT;
3052
3053/*
3054 * MPCC_SM_CONTROL_MPCC_SM_MODE enum
3055 */
3056
3057typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE {
3058MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0x00000000,
3059MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
3060MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
3061MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
3062} MPCC_SM_CONTROL_MPCC_SM_MODE;
3063
3064/*******************************************************
3065 * MPCC_OGAM Enums
3066 *******************************************************/
3067
3068/*
3069 * MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM enum
3070 */
3071
3072typedef enum MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM {
3073MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0x00000000,
3074MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 0x00000001,
3075} MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM;
3076
3077/*
3078 * MPCC_GAMUT_REMAP_MODE_ENUM enum
3079 */
3080
3081typedef enum MPCC_GAMUT_REMAP_MODE_ENUM {
3082MPCC_GAMUT_REMAP_MODE_0 = 0x00000000,
3083MPCC_GAMUT_REMAP_MODE_1 = 0x00000001,
3084MPCC_GAMUT_REMAP_MODE_2 = 0x00000002,
3085MPCC_GAMUT_REMAP_MODE_RSV = 0x00000003,
3086} MPCC_GAMUT_REMAP_MODE_ENUM;
3087
3088/*
3089 * MPCC_OGAM_LUT_2_CONFIG_ENUM enum
3090 */
3091
3092typedef enum MPCC_OGAM_LUT_2_CONFIG_ENUM {
3093MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0x00000000,
3094MPCC_OGAM_LUT_2CFG_MEMORY_A = 0x00000001,
3095MPCC_OGAM_LUT_2CFG_MEMORY_B = 0x00000002,
3096} MPCC_OGAM_LUT_2_CONFIG_ENUM;
3097
3098/*
3099 * MPCC_OGAM_LUT_CONFIG_MODE enum
3100 */
3101
3102typedef enum MPCC_OGAM_LUT_CONFIG_MODE {
3103MPCC_OGAM_DIFFERENT_RGB = 0x00000000,
3104MPCC_OGAM_ALL_USE_R = 0x00000001,
3105} MPCC_OGAM_LUT_CONFIG_MODE;
3106
3107/*
3108 * MPCC_OGAM_LUT_PWL_DISABLE_ENUM enum
3109 */
3110
3111typedef enum MPCC_OGAM_LUT_PWL_DISABLE_ENUM {
3112MPCC_OGAM_ENABLE_PWL = 0x00000000,
3113MPCC_OGAM_DISABLE_PWL = 0x00000001,
3114} MPCC_OGAM_LUT_PWL_DISABLE_ENUM;
3115
3116/*
3117 * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum
3118 */
3119
3120typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL {
3121MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0x00000000,
3122MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 0x00000001,
3123} MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL;
3124
3125/*
3126 * MPCC_OGAM_LUT_RAM_SEL enum
3127 */
3128
3129typedef enum MPCC_OGAM_LUT_RAM_SEL {
3130MPCC_OGAM_RAMA_ACCESS = 0x00000000,
3131MPCC_OGAM_RAMB_ACCESS = 0x00000001,
3132} MPCC_OGAM_LUT_RAM_SEL;
3133
3134/*
3135 * MPCC_OGAM_LUT_READ_COLOR_SEL enum
3136 */
3137
3138typedef enum MPCC_OGAM_LUT_READ_COLOR_SEL {
3139MPCC_OGAM_BLUE_LUT = 0x00000000,
3140MPCC_OGAM_GREEN_LUT = 0x00000001,
3141MPCC_OGAM_RED_LUT = 0x00000002,
3142} MPCC_OGAM_LUT_READ_COLOR_SEL;
3143
3144/*
3145 * MPCC_OGAM_LUT_READ_DBG enum
3146 */
3147
3148typedef enum MPCC_OGAM_LUT_READ_DBG {
3149MPCC_OGAM_DISABLE_DEBUG = 0x00000000,
3150MPCC_OGAM_ENABLE_DEBUG = 0x00000001,
3151} MPCC_OGAM_LUT_READ_DBG;
3152
3153/*
3154 * MPCC_OGAM_LUT_SEL_ENUM enum
3155 */
3156
3157typedef enum MPCC_OGAM_LUT_SEL_ENUM {
3158MPCC_OGAM_RAMA = 0x00000000,
3159MPCC_OGAM_RAMB = 0x00000001,
3160} MPCC_OGAM_LUT_SEL_ENUM;
3161
3162/*
3163 * MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM enum
3164 */
3165
3166typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM {
3167MPCC_OGAM_MODE_0 = 0x00000000,
3168MPCC_OGAM_MODE_RSV1 = 0x00000001,
3169MPCC_OGAM_MODE_2 = 0x00000002,
3170MPCC_OGAM_MODE_RSV = 0x00000003,
3171} MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM;
3172
3173/*
3174 * MPCC_OGAM_NUM_SEG enum
3175 */
3176
3177typedef enum MPCC_OGAM_NUM_SEG {
3178MPCC_OGAM_SEGMENTS_1 = 0x00000000,
3179MPCC_OGAM_SEGMENTS_2 = 0x00000001,
3180MPCC_OGAM_SEGMENTS_4 = 0x00000002,
3181MPCC_OGAM_SEGMENTS_8 = 0x00000003,
3182MPCC_OGAM_SEGMENTS_16 = 0x00000004,
3183MPCC_OGAM_SEGMENTS_32 = 0x00000005,
3184MPCC_OGAM_SEGMENTS_64 = 0x00000006,
3185MPCC_OGAM_SEGMENTS_128 = 0x00000007,
3186} MPCC_OGAM_NUM_SEG;
3187
3188/*
3189 * MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN enum
3190 */
3191
3192typedef enum MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN {
3193MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
3194MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
3195} MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN;
3196
3197/*******************************************************
3198 * MPCC_MCM Enums
3199 *******************************************************/
3200
3201/*
3202 * MPCC_MCM_3DLUT_30BIT_ENUM enum
3203 */
3204
3205typedef enum MPCC_MCM_3DLUT_30BIT_ENUM {
3206MPCC_MCM_3DLUT_36BIT = 0x00000000,
3207MPCC_MCM_3DLUT_30BIT = 0x00000001,
3208} MPCC_MCM_3DLUT_30BIT_ENUM;
3209
3210/*
3211 * MPCC_MCM_3DLUT_RAM_SEL enum
3212 */
3213
3214typedef enum MPCC_MCM_3DLUT_RAM_SEL {
3215MPCC_MCM_RAM0_ACCESS = 0x00000000,
3216MPCC_MCM_RAM1_ACCESS = 0x00000001,
3217MPCC_MCM_RAM2_ACCESS = 0x00000002,
3218MPCC_MCM_RAM3_ACCESS = 0x00000003,
3219} MPCC_MCM_3DLUT_RAM_SEL;
3220
3221/*
3222 * MPCC_MCM_3DLUT_SIZE_ENUM enum
3223 */
3224
3225typedef enum MPCC_MCM_3DLUT_SIZE_ENUM {
3226MPCC_MCM_3DLUT_17CUBE = 0x00000000,
3227MPCC_MCM_3DLUT_9CUBE = 0x00000001,
3228} MPCC_MCM_3DLUT_SIZE_ENUM;
3229
3230/*
3231 * MPCC_MCM_GAMMA_LUT_MODE_ENUM enum
3232 */
3233
3234typedef enum MPCC_MCM_GAMMA_LUT_MODE_ENUM {
3235MPCC_MCM_GAMMA_LUT_BYPASS = 0x00000000,
3236MPCC_MCM_GAMMA_LUT_RESERVED_1 = 0x00000001,
3237MPCC_MCM_GAMMA_LUT_RAM_LUT = 0x00000002,
3238MPCC_MCM_GAMMA_LUT_RESERVED_3 = 0x00000003,
3239} MPCC_MCM_GAMMA_LUT_MODE_ENUM;
3240
3241/*
3242 * MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM enum
3243 */
3244
3245typedef enum MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM {
3246MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0x00000000,
3247MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 0x00000001,
3248} MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM;
3249
3250/*
3251 * MPCC_MCM_GAMMA_LUT_SEL_ENUM enum
3252 */
3253
3254typedef enum MPCC_MCM_GAMMA_LUT_SEL_ENUM {
3255MPCC_MCM_GAMMA_LUT_RAMA = 0x00000000,
3256MPCC_MCM_GAMMA_LUT_RAMB = 0x00000001,
3257} MPCC_MCM_GAMMA_LUT_SEL_ENUM;
3258
3259/*
3260 * MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM enum
3261 */
3262
3263typedef enum MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM {
3264MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0x00000000,
3265MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_S3_12 = 0x00000001,
3266} MPCC_MCM_GAMUT_REMAP_COEF_FORMAT_ENUM;
3267
3268/*
3269 * MPCC_MCM_GAMUT_REMAP_MODE_ENUM enum
3270 */
3271
3272typedef enum MPCC_MCM_GAMUT_REMAP_MODE_ENUM {
3273MPCC_MCM_GAMUT_REMAP_MODE_0 = 0x00000000,
3274MPCC_MCM_GAMUT_REMAP_MODE_1 = 0x00000001,
3275MPCC_MCM_GAMUT_REMAP_MODE_2 = 0x00000002,
3276MPCC_MCM_GAMUT_REMAP_MODE_RSV = 0x00000003,
3277} MPCC_MCM_GAMUT_REMAP_MODE_ENUM;
3278
3279/*
3280 * MPCC_MCM_LUT_2_MODE_ENUM enum
3281 */
3282
3283typedef enum MPCC_MCM_LUT_2_MODE_ENUM {
3284MPCC_MCM_LUT_2_MODE_BYPASS = 0x00000000,
3285MPCC_MCM_LUT_2_MODE_RAMA_LUT = 0x00000001,
3286MPCC_MCM_LUT_2_MODE_RAMB_LUT = 0x00000002,
3287} MPCC_MCM_LUT_2_MODE_ENUM;
3288
3289/*
3290 * MPCC_MCM_LUT_CONFIG_MODE enum
3291 */
3292
3293typedef enum MPCC_MCM_LUT_CONFIG_MODE {
3294MPCC_MCM_LUT_DIFFERENT_RGB = 0x00000000,
3295MPCC_MCM_LUT_ALL_USE_R = 0x00000001,
3296} MPCC_MCM_LUT_CONFIG_MODE;
3297
3298/*
3299 * MPCC_MCM_LUT_NUM_SEG enum
3300 */
3301
3302typedef enum MPCC_MCM_LUT_NUM_SEG {
3303MPCC_MCM_LUT_SEGMENTS_1 = 0x00000000,
3304MPCC_MCM_LUT_SEGMENTS_2 = 0x00000001,
3305MPCC_MCM_LUT_SEGMENTS_4 = 0x00000002,
3306MPCC_MCM_LUT_SEGMENTS_8 = 0x00000003,
3307MPCC_MCM_LUT_SEGMENTS_16 = 0x00000004,
3308MPCC_MCM_LUT_SEGMENTS_32 = 0x00000005,
3309MPCC_MCM_LUT_SEGMENTS_64 = 0x00000006,
3310MPCC_MCM_LUT_SEGMENTS_128 = 0x00000007,
3311} MPCC_MCM_LUT_NUM_SEG;
3312
3313/*
3314 * MPCC_MCM_LUT_RAM_SEL enum
3315 */
3316
3317typedef enum MPCC_MCM_LUT_RAM_SEL {
3318MPCC_MCM_LUT_RAMA_ACCESS = 0x00000000,
3319MPCC_MCM_LUT_RAMB_ACCESS = 0x00000001,
3320} MPCC_MCM_LUT_RAM_SEL;
3321
3322/*
3323 * MPCC_MCM_LUT_READ_COLOR_SEL enum
3324 */
3325
3326typedef enum MPCC_MCM_LUT_READ_COLOR_SEL {
3327MPCC_MCM_LUT_BLUE_LUT = 0x00000000,
3328MPCC_MCM_LUT_GREEN_LUT = 0x00000001,
3329MPCC_MCM_LUT_RED_LUT = 0x00000002,
3330} MPCC_MCM_LUT_READ_COLOR_SEL;
3331
3332/*
3333 * MPCC_MCM_LUT_READ_DBG enum
3334 */
3335
3336typedef enum MPCC_MCM_LUT_READ_DBG {
3337MPCC_MCM_LUT_DISABLE_DEBUG = 0x00000000,
3338MPCC_MCM_LUT_ENABLE_DEBUG = 0x00000001,
3339} MPCC_MCM_LUT_READ_DBG;
3340
3341/*
3342 * MPCC_MCM_MEM_PWR_FORCE_ENUM enum
3343 */
3344
3345typedef enum MPCC_MCM_MEM_PWR_FORCE_ENUM {
3346MPCC_MCM_MEM_PWR_FORCE_DIS = 0x00000000,
3347MPCC_MCM_MEM_PWR_FORCE_LS = 0x00000001,
3348MPCC_MCM_MEM_PWR_FORCE_DS = 0x00000002,
3349MPCC_MCM_MEM_PWR_FORCE_SD = 0x00000003,
3350} MPCC_MCM_MEM_PWR_FORCE_ENUM;
3351
3352/*
3353 * MPCC_MCM_MEM_PWR_STATE_ENUM enum
3354 */
3355
3356typedef enum MPCC_MCM_MEM_PWR_STATE_ENUM {
3357MPCC_MCM_MEM_PWR_STATE_ON = 0x00000000,
3358MPCC_MCM_MEM_PWR_STATE_LS = 0x00000001,
3359MPCC_MCM_MEM_PWR_STATE_DS = 0x00000002,
3360MPCC_MCM_MEM_PWR_STATE_SD = 0x00000003,
3361} MPCC_MCM_MEM_PWR_STATE_ENUM;
3362
3363/*******************************************************
3364 * DPG Enums
3365 *******************************************************/
3366
3367/*
3368 * ENUM_DPG_BIT_DEPTH enum
3369 */
3370
3371typedef enum ENUM_DPG_BIT_DEPTH {
3372ENUM_DPG_BIT_DEPTH_6BPC = 0x00000000,
3373ENUM_DPG_BIT_DEPTH_8BPC = 0x00000001,
3374ENUM_DPG_BIT_DEPTH_10BPC = 0x00000002,
3375ENUM_DPG_BIT_DEPTH_12BPC = 0x00000003,
3376} ENUM_DPG_BIT_DEPTH;
3377
3378/*
3379 * ENUM_DPG_DYNAMIC_RANGE enum
3380 */
3381
3382typedef enum ENUM_DPG_DYNAMIC_RANGE {
3383ENUM_DPG_DYNAMIC_RANGE_VESA = 0x00000000,
3384ENUM_DPG_DYNAMIC_RANGE_CEA = 0x00000001,
3385} ENUM_DPG_DYNAMIC_RANGE;
3386
3387/*
3388 * ENUM_DPG_EN enum
3389 */
3390
3391typedef enum ENUM_DPG_EN {
3392ENUM_DPG_DISABLE = 0x00000000,
3393ENUM_DPG_ENABLE = 0x00000001,
3394} ENUM_DPG_EN;
3395
3396/*
3397 * ENUM_DPG_FIELD_POLARITY enum
3398 */
3399
3400typedef enum ENUM_DPG_FIELD_POLARITY {
3401ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000,
3402ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001,
3403} ENUM_DPG_FIELD_POLARITY;
3404
3405/*
3406 * ENUM_DPG_MODE enum
3407 */
3408
3409typedef enum ENUM_DPG_MODE {
3410ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0x00000000,
3411ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 0x00000001,
3412ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 0x00000002,
3413ENUM_DPG_MODE_VERTICAL_BAR = 0x00000003,
3414ENUM_DPG_MODE_HORIZONTAL_BAR = 0x00000004,
3415ENUM_DPG_MODE_RGB_SINGLE_RAMP = 0x00000005,
3416ENUM_DPG_MODE_RGB_DUAL_RAMP = 0x00000006,
3417ENUM_DPG_MODE_RGB_XR_BIAS = 0x00000007,
3418} ENUM_DPG_MODE;
3419
3420/*******************************************************
3421 * FMT Enums
3422 *******************************************************/
3423
3424/*
3425 * FMTMEM_PWR_DIS_CTRL enum
3426 */
3427
3428typedef enum FMTMEM_PWR_DIS_CTRL {
3429FMTMEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
3430FMTMEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
3431} FMTMEM_PWR_DIS_CTRL;
3432
3433/*
3434 * FMTMEM_PWR_FORCE_CTRL enum
3435 */
3436
3437typedef enum FMTMEM_PWR_FORCE_CTRL {
3438FMTMEM_NO_FORCE_REQUEST = 0x00000000,
3439FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
3440FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
3441FMTMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
3442} FMTMEM_PWR_FORCE_CTRL;
3443
3444/*
3445 * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3446 */
3447
3448typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3449FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000,
3450FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001,
3451FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002,
3452FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003,
3453} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3454
3455/*
3456 * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3457 */
3458
3459typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3460FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000,
3461FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001,
3462FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002,
3463FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003,
3464} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3465
3466/*
3467 * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3468 */
3469
3470typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3471FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000,
3472FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001,
3473FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002,
3474FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003,
3475} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3476
3477/*
3478 * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3479 */
3480
3481typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3482FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000,
3483FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
3484FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002,
3485} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3486
3487/*
3488 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3489 */
3490
3491typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3492FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000,
3493FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001,
3494FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002,
3495} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3496
3497/*
3498 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3499 */
3500
3501typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3502FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000,
3503FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001,
3504} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3505
3506/*
3507 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3508 */
3509
3510typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3511FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000,
3512FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001,
3513FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002,
3514} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3515
3516/*
3517 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3518 */
3519
3520typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3521FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000,
3522FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001,
3523} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3524
3525/*
3526 * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3527 */
3528
3529typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3530FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000,
3531FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001,
3532FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002,
3533FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003,
3534FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004,
3535FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005,
3536FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006,
3537FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007,
3538} FMT_CLAMP_CNTL_COLOR_FORMAT;
3539
3540/*
3541 * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3542 */
3543
3544typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3545FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000,
3546FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001,
3547} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
3548
3549/*
3550 * FMT_CONTROL_PIXEL_ENCODING enum
3551 */
3552
3553typedef enum FMT_CONTROL_PIXEL_ENCODING {
3554FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000,
3555FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001,
3556FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002,
3557FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003,
3558} FMT_CONTROL_PIXEL_ENCODING;
3559
3560/*
3561 * FMT_CONTROL_SUBSAMPLING_MODE enum
3562 */
3563
3564typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3565FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000,
3566FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001,
3567FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002,
3568FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003,
3569} FMT_CONTROL_SUBSAMPLING_MODE;
3570
3571/*
3572 * FMT_CONTROL_SUBSAMPLING_ORDER enum
3573 */
3574
3575typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3576FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000,
3577FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001,
3578} FMT_CONTROL_SUBSAMPLING_ORDER;
3579
3580/*
3581 * FMT_DEBUG_CNTL_COLOR_SELECT enum
3582 */
3583
3584typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3585FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x00000000,
3586FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x00000001,
3587FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x00000002,
3588FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x00000003,
3589} FMT_DEBUG_CNTL_COLOR_SELECT;
3590
3591/*
3592 * FMT_DYNAMIC_EXP_MODE enum
3593 */
3594
3595typedef enum FMT_DYNAMIC_EXP_MODE {
3596FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000,
3597FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001,
3598} FMT_DYNAMIC_EXP_MODE;
3599
3600/*
3601 * FMT_FRAME_RANDOM_ENABLE_CONTROL enum
3602 */
3603
3604typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL {
3605FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0x00000000,
3606FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 0x00000001,
3607} FMT_FRAME_RANDOM_ENABLE_CONTROL;
3608
3609/*
3610 * FMT_POWER_STATE_ENUM enum
3611 */
3612
3613typedef enum FMT_POWER_STATE_ENUM {
3614FMT_POWER_STATE_ENUM_ON = 0x00000000,
3615FMT_POWER_STATE_ENUM_LS = 0x00000001,
3616FMT_POWER_STATE_ENUM_DS = 0x00000002,
3617FMT_POWER_STATE_ENUM_SD = 0x00000003,
3618} FMT_POWER_STATE_ENUM;
3619
3620/*
3621 * FMT_RGB_RANDOM_ENABLE_CONTROL enum
3622 */
3623
3624typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL {
3625FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0x00000000,
3626FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 0x00000001,
3627} FMT_RGB_RANDOM_ENABLE_CONTROL;
3628
3629/*
3630 * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum
3631 */
3632
3633typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL {
3634FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0x00000000,
3635FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 0x00000001,
3636FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 0x00000002,
3637FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 0x00000003,
3638} FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL;
3639
3640/*
3641 * FMT_SPATIAL_DITHER_MODE enum
3642 */
3643
3644typedef enum FMT_SPATIAL_DITHER_MODE {
3645FMT_SPATIAL_DITHER_MODE_0 = 0x00000000,
3646FMT_SPATIAL_DITHER_MODE_1 = 0x00000001,
3647FMT_SPATIAL_DITHER_MODE_2 = 0x00000002,
3648FMT_SPATIAL_DITHER_MODE_3 = 0x00000003,
3649} FMT_SPATIAL_DITHER_MODE;
3650
3651/*
3652 * FMT_STEREOSYNC_OVERRIDE_CONTROL enum
3653 */
3654
3655typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL {
3656FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0x00000000,
3657FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 0x00000001,
3658} FMT_STEREOSYNC_OVERRIDE_CONTROL;
3659
3660/*
3661 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3662 */
3663
3664typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3665FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000,
3666FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001,
3667} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3668
3669/*******************************************************
3670 * OPPBUF Enums
3671 *******************************************************/
3672
3673/*
3674 * OPPBUF_DISPLAY_SEGMENTATION enum
3675 */
3676
3677typedef enum OPPBUF_DISPLAY_SEGMENTATION {
3678OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0x00000000,
3679OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 0x00000001,
3680OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 0x00000002,
3681OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 0x00000003,
3682OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 0x00000004,
3683} OPPBUF_DISPLAY_SEGMENTATION;
3684
3685/*******************************************************
3686 * OPP_PIPE Enums
3687 *******************************************************/
3688
3689/*
3690 * OPP_PIPE_CLOCK_ENABLE_CONTROL enum
3691 */
3692
3693typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL {
3694OPP_PIPE_CLOCK_DISABLE = 0x00000000,
3695OPP_PIPE_CLOCK_ENABLE = 0x00000001,
3696} OPP_PIPE_CLOCK_ENABLE_CONTROL;
3697
3698/*
3699 * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum
3700 */
3701
3702typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL {
3703OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0x00000000,
3704OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 0x00000001,
3705} OPP_PIPE_DIGTIAL_BYPASS_CONTROL;
3706
3707/*******************************************************
3708 * OPP_PIPE_CRC Enums
3709 *******************************************************/
3710
3711/*
3712 * OPP_PIPE_CRC_CONT_EN enum
3713 */
3714
3715typedef enum OPP_PIPE_CRC_CONT_EN {
3716OPP_PIPE_CRC_MODE_ONE_SHOT = 0x00000000,
3717OPP_PIPE_CRC_MODE_CONTINUOUS = 0x00000001,
3718} OPP_PIPE_CRC_CONT_EN;
3719
3720/*
3721 * OPP_PIPE_CRC_EN enum
3722 */
3723
3724typedef enum OPP_PIPE_CRC_EN {
3725OPP_PIPE_CRC_DISABLE = 0x00000000,
3726OPP_PIPE_CRC_ENABLE = 0x00000001,
3727} OPP_PIPE_CRC_EN;
3728
3729/*
3730 * OPP_PIPE_CRC_INTERLACE_EN enum
3731 */
3732
3733typedef enum OPP_PIPE_CRC_INTERLACE_EN {
3734OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0x00000000,
3735OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 0x00000001,
3736} OPP_PIPE_CRC_INTERLACE_EN;
3737
3738/*
3739 * OPP_PIPE_CRC_INTERLACE_MODE enum
3740 */
3741
3742typedef enum OPP_PIPE_CRC_INTERLACE_MODE {
3743OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0x00000000,
3744OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
3745OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 0x00000002,
3746OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 0x00000003,
3747} OPP_PIPE_CRC_INTERLACE_MODE;
3748
3749/*
3750 * OPP_PIPE_CRC_ONE_SHOT_PENDING enum
3751 */
3752
3753typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING {
3754OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0x00000000,
3755OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 0x00000001,
3756} OPP_PIPE_CRC_ONE_SHOT_PENDING;
3757
3758/*
3759 * OPP_PIPE_CRC_PIXEL_SELECT enum
3760 */
3761
3762typedef enum OPP_PIPE_CRC_PIXEL_SELECT {
3763OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0x00000000,
3764OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 0x00000001,
3765OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 0x00000002,
3766OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 0x00000003,
3767} OPP_PIPE_CRC_PIXEL_SELECT;
3768
3769/*
3770 * OPP_PIPE_CRC_SOURCE_SELECT enum
3771 */
3772
3773typedef enum OPP_PIPE_CRC_SOURCE_SELECT {
3774OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0x00000000,
3775OPP_PIPE_CRC_SOURCE_SELECT_SFT = 0x00000001,
3776} OPP_PIPE_CRC_SOURCE_SELECT;
3777
3778/*
3779 * OPP_PIPE_CRC_STEREO_EN enum
3780 */
3781
3782typedef enum OPP_PIPE_CRC_STEREO_EN {
3783OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0x00000000,
3784OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 0x00000001,
3785} OPP_PIPE_CRC_STEREO_EN;
3786
3787/*
3788 * OPP_PIPE_CRC_STEREO_MODE enum
3789 */
3790
3791typedef enum OPP_PIPE_CRC_STEREO_MODE {
3792OPP_PIPE_CRC_STEREO_MODE_LEFT = 0x00000000,
3793OPP_PIPE_CRC_STEREO_MODE_RIGHT = 0x00000001,
3794OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 0x00000002,
3795OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 0x00000003,
3796} OPP_PIPE_CRC_STEREO_MODE;
3797
3798/*******************************************************
3799 * OPP_TOP Enums
3800 *******************************************************/
3801
3802/*
3803 * OPP_TEST_CLK_SEL_CONTROL enum
3804 */
3805
3806typedef enum OPP_TEST_CLK_SEL_CONTROL {
3807OPP_TEST_CLK_SEL_DISPCLK_P = 0x00000000,
3808OPP_TEST_CLK_SEL_DISPCLK_R = 0x00000001,
3809OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 0x00000002,
3810OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 0x00000003,
3811OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 0x00000004,
3812OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 0x00000005,
3813OPP_TEST_CLK_SEL_RESERVED0 = 0x00000006,
3814OPP_TEST_CLK_SEL_RESERVED1 = 0x00000007,
3815OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 0x00000008,
3816OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 0x00000009,
3817OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 0x0000000a,
3818OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 0x0000000b,
3819OPP_TEST_CLK_SEL_RESERVED2 = 0x0000000c,
3820OPP_TEST_CLK_SEL_RESERVED3 = 0x0000000d,
3821} OPP_TEST_CLK_SEL_CONTROL;
3822
3823/*
3824 * OPP_TOP_CLOCK_ENABLE_STATUS enum
3825 */
3826
3827typedef enum OPP_TOP_CLOCK_ENABLE_STATUS {
3828OPP_TOP_CLOCK_DISABLED_STATUS = 0x00000000,
3829OPP_TOP_CLOCK_ENABLED_STATUS = 0x00000001,
3830} OPP_TOP_CLOCK_ENABLE_STATUS;
3831
3832/*
3833 * OPP_TOP_CLOCK_GATING_CONTROL enum
3834 */
3835
3836typedef enum OPP_TOP_CLOCK_GATING_CONTROL {
3837OPP_TOP_CLOCK_GATING_ENABLED = 0x00000000,
3838OPP_TOP_CLOCK_GATING_DISABLED = 0x00000001,
3839} OPP_TOP_CLOCK_GATING_CONTROL;
3840
3841/*******************************************************
3842 * OTG Enums
3843 *******************************************************/
3844
3845/*
3846 * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
3847 */
3848
3849typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
3850MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
3851MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
3852} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
3853
3854/*
3855 * MASTER_UPDATE_LOCK_SEL enum
3856 */
3857
3858typedef enum MASTER_UPDATE_LOCK_SEL {
3859MASTER_UPDATE_LOCK_SEL_0 = 0x00000000,
3860MASTER_UPDATE_LOCK_SEL_1 = 0x00000001,
3861MASTER_UPDATE_LOCK_SEL_2 = 0x00000002,
3862MASTER_UPDATE_LOCK_SEL_3 = 0x00000003,
3863MASTER_UPDATE_LOCK_SEL_RESERVED4 = 0x00000004,
3864MASTER_UPDATE_LOCK_SEL_RESERVED5 = 0x00000005,
3865} MASTER_UPDATE_LOCK_SEL;
3866
3867/*
3868 * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
3869 */
3870
3871typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
3872MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000,
3873MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 0x00000001,
3874MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 0x00000002,
3875MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003,
3876} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
3877
3878/*
3879 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum
3880 */
3881
3882typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN {
3883OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0x00000000,
3884OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 0x00000001,
3885} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN;
3886
3887/*
3888 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum
3889 */
3890
3891typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB {
3892OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0x00000000,
3893OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 0x00000001,
3894} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB;
3895
3896/*
3897 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum
3898 */
3899
3900typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR {
3901OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000,
3902OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001,
3903} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR;
3904
3905/*
3906 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum
3907 */
3908
3909typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE {
3910OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000,
3911OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001,
3912OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002,
3913OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003,
3914} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE;
3915
3916/*
3917 * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum
3918 */
3919
3920typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL {
3921OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0x00000000,
3922OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001,
3923OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 0x00000002,
3924OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003,
3925} OTG_CONTROL_OTG_DISABLE_POINT_CNTL;
3926
3927/*
3928 * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum
3929 */
3930
3931typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL {
3932OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
3933OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 0x00000001,
3934} OTG_CONTROL_OTG_FIELD_NUMBER_CNTL;
3935
3936/*
3937 * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum
3938 */
3939
3940typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY {
3941OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0x00000000,
3942OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 0x00000001,
3943} OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY;
3944
3945/*
3946 * OTG_CONTROL_OTG_MASTER_EN enum
3947 */
3948
3949typedef enum OTG_CONTROL_OTG_MASTER_EN {
3950OTG_CONTROL_OTG_MASTER_EN_FALSE = 0x00000000,
3951OTG_CONTROL_OTG_MASTER_EN_TRUE = 0x00000001,
3952} OTG_CONTROL_OTG_MASTER_EN;
3953
3954/*
3955 * OTG_CONTROL_OTG_OUT_MUX enum
3956 */
3957
3958typedef enum OTG_CONTROL_OTG_OUT_MUX {
3959OTG_CONTROL_OTG_OUT_MUX_0 = 0x00000000,
3960OTG_CONTROL_OTG_OUT_MUX_1 = 0x00000001,
3961OTG_CONTROL_OTG_OUT_MUX_2 = 0x00000002,
3962} OTG_CONTROL_OTG_OUT_MUX;
3963
3964/*
3965 * OTG_CONTROL_OTG_START_POINT_CNTL enum
3966 */
3967
3968typedef enum OTG_CONTROL_OTG_START_POINT_CNTL {
3969OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0x00000000,
3970OTG_CONTROL_OTG_START_POINT_CNTL_DP = 0x00000001,
3971} OTG_CONTROL_OTG_START_POINT_CNTL;
3972
3973/*
3974 * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum
3975 */
3976
3977typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN {
3978OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0x00000000,
3979OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 0x00000001,
3980} OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN;
3981
3982/*
3983 * OTG_CRC_CNTL_OTG_CRC1_EN enum
3984 */
3985
3986typedef enum OTG_CRC_CNTL_OTG_CRC1_EN {
3987OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0x00000000,
3988OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 0x00000001,
3989} OTG_CRC_CNTL_OTG_CRC1_EN;
3990
3991/*
3992 * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum
3993 */
3994
3995typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN {
3996OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0x00000000,
3997OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 0x00000001,
3998} OTG_CRC_CNTL_OTG_CRC_CONT_EN;
3999
4000/*
4001 * OTG_CRC_CNTL_OTG_CRC_CONT_MODE enum
4002 */
4003
4004typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_MODE {
4005OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0x00000000,
4006OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 0x00000001,
4007} OTG_CRC_CNTL_OTG_CRC_CONT_MODE;
4008
4009/*
4010 * OTG_CRC_CNTL_OTG_CRC_EN enum
4011 */
4012
4013typedef enum OTG_CRC_CNTL_OTG_CRC_EN {
4014OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0x00000000,
4015OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 0x00000001,
4016} OTG_CRC_CNTL_OTG_CRC_EN;
4017
4018/*
4019 * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum
4020 */
4021
4022typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE {
4023OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0x00000000,
4024OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
4025OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
4026OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003,
4027} OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE;
4028
4029/*
4030 * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum
4031 */
4032
4033typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE {
4034OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0x00000000,
4035OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 0x00000001,
4036OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 0x00000002,
4037OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003,
4038} OTG_CRC_CNTL_OTG_CRC_STEREO_MODE;
4039
4040/*
4041 * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum
4042 */
4043
4044typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS {
4045OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
4046OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001,
4047} OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS;
4048
4049/*
4050 * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum
4051 */
4052
4053typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT {
4054OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0x00000000,
4055OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 0x00000001,
4056OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 0x00000002,
4057OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 0x00000003,
4058OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 0x00000004,
4059OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 0x00000005,
4060OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 0x00000006,
4061OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 0x00000007,
4062} OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT;
4063
4064/*
4065 * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum
4066 */
4067
4068typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT {
4069OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0x00000000,
4070OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 0x00000001,
4071OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 0x00000002,
4072OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 0x00000003,
4073OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 0x00000004,
4074OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 0x00000005,
4075OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 0x00000006,
4076OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 0x00000007,
4077} OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT;
4078
4079/*
4080 * OTG_DIG_UPDATE_VCOUNT_MODE enum
4081 */
4082
4083typedef enum OTG_DIG_UPDATE_VCOUNT_MODE {
4084OTG_DIG_UPDATE_VCOUNT_0 = 0x00000000,
4085OTG_DIG_UPDATE_VCOUNT_1 = 0x00000001,
4086} OTG_DIG_UPDATE_VCOUNT_MODE;
4087
4088/*
4089 * OTG_DLPC_CONTROL_OTG_RESYNC_MODE enum
4090 */
4091
4092typedef enum OTG_DLPC_CONTROL_OTG_RESYNC_MODE {
4093OTG_DLPC_CONTROL_OTG_RESYNC_MODE_0 = 0x00000000,
4094OTG_DLPC_CONTROL_OTG_RESYNC_MODE_1 = 0x00000001,
4095} OTG_DLPC_CONTROL_OTG_RESYNC_MODE;
4096
4097/*
4098 * OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE enum
4099 */
4100
4101typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE {
4102OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000,
4103OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001,
4104OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 0x00000002,
4105OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 0x00000003,
4106} OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE;
4107
4108/*
4109 * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum
4110 */
4111
4112typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY {
4113OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0x00000000,
4114OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 0x00000001,
4115} OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY;
4116
4117/*
4118 * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum
4119 */
4120
4121typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME {
4122OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0x00000000,
4123OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 0x00000001,
4124OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 0x00000002,
4125OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 0x00000003,
4126} OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME;
4127
4128/*
4129 * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum
4130 */
4131
4132typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN {
4133OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0x00000000,
4134OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 0x00000001,
4135} OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN;
4136
4137/*
4138 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum
4139 */
4140
4141typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY {
4142OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000,
4143OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001,
4144} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY;
4145
4146/*
4147 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum
4148 */
4149
4150typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY {
4151OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0x00000000,
4152OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 0x00000001,
4153} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY;
4154
4155/*
4156 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum
4157 */
4158
4159typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT {
4160OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000,
4161OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x00000001,
4162OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x00000002,
4163OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x00000003,
4164OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x00000004,
4165OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x00000005,
4166OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000006,
4167OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000007,
4168OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000008,
4169OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000009,
4170OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x0000000a,
4171OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x0000000b,
4172OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x0000000c,
4173OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x0000000d,
4174OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x0000000e,
4175OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 0x0000000f,
4176OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 0x00000010,
4177OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 0x00000011,
4178OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 0x00000012,
4179OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 0x00000013,
4180} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT;
4181
4182/*
4183 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum
4184 */
4185
4186typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK {
4187OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000,
4188OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001,
4189} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK;
4190
4191/*
4192 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum
4193 */
4194
4195typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR {
4196OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
4197OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001,
4198} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR;
4199
4200/*
4201 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum
4202 */
4203
4204typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE {
4205OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000,
4206OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001,
4207OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002,
4208OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003,
4209} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE;
4210
4211/*
4212 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum
4213 */
4214
4215typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL {
4216OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000,
4217OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001,
4218} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL;
4219
4220/*
4221 * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum
4222 */
4223
4224typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL {
4225OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0x00000000,
4226OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 0x00000001,
4227OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 0x00000002,
4228OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 0x00000003,
4229OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 0x00000004,
4230OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 0x00000005,
4231} OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL;
4232
4233/*
4234 * OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL enum
4235 */
4236
4237typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL {
4238DIG_UPDATE_EYE_SEL_BOTH = 0x00000000,
4239DIG_UPDATE_EYE_SEL_LEFT = 0x00000001,
4240DIG_UPDATE_EYE_SEL_RIGHT = 0x00000002,
4241} OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL;
4242
4243/*
4244 * OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL enum
4245 */
4246
4247typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL {
4248DIG_UPDATE_FIELD_SEL_BOTH = 0x00000000,
4249DIG_UPDATE_FIELD_SEL_TOP = 0x00000001,
4250DIG_UPDATE_FIELD_SEL_BOTTOM = 0x00000002,
4251DIG_UPDATE_FIELD_SEL_RESERVED = 0x00000003,
4252} OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL;
4253
4254/*
4255 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum
4256 */
4257
4258typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD {
4259MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0x00000000,
4260MASTER_UPDATE_LOCK_DB_FIELD_TOP = 0x00000001,
4261MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 0x00000002,
4262MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 0x00000003,
4263} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD;
4264
4265/*
4266 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum
4267 */
4268
4269typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL {
4270MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0x00000000,
4271MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 0x00000001,
4272MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 0x00000002,
4273MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 0x00000003,
4274} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL;
4275
4276/*
4277 * OTG_GLOBAL_UPDATE_LOCK_EN enum
4278 */
4279
4280typedef enum OTG_GLOBAL_UPDATE_LOCK_EN {
4281OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0x00000000,
4282OTG_GLOBAL_UPDATE_LOCK_ENABLE = 0x00000001,
4283} OTG_GLOBAL_UPDATE_LOCK_EN;
4284
4285/*
4286 * OTG_GSL_MASTER_MODE enum
4287 */
4288
4289typedef enum OTG_GSL_MASTER_MODE {
4290OTG_GSL_MASTER_MODE_0 = 0x00000000,
4291OTG_GSL_MASTER_MODE_1 = 0x00000001,
4292OTG_GSL_MASTER_MODE_2 = 0x00000002,
4293OTG_GSL_MASTER_MODE_3 = 0x00000003,
4294} OTG_GSL_MASTER_MODE;
4295
4296/*
4297 * OTG_HORZ_REPETITION_COUNT enum
4298 */
4299
4300typedef enum OTG_HORZ_REPETITION_COUNT {
4301OTG_HORZ_REPETITION_COUNT_0 = 0x00000000,
4302OTG_HORZ_REPETITION_COUNT_1 = 0x00000001,
4303OTG_HORZ_REPETITION_COUNT_2 = 0x00000002,
4304OTG_HORZ_REPETITION_COUNT_3 = 0x00000003,
4305OTG_HORZ_REPETITION_COUNT_4 = 0x00000004,
4306OTG_HORZ_REPETITION_COUNT_5 = 0x00000005,
4307OTG_HORZ_REPETITION_COUNT_6 = 0x00000006,
4308OTG_HORZ_REPETITION_COUNT_7 = 0x00000007,
4309OTG_HORZ_REPETITION_COUNT_8 = 0x00000008,
4310OTG_HORZ_REPETITION_COUNT_9 = 0x00000009,
4311OTG_HORZ_REPETITION_COUNT_10 = 0x0000000a,
4312OTG_HORZ_REPETITION_COUNT_11 = 0x0000000b,
4313OTG_HORZ_REPETITION_COUNT_12 = 0x0000000c,
4314OTG_HORZ_REPETITION_COUNT_13 = 0x0000000d,
4315OTG_HORZ_REPETITION_COUNT_14 = 0x0000000e,
4316OTG_HORZ_REPETITION_COUNT_15 = 0x0000000f,
4317} OTG_HORZ_REPETITION_COUNT;
4318
4319/*
4320 * OTG_H_SYNC_A_POL enum
4321 */
4322
4323typedef enum OTG_H_SYNC_A_POL {
4324OTG_H_SYNC_A_POL_HIGH = 0x00000000,
4325OTG_H_SYNC_A_POL_LOW = 0x00000001,
4326} OTG_H_SYNC_A_POL;
4327
4328/*
4329 * OTG_H_TIMING_DIV_MODE enum
4330 */
4331
4332typedef enum OTG_H_TIMING_DIV_MODE {
4333OTG_H_TIMING_DIV_MODE_NO_DIV = 0x00000000,
4334OTG_H_TIMING_DIV_MODE_DIV_BY2 = 0x00000001,
4335OTG_H_TIMING_DIV_MODE_RESERVED = 0x00000002,
4336OTG_H_TIMING_DIV_MODE_DIV_BY4 = 0x00000003,
4337} OTG_H_TIMING_DIV_MODE;
4338
4339/*
4340 * OTG_H_TIMING_DIV_MODE_MANUAL enum
4341 */
4342
4343typedef enum OTG_H_TIMING_DIV_MODE_MANUAL {
4344OTG_H_TIMING_DIV_MODE_AUTO = 0x00000000,
4345OTG_H_TIMING_DIV_MODE_NOAUTO = 0x00000001,
4346} OTG_H_TIMING_DIV_MODE_MANUAL;
4347
4348/*
4349 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum
4350 */
4351
4352typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE {
4353OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0x00000000,
4354OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 0x00000001,
4355} OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE;
4356
4357/*
4358 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum
4359 */
4360
4361typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD {
4362OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000,
4363OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 0x00000001,
4364OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 0x00000002,
4365OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003,
4366} OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD;
4367
4368/*
4369 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum
4370 */
4371
4372typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK {
4373OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000,
4374OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001,
4375} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK;
4376
4377/*
4378 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum
4379 */
4380
4381typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE {
4382OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000,
4383OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001,
4384} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE;
4385
4386/*
4387 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
4388 */
4389
4390typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK {
4391OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000,
4392OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001,
4393} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK;
4394
4395/*
4396 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
4397 */
4398
4399typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
4400OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000,
4401OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001,
4402} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
4403
4404/*
4405 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum
4406 */
4407
4408typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK {
4409OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000,
4410OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001,
4411} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK;
4412
4413/*
4414 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum
4415 */
4416
4417typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE {
4418OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000,
4419OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001,
4420} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE;
4421
4422/*
4423 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum
4424 */
4425
4426typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK {
4427OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0x00000000,
4428OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 0x00000001,
4429} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK;
4430
4431/*
4432 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum
4433 */
4434
4435typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE {
4436OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0x00000000,
4437OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 0x00000001,
4438} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE;
4439
4440/*
4441 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum
4442 */
4443
4444typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK {
4445OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0x00000000,
4446OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 0x00000001,
4447} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK;
4448
4449/*
4450 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum
4451 */
4452
4453typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE {
4454OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0x00000000,
4455OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 0x00000001,
4456} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE;
4457
4458/*
4459 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum
4460 */
4461
4462typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK {
4463OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0x00000000,
4464OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 0x00000001,
4465} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK;
4466
4467/*
4468 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum
4469 */
4470
4471typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE {
4472OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0x00000000,
4473OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 0x00000001,
4474} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE;
4475
4476/*
4477 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum
4478 */
4479
4480typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK {
4481OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0x00000000,
4482OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 0x00000001,
4483} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK;
4484
4485/*
4486 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum
4487 */
4488
4489typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE {
4490OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000,
4491OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001,
4492} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE;
4493
4494/*
4495 * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum
4496 */
4497
4498typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE {
4499OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
4500OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001,
4501} OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE;
4502
4503/*
4504 * OTG_MASTER_UPDATE_LOCK_DB_EN enum
4505 */
4506
4507typedef enum OTG_MASTER_UPDATE_LOCK_DB_EN {
4508OTG_MASTER_UPDATE_LOCK_DISABLE = 0x00000000,
4509OTG_MASTER_UPDATE_LOCK_ENABLE = 0x00000001,
4510} OTG_MASTER_UPDATE_LOCK_DB_EN;
4511
4512/*
4513 * OTG_MASTER_UPDATE_LOCK_GSL_EN enum
4514 */
4515
4516typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN {
4517OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0x00000000,
4518OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 0x00000001,
4519} OTG_MASTER_UPDATE_LOCK_GSL_EN;
4520
4521/*
4522 * OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE enum
4523 */
4524
4525typedef enum OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE {
4526OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0x00000000,
4527OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 0x00000001,
4528} OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE;
4529
4530/*
4531 * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum
4532 */
4533
4534typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL {
4535OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000,
4536OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001,
4537OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002,
4538OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003,
4539} OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL;
4540
4541/*
4542 * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum
4543 */
4544
4545typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR {
4546OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0x00000000,
4547OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 0x00000001,
4548} OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR;
4549
4550/*
4551 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum
4552 */
4553
4554typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR {
4555OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
4556OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 0x00000001,
4557} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR;
4558
4559/*
4560 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum
4561 */
4562
4563typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE {
4564OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0x00000000,
4565OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 0x00000001,
4566} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE;
4567
4568/*
4569 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum
4570 */
4571
4572typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE {
4573OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0x00000000,
4574OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 0x00000001,
4575} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE;
4576
4577/*
4578 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum
4579 */
4580
4581typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE {
4582OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000,
4583OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001,
4584} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE;
4585
4586/*
4587 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum
4588 */
4589
4590typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE {
4591OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000,
4592OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001,
4593} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE;
4594
4595/*
4596 * OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL enum
4597 */
4598
4599typedef enum OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL {
4600OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0x00000000,
4601OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 0x00000001,
4602} OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL;
4603
4604/*
4605 * OTG_STEREO_CONTROL_OTG_STEREO_EN enum
4606 */
4607
4608typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN {
4609OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0x00000000,
4610OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 0x00000001,
4611} OTG_STEREO_CONTROL_OTG_STEREO_EN;
4612
4613/*
4614 * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum
4615 */
4616
4617typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY {
4618OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000,
4619OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001,
4620} OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY;
4621
4622/*
4623 * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum
4624 */
4625
4626typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY {
4627OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000,
4628OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001,
4629} OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY;
4630
4631/*
4632 * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum
4633 */
4634
4635typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE {
4636OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0x00000000,
4637OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001,
4638OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002,
4639OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003,
4640} OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE;
4641
4642/*
4643 * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum
4644 */
4645
4646typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR {
4647OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0x00000000,
4648OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 0x00000001,
4649} OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR;
4650
4651/*
4652 * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum
4653 */
4654
4655typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT {
4656OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0x00000000,
4657OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001,
4658OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002,
4659OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003,
4660OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004,
4661OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 0x00000005,
4662OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 0x00000006,
4663OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 0x00000007,
4664} OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT;
4665
4666/*
4667 * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum
4668 */
4669
4670typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN {
4671OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000,
4672OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001,
4673} OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN;
4674
4675/*
4676 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum
4677 */
4678
4679typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT {
4680OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0x00000000,
4681OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 0x00000001,
4682OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 0x00000002,
4683OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 0x00000003,
4684OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004,
4685OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005,
4686} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT;
4687
4688/*
4689 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum
4690 */
4691
4692typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT {
4693OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0x00000000,
4694OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 0x00000001,
4695OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 0x00000002,
4696OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 0x00000003,
4697OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 0x00000004,
4698OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 0x00000005,
4699OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 0x00000006,
4700OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007,
4701OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008,
4702OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009,
4703OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a,
4704OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b,
4705OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c,
4706OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d,
4707OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 0x0000000e,
4708OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f,
4709OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010,
4710OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 0x00000011,
4711OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 0x00000012,
4712OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 0x00000013,
4713OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 0x00000014,
4714OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015,
4715OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016,
4716OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 0x00000017,
4717OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 0x00000018,
4718} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT;
4719
4720/*
4721 * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum
4722 */
4723
4724typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL {
4725OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000,
4726OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001,
4727OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002,
4728OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003,
4729} OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;
4730
4731/*
4732 * OTG_TRIGA_FREQUENCY_SELECT enum
4733 */
4734
4735typedef enum OTG_TRIGA_FREQUENCY_SELECT {
4736OTG_TRIGA_FREQUENCY_SELECT_0 = 0x00000000,
4737OTG_TRIGA_FREQUENCY_SELECT_1 = 0x00000001,
4738OTG_TRIGA_FREQUENCY_SELECT_2 = 0x00000002,
4739OTG_TRIGA_FREQUENCY_SELECT_3 = 0x00000003,
4740} OTG_TRIGA_FREQUENCY_SELECT;
4741
4742/*
4743 * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum
4744 */
4745
4746typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL {
4747OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0x00000000,
4748OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 0x00000001,
4749OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 0x00000002,
4750OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 0x00000003,
4751} OTG_TRIGA_RISING_EDGE_DETECT_CNTL;
4752
4753/*
4754 * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum
4755 */
4756
4757typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR {
4758OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0x00000000,
4759OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 0x00000001,
4760} OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR;
4761
4762/*
4763 * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum
4764 */
4765
4766typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT {
4767OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0x00000000,
4768OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001,
4769OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002,
4770OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003,
4771OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004,
4772OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 0x00000005,
4773OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 0x00000006,
4774OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 0x00000007,
4775} OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT;
4776
4777/*
4778 * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum
4779 */
4780
4781typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN {
4782OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000,
4783OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001,
4784} OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN;
4785
4786/*
4787 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum
4788 */
4789
4790typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT {
4791OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0x00000000,
4792OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 0x00000001,
4793OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 0x00000002,
4794OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 0x00000003,
4795OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004,
4796OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005,
4797} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT;
4798
4799/*
4800 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum
4801 */
4802
4803typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT {
4804OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0x00000000,
4805OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 0x00000001,
4806OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 0x00000002,
4807OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 0x00000003,
4808OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 0x00000004,
4809OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 0x00000005,
4810OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 0x00000006,
4811OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007,
4812OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008,
4813OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009,
4814OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a,
4815OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b,
4816OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c,
4817OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d,
4818OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 0x0000000e,
4819OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f,
4820OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010,
4821OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 0x00000011,
4822OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 0x00000012,
4823OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 0x00000013,
4824OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 0x00000014,
4825OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015,
4826OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016,
4827OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 0x00000017,
4828OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 0x00000018,
4829} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT;
4830
4831/*
4832 * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum
4833 */
4834
4835typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL {
4836OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000,
4837OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001,
4838OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002,
4839OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003,
4840} OTG_TRIGB_FALLING_EDGE_DETECT_CNTL;
4841
4842/*
4843 * OTG_TRIGB_FREQUENCY_SELECT enum
4844 */
4845
4846typedef enum OTG_TRIGB_FREQUENCY_SELECT {
4847OTG_TRIGB_FREQUENCY_SELECT_0 = 0x00000000,
4848OTG_TRIGB_FREQUENCY_SELECT_1 = 0x00000001,
4849OTG_TRIGB_FREQUENCY_SELECT_2 = 0x00000002,
4850OTG_TRIGB_FREQUENCY_SELECT_3 = 0x00000003,
4851} OTG_TRIGB_FREQUENCY_SELECT;
4852
4853/*
4854 * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum
4855 */
4856
4857typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL {
4858OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0x00000000,
4859OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 0x00000001,
4860OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 0x00000002,
4861OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 0x00000003,
4862} OTG_TRIGB_RISING_EDGE_DETECT_CNTL;
4863
4864/*
4865 * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum
4866 */
4867
4868typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK {
4869OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0x00000000,
4870OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 0x00000001,
4871} OTG_UPDATE_LOCK_OTG_UPDATE_LOCK;
4872
4873/*
4874 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum
4875 */
4876
4877typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR {
4878OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
4879OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001,
4880} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR;
4881
4882/*
4883 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum
4884 */
4885
4886typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE {
4887OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
4888OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001,
4889} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE;
4890
4891/*
4892 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum
4893 */
4894
4895typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE {
4896OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000,
4897OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001,
4898} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE;
4899
4900/*
4901 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
4902 */
4903
4904typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
4905OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000,
4906OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001,
4907} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
4908
4909/*
4910 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum
4911 */
4912
4913typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR {
4914OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
4915OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001,
4916} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR;
4917
4918/*
4919 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum
4920 */
4921
4922typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE {
4923OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
4924OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001,
4925} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE;
4926
4927/*
4928 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum
4929 */
4930
4931typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE {
4932OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000,
4933OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001,
4934} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE;
4935
4936/*
4937 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum
4938 */
4939
4940typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR {
4941OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
4942OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001,
4943} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR;
4944
4945/*
4946 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum
4947 */
4948
4949typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE {
4950OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
4951OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001,
4952} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE;
4953
4954/*
4955 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum
4956 */
4957
4958typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE {
4959OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000,
4960OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001,
4961} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE;
4962
4963/*
4964 * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum
4965 */
4966
4967typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE {
4968OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000,
4969OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001,
4970OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002,
4971OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003,
4972} OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE;
4973
4974/*
4975 * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum
4976 */
4977
4978typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR {
4979OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
4980OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001,
4981} OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;
4982
4983/*
4984 * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum
4985 */
4986
4987typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR {
4988OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
4989OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001,
4990} OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR;
4991
4992/*
4993 * OTG_VUPDATE_BLOCK_DISABLE enum
4994 */
4995
4996typedef enum OTG_VUPDATE_BLOCK_DISABLE {
4997OTG_VUPDATE_BLOCK_DISABLE_OFF = 0x00000000,
4998OTG_VUPDATE_BLOCK_DISABLE_ON = 0x00000001,
4999} OTG_VUPDATE_BLOCK_DISABLE;
5000
5001/*
5002 * OTG_V_SYNC_A_POL enum
5003 */
5004
5005typedef enum OTG_V_SYNC_A_POL {
5006OTG_V_SYNC_A_POL_HIGH = 0x00000000,
5007OTG_V_SYNC_A_POL_LOW = 0x00000001,
5008} OTG_V_SYNC_A_POL;
5009
5010/*
5011 * OTG_V_SYNC_MODE enum
5012 */
5013
5014typedef enum OTG_V_SYNC_MODE {
5015OTG_V_SYNC_MODE_HSYNC = 0x00000000,
5016OTG_V_SYNC_MODE_HBLANK = 0x00000001,
5017} OTG_V_SYNC_MODE;
5018
5019/*
5020 * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum
5021 */
5022
5023typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD {
5024OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0x00000000,
5025OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 0x00000001,
5026} OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD;
5027
5028/*
5029 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum
5030 */
5031
5032typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT {
5033OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
5034OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001,
5035} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT;
5036
5037/*
5038 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum
5039 */
5040
5041typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC {
5042OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
5043OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001,
5044} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC;
5045
5046/*
5047 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum
5048 */
5049
5050typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL {
5051OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0x00000000,
5052OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 0x00000001,
5053} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL;
5054
5055/*
5056 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum
5057 */
5058
5059typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL {
5060OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0x00000000,
5061OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 0x00000001,
5062} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL;
5063
5064/*
5065 * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK enum
5066 */
5067
5068typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK {
5069OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0x00000000,
5070OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 0x00000001,
5071} OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK;
5072
5073/*******************************************************
5074 * OPTC_MISC Enums
5075 *******************************************************/
5076
5077/*
5078 * OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL enum
5079 */
5080
5081typedef enum OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL {
5082OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0x00000000,
5083OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 0x00000001,
5084OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 0x00000002,
5085OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 0x00000003,
5086OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 0x00000004,
5087OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 0x00000005,
5088} OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL;
5089
5090/*******************************************************
5091 * DMCUB Enums
5092 *******************************************************/
5093
5094/*
5095 * DC_DMCUB_INT_TYPE enum
5096 */
5097
5098typedef enum DC_DMCUB_INT_TYPE {
5099INT_LEVEL = 0x00000000,
5100INT_PULSE = 0x00000001,
5101} DC_DMCUB_INT_TYPE;
5102
5103/*
5104 * DC_DMCUB_TIMER_WINDOW enum
5105 */
5106
5107typedef enum DC_DMCUB_TIMER_WINDOW {
5108BITS_31_0 = 0x00000000,
5109BITS_32_1 = 0x00000001,
5110BITS_33_2 = 0x00000002,
5111BITS_34_3 = 0x00000003,
5112BITS_35_4 = 0x00000004,
5113BITS_36_5 = 0x00000005,
5114BITS_37_6 = 0x00000006,
5115BITS_38_7 = 0x00000007,
5116} DC_DMCUB_TIMER_WINDOW;
5117
5118/*******************************************************
5119 * RBBMIF Enums
5120 *******************************************************/
5121
5122/*
5123 * INVALID_REG_ACCESS_TYPE enum
5124 */
5125
5126typedef enum INVALID_REG_ACCESS_TYPE {
5127REG_UNALLOCATED_ADDR_WRITE = 0x00000000,
5128REG_UNALLOCATED_ADDR_READ = 0x00000001,
5129REG_VIRTUAL_WRITE = 0x00000002,
5130REG_VIRTUAL_READ = 0x00000003,
5131REG_SECURE_VIOLATE_WRITE = 0x00000004,
5132REG_SECURE_VIOLATE_READ = 0x00000005,
5133} INVALID_REG_ACCESS_TYPE;
5134
5135/*******************************************************
5136 * IHC Enums
5137 *******************************************************/
5138
5139/*
5140 * DMU_DC_GPU_TIMER_READ_SELECT enum
5141 */
5142
5143typedef enum DMU_DC_GPU_TIMER_READ_SELECT {
5144DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0x00000000,
5145DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 0x00000001,
5146DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 0x00000002,
5147DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 0x00000003,
5148DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 0x00000004,
5149DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 0x00000005,
5150DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 0x00000006,
5151DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 0x00000007,
5152RESERVED_8 = 0x00000008,
5153RESERVED_9 = 0x00000009,
5154RESERVED_10 = 0x0000000a,
5155RESERVED_11 = 0x0000000b,
5156DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 0x0000000c,
5157DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 0x0000000d,
5158DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 0x0000000e,
5159DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 0x0000000f,
5160DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 0x00000010,
5161DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 0x00000011,
5162DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 0x00000012,
5163DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 0x00000013,
5164RESERVED_20 = 0x00000014,
5165RESERVED_21 = 0x00000015,
5166RESERVED_22 = 0x00000016,
5167RESERVED_23 = 0x00000017,
5168DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 0x00000018,
5169DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 0x00000019,
5170DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 0x0000001a,
5171DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 0x0000001b,
5172DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 0x0000001c,
5173DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 0x0000001d,
5174DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 0x0000001e,
5175DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 0x0000001f,
5176RESERVED_32 = 0x00000020,
5177RESERVED_33 = 0x00000021,
5178RESERVED_34 = 0x00000022,
5179RESERVED_35 = 0x00000023,
5180DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 0x00000024,
5181DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 0x00000025,
5182DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 0x00000026,
5183DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 0x00000027,
5184DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 0x00000028,
5185DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 0x00000029,
5186DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 0x0000002a,
5187DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 0x0000002b,
5188RESERVED_44 = 0x0000002c,
5189RESERVED_45 = 0x0000002d,
5190RESERVED_46 = 0x0000002e,
5191RESERVED_47 = 0x0000002f,
5192DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 0x00000030,
5193DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 0x00000031,
5194DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 0x00000032,
5195DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 0x00000033,
5196DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 0x00000034,
5197DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 0x00000035,
5198DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 0x00000036,
5199DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 0x00000037,
5200RESERVED_56 = 0x00000038,
5201RESERVED_57 = 0x00000039,
5202RESERVED_58 = 0x0000003a,
5203RESERVED_59 = 0x0000003b,
5204RESERVED_60 = 0x0000003c,
5205RESERVED_61 = 0x0000003d,
5206RESERVED_62 = 0x0000003e,
5207RESERVED_63 = 0x0000003f,
5208DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 0x00000040,
5209DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 0x00000041,
5210DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 0x00000042,
5211DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 0x00000043,
5212DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 0x00000044,
5213DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 0x00000045,
5214DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 0x00000046,
5215DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 0x00000047,
5216RESERVED_72 = 0x00000048,
5217RESERVED_73 = 0x00000049,
5218RESERVED_74 = 0x0000004a,
5219RESERVED_75 = 0x0000004b,
5220DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 0x0000004c,
5221DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 0x0000004d,
5222DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 0x0000004e,
5223DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 0x0000004f,
5224DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 0x00000050,
5225DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 0x00000051,
5226DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 0x00000052,
5227DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 0x00000053,
5228RESERVED_84 = 0x00000054,
5229RESERVED_85 = 0x00000055,
5230RESERVED_86 = 0x00000056,
5231RESERVED_87 = 0x00000057,
5232RESERVED_88 = 0x00000058,
5233RESERVED_89 = 0x00000059,
5234RESERVED_90 = 0x0000005a,
5235RESERVED_91 = 0x0000005b,
5236} DMU_DC_GPU_TIMER_READ_SELECT;
5237
5238/*
5239 * DMU_DC_GPU_TIMER_START_POSITION enum
5240 */
5241
5242typedef enum DMU_DC_GPU_TIMER_START_POSITION {
5243DMU_GPU_TIMER_START_0_END_27 = 0x00000000,
5244DMU_GPU_TIMER_START_1_END_28 = 0x00000001,
5245DMU_GPU_TIMER_START_2_END_29 = 0x00000002,
5246DMU_GPU_TIMER_START_3_END_30 = 0x00000003,
5247DMU_GPU_TIMER_START_4_END_31 = 0x00000004,
5248DMU_GPU_TIMER_START_6_END_33 = 0x00000005,
5249DMU_GPU_TIMER_START_8_END_35 = 0x00000006,
5250DMU_GPU_TIMER_START_10_END_37 = 0x00000007,
5251} DMU_DC_GPU_TIMER_START_POSITION;
5252
5253/*
5254 * IHC_INTERRUPT_DEST enum
5255 */
5256
5257typedef enum IHC_INTERRUPT_DEST {
5258INTERRUPT_SENT_TO_IH = 0x00000000,
5259INTERRUPT_SENT_TO_DMCUB = 0x00000001,
5260} IHC_INTERRUPT_DEST;
5261
5262/*
5263 * IHC_INTERRUPT_LINE_STATUS enum
5264 */
5265
5266typedef enum IHC_INTERRUPT_LINE_STATUS {
5267INTERRUPT_LINE_NOT_ASSERTED = 0x00000000,
5268INTERRUPT_LINE_ASSERTED = 0x00000001,
5269} IHC_INTERRUPT_LINE_STATUS;
5270
5271/*******************************************************
5272 * DMU_MISC Enums
5273 *******************************************************/
5274
5275/*
5276 * DC_SMU_INTERRUPT_ENABLE enum
5277 */
5278
5279typedef enum DC_SMU_INTERRUPT_ENABLE {
5280DISABLE_THE_INTERRUPT = 0x00000000,
5281ENABLE_THE_INTERRUPT = 0x00000001,
5282} DC_SMU_INTERRUPT_ENABLE;
5283
5284/*
5285 * DMU_CLOCK_ON enum
5286 */
5287
5288typedef enum DMU_CLOCK_ON {
5289DMU_CLOCK_STATUS_ON = 0x00000000,
5290DMU_CLOCK_STATUS_OFF = 0x00000001,
5291} DMU_CLOCK_ON;
5292
5293/*
5294 * SMU_INTR enum
5295 */
5296
5297typedef enum SMU_INTR {
5298SMU_MSG_INTR_NOOP = 0x00000000,
5299SET_SMU_MSG_INTR = 0x00000001,
5300} SMU_INTR;
5301
5302/*******************************************************
5303 * DCCG Enums
5304 *******************************************************/
5305
5306/*
5307 * ALLOW_SR_ON_TRANS_REQ enum
5308 */
5309
5310typedef enum ALLOW_SR_ON_TRANS_REQ {
5311ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000,
5312ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001,
5313} ALLOW_SR_ON_TRANS_REQ;
5314
5315/*
5316 * AMCLOCK_ENABLE enum
5317 */
5318
5319typedef enum AMCLOCK_ENABLE {
5320ENABLE_AMCLK0 = 0x00000000,
5321ENABLE_AMCLK1 = 0x00000001,
5322} AMCLOCK_ENABLE;
5323
5324/*
5325 * CLEAR_SMU_INTR enum
5326 */
5327
5328typedef enum CLEAR_SMU_INTR {
5329SMU_INTR_STATUS_NOOP = 0x00000000,
5330SMU_INTR_STATUS_CLEAR = 0x00000001,
5331} CLEAR_SMU_INTR;
5332
5333/*
5334 * CLOCK_BRANCH_SOFT_RESET enum
5335 */
5336
5337typedef enum CLOCK_BRANCH_SOFT_RESET {
5338CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000,
5339CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001,
5340} CLOCK_BRANCH_SOFT_RESET;
5341
5342/*
5343 * DCCG_AUDIO_DTO0_SOURCE_SEL enum
5344 */
5345
5346typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
5347DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0x00000000,
5348DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 0x00000001,
5349DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 0x00000002,
5350DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 0x00000003,
5351DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000004,
5352} DCCG_AUDIO_DTO0_SOURCE_SEL;
5353
5354/*
5355 * DCCG_AUDIO_DTO2_SOURCE_SEL enum
5356 */
5357
5358typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
5359DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000,
5360DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 0x00000001,
5361} DCCG_AUDIO_DTO2_SOURCE_SEL;
5362
5363/*
5364 * DCCG_AUDIO_DTO_SEL enum
5365 */
5366
5367typedef enum DCCG_AUDIO_DTO_SEL {
5368DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000,
5369DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001,
5370DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002,
5371} DCCG_AUDIO_DTO_SEL;
5372
5373/*
5374 * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
5375 */
5376
5377typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
5378DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000,
5379DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001,
5380} DCCG_AUDIO_DTO_USE_512FBR_DTO;
5381
5382/*
5383 * DCCG_DBG_BLOCK_SEL enum
5384 */
5385
5386typedef enum DCCG_DBG_BLOCK_SEL {
5387DCCG_DBG_BLOCK_SEL_DCCG = 0x00000000,
5388DCCG_DBG_BLOCK_SEL_PMON = 0x00000001,
5389DCCG_DBG_BLOCK_SEL_PMON2 = 0x00000002,
5390} DCCG_DBG_BLOCK_SEL;
5391
5392/*
5393 * DCCG_DBG_EN enum
5394 */
5395
5396typedef enum DCCG_DBG_EN {
5397DCCG_DBG_EN_DISABLE = 0x00000000,
5398DCCG_DBG_EN_ENABLE = 0x00000001,
5399} DCCG_DBG_EN;
5400
5401/*
5402 * DCCG_DEEP_COLOR_CNTL enum
5403 */
5404
5405typedef enum DCCG_DEEP_COLOR_CNTL {
5406DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000,
5407DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001,
5408DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002,
5409DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003,
5410} DCCG_DEEP_COLOR_CNTL;
5411
5412/*
5413 * DCCG_FIFO_ERRDET_OVR_EN enum
5414 */
5415
5416typedef enum DCCG_FIFO_ERRDET_OVR_EN {
5417DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000,
5418DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001,
5419} DCCG_FIFO_ERRDET_OVR_EN;
5420
5421/*
5422 * DCCG_FIFO_ERRDET_RESET enum
5423 */
5424
5425typedef enum DCCG_FIFO_ERRDET_RESET {
5426DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000,
5427DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001,
5428} DCCG_FIFO_ERRDET_RESET;
5429
5430/*
5431 * DCCG_FIFO_ERRDET_STATE enum
5432 */
5433
5434typedef enum DCCG_FIFO_ERRDET_STATE {
5435DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000000,
5436DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000001,
5437} DCCG_FIFO_ERRDET_STATE;
5438
5439/*
5440 * DCCG_PERF_MODE_HSYNC enum
5441 */
5442
5443typedef enum DCCG_PERF_MODE_HSYNC {
5444DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000,
5445DCCG_PERF_MODE_HSYNC_START = 0x00000001,
5446} DCCG_PERF_MODE_HSYNC;
5447
5448/*
5449 * DCCG_PERF_MODE_VSYNC enum
5450 */
5451
5452typedef enum DCCG_PERF_MODE_VSYNC {
5453DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000,
5454DCCG_PERF_MODE_VSYNC_START = 0x00000001,
5455} DCCG_PERF_MODE_VSYNC;
5456
5457/*
5458 * DCCG_PERF_OTG_SELECT enum
5459 */
5460
5461typedef enum DCCG_PERF_OTG_SELECT {
5462DCCG_PERF_SEL_OTG0 = 0x00000000,
5463DCCG_PERF_SEL_OTG1 = 0x00000001,
5464DCCG_PERF_SEL_OTG2 = 0x00000002,
5465DCCG_PERF_SEL_OTG3 = 0x00000003,
5466DCCG_PERF_SEL_RESERVED = 0x00000004,
5467} DCCG_PERF_OTG_SELECT;
5468
5469/*
5470 * DCCG_PERF_RUN enum
5471 */
5472
5473typedef enum DCCG_PERF_RUN {
5474DCCG_PERF_RUN_NOOP = 0x00000000,
5475DCCG_PERF_RUN_START = 0x00000001,
5476} DCCG_PERF_RUN;
5477
5478/*
5479 * DC_MEM_GLOBAL_PWR_REQ_DIS enum
5480 */
5481
5482typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
5483DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000,
5484DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001,
5485} DC_MEM_GLOBAL_PWR_REQ_DIS;
5486
5487/*
5488 * DIO_FIFO_ERROR enum
5489 */
5490
5491typedef enum DIO_FIFO_ERROR {
5492DIO_FIFO_ERROR_00 = 0x00000000,
5493DIO_FIFO_ERROR_01 = 0x00000001,
5494DIO_FIFO_ERROR_10 = 0x00000002,
5495DIO_FIFO_ERROR_11 = 0x00000003,
5496} DIO_FIFO_ERROR;
5497
5498/*
5499 * DISABLE_CLOCK_GATING enum
5500 */
5501
5502typedef enum DISABLE_CLOCK_GATING {
5503CLOCK_GATING_ENABLED = 0x00000000,
5504CLOCK_GATING_DISABLED = 0x00000001,
5505} DISABLE_CLOCK_GATING;
5506
5507/*
5508 * DISABLE_CLOCK_GATING_IN_DCO enum
5509 */
5510
5511typedef enum DISABLE_CLOCK_GATING_IN_DCO {
5512CLOCK_GATING_ENABLED_IN_DCO = 0x00000000,
5513CLOCK_GATING_DISABLED_IN_DCO = 0x00000001,
5514} DISABLE_CLOCK_GATING_IN_DCO;
5515
5516/*
5517 * DISPCLK_CHG_FWD_CORR_DISABLE enum
5518 */
5519
5520typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
5521DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000,
5522DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001,
5523} DISPCLK_CHG_FWD_CORR_DISABLE;
5524
5525/*
5526 * DISPCLK_FREQ_RAMP_DONE enum
5527 */
5528
5529typedef enum DISPCLK_FREQ_RAMP_DONE {
5530DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000,
5531DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001,
5532} DISPCLK_FREQ_RAMP_DONE;
5533
5534/*
5535 * DPREFCLK_SRC_SEL enum
5536 */
5537
5538typedef enum DPREFCLK_SRC_SEL {
5539DPREFCLK_SRC_SEL_CK = 0x00000000,
5540DPREFCLK_SRC_SEL_P0PLL = 0x00000001,
5541DPREFCLK_SRC_SEL_P1PLL = 0x00000002,
5542DPREFCLK_SRC_SEL_P2PLL = 0x00000003,
5543} DPREFCLK_SRC_SEL;
5544
5545/*
5546 * DP_DTO_DS_DISABLE enum
5547 */
5548
5549typedef enum DP_DTO_DS_DISABLE {
5550DP_DTO_DESPREAD_DISABLE = 0x00000000,
5551DP_DTO_DESPREAD_ENABLE = 0x00000001,
5552} DP_DTO_DS_DISABLE;
5553
5554/*
5555 * DS_HW_CAL_ENABLE enum
5556 */
5557
5558typedef enum DS_HW_CAL_ENABLE {
5559DS_HW_CAL_DIS = 0x00000000,
5560DS_HW_CAL_EN = 0x00000001,
5561} DS_HW_CAL_ENABLE;
5562
5563/*
5564 * DS_REF_SRC enum
5565 */
5566
5567typedef enum DS_REF_SRC {
5568DS_REF_IS_XTALIN = 0x00000000,
5569DS_REF_IS_EXT_GENLOCK = 0x00000001,
5570DS_REF_IS_PCIE = 0x00000002,
5571} DS_REF_SRC;
5572
5573/*
5574 * DVO_ENABLE_RST enum
5575 */
5576
5577typedef enum DVO_ENABLE_RST {
5578DVO_ENABLE_RST_DISABLE = 0x00000000,
5579DVO_ENABLE_RST_ENABLE = 0x00000001,
5580} DVO_ENABLE_RST;
5581
5582/*
5583 * ENABLE enum
5584 */
5585
5586typedef enum ENABLE {
5587DISABLE_THE_FEATURE = 0x00000000,
5588ENABLE_THE_FEATURE = 0x00000001,
5589} ENABLE;
5590
5591/*
5592 * ENABLE_CLOCK enum
5593 */
5594
5595typedef enum ENABLE_CLOCK {
5596ENABLE_THE_REFCLK = 0x00000000,
5597ENABLE_THE_FUNC_CLOCK = 0x00000001,
5598} ENABLE_CLOCK;
5599
5600/*
5601 * FORCE_DISABLE_CLOCK enum
5602 */
5603
5604typedef enum FORCE_DISABLE_CLOCK {
5605NOT_FORCE_THE_CLOCK_DISABLED = 0x00000000,
5606FORCE_THE_CLOCK_DISABLED = 0x00000001,
5607} FORCE_DISABLE_CLOCK;
5608
5609/*
5610 * HDMICHARCLK_SRC_SEL enum
5611 */
5612
5613typedef enum HDMICHARCLK_SRC_SEL {
5614HDMICHARCLK_SRC_SEL_UNIPHYA = 0x00000000,
5615HDMICHARCLK_SRC_SEL_UNIPHYB = 0x00000001,
5616HDMICHARCLK_SRC_SEL_UNIPHYC = 0x00000002,
5617HDMICHARCLK_SRC_SEL_UNIPHYD = 0x00000003,
5618HDMICHARCLK_SRC_SEL_SRC_RESERVED = 0x00000004,
5619} HDMICHARCLK_SRC_SEL;
5620
5621/*
5622 * HDMISTREAMCLK_SRC_SEL enum
5623 */
5624
5625typedef enum HDMISTREAMCLK_SRC_SEL {
5626SEL_DTBCLK_P0 = 0x00000000,
5627SEL_DTBCLK_P1 = 0x00000001,
5628SEL_DTBCLK_P2 = 0x00000002,
5629SEL_DTBCLK_P3 = 0x00000003,
5630} HDMISTREAMCLK_SRC_SEL;
5631
5632/*
5633 * JITTER_REMOVE_DISABLE enum
5634 */
5635
5636typedef enum JITTER_REMOVE_DISABLE {
5637ENABLE_JITTER_REMOVAL = 0x00000000,
5638DISABLE_JITTER_REMOVAL = 0x00000001,
5639} JITTER_REMOVE_DISABLE;
5640
5641/*
5642 * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5643 */
5644
5645typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5646MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
5647MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001,
5648} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
5649
5650/*
5651 * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5652 */
5653
5654typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5655MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
5656MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001,
5657} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
5658
5659/*
5660 * OTG_ADD_PIXEL enum
5661 */
5662
5663typedef enum OTG_ADD_PIXEL {
5664OTG_ADD_PIXEL_NOOP = 0x00000000,
5665OTG_ADD_PIXEL_FORCE = 0x00000001,
5666} OTG_ADD_PIXEL;
5667
5668/*
5669 * OTG_DROP_PIXEL enum
5670 */
5671
5672typedef enum OTG_DROP_PIXEL {
5673OTG_DROP_PIXEL_NOOP = 0x00000000,
5674OTG_DROP_PIXEL_FORCE = 0x00000001,
5675} OTG_DROP_PIXEL;
5676
5677/*
5678 * PHYSYMCLK_FORCE_EN enum
5679 */
5680
5681typedef enum PHYSYMCLK_FORCE_EN {
5682PHYSYMCLK_FORCE_EN_DISABLE = 0x00000000,
5683PHYSYMCLK_FORCE_EN_ENABLE = 0x00000001,
5684} PHYSYMCLK_FORCE_EN;
5685
5686/*
5687 * PHYSYMCLK_FORCE_SRC_SEL enum
5688 */
5689
5690typedef enum PHYSYMCLK_FORCE_SRC_SEL {
5691PHYSYMCLK_FORCE_SRC_SYMCLK = 0x00000000,
5692PHYSYMCLK_FORCE_SRC_PHYD18CLK = 0x00000001,
5693PHYSYMCLK_FORCE_SRC_PHYD32CLK = 0x00000002,
5694} PHYSYMCLK_FORCE_SRC_SEL;
5695
5696/*
5697 * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
5698 */
5699
5700typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
5701PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000,
5702PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001,
5703PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002,
5704PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003,
5705PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 0x00000004,
5706} PIPE_PHYPLL_PIXEL_RATE_SOURCE;
5707
5708/*
5709 * PIPE_PIXEL_RATE_PLL_SOURCE enum
5710 */
5711
5712typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
5713PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000,
5714PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001,
5715} PIPE_PIXEL_RATE_PLL_SOURCE;
5716
5717/*
5718 * PIPE_PIXEL_RATE_SOURCE enum
5719 */
5720
5721typedef enum PIPE_PIXEL_RATE_SOURCE {
5722PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000,
5723PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001,
5724PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002,
5725} PIPE_PIXEL_RATE_SOURCE;
5726
5727/*
5728 * PLL_CFG_IF_SOFT_RESET enum
5729 */
5730
5731typedef enum PLL_CFG_IF_SOFT_RESET {
5732PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000,
5733PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001,
5734} PLL_CFG_IF_SOFT_RESET;
5735
5736/*
5737 * SYMCLK_FE_SRC enum
5738 */
5739
5740typedef enum SYMCLK_FE_SRC {
5741SYMCLK_FE_SRC_UNIPHYA = 0x00000000,
5742SYMCLK_FE_SRC_UNIPHYB = 0x00000001,
5743SYMCLK_FE_SRC_UNIPHYC = 0x00000002,
5744SYMCLK_FE_SRC_UNIPHYD = 0x00000003,
5745SYMCLK_FE_SRC_RESERVED = 0x00000004,
5746} SYMCLK_FE_SRC;
5747
5748/*
5749 * TEST_CLK_DIV_SEL enum
5750 */
5751
5752typedef enum TEST_CLK_DIV_SEL {
5753NO_DIV = 0x00000000,
5754DIV_2 = 0x00000001,
5755DIV_4 = 0x00000002,
5756DIV_8 = 0x00000003,
5757} TEST_CLK_DIV_SEL;
5758
5759/*
5760 * VSYNC_CNT_LATCH_MASK enum
5761 */
5762
5763typedef enum VSYNC_CNT_LATCH_MASK {
5764VSYNC_CNT_LATCH_MASK_0 = 0x00000000,
5765VSYNC_CNT_LATCH_MASK_1 = 0x00000001,
5766} VSYNC_CNT_LATCH_MASK;
5767
5768/*
5769 * VSYNC_CNT_RESET_SEL enum
5770 */
5771
5772typedef enum VSYNC_CNT_RESET_SEL {
5773VSYNC_CNT_RESET_SEL_0 = 0x00000000,
5774VSYNC_CNT_RESET_SEL_1 = 0x00000001,
5775} VSYNC_CNT_RESET_SEL;
5776
5777/*
5778 * XTAL_REF_CLOCK_SOURCE_SEL enum
5779 */
5780
5781typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
5782XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000,
5783XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 0x00000001,
5784} XTAL_REF_CLOCK_SOURCE_SEL;
5785
5786/*
5787 * XTAL_REF_SEL enum
5788 */
5789
5790typedef enum XTAL_REF_SEL {
5791XTAL_REF_SEL_1X = 0x00000000,
5792XTAL_REF_SEL_2X = 0x00000001,
5793} XTAL_REF_SEL;
5794
5795/*******************************************************
5796 * DP Enums
5797 *******************************************************/
5798
5799/*
5800 * DPHY_8B10B_CUR_DISP enum
5801 */
5802
5803typedef enum DPHY_8B10B_CUR_DISP {
5804DPHY_8B10B_CUR_DISP_ZERO = 0x00000000,
5805DPHY_8B10B_CUR_DISP_ONE = 0x00000001,
5806} DPHY_8B10B_CUR_DISP;
5807
5808/*
5809 * DPHY_8B10B_RESET enum
5810 */
5811
5812typedef enum DPHY_8B10B_RESET {
5813DPHY_8B10B_NOT_RESET = 0x00000000,
5814DPHY_8B10B_RESETET = 0x00000001,
5815} DPHY_8B10B_RESET;
5816
5817/*
5818 * DPHY_ATEST_SEL_LANE0 enum
5819 */
5820
5821typedef enum DPHY_ATEST_SEL_LANE0 {
5822DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000,
5823DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001,
5824} DPHY_ATEST_SEL_LANE0;
5825
5826/*
5827 * DPHY_ATEST_SEL_LANE1 enum
5828 */
5829
5830typedef enum DPHY_ATEST_SEL_LANE1 {
5831DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000,
5832DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001,
5833} DPHY_ATEST_SEL_LANE1;
5834
5835/*
5836 * DPHY_ATEST_SEL_LANE2 enum
5837 */
5838
5839typedef enum DPHY_ATEST_SEL_LANE2 {
5840DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000,
5841DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001,
5842} DPHY_ATEST_SEL_LANE2;
5843
5844/*
5845 * DPHY_ATEST_SEL_LANE3 enum
5846 */
5847
5848typedef enum DPHY_ATEST_SEL_LANE3 {
5849DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000,
5850DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001,
5851} DPHY_ATEST_SEL_LANE3;
5852
5853/*
5854 * DPHY_BYPASS enum
5855 */
5856
5857typedef enum DPHY_BYPASS {
5858DPHY_8B10B_OUTPUT = 0x00000000,
5859DPHY_DBG_OUTPUT = 0x00000001,
5860} DPHY_BYPASS;
5861
5862/*
5863 * DPHY_CRC_CONT_EN enum
5864 */
5865
5866typedef enum DPHY_CRC_CONT_EN {
5867DPHY_CRC_ONE_SHOT = 0x00000000,
5868DPHY_CRC_CONTINUOUS = 0x00000001,
5869} DPHY_CRC_CONT_EN;
5870
5871/*
5872 * DPHY_CRC_EN enum
5873 */
5874
5875typedef enum DPHY_CRC_EN {
5876DPHY_CRC_DISABLED = 0x00000000,
5877DPHY_CRC_ENABLED = 0x00000001,
5878} DPHY_CRC_EN;
5879
5880/*
5881 * DPHY_CRC_FIELD enum
5882 */
5883
5884typedef enum DPHY_CRC_FIELD {
5885DPHY_CRC_START_FROM_TOP_FIELD = 0x00000000,
5886DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x00000001,
5887} DPHY_CRC_FIELD;
5888
5889/*
5890 * DPHY_CRC_MST_PHASE_ERROR_ACK enum
5891 */
5892
5893typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
5894DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x00000000,
5895DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x00000001,
5896} DPHY_CRC_MST_PHASE_ERROR_ACK;
5897
5898/*
5899 * DPHY_CRC_SEL enum
5900 */
5901
5902typedef enum DPHY_CRC_SEL {
5903DPHY_CRC_LANE0_SELECTED = 0x00000000,
5904DPHY_CRC_LANE1_SELECTED = 0x00000001,
5905DPHY_CRC_LANE2_SELECTED = 0x00000002,
5906DPHY_CRC_LANE3_SELECTED = 0x00000003,
5907} DPHY_CRC_SEL;
5908
5909/*
5910 * DPHY_FEC_ENABLE enum
5911 */
5912
5913typedef enum DPHY_FEC_ENABLE {
5914DPHY_FEC_DISABLED = 0x00000000,
5915DPHY_FEC_ENABLED = 0x00000001,
5916} DPHY_FEC_ENABLE;
5917
5918/*
5919 * DPHY_FEC_READY enum
5920 */
5921
5922typedef enum DPHY_FEC_READY {
5923DPHY_FEC_READY_EN = 0x00000000,
5924DPHY_FEC_READY_DIS = 0x00000001,
5925} DPHY_FEC_READY;
5926
5927/*
5928 * DPHY_LOAD_BS_COUNT_START enum
5929 */
5930
5931typedef enum DPHY_LOAD_BS_COUNT_START {
5932DPHY_LOAD_BS_COUNT_STARTED = 0x00000000,
5933DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x00000001,
5934} DPHY_LOAD_BS_COUNT_START;
5935
5936/*
5937 * DPHY_PRBS_EN enum
5938 */
5939
5940typedef enum DPHY_PRBS_EN {
5941DPHY_PRBS_DISABLE = 0x00000000,
5942DPHY_PRBS_ENABLE = 0x00000001,
5943} DPHY_PRBS_EN;
5944
5945/*
5946 * DPHY_PRBS_SEL enum
5947 */
5948
5949typedef enum DPHY_PRBS_SEL {
5950DPHY_PRBS7_SELECTED = 0x00000000,
5951DPHY_PRBS23_SELECTED = 0x00000001,
5952DPHY_PRBS11_SELECTED = 0x00000002,
5953} DPHY_PRBS_SEL;
5954
5955/*
5956 * DPHY_RX_FAST_TRAINING_CAPABLE enum
5957 */
5958
5959typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
5960DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x00000000,
5961DPHY_FAST_TRAINING_CAPABLE = 0x00000001,
5962} DPHY_RX_FAST_TRAINING_CAPABLE;
5963
5964/*
5965 * DPHY_SKEW_BYPASS enum
5966 */
5967
5968typedef enum DPHY_SKEW_BYPASS {
5969DPHY_WITH_SKEW = 0x00000000,
5970DPHY_NO_SKEW = 0x00000001,
5971} DPHY_SKEW_BYPASS;
5972
5973/*
5974 * DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM enum
5975 */
5976
5977typedef enum DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM {
5978DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0x00000000,
5979DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 0x00000001,
5980} DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM;
5981
5982/*
5983 * DPHY_SW_FAST_TRAINING_START enum
5984 */
5985
5986typedef enum DPHY_SW_FAST_TRAINING_START {
5987DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x00000000,
5988DPHY_SW_FAST_TRAINING_STARTED = 0x00000001,
5989} DPHY_SW_FAST_TRAINING_START;
5990
5991/*
5992 * DPHY_TRAINING_PATTERN_SEL enum
5993 */
5994
5995typedef enum DPHY_TRAINING_PATTERN_SEL {
5996DPHY_TRAINING_PATTERN_1 = 0x00000000,
5997DPHY_TRAINING_PATTERN_2 = 0x00000001,
5998DPHY_TRAINING_PATTERN_3 = 0x00000002,
5999DPHY_TRAINING_PATTERN_4 = 0x00000003,
6000} DPHY_TRAINING_PATTERN_SEL;
6001
6002/*
6003 * DP_COMPONENT_DEPTH enum
6004 */
6005
6006typedef enum DP_COMPONENT_DEPTH {
6007DP_COMPONENT_DEPTH_6BPC = 0x00000000,
6008DP_COMPONENT_DEPTH_8BPC = 0x00000001,
6009DP_COMPONENT_DEPTH_10BPC = 0x00000002,
6010DP_COMPONENT_DEPTH_12BPC = 0x00000003,
6011DP_COMPONENT_DEPTH_16BPC = 0x00000004,
6012} DP_COMPONENT_DEPTH;
6013
6014/*
6015 * DP_COMPRESSED_PIXEL_FORMAT enum
6016 */
6017
6018typedef enum DP_COMPRESSED_PIXEL_FORMAT {
6019DP_DSC_444_S422 = 0x00000000,
6020DP_DSC_N422_N420 = 0x00000001,
6021} DP_COMPRESSED_PIXEL_FORMAT;
6022
6023/*
6024 * DP_DPHY_8B10B_EXT_DISP enum
6025 */
6026
6027typedef enum DP_DPHY_8B10B_EXT_DISP {
6028DP_DPHY_8B10B_EXT_DISP_ZERO = 0x00000000,
6029DP_DPHY_8B10B_EXT_DISP_ONE = 0x00000001,
6030} DP_DPHY_8B10B_EXT_DISP;
6031
6032/*
6033 * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
6034 */
6035
6036typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
6037DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x00000000,
6038DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x00000001,
6039} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
6040
6041/*
6042 * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
6043 */
6044
6045typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
6046DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x00000000,
6047DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x00000001,
6048} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
6049
6050/*
6051 * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
6052 */
6053
6054typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
6055DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0x00000000,
6056DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x00000001,
6057} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
6058
6059/*
6060 * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
6061 */
6062
6063typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
6064DP_DPHY_HBR2_PASS_THROUGH = 0x00000000,
6065DP_DPHY_HBR2_PATTERN_1 = 0x00000001,
6066DP_DPHY_HBR2_PATTERN_2_NEG = 0x00000002,
6067DP_DPHY_HBR2_PATTERN_3 = 0x00000003,
6068DP_DPHY_HBR2_PATTERN_2_POS = 0x00000006,
6069} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
6070
6071/*
6072 * DP_LINK_TRAINING_COMPLETE enum
6073 */
6074
6075typedef enum DP_LINK_TRAINING_COMPLETE {
6076DP_LINK_TRAINING_NOT_COMPLETE = 0x00000000,
6077DP_LINK_TRAINING_ALREADY_COMPLETE = 0x00000001,
6078} DP_LINK_TRAINING_COMPLETE;
6079
6080/*
6081 * DP_LINK_TRAINING_SWITCH_MODE enum
6082 */
6083
6084typedef enum DP_LINK_TRAINING_SWITCH_MODE {
6085DP_LINK_TRAINING_SWITCH_TO_IDLE = 0x00000000,
6086DP_LINK_TRAINING_SWITCH_TO_VIDEO = 0x00000001,
6087} DP_LINK_TRAINING_SWITCH_MODE;
6088
6089/*
6090 * DP_ML_PHY_SEQ_MODE enum
6091 */
6092
6093typedef enum DP_ML_PHY_SEQ_MODE {
6094DP_ML_PHY_SEQ_LINE_NUM = 0x00000000,
6095DP_ML_PHY_SEQ_IMMEDIATE = 0x00000001,
6096} DP_ML_PHY_SEQ_MODE;
6097
6098/*
6099 * DP_MSA_V_TIMING_OVERRIDE_EN enum
6100 */
6101
6102typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
6103MSA_V_TIMING_OVERRIDE_DISABLED = 0x00000000,
6104MSA_V_TIMING_OVERRIDE_ENABLED = 0x00000001,
6105} DP_MSA_V_TIMING_OVERRIDE_EN;
6106
6107/*
6108 * DP_MSE_BLANK_CODE enum
6109 */
6110
6111typedef enum DP_MSE_BLANK_CODE {
6112DP_MSE_BLANK_CODE_SF_FILLED = 0x00000000,
6113DP_MSE_BLANK_CODE_ZERO_FILLED = 0x00000001,
6114} DP_MSE_BLANK_CODE;
6115
6116/*
6117 * DP_MSE_LINK_LINE enum
6118 */
6119
6120typedef enum DP_MSE_LINK_LINE {
6121DP_MSE_LINK_LINE_32_MTP_LONG = 0x00000000,
6122DP_MSE_LINK_LINE_64_MTP_LONG = 0x00000001,
6123DP_MSE_LINK_LINE_128_MTP_LONG = 0x00000002,
6124DP_MSE_LINK_LINE_256_MTP_LONG = 0x00000003,
6125} DP_MSE_LINK_LINE;
6126
6127/*
6128 * DP_MSE_TIMESTAMP_MODE enum
6129 */
6130
6131typedef enum DP_MSE_TIMESTAMP_MODE {
6132DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x00000000,
6133DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x00000001,
6134} DP_MSE_TIMESTAMP_MODE;
6135
6136/*
6137 * DP_MSE_ZERO_ENCODER enum
6138 */
6139
6140typedef enum DP_MSE_ZERO_ENCODER {
6141DP_MSE_NOT_ZERO_FE_ENCODER = 0x00000000,
6142DP_MSE_ZERO_FE_ENCODER = 0x00000001,
6143} DP_MSE_ZERO_ENCODER;
6144
6145/*
6146 * DP_MSO_NUM_OF_SST_LINKS enum
6147 */
6148
6149typedef enum DP_MSO_NUM_OF_SST_LINKS {
6150DP_MSO_ONE_SSTLINK = 0x00000000,
6151DP_MSO_TWO_SSTLINK = 0x00000001,
6152DP_MSO_FOUR_SSTLINK = 0x00000002,
6153} DP_MSO_NUM_OF_SST_LINKS;
6154
6155/*
6156 * DP_PIXEL_ENCODING enum
6157 */
6158
6159typedef enum DP_PIXEL_ENCODING {
6160DP_PIXEL_ENCODING_RGB_YCBCR444 = 0x00000000,
6161DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
6162DP_PIXEL_ENCODING_YCBCR420 = 0x00000002,
6163DP_PIXEL_ENCODING_Y_ONLY = 0x00000003,
6164} DP_PIXEL_ENCODING;
6165
6166/*
6167 * DP_PIXEL_ENCODING_TYPE enum
6168 */
6169
6170typedef enum DP_PIXEL_ENCODING_TYPE {
6171DP_PIXEL_ENCODING_UNCOMPRESSED = 0x00000000,
6172DP_PIXEL_ENCODING_COMPRESSED = 0x00000001,
6173} DP_PIXEL_ENCODING_TYPE;
6174
6175/*
6176 * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
6177 */
6178
6179typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
6180DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000,
6181DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001,
6182} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
6183
6184/*
6185 * DP_SEC_ASP_PRIORITY enum
6186 */
6187
6188typedef enum DP_SEC_ASP_PRIORITY {
6189DP_SEC_ASP_LOW_PRIORITY = 0x00000000,
6190DP_SEC_ASP_HIGH_PRIORITY = 0x00000001,
6191} DP_SEC_ASP_PRIORITY;
6192
6193/*
6194 * DP_SEC_AUDIO_MUTE enum
6195 */
6196
6197typedef enum DP_SEC_AUDIO_MUTE {
6198DP_SEC_AUDIO_MUTE_HW_CTRL = 0x00000000,
6199DP_SEC_AUDIO_MUTE_SW_CTRL = 0x00000001,
6200} DP_SEC_AUDIO_MUTE;
6201
6202/*
6203 * DP_SEC_COLLISION_ACK enum
6204 */
6205
6206typedef enum DP_SEC_COLLISION_ACK {
6207DP_SEC_COLLISION_ACK_NO_EFFECT = 0x00000000,
6208DP_SEC_COLLISION_ACK_CLR_FLAG = 0x00000001,
6209} DP_SEC_COLLISION_ACK;
6210
6211/*
6212 * DP_SEC_GSP0_PRIORITY enum
6213 */
6214
6215typedef enum DP_SEC_GSP0_PRIORITY {
6216SEC_GSP0_PRIORITY_LOW = 0x00000000,
6217SEC_GSP0_PRIORITY_HIGH = 0x00000001,
6218} DP_SEC_GSP0_PRIORITY;
6219
6220/*
6221 * DP_SEC_GSP_SEND enum
6222 */
6223
6224typedef enum DP_SEC_GSP_SEND {
6225NOT_SENT = 0x00000000,
6226FORCE_SENT = 0x00000001,
6227} DP_SEC_GSP_SEND;
6228
6229/*
6230 * DP_SEC_GSP_SEND_ANY_LINE enum
6231 */
6232
6233typedef enum DP_SEC_GSP_SEND_ANY_LINE {
6234SEND_AT_LINK_NUMBER = 0x00000000,
6235SEND_AT_EARLIEST_TIME = 0x00000001,
6236} DP_SEC_GSP_SEND_ANY_LINE;
6237
6238/*
6239 * DP_SEC_GSP_SEND_PPS enum
6240 */
6241
6242typedef enum DP_SEC_GSP_SEND_PPS {
6243SEND_NORMAL_PACKET = 0x00000000,
6244SEND_PPS_PACKET = 0x00000001,
6245} DP_SEC_GSP_SEND_PPS;
6246
6247/*
6248 * DP_SEC_LINE_REFERENCE enum
6249 */
6250
6251typedef enum DP_SEC_LINE_REFERENCE {
6252REFER_TO_DP_SOF = 0x00000000,
6253REFER_TO_OTG_SOF = 0x00000001,
6254} DP_SEC_LINE_REFERENCE;
6255
6256/*
6257 * DP_SEC_TIMESTAMP_MODE enum
6258 */
6259
6260typedef enum DP_SEC_TIMESTAMP_MODE {
6261DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x00000000,
6262DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x00000001,
6263} DP_SEC_TIMESTAMP_MODE;
6264
6265/*
6266 * DP_STEER_OUTPUT_PIXEL_PER_CYCLE enum
6267 */
6268
6269typedef enum DP_STEER_OUTPUT_PIXEL_PER_CYCLE {
6270DP_STEER_1_PIX_PER_CYCLE = 0x00000000,
6271DP_STEER_2_PIX_PER_CYCLE = 0x00000001,
6272DP_STEER_4_PIX_PER_CYCLE = 0x00000002,
6273DP_STEER_8_PIX_PER_CYCLE = 0x00000003,
6274} DP_STEER_OUTPUT_PIXEL_PER_CYCLE;
6275
6276/*
6277 * DP_STEER_OVERFLOW_ACK enum
6278 */
6279
6280typedef enum DP_STEER_OVERFLOW_ACK {
6281DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
6282DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
6283} DP_STEER_OVERFLOW_ACK;
6284
6285/*
6286 * DP_STEER_OVERFLOW_MASK enum
6287 */
6288
6289typedef enum DP_STEER_OVERFLOW_MASK {
6290DP_STEER_OVERFLOW_MASKED = 0x00000000,
6291DP_STEER_OVERFLOW_UNMASK = 0x00000001,
6292} DP_STEER_OVERFLOW_MASK;
6293
6294/*
6295 * DP_SYNC_POLARITY enum
6296 */
6297
6298typedef enum DP_SYNC_POLARITY {
6299DP_SYNC_POLARITY_ACTIVE_HIGH = 0x00000000,
6300DP_SYNC_POLARITY_ACTIVE_LOW = 0x00000001,
6301} DP_SYNC_POLARITY;
6302
6303/*
6304 * DP_TU_OVERFLOW_ACK enum
6305 */
6306
6307typedef enum DP_TU_OVERFLOW_ACK {
6308DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
6309DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
6310} DP_TU_OVERFLOW_ACK;
6311
6312/*
6313 * DP_UDI_LANES enum
6314 */
6315
6316typedef enum DP_UDI_LANES {
6317DP_UDI_1_LANE = 0x00000000,
6318DP_UDI_2_LANES = 0x00000001,
6319DP_UDI_LANES_RESERVED = 0x00000002,
6320DP_UDI_4_LANES = 0x00000003,
6321} DP_UDI_LANES;
6322
6323/*
6324 * DP_VID_ENHANCED_FRAME_MODE enum
6325 */
6326
6327typedef enum DP_VID_ENHANCED_FRAME_MODE {
6328VID_NORMAL_FRAME_MODE = 0x00000000,
6329VID_ENHANCED_MODE = 0x00000001,
6330} DP_VID_ENHANCED_FRAME_MODE;
6331
6332/*
6333 * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
6334 */
6335
6336typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
6337DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000,
6338DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x00000001,
6339} DP_VID_M_N_DOUBLE_BUFFER_MODE;
6340
6341/*
6342 * DP_VID_M_N_GEN_EN enum
6343 */
6344
6345typedef enum DP_VID_M_N_GEN_EN {
6346DP_VID_M_N_PROGRAMMED_VIA_REG = 0x00000000,
6347DP_VID_M_N_CALC_AUTO = 0x00000001,
6348} DP_VID_M_N_GEN_EN;
6349
6350/*
6351 * DP_VID_N_INTERVAL enum
6352 */
6353
6354typedef enum DP_VID_N_INTERVAL {
6355DP_VID_1X_Nvid = 0x00000000,
6356DP_VID_2X_Nvid = 0x00000001,
6357DP_VID_4X_Nvid = 0x00000002,
6358DP_VID_8X_Nvid = 0x00000003,
6359} DP_VID_N_INTERVAL;
6360
6361/*
6362 * DP_VID_STREAM_DISABLE_ACK enum
6363 */
6364
6365typedef enum DP_VID_STREAM_DISABLE_ACK {
6366ID_STREAM_DISABLE_NO_ACK = 0x00000000,
6367ID_STREAM_DISABLE_ACKED = 0x00000001,
6368} DP_VID_STREAM_DISABLE_ACK;
6369
6370/*
6371 * DP_VID_STREAM_DISABLE_MASK enum
6372 */
6373
6374typedef enum DP_VID_STREAM_DISABLE_MASK {
6375VID_STREAM_DISABLE_MASKED = 0x00000000,
6376VID_STREAM_DISABLE_UNMASK = 0x00000001,
6377} DP_VID_STREAM_DISABLE_MASK;
6378
6379/*
6380 * DP_VID_STREAM_DIS_DEFER enum
6381 */
6382
6383typedef enum DP_VID_STREAM_DIS_DEFER {
6384DP_VID_STREAM_DIS_NO_DEFER = 0x00000000,
6385DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x00000001,
6386DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x00000002,
6387} DP_VID_STREAM_DIS_DEFER;
6388
6389/*
6390 * DP_VID_VBID_FIELD_POL enum
6391 */
6392
6393typedef enum DP_VID_VBID_FIELD_POL {
6394DP_VID_VBID_FIELD_POL_NORMAL = 0x00000000,
6395DP_VID_VBID_FIELD_POL_INV = 0x00000001,
6396} DP_VID_VBID_FIELD_POL;
6397
6398/*
6399 * FEC_ACTIVE_STATUS enum
6400 */
6401
6402typedef enum FEC_ACTIVE_STATUS {
6403DPHY_FEC_NOT_ACTIVE = 0x00000000,
6404DPHY_FEC_ACTIVE = 0x00000001,
6405} FEC_ACTIVE_STATUS;
6406
6407/*******************************************************
6408 * DIG Enums
6409 *******************************************************/
6410
6411/*
6412 * DIG_BE_CNTL_HPD_SELECT enum
6413 */
6414
6415typedef enum DIG_BE_CNTL_HPD_SELECT {
6416DIG_BE_CNTL_HPD1 = 0x00000000,
6417DIG_BE_CNTL_HPD2 = 0x00000001,
6418DIG_BE_CNTL_HPD3 = 0x00000002,
6419DIG_BE_CNTL_HPD4 = 0x00000003,
6420DIG_BE_CNTL_NO_HPD = 0x00000004,
6421} DIG_BE_CNTL_HPD_SELECT;
6422
6423/*
6424 * DIG_BE_CNTL_MODE enum
6425 */
6426
6427typedef enum DIG_BE_CNTL_MODE {
6428DIG_BE_DP_SST_MODE = 0x00000000,
6429DIG_BE_RESERVED1 = 0x00000001,
6430DIG_BE_TMDS_DVI_MODE = 0x00000002,
6431DIG_BE_TMDS_HDMI_MODE = 0x00000003,
6432DIG_BE_RESERVED4 = 0x00000004,
6433DIG_BE_DP_MST_MODE = 0x00000005,
6434DIG_BE_RESERVED2 = 0x00000006,
6435DIG_BE_RESERVED3 = 0x00000007,
6436} DIG_BE_CNTL_MODE;
6437
6438/*
6439 * DIG_DIGITAL_BYPASS_ENABLE enum
6440 */
6441
6442typedef enum DIG_DIGITAL_BYPASS_ENABLE {
6443DIG_DIGITAL_BYPASS_OFF = 0x00000000,
6444DIG_DIGITAL_BYPASS_ON = 0x00000001,
6445} DIG_DIGITAL_BYPASS_ENABLE;
6446
6447/*
6448 * DIG_DIGITAL_BYPASS_SEL enum
6449 */
6450
6451typedef enum DIG_DIGITAL_BYPASS_SEL {
6452DIG_DIGITAL_BYPASS_SEL_BYPASS = 0x00000000,
6453DIG_DIGITAL_BYPASS_SEL_36BPP = 0x00000001,
6454DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 0x00000002,
6455DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 0x00000003,
6456DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 0x00000004,
6457DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 0x00000005,
6458DIG_DIGITAL_BYPASS_SEL_ALPHA = 0x00000006,
6459} DIG_DIGITAL_BYPASS_SEL;
6460
6461/*
6462 * DIG_FE_CNTL_SOURCE_SELECT enum
6463 */
6464
6465typedef enum DIG_FE_CNTL_SOURCE_SELECT {
6466DIG_FE_SOURCE_FROM_OTG0 = 0x00000000,
6467DIG_FE_SOURCE_FROM_OTG1 = 0x00000001,
6468DIG_FE_SOURCE_FROM_OTG2 = 0x00000002,
6469DIG_FE_SOURCE_FROM_OTG3 = 0x00000003,
6470DIG_FE_SOURCE_RESERVED = 0x00000004,
6471} DIG_FE_CNTL_SOURCE_SELECT;
6472
6473/*
6474 * DIG_FE_CNTL_STEREOSYNC_SELECT enum
6475 */
6476
6477typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
6478DIG_FE_STEREOSYNC_FROM_OTG0 = 0x00000000,
6479DIG_FE_STEREOSYNC_FROM_OTG1 = 0x00000001,
6480DIG_FE_STEREOSYNC_FROM_OTG2 = 0x00000002,
6481DIG_FE_STEREOSYNC_FROM_OTG3 = 0x00000003,
6482DIG_FE_STEREOSYNC_RESERVED = 0x00000004,
6483} DIG_FE_CNTL_STEREOSYNC_SELECT;
6484
6485/*
6486 * DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX enum
6487 */
6488
6489typedef enum DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX {
6490DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x00000000,
6491DIG_FIFO_FORCE_RECOMP_MINMAX = 0x00000001,
6492} DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX;
6493
6494/*
6495 * DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL enum
6496 */
6497
6498typedef enum DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL {
6499DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000000,
6500DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x00000001,
6501} DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL;
6502
6503/*
6504 * DIG_FIFO_FORCE_RECAL_AVERAGE enum
6505 */
6506
6507typedef enum DIG_FIFO_FORCE_RECAL_AVERAGE {
6508DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x00000000,
6509DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x00000001,
6510} DIG_FIFO_FORCE_RECAL_AVERAGE;
6511
6512/*
6513 * DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE enum
6514 */
6515
6516typedef enum DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE {
6517DIG_FIFO_1_PIX_PER_CYCLE = 0x00000000,
6518DIG_FIFO_2_PIX_PER_CYCLE = 0x00000001,
6519DIG_FIFO_4_PIX_PER_CYCLE = 0x00000002,
6520DIG_FIFO_8_PIX_PER_CYCLE = 0x00000003,
6521} DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE;
6522
6523/*
6524 * DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR enum
6525 */
6526
6527typedef enum DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR {
6528DIG_FIFO_NO_ERROR_OCCURRED = 0x00000000,
6529DIG_FIFO_UNDERFLOW_OCCURRED = 0x00000001,
6530DIG_FIFO_OVERFLOW_OCCURRED = 0x00000002,
6531} DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR;
6532
6533/*
6534 * DIG_FIFO_READ_CLOCK_SRC enum
6535 */
6536
6537typedef enum DIG_FIFO_READ_CLOCK_SRC {
6538DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x00000000,
6539DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001,
6540} DIG_FIFO_READ_CLOCK_SRC;
6541
6542/*
6543 * DIG_MODE enum
6544 */
6545
6546typedef enum DIG_MODE {
6547DP_SST_MODE = 0x00000000,
6548RESERVED1 = 0x00000001,
6549TMDS_DVI_MODE = 0x00000002,
6550TMDS_HDMI_MODE = 0x00000003,
6551RESERVED4 = 0x00000004,
6552DP_MST_MODE = 0x00000005,
6553RESERVED2 = 0x00000006,
6554RESERVED3 = 0x00000007,
6555} DIG_MODE;
6556
6557/*
6558 * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
6559 */
6560
6561typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
6562DIG_OUTPUT_CRC_ON_LINK0 = 0x00000000,
6563DIG_OUTPUT_CRC_ON_LINK1 = 0x00000001,
6564} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
6565
6566/*
6567 * DIG_OUTPUT_CRC_DATA_SEL enum
6568 */
6569
6570typedef enum DIG_OUTPUT_CRC_DATA_SEL {
6571DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x00000000,
6572DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x00000001,
6573DIG_OUTPUT_CRC_FOR_VBI = 0x00000002,
6574DIG_OUTPUT_CRC_FOR_AUDIO = 0x00000003,
6575} DIG_OUTPUT_CRC_DATA_SEL;
6576
6577/*
6578 * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
6579 */
6580
6581typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
6582DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000,
6583DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x00000001,
6584} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
6585
6586/*
6587 * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
6588 */
6589
6590typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
6591DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x00000000,
6592DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001,
6593} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
6594
6595/*
6596 * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
6597 */
6598
6599typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
6600DIG_10BIT_TEST_PATTERN = 0x00000000,
6601DIG_ALTERNATING_TEST_PATTERN = 0x00000001,
6602} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
6603
6604/*
6605 * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
6606 */
6607
6608typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
6609DIG_TEST_PATTERN_NORMAL = 0x00000000,
6610DIG_TEST_PATTERN_RANDOM = 0x00000001,
6611} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
6612
6613/*
6614 * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
6615 */
6616
6617typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
6618DIG_RANDOM_PATTERN_ENABLED = 0x00000000,
6619DIG_RANDOM_PATTERN_RESETED = 0x00000001,
6620} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
6621
6622/*
6623 * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
6624 */
6625
6626typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
6627DIG_IN_NORMAL_OPERATION = 0x00000000,
6628DIG_IN_DEBUG_MODE = 0x00000001,
6629} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
6630
6631/*
6632 * HDMI_ACP_SEND enum
6633 */
6634
6635typedef enum HDMI_ACP_SEND {
6636HDMI_ACP_NOT_SEND = 0x00000000,
6637HDMI_ACP_PKT_SEND = 0x00000001,
6638} HDMI_ACP_SEND;
6639
6640/*
6641 * HDMI_ACR_AUDIO_PRIORITY enum
6642 */
6643
6644typedef enum HDMI_ACR_AUDIO_PRIORITY {
6645HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000,
6646HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001,
6647} HDMI_ACR_AUDIO_PRIORITY;
6648
6649/*
6650 * HDMI_ACR_CONT enum
6651 */
6652
6653typedef enum HDMI_ACR_CONT {
6654HDMI_ACR_CONT_DISABLE = 0x00000000,
6655HDMI_ACR_CONT_ENABLE = 0x00000001,
6656} HDMI_ACR_CONT;
6657
6658/*
6659 * HDMI_ACR_N_MULTIPLE enum
6660 */
6661
6662typedef enum HDMI_ACR_N_MULTIPLE {
6663HDMI_ACR_0_MULTIPLE_RESERVED = 0x00000000,
6664HDMI_ACR_1_MULTIPLE = 0x00000001,
6665HDMI_ACR_2_MULTIPLE = 0x00000002,
6666HDMI_ACR_3_MULTIPLE_RESERVED = 0x00000003,
6667HDMI_ACR_4_MULTIPLE = 0x00000004,
6668HDMI_ACR_5_MULTIPLE_RESERVED = 0x00000005,
6669HDMI_ACR_6_MULTIPLE_RESERVED = 0x00000006,
6670HDMI_ACR_7_MULTIPLE_RESERVED = 0x00000007,
6671} HDMI_ACR_N_MULTIPLE;
6672
6673/*
6674 * HDMI_ACR_SELECT enum
6675 */
6676
6677typedef enum HDMI_ACR_SELECT {
6678HDMI_ACR_SELECT_HW = 0x00000000,
6679HDMI_ACR_SELECT_32K = 0x00000001,
6680HDMI_ACR_SELECT_44K = 0x00000002,
6681HDMI_ACR_SELECT_48K = 0x00000003,
6682} HDMI_ACR_SELECT;
6683
6684/*
6685 * HDMI_ACR_SEND enum
6686 */
6687
6688typedef enum HDMI_ACR_SEND {
6689HDMI_ACR_NOT_SEND = 0x00000000,
6690HDMI_ACR_PKT_SEND = 0x00000001,
6691} HDMI_ACR_SEND;
6692
6693/*
6694 * HDMI_ACR_SOURCE enum
6695 */
6696
6697typedef enum HDMI_ACR_SOURCE {
6698HDMI_ACR_SOURCE_HW = 0x00000000,
6699HDMI_ACR_SOURCE_SW = 0x00000001,
6700} HDMI_ACR_SOURCE;
6701
6702/*
6703 * HDMI_AUDIO_DELAY_EN enum
6704 */
6705
6706typedef enum HDMI_AUDIO_DELAY_EN {
6707HDMI_AUDIO_DELAY_DISABLE = 0x00000000,
6708HDMI_AUDIO_DELAY_58CLK = 0x00000001,
6709HDMI_AUDIO_DELAY_56CLK = 0x00000002,
6710HDMI_AUDIO_DELAY_RESERVED = 0x00000003,
6711} HDMI_AUDIO_DELAY_EN;
6712
6713/*
6714 * HDMI_AUDIO_INFO_CONT enum
6715 */
6716
6717typedef enum HDMI_AUDIO_INFO_CONT {
6718HDMI_AUDIO_INFO_CONT_DISABLE = 0x00000000,
6719HDMI_AUDIO_INFO_CONT_ENABLE = 0x00000001,
6720} HDMI_AUDIO_INFO_CONT;
6721
6722/*
6723 * HDMI_AUDIO_INFO_SEND enum
6724 */
6725
6726typedef enum HDMI_AUDIO_INFO_SEND {
6727HDMI_AUDIO_INFO_NOT_SEND = 0x00000000,
6728HDMI_AUDIO_INFO_PKT_SEND = 0x00000001,
6729} HDMI_AUDIO_INFO_SEND;
6730
6731/*
6732 * HDMI_CLOCK_CHANNEL_RATE enum
6733 */
6734
6735typedef enum HDMI_CLOCK_CHANNEL_RATE {
6736HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000,
6737HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001,
6738} HDMI_CLOCK_CHANNEL_RATE;
6739
6740/*
6741 * HDMI_DATA_SCRAMBLE_EN enum
6742 */
6743
6744typedef enum HDMI_DATA_SCRAMBLE_EN {
6745HDMI_DATA_SCRAMBLE_DISABLE = 0x00000000,
6746HDMI_DATA_SCRAMBLE_ENABLE = 0x00000001,
6747} HDMI_DATA_SCRAMBLE_EN;
6748
6749/*
6750 * HDMI_DEEP_COLOR_DEPTH enum
6751 */
6752
6753typedef enum HDMI_DEEP_COLOR_DEPTH {
6754HDMI_DEEP_COLOR_DEPTH_24BPP = 0x00000000,
6755HDMI_DEEP_COLOR_DEPTH_30BPP = 0x00000001,
6756HDMI_DEEP_COLOR_DEPTH_36BPP = 0x00000002,
6757HDMI_DEEP_COLOR_DEPTH_48BPP = 0x00000003,
6758} HDMI_DEEP_COLOR_DEPTH;
6759
6760/*
6761 * HDMI_DEFAULT_PAHSE enum
6762 */
6763
6764typedef enum HDMI_DEFAULT_PAHSE {
6765HDMI_DEFAULT_PHASE_IS_0 = 0x00000000,
6766HDMI_DEFAULT_PHASE_IS_1 = 0x00000001,
6767} HDMI_DEFAULT_PAHSE;
6768
6769/*
6770 * HDMI_ERROR_ACK enum
6771 */
6772
6773typedef enum HDMI_ERROR_ACK {
6774HDMI_ERROR_ACK_INT = 0x00000000,
6775HDMI_ERROR_NOT_ACK = 0x00000001,
6776} HDMI_ERROR_ACK;
6777
6778/*
6779 * HDMI_ERROR_MASK enum
6780 */
6781
6782typedef enum HDMI_ERROR_MASK {
6783HDMI_ERROR_MASK_INT = 0x00000000,
6784HDMI_ERROR_NOT_MASK = 0x00000001,
6785} HDMI_ERROR_MASK;
6786
6787/*
6788 * HDMI_GC_AVMUTE enum
6789 */
6790
6791typedef enum HDMI_GC_AVMUTE {
6792HDMI_GC_AVMUTE_SET = 0x00000000,
6793HDMI_GC_AVMUTE_UNSET = 0x00000001,
6794} HDMI_GC_AVMUTE;
6795
6796/*
6797 * HDMI_GC_AVMUTE_CONT enum
6798 */
6799
6800typedef enum HDMI_GC_AVMUTE_CONT {
6801HDMI_GC_AVMUTE_CONT_DISABLE = 0x00000000,
6802HDMI_GC_AVMUTE_CONT_ENABLE = 0x00000001,
6803} HDMI_GC_AVMUTE_CONT;
6804
6805/*
6806 * HDMI_GC_CONT enum
6807 */
6808
6809typedef enum HDMI_GC_CONT {
6810HDMI_GC_CONT_DISABLE = 0x00000000,
6811HDMI_GC_CONT_ENABLE = 0x00000001,
6812} HDMI_GC_CONT;
6813
6814/*
6815 * HDMI_GC_SEND enum
6816 */
6817
6818typedef enum HDMI_GC_SEND {
6819HDMI_GC_NOT_SEND = 0x00000000,
6820HDMI_GC_PKT_SEND = 0x00000001,
6821} HDMI_GC_SEND;
6822
6823/*
6824 * HDMI_GENERIC_CONT enum
6825 */
6826
6827typedef enum HDMI_GENERIC_CONT {
6828HDMI_GENERIC_CONT_DISABLE = 0x00000000,
6829HDMI_GENERIC_CONT_ENABLE = 0x00000001,
6830} HDMI_GENERIC_CONT;
6831
6832/*
6833 * HDMI_GENERIC_SEND enum
6834 */
6835
6836typedef enum HDMI_GENERIC_SEND {
6837HDMI_GENERIC_NOT_SEND = 0x00000000,
6838HDMI_GENERIC_PKT_SEND = 0x00000001,
6839} HDMI_GENERIC_SEND;
6840
6841/*
6842 * HDMI_ISRC_CONT enum
6843 */
6844
6845typedef enum HDMI_ISRC_CONT {
6846HDMI_ISRC_CONT_DISABLE = 0x00000000,
6847HDMI_ISRC_CONT_ENABLE = 0x00000001,
6848} HDMI_ISRC_CONT;
6849
6850/*
6851 * HDMI_ISRC_SEND enum
6852 */
6853
6854typedef enum HDMI_ISRC_SEND {
6855HDMI_ISRC_NOT_SEND = 0x00000000,
6856HDMI_ISRC_PKT_SEND = 0x00000001,
6857} HDMI_ISRC_SEND;
6858
6859/*
6860 * HDMI_KEEPOUT_MODE enum
6861 */
6862
6863typedef enum HDMI_KEEPOUT_MODE {
6864HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x00000000,
6865HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x00000001,
6866} HDMI_KEEPOUT_MODE;
6867
6868/*
6869 * HDMI_METADATA_ENABLE enum
6870 */
6871
6872typedef enum HDMI_METADATA_ENABLE {
6873HDMI_METADATA_NOT_SEND = 0x00000000,
6874HDMI_METADATA_PKT_SEND = 0x00000001,
6875} HDMI_METADATA_ENABLE;
6876
6877/*
6878 * HDMI_MPEG_INFO_CONT enum
6879 */
6880
6881typedef enum HDMI_MPEG_INFO_CONT {
6882HDMI_MPEG_INFO_CONT_DISABLE = 0x00000000,
6883HDMI_MPEG_INFO_CONT_ENABLE = 0x00000001,
6884} HDMI_MPEG_INFO_CONT;
6885
6886/*
6887 * HDMI_MPEG_INFO_SEND enum
6888 */
6889
6890typedef enum HDMI_MPEG_INFO_SEND {
6891HDMI_MPEG_INFO_NOT_SEND = 0x00000000,
6892HDMI_MPEG_INFO_PKT_SEND = 0x00000001,
6893} HDMI_MPEG_INFO_SEND;
6894
6895/*
6896 * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
6897 */
6898
6899typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
6900HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x00000000,
6901HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x00000001,
6902} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
6903
6904/*
6905 * HDMI_NULL_SEND enum
6906 */
6907
6908typedef enum HDMI_NULL_SEND {
6909HDMI_NULL_NOT_SEND = 0x00000000,
6910HDMI_NULL_PKT_SEND = 0x00000001,
6911} HDMI_NULL_SEND;
6912
6913/*
6914 * HDMI_PACKET_GEN_VERSION enum
6915 */
6916
6917typedef enum HDMI_PACKET_GEN_VERSION {
6918HDMI_PACKET_GEN_VERSION_OLD = 0x00000000,
6919HDMI_PACKET_GEN_VERSION_NEW = 0x00000001,
6920} HDMI_PACKET_GEN_VERSION;
6921
6922/*
6923 * HDMI_PACKET_LINE_REFERENCE enum
6924 */
6925
6926typedef enum HDMI_PACKET_LINE_REFERENCE {
6927HDMI_PKT_LINE_REF_VSYNC = 0x00000000,
6928HDMI_PKT_LINE_REF_OTGSOF = 0x00000001,
6929} HDMI_PACKET_LINE_REFERENCE;
6930
6931/*
6932 * HDMI_PACKING_PHASE_OVERRIDE enum
6933 */
6934
6935typedef enum HDMI_PACKING_PHASE_OVERRIDE {
6936HDMI_PACKING_PHASE_SET_BY_HW = 0x00000000,
6937HDMI_PACKING_PHASE_SET_BY_SW = 0x00000001,
6938} HDMI_PACKING_PHASE_OVERRIDE;
6939
6940/*
6941 * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
6942 */
6943
6944typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
6945LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x00000000,
6946LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x00000001,
6947} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
6948
6949/*
6950 * TMDS_COLOR_FORMAT enum
6951 */
6952
6953typedef enum TMDS_COLOR_FORMAT {
6954TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000,
6955TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x00000001,
6956TMDS_COLOR_FORMAT_DUAL30BPP = 0x00000002,
6957TMDS_COLOR_FORMAT_RESERVED = 0x00000003,
6958} TMDS_COLOR_FORMAT;
6959
6960/*
6961 * TMDS_CTL0_DATA_INVERT enum
6962 */
6963
6964typedef enum TMDS_CTL0_DATA_INVERT {
6965TMDS_CTL0_DATA_NORMAL = 0x00000000,
6966TMDS_CTL0_DATA_INVERT_EN = 0x00000001,
6967} TMDS_CTL0_DATA_INVERT;
6968
6969/*
6970 * TMDS_CTL0_DATA_MODULATION enum
6971 */
6972
6973typedef enum TMDS_CTL0_DATA_MODULATION {
6974TMDS_CTL0_DATA_MODULATION_DISABLE = 0x00000000,
6975TMDS_CTL0_DATA_MODULATION_BIT0 = 0x00000001,
6976TMDS_CTL0_DATA_MODULATION_BIT1 = 0x00000002,
6977TMDS_CTL0_DATA_MODULATION_BIT2 = 0x00000003,
6978} TMDS_CTL0_DATA_MODULATION;
6979
6980/*
6981 * TMDS_CTL0_DATA_SEL enum
6982 */
6983
6984typedef enum TMDS_CTL0_DATA_SEL {
6985TMDS_CTL0_DATA_SEL0_RESERVED = 0x00000000,
6986TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
6987TMDS_CTL0_DATA_SEL2_VSYNC = 0x00000002,
6988TMDS_CTL0_DATA_SEL3_RESERVED = 0x00000003,
6989TMDS_CTL0_DATA_SEL4_HSYNC = 0x00000004,
6990TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x00000005,
6991TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x00000006,
6992TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x00000007,
6993} TMDS_CTL0_DATA_SEL;
6994
6995/*
6996 * TMDS_CTL0_PATTERN_OUT_EN enum
6997 */
6998
6999typedef enum TMDS_CTL0_PATTERN_OUT_EN {
7000TMDS_CTL0_PATTERN_OUT_DISABLE = 0x00000000,
7001TMDS_CTL0_PATTERN_OUT_ENABLE = 0x00000001,
7002} TMDS_CTL0_PATTERN_OUT_EN;
7003
7004/*
7005 * TMDS_CTL1_DATA_INVERT enum
7006 */
7007
7008typedef enum TMDS_CTL1_DATA_INVERT {
7009TMDS_CTL1_DATA_NORMAL = 0x00000000,
7010TMDS_CTL1_DATA_INVERT_EN = 0x00000001,
7011} TMDS_CTL1_DATA_INVERT;
7012
7013/*
7014 * TMDS_CTL1_DATA_MODULATION enum
7015 */
7016
7017typedef enum TMDS_CTL1_DATA_MODULATION {
7018TMDS_CTL1_DATA_MODULATION_DISABLE = 0x00000000,
7019TMDS_CTL1_DATA_MODULATION_BIT0 = 0x00000001,
7020TMDS_CTL1_DATA_MODULATION_BIT1 = 0x00000002,
7021TMDS_CTL1_DATA_MODULATION_BIT2 = 0x00000003,
7022} TMDS_CTL1_DATA_MODULATION;
7023
7024/*
7025 * TMDS_CTL1_DATA_SEL enum
7026 */
7027
7028typedef enum TMDS_CTL1_DATA_SEL {
7029TMDS_CTL1_DATA_SEL0_RESERVED = 0x00000000,
7030TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
7031TMDS_CTL1_DATA_SEL2_VSYNC = 0x00000002,
7032TMDS_CTL1_DATA_SEL3_RESERVED = 0x00000003,
7033TMDS_CTL1_DATA_SEL4_HSYNC = 0x00000004,
7034TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x00000005,
7035TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x00000006,
7036TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x00000007,
7037} TMDS_CTL1_DATA_SEL;
7038
7039/*
7040 * TMDS_CTL1_PATTERN_OUT_EN enum
7041 */
7042
7043typedef enum TMDS_CTL1_PATTERN_OUT_EN {
7044TMDS_CTL1_PATTERN_OUT_DISABLE = 0x00000000,
7045TMDS_CTL1_PATTERN_OUT_ENABLE = 0x00000001,
7046} TMDS_CTL1_PATTERN_OUT_EN;
7047
7048/*
7049 * TMDS_CTL2_DATA_INVERT enum
7050 */
7051
7052typedef enum TMDS_CTL2_DATA_INVERT {
7053TMDS_CTL2_DATA_NORMAL = 0x00000000,
7054TMDS_CTL2_DATA_INVERT_EN = 0x00000001,
7055} TMDS_CTL2_DATA_INVERT;
7056
7057/*
7058 * TMDS_CTL2_DATA_MODULATION enum
7059 */
7060
7061typedef enum TMDS_CTL2_DATA_MODULATION {
7062TMDS_CTL2_DATA_MODULATION_DISABLE = 0x00000000,
7063TMDS_CTL2_DATA_MODULATION_BIT0 = 0x00000001,
7064TMDS_CTL2_DATA_MODULATION_BIT1 = 0x00000002,
7065TMDS_CTL2_DATA_MODULATION_BIT2 = 0x00000003,
7066} TMDS_CTL2_DATA_MODULATION;
7067
7068/*
7069 * TMDS_CTL2_DATA_SEL enum
7070 */
7071
7072typedef enum TMDS_CTL2_DATA_SEL {
7073TMDS_CTL2_DATA_SEL0_RESERVED = 0x00000000,
7074TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
7075TMDS_CTL2_DATA_SEL2_VSYNC = 0x00000002,
7076TMDS_CTL2_DATA_SEL3_RESERVED = 0x00000003,
7077TMDS_CTL2_DATA_SEL4_HSYNC = 0x00000004,
7078TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x00000005,
7079TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x00000006,
7080TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x00000007,
7081} TMDS_CTL2_DATA_SEL;
7082
7083/*
7084 * TMDS_CTL2_PATTERN_OUT_EN enum
7085 */
7086
7087typedef enum TMDS_CTL2_PATTERN_OUT_EN {
7088TMDS_CTL2_PATTERN_OUT_DISABLE = 0x00000000,
7089TMDS_CTL2_PATTERN_OUT_ENABLE = 0x00000001,
7090} TMDS_CTL2_PATTERN_OUT_EN;
7091
7092/*
7093 * TMDS_CTL3_DATA_INVERT enum
7094 */
7095
7096typedef enum TMDS_CTL3_DATA_INVERT {
7097TMDS_CTL3_DATA_NORMAL = 0x00000000,
7098TMDS_CTL3_DATA_INVERT_EN = 0x00000001,
7099} TMDS_CTL3_DATA_INVERT;
7100
7101/*
7102 * TMDS_CTL3_DATA_MODULATION enum
7103 */
7104
7105typedef enum TMDS_CTL3_DATA_MODULATION {
7106TMDS_CTL3_DATA_MODULATION_DISABLE = 0x00000000,
7107TMDS_CTL3_DATA_MODULATION_BIT0 = 0x00000001,
7108TMDS_CTL3_DATA_MODULATION_BIT1 = 0x00000002,
7109TMDS_CTL3_DATA_MODULATION_BIT2 = 0x00000003,
7110} TMDS_CTL3_DATA_MODULATION;
7111
7112/*
7113 * TMDS_CTL3_DATA_SEL enum
7114 */
7115
7116typedef enum TMDS_CTL3_DATA_SEL {
7117TMDS_CTL3_DATA_SEL0_RESERVED = 0x00000000,
7118TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
7119TMDS_CTL3_DATA_SEL2_VSYNC = 0x00000002,
7120TMDS_CTL3_DATA_SEL3_RESERVED = 0x00000003,
7121TMDS_CTL3_DATA_SEL4_HSYNC = 0x00000004,
7122TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x00000005,
7123TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x00000006,
7124TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x00000007,
7125} TMDS_CTL3_DATA_SEL;
7126
7127/*
7128 * TMDS_CTL3_PATTERN_OUT_EN enum
7129 */
7130
7131typedef enum TMDS_CTL3_PATTERN_OUT_EN {
7132TMDS_CTL3_PATTERN_OUT_DISABLE = 0x00000000,
7133TMDS_CTL3_PATTERN_OUT_ENABLE = 0x00000001,
7134} TMDS_CTL3_PATTERN_OUT_EN;
7135
7136/*
7137 * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
7138 */
7139
7140typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
7141TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x00000000,
7142TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x00000001,
7143} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
7144
7145/*
7146 * TMDS_PIXEL_ENCODING enum
7147 */
7148
7149typedef enum TMDS_PIXEL_ENCODING {
7150TMDS_PIXEL_ENCODING_444_OR_420 = 0x00000000,
7151TMDS_PIXEL_ENCODING_422 = 0x00000001,
7152} TMDS_PIXEL_ENCODING;
7153
7154/*
7155 * TMDS_REG_TEST_OUTPUTA_CNTLA enum
7156 */
7157
7158typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
7159TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x00000000,
7160TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x00000001,
7161TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x00000002,
7162TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x00000003,
7163} TMDS_REG_TEST_OUTPUTA_CNTLA;
7164
7165/*
7166 * TMDS_REG_TEST_OUTPUTB_CNTLB enum
7167 */
7168
7169typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
7170TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x00000000,
7171TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x00000001,
7172TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x00000002,
7173TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x00000003,
7174} TMDS_REG_TEST_OUTPUTB_CNTLB;
7175
7176/*
7177 * TMDS_STEREOSYNC_CTL_SEL_REG enum
7178 */
7179
7180typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
7181TMDS_STEREOSYNC_CTL0 = 0x00000000,
7182TMDS_STEREOSYNC_CTL1 = 0x00000001,
7183TMDS_STEREOSYNC_CTL2 = 0x00000002,
7184TMDS_STEREOSYNC_CTL3 = 0x00000003,
7185} TMDS_STEREOSYNC_CTL_SEL_REG;
7186
7187/*
7188 * TMDS_SYNC_PHASE enum
7189 */
7190
7191typedef enum TMDS_SYNC_PHASE {
7192TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000,
7193TMDS_SYNC_PHASE_ON_FRAME_START = 0x00000001,
7194} TMDS_SYNC_PHASE;
7195
7196/*
7197 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
7198 */
7199
7200typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
7201TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x00000000,
7202TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x00000001,
7203} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
7204
7205/*
7206 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
7207 */
7208
7209typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
7210TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x00000000,
7211TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x00000001,
7212} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
7213
7214/*
7215 * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
7216 */
7217
7218typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
7219TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x00000000,
7220TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x00000001,
7221} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
7222
7223/*
7224 * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
7225 */
7226
7227typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
7228TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x00000000,
7229TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x00000001,
7230} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
7231
7232/*
7233 * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
7234 */
7235
7236typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
7237TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x00000000,
7238TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x00000001,
7239} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
7240
7241/*
7242 * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
7243 */
7244
7245typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
7246TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x00000000,
7247TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 0x00000001,
7248TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x00000002,
7249TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x00000003,
7250} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
7251
7252/*
7253 * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
7254 */
7255
7256typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
7257TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x00000000,
7258TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x00000001,
7259} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
7260
7261/*
7262 * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
7263 */
7264
7265typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
7266TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x00000000,
7267TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x00000001,
7268} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
7269
7270/*
7271 * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
7272 */
7273
7274typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
7275TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x00000000,
7276TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x00000001,
7277} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
7278
7279/*
7280 * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
7281 */
7282
7283typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
7284TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x00000000,
7285TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x00000001,
7286} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
7287
7288/*
7289 * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
7290 */
7291
7292typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
7293TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x00000000,
7294TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x00000001,
7295} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
7296
7297/*
7298 * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
7299 */
7300
7301typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
7302TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
7303TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x00000001,
7304} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
7305
7306/*
7307 * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
7308 */
7309
7310typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
7311TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
7312TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x00000001,
7313} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
7314
7315/*******************************************************
7316 * DOUT_I2C Enums
7317 *******************************************************/
7318
7319/*
7320 * DOUT_I2C_ACK enum
7321 */
7322
7323typedef enum DOUT_I2C_ACK {
7324DOUT_I2C_NO_ACK = 0x00000000,
7325DOUT_I2C_ACK_TO_CLEAN = 0x00000001,
7326} DOUT_I2C_ACK;
7327
7328/*
7329 * DOUT_I2C_ARBITRATION_ABORT_XFER enum
7330 */
7331
7332typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
7333DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000,
7334DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x00000001,
7335} DOUT_I2C_ARBITRATION_ABORT_XFER;
7336
7337/*
7338 * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
7339 */
7340
7341typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
7342DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000,
7343DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x00000001,
7344} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
7345
7346/*
7347 * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
7348 */
7349
7350typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
7351DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x00000000,
7352DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x00000001,
7353} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
7354
7355/*
7356 * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
7357 */
7358
7359typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
7360DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x00000000,
7361DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x00000001,
7362DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002,
7363DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003,
7364} DOUT_I2C_ARBITRATION_SW_PRIORITY;
7365
7366/*
7367 * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
7368 */
7369
7370typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
7371DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000,
7372DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x00000001,
7373} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
7374
7375/*
7376 * DOUT_I2C_CONTROL_DBG_REF_SEL enum
7377 */
7378
7379typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
7380DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x00000000,
7381DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x00000001,
7382} DOUT_I2C_CONTROL_DBG_REF_SEL;
7383
7384/*
7385 * DOUT_I2C_CONTROL_DDC_SELECT enum
7386 */
7387
7388typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
7389DOUT_I2C_CONTROL_SELECT_DDC1 = 0x00000000,
7390DOUT_I2C_CONTROL_SELECT_DDC2 = 0x00000001,
7391DOUT_I2C_CONTROL_SELECT_DDC3 = 0x00000002,
7392DOUT_I2C_CONTROL_SELECT_DDC4 = 0x00000003,
7393DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x00000004,
7394} DOUT_I2C_CONTROL_DDC_SELECT;
7395
7396/*
7397 * DOUT_I2C_CONTROL_GO enum
7398 */
7399
7400typedef enum DOUT_I2C_CONTROL_GO {
7401DOUT_I2C_CONTROL_STOP_TRANSFER = 0x00000000,
7402DOUT_I2C_CONTROL_START_TRANSFER = 0x00000001,
7403} DOUT_I2C_CONTROL_GO;
7404
7405/*
7406 * DOUT_I2C_CONTROL_SEND_RESET enum
7407 */
7408
7409typedef enum DOUT_I2C_CONTROL_SEND_RESET {
7410DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x00000000,
7411DOUT_I2C_CONTROL__SEND_RESET = 0x00000001,
7412} DOUT_I2C_CONTROL_SEND_RESET;
7413
7414/*
7415 * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum
7416 */
7417
7418typedef enum DOUT_I2C_CONTROL_SEND_RESET_LENGTH {
7419DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0x00000000,
7420DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 0x00000001,
7421} DOUT_I2C_CONTROL_SEND_RESET_LENGTH;
7422
7423/*
7424 * DOUT_I2C_CONTROL_SOFT_RESET enum
7425 */
7426
7427typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
7428DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000,
7429DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x00000001,
7430} DOUT_I2C_CONTROL_SOFT_RESET;
7431
7432/*
7433 * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
7434 */
7435
7436typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
7437DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x00000000,
7438DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x00000001,
7439} DOUT_I2C_CONTROL_SW_STATUS_RESET;
7440
7441/*
7442 * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
7443 */
7444
7445typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
7446DOUT_I2C_CONTROL_TRANS0 = 0x00000000,
7447DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x00000001,
7448DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x00000002,
7449DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x00000003,
7450} DOUT_I2C_CONTROL_TRANSACTION_COUNT;
7451
7452/*
7453 * DOUT_I2C_DATA_INDEX_WRITE enum
7454 */
7455
7456typedef enum DOUT_I2C_DATA_INDEX_WRITE {
7457DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x00000000,
7458DOUT_I2C_DATA__INDEX_WRITE = 0x00000001,
7459} DOUT_I2C_DATA_INDEX_WRITE;
7460
7461/*
7462 * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
7463 */
7464
7465typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
7466DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
7467DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x00000001,
7468} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
7469
7470/*
7471 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
7472 */
7473
7474typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
7475DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
7476DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x00000001,
7477} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
7478
7479/*
7480 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
7481 */
7482
7483typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
7484DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x00000000,
7485DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x00000001,
7486} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
7487
7488/*
7489 * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
7490 */
7491
7492typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
7493DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x00000000,
7494DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x00000001,
7495} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
7496
7497/*
7498 * DOUT_I2C_DDC_SPEED_THRESHOLD enum
7499 */
7500
7501typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
7502DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x00000000,
7503DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 0x00000001,
7504DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 0x00000002,
7505DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 0x00000003,
7506} DOUT_I2C_DDC_SPEED_THRESHOLD;
7507
7508/*
7509 * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
7510 */
7511
7512typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
7513DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000,
7514DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000001,
7515} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
7516
7517/*
7518 * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
7519 */
7520
7521typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
7522DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x00000000,
7523DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x00000001,
7524} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
7525
7526/*
7527 * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
7528 */
7529
7530typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
7531DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x00000000,
7532DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x00000001,
7533} DOUT_I2C_TRANSACTION_STOP_ON_NACK;
7534
7535/*******************************************************
7536 * DIO_MISC Enums
7537 *******************************************************/
7538
7539/*
7540 * CLOCK_GATING_EN enum
7541 */
7542
7543typedef enum CLOCK_GATING_EN {
7544CLOCK_GATING_ENABLE = 0x00000000,
7545CLOCK_GATING_DISABLE = 0x00000001,
7546} CLOCK_GATING_EN;
7547
7548/*
7549 * DAC_MUX_SELECT enum
7550 */
7551
7552typedef enum DAC_MUX_SELECT {
7553DAC_MUX_SELECT_DACA = 0x00000000,
7554DAC_MUX_SELECT_DACB = 0x00000001,
7555} DAC_MUX_SELECT;
7556
7557/*
7558 * DIOMEM_PWR_DIS_CTRL enum
7559 */
7560
7561typedef enum DIOMEM_PWR_DIS_CTRL {
7562DIOMEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
7563DIOMEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
7564} DIOMEM_PWR_DIS_CTRL;
7565
7566/*
7567 * DIOMEM_PWR_FORCE_CTRL enum
7568 */
7569
7570typedef enum DIOMEM_PWR_FORCE_CTRL {
7571DIOMEM_NO_FORCE_REQUEST = 0x00000000,
7572DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
7573DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
7574DIOMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
7575} DIOMEM_PWR_FORCE_CTRL;
7576
7577/*
7578 * DIOMEM_PWR_FORCE_CTRL2 enum
7579 */
7580
7581typedef enum DIOMEM_PWR_FORCE_CTRL2 {
7582DIOMEM_NO_FORCE_REQ = 0x00000000,
7583DIOMEM_FORCE_LIGHT_SLEEP_REQ = 0x00000001,
7584} DIOMEM_PWR_FORCE_CTRL2;
7585
7586/*
7587 * DIOMEM_PWR_SEL_CTRL enum
7588 */
7589
7590typedef enum DIOMEM_PWR_SEL_CTRL {
7591DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
7592DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001,
7593DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002,
7594} DIOMEM_PWR_SEL_CTRL;
7595
7596/*
7597 * DIOMEM_PWR_SEL_CTRL2 enum
7598 */
7599
7600typedef enum DIOMEM_PWR_SEL_CTRL2 {
7601DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0x00000000,
7602DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 0x00000001,
7603} DIOMEM_PWR_SEL_CTRL2;
7604
7605/*
7606 * DIO_CLOCK_GATING_DISABLE enum
7607 */
7608
7609typedef enum DIO_CLOCK_GATING_DISABLE {
7610DIO_CLOCK_GATING_EN = 0x00000000,
7611DIO_CLOCK_GATING_DIS = 0x00000001,
7612} DIO_CLOCK_GATING_DISABLE;
7613
7614/*
7615 * DIO_DBG_BLOCK_SEL enum
7616 */
7617
7618typedef enum DIO_DBG_BLOCK_SEL {
7619DIO_DBG_BLOCK_SEL_DIO = 0x00000000,
7620DIO_DBG_BLOCK_SEL_DIGFE_A = 0x0000000b,
7621DIO_DBG_BLOCK_SEL_DIGFE_B = 0x0000000c,
7622DIO_DBG_BLOCK_SEL_DIGFE_C = 0x0000000d,
7623DIO_DBG_BLOCK_SEL_DIGFE_D = 0x0000000e,
7624DIO_DBG_BLOCK_SEL_DIGA = 0x00000012,
7625DIO_DBG_BLOCK_SEL_DIGB = 0x00000013,
7626DIO_DBG_BLOCK_SEL_DIGC = 0x00000014,
7627DIO_DBG_BLOCK_SEL_DIGD = 0x00000015,
7628DIO_DBG_BLOCK_SEL_DPFE_A = 0x00000019,
7629DIO_DBG_BLOCK_SEL_DPFE_B = 0x0000001a,
7630DIO_DBG_BLOCK_SEL_DPFE_C = 0x0000001b,
7631DIO_DBG_BLOCK_SEL_DPFE_D = 0x0000001c,
7632DIO_DBG_BLOCK_SEL_DPA = 0x00000020,
7633DIO_DBG_BLOCK_SEL_DPB = 0x00000021,
7634DIO_DBG_BLOCK_SEL_DPC = 0x00000022,
7635DIO_DBG_BLOCK_SEL_DPD = 0x00000023,
7636DIO_DBG_BLOCK_SEL_AUX0 = 0x00000027,
7637DIO_DBG_BLOCK_SEL_AUX1 = 0x00000028,
7638DIO_DBG_BLOCK_SEL_AUX2 = 0x00000029,
7639DIO_DBG_BLOCK_SEL_AUX3 = 0x0000002a,
7640DIO_DBG_BLOCK_SEL_PERFMON_DIO = 0x0000002d,
7641DIO_DBG_BLOCK_SEL_RESERVED = 0x0000002e,
7642} DIO_DBG_BLOCK_SEL;
7643
7644/*
7645 * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum
7646 */
7647
7648typedef enum DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE {
7649DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x00000000,
7650DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x00000001,
7651} DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE;
7652
7653/*
7654 * ENUM_DIO_DCN_ACTIVE_STATUS enum
7655 */
7656
7657typedef enum ENUM_DIO_DCN_ACTIVE_STATUS {
7658ENUM_DCN_NOT_ACTIVE = 0x00000000,
7659ENUM_DCN_ACTIVE = 0x00000001,
7660} ENUM_DIO_DCN_ACTIVE_STATUS;
7661
7662/*
7663 * GENERIC_STEREOSYNC_SEL enum
7664 */
7665
7666typedef enum GENERIC_STEREOSYNC_SEL {
7667GENERIC_STEREOSYNC_SEL_D1 = 0x00000000,
7668GENERIC_STEREOSYNC_SEL_D2 = 0x00000001,
7669GENERIC_STEREOSYNC_SEL_D3 = 0x00000002,
7670GENERIC_STEREOSYNC_SEL_D4 = 0x00000003,
7671GENERIC_STEREOSYNC_SEL_RESERVED = 0x00000004,
7672} GENERIC_STEREOSYNC_SEL;
7673
7674/*
7675 * PM_ASSERT_RESET enum
7676 */
7677
7678typedef enum PM_ASSERT_RESET {
7679PM_ASSERT_RESET_0 = 0x00000000,
7680PM_ASSERT_RESET_1 = 0x00000001,
7681} PM_ASSERT_RESET;
7682
7683/*
7684 * SOFT_RESET enum
7685 */
7686
7687typedef enum SOFT_RESET {
7688SOFT_RESET_0 = 0x00000000,
7689SOFT_RESET_1 = 0x00000001,
7690} SOFT_RESET;
7691
7692/*
7693 * TMDS_MUX_SELECT enum
7694 */
7695
7696typedef enum TMDS_MUX_SELECT {
7697TMDS_MUX_SELECT_B = 0x00000000,
7698TMDS_MUX_SELECT_G = 0x00000001,
7699TMDS_MUX_SELECT_R = 0x00000002,
7700TMDS_MUX_SELECT_RESERVED = 0x00000003,
7701} TMDS_MUX_SELECT;
7702
7703/*******************************************************
7704 * DIG_STREAM_MAPPER Enums
7705 *******************************************************/
7706
7707/*
7708 * DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET enum
7709 */
7710
7711typedef enum DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET {
7712DIG_STREAM_MAPPER_LINK0 = 0x00000000,
7713DIG_STREAM_MAPPER_LINK1 = 0x00000001,
7714DIG_STREAM_MAPPER_LINK2 = 0x00000002,
7715DIG_STREAM_MAPPER_LINK3 = 0x00000003,
7716DIG_STREAM_MAPPER_LINK6 = 0x00000004,
7717} DIG_STREAM_MAPPER_DIG_STREAM_LINK_TARGET;
7718
7719/*******************************************************
7720 * DME Enums
7721 *******************************************************/
7722
7723/*
7724 * DME_MEM_POWER_STATE_ENUM enum
7725 */
7726
7727typedef enum DME_MEM_POWER_STATE_ENUM {
7728DME_MEM_POWER_STATE_ENUM_ON = 0x00000000,
7729DME_MEM_POWER_STATE_ENUM_LS = 0x00000001,
7730DME_MEM_POWER_STATE_ENUM_DS = 0x00000002,
7731DME_MEM_POWER_STATE_ENUM_SD = 0x00000003,
7732} DME_MEM_POWER_STATE_ENUM;
7733
7734/*
7735 * DME_MEM_PWR_DIS_CTRL enum
7736 */
7737
7738typedef enum DME_MEM_PWR_DIS_CTRL {
7739DME_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
7740DME_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
7741} DME_MEM_PWR_DIS_CTRL;
7742
7743/*
7744 * DME_MEM_PWR_FORCE_CTRL enum
7745 */
7746
7747typedef enum DME_MEM_PWR_FORCE_CTRL {
7748DME_MEM_NO_FORCE_REQUEST = 0x00000000,
7749DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
7750DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
7751DME_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
7752} DME_MEM_PWR_FORCE_CTRL;
7753
7754/*
7755 * METADATA_HUBP_SEL enum
7756 */
7757
7758typedef enum METADATA_HUBP_SEL {
7759METADATA_HUBP_SEL_0 = 0x00000000,
7760METADATA_HUBP_SEL_1 = 0x00000001,
7761METADATA_HUBP_SEL_2 = 0x00000002,
7762METADATA_HUBP_SEL_3 = 0x00000003,
7763METADATA_HUBP_SEL_RESERVED = 0x00000004,
7764} METADATA_HUBP_SEL;
7765
7766/*
7767 * METADATA_STREAM_TYPE_SEL enum
7768 */
7769
7770typedef enum METADATA_STREAM_TYPE_SEL {
7771METADATA_STREAM_DP = 0x00000000,
7772METADATA_STREAM_DVE = 0x00000001,
7773} METADATA_STREAM_TYPE_SEL;
7774
7775/*******************************************************
7776 * VPG Enums
7777 *******************************************************/
7778
7779/*
7780 * VPG_MEM_PWR_DIS_CTRL enum
7781 */
7782
7783typedef enum VPG_MEM_PWR_DIS_CTRL {
7784VPG_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
7785VPG_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
7786} VPG_MEM_PWR_DIS_CTRL;
7787
7788/*
7789 * VPG_MEM_PWR_FORCE_CTRL enum
7790 */
7791
7792typedef enum VPG_MEM_PWR_FORCE_CTRL {
7793VPG_MEM_NO_FORCE_REQ = 0x00000000,
7794VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 0x00000001,
7795} VPG_MEM_PWR_FORCE_CTRL;
7796
7797/*******************************************************
7798 * AFMT Enums
7799 *******************************************************/
7800
7801/*
7802 * AFMT_ACP_TYPE enum
7803 */
7804
7805typedef enum AFMT_ACP_TYPE {
7806ACP_TYPE_GENERIC_AUDIO = 0x00000000,
7807ACP_TYPE_ICE60958_AUDIO = 0x00000001,
7808ACP_TYPE_DVD_AUDIO = 0x00000002,
7809ACP_TYPE_SUPER_AUDIO_CD = 0x00000003,
7810} AFMT_ACP_TYPE;
7811
7812/*
7813 * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
7814 */
7815
7816typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
7817AFMT_AUDIO_CRC_CH0_SIG = 0x00000000,
7818AFMT_AUDIO_CRC_CH1_SIG = 0x00000001,
7819AFMT_AUDIO_CRC_CH2_SIG = 0x00000002,
7820AFMT_AUDIO_CRC_CH3_SIG = 0x00000003,
7821AFMT_AUDIO_CRC_CH4_SIG = 0x00000004,
7822AFMT_AUDIO_CRC_CH5_SIG = 0x00000005,
7823AFMT_AUDIO_CRC_CH6_SIG = 0x00000006,
7824AFMT_AUDIO_CRC_CH7_SIG = 0x00000007,
7825AFMT_AUDIO_CRC_RESERVED_8 = 0x00000008,
7826AFMT_AUDIO_CRC_RESERVED_9 = 0x00000009,
7827AFMT_AUDIO_CRC_RESERVED_10 = 0x0000000a,
7828AFMT_AUDIO_CRC_RESERVED_11 = 0x0000000b,
7829AFMT_AUDIO_CRC_RESERVED_12 = 0x0000000c,
7830AFMT_AUDIO_CRC_RESERVED_13 = 0x0000000d,
7831AFMT_AUDIO_CRC_RESERVED_14 = 0x0000000e,
7832AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x0000000f,
7833} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
7834
7835/*
7836 * AFMT_AUDIO_CRC_CONTROL_CONT enum
7837 */
7838
7839typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
7840AFMT_AUDIO_CRC_ONESHOT = 0x00000000,
7841AFMT_AUDIO_CRC_AUTO_RESTART = 0x00000001,
7842} AFMT_AUDIO_CRC_CONTROL_CONT;
7843
7844/*
7845 * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
7846 */
7847
7848typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
7849AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x00000000,
7850AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x00000001,
7851} AFMT_AUDIO_CRC_CONTROL_SOURCE;
7852
7853/*
7854 * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
7855 */
7856
7857typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
7858AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000,
7859AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x00000001,
7860} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
7861
7862/*
7863 * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
7864 */
7865
7866typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
7867AFMT_AUDIO_PACKET_SENT_DISABLED = 0x00000000,
7868AFMT_AUDIO_PACKET_SENT_ENABLED = 0x00000001,
7869} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
7870
7871/*
7872 * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
7873 */
7874
7875typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
7876AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0x00000000,
7877AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x00000001,
7878} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
7879
7880/*
7881 * AFMT_AUDIO_SRC_CONTROL_SELECT enum
7882 */
7883
7884typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
7885AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x00000000,
7886AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x00000001,
7887AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x00000002,
7888AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x00000003,
7889AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x00000004,
7890AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x00000005,
7891} AFMT_AUDIO_SRC_CONTROL_SELECT;
7892
7893/*
7894 * AFMT_HDMI_AUDIO_SEND_MAX_PACKETS enum
7895 */
7896
7897typedef enum AFMT_HDMI_AUDIO_SEND_MAX_PACKETS {
7898HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x00000000,
7899HDMI_SEND_MAX_AUDIO_PACKETS = 0x00000001,
7900} AFMT_HDMI_AUDIO_SEND_MAX_PACKETS;
7901
7902/*
7903 * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
7904 */
7905
7906typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
7907AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x00000000,
7908AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x00000001,
7909} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
7910
7911/*
7912 * AFMT_INTERRUPT_STATUS_CHG_MASK enum
7913 */
7914
7915typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
7916AFMT_INTERRUPT_DISABLE = 0x00000000,
7917AFMT_INTERRUPT_ENABLE = 0x00000001,
7918} AFMT_INTERRUPT_STATUS_CHG_MASK;
7919
7920/*
7921 * AFMT_MEM_PWR_DIS_CTRL enum
7922 */
7923
7924typedef enum AFMT_MEM_PWR_DIS_CTRL {
7925AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
7926AFMT_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
7927} AFMT_MEM_PWR_DIS_CTRL;
7928
7929/*
7930 * AFMT_MEM_PWR_FORCE_CTRL enum
7931 */
7932
7933typedef enum AFMT_MEM_PWR_FORCE_CTRL {
7934AFMT_MEM_NO_FORCE_REQUEST = 0x00000000,
7935AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
7936AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
7937AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
7938} AFMT_MEM_PWR_FORCE_CTRL;
7939
7940/*
7941 * AFMT_RAMP_CONTROL0_SIGN enum
7942 */
7943
7944typedef enum AFMT_RAMP_CONTROL0_SIGN {
7945AFMT_RAMP_SIGNED = 0x00000000,
7946AFMT_RAMP_UNSIGNED = 0x00000001,
7947} AFMT_RAMP_CONTROL0_SIGN;
7948
7949/*
7950 * AFMT_VBI_PACKET_CONTROL_ACP_SOURCE enum
7951 */
7952
7953typedef enum AFMT_VBI_PACKET_CONTROL_ACP_SOURCE {
7954AFMT_ACP_SOURCE_FROM_AZALIA = 0x00000000,
7955AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 0x00000001,
7956} AFMT_VBI_PACKET_CONTROL_ACP_SOURCE;
7957
7958/*
7959 * AUDIO_LAYOUT_SELECT enum
7960 */
7961
7962typedef enum AUDIO_LAYOUT_SELECT {
7963AUDIO_LAYOUT_0 = 0x00000000,
7964AUDIO_LAYOUT_1 = 0x00000001,
7965} AUDIO_LAYOUT_SELECT;
7966
7967/*******************************************************
7968 * DCOH_TOP Enums
7969 *******************************************************/
7970
7971/*
7972 * DCOH_TEST_CLOCK_MUX_SELECT_ENUM enum
7973 */
7974
7975typedef enum DCOH_TEST_CLOCK_MUX_SELECT_ENUM {
7976DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0x00000000,
7977DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_R = 0x00000001,
7978DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX1 = 0x00000002,
7979DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX2 = 0x00000003,
7980DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX3 = 0x00000004,
7981DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX4 = 0x00000005,
7982DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX5 = 0x00000006,
7983DCOH_TEST_CLOCK_MUX_SELECT_DISPCLK_G_AUX6 = 0x00000007,
7984DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_P = 0x00000008,
7985DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_R = 0x00000009,
7986DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX1 = 0x0000000a,
7987DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX2 = 0x0000000b,
7988DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX3 = 0x0000000c,
7989DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX4 = 0x0000000d,
7990DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX5 = 0x0000000e,
7991DCOH_TEST_CLOCK_MUX_SELECT_REFCLK_G_AUX6 = 0x0000000f,
7992DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK0 = 0x00000010,
7993DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK1 = 0x00000011,
7994DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK2 = 0x00000012,
7995DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK3 = 0x00000013,
7996DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK4 = 0x00000014,
7997DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK5 = 0x00000015,
7998DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK6 = 0x00000016,
7999DCOH_TEST_CLOCK_MUX_SELECT_DPIASYMCLK7 = 0x00000017,
8000DCOH_TEST_CLOCK_MUX_SELECT_PHYASYMCLK = 0x00000018,
8001DCOH_TEST_CLOCK_MUX_SELECT_PHYBSYMCLK = 0x00000019,
8002DCOH_TEST_CLOCK_MUX_SELECT_PHYCSYMCLK = 0x0000001a,
8003DCOH_TEST_CLOCK_MUX_SELECT_PHYDSYMCLK = 0x0000001b,
8004DCOH_TEST_CLOCK_MUX_SELECT_PHYESYMCLK = 0x0000001c,
8005DCOH_TEST_CLOCK_MUX_SELECT_PHYFSYMCLK = 0x0000001d,
8006DCOH_TEST_CLOCK_MUX_SELECT_PHYGSYMCLK = 0x0000001e,
8007} DCOH_TEST_CLOCK_MUX_SELECT_ENUM;
8008
8009/*
8010 * DCOH_TOP_CLOCK_GATING_DISABLE_ENUM enum
8011 */
8012
8013typedef enum DCOH_TOP_CLOCK_GATING_DISABLE_ENUM {
8014DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_ENABLED = 0x00000000,
8015DCOH_TOP_CLOCK_GATING_DISABLE_ENUM_DISABLED = 0x00000001,
8016} DCOH_TOP_CLOCK_GATING_DISABLE_ENUM;
8017
8018/*
8019 * DCOH_TOP_ENABLE_ENUM enum
8020 */
8021
8022typedef enum DCOH_TOP_ENABLE_ENUM {
8023DCOH_TOP_ENABLE_ENUM_DISABLED = 0x00000000,
8024DCOH_TOP_ENABLE_ENUM_ENABLED = 0x00000001,
8025} DCOH_TOP_ENABLE_ENUM;
8026
8027/*******************************************************
8028 * PHY_MUX Enums
8029 *******************************************************/
8030
8031/*
8032 * PHY_MUX_ENABLE_ENUM enum
8033 */
8034
8035typedef enum PHY_MUX_ENABLE_ENUM {
8036PHY_MUX_ENABLE_ENUM_DISABLED = 0x00000000,
8037PHY_MUX_ENABLE_ENUM_ENABLED = 0x00000001,
8038} PHY_MUX_ENABLE_ENUM;
8039
8040/*******************************************************
8041 * DP_AUX Enums
8042 *******************************************************/
8043
8044/*
8045 * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
8046 */
8047
8048typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
8049DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x00000000,
8050DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x00000001,
8051DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x00000002,
8052DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x00000003,
8053} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
8054
8055/*
8056 * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
8057 */
8058
8059typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
8060DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000,
8061DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x00000001,
8062} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
8063
8064/*
8065 * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
8066 */
8067
8068typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
8069DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x00000000,
8070DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x00000001,
8071} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
8072
8073/*
8074 * DP_AUX_ARB_STATUS enum
8075 */
8076
8077typedef enum DP_AUX_ARB_STATUS {
8078DP_AUX_IDLE = 0x00000000,
8079DP_AUX_IN_USE_LS = 0x00000001,
8080DP_AUX_IN_USE_GTC = 0x00000002,
8081DP_AUX_IN_USE_SW = 0x00000003,
8082DP_AUX_IN_USE_PHYWAKE = 0x00000004,
8083} DP_AUX_ARB_STATUS;
8084
8085/*
8086 * DP_AUX_CONTROL_HPD_SEL enum
8087 */
8088
8089typedef enum DP_AUX_CONTROL_HPD_SEL {
8090DP_AUX_CONTROL_HPD1_SELECTED = 0x00000000,
8091DP_AUX_CONTROL_HPD2_SELECTED = 0x00000001,
8092DP_AUX_CONTROL_HPD3_SELECTED = 0x00000002,
8093DP_AUX_CONTROL_HPD4_SELECTED = 0x00000003,
8094DP_AUX_CONTROL_NO_HPD_SELECTED = 0x00000004,
8095} DP_AUX_CONTROL_HPD_SEL;
8096
8097/*
8098 * DP_AUX_CONTROL_TEST_MODE enum
8099 */
8100
8101typedef enum DP_AUX_CONTROL_TEST_MODE {
8102DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x00000000,
8103DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x00000001,
8104} DP_AUX_CONTROL_TEST_MODE;
8105
8106/*
8107 * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
8108 */
8109
8110typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
8111ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000,
8112ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x00000001,
8113} DP_AUX_DEFINITE_ERR_REACHED_ACK;
8114
8115/*
8116 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
8117 */
8118
8119typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
8120DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000,
8121DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001,
8122} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
8123
8124/*
8125 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
8126 */
8127
8128typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
8129DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000,
8130DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001,
8131} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
8132
8133/*
8134 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
8135 */
8136
8137typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
8138DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000,
8139DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001,
8140} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
8141
8142/*
8143 * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
8144 */
8145
8146typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
8147DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000,
8148DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001,
8149DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002,
8150DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003,
8151} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
8152
8153/*
8154 * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
8155 */
8156
8157typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
8158DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000,
8159DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001,
8160DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002,
8161DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003,
8162} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
8163
8164/*
8165 * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
8166 */
8167
8168typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
8169DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0x00000000,
8170DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 0x00000001,
8171DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 0x00000002,
8172DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 0x00000003,
8173DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 0x00000004,
8174DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 0x00000005,
8175DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 0x00000006,
8176DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 0x00000007,
8177} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
8178
8179/*
8180 * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
8181 */
8182
8183typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
8184DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x00000000,
8185DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x00000001,
8186DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x00000002,
8187DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 0x00000003,
8188DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 0x00000004,
8189DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 0x00000005,
8190DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 0x00000006,
8191DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 0x00000007,
8192} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
8193
8194/*
8195 * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
8196 */
8197
8198typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
8199DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x00000000,
8200DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x00000001,
8201DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x00000002,
8202DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x00000003,
8203DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x00000004,
8204DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x00000005,
8205DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x00000006,
8206DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x00000007,
8207} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
8208
8209/*
8210 * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
8211 */
8212
8213typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
8214DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000,
8215DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001,
8216DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002,
8217DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003,
8218DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004,
8219DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005,
8220} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
8221
8222/*
8223 * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
8224 */
8225
8226typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
8227DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000,
8228DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001,
8229DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002,
8230DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003,
8231} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
8232
8233/*
8234 * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
8235 */
8236
8237typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
8238DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0x00000000,
8239DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 0x00000001,
8240} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
8241
8242/*
8243 * DP_AUX_ERR_OCCURRED_ACK enum
8244 */
8245
8246typedef enum DP_AUX_ERR_OCCURRED_ACK {
8247DP_AUX_ERR_OCCURRED__NOT_ACK = 0x00000000,
8248DP_AUX_ERR_OCCURRED__ACK = 0x00000001,
8249} DP_AUX_ERR_OCCURRED_ACK;
8250
8251/*
8252 * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
8253 */
8254
8255typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
8256DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0x00000000,
8257DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 0x00000001,
8258} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
8259
8260/*
8261 * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
8262 */
8263
8264typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
8265DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000,
8266DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001,
8267DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002,
8268DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003,
8269} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
8270
8271/*
8272 * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
8273 */
8274
8275typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
8276DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000,
8277DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001,
8278DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002,
8279DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003,
8280} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
8281
8282/*
8283 * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
8284 */
8285
8286typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
8287DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0x00000000,
8288DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 0x00000001,
8289DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 0x00000002,
8290DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 0x00000003,
8291} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
8292
8293/*
8294 * DP_AUX_INT_ACK enum
8295 */
8296
8297typedef enum DP_AUX_INT_ACK {
8298DP_AUX_INT__NOT_ACK = 0x00000000,
8299DP_AUX_INT__ACK = 0x00000001,
8300} DP_AUX_INT_ACK;
8301
8302/*
8303 * DP_AUX_LS_UPDATE_ACK enum
8304 */
8305
8306typedef enum DP_AUX_LS_UPDATE_ACK {
8307DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x00000000,
8308DP_AUX_INT_LS_UPDATE_ACK = 0x00000001,
8309} DP_AUX_LS_UPDATE_ACK;
8310
8311/*
8312 * DP_AUX_PHY_WAKE_PRIORITY enum
8313 */
8314
8315typedef enum DP_AUX_PHY_WAKE_PRIORITY {
8316DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0x00000000,
8317DP_AUX_PHY_WAKE_LOW_PRIORITY = 0x00000001,
8318} DP_AUX_PHY_WAKE_PRIORITY;
8319
8320/*
8321 * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
8322 */
8323
8324typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
8325DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x00000000,
8326DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x00000001,
8327} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
8328
8329/*
8330 * DP_AUX_RESET enum
8331 */
8332
8333typedef enum DP_AUX_RESET {
8334DP_AUX_RESET_DEASSERTED = 0x00000000,
8335DP_AUX_RESET_ASSERTED = 0x00000001,
8336} DP_AUX_RESET;
8337
8338/*
8339 * DP_AUX_RESET_DONE enum
8340 */
8341
8342typedef enum DP_AUX_RESET_DONE {
8343DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x00000000,
8344DP_AUX_RESET_SEQUENCE_DONE = 0x00000001,
8345} DP_AUX_RESET_DONE;
8346
8347/*
8348 * DP_AUX_RX_TIMEOUT_LEN_MUL enum
8349 */
8350
8351typedef enum DP_AUX_RX_TIMEOUT_LEN_MUL {
8352DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0x00000000,
8353DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 0x00000001,
8354DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 0x00000002,
8355DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 0x00000003,
8356} DP_AUX_RX_TIMEOUT_LEN_MUL;
8357
8358/*
8359 * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
8360 */
8361
8362typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
8363DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x00000000,
8364DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x00000001,
8365} DP_AUX_SW_CONTROL_LS_READ_TRIG;
8366
8367/*
8368 * DP_AUX_SW_CONTROL_SW_GO enum
8369 */
8370
8371typedef enum DP_AUX_SW_CONTROL_SW_GO {
8372DP_AUX_SW_CONTROL_SW__NOT_GO = 0x00000000,
8373DP_AUX_SW_CONTROL_SW__GO = 0x00000001,
8374} DP_AUX_SW_CONTROL_SW_GO;
8375
8376/*
8377 * DP_AUX_TX_PRECHARGE_LEN_MUL enum
8378 */
8379
8380typedef enum DP_AUX_TX_PRECHARGE_LEN_MUL {
8381DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0x00000000,
8382DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 0x00000001,
8383DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 0x00000002,
8384DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 0x00000003,
8385} DP_AUX_TX_PRECHARGE_LEN_MUL;
8386
8387/*******************************************************
8388 * HPD Enums
8389 *******************************************************/
8390
8391/*
8392 * HPD_INT_CONTROL_ACK enum
8393 */
8394
8395typedef enum HPD_INT_CONTROL_ACK {
8396HPD_INT_CONTROL_ACK_0 = 0x00000000,
8397HPD_INT_CONTROL_ACK_1 = 0x00000001,
8398} HPD_INT_CONTROL_ACK;
8399
8400/*
8401 * HPD_INT_CONTROL_POLARITY enum
8402 */
8403
8404typedef enum HPD_INT_CONTROL_POLARITY {
8405HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000,
8406HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001,
8407} HPD_INT_CONTROL_POLARITY;
8408
8409/*
8410 * HPD_INT_CONTROL_RX_INT_ACK enum
8411 */
8412
8413typedef enum HPD_INT_CONTROL_RX_INT_ACK {
8414HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000,
8415HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001,
8416} HPD_INT_CONTROL_RX_INT_ACK;
8417
8418/*******************************************************
8419 * HPO_TOP Enums
8420 *******************************************************/
8421
8422/*
8423 * HPO_TOP_CLOCK_GATING_DISABLE enum
8424 */
8425
8426typedef enum HPO_TOP_CLOCK_GATING_DISABLE {
8427HPO_TOP_CLOCK_GATING_EN = 0x00000000,
8428HPO_TOP_CLOCK_GATING_DIS = 0x00000001,
8429} HPO_TOP_CLOCK_GATING_DISABLE;
8430
8431/*
8432 * HPO_TOP_TEST_CLK_SEL enum
8433 */
8434
8435typedef enum HPO_TOP_TEST_CLK_SEL {
8436HPO_TOP_PERMANENT_DISPCLK = 0x00000000,
8437HPO_TOP_REGISTER_GATED_DISPCLK = 0x00000001,
8438HPO_TOP_PERMANENT_SOCCLK = 0x00000002,
8439HPO_TOP_TEST_CLOCK_RESERVED = 0x00000003,
8440HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 0x00000004,
8441HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 0x00000005,
8442HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 0x00000006,
8443HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 0x00000007,
8444HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 0x00000008,
8445HPO_TOP_PERMANENT_HDMICHARCLK0 = 0x00000009,
8446HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 0x0000000a,
8447HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 0x0000000b,
8448} HPO_TOP_TEST_CLK_SEL;
8449
8450/*******************************************************
8451 * DP_STREAM_MAPPER Enums
8452 *******************************************************/
8453
8454/*
8455 * DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET enum
8456 */
8457
8458typedef enum DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET {
8459DP_STREAM_MAPPER_LINK0 = 0x00000000,
8460DP_STREAM_MAPPER_LINK1 = 0x00000001,
8461DP_STREAM_MAPPER_LINK2 = 0x00000002,
8462DP_STREAM_MAPPER_LINK3 = 0x00000003,
8463DP_STREAM_MAPPER_RESERVED = 0x00000004,
8464} DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET;
8465
8466/*******************************************************
8467 * DP_STREAM_ENC Enums
8468 *******************************************************/
8469
8470/*
8471 * DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum
8472 */
8473
8474typedef enum DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR {
8475DP_STREAM_ENC_NO_ERROR_OCCURRED = 0x00000000,
8476DP_STREAM_ENC_UNDERFLOW_OCCURRED = 0x00000001,
8477DP_STREAM_ENC_OVERFLOW_OCCURRED = 0x00000002,
8478} DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR;
8479
8480/*
8481 * DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum
8482 */
8483
8484typedef enum DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT {
8485DP_STREAM_ENC_HARDWARE = 0x00000000,
8486DP_STREAM_ENC_PROGRAMMABLE = 0x00000001,
8487} DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT;
8488
8489/*
8490 * DP_STREAM_ENC_READ_CLOCK_CONTROL enum
8491 */
8492
8493typedef enum DP_STREAM_ENC_READ_CLOCK_CONTROL {
8494DP_STREAM_ENC_DCCG = 0x00000000,
8495DP_STREAM_ENC_DISPLAY_PIPE = 0x00000001,
8496} DP_STREAM_ENC_READ_CLOCK_CONTROL;
8497
8498/*
8499 * DP_STREAM_ENC_RESET_CONTROL enum
8500 */
8501
8502typedef enum DP_STREAM_ENC_RESET_CONTROL {
8503DP_STREAM_ENC_NOT_RESET = 0x00000000,
8504DP_STREAM_ENC_RESET = 0x00000001,
8505} DP_STREAM_ENC_RESET_CONTROL;
8506
8507/*
8508 * DP_STREAM_ENC_STREAM_ACTIVE enum
8509 */
8510
8511typedef enum DP_STREAM_ENC_STREAM_ACTIVE {
8512DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0x00000000,
8513DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 0x00000001,
8514} DP_STREAM_ENC_STREAM_ACTIVE;
8515
8516/*******************************************************
8517 * DP_SYM32_ENC Enums
8518 *******************************************************/
8519
8520/*
8521 * ENUM_DP_SYM32_ENC_AUDIO_MUTE enum
8522 */
8523
8524typedef enum ENUM_DP_SYM32_ENC_AUDIO_MUTE {
8525DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0x00000000,
8526DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 0x00000001,
8527} ENUM_DP_SYM32_ENC_AUDIO_MUTE;
8528
8529/*
8530 * ENUM_DP_SYM32_ENC_CONTINUOUS_MODE enum
8531 */
8532
8533typedef enum ENUM_DP_SYM32_ENC_CONTINUOUS_MODE {
8534DP_SYM32_ENC_ONE_SHOT_MODE = 0x00000000,
8535DP_SYM32_ENC_CONTINUOUS_MODE = 0x00000001,
8536} ENUM_DP_SYM32_ENC_CONTINUOUS_MODE;
8537
8538/*
8539 * ENUM_DP_SYM32_ENC_CRC_VALID enum
8540 */
8541
8542typedef enum ENUM_DP_SYM32_ENC_CRC_VALID {
8543DP_SYM32_ENC_CRC_NOT_VALID = 0x00000000,
8544DP_SYM32_ENC_CRC_VALID = 0x00000001,
8545} ENUM_DP_SYM32_ENC_CRC_VALID;
8546
8547/*
8548 * ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH enum
8549 */
8550
8551typedef enum ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH {
8552DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0x00000000,
8553DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 0x00000001,
8554DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 0x00000002,
8555DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 0x00000003,
8556} ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH;
8557
8558/*
8559 * ENUM_DP_SYM32_ENC_ENABLE enum
8560 */
8561
8562typedef enum ENUM_DP_SYM32_ENC_ENABLE {
8563DP_SYM32_ENC_DISABLE = 0x00000000,
8564DP_SYM32_ENC_ENABLE = 0x00000001,
8565} ENUM_DP_SYM32_ENC_ENABLE;
8566
8567/*
8568 * ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED enum
8569 */
8570
8571typedef enum ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED {
8572DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0x00000000,
8573DP_SYM32_ENC_GSP_DEADLINE_MISSED = 0x00000001,
8574} ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED;
8575
8576/*
8577 * ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION enum
8578 */
8579
8580typedef enum ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION {
8581DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0x00000000,
8582DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 0x00000001,
8583} ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION;
8584
8585/*
8586 * ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE enum
8587 */
8588
8589typedef enum ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE {
8590DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0x00000000,
8591DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 0x00000001,
8592DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 0x00000002,
8593DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 0x00000003,
8594} ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE;
8595
8596/*
8597 * ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING enum
8598 */
8599
8600typedef enum ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING {
8601DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0x00000000,
8602DP_SYM32_ENC_GSP_TRIGGER_PENDING = 0x00000001,
8603} ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING;
8604
8605/*
8606 * ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM enum
8607 */
8608
8609typedef enum ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM {
8610DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0x00000000,
8611DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
8612DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
8613DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
8614} ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM;
8615
8616/*
8617 * ENUM_DP_SYM32_ENC_OVERFLOW_STATUS enum
8618 */
8619
8620typedef enum ENUM_DP_SYM32_ENC_OVERFLOW_STATUS {
8621DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0x00000000,
8622DP_SYM32_ENC_OVERFLOW_OCCURRED = 0x00000001,
8623} ENUM_DP_SYM32_ENC_OVERFLOW_STATUS;
8624
8625/*
8626 * ENUM_DP_SYM32_ENC_PENDING enum
8627 */
8628
8629typedef enum ENUM_DP_SYM32_ENC_PENDING {
8630DP_SYM32_ENC_NOT_PENDING = 0x00000000,
8631DP_SYM32_ENC_PENDING = 0x00000001,
8632} ENUM_DP_SYM32_ENC_PENDING;
8633
8634/*
8635 * ENUM_DP_SYM32_ENC_PIXEL_ENCODING enum
8636 */
8637
8638typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING {
8639DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0x00000000,
8640DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 0x00000001,
8641DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 0x00000002,
8642DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 0x00000003,
8643} ENUM_DP_SYM32_ENC_PIXEL_ENCODING;
8644
8645/*
8646 * ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE enum
8647 */
8648
8649typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE {
8650DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0x00000000,
8651DP_SYM32_ENC_COMPRESSED_FORMAT = 0x00000001,
8652} ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE;
8653
8654/*
8655 * ENUM_DP_SYM32_ENC_POWER_STATE_ENUM enum
8656 */
8657
8658typedef enum ENUM_DP_SYM32_ENC_POWER_STATE_ENUM {
8659DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0x00000000,
8660DP_SYM32_ENC_POWER_STATE_ENUM_LS = 0x00000001,
8661DP_SYM32_ENC_POWER_STATE_ENUM_DS = 0x00000002,
8662DP_SYM32_ENC_POWER_STATE_ENUM_SD = 0x00000003,
8663} ENUM_DP_SYM32_ENC_POWER_STATE_ENUM;
8664
8665/*
8666 * ENUM_DP_SYM32_ENC_RESET enum
8667 */
8668
8669typedef enum ENUM_DP_SYM32_ENC_RESET {
8670DP_SYM32_ENC_NOT_RESET = 0x00000000,
8671DP_SYM32_ENC_RESET = 0x00000001,
8672} ENUM_DP_SYM32_ENC_RESET;
8673
8674/*
8675 * ENUM_DP_SYM32_ENC_SDP_PRIORITY enum
8676 */
8677
8678typedef enum ENUM_DP_SYM32_ENC_SDP_PRIORITY {
8679DP_SYM32_ENC_SDP_LOW_PRIORITY = 0x00000000,
8680DP_SYM32_ENC_SDP_HIGH_PRIORITY = 0x00000001,
8681} ENUM_DP_SYM32_ENC_SDP_PRIORITY;
8682
8683/*
8684 * ENUM_DP_SYM32_ENC_SOF_REFERENCE enum
8685 */
8686
8687typedef enum ENUM_DP_SYM32_ENC_SOF_REFERENCE {
8688DP_SYM32_ENC_DP_SOF = 0x00000000,
8689DP_SYM32_ENC_OTG_SOF = 0x00000001,
8690} ENUM_DP_SYM32_ENC_SOF_REFERENCE;
8691
8692/*
8693 * ENUM_DP_SYM32_ENC_VID_STREAM_DEFER enum
8694 */
8695
8696typedef enum ENUM_DP_SYM32_ENC_VID_STREAM_DEFER {
8697DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0x00000000,
8698DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 0x00000001,
8699DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 0x00000002,
8700} ENUM_DP_SYM32_ENC_VID_STREAM_DEFER;
8701
8702/*******************************************************
8703 * DP_DPHY_SYM32 Enums
8704 *******************************************************/
8705
8706/*
8707 * ENUM_DP_DPHY_SYM32_CRC_END_EVENT enum
8708 */
8709
8710typedef enum ENUM_DP_DPHY_SYM32_CRC_END_EVENT {
8711DP_DPHY_SYM32_CRC_END_LLCP = 0x00000000,
8712DP_DPHY_SYM32_CRC_END_PS_ONLY = 0x00000001,
8713DP_DPHY_SYM32_CRC_END_PS_LT_SR = 0x00000002,
8714DP_DPHY_SYM32_CRC_END_PS_ANY = 0x00000003,
8715} ENUM_DP_DPHY_SYM32_CRC_END_EVENT;
8716
8717/*
8718 * ENUM_DP_DPHY_SYM32_CRC_START_EVENT enum
8719 */
8720
8721typedef enum ENUM_DP_DPHY_SYM32_CRC_START_EVENT {
8722DP_DPHY_SYM32_CRC_START_LLCP = 0x00000000,
8723DP_DPHY_SYM32_CRC_START_PS_ONLY = 0x00000001,
8724DP_DPHY_SYM32_CRC_START_PS_LT_SR = 0x00000002,
8725DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 0x00000003,
8726DP_DPHY_SYM32_CRC_START_TP_START = 0x00000004,
8727} ENUM_DP_DPHY_SYM32_CRC_START_EVENT;
8728
8729/*
8730 * ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE enum
8731 */
8732
8733typedef enum ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE {
8734DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0x00000000,
8735DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 0x00000001,
8736DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 0x00000002,
8737} ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE;
8738
8739/*
8740 * ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS enum
8741 */
8742
8743typedef enum ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS {
8744DP_DPHY_SYM32_CRC_USE_END_EVENT = 0x00000000,
8745DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 0x00000001,
8746} ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS;
8747
8748/*
8749 * ENUM_DP_DPHY_SYM32_ENABLE enum
8750 */
8751
8752typedef enum ENUM_DP_DPHY_SYM32_ENABLE {
8753DP_DPHY_SYM32_DISABLE = 0x00000000,
8754DP_DPHY_SYM32_ENABLE = 0x00000001,
8755} ENUM_DP_DPHY_SYM32_ENABLE;
8756
8757/*
8758 * ENUM_DP_DPHY_SYM32_MODE enum
8759 */
8760
8761typedef enum ENUM_DP_DPHY_SYM32_MODE {
8762DP_DPHY_SYM32_LT_TPS1 = 0x00000000,
8763DP_DPHY_SYM32_LT_TPS2 = 0x00000001,
8764DP_DPHY_SYM32_ACTIVE = 0x00000002,
8765DP_DPHY_SYM32_TEST = 0x00000003,
8766} ENUM_DP_DPHY_SYM32_MODE;
8767
8768/*
8769 * ENUM_DP_DPHY_SYM32_NUM_LANES enum
8770 */
8771
8772typedef enum ENUM_DP_DPHY_SYM32_NUM_LANES {
8773DP_DPHY_SYM32_1LANE = 0x00000000,
8774DP_DPHY_SYM32_2LANE = 0x00000001,
8775DP_DPHY_SYM32_RESERVED = 0x00000002,
8776DP_DPHY_SYM32_4LANE = 0x00000003,
8777} ENUM_DP_DPHY_SYM32_NUM_LANES;
8778
8779/*
8780 * ENUM_DP_DPHY_SYM32_OUTPUT_MODE enum
8781 */
8782
8783typedef enum ENUM_DP_DPHY_SYM32_OUTPUT_MODE {
8784DP_DPHY_SYM32_OUTPUT_PHY = 0x00000000,
8785DP_DPHY_SYM32_OUTPUT_DPIA = 0x00000001,
8786} ENUM_DP_DPHY_SYM32_OUTPUT_MODE;
8787
8788/*
8789 * ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING enum
8790 */
8791
8792typedef enum ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING {
8793DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0x00000000,
8794DP_DPHY_SYM32_RATE_UPDATE_PENDING = 0x00000001,
8795} ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING;
8796
8797/*
8798 * ENUM_DP_DPHY_SYM32_RESET enum
8799 */
8800
8801typedef enum ENUM_DP_DPHY_SYM32_RESET {
8802DP_DPHY_SYM32_NOT_RESET = 0x00000000,
8803DP_DPHY_SYM32_RESET = 0x00000001,
8804} ENUM_DP_DPHY_SYM32_RESET;
8805
8806/*
8807 * ENUM_DP_DPHY_SYM32_RESET_STATUS enum
8808 */
8809
8810typedef enum ENUM_DP_DPHY_SYM32_RESET_STATUS {
8811DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0x00000000,
8812DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 0x00000001,
8813} ENUM_DP_DPHY_SYM32_RESET_STATUS;
8814
8815/*
8816 * ENUM_DP_DPHY_SYM32_SAT_UPDATE enum
8817 */
8818
8819typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE {
8820DP_DPHY_SYM32_SAT_NO_UPDATE = 0x00000000,
8821DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 0x00000001,
8822DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 0x00000002,
8823} ENUM_DP_DPHY_SYM32_SAT_UPDATE;
8824
8825/*
8826 * ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING enum
8827 */
8828
8829typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING {
8830DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0x00000000,
8831DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 0x00000001,
8832DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 0x00000002,
8833} ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING;
8834
8835/*
8836 * ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS enum
8837 */
8838
8839typedef enum ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS {
8840DP_DPHY_SYM32_SCHEDULER_OFF = 0x00000000,
8841DP_DPHY_SYM32_SCHEDULER_ASLEEP = 0x00000001,
8842DP_DPHY_SYM32_SCHEDULER_AWAKE = 0x00000002,
8843} ENUM_DP_DPHY_SYM32_SCHEDULER_STATUS;
8844
8845/*
8846 * ENUM_DP_DPHY_SYM32_STATUS enum
8847 */
8848
8849typedef enum ENUM_DP_DPHY_SYM32_STATUS {
8850DP_DPHY_SYM32_STATUS_IDLE = 0x00000000,
8851DP_DPHY_SYM32_STATUS_ENABLED = 0x00000001,
8852} ENUM_DP_DPHY_SYM32_STATUS;
8853
8854/*
8855 * ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE enum
8856 */
8857
8858typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE {
8859DP_DPHY_SYM32_STREAM_OVR_NONE = 0x00000000,
8860DP_DPHY_SYM32_STREAM_OVR_REPLACE = 0x00000001,
8861DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 0x00000002,
8862} ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE;
8863
8864/*
8865 * ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE enum
8866 */
8867
8868typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE {
8869DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0x00000000,
8870DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 0x00000001,
8871} ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE;
8872
8873/*
8874 * ENUM_DP_DPHY_SYM32_TP_PRBS_SEL enum
8875 */
8876
8877typedef enum ENUM_DP_DPHY_SYM32_TP_PRBS_SEL {
8878DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0x00000000,
8879DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 0x00000001,
8880DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 0x00000002,
8881DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 0x00000003,
8882DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 0x00000004,
8883DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 0x00000005,
8884} ENUM_DP_DPHY_SYM32_TP_PRBS_SEL;
8885
8886/*
8887 * ENUM_DP_DPHY_SYM32_TP_SELECT enum
8888 */
8889
8890typedef enum ENUM_DP_DPHY_SYM32_TP_SELECT {
8891DP_DPHY_SYM32_TP_SELECT_TPS1 = 0x00000000,
8892DP_DPHY_SYM32_TP_SELECT_TPS2 = 0x00000001,
8893DP_DPHY_SYM32_TP_SELECT_PRBS = 0x00000002,
8894DP_DPHY_SYM32_TP_SELECT_CUSTOM = 0x00000003,
8895DP_DPHY_SYM32_TP_SELECT_SQUARE = 0x00000004,
8896} ENUM_DP_DPHY_SYM32_TP_SELECT;
8897
8898/*******************************************************
8899 * APG Enums
8900 *******************************************************/
8901
8902/*
8903 * APG_AUDIO_CRC_CONTROL_CH_SEL enum
8904 */
8905
8906typedef enum APG_AUDIO_CRC_CONTROL_CH_SEL {
8907APG_AUDIO_CRC_CH0_SIG = 0x00000000,
8908APG_AUDIO_CRC_CH1_SIG = 0x00000001,
8909APG_AUDIO_CRC_CH2_SIG = 0x00000002,
8910APG_AUDIO_CRC_CH3_SIG = 0x00000003,
8911APG_AUDIO_CRC_CH4_SIG = 0x00000004,
8912APG_AUDIO_CRC_CH5_SIG = 0x00000005,
8913APG_AUDIO_CRC_CH6_SIG = 0x00000006,
8914APG_AUDIO_CRC_CH7_SIG = 0x00000007,
8915APG_AUDIO_CRC_RESERVED_8 = 0x00000008,
8916APG_AUDIO_CRC_RESERVED_9 = 0x00000009,
8917APG_AUDIO_CRC_RESERVED_10 = 0x0000000a,
8918APG_AUDIO_CRC_RESERVED_11 = 0x0000000b,
8919APG_AUDIO_CRC_RESERVED_12 = 0x0000000c,
8920APG_AUDIO_CRC_RESERVED_13 = 0x0000000d,
8921APG_AUDIO_CRC_RESERVED_14 = 0x0000000e,
8922APG_AUDIO_CRC_RESERVED_15 = 0x0000000f,
8923} APG_AUDIO_CRC_CONTROL_CH_SEL;
8924
8925/*
8926 * APG_AUDIO_CRC_CONTROL_CONT enum
8927 */
8928
8929typedef enum APG_AUDIO_CRC_CONTROL_CONT {
8930APG_AUDIO_CRC_ONESHOT = 0x00000000,
8931APG_AUDIO_CRC_CONTINUOUS = 0x00000001,
8932} APG_AUDIO_CRC_CONTROL_CONT;
8933
8934/*
8935 * APG_DBG_ACP_TYPE enum
8936 */
8937
8938typedef enum APG_DBG_ACP_TYPE {
8939APG_ACP_TYPE_GENERIC_AUDIO = 0x00000000,
8940APG_ACP_TYPE_ICE60958_AUDIO = 0x00000001,
8941APG_ACP_TYPE_DVD_AUDIO = 0x00000002,
8942APG_ACP_TYPE_SUPER_AUDIO_CD = 0x00000003,
8943} APG_DBG_ACP_TYPE;
8944
8945/*
8946 * APG_DBG_AUDIO_DTO_BASE enum
8947 */
8948
8949typedef enum APG_DBG_AUDIO_DTO_BASE {
8950BASE_RATE_48KHZ = 0x00000000,
8951BASE_RATE_44P1KHZ = 0x00000001,
8952} APG_DBG_AUDIO_DTO_BASE;
8953
8954/*
8955 * APG_DBG_AUDIO_DTO_DIV enum
8956 */
8957
8958typedef enum APG_DBG_AUDIO_DTO_DIV {
8959DIVISOR_BY1 = 0x00000000,
8960DIVISOR_BY2_RESERVED = 0x00000001,
8961DIVISOR_BY3 = 0x00000002,
8962DIVISOR_BY4_RESERVED = 0x00000003,
8963DIVISOR_BY5_RESERVED = 0x00000004,
8964DIVISOR_BY6_RESERVED = 0x00000005,
8965DIVISOR_BY7_RESERVED = 0x00000006,
8966DIVISOR_BY8_RESERVED = 0x00000007,
8967} APG_DBG_AUDIO_DTO_DIV;
8968
8969/*
8970 * APG_DBG_AUDIO_DTO_MULTI enum
8971 */
8972
8973typedef enum APG_DBG_AUDIO_DTO_MULTI {
8974MULTIPLE_BY1 = 0x00000000,
8975MULTIPLE_BY2 = 0x00000001,
8976MULTIPLE_BY3_RESERVED = 0x00000002,
8977MULTIPLE_BY4 = 0x00000003,
8978MULTIPLE_RESERVED = 0x00000004,
8979} APG_DBG_AUDIO_DTO_MULTI;
8980
8981/*
8982 * APG_DBG_MUX_SEL enum
8983 */
8984
8985typedef enum APG_DBG_MUX_SEL {
8986APG_FUNCTIONAL_MODE = 0x00000000,
8987APG_DEBUG_AUDIO_MODE = 0x00000001,
8988} APG_DBG_MUX_SEL;
8989
8990/*
8991 * APG_DP_ASP_CHANNEL_COUNT_OVERRIDE enum
8992 */
8993
8994typedef enum APG_DP_ASP_CHANNEL_COUNT_OVERRIDE {
8995APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000,
8996APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001,
8997} APG_DP_ASP_CHANNEL_COUNT_OVERRIDE;
8998
8999/*
9000 * APG_MEM_POWER_STATE enum
9001 */
9002
9003typedef enum APG_MEM_POWER_STATE {
9004APG_MEM_POWER_STATE_ON = 0x00000000,
9005APG_MEM_POWER_STATE_LS = 0x00000001,
9006APG_MEM_POWER_STATE_DS = 0x00000002,
9007APG_MEM_POWER_STATE_SD = 0x00000003,
9008} APG_MEM_POWER_STATE;
9009
9010/*
9011 * APG_MEM_PWR_DIS_CTRL enum
9012 */
9013
9014typedef enum APG_MEM_PWR_DIS_CTRL {
9015APG_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
9016APG_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
9017} APG_MEM_PWR_DIS_CTRL;
9018
9019/*
9020 * APG_MEM_PWR_FORCE_CTRL enum
9021 */
9022
9023typedef enum APG_MEM_PWR_FORCE_CTRL {
9024APG_MEM_NO_FORCE_REQUEST = 0x00000000,
9025APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
9026APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
9027APG_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
9028} APG_MEM_PWR_FORCE_CTRL;
9029
9030/*
9031 * APG_PACKET_CONTROL_ACP_SOURCE enum
9032 */
9033
9034typedef enum APG_PACKET_CONTROL_ACP_SOURCE {
9035APG_ACP_SOURCE_NO_OVERRIDE = 0x00000000,
9036APG_ACP_OVERRIDE = 0x00000001,
9037} APG_PACKET_CONTROL_ACP_SOURCE;
9038
9039/*
9040 * APG_PACKET_CONTROL_AUDIO_INFO_SOURCE enum
9041 */
9042
9043typedef enum APG_PACKET_CONTROL_AUDIO_INFO_SOURCE {
9044APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0x00000000,
9045APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 0x00000001,
9046} APG_PACKET_CONTROL_AUDIO_INFO_SOURCE;
9047
9048/*
9049 * APG_RAMP_CONTROL_SIGN enum
9050 */
9051
9052typedef enum APG_RAMP_CONTROL_SIGN {
9053APG_RAMP_SIGNED = 0x00000000,
9054APG_RAMP_UNSIGNED = 0x00000001,
9055} APG_RAMP_CONTROL_SIGN;
9056
9057/*******************************************************
9058 * DCIO Enums
9059 *******************************************************/
9060
9061/*
9062 * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
9063 */
9064
9065typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
9066DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0x00000000,
9067DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 0x00000001,
9068DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 0x00000002,
9069DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 0x00000003,
9070DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 0x00000004,
9071DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 0x00000005,
9072} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
9073
9074/*
9075 * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
9076 */
9077
9078typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
9079DCIO_TEST_CLK_SEL_DISPCLK = 0x00000000,
9080DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x00000001,
9081DCIO_TEST_CLK_SEL_SOCCLK = 0x00000002,
9082} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
9083
9084/*
9085 * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
9086 */
9087
9088typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
9089DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x00000000,
9090DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x00000001,
9091} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
9092
9093/*
9094 * DCIO_DBG_ASYNC_4BIT_SEL enum
9095 */
9096
9097typedef enum DCIO_DBG_ASYNC_4BIT_SEL {
9098DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0x00000000,
9099DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 0x00000001,
9100DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 0x00000002,
9101DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 0x00000003,
9102DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 0x00000004,
9103DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 0x00000005,
9104DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 0x00000006,
9105DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 0x00000007,
9106} DCIO_DBG_ASYNC_4BIT_SEL;
9107
9108/*
9109 * DCIO_DBG_ASYNC_BLOCK_SEL enum
9110 */
9111
9112typedef enum DCIO_DBG_ASYNC_BLOCK_SEL {
9113DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0x00000000,
9114DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 0x00000001,
9115DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 0x00000002,
9116DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 0x00000003,
9117} DCIO_DBG_ASYNC_BLOCK_SEL;
9118
9119/*
9120 * DCIO_DCRXPHY_SOFT_RESET enum
9121 */
9122
9123typedef enum DCIO_DCRXPHY_SOFT_RESET {
9124DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x00000000,
9125DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x00000001,
9126} DCIO_DCRXPHY_SOFT_RESET;
9127
9128/*
9129 * DCIO_DC_GENERICA_SEL enum
9130 */
9131
9132typedef enum DCIO_DC_GENERICA_SEL {
9133DCIO_GENERICA_SEL_STEREOSYNC = 0x00000001,
9134DCIO_GENERICA_SEL_GENERICA_DCCG = 0x0000000a,
9135DCIO_GENERICA_SEL_SYNCEN = 0x0000000b,
9136} DCIO_DC_GENERICA_SEL;
9137
9138/*
9139 * DCIO_DC_GENERICB_SEL enum
9140 */
9141
9142typedef enum DCIO_DC_GENERICB_SEL {
9143DCIO_GENERICB_SEL_STEREOSYNC = 0x00000001,
9144DCIO_GENERICB_SEL_GENERICB_DCCG = 0x0000000a,
9145DCIO_GENERICB_SEL_SYNCEN = 0x0000000b,
9146} DCIO_DC_GENERICB_SEL;
9147
9148/*
9149 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
9150 */
9151
9152typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
9153DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x00000000,
9154DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x00000001,
9155DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x00000002,
9156DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x00000003,
9157DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x00000004,
9158DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x00000005,
9159DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x00000006,
9160} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
9161
9162/*
9163 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
9164 */
9165
9166typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
9167DCIO_UNIPHYA_FBDIV_CLK = 0x00000000,
9168DCIO_UNIPHYB_FBDIV_CLK = 0x00000001,
9169DCIO_UNIPHYC_FBDIV_CLK = 0x00000002,
9170DCIO_UNIPHYD_FBDIV_CLK = 0x00000003,
9171DCIO_UNIPHYE_FBDIV_CLK = 0x00000004,
9172DCIO_UNIPHYF_FBDIV_CLK = 0x00000005,
9173DCIO_UNIPHYG_FBDIV_CLK = 0x00000006,
9174} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
9175
9176/*
9177 * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
9178 */
9179
9180typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
9181DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x00000000,
9182DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x00000001,
9183DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x00000002,
9184DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x00000003,
9185DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x00000004,
9186DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x00000005,
9187DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x00000006,
9188} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
9189
9190/*
9191 * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
9192 */
9193
9194typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
9195DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x00000000,
9196DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x00000001,
9197DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x00000002,
9198DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x00000003,
9199DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x00000004,
9200DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x00000005,
9201DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x00000006,
9202} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
9203
9204/*
9205 * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum
9206 */
9207
9208typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
9209DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x00000000,
9210DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x00000001,
9211} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
9212
9213/*
9214 * DCIO_DC_GPU_TIMER_READ_SELECT enum
9215 */
9216
9217typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
9218DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000,
9219DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001,
9220DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x00000002,
9221DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x00000003,
9222DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000004,
9223DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000005,
9224} DCIO_DC_GPU_TIMER_READ_SELECT;
9225
9226/*
9227 * DCIO_DC_GPU_TIMER_START_POSITION enum
9228 */
9229
9230typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
9231DCIO_GPU_TIMER_START_0_END_27 = 0x00000000,
9232DCIO_GPU_TIMER_START_1_END_28 = 0x00000001,
9233DCIO_GPU_TIMER_START_2_END_29 = 0x00000002,
9234DCIO_GPU_TIMER_START_3_END_30 = 0x00000003,
9235DCIO_GPU_TIMER_START_4_END_31 = 0x00000004,
9236DCIO_GPU_TIMER_START_6_END_33 = 0x00000005,
9237DCIO_GPU_TIMER_START_8_END_35 = 0x00000006,
9238DCIO_GPU_TIMER_START_10_END_37 = 0x00000007,
9239} DCIO_DC_GPU_TIMER_START_POSITION;
9240
9241/*
9242 * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
9243 */
9244
9245typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
9246DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x00000000,
9247DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x00000001,
9248DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x00000002,
9249DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003,
9250} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
9251
9252/*
9253 * DCIO_DIO_EXT_VSYNC_MASK enum
9254 */
9255
9256typedef enum DCIO_DIO_EXT_VSYNC_MASK {
9257DCIO_EXT_VSYNC_MASK_NONE = 0x00000000,
9258DCIO_EXT_VSYNC_MASK_PIPE0 = 0x00000001,
9259DCIO_EXT_VSYNC_MASK_PIPE1 = 0x00000002,
9260DCIO_EXT_VSYNC_MASK_PIPE2 = 0x00000003,
9261DCIO_EXT_VSYNC_MASK_PIPE3 = 0x00000004,
9262DCIO_EXT_VSYNC_MASK_PIPE4 = 0x00000005,
9263DCIO_EXT_VSYNC_MASK_PIPE5 = 0x00000006,
9264DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x00000007,
9265} DCIO_DIO_EXT_VSYNC_MASK;
9266
9267/*
9268 * DCIO_DIO_OTG_EXT_VSYNC_MUX enum
9269 */
9270
9271typedef enum DCIO_DIO_OTG_EXT_VSYNC_MUX {
9272DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x00000000,
9273DCIO_EXT_VSYNC_MUX_OTG0 = 0x00000001,
9274DCIO_EXT_VSYNC_MUX_OTG1 = 0x00000002,
9275DCIO_EXT_VSYNC_MUX_OTG2 = 0x00000003,
9276DCIO_EXT_VSYNC_MUX_OTG3 = 0x00000004,
9277DCIO_EXT_VSYNC_MUX_OTG4 = 0x00000005,
9278DCIO_EXT_VSYNC_MUX_OTG5 = 0x00000006,
9279DCIO_EXT_VSYNC_MUX_GENERICB = 0x00000007,
9280} DCIO_DIO_OTG_EXT_VSYNC_MUX;
9281
9282/*
9283 * DCIO_DPCS_INTERRUPT_MASK enum
9284 */
9285
9286typedef enum DCIO_DPCS_INTERRUPT_MASK {
9287DCIO_DPCS_INTERRUPT_DISABLE = 0x00000000,
9288DCIO_DPCS_INTERRUPT_ENABLE = 0x00000001,
9289} DCIO_DPCS_INTERRUPT_MASK;
9290
9291/*
9292 * DCIO_DPCS_INTERRUPT_TYPE enum
9293 */
9294
9295typedef enum DCIO_DPCS_INTERRUPT_TYPE {
9296DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
9297DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
9298} DCIO_DPCS_INTERRUPT_TYPE;
9299
9300/*
9301 * DCIO_GENLK_CLK_GSL_MASK enum
9302 */
9303
9304typedef enum DCIO_GENLK_CLK_GSL_MASK {
9305DCIO_GENLK_CLK_GSL_MASK_NO = 0x00000000,
9306DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x00000001,
9307DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x00000002,
9308} DCIO_GENLK_CLK_GSL_MASK;
9309
9310/*
9311 * DCIO_GENLK_VSYNC_GSL_MASK enum
9312 */
9313
9314typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
9315DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x00000000,
9316DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x00000001,
9317DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x00000002,
9318} DCIO_GENLK_VSYNC_GSL_MASK;
9319
9320/*
9321 * DCIO_GSL_SEL enum
9322 */
9323
9324typedef enum DCIO_GSL_SEL {
9325DCIO_GSL_SEL_GROUP_0 = 0x00000000,
9326DCIO_GSL_SEL_GROUP_1 = 0x00000001,
9327DCIO_GSL_SEL_GROUP_2 = 0x00000002,
9328} DCIO_GSL_SEL;
9329
9330/*
9331 * DCIO_PHY_HPO_ENC_SRC_SEL enum
9332 */
9333
9334typedef enum DCIO_PHY_HPO_ENC_SRC_SEL {
9335HPO_SRC0 = 0x00000000,
9336HPO_SRC_RESERVED = 0x00000001,
9337} DCIO_PHY_HPO_ENC_SRC_SEL;
9338
9339/*
9340 * DCIO_SWAPLOCK_A_GSL_MASK enum
9341 */
9342
9343typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
9344DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x00000000,
9345DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x00000001,
9346DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x00000002,
9347} DCIO_SWAPLOCK_A_GSL_MASK;
9348
9349/*
9350 * DCIO_SWAPLOCK_B_GSL_MASK enum
9351 */
9352
9353typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
9354DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x00000000,
9355DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x00000001,
9356DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x00000002,
9357} DCIO_SWAPLOCK_B_GSL_MASK;
9358
9359/*
9360 * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
9361 */
9362
9363typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
9364DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x00000000,
9365DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x00000001,
9366DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x00000002,
9367DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x00000003,
9368} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
9369
9370/*
9371 * DCIO_UNIPHY_IMPCAL_SEL enum
9372 */
9373
9374typedef enum DCIO_UNIPHY_IMPCAL_SEL {
9375DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x00000000,
9376DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x00000001,
9377} DCIO_UNIPHY_IMPCAL_SEL;
9378
9379/*
9380 * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
9381 */
9382
9383typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
9384DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x00000000,
9385DCIO_UNIPHY_CHANNEL_INVERTED = 0x00000001,
9386} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
9387
9388/*
9389 * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
9390 */
9391
9392typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
9393DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000,
9394DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x00000001,
9395DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002,
9396DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 0x00000003,
9397} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
9398
9399/*******************************************************
9400 * DCIO_CHIP Enums
9401 *******************************************************/
9402
9403/*
9404 * DCIOCHIP_AUX_ALL_PWR_OK enum
9405 */
9406
9407typedef enum DCIOCHIP_AUX_ALL_PWR_OK {
9408DCIOCHIP_AUX_ALL_PWR_OK_0 = 0x00000000,
9409DCIOCHIP_AUX_ALL_PWR_OK_1 = 0x00000001,
9410} DCIOCHIP_AUX_ALL_PWR_OK;
9411
9412/*
9413 * DCIOCHIP_AUX_CSEL0P9 enum
9414 */
9415
9416typedef enum DCIOCHIP_AUX_CSEL0P9 {
9417DCIOCHIP_AUX_CSEL_DEC1P0 = 0x00000000,
9418DCIOCHIP_AUX_CSEL_DEC0P9 = 0x00000001,
9419} DCIOCHIP_AUX_CSEL0P9;
9420
9421/*
9422 * DCIOCHIP_AUX_CSEL1P1 enum
9423 */
9424
9425typedef enum DCIOCHIP_AUX_CSEL1P1 {
9426DCIOCHIP_AUX_CSEL_INC1P0 = 0x00000000,
9427DCIOCHIP_AUX_CSEL_INC1P1 = 0x00000001,
9428} DCIOCHIP_AUX_CSEL1P1;
9429
9430/*
9431 * DCIOCHIP_AUX_FALLSLEWSEL enum
9432 */
9433
9434typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
9435DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x00000000,
9436DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x00000001,
9437DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x00000002,
9438DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x00000003,
9439} DCIOCHIP_AUX_FALLSLEWSEL;
9440
9441/*
9442 * DCIOCHIP_AUX_HYS_TUNE enum
9443 */
9444
9445typedef enum DCIOCHIP_AUX_HYS_TUNE {
9446DCIOCHIP_AUX_HYS_TUNE_0 = 0x00000000,
9447DCIOCHIP_AUX_HYS_TUNE_1 = 0x00000001,
9448DCIOCHIP_AUX_HYS_TUNE_2 = 0x00000002,
9449DCIOCHIP_AUX_HYS_TUNE_3 = 0x00000003,
9450} DCIOCHIP_AUX_HYS_TUNE;
9451
9452/*
9453 * DCIOCHIP_AUX_RECEIVER_SEL enum
9454 */
9455
9456typedef enum DCIOCHIP_AUX_RECEIVER_SEL {
9457DCIOCHIP_AUX_RECEIVER_SEL_0 = 0x00000000,
9458DCIOCHIP_AUX_RECEIVER_SEL_1 = 0x00000001,
9459DCIOCHIP_AUX_RECEIVER_SEL_2 = 0x00000002,
9460DCIOCHIP_AUX_RECEIVER_SEL_3 = 0x00000003,
9461} DCIOCHIP_AUX_RECEIVER_SEL;
9462
9463/*
9464 * DCIOCHIP_AUX_RSEL0P9 enum
9465 */
9466
9467typedef enum DCIOCHIP_AUX_RSEL0P9 {
9468DCIOCHIP_AUX_RSEL_DEC1P0 = 0x00000000,
9469DCIOCHIP_AUX_RSEL_DEC0P9 = 0x00000001,
9470} DCIOCHIP_AUX_RSEL0P9;
9471
9472/*
9473 * DCIOCHIP_AUX_RSEL1P1 enum
9474 */
9475
9476typedef enum DCIOCHIP_AUX_RSEL1P1 {
9477DCIOCHIP_AUX_RSEL_INC1P0 = 0x00000000,
9478DCIOCHIP_AUX_RSEL_INC1P1 = 0x00000001,
9479} DCIOCHIP_AUX_RSEL1P1;
9480
9481/*
9482 * DCIOCHIP_AUX_SPIKESEL enum
9483 */
9484
9485typedef enum DCIOCHIP_AUX_SPIKESEL {
9486DCIOCHIP_AUX_SPIKESEL_50NS = 0x00000000,
9487DCIOCHIP_AUX_SPIKESEL_10NS = 0x00000001,
9488} DCIOCHIP_AUX_SPIKESEL;
9489
9490/*
9491 * DCIOCHIP_AUX_VOD_TUNE enum
9492 */
9493
9494typedef enum DCIOCHIP_AUX_VOD_TUNE {
9495DCIOCHIP_AUX_VOD_TUNE_0 = 0x00000000,
9496DCIOCHIP_AUX_VOD_TUNE_1 = 0x00000001,
9497DCIOCHIP_AUX_VOD_TUNE_2 = 0x00000002,
9498DCIOCHIP_AUX_VOD_TUNE_3 = 0x00000003,
9499} DCIOCHIP_AUX_VOD_TUNE;
9500
9501/*
9502 * DCIOCHIP_GPIO_MASK_EN enum
9503 */
9504
9505typedef enum DCIOCHIP_GPIO_MASK_EN {
9506DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x00000000,
9507DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x00000001,
9508} DCIOCHIP_GPIO_MASK_EN;
9509
9510/*
9511 * DCIOCHIP_HPD_SEL enum
9512 */
9513
9514typedef enum DCIOCHIP_HPD_SEL {
9515DCIOCHIP_HPD_SEL_ASYNC = 0x00000000,
9516DCIOCHIP_HPD_SEL_CLOCKED = 0x00000001,
9517} DCIOCHIP_HPD_SEL;
9518
9519/*
9520 * DCIOCHIP_I2C_COMPSEL enum
9521 */
9522
9523typedef enum DCIOCHIP_I2C_COMPSEL {
9524DCIOCHIP_I2C_REC_SCHMIT = 0x00000000,
9525DCIOCHIP_I2C_REC_COMPARATOR = 0x00000001,
9526} DCIOCHIP_I2C_COMPSEL;
9527
9528/*
9529 * DCIOCHIP_I2C_FALLSLEWSEL enum
9530 */
9531
9532typedef enum DCIOCHIP_I2C_FALLSLEWSEL {
9533DCIOCHIP_I2C_FALLSLEWSEL_00 = 0x00000000,
9534DCIOCHIP_I2C_FALLSLEWSEL_01 = 0x00000001,
9535DCIOCHIP_I2C_FALLSLEWSEL_10 = 0x00000002,
9536DCIOCHIP_I2C_FALLSLEWSEL_11 = 0x00000003,
9537} DCIOCHIP_I2C_FALLSLEWSEL;
9538
9539/*
9540 * DCIOCHIP_I2C_RECEIVER_SEL enum
9541 */
9542
9543typedef enum DCIOCHIP_I2C_RECEIVER_SEL {
9544DCIOCHIP_I2C_RECEIVER_SEL_0 = 0x00000000,
9545DCIOCHIP_I2C_RECEIVER_SEL_1 = 0x00000001,
9546DCIOCHIP_I2C_RECEIVER_SEL_2 = 0x00000002,
9547DCIOCHIP_I2C_RECEIVER_SEL_3 = 0x00000003,
9548} DCIOCHIP_I2C_RECEIVER_SEL;
9549
9550/*
9551 * DCIOCHIP_I2C_VPH_1V2_EN enum
9552 */
9553
9554typedef enum DCIOCHIP_I2C_VPH_1V2_EN {
9555DCIOCHIP_I2C_VPH_1V2_EN_0 = 0x00000000,
9556DCIOCHIP_I2C_VPH_1V2_EN_1 = 0x00000001,
9557} DCIOCHIP_I2C_VPH_1V2_EN;
9558
9559/*
9560 * DCIOCHIP_INVERT enum
9561 */
9562
9563typedef enum DCIOCHIP_INVERT {
9564DCIOCHIP_POL_NON_INVERT = 0x00000000,
9565DCIOCHIP_POL_INVERT = 0x00000001,
9566} DCIOCHIP_INVERT;
9567
9568/*
9569 * DCIOCHIP_MASK enum
9570 */
9571
9572typedef enum DCIOCHIP_MASK {
9573DCIOCHIP_MASK_DISABLE = 0x00000000,
9574DCIOCHIP_MASK_ENABLE = 0x00000001,
9575} DCIOCHIP_MASK;
9576
9577/*
9578 * DCIOCHIP_PAD_MODE enum
9579 */
9580
9581typedef enum DCIOCHIP_PAD_MODE {
9582DCIOCHIP_PAD_MODE_DDC = 0x00000000,
9583DCIOCHIP_PAD_MODE_DP = 0x00000001,
9584} DCIOCHIP_PAD_MODE;
9585
9586/*
9587 * DCIOCHIP_PD_EN enum
9588 */
9589
9590typedef enum DCIOCHIP_PD_EN {
9591DCIOCHIP_PD_EN_NOTALLOW = 0x00000000,
9592DCIOCHIP_PD_EN_ALLOW = 0x00000001,
9593} DCIOCHIP_PD_EN;
9594
9595/*
9596 * DCIOCHIP_REF_27_SRC_SEL enum
9597 */
9598
9599typedef enum DCIOCHIP_REF_27_SRC_SEL {
9600DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x00000000,
9601DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001,
9602DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x00000002,
9603DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003,
9604} DCIOCHIP_REF_27_SRC_SEL;
9605
9606/*******************************************************
9607 * PWRSEQ Enums
9608 *******************************************************/
9609
9610/*
9611 * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
9612 */
9613
9614typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
9615PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x00000000,
9616PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x00000001,
9617} PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
9618
9619/*
9620 * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN enum
9621 */
9622
9623typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN {
9624PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0x00000000,
9625PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 0x00000001,
9626} PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN;
9627
9628/*
9629 * PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum
9630 */
9631
9632typedef enum PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
9633PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x00000000,
9634PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x00000001,
9635PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x00000002,
9636PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x00000003,
9637} PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
9638
9639/*
9640 * PWRSEQ_BL_PWM_CNTL_BL_PWM_EN enum
9641 */
9642
9643typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_EN {
9644PWRSEQ_BL_PWM_DISABLE = 0x00000000,
9645PWRSEQ_BL_PWM_ENABLE = 0x00000001,
9646} PWRSEQ_BL_PWM_CNTL_BL_PWM_EN;
9647
9648/*
9649 * PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
9650 */
9651
9652typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
9653PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0x00000000,
9654PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 0x00000001,
9655} PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
9656
9657/*
9658 * PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
9659 */
9660
9661typedef enum PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
9662PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000,
9663PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001,
9664} PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
9665
9666/*
9667 * PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
9668 */
9669
9670typedef enum PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
9671PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000,
9672PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 0x00000001,
9673} PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
9674
9675/*
9676 * PWRSEQ_BL_PWM_GRP1_REG_LOCK enum
9677 */
9678
9679typedef enum PWRSEQ_BL_PWM_GRP1_REG_LOCK {
9680PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x00000000,
9681PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x00000001,
9682} PWRSEQ_BL_PWM_GRP1_REG_LOCK;
9683
9684/*
9685 * PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
9686 */
9687
9688typedef enum PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
9689PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000,
9690PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001,
9691} PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
9692
9693/*
9694 * PWRSEQ_GPIO_MASK_EN enum
9695 */
9696
9697typedef enum PWRSEQ_GPIO_MASK_EN {
9698PWRSEQ_GPIO_MASK_EN_HARDWARE = 0x00000000,
9699PWRSEQ_GPIO_MASK_EN_SOFTWARE = 0x00000001,
9700} PWRSEQ_GPIO_MASK_EN;
9701
9702/*
9703 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON enum
9704 */
9705
9706typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON {
9707PWRSEQ_PANEL_BLON_OFF = 0x00000000,
9708PWRSEQ_PANEL_BLON_ON = 0x00000001,
9709} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON;
9710
9711/*
9712 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL enum
9713 */
9714
9715typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL {
9716PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0x00000000,
9717PWRSEQ_PANEL_BLON_POL_INVERT = 0x00000001,
9718} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL;
9719
9720/*
9721 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON enum
9722 */
9723
9724typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON {
9725PWRSEQ_PANEL_DIGON_OFF = 0x00000000,
9726PWRSEQ_PANEL_DIGON_ON = 0x00000001,
9727} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON;
9728
9729/*
9730 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL enum
9731 */
9732
9733typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL {
9734PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0x00000000,
9735PWRSEQ_PANEL_DIGON_POL_INVERT = 0x00000001,
9736} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL;
9737
9738/*
9739 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL enum
9740 */
9741
9742typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL {
9743PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0x00000000,
9744PWRSEQ_PANEL_SYNCEN_POL_INVERT = 0x00000001,
9745} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL;
9746
9747/*
9748 * PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE enum
9749 */
9750
9751typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE {
9752PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0x00000000,
9753PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 0x00000001,
9754} PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE;
9755
9756/*
9757 * PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN enum
9758 */
9759
9760typedef enum PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN {
9761PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0x00000000,
9762PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 0x00000001,
9763} PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN;
9764
9765/*******************************************************
9766 * AZCONTROLLER Enums
9767 *******************************************************/
9768
9769/*
9770 * AZ_CORB_SIZE enum
9771 */
9772
9773typedef enum AZ_CORB_SIZE {
9774AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x00000000,
9775AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x00000001,
9776AZ_CORB_SIZE_256ENTRIES = 0x00000002,
9777AZ_CORB_SIZE_RESERVED = 0x00000003,
9778} AZ_CORB_SIZE;
9779
9780/*
9781 * AZ_GLOBAL_CAPABILITIES enum
9782 */
9783
9784typedef enum AZ_GLOBAL_CAPABILITIES {
9785AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0x00000000,
9786AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 0x00000001,
9787} AZ_GLOBAL_CAPABILITIES;
9788
9789/*
9790 * AZ_RIRB_SIZE enum
9791 */
9792
9793typedef enum AZ_RIRB_SIZE {
9794AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x00000000,
9795AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x00000001,
9796AZ_RIRB_SIZE_256ENTRIES = 0x00000002,
9797AZ_RIRB_SIZE_UNDEFINED = 0x00000003,
9798} AZ_RIRB_SIZE;
9799
9800/*
9801 * AZ_RIRB_WRITE_POINTER_RESET enum
9802 */
9803
9804typedef enum AZ_RIRB_WRITE_POINTER_RESET {
9805AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x00000000,
9806AZ_RIRB_WRITE_POINTER_DO_RESET = 0x00000001,
9807} AZ_RIRB_WRITE_POINTER_RESET;
9808
9809/*
9810 * AZ_STATE_CHANGE_STATUS enum
9811 */
9812
9813typedef enum AZ_STATE_CHANGE_STATUS {
9814AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x00000000,
9815AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x00000001,
9816} AZ_STATE_CHANGE_STATUS;
9817
9818/*
9819 * CORB_READ_POINTER_RESET enum
9820 */
9821
9822typedef enum CORB_READ_POINTER_RESET {
9823CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x00000000,
9824CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x00000001,
9825} CORB_READ_POINTER_RESET;
9826
9827/*
9828 * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
9829 */
9830
9831typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
9832DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0x00000000,
9833DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 0x00000001,
9834} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
9835
9836/*
9837 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
9838 */
9839
9840typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
9841GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x00000000,
9842GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x00000001,
9843} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
9844
9845/*
9846 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
9847 */
9848
9849typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
9850GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x00000000,
9851GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x00000001,
9852} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
9853
9854/*
9855 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
9856 */
9857
9858typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
9859GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x00000000,
9860GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x00000001,
9861} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
9862
9863/*
9864 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
9865 */
9866
9867typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
9868GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0x00000000,
9869GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 0x00000001,
9870} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
9871
9872/*
9873 * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
9874 */
9875
9876typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
9877ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x00000000,
9878ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x00000001,
9879} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
9880
9881/*
9882 * GLOBAL_CONTROL_CONTROLLER_RESET enum
9883 */
9884
9885typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
9886CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x00000000,
9887CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x00000001,
9888} GLOBAL_CONTROL_CONTROLLER_RESET;
9889
9890/*
9891 * GLOBAL_CONTROL_FLUSH_CONTROL enum
9892 */
9893
9894typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
9895FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x00000000,
9896FLUSH_CONTROL_FLUSH_STARTED = 0x00000001,
9897} GLOBAL_CONTROL_FLUSH_CONTROL;
9898
9899/*
9900 * GLOBAL_STATUS_FLUSH_STATUS enum
9901 */
9902
9903typedef enum GLOBAL_STATUS_FLUSH_STATUS {
9904GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x00000000,
9905GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x00000001,
9906} GLOBAL_STATUS_FLUSH_STATUS;
9907
9908/*
9909 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
9910 */
9911
9912typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
9913IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0x00000000,
9914IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 0x00000001,
9915} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
9916
9917/*
9918 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
9919 */
9920
9921typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
9922IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0x00000000,
9923IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 0x00000001,
9924} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
9925
9926/*
9927 * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
9928 */
9929
9930typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
9931RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
9932RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
9933} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
9934
9935/*
9936 * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
9937 */
9938
9939typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
9940RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
9941RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
9942} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
9943
9944/*
9945 * STREAM_0_SYNCHRONIZATION enum
9946 */
9947
9948typedef enum STREAM_0_SYNCHRONIZATION {
9949STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
9950STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
9951} STREAM_0_SYNCHRONIZATION;
9952
9953/*
9954 * STREAM_10_SYNCHRONIZATION enum
9955 */
9956
9957typedef enum STREAM_10_SYNCHRONIZATION {
9958STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9959STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9960} STREAM_10_SYNCHRONIZATION;
9961
9962/*
9963 * STREAM_11_SYNCHRONIZATION enum
9964 */
9965
9966typedef enum STREAM_11_SYNCHRONIZATION {
9967STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9968STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9969} STREAM_11_SYNCHRONIZATION;
9970
9971/*
9972 * STREAM_12_SYNCHRONIZATION enum
9973 */
9974
9975typedef enum STREAM_12_SYNCHRONIZATION {
9976STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9977STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9978} STREAM_12_SYNCHRONIZATION;
9979
9980/*
9981 * STREAM_13_SYNCHRONIZATION enum
9982 */
9983
9984typedef enum STREAM_13_SYNCHRONIZATION {
9985STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9986STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9987} STREAM_13_SYNCHRONIZATION;
9988
9989/*
9990 * STREAM_14_SYNCHRONIZATION enum
9991 */
9992
9993typedef enum STREAM_14_SYNCHRONIZATION {
9994STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9995STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9996} STREAM_14_SYNCHRONIZATION;
9997
9998/*
9999 * STREAM_15_SYNCHRONIZATION enum
10000 */
10001
10002typedef enum STREAM_15_SYNCHRONIZATION {
10003STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10004STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10005} STREAM_15_SYNCHRONIZATION;
10006
10007/*
10008 * STREAM_1_SYNCHRONIZATION enum
10009 */
10010
10011typedef enum STREAM_1_SYNCHRONIZATION {
10012STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10013STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10014} STREAM_1_SYNCHRONIZATION;
10015
10016/*
10017 * STREAM_2_SYNCHRONIZATION enum
10018 */
10019
10020typedef enum STREAM_2_SYNCHRONIZATION {
10021STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10022STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10023} STREAM_2_SYNCHRONIZATION;
10024
10025/*
10026 * STREAM_3_SYNCHRONIZATION enum
10027 */
10028
10029typedef enum STREAM_3_SYNCHRONIZATION {
10030STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10031STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10032} STREAM_3_SYNCHRONIZATION;
10033
10034/*
10035 * STREAM_4_SYNCHRONIZATION enum
10036 */
10037
10038typedef enum STREAM_4_SYNCHRONIZATION {
10039STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10040STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10041} STREAM_4_SYNCHRONIZATION;
10042
10043/*
10044 * STREAM_5_SYNCHRONIZATION enum
10045 */
10046
10047typedef enum STREAM_5_SYNCHRONIZATION {
10048STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10049STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10050} STREAM_5_SYNCHRONIZATION;
10051
10052/*
10053 * STREAM_6_SYNCHRONIZATION enum
10054 */
10055
10056typedef enum STREAM_6_SYNCHRONIZATION {
10057STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10058STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10059} STREAM_6_SYNCHRONIZATION;
10060
10061/*
10062 * STREAM_7_SYNCHRONIZATION enum
10063 */
10064
10065typedef enum STREAM_7_SYNCHRONIZATION {
10066STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10067STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10068} STREAM_7_SYNCHRONIZATION;
10069
10070/*
10071 * STREAM_8_SYNCHRONIZATION enum
10072 */
10073
10074typedef enum STREAM_8_SYNCHRONIZATION {
10075STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10076STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10077} STREAM_8_SYNCHRONIZATION;
10078
10079/*
10080 * STREAM_9_SYNCHRONIZATION enum
10081 */
10082
10083typedef enum STREAM_9_SYNCHRONIZATION {
10084STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10085STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10086} STREAM_9_SYNCHRONIZATION;
10087
10088/*******************************************************
10089 * AZENDPOINT Enums
10090 *******************************************************/
10091
10092/*
10093 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10094 */
10095
10096typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10097AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
10098AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
10099AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
10100AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
10101AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
10102AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
10103} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10104
10105/*
10106 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10107 */
10108
10109typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10110AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
10111AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
10112AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
10113AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
10114AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
10115AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
10116AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
10117AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
10118AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
10119} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10120
10121/*
10122 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10123 */
10124
10125typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10126AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
10127AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
10128AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
10129AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
10130AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
10131AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
10132AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
10133AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
10134} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10135
10136/*
10137 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10138 */
10139
10140typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10141AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
10142AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
10143AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
10144AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
10145AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
10146} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10147
10148/*
10149 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10150 */
10151
10152typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10153AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
10154AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
10155} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10156
10157/*
10158 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10159 */
10160
10161typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10162AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
10163AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
10164} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10165
10166/*
10167 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
10168 */
10169
10170typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
10171AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0x00000000,
10172AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 0x00000001,
10173} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
10174
10175/*
10176 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
10177 */
10178
10179typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
10180AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0x00000000,
10181AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 0x00000001,
10182} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
10183
10184/*
10185 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10186 */
10187
10188typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10189AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
10190AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
10191} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10192
10193/*
10194 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
10195 */
10196
10197typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
10198AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0x00000000,
10199AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 0x00000001,
10200} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
10201
10202/*
10203 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
10204 */
10205
10206typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
10207AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0x00000000,
10208AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 0x00000001,
10209} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
10210
10211/*
10212 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
10213 */
10214
10215typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
10216AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0x00000000,
10217AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 0x00000001,
10218} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
10219
10220/*
10221 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
10222 */
10223
10224typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
10225AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0x00000000,
10226AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 0x00000001,
10227} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
10228
10229/*
10230 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
10231 */
10232
10233typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
10234AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0x00000000,
10235AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 0x00000001,
10236} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
10237
10238/*
10239 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
10240 */
10241
10242typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
10243AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0x00000000,
10244AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 0x00000001,
10245} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
10246
10247/*
10248 * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum
10249 */
10250
10251typedef enum AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE {
10252AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0x00000000,
10253AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 0x00000001,
10254AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 0x00000002,
10255AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 0x00000003,
10256AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 0x00000004,
10257AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 0x00000005,
10258AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 0x00000006,
10259AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 0x00000007,
10260AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 0x00000008,
10261AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 0x00000009,
10262AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 0x0000000a,
10263AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 0x0000000b,
10264AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 0x0000000c,
10265AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 0x0000000d,
10266AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 0x0000000e,
10267AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 0x0000000f,
10268} AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE;
10269
10270/*
10271 * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
10272 */
10273
10274typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
10275AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0x00000000,
10276AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x00000001,
10277} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
10278
10279/*
10280 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
10281 */
10282
10283typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
10284AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0x00000000,
10285AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 0x00000001,
10286} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
10287
10288/*
10289 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10290 */
10291
10292typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10293AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
10294AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
10295} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10296
10297/*
10298 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
10299 */
10300
10301typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
10302AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0x00000000,
10303AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 0x00000001,
10304} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
10305
10306/*
10307 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10308 */
10309
10310typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10311AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
10312AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
10313} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10314
10315/*
10316 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
10317 */
10318
10319typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
10320AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0x00000000,
10321AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 0x00000001,
10322} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
10323
10324/*
10325 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10326 */
10327
10328typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10329AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
10330AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
10331} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10332
10333/*
10334 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
10335 */
10336
10337typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
10338AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0x00000000,
10339AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 0x00000001,
10340} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
10341
10342/*
10343 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10344 */
10345
10346typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10347AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
10348AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
10349} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10350
10351/*
10352 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10353 */
10354
10355typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10356AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
10357AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
10358} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
10359
10360/*
10361 * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10362 */
10363
10364typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10365AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
10366AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
10367} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10368
10369/*
10370 * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
10371 */
10372
10373typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
10374AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0x00000000,
10375AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 0x00000001,
10376} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
10377
10378/*******************************************************
10379 * AZF0CONTROLLER Enums
10380 *******************************************************/
10381
10382/*
10383 * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
10384 */
10385
10386typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
10387AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0x00000000,
10388AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 0x00000001,
10389} AZALIA_SOFT_RESET_REFCLK_SOFT_RESET;
10390
10391/*
10392 * MEM_PWR_DIS_CTRL enum
10393 */
10394
10395typedef enum MEM_PWR_DIS_CTRL {
10396ENABLE_MEM_PWR_CTRL = 0x00000000,
10397DISABLE_MEM_PWR_CTRL = 0x00000001,
10398} MEM_PWR_DIS_CTRL;
10399
10400/*
10401 * MEM_PWR_FORCE_CTRL enum
10402 */
10403
10404typedef enum MEM_PWR_FORCE_CTRL {
10405NO_FORCE_REQUEST = 0x00000000,
10406FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
10407FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
10408FORCE_SHUT_DOWN_REQUEST = 0x00000003,
10409} MEM_PWR_FORCE_CTRL;
10410
10411/*
10412 * MEM_PWR_FORCE_CTRL2 enum
10413 */
10414
10415typedef enum MEM_PWR_FORCE_CTRL2 {
10416NO_FORCE_REQ = 0x00000000,
10417FORCE_LIGHT_SLEEP_REQ = 0x00000001,
10418} MEM_PWR_FORCE_CTRL2;
10419
10420/*
10421 * MEM_PWR_SEL_CTRL enum
10422 */
10423
10424typedef enum MEM_PWR_SEL_CTRL {
10425DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
10426DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001,
10427DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002,
10428} MEM_PWR_SEL_CTRL;
10429
10430/*
10431 * MEM_PWR_SEL_CTRL2 enum
10432 */
10433
10434typedef enum MEM_PWR_SEL_CTRL2 {
10435DYNAMIC_DEEP_SLEEP_EN = 0x00000000,
10436DYNAMIC_LIGHT_SLEEP_EN = 0x00000001,
10437} MEM_PWR_SEL_CTRL2;
10438
10439/*******************************************************
10440 * AZF0ROOT Enums
10441 *******************************************************/
10442
10443/*
10444 * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
10445 */
10446
10447typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
10448CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0x00000000,
10449CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 0x00000001,
10450CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 0x00000002,
10451CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 0x00000003,
10452CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 0x00000004,
10453CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 0x00000005,
10454CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 0x00000006,
10455CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 0x00000007,
10456} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
10457
10458/*
10459 * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
10460 */
10461
10462typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
10463CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0x00000000,
10464CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 0x00000001,
10465CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 0x00000002,
10466CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 0x00000003,
10467CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 0x00000004,
10468CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 0x00000005,
10469CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 0x00000006,
10470CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 0x00000007,
10471} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
10472
10473/*******************************************************
10474 * AZINPUTENDPOINT Enums
10475 *******************************************************/
10476
10477/*
10478 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10479 */
10480
10481typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10482AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
10483AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
10484AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
10485AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
10486AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
10487AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
10488} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10489
10490/*
10491 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10492 */
10493
10494typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10495AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
10496AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
10497AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
10498AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
10499AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
10500AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
10501AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
10502AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
10503AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
10504} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10505
10506/*
10507 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10508 */
10509
10510typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10511AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
10512AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
10513AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
10514AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
10515AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
10516AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
10517AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
10518AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
10519} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10520
10521/*
10522 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10523 */
10524
10525typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10526AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
10527AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
10528AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
10529AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
10530AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
10531} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10532
10533/*
10534 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10535 */
10536
10537typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10538AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
10539AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
10540} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10541
10542/*
10543 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10544 */
10545
10546typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10547AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
10548AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
10549} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10550
10551/*
10552 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10553 */
10554
10555typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10556AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
10557AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
10558} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10559
10560/*
10561 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
10562 */
10563
10564typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
10565AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0x00000000,
10566AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 0x00000001,
10567} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
10568
10569/*
10570 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10571 */
10572
10573typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10574AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
10575AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
10576} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10577
10578/*
10579 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
10580 */
10581
10582typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
10583AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0x00000000,
10584AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 0x00000001,
10585} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
10586
10587/*
10588 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10589 */
10590
10591typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10592AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
10593AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
10594} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10595
10596/*
10597 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
10598 */
10599
10600typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
10601AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0x00000000,
10602AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 0x00000001,
10603} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
10604
10605/*
10606 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10607 */
10608
10609typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10610AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
10611AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
10612} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10613
10614/*
10615 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
10616 */
10617
10618typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
10619AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0x00000000,
10620AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 0x00000001,
10621} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
10622
10623/*
10624 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10625 */
10626
10627typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10628AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
10629AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
10630} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10631
10632/*
10633 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10634 */
10635
10636typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10637AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
10638AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
10639} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10640
10641/*
10642 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
10643 */
10644
10645typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
10646AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0x00000000,
10647AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 0x00000001,
10648} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
10649
10650/*******************************************************
10651 * AZROOT Enums
10652 *******************************************************/
10653
10654/*
10655 * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
10656 */
10657
10658typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
10659AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0x00000000,
10660AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 0x00000001,
10661} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
10662
10663/*******************************************************
10664 * AZF0STREAM Enums
10665 *******************************************************/
10666
10667/*
10668 * AZ_LATENCY_COUNTER_CONTROL enum
10669 */
10670
10671typedef enum AZ_LATENCY_COUNTER_CONTROL {
10672AZ_LATENCY_COUNTER_NO_RESET = 0x00000000,
10673AZ_LATENCY_COUNTER_RESET_DONE = 0x00000001,
10674} AZ_LATENCY_COUNTER_CONTROL;
10675
10676/*******************************************************
10677 * AZSTREAM Enums
10678 *******************************************************/
10679
10680/*
10681 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
10682 */
10683
10684typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
10685OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000,
10686OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001,
10687} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
10688
10689/*
10690 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
10691 */
10692
10693typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
10694OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000,
10695OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001,
10696} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
10697
10698/*
10699 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
10700 */
10701
10702typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
10703OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000,
10704OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001,
10705} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
10706
10707/*
10708 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
10709 */
10710
10711typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
10712OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000,
10713OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001,
10714} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
10715
10716/*
10717 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
10718 */
10719
10720typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
10721OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000,
10722OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001,
10723} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
10724
10725/*
10726 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
10727 */
10728
10729typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
10730OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000,
10731OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001,
10732} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
10733
10734/*
10735 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
10736 */
10737
10738typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
10739OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000,
10740OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001,
10741} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
10742
10743/*
10744 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
10745 */
10746
10747typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
10748OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000,
10749OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001,
10750} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
10751
10752/*
10753 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
10754 */
10755
10756typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
10757OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000,
10758OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001,
10759} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
10760
10761/*
10762 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
10763 */
10764
10765typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
10766OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
10767OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
10768OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
10769OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
10770OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
10771OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
10772} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
10773
10774/*
10775 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
10776 */
10777
10778typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
10779OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
10780OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
10781OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
10782OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
10783OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
10784OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
10785OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
10786OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
10787OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008,
10788OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009,
10789OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a,
10790OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b,
10791OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c,
10792OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d,
10793OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e,
10794OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f,
10795} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
10796
10797/*
10798 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
10799 */
10800
10801typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
10802OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
10803OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
10804OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
10805OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
10806OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
10807OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
10808OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
10809OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
10810} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
10811
10812/*
10813 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
10814 */
10815
10816typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
10817OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
10818OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
10819OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
10820OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
10821OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
10822} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
10823
10824/*
10825 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
10826 */
10827
10828typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
10829OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
10830OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
10831} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
10832
10833/*******************************************************
10834 * AZF0ENDPOINT Enums
10835 *******************************************************/
10836
10837/*
10838 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10839 */
10840
10841typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
10842AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
10843AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
10844} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
10845
10846/*
10847 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
10848 */
10849
10850typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
10851AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
10852AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
10853} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
10854
10855/*
10856 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10857 */
10858
10859typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10860AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
10861AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
10862} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
10863
10864/*
10865 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10866 */
10867
10868typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10869AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
10870AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
10871} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
10872
10873/*
10874 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
10875 */
10876
10877typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
10878AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
10879AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 0x00000001,
10880} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
10881
10882/*
10883 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10884 */
10885
10886typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
10887AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
10888AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
10889} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
10890
10891/*
10892 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
10893 */
10894
10895typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
10896AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
10897AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
10898} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
10899
10900/*
10901 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10902 */
10903
10904typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
10905AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
10906AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
10907} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
10908
10909/*
10910 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
10911 */
10912
10913typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10914AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
10915AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
10916} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
10917
10918/*
10919 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10920 */
10921
10922typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10923AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
10924AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
10925} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
10926
10927/*
10928 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10929 */
10930
10931typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10932AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
10933AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
10934} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
10935
10936/*
10937 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
10938 */
10939
10940typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
10941AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
10942AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
10943AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
10944AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
10945AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
10946AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
10947AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
10948AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
10949AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
10950AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
10951} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
10952
10953/*
10954 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10955 */
10956
10957typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
10958AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
10959AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
10960} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
10961
10962/*
10963 * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10964 */
10965
10966typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10967AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
10968AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
10969} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
10970
10971/*
10972 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
10973 */
10974
10975typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
10976AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0x00000000,
10977AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 0x00000001,
10978} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
10979
10980/*
10981 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10982 */
10983
10984typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
10985AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
10986AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
10987} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
10988
10989/*
10990 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10991 */
10992
10993typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10994AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
10995AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
10996} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
10997
10998/*
10999 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11000 */
11001
11002typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11003AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
11004AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
11005} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
11006
11007/*
11008 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11009 */
11010
11011typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11012AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0x00000000,
11013AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
11014} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
11015
11016/*
11017 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11018 */
11019
11020typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11021AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
11022AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
11023} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
11024
11025/*
11026 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11027 */
11028
11029typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
11030AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
11031AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
11032} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
11033
11034/*
11035 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11036 */
11037
11038typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11039AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
11040AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
11041} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
11042
11043/*
11044 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11045 */
11046
11047typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11048AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
11049AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
11050} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
11051
11052/*
11053 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11054 */
11055
11056typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11057AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
11058AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
11059} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
11060
11061/*
11062 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11063 */
11064
11065typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11066AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
11067AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
11068AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
11069AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
11070AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
11071AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
11072AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
11073AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
11074AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
11075AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
11076} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
11077
11078/*
11079 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11080 */
11081
11082typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
11083AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
11084AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
11085} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
11086
11087/*
11088 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
11089 */
11090
11091typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
11092AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0x00000000,
11093AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
11094} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
11095
11096/*
11097 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
11098 */
11099
11100typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
11101AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0x00000000,
11102AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 0x00000001,
11103} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
11104
11105/*
11106 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
11107 */
11108
11109typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
11110AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
11111AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
11112} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
11113
11114/*
11115 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
11116 */
11117
11118typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
11119AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
11120AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
11121} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
11122
11123/*
11124 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
11125 */
11126
11127typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
11128AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
11129AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
11130} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
11131
11132/*
11133 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
11134 */
11135
11136typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
11137AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0x00000000,
11138AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 0x00000001,
11139} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
11140
11141/*
11142 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
11143 */
11144
11145typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
11146AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
11147AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
11148} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
11149
11150/*
11151 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
11152 */
11153
11154typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
11155AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
11156AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
11157} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
11158
11159/*******************************************************
11160 * AZF0INPUTENDPOINT Enums
11161 *******************************************************/
11162
11163/*
11164 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11165 */
11166
11167typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
11168AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
11169AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 0x00000001,
11170} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
11171
11172/*
11173 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
11174 */
11175
11176typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
11177AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
11178AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
11179} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
11180
11181/*
11182 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11183 */
11184
11185typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11186AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
11187AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
11188} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
11189
11190/*
11191 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11192 */
11193
11194typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11195AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0x00000000,
11196AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 0x00000001,
11197} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
11198
11199/*
11200 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
11201 */
11202
11203typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
11204AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
11205AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 0x00000001,
11206} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
11207
11208/*
11209 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11210 */
11211
11212typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11213AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
11214AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
11215} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
11216
11217/*
11218 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11219 */
11220
11221typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11222AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
11223AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
11224} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
11225
11226/*
11227 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11228 */
11229
11230typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
11231AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
11232AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
11233} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
11234
11235/*
11236 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11237 */
11238
11239typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11240AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
11241AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
11242} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
11243
11244/*
11245 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11246 */
11247
11248typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11249AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0x00000000,
11250AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
11251} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
11252
11253/*
11254 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11255 */
11256
11257typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11258AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0x00000000,
11259AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
11260} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
11261
11262/*
11263 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11264 */
11265
11266typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11267AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
11268AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
11269AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
11270AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
11271AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
11272AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
11273AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
11274AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
11275AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
11276AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
11277} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
11278
11279/*
11280 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11281 */
11282
11283typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
11284AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
11285AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
11286} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
11287
11288/*
11289 * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
11290 */
11291
11292typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
11293AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0x00000000,
11294AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 0x00000001,
11295} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
11296
11297/*
11298 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11299 */
11300
11301typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
11302AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
11303AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
11304} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
11305
11306/*
11307 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11308 */
11309
11310typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11311AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
11312AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
11313} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
11314
11315/*
11316 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11317 */
11318
11319typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11320AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
11321AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
11322} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
11323
11324/*
11325 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11326 */
11327
11328typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11329AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
11330AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
11331} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
11332
11333/*
11334 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11335 */
11336
11337typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11338AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0x00000000,
11339AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 0x00000001,
11340} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
11341
11342/*
11343 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11344 */
11345
11346typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
11347AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
11348AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
11349} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
11350
11351/*
11352 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11353 */
11354
11355typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11356AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
11357AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
11358} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
11359
11360/*
11361 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11362 */
11363
11364typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11365AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0x00000000,
11366AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 0x00000001,
11367} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
11368
11369/*
11370 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11371 */
11372
11373typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11374AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
11375AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
11376} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
11377
11378/*
11379 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11380 */
11381
11382typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11383AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
11384AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
11385AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
11386AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
11387AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
11388AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
11389AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
11390AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
11391AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
11392AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
11393} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
11394
11395/*
11396 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11397 */
11398
11399typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
11400AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
11401AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
11402} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
11403
11404/*
11405 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
11406 */
11407
11408typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
11409AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0x00000000,
11410AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
11411} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
11412
11413/*
11414 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
11415 */
11416
11417typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
11418AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0x00000000,
11419AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 0x00000001,
11420} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
11421
11422/*
11423 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
11424 */
11425
11426typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
11427AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0x00000000,
11428AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 0x00000001,
11429} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
11430
11431/*
11432 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
11433 */
11434
11435typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
11436AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0x00000000,
11437AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 0x00000001,
11438} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
11439
11440/*
11441 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
11442 */
11443
11444typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
11445AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
11446AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
11447} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
11448
11449/*
11450 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
11451 */
11452
11453typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
11454AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
11455AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
11456} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
11457
11458/*
11459 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
11460 */
11461
11462typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
11463AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
11464AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
11465} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
11466
11467/*
11468 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
11469 */
11470
11471typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
11472AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000000,
11473AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000001,
11474} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
11475
11476/*
11477 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
11478 */
11479
11480typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
11481AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
11482AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
11483} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
11484
11485/*
11486 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
11487 */
11488
11489typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
11490AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
11491AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
11492} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
11493
11494/*******************************************************
11495 * DSCC Enums
11496 *******************************************************/
11497
11498/*
11499 * DSCC_BITS_PER_COMPONENT_ENUM enum
11500 */
11501
11502typedef enum DSCC_BITS_PER_COMPONENT_ENUM {
11503DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008,
11504DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a,
11505DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c,
11506} DSCC_BITS_PER_COMPONENT_ENUM;
11507
11508/*
11509 * DSCC_DSC_VERSION_MAJOR_ENUM enum
11510 */
11511
11512typedef enum DSCC_DSC_VERSION_MAJOR_ENUM {
11513DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 0x00000001,
11514} DSCC_DSC_VERSION_MAJOR_ENUM;
11515
11516/*
11517 * DSCC_DSC_VERSION_MINOR_ENUM enum
11518 */
11519
11520typedef enum DSCC_DSC_VERSION_MINOR_ENUM {
11521DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 0x00000001,
11522DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 0x00000002,
11523} DSCC_DSC_VERSION_MINOR_ENUM;
11524
11525/*
11526 * DSCC_ENABLE_ENUM enum
11527 */
11528
11529typedef enum DSCC_ENABLE_ENUM {
11530DSCC_ENABLE_ENUM_DISABLED = 0x00000000,
11531DSCC_ENABLE_ENUM_ENABLED = 0x00000001,
11532} DSCC_ENABLE_ENUM;
11533
11534/*
11535 * DSCC_ICH_RESET_ENUM enum
11536 */
11537
11538typedef enum DSCC_ICH_RESET_ENUM {
11539DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 0x00000001,
11540DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 0x00000002,
11541DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 0x00000004,
11542DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 0x00000008,
11543} DSCC_ICH_RESET_ENUM;
11544
11545/*
11546 * DSCC_LINEBUF_DEPTH_ENUM enum
11547 */
11548
11549typedef enum DSCC_LINEBUF_DEPTH_ENUM {
11550DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 0x00000008,
11551DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 0x00000009,
11552DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 0x0000000a,
11553DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 0x0000000b,
11554DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 0x0000000c,
11555DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 0x0000000d,
11556} DSCC_LINEBUF_DEPTH_ENUM;
11557
11558/*
11559 * DSCC_MEM_PWR_DIS_ENUM enum
11560 */
11561
11562typedef enum DSCC_MEM_PWR_DIS_ENUM {
11563DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0x00000000,
11564DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 0x00000001,
11565} DSCC_MEM_PWR_DIS_ENUM;
11566
11567/*
11568 * DSCC_MEM_PWR_FORCE_ENUM enum
11569 */
11570
11571typedef enum DSCC_MEM_PWR_FORCE_ENUM {
11572DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0x00000000,
11573DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
11574DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
11575DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
11576} DSCC_MEM_PWR_FORCE_ENUM;
11577
11578/*
11579 * POWER_STATE_ENUM enum
11580 */
11581
11582typedef enum POWER_STATE_ENUM {
11583POWER_STATE_ENUM_ON = 0x00000000,
11584POWER_STATE_ENUM_LS = 0x00000001,
11585POWER_STATE_ENUM_DS = 0x00000002,
11586POWER_STATE_ENUM_SD = 0x00000003,
11587} POWER_STATE_ENUM;
11588
11589/*******************************************************
11590 * DSCCIF Enums
11591 *******************************************************/
11592
11593/*
11594 * DSCCIF_BITS_PER_COMPONENT_ENUM enum
11595 */
11596
11597typedef enum DSCCIF_BITS_PER_COMPONENT_ENUM {
11598DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008,
11599DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a,
11600DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c,
11601} DSCCIF_BITS_PER_COMPONENT_ENUM;
11602
11603/*
11604 * DSCCIF_ENABLE_ENUM enum
11605 */
11606
11607typedef enum DSCCIF_ENABLE_ENUM {
11608DSCCIF_ENABLE_ENUM_DISABLED = 0x00000000,
11609DSCCIF_ENABLE_ENUM_ENABLED = 0x00000001,
11610} DSCCIF_ENABLE_ENUM;
11611
11612/*
11613 * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum
11614 */
11615
11616typedef enum DSCCIF_INPUT_PIXEL_FORMAT_ENUM {
11617DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0x00000000,
11618DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 0x00000001,
11619DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 0x00000002,
11620DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 0x00000003,
11621DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 0x00000004,
11622} DSCCIF_INPUT_PIXEL_FORMAT_ENUM;
11623
11624/*******************************************************
11625 * DSC_TOP Enums
11626 *******************************************************/
11627
11628/*
11629 * CLOCK_GATING_DISABLE_ENUM enum
11630 */
11631
11632typedef enum CLOCK_GATING_DISABLE_ENUM {
11633CLOCK_GATING_DISABLE_ENUM_ENABLED = 0x00000000,
11634CLOCK_GATING_DISABLE_ENUM_DISABLED = 0x00000001,
11635} CLOCK_GATING_DISABLE_ENUM;
11636
11637/*
11638 * ENABLE_ENUM enum
11639 */
11640
11641typedef enum ENABLE_ENUM {
11642ENABLE_ENUM_DISABLED = 0x00000000,
11643ENABLE_ENUM_ENABLED = 0x00000001,
11644} ENABLE_ENUM;
11645
11646/*
11647 * TEST_CLOCK_MUX_SELECT_ENUM enum
11648 */
11649
11650typedef enum TEST_CLOCK_MUX_SELECT_ENUM {
11651TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0x00000000,
11652TEST_CLOCK_MUX_SELECT_DISPCLK_G = 0x00000001,
11653TEST_CLOCK_MUX_SELECT_DISPCLK_R = 0x00000002,
11654TEST_CLOCK_MUX_SELECT_DSCCLK_P = 0x00000003,
11655TEST_CLOCK_MUX_SELECT_DSCCLK_G = 0x00000004,
11656TEST_CLOCK_MUX_SELECT_DSCCLK_R = 0x00000005,
11657TEST_CLOCK_MUX_SELECT_DSCCLK_D = 0x00000006,
11658} TEST_CLOCK_MUX_SELECT_ENUM;
11659
11660/*******************************************************
11661 * DWB_TOP Enums
11662 *******************************************************/
11663
11664/*
11665 * DWB_CRC_CONT_EN_ENUM enum
11666 */
11667
11668typedef enum DWB_CRC_CONT_EN_ENUM {
11669DWB_CRC_CONT_EN_ONE_SHOT = 0x00000000,
11670DWB_CRC_CONT_EN_CONT = 0x00000001,
11671} DWB_CRC_CONT_EN_ENUM;
11672
11673/*
11674 * DWB_CRC_SRC_SEL_ENUM enum
11675 */
11676
11677typedef enum DWB_CRC_SRC_SEL_ENUM {
11678DWB_CRC_SRC_SEL_DWB_IN = 0x00000000,
11679DWB_CRC_SRC_SEL_OGAM_OUT = 0x00000001,
11680DWB_CRC_SRC_SEL_DWB_OUT = 0x00000002,
11681} DWB_CRC_SRC_SEL_ENUM;
11682
11683/*
11684 * DWB_DATA_OVERFLOW_INT_TYPE_ENUM enum
11685 */
11686
11687typedef enum DWB_DATA_OVERFLOW_INT_TYPE_ENUM {
11688DWB_DATA_OVERFLOW_INT_TYPE_0 = 0x00000000,
11689DWB_DATA_OVERFLOW_INT_TYPE_1 = 0x00000001,
11690} DWB_DATA_OVERFLOW_INT_TYPE_ENUM;
11691
11692/*
11693 * DWB_DATA_OVERFLOW_TYPE_ENUM enum
11694 */
11695
11696typedef enum DWB_DATA_OVERFLOW_TYPE_ENUM {
11697DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0x00000000,
11698DWB_DATA_OVERFLOW_TYPE_BUFFER = 0x00000001,
11699DWB_DATA_OVERFLOW_TYPE_VUPDATE = 0x00000002,
11700DWB_DATA_OVERFLOW_TYPE_VREADY = 0x00000003,
11701} DWB_DATA_OVERFLOW_TYPE_ENUM;
11702
11703/*
11704 * DWB_DEBUG_SEL_ENUM enum
11705 */
11706
11707typedef enum DWB_DEBUG_SEL_ENUM {
11708DWB_DEBUG_SEL_FC = 0x00000000,
11709DWB_DEBUG_SEL_RESERVED = 0x00000001,
11710DWB_DEBUG_SEL_DWBCP = 0x00000002,
11711DWB_DEBUG_SEL_PERFMON = 0x00000003,
11712} DWB_DEBUG_SEL_ENUM;
11713
11714/*
11715 * DWB_MEM_PWR_FORCE_ENUM enum
11716 */
11717
11718typedef enum DWB_MEM_PWR_FORCE_ENUM {
11719DWB_MEM_PWR_FORCE_DIS = 0x00000000,
11720DWB_MEM_PWR_FORCE_LS = 0x00000001,
11721DWB_MEM_PWR_FORCE_DS = 0x00000002,
11722DWB_MEM_PWR_FORCE_SD = 0x00000003,
11723} DWB_MEM_PWR_FORCE_ENUM;
11724
11725/*
11726 * DWB_MEM_PWR_STATE_ENUM enum
11727 */
11728
11729typedef enum DWB_MEM_PWR_STATE_ENUM {
11730DWB_MEM_PWR_STATE_ON = 0x00000000,
11731DWB_MEM_PWR_STATE_LS = 0x00000001,
11732DWB_MEM_PWR_STATE_DS = 0x00000002,
11733DWB_MEM_PWR_STATE_SD = 0x00000003,
11734} DWB_MEM_PWR_STATE_ENUM;
11735
11736/*
11737 * DWB_TEST_CLK_SEL_ENUM enum
11738 */
11739
11740typedef enum DWB_TEST_CLK_SEL_ENUM {
11741DWB_TEST_CLK_SEL_R = 0x00000000,
11742DWB_TEST_CLK_SEL_G = 0x00000001,
11743DWB_TEST_CLK_SEL_P = 0x00000002,
11744} DWB_TEST_CLK_SEL_ENUM;
11745
11746/*
11747 * FC_EYE_SELECTION_ENUM enum
11748 */
11749
11750typedef enum FC_EYE_SELECTION_ENUM {
11751FC_EYE_SELECTION_STEREO_DIS = 0x00000000,
11752FC_EYE_SELECTION_LEFT_EYE = 0x00000001,
11753FC_EYE_SELECTION_RIGHT_EYE = 0x00000002,
11754} FC_EYE_SELECTION_ENUM;
11755
11756/*
11757 * FC_FRAME_CAPTURE_RATE_ENUM enum
11758 */
11759
11760typedef enum FC_FRAME_CAPTURE_RATE_ENUM {
11761FC_FRAME_CAPTURE_RATE_FULL = 0x00000000,
11762FC_FRAME_CAPTURE_RATE_HALF = 0x00000001,
11763FC_FRAME_CAPTURE_RATE_THIRD = 0x00000002,
11764FC_FRAME_CAPTURE_RATE_QUARTER = 0x00000003,
11765} FC_FRAME_CAPTURE_RATE_ENUM;
11766
11767/*
11768 * FC_STEREO_EYE_POLARITY_ENUM enum
11769 */
11770
11771typedef enum FC_STEREO_EYE_POLARITY_ENUM {
11772FC_STEREO_EYE_POLARITY_LEFT = 0x00000000,
11773FC_STEREO_EYE_POLARITY_RIGHT = 0x00000001,
11774} FC_STEREO_EYE_POLARITY_ENUM;
11775
11776/*******************************************************
11777 * DWBCP Enums
11778 *******************************************************/
11779
11780/*
11781 * DWB_GAMUT_REMAP_COEF_FORMAT_ENUM enum
11782 */
11783
11784typedef enum DWB_GAMUT_REMAP_COEF_FORMAT_ENUM {
11785DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0x00000000,
11786DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 0x00000001,
11787} DWB_GAMUT_REMAP_COEF_FORMAT_ENUM;
11788
11789/*
11790 * DWB_GAMUT_REMAP_MODE_ENUM enum
11791 */
11792
11793typedef enum DWB_GAMUT_REMAP_MODE_ENUM {
11794DWB_GAMUT_REMAP_MODE_BYPASS = 0x00000000,
11795DWB_GAMUT_REMAP_MODE_COEF_A = 0x00000001,
11796DWB_GAMUT_REMAP_MODE_COEF_B = 0x00000002,
11797DWB_GAMUT_REMAP_MODE_RESERVED = 0x00000003,
11798} DWB_GAMUT_REMAP_MODE_ENUM;
11799
11800/*
11801 * DWB_LUT_NUM_SEG enum
11802 */
11803
11804typedef enum DWB_LUT_NUM_SEG {
11805DWB_SEGMENTS_1 = 0x00000000,
11806DWB_SEGMENTS_2 = 0x00000001,
11807DWB_SEGMENTS_4 = 0x00000002,
11808DWB_SEGMENTS_8 = 0x00000003,
11809DWB_SEGMENTS_16 = 0x00000004,
11810DWB_SEGMENTS_32 = 0x00000005,
11811DWB_SEGMENTS_64 = 0x00000006,
11812DWB_SEGMENTS_128 = 0x00000007,
11813} DWB_LUT_NUM_SEG;
11814
11815/*
11816 * DWB_OGAM_LUT_CONFIG_MODE_ENUM enum
11817 */
11818
11819typedef enum DWB_OGAM_LUT_CONFIG_MODE_ENUM {
11820DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0x00000000,
11821DWB_OGAM_LUT_CONFIG_MODE_SAME = 0x00000001,
11822} DWB_OGAM_LUT_CONFIG_MODE_ENUM;
11823
11824/*
11825 * DWB_OGAM_LUT_HOST_SEL_ENUM enum
11826 */
11827
11828typedef enum DWB_OGAM_LUT_HOST_SEL_ENUM {
11829DWB_OGAM_LUT_HOST_SEL_RAMA = 0x00000000,
11830DWB_OGAM_LUT_HOST_SEL_RAMB = 0x00000001,
11831} DWB_OGAM_LUT_HOST_SEL_ENUM;
11832
11833/*
11834 * DWB_OGAM_LUT_READ_COLOR_SEL_ENUM enum
11835 */
11836
11837typedef enum DWB_OGAM_LUT_READ_COLOR_SEL_ENUM {
11838DWB_OGAM_LUT_READ_COLOR_SEL_B = 0x00000000,
11839DWB_OGAM_LUT_READ_COLOR_SEL_G = 0x00000001,
11840DWB_OGAM_LUT_READ_COLOR_SEL_R = 0x00000002,
11841DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 0x00000003,
11842} DWB_OGAM_LUT_READ_COLOR_SEL_ENUM;
11843
11844/*
11845 * DWB_OGAM_LUT_READ_DBG_ENUM enum
11846 */
11847
11848typedef enum DWB_OGAM_LUT_READ_DBG_ENUM {
11849DWB_OGAM_LUT_READ_DBG_DISABLE = 0x00000000,
11850DWB_OGAM_LUT_READ_DBG_ENABLE = 0x00000001,
11851} DWB_OGAM_LUT_READ_DBG_ENUM;
11852
11853/*
11854 * DWB_OGAM_MODE_ENUM enum
11855 */
11856
11857typedef enum DWB_OGAM_MODE_ENUM {
11858DWB_OGAM_MODE_BYPASS = 0x00000000,
11859DWB_OGAM_MODE_RESERVED = 0x00000001,
11860DWB_OGAM_MODE_RAM_LUT_ENABLED = 0x00000002,
11861} DWB_OGAM_MODE_ENUM;
11862
11863/*
11864 * DWB_OGAM_PWL_DISABLE_ENUM enum
11865 */
11866
11867typedef enum DWB_OGAM_PWL_DISABLE_ENUM {
11868DWB_OGAM_PWL_DISABLE_FALSE = 0x00000000,
11869DWB_OGAM_PWL_DISABLE_TRUE = 0x00000001,
11870} DWB_OGAM_PWL_DISABLE_ENUM;
11871
11872/*
11873 * DWB_OGAM_SELECT_ENUM enum
11874 */
11875
11876typedef enum DWB_OGAM_SELECT_ENUM {
11877DWB_OGAM_SELECT_A = 0x00000000,
11878DWB_OGAM_SELECT_B = 0x00000001,
11879} DWB_OGAM_SELECT_ENUM;
11880
11881/*******************************************************
11882 * RDPCSTX Enums
11883 *******************************************************/
11884
11885/*
11886 * RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN enum
11887 */
11888
11889typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN {
11890RDPCS_EXT_REFCLK_DISABLE = 0x00000000,
11891RDPCS_EXT_REFCLK_ENABLE = 0x00000001,
11892} RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN;
11893
11894/*
11895 * RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON enum
11896 */
11897
11898typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON {
11899RDPCS_OCLACLK_CLOCK_OFF = 0x00000000,
11900RDPCS_OCLACLK_CLOCK_ON = 0x00000001,
11901} RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_CLOCK_ON;
11902
11903/*
11904 * RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN enum
11905 */
11906
11907typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN {
11908RDPCS_OCLACLK_DISABLE = 0x00000000,
11909RDPCS_OCLACLK_ENABLE = 0x00000001,
11910} RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_EN;
11911
11912/*
11913 * RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS enum
11914 */
11915
11916typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS {
11917RDPCS_OCLACLK_GATE_ENABLE = 0x00000000,
11918RDPCS_OCLACLK_GATE_DISABLE = 0x00000001,
11919} RDPCSTX_CLOCK_CNTL_RDPCS_OCLACLK_GATE_DIS;
11920
11921/*
11922 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum
11923 */
11924
11925typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON {
11926RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF = 0x00000000,
11927RDPCS_SYMCLK_SRAMCLK_CLOCK_ON = 0x00000001,
11928} RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON;
11929
11930/*
11931 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum
11932 */
11933
11934typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN {
11935RDPCS_SRAMCLK_DISABLE = 0x00000000,
11936RDPCS_SRAMCLK_ENABLE = 0x00000001,
11937} RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN;
11938
11939/*
11940 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum
11941 */
11942
11943typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS {
11944RDPCS_SRAMCLK_GATE_ENABLE = 0x00000000,
11945RDPCS_SRAMCLK_GATE_DISABLE = 0x00000001,
11946} RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS;
11947
11948/*
11949 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS enum
11950 */
11951
11952typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS {
11953RDPCS_SRAMCLK_NOT_PASS = 0x00000000,
11954RDPCS_SRAMCLK_PASS = 0x00000001,
11955} RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_PASS;
11956
11957/*
11958 * RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON enum
11959 */
11960
11961typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON {
11962RDPCS_TX_CLK_CLOCK_OFF = 0x00000000,
11963RDPCS_TX_CLK_CLOCK_ON = 0x00000001,
11964} RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_CLOCK_ON;
11965
11966/*
11967 * RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN enum
11968 */
11969
11970typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN {
11971RDPCS_TX_CLK_DISABLE = 0x00000000,
11972RDPCS_TX_CLK_ENABLE = 0x00000001,
11973} RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_EN;
11974
11975/*
11976 * RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS enum
11977 */
11978
11979typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS {
11980RDPCS_TX_CLK_GATE_ENABLE = 0x00000000,
11981RDPCS_TX_CLK_GATE_DISABLE = 0x00000001,
11982} RDPCSTX_CLOCK_CNTL_RDPCS_TX_CLK_GATE_DIS;
11983
11984/*
11985 * RDPCSTX_CLOCK_CNTL_TX_CLK_EN enum
11986 */
11987
11988typedef enum RDPCSTX_CLOCK_CNTL_TX_CLK_EN {
11989RDPCS_EXT_REFCLK_EN_DISABLE = 0x00000000,
11990RDPCS_EXT_REFCLK_EN_ENABLE = 0x00000001,
11991} RDPCSTX_CLOCK_CNTL_TX_CLK_EN;
11992
11993/*
11994 * RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET enum
11995 */
11996
11997typedef enum RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET {
11998RDPCS_CBUS_SOFT_RESET_DISABLE = 0x00000000,
11999RDPCS_CBUS_SOFT_RESET_ENABLE = 0x00000001,
12000} RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET;
12001
12002/*
12003 * RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET enum
12004 */
12005
12006typedef enum RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET {
12007RDPCS_SRAM_SRAM_RESET_DISABLE = 0x00000000,
12008RDPCS_SRAM_SRAM_RESET_ENABLE = 0x00000001,
12009} RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET;
12010
12011/*
12012 * RDPCSTX_CNTL_RDPCS_TX_FIFO_EN enum
12013 */
12014
12015typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_EN {
12016RDPCS_TX_FIFO_DISABLE = 0x00000000,
12017RDPCS_TX_FIFO_ENABLE = 0x00000001,
12018} RDPCSTX_CNTL_RDPCS_TX_FIFO_EN;
12019
12020/*
12021 * RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN enum
12022 */
12023
12024typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN {
12025RDPCS_TX_FIFO_LANE_DISABLE = 0x00000000,
12026RDPCS_TX_FIFO_LANE_ENABLE = 0x00000001,
12027} RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN;
12028
12029/*
12030 * RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET enum
12031 */
12032
12033typedef enum RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET {
12034RDPCS_TX_SOFT_RESET_DISABLE = 0x00000000,
12035RDPCS_TX_SOFT_RESET_ENABLE = 0x00000001,
12036} RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET;
12037
12038/*
12039 * RDPCSTX_FIFO_EMPTY enum
12040 */
12041
12042typedef enum RDPCSTX_FIFO_EMPTY {
12043RDPCSTX_FIFO_NOT_EMPTY = 0x00000000,
12044RDPCSTX_FIFO_IS_EMPTY = 0x00000001,
12045} RDPCSTX_FIFO_EMPTY;
12046
12047/*
12048 * RDPCSTX_FIFO_FULL enum
12049 */
12050
12051typedef enum RDPCSTX_FIFO_FULL {
12052RDPCSTX_FIFO_NOT_FULL = 0x00000000,
12053RDPCSTX_FIFO_IS_FULL = 0x00000001,
12054} RDPCSTX_FIFO_FULL;
12055
12056/*
12057 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum
12058 */
12059
12060typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE {
12061RDPCS_DPALT_4LANE_TOGGLE_2LANE = 0x00000000,
12062RDPCS_DPALT_4LANE_TOGGLE_4LANE = 0x00000001,
12063} RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE;
12064
12065/*
12066 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum
12067 */
12068
12069typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK {
12070RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0x00000000,
12071RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE = 0x00000001,
12072} RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK;
12073
12074/*
12075 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum
12076 */
12077
12078typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE {
12079RDPCS_DPALT_DISABLE_TOGGLE_ENABLE = 0x00000000,
12080RDPCS_DPALT_DISABLE_TOGGLE_DISABLE = 0x00000001,
12081} RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE;
12082
12083/*
12084 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum
12085 */
12086
12087typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK {
12088RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0x00000000,
12089RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 0x00000001,
12090} RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK;
12091
12092/*
12093 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum
12094 */
12095
12096typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK {
12097RDPCS_REG_FIFO_ERROR_MASK_DISABLE = 0x00000000,
12098RDPCS_REG_FIFO_ERROR_MASK_ENABLE = 0x00000001,
12099} RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK;
12100
12101/*
12102 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK enum
12103 */
12104
12105typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK {
12106RDPCS_TX_FIFO_ERROR_MASK_DISABLE = 0x00000000,
12107RDPCS_TX_FIFO_ERROR_MASK_ENABLE = 0x00000001,
12108} RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK;
12109
12110/*
12111 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL enum
12112 */
12113
12114typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL {
12115RDPCS_PHY_CR_MUX_SEL_FOR_USB = 0x00000000,
12116RDPCS_PHY_CR_MUX_SEL_FOR_DC = 0x00000001,
12117} RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL;
12118
12119/*
12120 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum
12121 */
12122
12123typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL {
12124RDPCS_PHY_CR_PARA_SEL_JTAG = 0x00000000,
12125RDPCS_PHY_CR_PARA_SEL_CR = 0x00000001,
12126} RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL;
12127
12128/*
12129 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum
12130 */
12131
12132typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE {
12133RDPCS_PHY_REF_RANGE_0 = 0x00000000,
12134RDPCS_PHY_REF_RANGE_1 = 0x00000001,
12135RDPCS_PHY_REF_RANGE_2 = 0x00000002,
12136RDPCS_PHY_REF_RANGE_3 = 0x00000003,
12137RDPCS_PHY_REF_RANGE_4 = 0x00000004,
12138RDPCS_PHY_REF_RANGE_5 = 0x00000005,
12139RDPCS_PHY_REF_RANGE_6 = 0x00000006,
12140RDPCS_PHY_REF_RANGE_7 = 0x00000007,
12141} RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE;
12142
12143/*
12144 * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE enum
12145 */
12146
12147typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE {
12148RDPCS_SRAM_EXT_LD_NOT_DONE = 0x00000000,
12149RDPCS_SRAM_EXT_LD_DONE = 0x00000001,
12150} RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE;
12151
12152/*
12153 * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE enum
12154 */
12155
12156typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE {
12157RDPCS_SRAM_INIT_NOT_DONE = 0x00000000,
12158RDPCS_SRAM_INIT_DONE = 0x00000001,
12159} RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE;
12160
12161/*
12162 * RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV enum
12163 */
12164
12165typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV {
12166RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1 = 0x00000000,
12167RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2 = 0x00000001,
12168RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3 = 0x00000002,
12169RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8 = 0x00000003,
12170RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16 = 0x00000004,
12171} RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;
12172
12173/*
12174 * RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV enum
12175 */
12176
12177typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV {
12178RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0x00000000,
12179RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 0x00000001,
12180RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 0x00000002,
12181RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 0x00000003,
12182} RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV;
12183
12184/*
12185 * RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV enum
12186 */
12187
12188typedef enum RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV {
12189RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0x00000000,
12190RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2 = 0x00000001,
12191RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4 = 0x00000002,
12192RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8 = 0x00000003,
12193RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3 = 0x00000004,
12194RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5 = 0x00000005,
12195RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6 = 0x00000006,
12196RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10 = 0x00000007,
12197} RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;
12198
12199/*
12200 * RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL enum
12201 */
12202
12203typedef enum RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL {
12204RDPCS_PHY_DP_TX_TERM_CTRL_54 = 0x00000000,
12205RDPCS_PHY_DP_TX_TERM_CTRL_52 = 0x00000001,
12206RDPCS_PHY_DP_TX_TERM_CTRL_50 = 0x00000002,
12207RDPCS_PHY_DP_TX_TERM_CTRL_48 = 0x00000003,
12208RDPCS_PHY_DP_TX_TERM_CTRL_46 = 0x00000004,
12209RDPCS_PHY_DP_TX_TERM_CTRL_44 = 0x00000005,
12210RDPCS_PHY_DP_TX_TERM_CTRL_42 = 0x00000006,
12211RDPCS_PHY_DP_TX_TERM_CTRL_40 = 0x00000007,
12212} RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL;
12213
12214/*
12215 * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT enum
12216 */
12217
12218typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT {
12219RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0x00000000,
12220RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT = 0x00000001,
12221} RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT;
12222
12223/*
12224 * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE enum
12225 */
12226
12227typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE {
12228RDPCS_PHY_DP_TX_RATE = 0x00000000,
12229RDPCS_PHY_DP_TX_RATE_DIV2 = 0x00000001,
12230RDPCS_PHY_DP_TX_RATE_DIV4 = 0x00000002,
12231} RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE;
12232
12233/*
12234 * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH enum
12235 */
12236
12237typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH {
12238RDPCS_PHY_DP_TX_WIDTH_8 = 0x00000000,
12239RDPCS_PHY_DP_TX_WIDTH_10 = 0x00000001,
12240RDPCS_PHY_DP_TX_WIDTH_16 = 0x00000002,
12241RDPCS_PHY_DP_TX_WIDTH_20 = 0x00000003,
12242} RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH;
12243
12244/*
12245 * RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE enum
12246 */
12247
12248typedef enum RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE {
12249RRDPCS_PHY_DP_TX_PSTATE_POWER_UP = 0x00000000,
12250RRDPCS_PHY_DP_TX_PSTATE_HOLD = 0x00000001,
12251RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF = 0x00000002,
12252RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN = 0x00000003,
12253} RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE;
12254
12255/*
12256 * RDPCSTX_PHY_REF_ALT_CLK_EN enum
12257 */
12258
12259typedef enum RDPCSTX_PHY_REF_ALT_CLK_EN {
12260RDPCS_PHY_REF_ALT_CLK_DISABLE = 0x00000000,
12261RDPCS_PHY_REF_ALT_CLK_ENABLE = 0x00000001,
12262} RDPCSTX_PHY_REF_ALT_CLK_EN;
12263
12264/*
12265 * RDPCSTX_TX_FIFO_DISABLED_MASK enum
12266 */
12267
12268typedef enum RDPCSTX_TX_FIFO_DISABLED_MASK {
12269RDPCSTX_TX_FIFO_DISABLED_MASK_DISABLE = 0x00000000,
12270RDPCSTX_TX_FIFO_DISABLED_MASK_ENABLE = 0x00000001,
12271} RDPCSTX_TX_FIFO_DISABLED_MASK;
12272
12273/*
12274 * RDPCS_DBG_OCLA_SEL enum
12275 */
12276
12277typedef enum RDPCS_DBG_OCLA_SEL {
12278RDPCS_DBG_OCLA_SEL_MON_OUT_7_0 = 0x00000000,
12279RDPCS_DBG_OCLA_SEL_MON_OUT_15_8 = 0x00000001,
12280RDPCS_DBG_OCLA_SEL_MON_OUT_23_16 = 0x00000002,
12281RDPCS_DBG_OCLA_SEL_MON_OUT_31_24 = 0x00000003,
12282RDPCS_DBG_OCLA_SEL_MON_OUT_39_32 = 0x00000004,
12283RDPCS_DBG_OCLA_SEL_MON_OUT_47_40 = 0x00000005,
12284RDPCS_DBG_OCLA_SEL_MON_OUT_55_48 = 0x00000006,
12285RDPCS_DBG_OCLA_SEL_MON_OUT_63_56 = 0x00000007,
12286} RDPCS_DBG_OCLA_SEL;
12287
12288/*
12289 * RDPCS_TEST_CLK_SEL enum
12290 */
12291
12292typedef enum RDPCS_TEST_CLK_SEL {
12293RDPCS_TEST_CLK_SEL_NONE = 0x00000000,
12294RDPCS_TEST_CLK_SEL_CFGCLK = 0x00000001,
12295RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 0x00000002,
12296RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 0x00000003,
12297RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 0x00000004,
12298RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 0x00000005,
12299RDPCS_TEST_CLK_SEL_SRAMCLK = 0x00000006,
12300RDPCS_TEST_CLK_SEL_EXT_CR_CLK = 0x00000007,
12301RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK = 0x00000008,
12302RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK = 0x00000009,
12303RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK = 0x0000000a,
12304RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK = 0x0000000b,
12305RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 0x0000000c,
12306RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 0x0000000d,
12307RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK = 0x0000000e,
12308RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk = 0x0000000f,
12309RDPCS_TEST_CLK_SEL_dtb_out0 = 0x00000010,
12310RDPCS_TEST_CLK_SEL_dtb_out1 = 0x00000011,
12311} RDPCS_TEST_CLK_SEL;
12312
12313/*
12314 * RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB enum
12315 */
12316
12317typedef enum RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB {
12318RDPCS_LANE_PACK_FROM_MSB_DISABLE = 0x00000000,
12319RDPCS_LANE_PACK_FROM_MSB_ENABLE = 0x00000001,
12320} RDPCS_TX_CNTL_TX_LANE_PACK_FROM_MSB;
12321
12322/*
12323 * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum
12324 */
12325
12326typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE {
12327RDPCS_MEM_PWR_NO_FORCE = 0x00000000,
12328RDPCS_MEM_PWR_LIGHT_SLEEP = 0x00000001,
12329RDPCS_MEM_PWR_DEEP_SLEEP = 0x00000002,
12330RDPCS_MEM_PWR_SHUT_DOWN = 0x00000003,
12331} RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE;
12332
12333/*
12334 * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum
12335 */
12336
12337typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE {
12338RDPCS_MEM_PWR_PWR_STATE_ON = 0x00000000,
12339RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 0x00000001,
12340RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP = 0x00000002,
12341RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN = 0x00000003,
12342} RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE;
12343
12344/*
12345 * RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK enum
12346 */
12347
12348typedef enum RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK {
12349RDPCS_LANE_BIT_ORDER_REVERSE_DISABLE = 0x00000000,
12350RDPCS_LANE_BIT_ORDER_REVERSE_ENABLE = 0x00000001,
12351} RPDCSTX_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK;
12352
12353/*******************************************************
12354 * RLC Enums
12355 *******************************************************/
12356
12357/*
12358 * RLC_DOORBELL_MODE enum
12359 */
12360
12361typedef enum RLC_DOORBELL_MODE {
12362RLC_DOORBELL_MODE_DISABLE = 0x00000000,
12363RLC_DOORBELL_MODE_ENABLE = 0x00000001,
12364RLC_DOORBELL_MODE_ENABLE_PF = 0x00000002,
12365RLC_DOORBELL_MODE_ENABLE_PF_VF = 0x00000003,
12366} RLC_DOORBELL_MODE;
12367
12368/*
12369 * RLC_PERFCOUNTER_SEL enum
12370 */
12371
12372typedef enum RLC_PERFCOUNTER_SEL {
12373RLC_PERF_SEL_POWER_FEATURE_0 = 0x00000000,
12374RLC_PERF_SEL_POWER_FEATURE_1 = 0x00000001,
12375RLC_PERF_SEL_CP_INTERRUPT = 0x00000002,
12376RLC_PERF_SEL_GRBM_INTERRUPT = 0x00000003,
12377RLC_PERF_SEL_SPM_INTERRUPT = 0x00000004,
12378RLC_PERF_SEL_IH_INTERRUPT = 0x00000005,
12379RLC_PERF_SEL_SERDES_COMMAND_WRITE = 0x00000006,
12380} RLC_PERFCOUNTER_SEL;
12381
12382/*
12383 * RLC_PERFMON_STATE enum
12384 */
12385
12386typedef enum RLC_PERFMON_STATE {
12387RLC_PERFMON_STATE_RESET = 0x00000000,
12388RLC_PERFMON_STATE_ENABLE = 0x00000001,
12389RLC_PERFMON_STATE_DISABLE = 0x00000002,
12390RLC_PERFMON_STATE_RESERVED_3 = 0x00000003,
12391RLC_PERFMON_STATE_RESERVED_4 = 0x00000004,
12392RLC_PERFMON_STATE_RESERVED_5 = 0x00000005,
12393RLC_PERFMON_STATE_RESERVED_6 = 0x00000006,
12394RLC_PERFMON_STATE_ROLLOVER = 0x00000007,
12395} RLC_PERFMON_STATE;
12396
12397/*
12398 * RSPM_CMD enum
12399 */
12400
12401typedef enum RSPM_CMD {
12402RSPM_CMD_INVALID = 0x00000000,
12403RSPM_CMD_IDLE = 0x00000001,
12404RSPM_CMD_CALIBRATE = 0x00000002,
12405RSPM_CMD_SPM_RESET = 0x00000003,
12406RSPM_CMD_SPM_START = 0x00000004,
12407RSPM_CMD_SPM_STOP = 0x00000005,
12408RSPM_CMD_PERF_RESET = 0x00000006,
12409RSPM_CMD_PERF_SAMPLE = 0x00000007,
12410RSPM_CMD_PROF_START = 0x00000008,
12411RSPM_CMD_PROF_STOP = 0x00000009,
12412RSPM_CMD_FORCE_SAMPLE = 0x0000000a,
12413} RSPM_CMD;
12414
12415/*******************************************************
12416 * COMP Enums
12417 *******************************************************/
12418
12419/*
12420 * CSCNTL_TYPE enum
12421 */
12422
12423typedef enum CSCNTL_TYPE {
12424CSCNTL_TYPE_TG = 0x00000000,
12425CSCNTL_TYPE_STATE = 0x00000001,
12426CSCNTL_TYPE_EVENT = 0x00000002,
12427CSCNTL_TYPE_PRIVATE = 0x00000003,
12428} CSCNTL_TYPE;
12429
12430/*
12431 * CSDATA_TYPE enum
12432 */
12433
12434typedef enum CSDATA_TYPE {
12435CSDATA_TYPE_TG = 0x00000000,
12436CSDATA_TYPE_STATE = 0x00000001,
12437CSDATA_TYPE_EVENT = 0x00000002,
12438CSDATA_TYPE_PRIVATE = 0x00000003,
12439} CSDATA_TYPE;
12440
12441/*
12442 * CSDATA_TYPE_WIDTH value
12443 */
12444
12445#define CSDATA_TYPE_WIDTH 0x00000002
12446
12447/*
12448 * CSDATA_ADDR_WIDTH value
12449 */
12450
12451#define CSDATA_ADDR_WIDTH 0x00000007
12452
12453/*
12454 * CSDATA_DATA_WIDTH value
12455 */
12456
12457#define CSDATA_DATA_WIDTH 0x00000020
12458
12459/*
12460 * CSCNTL_TYPE_WIDTH value
12461 */
12462
12463#define CSCNTL_TYPE_WIDTH 0x00000002
12464
12465/*
12466 * CSCNTL_ADDR_WIDTH value
12467 */
12468
12469#define CSCNTL_ADDR_WIDTH 0x00000007
12470
12471/*
12472 * CSCNTL_DATA_WIDTH value
12473 */
12474
12475#define CSCNTL_DATA_WIDTH 0x00000020
12476
12477/*******************************************************
12478 * GE Enums
12479 *******************************************************/
12480
12481/*
12482 * GE1_PERFCOUNT_SELECT enum
12483 */
12484
12485typedef enum GE1_PERFCOUNT_SELECT {
12486ge1_assembler_busy = 0x00000000,
12487ge1_assembler_stalled = 0x00000001,
12488ge1_dma_busy = 0x00000002,
12489ge1_dma_lat_bin_0 = 0x00000003,
12490ge1_dma_lat_bin_1 = 0x00000004,
12491ge1_dma_lat_bin_2 = 0x00000005,
12492ge1_dma_lat_bin_3 = 0x00000006,
12493ge1_dma_lat_bin_4 = 0x00000007,
12494ge1_dma_lat_bin_5 = 0x00000008,
12495ge1_dma_lat_bin_6 = 0x00000009,
12496ge1_dma_lat_bin_7 = 0x0000000a,
12497ge1_dma_return_cl0 = 0x0000000b,
12498ge1_dma_return_cl1 = 0x0000000c,
12499ge1_dma_utcl1_consecutive_retry_event = 0x0000000d,
12500ge1_dma_utcl1_request_event = 0x0000000e,
12501ge1_dma_utcl1_retry_event = 0x0000000f,
12502ge1_dma_utcl1_stall_event = 0x00000010,
12503ge1_dma_utcl1_stall_utcl2_event = 0x00000011,
12504ge1_dma_utcl1_translation_hit_event = 0x00000012,
12505ge1_dma_utcl1_translation_miss_event = 0x00000013,
12506ge1_assembler_dma_starved = 0x00000014,
12507ge1_rbiu_di_fifo_stalled_p0 = 0x00000015,
12508ge1_rbiu_di_fifo_starved_p0 = 0x00000016,
12509ge1_rbiu_dr_fifo_stalled_p0 = 0x00000017,
12510ge1_rbiu_dr_fifo_starved_p0 = 0x00000018,
12511ge1_sclk_reg_vld = 0x00000019,
12512ge1_stat_busy = 0x0000001a,
12513ge1_stat_no_dma_busy = 0x0000001b,
12514ge1_pipe0_to_pipe1 = 0x0000001c,
12515ge1_pipe1_to_pipe0 = 0x0000001d,
12516ge1_dma_return_size_cl0 = 0x0000001e,
12517ge1_dma_return_size_cl1 = 0x0000001f,
12518ge1_small_draws_one_instance = 0x00000020,
12519ge1_sclk_input_vld = 0x00000021,
12520ge1_prim_group_limit_hit = 0x00000022,
12521ge1_unopt_multi_instance_draws = 0x00000023,
12522ge1_rbiu_di_fifo_stalled_p1 = 0x00000024,
12523ge1_rbiu_di_fifo_starved_p1 = 0x00000025,
12524ge1_rbiu_dr_fifo_stalled_p1 = 0x00000026,
12525ge1_rbiu_dr_fifo_starved_p1 = 0x00000027,
12526} GE1_PERFCOUNT_SELECT;
12527
12528/*
12529 * GE2_DIST_PERFCOUNT_SELECT enum
12530 */
12531
12532typedef enum GE2_DIST_PERFCOUNT_SELECT {
12533ge_dist_hs_done = 0x00000000,
12534ge_dist_hs_done_latency_se0 = 0x00000001,
12535ge_dist_hs_done_latency_se1 = 0x00000002,
12536ge_dist_hs_done_latency_se2 = 0x00000003,
12537ge_dist_hs_done_latency_se3 = 0x00000004,
12538ge_dist_hs_done_latency_se4 = 0x00000005,
12539ge_dist_hs_done_latency_se5 = 0x00000006,
12540ge_dist_hs_done_latency_se6 = 0x00000007,
12541ge_dist_hs_done_latency_se7 = 0x00000008,
12542ge_dist_inside_tf_bin_0 = 0x00000009,
12543ge_dist_inside_tf_bin_1 = 0x0000000a,
12544ge_dist_inside_tf_bin_2 = 0x0000000b,
12545ge_dist_inside_tf_bin_3 = 0x0000000c,
12546ge_dist_inside_tf_bin_4 = 0x0000000d,
12547ge_dist_inside_tf_bin_5 = 0x0000000e,
12548ge_dist_inside_tf_bin_6 = 0x0000000f,
12549ge_dist_inside_tf_bin_7 = 0x00000010,
12550ge_dist_inside_tf_bin_8 = 0x00000011,
12551ge_dist_null_patch = 0x00000012,
12552ge_dist_sclk_core_vld = 0x00000013,
12553ge_dist_sclk_wd_te11_vld = 0x00000014,
12554ge_dist_tfreq_lat_bin_0 = 0x00000015,
12555ge_dist_tfreq_lat_bin_1 = 0x00000016,
12556ge_dist_tfreq_lat_bin_2 = 0x00000017,
12557ge_dist_tfreq_lat_bin_3 = 0x00000018,
12558ge_dist_tfreq_lat_bin_4 = 0x00000019,
12559ge_dist_tfreq_lat_bin_5 = 0x0000001a,
12560ge_dist_tfreq_lat_bin_6 = 0x0000001b,
12561ge_dist_tfreq_lat_bin_7 = 0x0000001c,
12562ge_dist_tfreq_utcl1_consecutive_retry_event = 0x0000001d,
12563ge_dist_tfreq_utcl1_request_event = 0x0000001e,
12564ge_dist_tfreq_utcl1_retry_event = 0x0000001f,
12565ge_dist_tfreq_utcl1_stall_event = 0x00000020,
12566ge_dist_tfreq_utcl1_stall_utcl2_event = 0x00000021,
12567ge_dist_tfreq_utcl1_translation_hit_event = 0x00000022,
12568ge_dist_tfreq_utcl1_translation_miss_event = 0x00000023,
12569ge_dist_pc_feorder_fifo_full = 0x00000024,
12570ge_dist_pc_ge_manager_busy = 0x00000025,
12571ge_dist_sclk_input_vld = 0x00000026,
12572ge_dist_wd_te11_busy = 0x00000027,
12573ge_dist_te11_starved = 0x00000028,
12574ge_dist_switch_mode_stall = 0x00000029,
12575ge_all_tf_eq = 0x0000002a,
12576ge_all_tf2 = 0x0000002b,
12577ge_all_tf3 = 0x0000002c,
12578ge_all_tf4 = 0x0000002d,
12579ge_all_tf5 = 0x0000002e,
12580ge_all_tf6 = 0x0000002f,
12581ge_se0_te11_starved_on_hs_done = 0x00000030,
12582ge_se1_te11_starved_on_hs_done = 0x00000031,
12583ge_se2_te11_starved_on_hs_done = 0x00000032,
12584ge_se3_te11_starved_on_hs_done = 0x00000033,
12585ge_se4_te11_starved_on_hs_done = 0x00000034,
12586ge_se5_te11_starved_on_hs_done = 0x00000035,
12587ge_se6_te11_starved_on_hs_done = 0x00000036,
12588ge_se7_te11_starved_on_hs_done = 0x00000037,
12589ge_dist_op_fifo_full_starve = 0x00000038,
12590ge_dist_hs_done_se0 = 0x00000039,
12591ge_dist_hs_done_se1 = 0x0000003a,
12592ge_dist_hs_done_se2 = 0x0000003b,
12593ge_dist_hs_done_se3 = 0x0000003c,
12594ge_dist_hs_done_se4 = 0x0000003d,
12595ge_dist_hs_done_se5 = 0x0000003e,
12596ge_dist_hs_done_se6 = 0x0000003f,
12597ge_dist_hs_done_se7 = 0x00000040,
12598ge_dist_hs_done_latency = 0x00000041,
12599ge_dist_distributer_busy = 0x00000042,
12600ge_tf_ret_data_stalling_hs_done = 0x00000043,
12601ge_num_of_no_dist_patches = 0x00000044,
12602ge_num_of_donut_dist_patches = 0x00000045,
12603ge_num_of_patch_dist_patches = 0x00000046,
12604ge_num_of_se_switches_due_to_patch_accum = 0x00000047,
12605ge_num_of_se_switches_due_to_donut = 0x00000048,
12606ge_num_of_se_switches_due_to_trap = 0x00000049,
12607ge_num_of_hs_dealloc_events = 0x0000004a,
12608ge_agm_gcr_req = 0x0000004b,
12609ge_agm_gcr_tag_stall = 0x0000004c,
12610ge_agm_gcr_crd_stall = 0x0000004d,
12611ge_agm_gcr_stall = 0x0000004e,
12612ge_agm_gcr_latency = 0x0000004f,
12613ge_distclk_vld = 0x00000050,
12614ge_dist_indx_fifos_full_and_empty = 0x00000051,
12615ge_hs_done_all_tf0_se0 = 0x00000052,
12616ge_hs_done_all_tf0_se1 = 0x00000053,
12617ge_hs_done_all_tf0_se2 = 0x00000054,
12618ge_hs_done_all_tf0_se3 = 0x00000055,
12619ge_hs_done_all_tf0_se4 = 0x00000056,
12620ge_hs_done_all_tf0_se5 = 0x00000057,
12621ge_hs_done_all_tf0_se6 = 0x00000058,
12622ge_hs_done_all_tf0_se7 = 0x00000059,
12623ge_hs_done_all_tf1_se0 = 0x0000005a,
12624ge_hs_done_all_tf1_se1 = 0x0000005b,
12625ge_hs_done_all_tf1_se2 = 0x0000005c,
12626ge_hs_done_all_tf1_se3 = 0x0000005d,
12627ge_hs_done_all_tf1_se4 = 0x0000005e,
12628ge_hs_done_all_tf1_se5 = 0x0000005f,
12629ge_hs_done_all_tf1_se6 = 0x00000060,
12630ge_hs_done_all_tf1_se7 = 0x00000061,
12631ge_agm_gcr_req_outstanding = 0x00000062,
12632ge_agm_gcr_req_amount = 0x00000063,
12633ge_agm_gcr_combine = 0x00000064,
12634} GE2_DIST_PERFCOUNT_SELECT;
12635
12636/*
12637 * GE2_SE_PERFCOUNT_SELECT enum
12638 */
12639
12640typedef enum GE2_SE_PERFCOUNT_SELECT {
12641ge_se_ds_prims = 0x00000000,
12642ge_se_es_thread_groups = 0x00000001,
12643ge_se_esvert_stalled_gsprim = 0x00000002,
12644ge_se_hs_tfm_stall = 0x00000003,
12645ge_se_hs_tgs_active_high_water_mark = 0x00000004,
12646ge_se_hs_thread_groups = 0x00000005,
12647ge_se_reused_es_indices = 0x00000006,
12648ge_se_sclk_ngg_vld = 0x00000007,
12649ge_se_sclk_te11_vld = 0x00000008,
12650ge_se_spi_esvert_eov = 0x00000009,
12651ge_se_spi_esvert_stalled = 0x0000000a,
12652ge_se_spi_esvert_starved_busy = 0x0000000b,
12653ge_se_spi_esvert_valid = 0x0000000c,
12654ge_se_spi_gsprim_cont = 0x0000000d,
12655ge_se_spi_gsprim_eov = 0x0000000e,
12656ge_se_spi_gsprim_stalled = 0x0000000f,
12657ge_se_spi_gsprim_starved_busy = 0x00000010,
12658ge_se_spi_gsprim_valid = 0x00000011,
12659ge_se_spi_gssubgrp_is_event = 0x00000012,
12660ge_se_spi_gssubgrp_send = 0x00000013,
12661ge_se_spi_hsvert_eov = 0x00000014,
12662ge_se_spi_hsvert_stalled = 0x00000015,
12663ge_se_spi_hsvert_starved_busy = 0x00000016,
12664ge_se_spi_hsvert_valid = 0x00000017,
12665ge_se_spi_hsgrp_is_event = 0x00000018,
12666ge_se_spi_hsgrp_send = 0x00000019,
12667ge_se_spi_lsvert_eov = 0x0000001a,
12668ge_se_spi_lsvert_stalled = 0x0000001b,
12669ge_se_spi_lsvert_starved_busy = 0x0000001c,
12670ge_se_spi_lsvert_valid = 0x0000001d,
12671ge_se_spi_hsvert_fifo_full_stall = 0x0000001e,
12672ge_se_spi_tgrp_fifo_stall = 0x0000001f,
12673ge_spi_hsgrp_spi_stall = 0x00000020,
12674ge_se_spi_gssubgrp_event_window_active = 0x00000021,
12675ge_se_hs_input_stall = 0x00000022,
12676ge_se_sending_vert_or_prim = 0x00000023,
12677ge_se_sclk_input_vld = 0x00000024,
12678ge_spi_lswave_fifo_full_stall = 0x00000025,
12679ge_spi_hswave_fifo_full_stall = 0x00000026,
12680ge_hs_tif_stall = 0x00000027,
12681ge_csb_spi_bp = 0x00000028,
12682ge_ngg_starving_for_wave_id = 0x00000029,
12683ge_pa0_csb_eop = 0x0000002a,
12684ge_ngg_starved_idle = 0x0000002b,
12685ge_gsprim_send = 0x0000002c,
12686ge_esvert_send = 0x0000002d,
12687ge_ngg_starved_after_work = 0x0000002e,
12688ge_ngg_subgrp_fifo_stall = 0x0000002f,
12689ge_ngg_ord_id_req_stall = 0x00000030,
12690ge_ngg_indx_bus_stall = 0x00000031,
12691ge_hs_stall_tfmm_fifo_full = 0x00000032,
12692ge_gs_issue_rtr_stalled = 0x00000033,
12693ge_gsprim_stalled_esvert = 0x00000034,
12694ge_gsthread_stalled = 0x00000035,
12695ge_ngg_attr_grp_alloc = 0x00000036,
12696ge_ngg_attr_discard_alloc = 0x00000037,
12697ge_ngg_pc_space_not_avail = 0x00000038,
12698ge_ngg_agm_req_stall = 0x00000039,
12699ge_ngg_spi_esvert_partial_eov = 0x0000003a,
12700ge_ngg_spi_gsprim_partial_eov = 0x0000003b,
12701ge_spi_gsgrp_valid = 0x0000003c,
12702ge_ngg_attr_grp_latency = 0x0000003d,
12703ge_ngg_reuse_prim_limit_hit = 0x0000003e,
12704ge_ngg_reuse_vert_limit_hit = 0x0000003f,
12705ge_te11_con_stall = 0x00000040,
12706ge_te11_compactor_starved = 0x00000041,
12707ge_ngg_stall_tess_off_tess_on = 0x00000042,
12708ge_ngg_stall_tess_on_tess_off = 0x00000043,
12709ge_merged_lses_vert_stalled = 0x00000044,
12710ge_merged_hsgs_vert_stalled = 0x00000045,
12711ge_merged_hsgs_grp_stalled = 0x00000046,
12712ge_merge_lses_fifo_blocked = 0x00000047,
12713ge_merge_hsgs_fifo_blocked = 0x00000048,
12714ge_merge_lses_vert_switch = 0x00000049,
12715ge_merge_hsgs_vert_switch = 0x0000004a,
12716ge_merge_hsgs_grp_switch = 0x0000004b,
12717ge_merge_gsgrp_rdy_pending_verts = 0x0000004c,
12718ge_merge_hsgrp_rdy_pending_verts = 0x0000004d,
12719ge_se_ds_cache_hits = 0x0000004e,
12720ge_se_api_vs_verts = 0x0000004f,
12721ge_se_api_ds_verts = 0x00000050,
12722ge_se_combined_busy = 0x00000051,
12723ge_spi_lsvert_send = 0x00000052,
12724ge_spi_hsvert_send = 0x00000053,
12725ge_ngg_attr_grp_wasted = 0x00000054,
12726ge_spi_gssubgrp_stalled = 0x00000055,
12727ge_ngg_attr_null_dealloc = 0x00000056,
12728ge_ngg_busy_base = 0x00000057,
12729} GE2_SE_PERFCOUNT_SELECT;
12730
12731/*
12732 * VGT_DETECT_ONE enum
12733 */
12734
12735typedef enum VGT_DETECT_ONE {
12736ENABLE_TF1_OPT = 0x00000000,
12737DISABLE_TF1_OPT = 0x00000001,
12738} VGT_DETECT_ONE;
12739
12740/*
12741 * VGT_DETECT_ZERO enum
12742 */
12743
12744typedef enum VGT_DETECT_ZERO {
12745ENABLE_TF0_OPT = 0x00000000,
12746DISABLE_TF0_OPT = 0x00000001,
12747} VGT_DETECT_ZERO;
12748
12749/*
12750 * VGT_DIST_MODE enum
12751 */
12752
12753typedef enum VGT_DIST_MODE {
12754NO_DIST = 0x00000000,
12755PATCHES = 0x00000001,
12756DONUTS = 0x00000002,
12757TRAPEZOIDS = 0x00000003,
12758} VGT_DIST_MODE;
12759
12760/*
12761 * VGT_DI_INDEX_SIZE enum
12762 */
12763
12764typedef enum VGT_DI_INDEX_SIZE {
12765DI_INDEX_SIZE_16_BIT = 0x00000000,
12766DI_INDEX_SIZE_32_BIT = 0x00000001,
12767DI_INDEX_SIZE_8_BIT = 0x00000002,
12768} VGT_DI_INDEX_SIZE;
12769
12770/*
12771 * VGT_DI_PRIM_TYPE enum
12772 */
12773
12774typedef enum VGT_DI_PRIM_TYPE {
12775DI_PT_NONE = 0x00000000,
12776DI_PT_POINTLIST = 0x00000001,
12777DI_PT_LINELIST = 0x00000002,
12778DI_PT_LINESTRIP = 0x00000003,
12779DI_PT_TRILIST = 0x00000004,
12780DI_PT_TRIFAN = 0x00000005,
12781DI_PT_TRISTRIP = 0x00000006,
12782DI_PT_2D_RECTANGLE = 0x00000007,
12783DI_PT_UNUSED_1 = 0x00000008,
12784DI_PT_PATCH = 0x00000009,
12785DI_PT_LINELIST_ADJ = 0x0000000a,
12786DI_PT_LINESTRIP_ADJ = 0x0000000b,
12787DI_PT_TRILIST_ADJ = 0x0000000c,
12788DI_PT_TRISTRIP_ADJ = 0x0000000d,
12789DI_PT_UNUSED_3 = 0x0000000e,
12790DI_PT_UNUSED_4 = 0x0000000f,
12791DI_PT_UNUSED_5 = 0x00000010,
12792DI_PT_RECTLIST = 0x00000011,
12793DI_PT_LINELOOP = 0x00000012,
12794DI_PT_QUADLIST = 0x00000013,
12795DI_PT_QUADSTRIP = 0x00000014,
12796DI_PT_POLYGON = 0x00000015,
12797} VGT_DI_PRIM_TYPE;
12798
12799/*
12800 * VGT_DI_SOURCE_SELECT enum
12801 */
12802
12803typedef enum VGT_DI_SOURCE_SELECT {
12804DI_SRC_SEL_DMA = 0x00000000,
12805DI_SRC_SEL_IMMEDIATE = 0x00000001,
12806DI_SRC_SEL_AUTO_INDEX = 0x00000002,
12807DI_SRC_SEL_RESERVED = 0x00000003,
12808} VGT_DI_SOURCE_SELECT;
12809
12810/*
12811 * VGT_DMA_BUF_TYPE enum
12812 */
12813
12814typedef enum VGT_DMA_BUF_TYPE {
12815VGT_DMA_BUF_MEM = 0x00000000,
12816VGT_DMA_BUF_RING = 0x00000001,
12817VGT_DMA_BUF_SETUP = 0x00000002,
12818VGT_DMA_PTR_UPDATE = 0x00000003,
12819} VGT_DMA_BUF_TYPE;
12820
12821/*
12822 * VGT_DMA_SWAP_MODE enum
12823 */
12824
12825typedef enum VGT_DMA_SWAP_MODE {
12826VGT_DMA_SWAP_NONE = 0x00000000,
12827VGT_DMA_SWAP_16_BIT = 0x00000001,
12828VGT_DMA_SWAP_32_BIT = 0x00000002,
12829VGT_DMA_SWAP_WORD = 0x00000003,
12830} VGT_DMA_SWAP_MODE;
12831
12832/*
12833 * VGT_EVENT_TYPE enum
12834 */
12835
12836typedef enum VGT_EVENT_TYPE {
12837Reserved_0x00 = 0x00000000,
12838SAMPLE_STREAMOUTSTATS1 = 0x00000001,
12839SAMPLE_STREAMOUTSTATS2 = 0x00000002,
12840SAMPLE_STREAMOUTSTATS3 = 0x00000003,
12841CACHE_FLUSH_TS = 0x00000004,
12842CONTEXT_DONE = 0x00000005,
12843CACHE_FLUSH = 0x00000006,
12844CS_PARTIAL_FLUSH = 0x00000007,
12845VGT_STREAMOUT_SYNC = 0x00000008,
12846EVENT_STATE_CHANGE = 0x00000009,
12847VGT_STREAMOUT_RESET = 0x0000000a,
12848END_OF_PIPE_INCR_DE = 0x0000000b,
12849END_OF_PIPE_IB_END = 0x0000000c,
12850RST_PIX_CNT = 0x0000000d,
12851BREAK_BATCH = 0x0000000e,
12852VS_PARTIAL_FLUSH = 0x0000000f,
12853PS_PARTIAL_FLUSH = 0x00000010,
12854FLUSH_HS_OUTPUT = 0x00000011,
12855FLUSH_DFSM = 0x00000012,
12856RESET_TO_LOWEST_VGT = 0x00000013,
12857CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014,
12858WAIT_SYNC = 0x00000015,
12859CACHE_FLUSH_AND_INV_EVENT = 0x00000016,
12860PERFCOUNTER_START = 0x00000017,
12861PERFCOUNTER_STOP = 0x00000018,
12862PIPELINESTAT_START = 0x00000019,
12863PIPELINESTAT_STOP = 0x0000001a,
12864PERFCOUNTER_SAMPLE = 0x0000001b,
12865FLUSH_ES_OUTPUT = 0x0000001c,
12866BIN_CONF_OVERRIDE_CHECK = 0x0000001d,
12867SAMPLE_PIPELINESTAT = 0x0000001e,
12868SO_VGTSTREAMOUT_FLUSH = 0x0000001f,
12869SAMPLE_STREAMOUTSTATS = 0x00000020,
12870RESET_VTX_CNT = 0x00000021,
12871BLOCK_CONTEXT_DONE = 0x00000022,
12872CS_CONTEXT_DONE = 0x00000023,
12873VGT_FLUSH = 0x00000024,
12874TGID_ROLLOVER = 0x00000025,
12875SQ_NON_EVENT = 0x00000026,
12876SC_SEND_DB_VPZ = 0x00000027,
12877BOTTOM_OF_PIPE_TS = 0x00000028,
12878FLUSH_SX_TS = 0x00000029,
12879DB_CACHE_FLUSH_AND_INV = 0x0000002a,
12880FLUSH_AND_INV_DB_DATA_TS = 0x0000002b,
12881FLUSH_AND_INV_DB_META = 0x0000002c,
12882FLUSH_AND_INV_CB_DATA_TS = 0x0000002d,
12883FLUSH_AND_INV_CB_META = 0x0000002e,
12884CS_DONE = 0x0000002f,
12885PS_DONE = 0x00000030,
12886FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031,
12887SX_CB_RAT_ACK_REQUEST = 0x00000032,
12888THREAD_TRACE_START = 0x00000033,
12889THREAD_TRACE_STOP = 0x00000034,
12890THREAD_TRACE_MARKER = 0x00000035,
12891THREAD_TRACE_DRAW = 0x00000036,
12892THREAD_TRACE_FINISH = 0x00000037,
12893PIXEL_PIPE_STAT_CONTROL = 0x00000038,
12894PIXEL_PIPE_STAT_DUMP = 0x00000039,
12895PIXEL_PIPE_STAT_RESET = 0x0000003a,
12896CONTEXT_SUSPEND = 0x0000003b,
12897OFFCHIP_HS_DEALLOC = 0x0000003c,
12898ENABLE_NGG_PIPELINE = 0x0000003d,
12899ENABLE_PIPELINE_NOT_USED = 0x0000003e,
12900DRAW_DONE = 0x0000003f,
12901} VGT_EVENT_TYPE;
12902
12903/*
12904 * VGT_GROUP_CONV_SEL enum
12905 */
12906
12907typedef enum VGT_GROUP_CONV_SEL {
12908VGT_GRP_INDEX_16 = 0x00000000,
12909VGT_GRP_INDEX_32 = 0x00000001,
12910VGT_GRP_UINT_16 = 0x00000002,
12911VGT_GRP_UINT_32 = 0x00000003,
12912VGT_GRP_SINT_16 = 0x00000004,
12913VGT_GRP_SINT_32 = 0x00000005,
12914VGT_GRP_FLOAT_32 = 0x00000006,
12915VGT_GRP_AUTO_PRIM = 0x00000007,
12916VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008,
12917} VGT_GROUP_CONV_SEL;
12918
12919/*
12920 * VGT_GS_MODE_TYPE enum
12921 */
12922
12923typedef enum VGT_GS_MODE_TYPE {
12924GS_OFF = 0x00000000,
12925GS_SCENARIO_A = 0x00000001,
12926GS_SCENARIO_B = 0x00000002,
12927GS_SCENARIO_G = 0x00000003,
12928GS_SCENARIO_C = 0x00000004,
12929SPRITE_EN = 0x00000005,
12930} VGT_GS_MODE_TYPE;
12931
12932/*
12933 * VGT_GS_OUTPRIM_TYPE enum
12934 */
12935
12936typedef enum VGT_GS_OUTPRIM_TYPE {
12937POINTLIST = 0x00000000,
12938LINESTRIP = 0x00000001,
12939TRISTRIP = 0x00000002,
12940RECT_2D = 0x00000003,
12941RECTLIST = 0x00000004,
12942} VGT_GS_OUTPRIM_TYPE;
12943
12944/*
12945 * VGT_INDEX_TYPE_MODE enum
12946 */
12947
12948typedef enum VGT_INDEX_TYPE_MODE {
12949VGT_INDEX_16 = 0x00000000,
12950VGT_INDEX_32 = 0x00000001,
12951VGT_INDEX_8 = 0x00000002,
12952} VGT_INDEX_TYPE_MODE;
12953
12954/*
12955 * VGT_OUTPATH_SELECT enum
12956 */
12957
12958typedef enum VGT_OUTPATH_SELECT {
12959VGT_OUTPATH_VTX_REUSE = 0x00000000,
12960VGT_OUTPATH_GS_BLOCK = 0x00000001,
12961VGT_OUTPATH_HS_BLOCK = 0x00000002,
12962VGT_OUTPATH_PRIM_GEN = 0x00000003,
12963VGT_OUTPATH_TE_PRIM_GEN = 0x00000004,
12964VGT_OUTPATH_TE_GS_BLOCK = 0x00000005,
12965VGT_OUTPATH_TE_OUTPUT = 0x00000006,
12966} VGT_OUTPATH_SELECT;
12967
12968/*
12969 * VGT_OUT_PRIM_TYPE enum
12970 */
12971
12972typedef enum VGT_OUT_PRIM_TYPE {
12973VGT_OUT_POINT = 0x00000000,
12974VGT_OUT_LINE = 0x00000001,
12975VGT_OUT_TRI = 0x00000002,
12976VGT_OUT_2D_RECT = 0x00000003,
12977VGT_OUT_RECT_V0 = 0x00000004,
12978VGT_OUT_DUMMY_1 = 0x00000005,
12979VGT_OUT_DUMMY_2 = 0x00000006,
12980VGT_OUT_DUMMY_3 = 0x00000007,
12981VGT_OUT_PATCH = 0x00000008,
12982VGT_OUT_LINE_ADJ = 0x00000009,
12983VGT_OUT_TRI_ADJ = 0x0000000a,
12984} VGT_OUT_PRIM_TYPE;
12985
12986/*
12987 * VGT_RDREQ_POLICY enum
12988 */
12989
12990typedef enum VGT_RDREQ_POLICY {
12991VGT_POLICY_LRU = 0x00000000,
12992VGT_POLICY_STREAM = 0x00000001,
12993VGT_POLICY_BYPASS = 0x00000002,
12994} VGT_RDREQ_POLICY;
12995
12996/*
12997 * VGT_SPEC_DATA_READ enum
12998 */
12999
13000typedef enum VGT_SPEC_DATA_READ {
13001VGT_SPEC_DATA_READ_AUTO = 0x00000000,
13002VGT_SPEC_DATA_READ_FORCE_ON = 0x00000001,
13003VGT_SPEC_DATA_READ_FORCE_OFF = 0x00000002,
13004} VGT_SPEC_DATA_READ;
13005
13006/*
13007 * VGT_STAGES_GS_EN enum
13008 */
13009
13010typedef enum VGT_STAGES_GS_EN {
13011GS_STAGE_OFF = 0x00000000,
13012GS_STAGE_ON = 0x00000001,
13013} VGT_STAGES_GS_EN;
13014
13015/*
13016 * VGT_STAGES_HS_EN enum
13017 */
13018
13019typedef enum VGT_STAGES_HS_EN {
13020HS_STAGE_OFF = 0x00000000,
13021HS_STAGE_ON = 0x00000001,
13022} VGT_STAGES_HS_EN;
13023
13024/*
13025 * VGT_TEMPORAL enum
13026 */
13027
13028typedef enum VGT_TEMPORAL {
13029VGT_TEMPORAL_NORMAL = 0x00000000,
13030VGT_TEMPORAL_HIGH_PRIORITY = 0x00000001,
13031VGT_TEMPORAL_STREAM = 0x00000002,
13032VGT_TEMPORAL_DISCARD = 0x00000003,
13033} VGT_TEMPORAL;
13034
13035/*
13036 * VGT_TESS_PARTITION enum
13037 */
13038
13039typedef enum VGT_TESS_PARTITION {
13040PART_INTEGER = 0x00000000,
13041PART_POW2 = 0x00000001,
13042PART_FRAC_ODD = 0x00000002,
13043PART_FRAC_EVEN = 0x00000003,
13044} VGT_TESS_PARTITION;
13045
13046/*
13047 * VGT_TESS_TOPOLOGY enum
13048 */
13049
13050typedef enum VGT_TESS_TOPOLOGY {
13051OUTPUT_POINT = 0x00000000,
13052OUTPUT_LINE = 0x00000001,
13053OUTPUT_TRIANGLE_CW = 0x00000002,
13054OUTPUT_TRIANGLE_CCW = 0x00000003,
13055} VGT_TESS_TOPOLOGY;
13056
13057/*
13058 * VGT_TESS_TYPE enum
13059 */
13060
13061typedef enum VGT_TESS_TYPE {
13062TESS_ISOLINE = 0x00000000,
13063TESS_TRIANGLE = 0x00000001,
13064TESS_QUAD = 0x00000002,
13065} VGT_TESS_TYPE;
13066
13067/*
13068 * WD_IA_DRAW_REG_XFER enum
13069 */
13070
13071typedef enum WD_IA_DRAW_REG_XFER {
13072WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 0x00000000,
13073WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001,
13074WD_IA_DRAW_REG_XFER_VGT_GS_OUT_PRIM_TYPE = 0x00000002,
13075WD_IA_DRAW_REG_XFER_GE_CNTL = 0x00000003,
13076WD_IA_DRAW_REG_XFER_VGT_PRIMITIVE_TYPE = 0x00000004,
13077WD_IA_DRAW_REG_XFER_GFX_PIPE_CONTROL = 0x00000005,
13078WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 0x00000006,
13079WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 0x00000007,
13080WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 0x00000008,
13081WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 0x00000009,
13082WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 0x0000000a,
13083WD_IA_DRAW_REG_XFER_VGT_DRAW_PAYLOAD_CNTL = 0x0000000b,
13084WD_IA_DRAW_REG_XFER_GE_STEREO_CNTL = 0x0000000c,
13085WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_RESET = 0x0000000d,
13086WD_IA_DRAW_REG_XFER_VGT_PRIMITIVEID_EN = 0x0000000e,
13087WD_IA_DRAW_REG_XFER_GE_USER_VGPR1 = 0x0000000f,
13088WD_IA_DRAW_REG_XFER_GE_USER_VGPR2 = 0x00000010,
13089WD_IA_DRAW_REG_XFER_GE_USER_VGPR3 = 0x00000011,
13090WD_IA_DRAW_REG_XFER_GE_VRS_RATE = 0x00000012,
13091WD_IA_DRAW_REG_XFER_GE_PC_ALLOC = 0x00000013,
13092WD_IA_DRAW_REG_XFER_SPI_SHADER_GS_OUT_CONFIG_PS = 0x00000014,
13093WD_IA_DRAW_REG_XFER_GE_GS_THROTTLE = 0x00000015,
13094} WD_IA_DRAW_REG_XFER;
13095
13096/*
13097 * WD_IA_DRAW_SOURCE enum
13098 */
13099
13100typedef enum WD_IA_DRAW_SOURCE {
13101WD_IA_DRAW_SOURCE_DMA = 0x00000000,
13102WD_IA_DRAW_SOURCE_IMMD = 0x00000001,
13103WD_IA_DRAW_SOURCE_AUTO = 0x00000002,
13104WD_IA_DRAW_SOURCE_OPAQ = 0x00000003,
13105} WD_IA_DRAW_SOURCE;
13106
13107/*
13108 * WD_IA_DRAW_TYPE enum
13109 */
13110
13111typedef enum WD_IA_DRAW_TYPE {
13112WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000,
13113WD_IA_DRAW_TYPE_INDX_OFF = 0x00000001,
13114WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002,
13115WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003,
13116WD_IA_DRAW_TYPE_REG_XFER = 0x00000004,
13117WD_IA_DRAW_TYPE_MIN_INDX = 0x00000005,
13118WD_IA_DRAW_TYPE_MAX_INDX = 0x00000006,
13119WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007,
13120} WD_IA_DRAW_TYPE;
13121
13122/*
13123 * GS_THREADID_SIZE value
13124 */
13125
13126#define GSTHREADID_SIZE 0x00000002
13127
13128/*******************************************************
13129 * CH Enums
13130 *******************************************************/
13131
13132/*
13133 * CHA_PERF_SEL enum
13134 */
13135
13136typedef enum CHA_PERF_SEL {
13137CHA_PERF_SEL_BUSY = 0x00000000,
13138CHA_PERF_SEL_STALL_CHC0 = 0x00000001,
13139CHA_PERF_SEL_STALL_CHC1 = 0x00000002,
13140CHA_PERF_SEL_STALL_CHC2 = 0x00000003,
13141CHA_PERF_SEL_STALL_CHC3 = 0x00000004,
13142CHA_PERF_SEL_REQUEST_CHC0 = 0x00000005,
13143CHA_PERF_SEL_REQUEST_CHC1 = 0x00000006,
13144CHA_PERF_SEL_REQUEST_CHC2 = 0x00000007,
13145CHA_PERF_SEL_REQUEST_CHC3 = 0x00000008,
13146CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 0x00000009,
13147CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 0x0000000a,
13148CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 0x0000000b,
13149CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 0x0000000c,
13150CHA_PERF_SEL_IO_32B_WDS_CHC0 = 0x0000000d,
13151CHA_PERF_SEL_IO_32B_WDS_CHC1 = 0x0000000e,
13152CHA_PERF_SEL_IO_32B_WDS_CHC2 = 0x0000000f,
13153CHA_PERF_SEL_IO_32B_WDS_CHC3 = 0x00000010,
13154CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 0x00000011,
13155CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 0x00000012,
13156CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 0x00000013,
13157CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 0x00000014,
13158CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 0x00000015,
13159CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 0x00000016,
13160CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 0x00000017,
13161CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 0x00000018,
13162CHA_PERF_SEL_ARB_REQUESTS = 0x00000019,
13163CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x0000001a,
13164CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 0x0000001b,
13165CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 0x0000001c,
13166CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 0x0000001d,
13167CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 0x0000001e,
13168CHA_PERF_SEL_CYCLE = 0x0000001f,
13169} CHA_PERF_SEL;
13170
13171/*
13172 * CHC_PERF_SEL enum
13173 */
13174
13175typedef enum CHC_PERF_SEL {
13176CHC_PERF_SEL_CYCLE = 0x00000000,
13177CHC_PERF_SEL_BUSY = 0x00000001,
13178CHC_PERF_SEL_STARVE = 0x00000002,
13179CHC_PERF_SEL_ARB_RET_LEVEL = 0x00000003,
13180CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000004,
13181CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x00000005,
13182CHC_PERF_SEL_REQ = 0x00000006,
13183CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x00000007,
13184CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000008,
13185CHC_PERF_SEL_REQ_NOP_ACK = 0x00000009,
13186CHC_PERF_SEL_REQ_NOP_RTN0 = 0x0000000a,
13187CHC_PERF_SEL_REQ_READ = 0x0000000b,
13188CHC_PERF_SEL_REQ_READ_128B = 0x0000000c,
13189CHC_PERF_SEL_REQ_READ_32B = 0x0000000d,
13190CHC_PERF_SEL_REQ_READ_64B = 0x0000000e,
13191CHC_PERF_SEL_REQ_WRITE = 0x0000000f,
13192CHC_PERF_SEL_REQ_WRITE_32B = 0x00000010,
13193CHC_PERF_SEL_REQ_WRITE_64B = 0x00000011,
13194CHC_PERF_SEL_STALL_GL2_GL1 = 0x00000012,
13195CHC_PERF_SEL_STALL_BUFFER_FULL = 0x00000013,
13196CHC_PERF_SEL_REQ_CLIENT0 = 0x00000014,
13197CHC_PERF_SEL_REQ_CLIENT1 = 0x00000015,
13198CHC_PERF_SEL_REQ_CLIENT2 = 0x00000016,
13199CHC_PERF_SEL_REQ_CLIENT3 = 0x00000017,
13200CHC_PERF_SEL_REQ_CLIENT4 = 0x00000018,
13201CHC_PERF_SEL_REQ_CLIENT5 = 0x00000019,
13202CHC_PERF_SEL_REQ_CLIENT6 = 0x0000001a,
13203CHC_PERF_SEL_REQ_CLIENT7 = 0x0000001b,
13204CHC_PERF_SEL_REQ_CLIENT8 = 0x0000001c,
13205CHC_PERF_SEL_REQ_CLIENT9 = 0x0000001d,
13206CHC_PERF_SEL_REQ_CLIENT10 = 0x0000001e,
13207CHC_PERF_SEL_REQ_CLIENT11 = 0x0000001f,
13208CHC_PERF_SEL_REQ_CLIENT12 = 0x00000020,
13209CHC_PERF_SEL_REQ_CLIENT13 = 0x00000021,
13210CHC_PERF_SEL_REQ_CLIENT14 = 0x00000022,
13211CHC_PERF_SEL_REQ_CLIENT15 = 0x00000023,
13212CHC_PERF_SEL_REQ_CLIENT16 = 0x00000024,
13213CHC_PERF_SEL_REQ_CLIENT17 = 0x00000025,
13214CHC_PERF_SEL_REQ_CLIENT18 = 0x00000026,
13215CHC_PERF_SEL_REQ_CLIENT19 = 0x00000027,
13216CHC_PERF_SEL_REQ_CLIENT20 = 0x00000028,
13217CHC_PERF_SEL_REQ_CLIENT21 = 0x00000029,
13218CHC_PERF_SEL_REQ_CLIENT22 = 0x0000002a,
13219CHC_PERF_SEL_REQ_CLIENT23 = 0x0000002b,
13220} CHC_PERF_SEL;
13221
13222/*******************************************************
13223 * GRBM Enums
13224 *******************************************************/
13225
13226/*
13227 * GRBM_PERF_SEL enum
13228 */
13229
13230typedef enum GRBM_PERF_SEL {
13231GRBM_PERF_SEL_COUNT = 0x00000000,
13232GRBM_PERF_SEL_USER_DEFINED = 0x00000001,
13233GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002,
13234GRBM_PERF_SEL_CP_BUSY = 0x00000003,
13235GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004,
13236GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005,
13237GRBM_PERF_SEL_CB_BUSY = 0x00000006,
13238GRBM_PERF_SEL_DB_BUSY = 0x00000007,
13239GRBM_PERF_SEL_PA_BUSY = 0x00000008,
13240GRBM_PERF_SEL_SC_BUSY = 0x00000009,
13241GRBM_PERF_SEL_SPI_BUSY = 0x0000000b,
13242GRBM_PERF_SEL_SX_BUSY = 0x0000000c,
13243GRBM_PERF_SEL_TA_BUSY = 0x0000000d,
13244GRBM_PERF_SEL_CB_CLEAN = 0x0000000e,
13245GRBM_PERF_SEL_DB_CLEAN = 0x0000000f,
13246GRBM_PERF_SEL_BCI_BUSY = 0x0000001a,
13247GRBM_PERF_SEL_RLC_BUSY = 0x0000001b,
13248GRBM_PERF_SEL_TCP_BUSY = 0x0000001c,
13249GRBM_PERF_SEL_CPG_BUSY = 0x0000001d,
13250GRBM_PERF_SEL_CPC_BUSY = 0x0000001e,
13251GRBM_PERF_SEL_CPF_BUSY = 0x0000001f,
13252GRBM_PERF_SEL_GE_BUSY = 0x00000020,
13253GRBM_PERF_SEL_GE_NO_DMA_BUSY = 0x00000021,
13254GRBM_PERF_SEL_UTCL2_BUSY = 0x00000022,
13255GRBM_PERF_SEL_EA_BUSY = 0x00000023,
13256GRBM_PERF_SEL_UTCL1_BUSY = 0x00000027,
13257GRBM_PERF_SEL_GL2CC_BUSY = 0x00000028,
13258GRBM_PERF_SEL_SDMA_BUSY = 0x00000029,
13259GRBM_PERF_SEL_CH_BUSY = 0x0000002a,
13260GRBM_PERF_SEL_PMM_BUSY = 0x0000002c,
13261GRBM_PERF_SEL_GUS_BUSY = 0x0000002d,
13262GRBM_PERF_SEL_GL1CC_BUSY = 0x0000002e,
13263GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 0x0000002f,
13264GRBM_PERF_SEL_GL1XCC_BUSY = 0x00000030,
13265GRBM_PERF_SEL_PC_BUSY = 0x00000031,
13266} GRBM_PERF_SEL;
13267
13268/*******************************************************
13269 * CP Enums
13270 *******************************************************/
13271
13272/*
13273 * CPC_LATENCY_STATS_SEL enum
13274 */
13275
13276typedef enum CPC_LATENCY_STATS_SEL {
13277CPC_LATENCY_STATS_SEL_XACK_MAX = 0x00000000,
13278CPC_LATENCY_STATS_SEL_XACK_MIN = 0x00000001,
13279CPC_LATENCY_STATS_SEL_XACK_LAST = 0x00000002,
13280CPC_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003,
13281CPC_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004,
13282CPC_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005,
13283CPC_LATENCY_STATS_SEL_INVAL_MAX = 0x00000006,
13284CPC_LATENCY_STATS_SEL_INVAL_MIN = 0x00000007,
13285CPC_LATENCY_STATS_SEL_INVAL_LAST = 0x00000008,
13286} CPC_LATENCY_STATS_SEL;
13287
13288/*
13289 * CPC_PERFCOUNT_SEL enum
13290 */
13291
13292typedef enum CPC_PERFCOUNT_SEL {
13293CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000,
13294CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001,
13295CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002,
13296CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005,
13297CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006,
13298CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007,
13299CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008,
13300CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_READ = 0x00000009,
13301CPC_PERF_SEL_ME1_STALL_WAIT_ON_MEM_WRITE = 0x0000000a,
13302CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b,
13303CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c,
13304CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d,
13305CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e,
13306CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f,
13307CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010,
13308CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_READ = 0x00000011,
13309CPC_PERF_SEL_ME2_STALL_WAIT_ON_MEM_WRITE = 0x00000012,
13310CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013,
13311CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014,
13312CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015,
13313CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000016,
13314CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000017,
13315CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000018,
13316CPC_PERF_SEL_CPC_STAT_BUSY = 0x00000019,
13317CPC_PERF_SEL_CPC_STAT_IDLE = 0x0000001a,
13318CPC_PERF_SEL_CPC_STAT_STALL = 0x0000001b,
13319CPC_PERF_SEL_CPC_TCIU_BUSY = 0x0000001c,
13320CPC_PERF_SEL_CPC_TCIU_IDLE = 0x0000001d,
13321CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 0x0000001e,
13322CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 0x0000001f,
13323CPC_PERF_SEL_CPC_UTCL2IU_STALL = 0x00000020,
13324CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 0x00000021,
13325CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 0x00000022,
13326CPC_PERF_SEL_CPC_GCRIU_BUSY = 0x00000023,
13327CPC_PERF_SEL_CPC_GCRIU_IDLE = 0x00000024,
13328CPC_PERF_SEL_CPC_GCRIU_STALL = 0x00000025,
13329CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000026,
13330CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 0x00000027,
13331CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 0x00000028,
13332CPC_PERF_SEL_CPC_UTCL2IU_XACK = 0x00000029,
13333CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 0x0000002a,
13334CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 0x0000002b,
13335CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 0x0000002c,
13336CPC_PERF_SEL_MES_THREAD0 = 0x0000002d,
13337CPC_PERF_SEL_MES_THREAD1 = 0x0000002e,
13338CPC_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002f,
13339CPC_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000030,
13340CPC_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000031,
13341CPC_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x00000032,
13342CPC_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000033,
13343CPC_PERF_SEL_MEC_THREAD0 = 0x00000034,
13344CPC_PERF_SEL_MEC_THREAD1 = 0x00000035,
13345CPC_PERF_SEL_MEC_THREAD2 = 0x00000036,
13346CPC_PERF_SEL_MEC_THREAD3 = 0x00000037,
13347} CPC_PERFCOUNT_SEL;
13348
13349/*
13350 * CPF_LATENCY_STATS_SEL enum
13351 */
13352
13353typedef enum CPF_LATENCY_STATS_SEL {
13354CPF_LATENCY_STATS_SEL_XACK_MAX = 0x00000000,
13355CPF_LATENCY_STATS_SEL_XACK_MIN = 0x00000001,
13356CPF_LATENCY_STATS_SEL_XACK_LAST = 0x00000002,
13357CPF_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003,
13358CPF_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004,
13359CPF_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005,
13360CPF_LATENCY_STATS_SEL_READ_MAX = 0x00000006,
13361CPF_LATENCY_STATS_SEL_READ_MIN = 0x00000007,
13362CPF_LATENCY_STATS_SEL_READ_LAST = 0x00000008,
13363CPF_LATENCY_STATS_SEL_INVAL_MAX = 0x00000009,
13364CPF_LATENCY_STATS_SEL_INVAL_MIN = 0x0000000a,
13365CPF_LATENCY_STATS_SEL_INVAL_LAST = 0x0000000b,
13366} CPF_LATENCY_STATS_SEL;
13367
13368/*
13369 * CPF_PERFCOUNTWINDOW_SEL enum
13370 */
13371
13372typedef enum CPF_PERFCOUNTWINDOW_SEL {
13373CPF_PERFWINDOW_SEL_CSF = 0x00000000,
13374CPF_PERFWINDOW_SEL_HQD1 = 0x00000001,
13375CPF_PERFWINDOW_SEL_HQD2 = 0x00000002,
13376CPF_PERFWINDOW_SEL_RDMA = 0x00000003,
13377CPF_PERFWINDOW_SEL_RWPP = 0x00000004,
13378} CPF_PERFCOUNTWINDOW_SEL;
13379
13380/*
13381 * CPF_PERFCOUNT_SEL enum
13382 */
13383
13384typedef enum CPF_PERFCOUNT_SEL {
13385CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000,
13386CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002,
13387CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003,
13388CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004,
13389CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005,
13390CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006,
13391CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 0x00000007,
13392CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a,
13393CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b,
13394CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c,
13395CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d,
13396CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e,
13397CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x0000000f,
13398CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000010,
13399CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000011,
13400CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000012,
13401CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 0x00000013,
13402CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 0x00000014,
13403CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000015,
13404CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000016,
13405CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000017,
13406CPF_PERF_SEL_CPF_STAT_BUSY = 0x00000018,
13407CPF_PERF_SEL_CPF_STAT_IDLE = 0x00000019,
13408CPF_PERF_SEL_CPF_STAT_STALL = 0x0000001a,
13409CPF_PERF_SEL_CPF_TCIU_BUSY = 0x0000001b,
13410CPF_PERF_SEL_CPF_TCIU_IDLE = 0x0000001c,
13411CPF_PERF_SEL_CPF_TCIU_STALL = 0x0000001d,
13412CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 0x0000001e,
13413CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 0x0000001f,
13414CPF_PERF_SEL_CPF_UTCL2IU_STALL = 0x00000020,
13415CPF_PERF_SEL_CPF_GCRIU_BUSY = 0x00000021,
13416CPF_PERF_SEL_CPF_GCRIU_IDLE = 0x00000022,
13417CPF_PERF_SEL_CPF_GCRIU_STALL = 0x00000023,
13418CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000024,
13419CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 0x00000025,
13420CPF_PERF_SEL_CPF_UTCL2IU_XACK = 0x00000026,
13421CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 0x00000027,
13422CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 0x00000028,
13423CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 0x00000029,
13424CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 0x0000002a,
13425CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 0x0000002b,
13426} CPF_PERFCOUNT_SEL;
13427
13428/*
13429 * CPF_SCRATCH_REG_ATOMIC_OP enum
13430 */
13431
13432typedef enum CPF_SCRATCH_REG_ATOMIC_OP {
13433CPF_SCRATCH_REG_ATOMIC_ADD = 0x00000000,
13434CPF_SCRATCH_REG_ATOMIC_SUB = 0x00000001,
13435CPF_SCRATCH_REG_ATOMIC_OR = 0x00000002,
13436CPF_SCRATCH_REG_ATOMIC_AND = 0x00000003,
13437CPF_SCRATCH_REG_ATOMIC_NOT = 0x00000004,
13438CPF_SCRATCH_REG_ATOMIC_MIN = 0x00000005,
13439CPF_SCRATCH_REG_ATOMIC_MAX = 0x00000006,
13440CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 0x00000007,
13441} CPF_SCRATCH_REG_ATOMIC_OP;
13442
13443/*
13444 * CPG_LATENCY_STATS_SEL enum
13445 */
13446
13447typedef enum CPG_LATENCY_STATS_SEL {
13448CPG_LATENCY_STATS_SEL_XACK_MAX = 0x00000000,
13449CPG_LATENCY_STATS_SEL_XACK_MIN = 0x00000001,
13450CPG_LATENCY_STATS_SEL_XACK_LAST = 0x00000002,
13451CPG_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003,
13452CPG_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004,
13453CPG_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005,
13454CPG_LATENCY_STATS_SEL_WRITE_MAX = 0x00000006,
13455CPG_LATENCY_STATS_SEL_WRITE_MIN = 0x00000007,
13456CPG_LATENCY_STATS_SEL_WRITE_LAST = 0x00000008,
13457CPG_LATENCY_STATS_SEL_READ_MAX = 0x00000009,
13458CPG_LATENCY_STATS_SEL_READ_MIN = 0x0000000a,
13459CPG_LATENCY_STATS_SEL_READ_LAST = 0x0000000b,
13460CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 0x0000000c,
13461CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 0x0000000d,
13462CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 0x0000000e,
13463CPG_LATENCY_STATS_SEL_INVAL_MAX = 0x0000000f,
13464CPG_LATENCY_STATS_SEL_INVAL_MIN = 0x00000010,
13465CPG_LATENCY_STATS_SEL_INVAL_LAST = 0x00000011,
13466} CPG_LATENCY_STATS_SEL;
13467
13468/*
13469 * CPG_PERFCOUNTWINDOW_SEL enum
13470 */
13471
13472typedef enum CPG_PERFCOUNTWINDOW_SEL {
13473CPG_PERFWINDOW_SEL_PFP = 0x00000000,
13474CPG_PERFWINDOW_SEL_ME = 0x00000001,
13475CPG_PERFWINDOW_SEL_CE = 0x00000002,
13476CPG_PERFWINDOW_SEL_MES = 0x00000003,
13477CPG_PERFWINDOW_SEL_MEC1 = 0x00000004,
13478CPG_PERFWINDOW_SEL_MEC2 = 0x00000005,
13479CPG_PERFWINDOW_SEL_DFY = 0x00000006,
13480CPG_PERFWINDOW_SEL_DMA = 0x00000007,
13481CPG_PERFWINDOW_SEL_SHADOW = 0x00000008,
13482CPG_PERFWINDOW_SEL_RB = 0x00000009,
13483CPG_PERFWINDOW_SEL_CEDMA = 0x0000000a,
13484CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 0x0000000b,
13485CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 0x0000000c,
13486CPG_PERFWINDOW_SEL_PQ1 = 0x0000000d,
13487CPG_PERFWINDOW_SEL_PQ2 = 0x0000000e,
13488CPG_PERFWINDOW_SEL_PQ3 = 0x0000000f,
13489CPG_PERFWINDOW_SEL_MEMWR = 0x00000010,
13490CPG_PERFWINDOW_SEL_MEMRD = 0x00000011,
13491CPG_PERFWINDOW_SEL_VGT0 = 0x00000012,
13492CPG_PERFWINDOW_SEL_VGT1 = 0x00000013,
13493CPG_PERFWINDOW_SEL_APPEND = 0x00000014,
13494CPG_PERFWINDOW_SEL_QURD = 0x00000015,
13495CPG_PERFWINDOW_SEL_DDID = 0x00000016,
13496CPG_PERFWINDOW_SEL_SR = 0x00000017,
13497CPG_PERFWINDOW_SEL_QU_EOP = 0x00000018,
13498CPG_PERFWINDOW_SEL_QU_STRM = 0x00000019,
13499CPG_PERFWINDOW_SEL_QU_PIPE = 0x0000001a,
13500CPG_PERFWINDOW_SEL_RESERVED1 = 0x0000001b,
13501CPG_PERFWINDOW_SEL_CPC_IC = 0x0000001c,
13502CPG_PERFWINDOW_SEL_RESERVED2 = 0x0000001d,
13503CPG_PERFWINDOW_SEL_CPG_IC = 0x0000001e,
13504} CPG_PERFCOUNTWINDOW_SEL;
13505
13506/*
13507 * CPG_PERFCOUNT_SEL enum
13508 */
13509
13510typedef enum CPG_PERFCOUNT_SEL {
13511CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000,
13512CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001,
13513CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004,
13514CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005,
13515CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006,
13516CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007,
13517CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009,
13518CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a,
13519CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b,
13520CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c,
13521CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d,
13522CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e,
13523CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f,
13524CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010,
13525CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011,
13526CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012,
13527CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013,
13528CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014,
13529CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015,
13530CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016,
13531CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017,
13532CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018,
13533CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019,
13534CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a,
13535CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b,
13536CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c,
13537CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d,
13538CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f,
13539CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020,
13540CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021,
13541CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x00000022,
13542CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000023,
13543CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024,
13544CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025,
13545CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026,
13546CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027,
13547CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029,
13548CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a,
13549CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b,
13550CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c,
13551CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d,
13552CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x0000002e,
13553CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x0000002f,
13554CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000030,
13555CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000031,
13556CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000032,
13557CPG_PERF_SEL_CPG_STAT_BUSY = 0x00000033,
13558CPG_PERF_SEL_CPG_STAT_IDLE = 0x00000034,
13559CPG_PERF_SEL_CPG_STAT_STALL = 0x00000035,
13560CPG_PERF_SEL_CPG_TCIU_BUSY = 0x00000036,
13561CPG_PERF_SEL_CPG_TCIU_IDLE = 0x00000037,
13562CPG_PERF_SEL_CPG_TCIU_STALL = 0x00000038,
13563CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 0x00000039,
13564CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 0x0000003a,
13565CPG_PERF_SEL_CPG_UTCL2IU_STALL = 0x0000003b,
13566CPG_PERF_SEL_CPG_GCRIU_BUSY = 0x0000003c,
13567CPG_PERF_SEL_CPG_GCRIU_IDLE = 0x0000003d,
13568CPG_PERF_SEL_CPG_GCRIU_STALL = 0x0000003e,
13569CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x0000003f,
13570CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 0x00000040,
13571CPG_PERF_SEL_CPG_UTCL2IU_XACK = 0x00000041,
13572CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 0x00000042,
13573CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 0x00000043,
13574CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 0x00000044,
13575CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 0x00000045,
13576CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 0x00000046,
13577CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 0x00000047,
13578CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 0x00000048,
13579CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 0x00000049,
13580CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 0x0000004a,
13581CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 0x0000004b,
13582CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 0x0000004c,
13583CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 0x0000004d,
13584CPG_PERF_SEL_DMA_BUSY = 0x0000004e,
13585CPG_PERF_SEL_DMA_STARVED = 0x0000004f,
13586CPG_PERF_SEL_DMA_STALLED = 0x00000050,
13587CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 0x00000051,
13588CPG_PERF_SEL_PFP_PWS_STALLED0 = 0x00000052,
13589CPG_PERF_SEL_ME_PWS_STALLED0 = 0x00000053,
13590CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS0 = 0x00000054,
13591CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS0 = 0x00000055,
13592CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL0 = 0x00000056,
13593CPG_PERF_SEL_PFP_PWS_STALLED1 = 0x00000057,
13594CPG_PERF_SEL_ME_PWS_STALLED1 = 0x00000058,
13595CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_BYPASS1 = 0x00000059,
13596CPG_PERF_SEL_PFP_VGTDMA_INDR_STRUCT_NOT_BYPASS1 = 0x0000005a,
13597CPG_PERF_SEL_PFP_VGTDMA_DB_ROQ_DATA_STALL1 = 0x0000005b,
13598} CPG_PERFCOUNT_SEL;
13599
13600/*
13601 * CP_ALPHA_TAG_RAM_SEL enum
13602 */
13603
13604typedef enum CP_ALPHA_TAG_RAM_SEL {
13605CPG_TAG_RAM = 0x00000000,
13606CPC_TAG_RAM = 0x00000001,
13607CPF_TAG_RAM = 0x00000002,
13608RSV_TAG_RAM = 0x00000003,
13609} CP_ALPHA_TAG_RAM_SEL;
13610
13611/*
13612 * CP_DDID_CNTL_MODE enum
13613 */
13614
13615typedef enum CP_DDID_CNTL_MODE {
13616STALL = 0x00000000,
13617OVERRUN = 0x00000001,
13618} CP_DDID_CNTL_MODE;
13619
13620/*
13621 * CP_DDID_CNTL_SIZE enum
13622 */
13623
13624typedef enum CP_DDID_CNTL_SIZE {
13625SIZE_8K = 0x00000000,
13626SIZE_16K = 0x00000001,
13627} CP_DDID_CNTL_SIZE;
13628
13629/*
13630 * CP_DDID_CNTL_VMID_SEL enum
13631 */
13632
13633typedef enum CP_DDID_CNTL_VMID_SEL {
13634DDID_VMID_PIPE = 0x00000000,
13635DDID_VMID_CNTL = 0x00000001,
13636} CP_DDID_CNTL_VMID_SEL;
13637
13638/*
13639 * CP_ME_ID enum
13640 */
13641
13642typedef enum CP_ME_ID {
13643ME_ID0 = 0x00000000,
13644ME_ID1 = 0x00000001,
13645ME_ID2 = 0x00000002,
13646ME_ID3 = 0x00000003,
13647} CP_ME_ID;
13648
13649/*
13650 * CP_PIPE_ID enum
13651 */
13652
13653typedef enum CP_PIPE_ID {
13654PIPE_ID0 = 0x00000000,
13655PIPE_ID1 = 0x00000001,
13656PIPE_ID2 = 0x00000002,
13657PIPE_ID3 = 0x00000003,
13658} CP_PIPE_ID;
13659
13660/*
13661 * CP_RING_ID enum
13662 */
13663
13664typedef enum CP_RING_ID {
13665RINGID0 = 0x00000000,
13666RINGID1 = 0x00000001,
13667RINGID2 = 0x00000002,
13668RINGID3 = 0x00000003,
13669} CP_RING_ID;
13670
13671/*
13672 * IQ_RETRY_TYPE value
13673 */
13674
13675#define IQ_QUEUE_SLEEP 0x00000000
13676#define IQ_OFFLOAD_RETRY 0x00000001
13677#define IQ_SCH_WAVE_MSG 0x00000002
13678#define IQ_DEQUEUE_RETRY 0x00000004
13679
13680/*
13681 * IQ_INTR_TYPE value
13682 */
13683
13684#define IQ_INTR_TYPE_PQ 0x00000000
13685#define IQ_INTR_TYPE_IB 0x00000001
13686#define IQ_INTR_TYPE_MQD 0x00000002
13687
13688/*
13689 * VMID_SIZE value
13690 */
13691
13692#define VMID_SZ 0x00000004
13693
13694/*
13695 * CONFIG_SPACE value
13696 */
13697
13698#define CONFIG_SPACE_START 0x00002000
13699#define CONFIG_SPACE_END 0x00009fff
13700
13701/*
13702 * CONFIG_SPACE1 valu
13703 */
13704
13705#define CONFIG_SPACE1_START 0x00002000
13706#define CONFIG_SPACE1_END 0x00002bff
13707
13708/*
13709 * CONFIG_SPACE2 value
13710 */
13711
13712#define CONFIG_SPACE2_START 0x00003000
13713#define CONFIG_SPACE2_END 0x00009fff
13714
13715/*
13716 * UCONFIG_SPACE value
13717 */
13718
13719#define UCONFIG_SPACE_START 0x0000c000
13720#define UCONFIG_SPACE_END 0x0000ffff
13721
13722/*
13723 * PERSISTENT_SPACE value
13724 */
13725
13726#define PERSISTENT_SPACE_START 0x00002c00
13727#define PERSISTENT_SPACE_END 0x00002fff
13728
13729/*
13730 * CONTEXT_SPACE value
13731 */
13732
13733#define CONTEXT_SPACE_START 0x0000a000
13734#define CONTEXT_SPACE_END 0x0000a3ff
13735
13736/*******************************************************
13737 * GCR Enums
13738 *******************************************************/
13739
13740/*
13741 * GCRPerfSel enum
13742 */
13743
13744typedef enum GCRPerfSel {
13745GCR_PERF_SEL_NONE = 0x00000000,
13746GCR_PERF_SEL_SDMA0_ALL_REQ = 0x00000001,
13747GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 0x00000002,
13748GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 0x00000003,
13749GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 0x00000004,
13750GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 0x00000005,
13751GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 0x00000006,
13752GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 0x00000007,
13753GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 0x00000008,
13754GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 0x00000009,
13755GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 0x0000000a,
13756GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 0x0000000b,
13757GCR_PERF_SEL_SDMA0_METADATA_REQ = 0x0000000c,
13758GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 0x0000000d,
13759GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 0x0000000e,
13760GCR_PERF_SEL_SDMA0_TCP_REQ = 0x0000000f,
13761GCR_PERF_SEL_SDMA0_GL1_TLB_SHOOTDOWN_REQ = 0x00000010,
13762GCR_PERF_SEL_SDMA1_ALL_REQ = 0x00000011,
13763GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 0x00000012,
13764GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 0x00000013,
13765GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 0x00000014,
13766GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 0x00000015,
13767GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 0x00000016,
13768GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 0x00000017,
13769GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 0x00000018,
13770GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 0x00000019,
13771GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 0x0000001a,
13772GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 0x0000001b,
13773GCR_PERF_SEL_SDMA1_METADATA_REQ = 0x0000001c,
13774GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 0x0000001d,
13775GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 0x0000001e,
13776GCR_PERF_SEL_SDMA1_TCP_REQ = 0x0000001f,
13777GCR_PERF_SEL_SDMA1_GL1_TLB_SHOOTDOWN_REQ = 0x00000020,
13778GCR_PERF_SEL_CPC_ALL_REQ = 0x00000021,
13779GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 0x00000022,
13780GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 0x00000023,
13781GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 0x00000024,
13782GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 0x00000025,
13783GCR_PERF_SEL_CPC_GL2_ALL_REQ = 0x00000026,
13784GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 0x00000027,
13785GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 0x00000028,
13786GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 0x00000029,
13787GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 0x0000002a,
13788GCR_PERF_SEL_CPC_GL1_ALL_REQ = 0x0000002b,
13789GCR_PERF_SEL_CPC_METADATA_REQ = 0x0000002c,
13790GCR_PERF_SEL_CPC_SQC_DATA_REQ = 0x0000002d,
13791GCR_PERF_SEL_CPC_SQC_INST_REQ = 0x0000002e,
13792GCR_PERF_SEL_CPC_TCP_REQ = 0x0000002f,
13793GCR_PERF_SEL_CPC_GL1_TLB_SHOOTDOWN_REQ = 0x00000030,
13794GCR_PERF_SEL_CPG_ALL_REQ = 0x00000031,
13795GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 0x00000032,
13796GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 0x00000033,
13797GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 0x00000034,
13798GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 0x00000035,
13799GCR_PERF_SEL_CPG_GL2_ALL_REQ = 0x00000036,
13800GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 0x00000037,
13801GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 0x00000038,
13802GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 0x00000039,
13803GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 0x0000003a,
13804GCR_PERF_SEL_CPG_GL1_ALL_REQ = 0x0000003b,
13805GCR_PERF_SEL_CPG_METADATA_REQ = 0x0000003c,
13806GCR_PERF_SEL_CPG_SQC_DATA_REQ = 0x0000003d,
13807GCR_PERF_SEL_CPG_SQC_INST_REQ = 0x0000003e,
13808GCR_PERF_SEL_CPG_TCP_REQ = 0x0000003f,
13809GCR_PERF_SEL_CPG_GL1_TLB_SHOOTDOWN_REQ = 0x00000040,
13810GCR_PERF_SEL_CPF_ALL_REQ = 0x00000041,
13811GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 0x00000042,
13812GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 0x00000043,
13813GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 0x00000044,
13814GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 0x00000045,
13815GCR_PERF_SEL_CPF_GL2_ALL_REQ = 0x00000046,
13816GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 0x00000047,
13817GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 0x00000048,
13818GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 0x00000049,
13819GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 0x0000004a,
13820GCR_PERF_SEL_CPF_GL1_ALL_REQ = 0x0000004b,
13821GCR_PERF_SEL_CPF_METADATA_REQ = 0x0000004c,
13822GCR_PERF_SEL_CPF_SQC_DATA_REQ = 0x0000004d,
13823GCR_PERF_SEL_CPF_SQC_INST_REQ = 0x0000004e,
13824GCR_PERF_SEL_CPF_TCP_REQ = 0x0000004f,
13825GCR_PERF_SEL_CPF_GL1_TLB_SHOOTDOWN_REQ = 0x00000050,
13826GCR_PERF_SEL_VIRT_REQ = 0x00000051,
13827GCR_PERF_SEL_PHY_REQ = 0x00000052,
13828GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 0x00000053,
13829GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 0x00000054,
13830GCR_PERF_SEL_ALL_REQ = 0x00000055,
13831GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 0x00000056,
13832GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 0x00000057,
13833GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 0x00000058,
13834GCR_PERF_SEL_UTCL2_REQ = 0x00000059,
13835GCR_PERF_SEL_UTCL2_RET = 0x0000005a,
13836GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 0x0000005b,
13837GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 0x0000005c,
13838GCR_PERF_SEL_UTCL2_FILTERED_RET = 0x0000005d,
13839GCR_PERF_SEL_PMM_ABIT_NUM_FLUSH = 0x0000005e,
13840GCR_PERF_SEL_PMM_ABIT_FLUSH_ONGOING = 0x0000005f,
13841GCR_PERF_SEL_PMM_NUM_INTERRUPT = 0x00000060,
13842GCR_PERF_SEL_PMM_STALL_PMM_IH_CREDITS = 0x00000061,
13843GCR_PERF_SEL_PMM_INTERRUPT_READY_TO_SEND = 0x00000062,
13844GCR_PERF_SEL_PMM_ABIT_TIMER_FLUSH = 0x00000063,
13845GCR_PERF_SEL_PMM_ABIT_FORCE_FLUSH = 0x00000064,
13846GCR_PERF_SEL_PMM_ABIT_FLUSH_INTERRUPT = 0x00000065,
13847GCR_PERF_SEL_PMM_ALOG_INTERRUPT = 0x00000066,
13848GCR_PERF_SEL_PMM_MAM_FLUSH_REQ = 0x00000067,
13849GCR_PERF_SEL_PMM_MAM_FLUSH_RESP = 0x00000068,
13850GCR_PERF_SEL_PMM_RLC_CGCG_REQ = 0x00000069,
13851GCR_PERF_SEL_PMM_RLC_CGCG_RESP = 0x0000006a,
13852GCR_PERF_SEL_RLC_ALL_REQ = 0x0000006b,
13853GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 0x0000006c,
13854GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 0x0000006d,
13855GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 0x0000006e,
13856GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 0x0000006f,
13857GCR_PERF_SEL_RLC_GL2_ALL_REQ = 0x00000070,
13858GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 0x00000071,
13859GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 0x00000072,
13860GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 0x00000073,
13861GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 0x00000074,
13862GCR_PERF_SEL_RLC_GL1_ALL_REQ = 0x00000075,
13863GCR_PERF_SEL_RLC_METADATA_REQ = 0x00000076,
13864GCR_PERF_SEL_RLC_SQC_DATA_REQ = 0x00000077,
13865GCR_PERF_SEL_RLC_SQC_INST_REQ = 0x00000078,
13866GCR_PERF_SEL_RLC_TCP_REQ = 0x00000079,
13867GCR_PERF_SEL_RLC_GL1_TLB_SHOOTDOWN_REQ = 0x0000007a,
13868GCR_PERF_SEL_PM_ALL_REQ = 0x0000007b,
13869GCR_PERF_SEL_PM_GL2_RANGE_REQ = 0x0000007c,
13870GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 0x0000007d,
13871GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 0x0000007e,
13872GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 0x0000007f,
13873GCR_PERF_SEL_PM_GL2_ALL_REQ = 0x00000080,
13874GCR_PERF_SEL_PM_GL1_RANGE_REQ = 0x00000081,
13875GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 0x00000082,
13876GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 0x00000083,
13877GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 0x00000084,
13878GCR_PERF_SEL_PM_GL1_ALL_REQ = 0x00000085,
13879GCR_PERF_SEL_PM_METADATA_REQ = 0x00000086,
13880GCR_PERF_SEL_PM_SQC_DATA_REQ = 0x00000087,
13881GCR_PERF_SEL_PM_SQC_INST_REQ = 0x00000088,
13882GCR_PERF_SEL_PM_TCP_REQ = 0x00000089,
13883GCR_PERF_SEL_PM_GL1_TLB_SHOOTDOWN_REQ = 0x0000008a,
13884GCR_PERF_SEL_PIO_ALL_REQ = 0x0000008b,
13885GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 0x0000008c,
13886GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 0x0000008d,
13887GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 0x0000008e,
13888GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 0x0000008f,
13889GCR_PERF_SEL_PIO_GL2_ALL_REQ = 0x00000090,
13890GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 0x00000091,
13891GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 0x00000092,
13892GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 0x00000093,
13893GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 0x00000094,
13894GCR_PERF_SEL_PIO_GL1_ALL_REQ = 0x00000095,
13895GCR_PERF_SEL_PIO_METADATA_REQ = 0x00000096,
13896GCR_PERF_SEL_PIO_SQC_DATA_REQ = 0x00000097,
13897GCR_PERF_SEL_PIO_SQC_INST_REQ = 0x00000098,
13898GCR_PERF_SEL_PIO_TCP_REQ = 0x00000099,
13899GCR_PERF_SEL_PIO_GL1_TLB_SHOOTDOWN_REQ = 0x0000009a,
13900} GCRPerfSel;
13901
13902/*******************************************************
13903 * GC_EA_CPWD Enums
13904 *******************************************************/
13905
13906/*
13907 * GC_EA_CPWD_PERFCOUNT_SEL enum
13908 */
13909
13910typedef enum GC_EA_CPWD_PERFCOUNT_SEL {
13911GC_EA_CPWD_PERF_SEL_ALWAYS_COUNT = 0x00000000,
13912GC_EA_CPWD_PERF_SEL_RDRAM_NUM_BANKS_VLD = 0x00000001,
13913GC_EA_CPWD_PERF_SEL_RDRAM_REQ_PER_CLIGRP = 0x00000002,
13914GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP = 0x00000003,
13915GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START0 = 0x00000004,
13916GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END0 = 0x00000005,
13917GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_START1 = 0x00000006,
13918GC_EA_CPWD_PERF_SEL_RDRAM_LATENCY_END1 = 0x00000007,
13919GC_EA_CPWD_PERF_SEL_WDRAM_NUM_BANKS_VLD = 0x00000008,
13920GC_EA_CPWD_PERF_SEL_WDRAM_REQ_PER_CLIGRP = 0x00000009,
13921GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP = 0x0000000a,
13922GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START0 = 0x0000000b,
13923GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END0 = 0x0000000c,
13924GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_START1 = 0x0000000d,
13925GC_EA_CPWD_PERF_SEL_WDRAM_LATENCY_END1 = 0x0000000e,
13926GC_EA_CPWD_PERF_SEL_RGMI_NUM_BANKS_VLD = 0x0000000f,
13927GC_EA_CPWD_PERF_SEL_RGMI_REQ_PER_CLIGRP = 0x00000010,
13928GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR = 0x00000011,
13929GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START0 = 0x00000012,
13930GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END0 = 0x00000013,
13931GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_START1 = 0x00000014,
13932GC_EA_CPWD_PERF_SEL_RGMI_LATENCY_END1 = 0x00000015,
13933GC_EA_CPWD_PERF_SEL_WGMI_NUM_BANKS_VLD = 0x00000016,
13934GC_EA_CPWD_PERF_SEL_WGMI_REQ_PER_CLIGRP = 0x00000017,
13935GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP = 0x00000018,
13936GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START0 = 0x00000019,
13937GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END0 = 0x0000001a,
13938GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_START1 = 0x0000001b,
13939GC_EA_CPWD_PERF_SEL_WGMI_LATENCY_END1 = 0x0000001c,
13940GC_EA_CPWD_PERF_SEL_RIO_REQ_PER_CLIGRP = 0x0000001d,
13941GC_EA_CPWD_PERF_SEL_RIO_SIZE_REQ = 0x0000001e,
13942GC_EA_CPWD_PERF_SEL_RIO_GRP0_SIZE_REQ = 0x0000001f,
13943GC_EA_CPWD_PERF_SEL_RIO_GRP1_SIZE_REQ = 0x00000020,
13944GC_EA_CPWD_PERF_SEL_RIO_GRP2_SIZE_REQ = 0x00000021,
13945GC_EA_CPWD_PERF_SEL_RIO_GRP3_SIZE_REQ = 0x00000022,
13946GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START0 = 0x00000023,
13947GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END0 = 0x00000024,
13948GC_EA_CPWD_PERF_SEL_RIO_LATENCY_START1 = 0x00000025,
13949GC_EA_CPWD_PERF_SEL_RIO_LATENCY_END1 = 0x00000026,
13950GC_EA_CPWD_PERF_SEL_WIO_REQ_PER_CLIGRP = 0x00000027,
13951GC_EA_CPWD_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP = 0x00000028,
13952GC_EA_CPWD_PERF_SEL_WIO_SIZE_REQ = 0x00000029,
13953GC_EA_CPWD_PERF_SEL_WIO_GRP0_SIZE_REQ = 0x0000002a,
13954GC_EA_CPWD_PERF_SEL_WIO_GRP1_SIZE_REQ = 0x0000002b,
13955GC_EA_CPWD_PERF_SEL_WIO_GRP2_SIZE_REQ = 0x0000002c,
13956GC_EA_CPWD_PERF_SEL_WIO_GRP3_SIZE_REQ = 0x0000002d,
13957GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START0 = 0x0000002e,
13958GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END0 = 0x0000002f,
13959GC_EA_CPWD_PERF_SEL_WIO_LATENCY_START1 = 0x00000030,
13960GC_EA_CPWD_PERF_SEL_WIO_LATENCY_END1 = 0x00000031,
13961GC_EA_CPWD_PERF_SEL_SARB_REQ_PER_VC = 0x00000032,
13962GC_EA_CPWD_PERF_SEL_SARB_DRAM_REQ_PER_VC = 0x00000033,
13963GC_EA_CPWD_PERF_SEL_SARB_GMI_REQ_PER_VC = 0x00000034,
13964GC_EA_CPWD_PERF_SEL_SARB_IO_REQ_PER_VC = 0x00000035,
13965GC_EA_CPWD_PERF_SEL_SARB_SIZE_REQ = 0x00000036,
13966GC_EA_CPWD_PERF_SEL_SARB_DRAM_SIZE_REQ = 0x00000037,
13967GC_EA_CPWD_PERF_SEL_SARB_GMI_SIZE_REQ = 0x00000038,
13968GC_EA_CPWD_PERF_SEL_SARB_IO_SIZE_REQ = 0x00000039,
13969GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START0 = 0x0000003a,
13970GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END0 = 0x0000003b,
13971GC_EA_CPWD_PERF_SEL_SARB_LATENCY_START1 = 0x0000003c,
13972GC_EA_CPWD_PERF_SEL_SARB_LATENCY_END1 = 0x0000003d,
13973GC_EA_CPWD_PERF_SEL_SARB_BUSY = 0x0000003e,
13974GC_EA_CPWD_PERF_SEL_SARB_STALLED = 0x0000003f,
13975GC_EA_CPWD_PERF_SEL_SARB_STARVING = 0x00000040,
13976GC_EA_CPWD_PERF_SEL_SARB_IDLE = 0x00000041,
13977GC_EA_CPWD_PERF_SEL_RRET_VLD = 0x00000042,
13978GC_EA_CPWD_PERF_SEL_WRET_VLD = 0x00000043,
13979GC_EA_CPWD_PERF_SEL_PRB_REQ = 0x00000044,
13980GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_EVICT = 0x00000045,
13981GC_EA_CPWD_PERF_SEL_MAM_ARAM_REQ_VLD = 0x00000046,
13982GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT = 0x00000047,
13983GC_EA_CPWD_PERF_SEL_MAM_NUM_DQRY = 0x00000048,
13984GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT = 0x00000049,
13985GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED = 0x0000004a,
13986GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_COMPLETED = 0x0000004b,
13987GC_EA_CPWD_PERF_SEL_MAM_AFLUSH_ONGOING = 0x0000004c,
13988GC_EA_CPWD_PERF_SEL_RDRAM_SIZE_REQ = 0x0000004d,
13989GC_EA_CPWD_PERF_SEL_WDRAM_SIZE_REQ = 0x0000004e,
13990GC_EA_CPWD_PERF_SEL_RGMI_SIZE_REQ = 0x0000004f,
13991GC_EA_CPWD_PERF_SEL_WGMI_SIZE_REQ = 0x00000050,
13992GC_EA_CPWD_PERF_SEL_SARB_DRAM_RW_TURN_AROUND = 0x00000051,
13993GC_EA_CPWD_PERF_SEL_SARB_GMI_RW_TURN_AROUND = 0x00000052,
13994GC_EA_CPWD_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000053,
13995GC_EA_CPWD_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000054,
13996GC_EA_CPWD_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000055,
13997GC_EA_CPWD_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000056,
13998GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_EVICT = 0x00000057,
13999GC_EA_CPWD_PERF_SEL_MAM_DBIT_REQ_VLD = 0x00000058,
14000GC_EA_CPWD_PERF_SEL_SARB_COHERENT_SIZE_REQ = 0x00000059,
14001GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT_EVICT = 0x0000005a,
14002GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_LRU_EVICT = 0x0000005b,
14003GC_EA_CPWD_PERF_SEL_MAM_FLUSH_REQ = 0x0000005c,
14004GC_EA_CPWD_PERF_SEL_MAM_FLUSH_RESP = 0x0000005d,
14005GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_HIT_EVICT = 0x0000005e,
14006GC_EA_CPWD_PERF_SEL_MAM_DBIT_FA_LRU_EVICT = 0x0000005f,
14007GC_EA_CPWD_PERF_SEL_MAM_DQRY_ONGOING = 0x00000060,
14008GC_EA_CPWD_PERF_SEL_MAM_ARAM_FA_HIT = 0x00000061,
14009} GC_EA_CPWD_PERFCOUNT_SEL;
14010
14011/*******************************************************
14012 * GC_VML2PERFS Enums
14013 *******************************************************/
14014
14015/*
14016 * GCVML2_SPM_PERF_SEL enum
14017 */
14018
14019typedef enum GCVML2_SPM_PERF_SEL {
14020GCVML2_SPM_PERF_SEL_EVENT_0 = 0x00000000,
14021GCVML2_SPM_PERF_SEL_EVENT_1 = 0x00000001,
14022GCVML2_SPM_PERF_SEL_EVENT_2 = 0x00000002,
14023GCVML2_SPM_PERF_SEL_EVENT_3 = 0x00000003,
14024GCVML2_SPM_PERF_SEL_EVENT_4 = 0x00000004,
14025GCVML2_SPM_PERF_SEL_EVENT_5 = 0x00000005,
14026GCVML2_SPM_PERF_SEL_EVENT_6 = 0x00000006,
14027GCVML2_SPM_PERF_SEL_EVENT_7 = 0x00000007,
14028GCVML2_SPM_PERF_SEL_EVENT_8 = 0x00000008,
14029GCVML2_SPM_PERF_SEL_EVENT_9 = 0x00000009,
14030GCVML2_SPM_PERF_SEL_EVENT_10 = 0x0000000a,
14031GCVML2_SPM_PERF_SEL_EVENT_11 = 0x0000000b,
14032GCVML2_SPM_PERF_SEL_EVENT_12 = 0x0000000c,
14033GCVML2_SPM_PERF_SEL_EVENT_13 = 0x0000000d,
14034GCVML2_SPM_PERF_SEL_EVENT_14 = 0x0000000e,
14035GCVML2_SPM_PERF_SEL_EVENT_15 = 0x0000000f,
14036GCVML2_SPM_PERF_SEL_EVENT_16 = 0x00000010,
14037GCVML2_SPM_PERF_SEL_EVENT_17 = 0x00000011,
14038GCVML2_SPM_PERF_SEL_EVENT_18 = 0x00000012,
14039GCVML2_SPM_PERF_SEL_EVENT_19 = 0x00000013,
14040GCVML2_SPM_PERF_SEL_EVENT_20 = 0x00000014,
14041GCVML2_SPM_PERF_SEL_EVENT_21 = 0x00000015,
14042GCVML2_SPM_PERF_SEL_EVENT_22 = 0x00000016,
14043GCVML2_SPM_PERF_SEL_EVENT_23 = 0x00000017,
14044GCVML2_SPM_PERF_SEL_EVENT_24 = 0x00000018,
14045GCVML2_SPM_PERF_SEL_EVENT_25 = 0x00000019,
14046GCVML2_SPM_PERF_SEL_EVENT_26 = 0x0000001a,
14047GCVML2_SPM_PERF_SEL_EVENT_27 = 0x0000001b,
14048GCVML2_SPM_PERF_SEL_EVENT_28 = 0x0000001c,
14049GCVML2_SPM_PERF_SEL_EVENT_29 = 0x0000001d,
14050GCVML2_SPM_PERF_SEL_EVENT_30 = 0x0000001e,
14051GCVML2_SPM_PERF_SEL_EVENT_31 = 0x0000001f,
14052GCVML2_SPM_PERF_SEL_EVENT_32 = 0x00000020,
14053GCVML2_SPM_PERF_SEL_EVENT_33 = 0x00000021,
14054GCVML2_SPM_PERF_SEL_EVENT_34 = 0x00000022,
14055GCVML2_SPM_PERF_SEL_EVENT_35 = 0x00000023,
14056GCVML2_SPM_PERF_SEL_EVENT_36 = 0x00000024,
14057GCVML2_SPM_PERF_SEL_EVENT_37 = 0x00000025,
14058GCVML2_SPM_PERF_SEL_EVENT_38 = 0x00000026,
14059GCVML2_SPM_PERF_SEL_EVENT_39 = 0x00000027,
14060GCVML2_SPM_PERF_SEL_EVENT_40 = 0x00000028,
14061GCVML2_SPM_PERF_SEL_EVENT_41 = 0x00000029,
14062GCVML2_SPM_PERF_SEL_EVENT_42 = 0x0000002a,
14063GCVML2_SPM_PERF_SEL_EVENT_43 = 0x0000002b,
14064GCVML2_SPM_PERF_SEL_EVENT_44 = 0x0000002c,
14065GCVML2_SPM_PERF_SEL_EVENT_45 = 0x0000002d,
14066GCVML2_SPM_PERF_SEL_EVENT_46 = 0x0000002e,
14067GCVML2_SPM_PERF_SEL_EVENT_47 = 0x0000002f,
14068GCVML2_SPM_PERF_SEL_EVENT_48 = 0x00000030,
14069GCVML2_SPM_PERF_SEL_EVENT_49 = 0x00000031,
14070GCVML2_SPM_PERF_SEL_EVENT_50 = 0x00000032,
14071GCVML2_SPM_PERF_SEL_EVENT_51 = 0x00000033,
14072GCVML2_SPM_PERF_SEL_EVENT_52 = 0x00000034,
14073GCVML2_SPM_PERF_SEL_EVENT_53 = 0x00000035,
14074GCVML2_SPM_PERF_SEL_EVENT_54 = 0x00000036,
14075GCVML2_SPM_PERF_SEL_EVENT_55 = 0x00000037,
14076GCVML2_SPM_PERF_SEL_EVENT_56 = 0x00000038,
14077GCVML2_SPM_PERF_SEL_EVENT_57 = 0x00000039,
14078GCVML2_SPM_PERF_SEL_EVENT_58 = 0x0000003a,
14079GCVML2_SPM_PERF_SEL_EVENT_59 = 0x0000003b,
14080GCVML2_SPM_PERF_SEL_EVENT_60 = 0x0000003c,
14081GCVML2_SPM_PERF_SEL_EVENT_61 = 0x0000003d,
14082GCVML2_SPM_PERF_SEL_EVENT_62 = 0x0000003e,
14083GCVML2_SPM_PERF_SEL_EVENT_63 = 0x0000003f,
14084GCVML2_SPM_PERF_SEL_EVENT_64 = 0x00000040,
14085GCVML2_SPM_PERF_SEL_EVENT_65 = 0x00000041,
14086GCVML2_SPM_PERF_SEL_EVENT_66 = 0x00000042,
14087GCVML2_SPM_PERF_SEL_EVENT_67 = 0x00000043,
14088GCVML2_SPM_PERF_SEL_EVENT_68 = 0x00000044,
14089GCVML2_SPM_PERF_SEL_EVENT_69 = 0x00000045,
14090GCVML2_SPM_PERF_SEL_EVENT_70 = 0x00000046,
14091GCVML2_SPM_PERF_SEL_EVENT_71 = 0x00000047,
14092GCVML2_SPM_PERF_SEL_EVENT_72 = 0x00000048,
14093GCVML2_SPM_PERF_SEL_EVENT_73 = 0x00000049,
14094GCVML2_SPM_PERF_SEL_EVENT_74 = 0x0000004a,
14095GCVML2_SPM_PERF_SEL_EVENT_75 = 0x0000004b,
14096GCVML2_SPM_PERF_SEL_EVENT_76 = 0x0000004c,
14097GCVML2_SPM_PERF_SEL_EVENT_77 = 0x0000004d,
14098GCVML2_SPM_PERF_SEL_EVENT_78 = 0x0000004e,
14099GCVML2_SPM_PERF_SEL_EVENT_79 = 0x0000004f,
14100GCVML2_SPM_PERF_SEL_EVENT_80 = 0x00000050,
14101GCVML2_SPM_PERF_SEL_EVENT_81 = 0x00000051,
14102GCVML2_SPM_PERF_SEL_EVENT_82 = 0x00000052,
14103GCVML2_SPM_PERF_SEL_EVENT_83 = 0x00000053,
14104GCVML2_SPM_PERF_SEL_EVENT_84 = 0x00000054,
14105GCVML2_SPM_PERF_SEL_EVENT_85 = 0x00000055,
14106GCVML2_SPM_PERF_SEL_EVENT_86 = 0x00000056,
14107GCVML2_SPM_PERF_SEL_EVENT_87 = 0x00000057,
14108GCVML2_SPM_PERF_SEL_EVENT_88 = 0x00000058,
14109GCVML2_SPM_PERF_SEL_EVENT_89 = 0x00000059,
14110GCVML2_SPM_PERF_SEL_EVENT_90 = 0x0000005a,
14111} GCVML2_SPM_PERF_SEL;
14112
14113/*******************************************************
14114 * GC_VML2PL Enums
14115 *******************************************************/
14116
14117/*
14118 * GCUTCL2_PERF_SEL enum
14119 */
14120
14121typedef enum GCUTCL2_PERF_SEL {
14122GCUTCL2_PERF_SEL_EVENT_0 = 0x00000000,
14123GCUTCL2_PERF_SEL_EVENT_1 = 0x00000001,
14124GCUTCL2_PERF_SEL_EVENT_2 = 0x00000002,
14125GCUTCL2_PERF_SEL_EVENT_3 = 0x00000003,
14126GCUTCL2_PERF_SEL_EVENT_4 = 0x00000004,
14127GCUTCL2_PERF_SEL_EVENT_5 = 0x00000005,
14128GCUTCL2_PERF_SEL_EVENT_6 = 0x00000006,
14129GCUTCL2_PERF_SEL_EVENT_7 = 0x00000007,
14130GCUTCL2_PERF_SEL_EVENT_8 = 0x00000008,
14131GCUTCL2_PERF_SEL_EVENT_9 = 0x00000009,
14132GCUTCL2_PERF_SEL_EVENT_10 = 0x0000000a,
14133GCUTCL2_PERF_SEL_EVENT_11 = 0x0000000b,
14134GCUTCL2_PERF_SEL_EVENT_12 = 0x0000000c,
14135GCUTCL2_PERF_SEL_EVENT_13 = 0x0000000d,
14136GCUTCL2_PERF_SEL_EVENT_14 = 0x0000000e,
14137GCUTCL2_PERF_SEL_EVENT_15 = 0x0000000f,
14138GCUTCL2_PERF_SEL_EVENT_16 = 0x00000010,
14139GCUTCL2_PERF_SEL_EVENT_17 = 0x00000011,
14140GCUTCL2_PERF_SEL_EVENT_18 = 0x00000012,
14141GCUTCL2_PERF_SEL_EVENT_19 = 0x00000013,
14142GCUTCL2_PERF_SEL_EVENT_20 = 0x00000014,
14143GCUTCL2_PERF_SEL_EVENT_21 = 0x00000015,
14144GCUTCL2_PERF_SEL_EVENT_22 = 0x00000016,
14145GCUTCL2_PERF_SEL_EVENT_23 = 0x00000017,
14146GCUTCL2_PERF_SEL_EVENT_24 = 0x00000018,
14147GCUTCL2_PERF_SEL_EVENT_25 = 0x00000019,
14148GCUTCL2_PERF_SEL_EVENT_26 = 0x0000001a,
14149GCUTCL2_PERF_SEL_EVENT_27 = 0x0000001b,
14150GCUTCL2_PERF_SEL_EVENT_28 = 0x0000001c,
14151GCUTCL2_PERF_SEL_EVENT_29 = 0x0000001d,
14152GCUTCL2_PERF_SEL_EVENT_30 = 0x0000001e,
14153GCUTCL2_PERF_SEL_EVENT_31 = 0x0000001f,
14154GCUTCL2_PERF_SEL_EVENT_32 = 0x00000020,
14155GCUTCL2_PERF_SEL_EVENT_33 = 0x00000021,
14156GCUTCL2_PERF_SEL_EVENT_34 = 0x00000022,
14157GCUTCL2_PERF_SEL_EVENT_35 = 0x00000023,
14158GCUTCL2_PERF_SEL_EVENT_36 = 0x00000024,
14159} GCUTCL2_PERF_SEL;
14160
14161/*
14162 * GCVML2_PERF_SEL enum
14163 */
14164
14165typedef enum GCVML2_PERF_SEL {
14166GCVML2_PERF_SEL_EVENT_0 = 0x00000000,
14167GCVML2_PERF_SEL_EVENT_1 = 0x00000001,
14168GCVML2_PERF_SEL_EVENT_2 = 0x00000002,
14169GCVML2_PERF_SEL_EVENT_3 = 0x00000003,
14170GCVML2_PERF_SEL_EVENT_4 = 0x00000004,
14171GCVML2_PERF_SEL_EVENT_5 = 0x00000005,
14172GCVML2_PERF_SEL_EVENT_6 = 0x00000006,
14173GCVML2_PERF_SEL_EVENT_7 = 0x00000007,
14174GCVML2_PERF_SEL_EVENT_8 = 0x00000008,
14175GCVML2_PERF_SEL_EVENT_9 = 0x00000009,
14176GCVML2_PERF_SEL_EVENT_10 = 0x0000000a,
14177GCVML2_PERF_SEL_EVENT_11 = 0x0000000b,
14178GCVML2_PERF_SEL_EVENT_12 = 0x0000000c,
14179GCVML2_PERF_SEL_EVENT_13 = 0x0000000d,
14180GCVML2_PERF_SEL_EVENT_14 = 0x0000000e,
14181GCVML2_PERF_SEL_EVENT_15 = 0x0000000f,
14182GCVML2_PERF_SEL_EVENT_16 = 0x00000010,
14183GCVML2_PERF_SEL_EVENT_17 = 0x00000011,
14184GCVML2_PERF_SEL_EVENT_18 = 0x00000012,
14185GCVML2_PERF_SEL_EVENT_19 = 0x00000013,
14186GCVML2_PERF_SEL_EVENT_20 = 0x00000014,
14187GCVML2_PERF_SEL_EVENT_21 = 0x00000015,
14188GCVML2_PERF_SEL_EVENT_22 = 0x00000016,
14189GCVML2_PERF_SEL_EVENT_23 = 0x00000017,
14190GCVML2_PERF_SEL_EVENT_24 = 0x00000018,
14191GCVML2_PERF_SEL_EVENT_25 = 0x00000019,
14192GCVML2_PERF_SEL_EVENT_26 = 0x0000001a,
14193GCVML2_PERF_SEL_EVENT_27 = 0x0000001b,
14194GCVML2_PERF_SEL_EVENT_28 = 0x0000001c,
14195GCVML2_PERF_SEL_EVENT_29 = 0x0000001d,
14196GCVML2_PERF_SEL_EVENT_30 = 0x0000001e,
14197GCVML2_PERF_SEL_EVENT_31 = 0x0000001f,
14198GCVML2_PERF_SEL_EVENT_32 = 0x00000020,
14199GCVML2_PERF_SEL_EVENT_33 = 0x00000021,
14200GCVML2_PERF_SEL_EVENT_34 = 0x00000022,
14201GCVML2_PERF_SEL_EVENT_35 = 0x00000023,
14202GCVML2_PERF_SEL_EVENT_36 = 0x00000024,
14203GCVML2_PERF_SEL_EVENT_37 = 0x00000025,
14204GCVML2_PERF_SEL_EVENT_38 = 0x00000026,
14205GCVML2_PERF_SEL_EVENT_39 = 0x00000027,
14206GCVML2_PERF_SEL_EVENT_40 = 0x00000028,
14207GCVML2_PERF_SEL_EVENT_41 = 0x00000029,
14208GCVML2_PERF_SEL_EVENT_42 = 0x0000002a,
14209GCVML2_PERF_SEL_EVENT_43 = 0x0000002b,
14210GCVML2_PERF_SEL_EVENT_44 = 0x0000002c,
14211GCVML2_PERF_SEL_EVENT_45 = 0x0000002d,
14212GCVML2_PERF_SEL_EVENT_46 = 0x0000002e,
14213GCVML2_PERF_SEL_EVENT_47 = 0x0000002f,
14214GCVML2_PERF_SEL_EVENT_48 = 0x00000030,
14215GCVML2_PERF_SEL_EVENT_49 = 0x00000031,
14216GCVML2_PERF_SEL_EVENT_50 = 0x00000032,
14217GCVML2_PERF_SEL_EVENT_51 = 0x00000033,
14218GCVML2_PERF_SEL_EVENT_52 = 0x00000034,
14219GCVML2_PERF_SEL_EVENT_53 = 0x00000035,
14220GCVML2_PERF_SEL_EVENT_54 = 0x00000036,
14221GCVML2_PERF_SEL_EVENT_55 = 0x00000037,
14222GCVML2_PERF_SEL_EVENT_56 = 0x00000038,
14223GCVML2_PERF_SEL_EVENT_57 = 0x00000039,
14224GCVML2_PERF_SEL_EVENT_58 = 0x0000003a,
14225GCVML2_PERF_SEL_EVENT_59 = 0x0000003b,
14226GCVML2_PERF_SEL_EVENT_60 = 0x0000003c,
14227GCVML2_PERF_SEL_EVENT_61 = 0x0000003d,
14228GCVML2_PERF_SEL_EVENT_62 = 0x0000003e,
14229GCVML2_PERF_SEL_EVENT_63 = 0x0000003f,
14230GCVML2_PERF_SEL_EVENT_64 = 0x00000040,
14231GCVML2_PERF_SEL_EVENT_65 = 0x00000041,
14232GCVML2_PERF_SEL_EVENT_66 = 0x00000042,
14233GCVML2_PERF_SEL_EVENT_67 = 0x00000043,
14234GCVML2_PERF_SEL_EVENT_68 = 0x00000044,
14235GCVML2_PERF_SEL_EVENT_69 = 0x00000045,
14236GCVML2_PERF_SEL_EVENT_70 = 0x00000046,
14237GCVML2_PERF_SEL_EVENT_71 = 0x00000047,
14238GCVML2_PERF_SEL_EVENT_72 = 0x00000048,
14239GCVML2_PERF_SEL_EVENT_73 = 0x00000049,
14240GCVML2_PERF_SEL_EVENT_74 = 0x0000004a,
14241GCVML2_PERF_SEL_EVENT_75 = 0x0000004b,
14242GCVML2_PERF_SEL_EVENT_76 = 0x0000004c,
14243GCVML2_PERF_SEL_EVENT_77 = 0x0000004d,
14244GCVML2_PERF_SEL_EVENT_78 = 0x0000004e,
14245GCVML2_PERF_SEL_EVENT_79 = 0x0000004f,
14246GCVML2_PERF_SEL_EVENT_80 = 0x00000050,
14247GCVML2_PERF_SEL_EVENT_81 = 0x00000051,
14248GCVML2_PERF_SEL_EVENT_82 = 0x00000052,
14249GCVML2_PERF_SEL_EVENT_83 = 0x00000053,
14250GCVML2_PERF_SEL_EVENT_84 = 0x00000054,
14251GCVML2_PERF_SEL_EVENT_85 = 0x00000055,
14252GCVML2_PERF_SEL_EVENT_86 = 0x00000056,
14253GCVML2_PERF_SEL_EVENT_87 = 0x00000057,
14254GCVML2_PERF_SEL_EVENT_88 = 0x00000058,
14255GCVML2_PERF_SEL_EVENT_89 = 0x00000059,
14256GCVML2_PERF_SEL_EVENT_90 = 0x0000005a,
14257} GCVML2_PERF_SEL;
14258
14259/*******************************************************
14260 * CB Enums
14261 *******************************************************/
14262
14263/*
14264 * BlendOp enum
14265 */
14266
14267typedef enum BlendOp {
14268BLEND_ZERO = 0x00000000,
14269BLEND_ONE = 0x00000001,
14270BLEND_SRC_COLOR = 0x00000002,
14271BLEND_ONE_MINUS_SRC_COLOR = 0x00000003,
14272BLEND_SRC_ALPHA = 0x00000004,
14273BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005,
14274BLEND_DST_ALPHA = 0x00000006,
14275BLEND_ONE_MINUS_DST_ALPHA = 0x00000007,
14276BLEND_DST_COLOR = 0x00000008,
14277BLEND_ONE_MINUS_DST_COLOR = 0x00000009,
14278BLEND_SRC_ALPHA_SATURATE = 0x0000000a,
14279BLEND_CONSTANT_COLOR = 0x0000000b,
14280BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000c,
14281BLEND_SRC1_COLOR = 0x0000000d,
14282BLEND_INV_SRC1_COLOR = 0x0000000e,
14283BLEND_SRC1_ALPHA = 0x0000000f,
14284BLEND_INV_SRC1_ALPHA = 0x00000010,
14285BLEND_CONSTANT_ALPHA = 0x00000011,
14286BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000012,
14287} BlendOp;
14288
14289/*
14290 * BlendOpt enum
14291 */
14292
14293typedef enum BlendOpt {
14294FORCE_OPT_AUTO = 0x00000000,
14295FORCE_OPT_DISABLE = 0x00000001,
14296FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002,
14297FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003,
14298FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004,
14299FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005,
14300FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006,
14301FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007,
14302} BlendOpt;
14303
14304/*
14305 * CBMode enum
14306 */
14307
14308typedef enum CBMode {
14309CB_DISABLE = 0x00000000,
14310CB_NORMAL = 0x00000001,
14311CB_ELIMINATE_FAST_CLEAR = 0x00000002,
14312CB_DCC_DECOMPRESS = 0x00000003,
14313CB_RESERVED = 0x00000004,
14314} CBMode;
14315
14316/*
14317 * CBPerfClearFilterSel enum
14318 */
14319
14320typedef enum CBPerfClearFilterSel {
14321CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000,
14322CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001,
14323} CBPerfClearFilterSel;
14324
14325/*
14326 * CBPerfOpFilterSel enum
14327 */
14328
14329typedef enum CBPerfOpFilterSel {
14330CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000,
14331CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001,
14332CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002,
14333CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003,
14334CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004,
14335CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005,
14336} CBPerfOpFilterSel;
14337
14338/*
14339 * CBPerfSel enum
14340 */
14341
14342typedef enum CBPerfSel {
14343CB_PERF_SEL_BUSY = 0x00000001,
14344CB_PERF_SEL_DRAWN_BUSY = 0x00000002,
14345CB_PERF_SEL_DRAWN_PIXEL = 0x00000003,
14346CB_PERF_SEL_DRAWN_QUAD = 0x00000004,
14347CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000005,
14348CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 0x0000000f,
14349CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 0x00000010,
14350CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 0x00000011,
14351CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 0x00000012,
14352CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST = 0x00000015,
14353CB_PERF_SEL_CC_CRW_GLX_REQ_READ_REQUEST_IN_FLIGHT = 0x00000016,
14354CB_PERF_SEL_CC_CRW_GLX_REQ_WRITE_REQUEST = 0x00000017,
14355CB_PERF_SEL_CC_CRW_GLX_SRC_WRITE_CYCLES = 0x00000018,
14356CB_PERF_SEL_CC_FDCC_COMPRESS_FRAG_TIDS_IN = 0x00000019,
14357CB_PERF_SEL_CC_FDCC_DECOMPRESS_FRAG_TIDS_OUT = 0x0000001a,
14358CB_PERF_SEL_EVENT = 0x00000032,
14359CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x00000033,
14360CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x00000034,
14361CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x00000035,
14362CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000036,
14363CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x00000037,
14364CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x00000038,
14365CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x00000039,
14366CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS = 0x0000003a,
14367CB_PERF_SEL_STATIC_CLOCK_EN = 0x0000003c,
14368CB_PERF_SEL_PERFMON_CLOCK_EN = 0x0000003d,
14369CB_PERF_SEL_BLEND_CLOCK_EN = 0x0000003e,
14370CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 0x0000003f,
14371CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 0x00000040,
14372CB_PERF_SEL_GRBM_CLOCK_EN = 0x00000041,
14373CB_PERF_SEL_MEMARB_CLOCK_EN = 0x00000042,
14374CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 0x00000043,
14375CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 0x00000044,
14376CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 0x00000045,
14377CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 0x00000046,
14378CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 0x00000047,
14379CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 0x00000048,
14380CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 0x00000049,
14381CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 0x0000004a,
14382CB_PERF_SEL_EVENTS_CLK_EN = 0x0000004b,
14383CB_PERF_SEL_CC_TAG_HIT = 0x00000050,
14384CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000051,
14385CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000052,
14386CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 0x00000053,
14387CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x00000058,
14388CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x00000059,
14389CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x0000005a,
14390CB_PERF_SEL_CC_CACHE_STALL = 0x0000005b,
14391CB_PERF_SEL_CC_CACHE_FLUSH = 0x0000005c,
14392CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x0000005d,
14393CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000005e,
14394CB_PERF_SEL_CC_CACHE_QBLOCKS_FLUSHED = 0x0000005f,
14395CB_PERF_SEL_CC_CACHE_DIRTY_QBLOCKS_FLUSHED = 0x00000060,
14396CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x00000061,
14397CB_PERF_SEL_CCC_IN_EVICT_HAZARD_STALL = 0x00000062,
14398CB_PERF_SEL_CCC_COLOR_RESOURCE_PANIC = 0x00000063,
14399CB_PERF_SEL_CCC_FMASK_RESOURCE_PANIC = 0x00000064,
14400CB_PERF_SEL_CCC_FREE_WAYS_PANIC = 0x00000065,
14401CB_PERF_SEL_CCC_SKID_FIFO_FULL = 0x00000066,
14402CB_PERF_SEL_CCC_SKID_FIFO_STALL = 0x00000067,
14403CB_PERF_SEL_CCC_COLOR_RESOURCE_STALL = 0x00000068,
14404CB_PERF_SEL_CCC_FMASK_RESOURCE_STALL = 0x00000069,
14405CB_PERF_SEL_CCC_FREE_WAYS_STALL = 0x0000006a,
14406CB_PERF_SEL_BE_SRCFIFO_FULL = 0x0000006e,
14407CB_PERF_SEL_BE_RDLATFIFO_FULL = 0x0000006f,
14408CB_PERF_SEL_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x00000070,
14409CB_PERF_SEL_CC_QUADFRAG_VALID_READY = 0x00000071,
14410CB_PERF_SEL_CC_QUADFRAG_VALID_READYB = 0x00000072,
14411CB_PERF_SEL_CC_QUADFRAG_VALIDB_READY = 0x00000073,
14412CB_PERF_SEL_CC_QUADFRAG_VALIDB_READYB = 0x00000074,
14413CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READY = 0x00000076,
14414CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALID_READYB = 0x00000077,
14415CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READY = 0x00000078,
14416CB_PERF_SEL_CC_BB_BLEND_PIXEL_VALIDB_READYB = 0x00000079,
14417CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 0x00000096,
14418CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 0x00000097,
14419CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 0x00000098,
14420CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000b4,
14421CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000b5,
14422CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000b6,
14423CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000b7,
14424CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 0x000000b8,
14425CB_PERF_SEL_BLEND_STALL_ON_CACHE_ACCESS = 0x000000b9,
14426CB_PERF_SEL_BLEND_COLLISION_DUE_TO_CACHE_WRITE = 0x000000ba,
14427CB_PERF_SEL_BLEND_RAW_HAZARD_STALL = 0x000000bb,
14428CB_PERF_SEL_BE_CS_FILLRATE_1X2 = 0x000000be,
14429CB_PERF_SEL_BE_CS_FILLRATE_2X1 = 0x000000bf,
14430CB_PERF_SEL_BE_CS_FILLRATE_2X2 = 0x000000c0,
14431CB_PERF_SEL_FORMAT_IS_32_R = 0x000000fa,
14432CB_PERF_SEL_FORMAT_IS_32_AR = 0x000000fb,
14433CB_PERF_SEL_FORMAT_IS_32_GR = 0x000000fc,
14434CB_PERF_SEL_FORMAT_IS_32_ABGR = 0x000000fd,
14435CB_PERF_SEL_FORMAT_IS_FP16_ABGR = 0x000000fe,
14436CB_PERF_SEL_FORMAT_IS_SIGNED16_ABGR = 0x000000ff,
14437CB_PERF_SEL_FORMAT_IS_UNSIGNED16_ABGR = 0x00000100,
14438CB_PERF_SEL_FORMAT_IS_32BPP_8PIX = 0x00000101,
14439CB_PERF_SEL_FORMAT_IS_16_16_UNSIGNED_8PIX = 0x00000102,
14440CB_PERF_SEL_FORMAT_IS_16_16_SIGNED_8PIX = 0x00000103,
14441CB_PERF_SEL_FORMAT_IS_16_16_FLOAT_8PIX = 0x00000104,
14442CB_PERF_SEL_EXPORT_ADDED_1_FRAGMENT = 0x00000105,
14443CB_PERF_SEL_EXPORT_ADDED_2_FRAGMENTS = 0x00000106,
14444CB_PERF_SEL_EXPORT_ADDED_3_FRAGMENTS = 0x00000107,
14445CB_PERF_SEL_EXPORT_ADDED_4_FRAGMENTS = 0x00000108,
14446CB_PERF_SEL_EXPORT_ADDED_5_FRAGMENTS = 0x00000109,
14447CB_PERF_SEL_EXPORT_ADDED_6_FRAGMENTS = 0x0000010a,
14448CB_PERF_SEL_EXPORT_ADDED_7_FRAGMENTS = 0x0000010b,
14449CB_PERF_SEL_EXPORT_BLEND_OPT_DONT_READ_DST = 0x0000010c,
14450CB_PERF_SEL_EXPORT_BLEND_OPT_BLEND_BYPASS = 0x0000010d,
14451CB_PERF_SEL_EXPORT_BLEND_OPT_DISCARD_PIXELS = 0x0000010e,
14452CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_BEFORE_UPDATE = 0x0000010f,
14453CB_PERF_SEL_EXPORT_HAS_1_FRAGMENT_AFTER_UPDATE = 0x00000110,
14454CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0x00000111,
14455CB_PERF_SEL_EXPORT_HAS_2_FRAGMENTS_AFTER_UPDATE = 0x00000112,
14456CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0x00000113,
14457CB_PERF_SEL_EXPORT_HAS_3_FRAGMENTS_AFTER_UPDATE = 0x00000114,
14458CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0x00000115,
14459CB_PERF_SEL_EXPORT_HAS_4_FRAGMENTS_AFTER_UPDATE = 0x00000116,
14460CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0x00000117,
14461CB_PERF_SEL_EXPORT_HAS_5_FRAGMENTS_AFTER_UPDATE = 0x00000118,
14462CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0x00000119,
14463CB_PERF_SEL_EXPORT_HAS_6_FRAGMENTS_AFTER_UPDATE = 0x0000011a,
14464CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0x0000011b,
14465CB_PERF_SEL_EXPORT_HAS_7_FRAGMENTS_AFTER_UPDATE = 0x0000011c,
14466CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0x0000011d,
14467CB_PERF_SEL_EXPORT_HAS_8_FRAGMENTS_AFTER_UPDATE = 0x0000011e,
14468CB_PERF_SEL_EXPORT_READS_FRAGMENT_0 = 0x0000011f,
14469CB_PERF_SEL_EXPORT_READS_FRAGMENT_1 = 0x00000120,
14470CB_PERF_SEL_EXPORT_READS_FRAGMENT_2 = 0x00000121,
14471CB_PERF_SEL_EXPORT_READS_FRAGMENT_3 = 0x00000122,
14472CB_PERF_SEL_EXPORT_READS_FRAGMENT_4 = 0x00000123,
14473CB_PERF_SEL_EXPORT_READS_FRAGMENT_5 = 0x00000124,
14474CB_PERF_SEL_EXPORT_READS_FRAGMENT_6 = 0x00000125,
14475CB_PERF_SEL_EXPORT_READS_FRAGMENT_7 = 0x00000126,
14476CB_PERF_SEL_EXPORT_REMOVED_1_FRAGMENT = 0x00000127,
14477CB_PERF_SEL_EXPORT_REMOVED_2_FRAGMENTS = 0x00000128,
14478CB_PERF_SEL_EXPORT_REMOVED_3_FRAGMENTS = 0x00000129,
14479CB_PERF_SEL_EXPORT_REMOVED_4_FRAGMENTS = 0x0000012a,
14480CB_PERF_SEL_EXPORT_REMOVED_5_FRAGMENTS = 0x0000012b,
14481CB_PERF_SEL_EXPORT_REMOVED_6_FRAGMENTS = 0x0000012c,
14482CB_PERF_SEL_EXPORT_REMOVED_7_FRAGMENTS = 0x0000012d,
14483CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_0 = 0x0000012e,
14484CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_1 = 0x0000012f,
14485CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_2 = 0x00000130,
14486CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_3 = 0x00000131,
14487CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_4 = 0x00000132,
14488CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_5 = 0x00000133,
14489CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_6 = 0x00000134,
14490CB_PERF_SEL_EXPORT_WRITES_FRAGMENT_7 = 0x00000135,
14491CB_PERF_SEL_EXPORT_KILLED_BY_COLOR_INVALID = 0x00000136,
14492CB_PERF_SEL_EXPORT_KILLED_BY_DISCARD_PIXEL = 0x00000137,
14493CB_PERF_SEL_EXPORT_KILLED_BY_NULL_SAMPLE_MASK = 0x00000138,
14494CB_PERF_SEL_EXPORT_KILLED_BY_NULL_TARGET_SHADER_MASK = 0x00000139,
14495} CBPerfSel;
14496
14497/*
14498 * CombFunc enum
14499 */
14500
14501typedef enum CombFunc {
14502COMB_DST_PLUS_SRC = 0x00000000,
14503COMB_SRC_MINUS_DST = 0x00000001,
14504COMB_MIN_DST_SRC = 0x00000002,
14505COMB_MAX_DST_SRC = 0x00000003,
14506COMB_DST_MINUS_SRC = 0x00000004,
14507} CombFunc;
14508
14509/*
14510 * MemArbMode enum
14511 */
14512
14513typedef enum MemArbMode {
14514MEM_ARB_MODE_FIXED = 0x00000000,
14515MEM_ARB_MODE_AGE = 0x00000001,
14516MEM_ARB_MODE_WEIGHT = 0x00000002,
14517MEM_ARB_MODE_BOTH = 0x00000003,
14518} MemArbMode;
14519
14520/*******************************************************
14521 * PH Enums
14522 *******************************************************/
14523
14524/*
14525 * PH_PERFCNT_SEL enum
14526 */
14527
14528typedef enum PH_PERFCNT_SEL {
14529PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0x00000000,
14530PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000001,
14531PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 0x00000002,
14532PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x00000003,
14533PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 0x00000004,
14534PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 0x00000005,
14535PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x00000006,
14536PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x00000007,
14537PH_PERF_SEL_SC0_ARB_BUSY = 0x00000008,
14538PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 0x00000009,
14539PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 0x0000000a,
14540PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 0x0000000b,
14541PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 0x0000000c,
14542PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 0x0000000d,
14543PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x0000000e,
14544PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 0x0000000f,
14545PH_PERF_SEL_SC0_SEND = 0x00000010,
14546PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000011,
14547PH_PERF_SEL_SC0_CREDIT_AT_MAX = 0x00000012,
14548PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000013,
14549PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 0x00000014,
14550PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 0x00000015,
14551PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 0x00000016,
14552PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000017,
14553PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 0x00000018,
14554PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 0x00000019,
14555PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 0x0000001a,
14556PH_PERF_SEL_SC0_PA0_FIFO_FULL = 0x0000001b,
14557PH_PERF_SEL_SC0_PA0_NULL_WE = 0x0000001c,
14558PH_PERF_SEL_SC0_PA0_EVENT_WE = 0x0000001d,
14559PH_PERF_SEL_SC0_PA0_FPOV_WE = 0x0000001e,
14560PH_PERF_SEL_SC0_PA0_FPOP_WE = 0x0000001f,
14561PH_PERF_SEL_SC0_PA0_EOP_WE = 0x00000020,
14562PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 0x00000021,
14563PH_PERF_SEL_SC0_PA0_EOPG_WE = 0x00000022,
14564PH_PERF_SEL_SC0_PA0_DEALLOC_WE = 0x00000023,
14565PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 0x00000024,
14566PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 0x00000025,
14567PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 0x00000026,
14568PH_PERF_SEL_SC0_PA1_FIFO_FULL = 0x00000027,
14569PH_PERF_SEL_SC0_PA1_NULL_WE = 0x00000028,
14570PH_PERF_SEL_SC0_PA1_EVENT_WE = 0x00000029,
14571PH_PERF_SEL_SC0_PA1_FPOV_WE = 0x0000002a,
14572PH_PERF_SEL_SC0_PA1_FPOP_WE = 0x0000002b,
14573PH_PERF_SEL_SC0_PA1_EOP_WE = 0x0000002c,
14574PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 0x0000002d,
14575PH_PERF_SEL_SC0_PA1_EOPG_WE = 0x0000002e,
14576PH_PERF_SEL_SC0_PA1_DEALLOC_WE = 0x0000002f,
14577PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 0x00000030,
14578PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 0x00000031,
14579PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 0x00000032,
14580PH_PERF_SEL_SC0_PA2_FIFO_FULL = 0x00000033,
14581PH_PERF_SEL_SC0_PA2_NULL_WE = 0x00000034,
14582PH_PERF_SEL_SC0_PA2_EVENT_WE = 0x00000035,
14583PH_PERF_SEL_SC0_PA2_FPOV_WE = 0x00000036,
14584PH_PERF_SEL_SC0_PA2_FPOP_WE = 0x00000037,
14585PH_PERF_SEL_SC0_PA2_EOP_WE = 0x00000038,
14586PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 0x00000039,
14587PH_PERF_SEL_SC0_PA2_EOPG_WE = 0x0000003a,
14588PH_PERF_SEL_SC0_PA2_DEALLOC_WE = 0x0000003b,
14589PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 0x0000003c,
14590PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 0x0000003d,
14591PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 0x0000003e,
14592PH_PERF_SEL_SC0_PA3_FIFO_FULL = 0x0000003f,
14593PH_PERF_SEL_SC0_PA3_NULL_WE = 0x00000040,
14594PH_PERF_SEL_SC0_PA3_EVENT_WE = 0x00000041,
14595PH_PERF_SEL_SC0_PA3_FPOV_WE = 0x00000042,
14596PH_PERF_SEL_SC0_PA3_FPOP_WE = 0x00000043,
14597PH_PERF_SEL_SC0_PA3_EOP_WE = 0x00000044,
14598PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 0x00000045,
14599PH_PERF_SEL_SC0_PA3_EOPG_WE = 0x00000046,
14600PH_PERF_SEL_SC0_PA3_DEALLOC_WE = 0x00000047,
14601PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 0x00000048,
14602PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 0x00000049,
14603PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 0x0000004a,
14604PH_PERF_SEL_SC0_PA4_FIFO_FULL = 0x0000004b,
14605PH_PERF_SEL_SC0_PA4_NULL_WE = 0x0000004c,
14606PH_PERF_SEL_SC0_PA4_EVENT_WE = 0x0000004d,
14607PH_PERF_SEL_SC0_PA4_FPOV_WE = 0x0000004e,
14608PH_PERF_SEL_SC0_PA4_FPOP_WE = 0x0000004f,
14609PH_PERF_SEL_SC0_PA4_EOP_WE = 0x00000050,
14610PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 0x00000051,
14611PH_PERF_SEL_SC0_PA4_EOPG_WE = 0x00000052,
14612PH_PERF_SEL_SC0_PA4_DEALLOC_WE = 0x00000053,
14613PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 0x00000054,
14614PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 0x00000055,
14615PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 0x00000056,
14616PH_PERF_SEL_SC0_PA5_FIFO_FULL = 0x00000057,
14617PH_PERF_SEL_SC0_PA5_NULL_WE = 0x00000058,
14618PH_PERF_SEL_SC0_PA5_EVENT_WE = 0x00000059,
14619PH_PERF_SEL_SC0_PA5_FPOV_WE = 0x0000005a,
14620PH_PERF_SEL_SC0_PA5_FPOP_WE = 0x0000005b,
14621PH_PERF_SEL_SC0_PA5_EOP_WE = 0x0000005c,
14622PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 0x0000005d,
14623PH_PERF_SEL_SC0_PA5_EOPG_WE = 0x0000005e,
14624PH_PERF_SEL_SC0_PA5_DEALLOC_WE = 0x0000005f,
14625PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 0x00000060,
14626PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 0x00000061,
14627PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 0x00000062,
14628PH_PERF_SEL_SC0_PA6_FIFO_FULL = 0x00000063,
14629PH_PERF_SEL_SC0_PA6_NULL_WE = 0x00000064,
14630PH_PERF_SEL_SC0_PA6_EVENT_WE = 0x00000065,
14631PH_PERF_SEL_SC0_PA6_FPOV_WE = 0x00000066,
14632PH_PERF_SEL_SC0_PA6_FPOP_WE = 0x00000067,
14633PH_PERF_SEL_SC0_PA6_EOP_WE = 0x00000068,
14634PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 0x00000069,
14635PH_PERF_SEL_SC0_PA6_EOPG_WE = 0x0000006a,
14636PH_PERF_SEL_SC0_PA6_DEALLOC_WE = 0x0000006b,
14637PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 0x0000006c,
14638PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 0x0000006d,
14639PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 0x0000006e,
14640PH_PERF_SEL_SC0_PA7_FIFO_FULL = 0x0000006f,
14641PH_PERF_SEL_SC0_PA7_NULL_WE = 0x00000070,
14642PH_PERF_SEL_SC0_PA7_EVENT_WE = 0x00000071,
14643PH_PERF_SEL_SC0_PA7_FPOV_WE = 0x00000072,
14644PH_PERF_SEL_SC0_PA7_FPOP_WE = 0x00000073,
14645PH_PERF_SEL_SC0_PA7_EOP_WE = 0x00000074,
14646PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 0x00000075,
14647PH_PERF_SEL_SC0_PA7_EOPG_WE = 0x00000076,
14648PH_PERF_SEL_SC0_PA7_DEALLOC_WE = 0x00000077,
14649PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 0x00000078,
14650PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000079,
14651PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000007a,
14652PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000007b,
14653PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 0x0000007c,
14654PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 0x0000007d,
14655PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000007e,
14656PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000007f,
14657PH_PERF_SEL_SC1_ARB_BUSY = 0x00000080,
14658PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 0x00000081,
14659PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 0x00000082,
14660PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 0x00000083,
14661PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 0x00000084,
14662PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 0x00000085,
14663PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000086,
14664PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 0x00000087,
14665PH_PERF_SEL_SC1_SEND = 0x00000088,
14666PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000089,
14667PH_PERF_SEL_SC1_CREDIT_AT_MAX = 0x0000008a,
14668PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000008b,
14669PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 0x0000008c,
14670PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 0x0000008d,
14671PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000008e,
14672PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000008f,
14673PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 0x00000090,
14674PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 0x00000091,
14675PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 0x00000092,
14676PH_PERF_SEL_SC1_PA0_FIFO_FULL = 0x00000093,
14677PH_PERF_SEL_SC1_PA0_NULL_WE = 0x00000094,
14678PH_PERF_SEL_SC1_PA0_EVENT_WE = 0x00000095,
14679PH_PERF_SEL_SC1_PA0_FPOV_WE = 0x00000096,
14680PH_PERF_SEL_SC1_PA0_FPOP_WE = 0x00000097,
14681PH_PERF_SEL_SC1_PA0_EOP_WE = 0x00000098,
14682PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 0x00000099,
14683PH_PERF_SEL_SC1_PA0_EOPG_WE = 0x0000009a,
14684PH_PERF_SEL_SC1_PA0_DEALLOC_WE = 0x0000009b,
14685PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 0x0000009c,
14686PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 0x0000009d,
14687PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 0x0000009e,
14688PH_PERF_SEL_SC1_PA1_FIFO_FULL = 0x0000009f,
14689PH_PERF_SEL_SC1_PA1_NULL_WE = 0x000000a0,
14690PH_PERF_SEL_SC1_PA1_EVENT_WE = 0x000000a1,
14691PH_PERF_SEL_SC1_PA1_FPOV_WE = 0x000000a2,
14692PH_PERF_SEL_SC1_PA1_FPOP_WE = 0x000000a3,
14693PH_PERF_SEL_SC1_PA1_EOP_WE = 0x000000a4,
14694PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 0x000000a5,
14695PH_PERF_SEL_SC1_PA1_EOPG_WE = 0x000000a6,
14696PH_PERF_SEL_SC1_PA1_DEALLOC_WE = 0x000000a7,
14697PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 0x000000a8,
14698PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 0x000000a9,
14699PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 0x000000aa,
14700PH_PERF_SEL_SC1_PA2_FIFO_FULL = 0x000000ab,
14701PH_PERF_SEL_SC1_PA2_NULL_WE = 0x000000ac,
14702PH_PERF_SEL_SC1_PA2_EVENT_WE = 0x000000ad,
14703PH_PERF_SEL_SC1_PA2_FPOV_WE = 0x000000ae,
14704PH_PERF_SEL_SC1_PA2_FPOP_WE = 0x000000af,
14705PH_PERF_SEL_SC1_PA2_EOP_WE = 0x000000b0,
14706PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 0x000000b1,
14707PH_PERF_SEL_SC1_PA2_EOPG_WE = 0x000000b2,
14708PH_PERF_SEL_SC1_PA2_DEALLOC_WE = 0x000000b3,
14709PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 0x000000b4,
14710PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 0x000000b5,
14711PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 0x000000b6,
14712PH_PERF_SEL_SC1_PA3_FIFO_FULL = 0x000000b7,
14713PH_PERF_SEL_SC1_PA3_NULL_WE = 0x000000b8,
14714PH_PERF_SEL_SC1_PA3_EVENT_WE = 0x000000b9,
14715PH_PERF_SEL_SC1_PA3_FPOV_WE = 0x000000ba,
14716PH_PERF_SEL_SC1_PA3_FPOP_WE = 0x000000bb,
14717PH_PERF_SEL_SC1_PA3_EOP_WE = 0x000000bc,
14718PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 0x000000bd,
14719PH_PERF_SEL_SC1_PA3_EOPG_WE = 0x000000be,
14720PH_PERF_SEL_SC1_PA3_DEALLOC_WE = 0x000000bf,
14721PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 0x000000c0,
14722PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 0x000000c1,
14723PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 0x000000c2,
14724PH_PERF_SEL_SC1_PA4_FIFO_FULL = 0x000000c3,
14725PH_PERF_SEL_SC1_PA4_NULL_WE = 0x000000c4,
14726PH_PERF_SEL_SC1_PA4_EVENT_WE = 0x000000c5,
14727PH_PERF_SEL_SC1_PA4_FPOV_WE = 0x000000c6,
14728PH_PERF_SEL_SC1_PA4_FPOP_WE = 0x000000c7,
14729PH_PERF_SEL_SC1_PA4_EOP_WE = 0x000000c8,
14730PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 0x000000c9,
14731PH_PERF_SEL_SC1_PA4_EOPG_WE = 0x000000ca,
14732PH_PERF_SEL_SC1_PA4_DEALLOC_WE = 0x000000cb,
14733PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 0x000000cc,
14734PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 0x000000cd,
14735PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 0x000000ce,
14736PH_PERF_SEL_SC1_PA5_FIFO_FULL = 0x000000cf,
14737PH_PERF_SEL_SC1_PA5_NULL_WE = 0x000000d0,
14738PH_PERF_SEL_SC1_PA5_EVENT_WE = 0x000000d1,
14739PH_PERF_SEL_SC1_PA5_FPOV_WE = 0x000000d2,
14740PH_PERF_SEL_SC1_PA5_FPOP_WE = 0x000000d3,
14741PH_PERF_SEL_SC1_PA5_EOP_WE = 0x000000d4,
14742PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 0x000000d5,
14743PH_PERF_SEL_SC1_PA5_EOPG_WE = 0x000000d6,
14744PH_PERF_SEL_SC1_PA5_DEALLOC_WE = 0x000000d7,
14745PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 0x000000d8,
14746PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 0x000000d9,
14747PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 0x000000da,
14748PH_PERF_SEL_SC1_PA6_FIFO_FULL = 0x000000db,
14749PH_PERF_SEL_SC1_PA6_NULL_WE = 0x000000dc,
14750PH_PERF_SEL_SC1_PA6_EVENT_WE = 0x000000dd,
14751PH_PERF_SEL_SC1_PA6_FPOV_WE = 0x000000de,
14752PH_PERF_SEL_SC1_PA6_FPOP_WE = 0x000000df,
14753PH_PERF_SEL_SC1_PA6_EOP_WE = 0x000000e0,
14754PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 0x000000e1,
14755PH_PERF_SEL_SC1_PA6_EOPG_WE = 0x000000e2,
14756PH_PERF_SEL_SC1_PA6_DEALLOC_WE = 0x000000e3,
14757PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 0x000000e4,
14758PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 0x000000e5,
14759PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 0x000000e6,
14760PH_PERF_SEL_SC1_PA7_FIFO_FULL = 0x000000e7,
14761PH_PERF_SEL_SC1_PA7_NULL_WE = 0x000000e8,
14762PH_PERF_SEL_SC1_PA7_EVENT_WE = 0x000000e9,
14763PH_PERF_SEL_SC1_PA7_FPOV_WE = 0x000000ea,
14764PH_PERF_SEL_SC1_PA7_FPOP_WE = 0x000000eb,
14765PH_PERF_SEL_SC1_PA7_EOP_WE = 0x000000ec,
14766PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 0x000000ed,
14767PH_PERF_SEL_SC1_PA7_EOPG_WE = 0x000000ee,
14768PH_PERF_SEL_SC1_PA7_DEALLOC_WE = 0x000000ef,
14769PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 0x000000f0,
14770PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000000f1,
14771PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 0x000000f2,
14772PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000000f3,
14773PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 0x000000f4,
14774PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 0x000000f5,
14775PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000000f6,
14776PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000000f7,
14777PH_PERF_SEL_SC2_ARB_BUSY = 0x000000f8,
14778PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 0x000000f9,
14779PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 0x000000fa,
14780PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 0x000000fb,
14781PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 0x000000fc,
14782PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 0x000000fd,
14783PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000000fe,
14784PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 0x000000ff,
14785PH_PERF_SEL_SC2_SEND = 0x00000100,
14786PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000101,
14787PH_PERF_SEL_SC2_CREDIT_AT_MAX = 0x00000102,
14788PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000103,
14789PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 0x00000104,
14790PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 0x00000105,
14791PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x00000106,
14792PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000107,
14793PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 0x00000108,
14794PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 0x00000109,
14795PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 0x0000010a,
14796PH_PERF_SEL_SC2_PA0_FIFO_FULL = 0x0000010b,
14797PH_PERF_SEL_SC2_PA0_NULL_WE = 0x0000010c,
14798PH_PERF_SEL_SC2_PA0_EVENT_WE = 0x0000010d,
14799PH_PERF_SEL_SC2_PA0_FPOV_WE = 0x0000010e,
14800PH_PERF_SEL_SC2_PA0_FPOP_WE = 0x0000010f,
14801PH_PERF_SEL_SC2_PA0_EOP_WE = 0x00000110,
14802PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 0x00000111,
14803PH_PERF_SEL_SC2_PA0_EOPG_WE = 0x00000112,
14804PH_PERF_SEL_SC2_PA0_DEALLOC_WE = 0x00000113,
14805PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 0x00000114,
14806PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 0x00000115,
14807PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 0x00000116,
14808PH_PERF_SEL_SC2_PA1_FIFO_FULL = 0x00000117,
14809PH_PERF_SEL_SC2_PA1_NULL_WE = 0x00000118,
14810PH_PERF_SEL_SC2_PA1_EVENT_WE = 0x00000119,
14811PH_PERF_SEL_SC2_PA1_FPOV_WE = 0x0000011a,
14812PH_PERF_SEL_SC2_PA1_FPOP_WE = 0x0000011b,
14813PH_PERF_SEL_SC2_PA1_EOP_WE = 0x0000011c,
14814PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 0x0000011d,
14815PH_PERF_SEL_SC2_PA1_EOPG_WE = 0x0000011e,
14816PH_PERF_SEL_SC2_PA1_DEALLOC_WE = 0x0000011f,
14817PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 0x00000120,
14818PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 0x00000121,
14819PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 0x00000122,
14820PH_PERF_SEL_SC2_PA2_FIFO_FULL = 0x00000123,
14821PH_PERF_SEL_SC2_PA2_NULL_WE = 0x00000124,
14822PH_PERF_SEL_SC2_PA2_EVENT_WE = 0x00000125,
14823PH_PERF_SEL_SC2_PA2_FPOV_WE = 0x00000126,
14824PH_PERF_SEL_SC2_PA2_FPOP_WE = 0x00000127,
14825PH_PERF_SEL_SC2_PA2_EOP_WE = 0x00000128,
14826PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 0x00000129,
14827PH_PERF_SEL_SC2_PA2_EOPG_WE = 0x0000012a,
14828PH_PERF_SEL_SC2_PA2_DEALLOC_WE = 0x0000012b,
14829PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 0x0000012c,
14830PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 0x0000012d,
14831PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 0x0000012e,
14832PH_PERF_SEL_SC2_PA3_FIFO_FULL = 0x0000012f,
14833PH_PERF_SEL_SC2_PA3_NULL_WE = 0x00000130,
14834PH_PERF_SEL_SC2_PA3_EVENT_WE = 0x00000131,
14835PH_PERF_SEL_SC2_PA3_FPOV_WE = 0x00000132,
14836PH_PERF_SEL_SC2_PA3_FPOP_WE = 0x00000133,
14837PH_PERF_SEL_SC2_PA3_EOP_WE = 0x00000134,
14838PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 0x00000135,
14839PH_PERF_SEL_SC2_PA3_EOPG_WE = 0x00000136,
14840PH_PERF_SEL_SC2_PA3_DEALLOC_WE = 0x00000137,
14841PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 0x00000138,
14842PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 0x00000139,
14843PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 0x0000013a,
14844PH_PERF_SEL_SC2_PA4_FIFO_FULL = 0x0000013b,
14845PH_PERF_SEL_SC2_PA4_NULL_WE = 0x0000013c,
14846PH_PERF_SEL_SC2_PA4_EVENT_WE = 0x0000013d,
14847PH_PERF_SEL_SC2_PA4_FPOV_WE = 0x0000013e,
14848PH_PERF_SEL_SC2_PA4_FPOP_WE = 0x0000013f,
14849PH_PERF_SEL_SC2_PA4_EOP_WE = 0x00000140,
14850PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 0x00000141,
14851PH_PERF_SEL_SC2_PA4_EOPG_WE = 0x00000142,
14852PH_PERF_SEL_SC2_PA4_DEALLOC_WE = 0x00000143,
14853PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 0x00000144,
14854PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 0x00000145,
14855PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 0x00000146,
14856PH_PERF_SEL_SC2_PA5_FIFO_FULL = 0x00000147,
14857PH_PERF_SEL_SC2_PA5_NULL_WE = 0x00000148,
14858PH_PERF_SEL_SC2_PA5_EVENT_WE = 0x00000149,
14859PH_PERF_SEL_SC2_PA5_FPOV_WE = 0x0000014a,
14860PH_PERF_SEL_SC2_PA5_FPOP_WE = 0x0000014b,
14861PH_PERF_SEL_SC2_PA5_EOP_WE = 0x0000014c,
14862PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 0x0000014d,
14863PH_PERF_SEL_SC2_PA5_EOPG_WE = 0x0000014e,
14864PH_PERF_SEL_SC2_PA5_DEALLOC_WE = 0x0000014f,
14865PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 0x00000150,
14866PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 0x00000151,
14867PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 0x00000152,
14868PH_PERF_SEL_SC2_PA6_FIFO_FULL = 0x00000153,
14869PH_PERF_SEL_SC2_PA6_NULL_WE = 0x00000154,
14870PH_PERF_SEL_SC2_PA6_EVENT_WE = 0x00000155,
14871PH_PERF_SEL_SC2_PA6_FPOV_WE = 0x00000156,
14872PH_PERF_SEL_SC2_PA6_FPOP_WE = 0x00000157,
14873PH_PERF_SEL_SC2_PA6_EOP_WE = 0x00000158,
14874PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 0x00000159,
14875PH_PERF_SEL_SC2_PA6_EOPG_WE = 0x0000015a,
14876PH_PERF_SEL_SC2_PA6_DEALLOC_WE = 0x0000015b,
14877PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 0x0000015c,
14878PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 0x0000015d,
14879PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 0x0000015e,
14880PH_PERF_SEL_SC2_PA7_FIFO_FULL = 0x0000015f,
14881PH_PERF_SEL_SC2_PA7_NULL_WE = 0x00000160,
14882PH_PERF_SEL_SC2_PA7_EVENT_WE = 0x00000161,
14883PH_PERF_SEL_SC2_PA7_FPOV_WE = 0x00000162,
14884PH_PERF_SEL_SC2_PA7_FPOP_WE = 0x00000163,
14885PH_PERF_SEL_SC2_PA7_EOP_WE = 0x00000164,
14886PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 0x00000165,
14887PH_PERF_SEL_SC2_PA7_EOPG_WE = 0x00000166,
14888PH_PERF_SEL_SC2_PA7_DEALLOC_WE = 0x00000167,
14889PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 0x00000168,
14890PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000169,
14891PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000016a,
14892PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000016b,
14893PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 0x0000016c,
14894PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 0x0000016d,
14895PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000016e,
14896PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000016f,
14897PH_PERF_SEL_SC3_ARB_BUSY = 0x00000170,
14898PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 0x00000171,
14899PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 0x00000172,
14900PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 0x00000173,
14901PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 0x00000174,
14902PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 0x00000175,
14903PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000176,
14904PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 0x00000177,
14905PH_PERF_SEL_SC3_SEND = 0x00000178,
14906PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000179,
14907PH_PERF_SEL_SC3_CREDIT_AT_MAX = 0x0000017a,
14908PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000017b,
14909PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 0x0000017c,
14910PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 0x0000017d,
14911PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000017e,
14912PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000017f,
14913PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 0x00000180,
14914PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 0x00000181,
14915PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 0x00000182,
14916PH_PERF_SEL_SC3_PA0_FIFO_FULL = 0x00000183,
14917PH_PERF_SEL_SC3_PA0_NULL_WE = 0x00000184,
14918PH_PERF_SEL_SC3_PA0_EVENT_WE = 0x00000185,
14919PH_PERF_SEL_SC3_PA0_FPOV_WE = 0x00000186,
14920PH_PERF_SEL_SC3_PA0_FPOP_WE = 0x00000187,
14921PH_PERF_SEL_SC3_PA0_EOP_WE = 0x00000188,
14922PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 0x00000189,
14923PH_PERF_SEL_SC3_PA0_EOPG_WE = 0x0000018a,
14924PH_PERF_SEL_SC3_PA0_DEALLOC_WE = 0x0000018b,
14925PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 0x0000018c,
14926PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 0x0000018d,
14927PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 0x0000018e,
14928PH_PERF_SEL_SC3_PA1_FIFO_FULL = 0x0000018f,
14929PH_PERF_SEL_SC3_PA1_NULL_WE = 0x00000190,
14930PH_PERF_SEL_SC3_PA1_EVENT_WE = 0x00000191,
14931PH_PERF_SEL_SC3_PA1_FPOV_WE = 0x00000192,
14932PH_PERF_SEL_SC3_PA1_FPOP_WE = 0x00000193,
14933PH_PERF_SEL_SC3_PA1_EOP_WE = 0x00000194,
14934PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 0x00000195,
14935PH_PERF_SEL_SC3_PA1_EOPG_WE = 0x00000196,
14936PH_PERF_SEL_SC3_PA1_DEALLOC_WE = 0x00000197,
14937PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 0x00000198,
14938PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 0x00000199,
14939PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 0x0000019a,
14940PH_PERF_SEL_SC3_PA2_FIFO_FULL = 0x0000019b,
14941PH_PERF_SEL_SC3_PA2_NULL_WE = 0x0000019c,
14942PH_PERF_SEL_SC3_PA2_EVENT_WE = 0x0000019d,
14943PH_PERF_SEL_SC3_PA2_FPOV_WE = 0x0000019e,
14944PH_PERF_SEL_SC3_PA2_FPOP_WE = 0x0000019f,
14945PH_PERF_SEL_SC3_PA2_EOP_WE = 0x000001a0,
14946PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 0x000001a1,
14947PH_PERF_SEL_SC3_PA2_EOPG_WE = 0x000001a2,
14948PH_PERF_SEL_SC3_PA2_DEALLOC_WE = 0x000001a3,
14949PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 0x000001a4,
14950PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 0x000001a5,
14951PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 0x000001a6,
14952PH_PERF_SEL_SC3_PA3_FIFO_FULL = 0x000001a7,
14953PH_PERF_SEL_SC3_PA3_NULL_WE = 0x000001a8,
14954PH_PERF_SEL_SC3_PA3_EVENT_WE = 0x000001a9,
14955PH_PERF_SEL_SC3_PA3_FPOV_WE = 0x000001aa,
14956PH_PERF_SEL_SC3_PA3_FPOP_WE = 0x000001ab,
14957PH_PERF_SEL_SC3_PA3_EOP_WE = 0x000001ac,
14958PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 0x000001ad,
14959PH_PERF_SEL_SC3_PA3_EOPG_WE = 0x000001ae,
14960PH_PERF_SEL_SC3_PA3_DEALLOC_WE = 0x000001af,
14961PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 0x000001b0,
14962PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 0x000001b1,
14963PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 0x000001b2,
14964PH_PERF_SEL_SC3_PA4_FIFO_FULL = 0x000001b3,
14965PH_PERF_SEL_SC3_PA4_NULL_WE = 0x000001b4,
14966PH_PERF_SEL_SC3_PA4_EVENT_WE = 0x000001b5,
14967PH_PERF_SEL_SC3_PA4_FPOV_WE = 0x000001b6,
14968PH_PERF_SEL_SC3_PA4_FPOP_WE = 0x000001b7,
14969PH_PERF_SEL_SC3_PA4_EOP_WE = 0x000001b8,
14970PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 0x000001b9,
14971PH_PERF_SEL_SC3_PA4_EOPG_WE = 0x000001ba,
14972PH_PERF_SEL_SC3_PA4_DEALLOC_WE = 0x000001bb,
14973PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 0x000001bc,
14974PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 0x000001bd,
14975PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 0x000001be,
14976PH_PERF_SEL_SC3_PA5_FIFO_FULL = 0x000001bf,
14977PH_PERF_SEL_SC3_PA5_NULL_WE = 0x000001c0,
14978PH_PERF_SEL_SC3_PA5_EVENT_WE = 0x000001c1,
14979PH_PERF_SEL_SC3_PA5_FPOV_WE = 0x000001c2,
14980PH_PERF_SEL_SC3_PA5_FPOP_WE = 0x000001c3,
14981PH_PERF_SEL_SC3_PA5_EOP_WE = 0x000001c4,
14982PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 0x000001c5,
14983PH_PERF_SEL_SC3_PA5_EOPG_WE = 0x000001c6,
14984PH_PERF_SEL_SC3_PA5_DEALLOC_WE = 0x000001c7,
14985PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 0x000001c8,
14986PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 0x000001c9,
14987PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 0x000001ca,
14988PH_PERF_SEL_SC3_PA6_FIFO_FULL = 0x000001cb,
14989PH_PERF_SEL_SC3_PA6_NULL_WE = 0x000001cc,
14990PH_PERF_SEL_SC3_PA6_EVENT_WE = 0x000001cd,
14991PH_PERF_SEL_SC3_PA6_FPOV_WE = 0x000001ce,
14992PH_PERF_SEL_SC3_PA6_FPOP_WE = 0x000001cf,
14993PH_PERF_SEL_SC3_PA6_EOP_WE = 0x000001d0,
14994PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 0x000001d1,
14995PH_PERF_SEL_SC3_PA6_EOPG_WE = 0x000001d2,
14996PH_PERF_SEL_SC3_PA6_DEALLOC_WE = 0x000001d3,
14997PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 0x000001d4,
14998PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 0x000001d5,
14999PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 0x000001d6,
15000PH_PERF_SEL_SC3_PA7_FIFO_FULL = 0x000001d7,
15001PH_PERF_SEL_SC3_PA7_NULL_WE = 0x000001d8,
15002PH_PERF_SEL_SC3_PA7_EVENT_WE = 0x000001d9,
15003PH_PERF_SEL_SC3_PA7_FPOV_WE = 0x000001da,
15004PH_PERF_SEL_SC3_PA7_FPOP_WE = 0x000001db,
15005PH_PERF_SEL_SC3_PA7_EOP_WE = 0x000001dc,
15006PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 0x000001dd,
15007PH_PERF_SEL_SC3_PA7_EOPG_WE = 0x000001de,
15008PH_PERF_SEL_SC3_PA7_DEALLOC_WE = 0x000001df,
15009PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 0x000001e0,
15010PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000001e1,
15011PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 0x000001e2,
15012PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000001e3,
15013PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 0x000001e4,
15014PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 0x000001e5,
15015PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000001e6,
15016PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000001e7,
15017PH_PERF_SEL_SC4_ARB_BUSY = 0x000001e8,
15018PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 0x000001e9,
15019PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 0x000001ea,
15020PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 0x000001eb,
15021PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 0x000001ec,
15022PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 0x000001ed,
15023PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000001ee,
15024PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 0x000001ef,
15025PH_PERF_SEL_SC4_SEND = 0x000001f0,
15026PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001f1,
15027PH_PERF_SEL_SC4_CREDIT_AT_MAX = 0x000001f2,
15028PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001f3,
15029PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 0x000001f4,
15030PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 0x000001f5,
15031PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000001f6,
15032PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000001f7,
15033PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 0x000001f8,
15034PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 0x000001f9,
15035PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 0x000001fa,
15036PH_PERF_SEL_SC4_PA0_FIFO_FULL = 0x000001fb,
15037PH_PERF_SEL_SC4_PA0_NULL_WE = 0x000001fc,
15038PH_PERF_SEL_SC4_PA0_EVENT_WE = 0x000001fd,
15039PH_PERF_SEL_SC4_PA0_FPOV_WE = 0x000001fe,
15040PH_PERF_SEL_SC4_PA0_FPOP_WE = 0x000001ff,
15041PH_PERF_SEL_SC4_PA0_EOP_WE = 0x00000200,
15042PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 0x00000201,
15043PH_PERF_SEL_SC4_PA0_EOPG_WE = 0x00000202,
15044PH_PERF_SEL_SC4_PA0_DEALLOC_WE = 0x00000203,
15045PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 0x00000204,
15046PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 0x00000205,
15047PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 0x00000206,
15048PH_PERF_SEL_SC4_PA1_FIFO_FULL = 0x00000207,
15049PH_PERF_SEL_SC4_PA1_NULL_WE = 0x00000208,
15050PH_PERF_SEL_SC4_PA1_EVENT_WE = 0x00000209,
15051PH_PERF_SEL_SC4_PA1_FPOV_WE = 0x0000020a,
15052PH_PERF_SEL_SC4_PA1_FPOP_WE = 0x0000020b,
15053PH_PERF_SEL_SC4_PA1_EOP_WE = 0x0000020c,
15054PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 0x0000020d,
15055PH_PERF_SEL_SC4_PA1_EOPG_WE = 0x0000020e,
15056PH_PERF_SEL_SC4_PA1_DEALLOC_WE = 0x0000020f,
15057PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 0x00000210,
15058PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 0x00000211,
15059PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 0x00000212,
15060PH_PERF_SEL_SC4_PA2_FIFO_FULL = 0x00000213,
15061PH_PERF_SEL_SC4_PA2_NULL_WE = 0x00000214,
15062PH_PERF_SEL_SC4_PA2_EVENT_WE = 0x00000215,
15063PH_PERF_SEL_SC4_PA2_FPOV_WE = 0x00000216,
15064PH_PERF_SEL_SC4_PA2_FPOP_WE = 0x00000217,
15065PH_PERF_SEL_SC4_PA2_EOP_WE = 0x00000218,
15066PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 0x00000219,
15067PH_PERF_SEL_SC4_PA2_EOPG_WE = 0x0000021a,
15068PH_PERF_SEL_SC4_PA2_DEALLOC_WE = 0x0000021b,
15069PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 0x0000021c,
15070PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 0x0000021d,
15071PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 0x0000021e,
15072PH_PERF_SEL_SC4_PA3_FIFO_FULL = 0x0000021f,
15073PH_PERF_SEL_SC4_PA3_NULL_WE = 0x00000220,
15074PH_PERF_SEL_SC4_PA3_EVENT_WE = 0x00000221,
15075PH_PERF_SEL_SC4_PA3_FPOV_WE = 0x00000222,
15076PH_PERF_SEL_SC4_PA3_FPOP_WE = 0x00000223,
15077PH_PERF_SEL_SC4_PA3_EOP_WE = 0x00000224,
15078PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 0x00000225,
15079PH_PERF_SEL_SC4_PA3_EOPG_WE = 0x00000226,
15080PH_PERF_SEL_SC4_PA3_DEALLOC_WE = 0x00000227,
15081PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 0x00000228,
15082PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 0x00000229,
15083PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 0x0000022a,
15084PH_PERF_SEL_SC4_PA4_FIFO_FULL = 0x0000022b,
15085PH_PERF_SEL_SC4_PA4_NULL_WE = 0x0000022c,
15086PH_PERF_SEL_SC4_PA4_EVENT_WE = 0x0000022d,
15087PH_PERF_SEL_SC4_PA4_FPOV_WE = 0x0000022e,
15088PH_PERF_SEL_SC4_PA4_FPOP_WE = 0x0000022f,
15089PH_PERF_SEL_SC4_PA4_EOP_WE = 0x00000230,
15090PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 0x00000231,
15091PH_PERF_SEL_SC4_PA4_EOPG_WE = 0x00000232,
15092PH_PERF_SEL_SC4_PA4_DEALLOC_WE = 0x00000233,
15093PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 0x00000234,
15094PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 0x00000235,
15095PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 0x00000236,
15096PH_PERF_SEL_SC4_PA5_FIFO_FULL = 0x00000237,
15097PH_PERF_SEL_SC4_PA5_NULL_WE = 0x00000238,
15098PH_PERF_SEL_SC4_PA5_EVENT_WE = 0x00000239,
15099PH_PERF_SEL_SC4_PA5_FPOV_WE = 0x0000023a,
15100PH_PERF_SEL_SC4_PA5_FPOP_WE = 0x0000023b,
15101PH_PERF_SEL_SC4_PA5_EOP_WE = 0x0000023c,
15102PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 0x0000023d,
15103PH_PERF_SEL_SC4_PA5_EOPG_WE = 0x0000023e,
15104PH_PERF_SEL_SC4_PA5_DEALLOC_WE = 0x0000023f,
15105PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 0x00000240,
15106PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 0x00000241,
15107PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 0x00000242,
15108PH_PERF_SEL_SC4_PA6_FIFO_FULL = 0x00000243,
15109PH_PERF_SEL_SC4_PA6_NULL_WE = 0x00000244,
15110PH_PERF_SEL_SC4_PA6_EVENT_WE = 0x00000245,
15111PH_PERF_SEL_SC4_PA6_FPOV_WE = 0x00000246,
15112PH_PERF_SEL_SC4_PA6_FPOP_WE = 0x00000247,
15113PH_PERF_SEL_SC4_PA6_EOP_WE = 0x00000248,
15114PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 0x00000249,
15115PH_PERF_SEL_SC4_PA6_EOPG_WE = 0x0000024a,
15116PH_PERF_SEL_SC4_PA6_DEALLOC_WE = 0x0000024b,
15117PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 0x0000024c,
15118PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 0x0000024d,
15119PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 0x0000024e,
15120PH_PERF_SEL_SC4_PA7_FIFO_FULL = 0x0000024f,
15121PH_PERF_SEL_SC4_PA7_NULL_WE = 0x00000250,
15122PH_PERF_SEL_SC4_PA7_EVENT_WE = 0x00000251,
15123PH_PERF_SEL_SC4_PA7_FPOV_WE = 0x00000252,
15124PH_PERF_SEL_SC4_PA7_FPOP_WE = 0x00000253,
15125PH_PERF_SEL_SC4_PA7_EOP_WE = 0x00000254,
15126PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 0x00000255,
15127PH_PERF_SEL_SC4_PA7_EOPG_WE = 0x00000256,
15128PH_PERF_SEL_SC4_PA7_DEALLOC_WE = 0x00000257,
15129PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 0x00000258,
15130PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000259,
15131PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000025a,
15132PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000025b,
15133PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 0x0000025c,
15134PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 0x0000025d,
15135PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000025e,
15136PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000025f,
15137PH_PERF_SEL_SC5_ARB_BUSY = 0x00000260,
15138PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 0x00000261,
15139PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 0x00000262,
15140PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 0x00000263,
15141PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 0x00000264,
15142PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 0x00000265,
15143PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000266,
15144PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 0x00000267,
15145PH_PERF_SEL_SC5_SEND = 0x00000268,
15146PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000269,
15147PH_PERF_SEL_SC5_CREDIT_AT_MAX = 0x0000026a,
15148PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000026b,
15149PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 0x0000026c,
15150PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 0x0000026d,
15151PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000026e,
15152PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000026f,
15153PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 0x00000270,
15154PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 0x00000271,
15155PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 0x00000272,
15156PH_PERF_SEL_SC5_PA0_FIFO_FULL = 0x00000273,
15157PH_PERF_SEL_SC5_PA0_NULL_WE = 0x00000274,
15158PH_PERF_SEL_SC5_PA0_EVENT_WE = 0x00000275,
15159PH_PERF_SEL_SC5_PA0_FPOV_WE = 0x00000276,
15160PH_PERF_SEL_SC5_PA0_FPOP_WE = 0x00000277,
15161PH_PERF_SEL_SC5_PA0_EOP_WE = 0x00000278,
15162PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 0x00000279,
15163PH_PERF_SEL_SC5_PA0_EOPG_WE = 0x0000027a,
15164PH_PERF_SEL_SC5_PA0_DEALLOC_WE = 0x0000027b,
15165PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 0x0000027c,
15166PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 0x0000027d,
15167PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 0x0000027e,
15168PH_PERF_SEL_SC5_PA1_FIFO_FULL = 0x0000027f,
15169PH_PERF_SEL_SC5_PA1_NULL_WE = 0x00000280,
15170PH_PERF_SEL_SC5_PA1_EVENT_WE = 0x00000281,
15171PH_PERF_SEL_SC5_PA1_FPOV_WE = 0x00000282,
15172PH_PERF_SEL_SC5_PA1_FPOP_WE = 0x00000283,
15173PH_PERF_SEL_SC5_PA1_EOP_WE = 0x00000284,
15174PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 0x00000285,
15175PH_PERF_SEL_SC5_PA1_EOPG_WE = 0x00000286,
15176PH_PERF_SEL_SC5_PA1_DEALLOC_WE = 0x00000287,
15177PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 0x00000288,
15178PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 0x00000289,
15179PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 0x0000028a,
15180PH_PERF_SEL_SC5_PA2_FIFO_FULL = 0x0000028b,
15181PH_PERF_SEL_SC5_PA2_NULL_WE = 0x0000028c,
15182PH_PERF_SEL_SC5_PA2_EVENT_WE = 0x0000028d,
15183PH_PERF_SEL_SC5_PA2_FPOV_WE = 0x0000028e,
15184PH_PERF_SEL_SC5_PA2_FPOP_WE = 0x0000028f,
15185PH_PERF_SEL_SC5_PA2_EOP_WE = 0x00000290,
15186PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 0x00000291,
15187PH_PERF_SEL_SC5_PA2_EOPG_WE = 0x00000292,
15188PH_PERF_SEL_SC5_PA2_DEALLOC_WE = 0x00000293,
15189PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 0x00000294,
15190PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 0x00000295,
15191PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 0x00000296,
15192PH_PERF_SEL_SC5_PA3_FIFO_FULL = 0x00000297,
15193PH_PERF_SEL_SC5_PA3_NULL_WE = 0x00000298,
15194PH_PERF_SEL_SC5_PA3_EVENT_WE = 0x00000299,
15195PH_PERF_SEL_SC5_PA3_FPOV_WE = 0x0000029a,
15196PH_PERF_SEL_SC5_PA3_FPOP_WE = 0x0000029b,
15197PH_PERF_SEL_SC5_PA3_EOP_WE = 0x0000029c,
15198PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 0x0000029d,
15199PH_PERF_SEL_SC5_PA3_EOPG_WE = 0x0000029e,
15200PH_PERF_SEL_SC5_PA3_DEALLOC_WE = 0x0000029f,
15201PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 0x000002a0,
15202PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 0x000002a1,
15203PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 0x000002a2,
15204PH_PERF_SEL_SC5_PA4_FIFO_FULL = 0x000002a3,
15205PH_PERF_SEL_SC5_PA4_NULL_WE = 0x000002a4,
15206PH_PERF_SEL_SC5_PA4_EVENT_WE = 0x000002a5,
15207PH_PERF_SEL_SC5_PA4_FPOV_WE = 0x000002a6,
15208PH_PERF_SEL_SC5_PA4_FPOP_WE = 0x000002a7,
15209PH_PERF_SEL_SC5_PA4_EOP_WE = 0x000002a8,
15210PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 0x000002a9,
15211PH_PERF_SEL_SC5_PA4_EOPG_WE = 0x000002aa,
15212PH_PERF_SEL_SC5_PA4_DEALLOC_WE = 0x000002ab,
15213PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 0x000002ac,
15214PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 0x000002ad,
15215PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 0x000002ae,
15216PH_PERF_SEL_SC5_PA5_FIFO_FULL = 0x000002af,
15217PH_PERF_SEL_SC5_PA5_NULL_WE = 0x000002b0,
15218PH_PERF_SEL_SC5_PA5_EVENT_WE = 0x000002b1,
15219PH_PERF_SEL_SC5_PA5_FPOV_WE = 0x000002b2,
15220PH_PERF_SEL_SC5_PA5_FPOP_WE = 0x000002b3,
15221PH_PERF_SEL_SC5_PA5_EOP_WE = 0x000002b4,
15222PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 0x000002b5,
15223PH_PERF_SEL_SC5_PA5_EOPG_WE = 0x000002b6,
15224PH_PERF_SEL_SC5_PA5_DEALLOC_WE = 0x000002b7,
15225PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 0x000002b8,
15226PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 0x000002b9,
15227PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 0x000002ba,
15228PH_PERF_SEL_SC5_PA6_FIFO_FULL = 0x000002bb,
15229PH_PERF_SEL_SC5_PA6_NULL_WE = 0x000002bc,
15230PH_PERF_SEL_SC5_PA6_EVENT_WE = 0x000002bd,
15231PH_PERF_SEL_SC5_PA6_FPOV_WE = 0x000002be,
15232PH_PERF_SEL_SC5_PA6_FPOP_WE = 0x000002bf,
15233PH_PERF_SEL_SC5_PA6_EOP_WE = 0x000002c0,
15234PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 0x000002c1,
15235PH_PERF_SEL_SC5_PA6_EOPG_WE = 0x000002c2,
15236PH_PERF_SEL_SC5_PA6_DEALLOC_WE = 0x000002c3,
15237PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 0x000002c4,
15238PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 0x000002c5,
15239PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 0x000002c6,
15240PH_PERF_SEL_SC5_PA7_FIFO_FULL = 0x000002c7,
15241PH_PERF_SEL_SC5_PA7_NULL_WE = 0x000002c8,
15242PH_PERF_SEL_SC5_PA7_EVENT_WE = 0x000002c9,
15243PH_PERF_SEL_SC5_PA7_FPOV_WE = 0x000002ca,
15244PH_PERF_SEL_SC5_PA7_FPOP_WE = 0x000002cb,
15245PH_PERF_SEL_SC5_PA7_EOP_WE = 0x000002cc,
15246PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 0x000002cd,
15247PH_PERF_SEL_SC5_PA7_EOPG_WE = 0x000002ce,
15248PH_PERF_SEL_SC5_PA7_DEALLOC_WE = 0x000002cf,
15249PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 0x000002d0,
15250PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000002d1,
15251PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 0x000002d2,
15252PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000002d3,
15253PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 0x000002d4,
15254PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 0x000002d5,
15255PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000002d6,
15256PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000002d7,
15257PH_PERF_SEL_SC6_ARB_BUSY = 0x000002d8,
15258PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 0x000002d9,
15259PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 0x000002da,
15260PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 0x000002db,
15261PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 0x000002dc,
15262PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 0x000002dd,
15263PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000002de,
15264PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 0x000002df,
15265PH_PERF_SEL_SC6_SEND = 0x000002e0,
15266PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000002e1,
15267PH_PERF_SEL_SC6_CREDIT_AT_MAX = 0x000002e2,
15268PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000002e3,
15269PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 0x000002e4,
15270PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 0x000002e5,
15271PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000002e6,
15272PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000002e7,
15273PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 0x000002e8,
15274PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 0x000002e9,
15275PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 0x000002ea,
15276PH_PERF_SEL_SC6_PA0_FIFO_FULL = 0x000002eb,
15277PH_PERF_SEL_SC6_PA0_NULL_WE = 0x000002ec,
15278PH_PERF_SEL_SC6_PA0_EVENT_WE = 0x000002ed,
15279PH_PERF_SEL_SC6_PA0_FPOV_WE = 0x000002ee,
15280PH_PERF_SEL_SC6_PA0_FPOP_WE = 0x000002ef,
15281PH_PERF_SEL_SC6_PA0_EOP_WE = 0x000002f0,
15282PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 0x000002f1,
15283PH_PERF_SEL_SC6_PA0_EOPG_WE = 0x000002f2,
15284PH_PERF_SEL_SC6_PA0_DEALLOC_WE = 0x000002f3,
15285PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 0x000002f4,
15286PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 0x000002f5,
15287PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 0x000002f6,
15288PH_PERF_SEL_SC6_PA1_FIFO_FULL = 0x000002f7,
15289PH_PERF_SEL_SC6_PA1_NULL_WE = 0x000002f8,
15290PH_PERF_SEL_SC6_PA1_EVENT_WE = 0x000002f9,
15291PH_PERF_SEL_SC6_PA1_FPOV_WE = 0x000002fa,
15292PH_PERF_SEL_SC6_PA1_FPOP_WE = 0x000002fb,
15293PH_PERF_SEL_SC6_PA1_EOP_WE = 0x000002fc,
15294PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 0x000002fd,
15295PH_PERF_SEL_SC6_PA1_EOPG_WE = 0x000002fe,
15296PH_PERF_SEL_SC6_PA1_DEALLOC_WE = 0x000002ff,
15297PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 0x00000300,
15298PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 0x00000301,
15299PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 0x00000302,
15300PH_PERF_SEL_SC6_PA2_FIFO_FULL = 0x00000303,
15301PH_PERF_SEL_SC6_PA2_NULL_WE = 0x00000304,
15302PH_PERF_SEL_SC6_PA2_EVENT_WE = 0x00000305,
15303PH_PERF_SEL_SC6_PA2_FPOV_WE = 0x00000306,
15304PH_PERF_SEL_SC6_PA2_FPOP_WE = 0x00000307,
15305PH_PERF_SEL_SC6_PA2_EOP_WE = 0x00000308,
15306PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 0x00000309,
15307PH_PERF_SEL_SC6_PA2_EOPG_WE = 0x0000030a,
15308PH_PERF_SEL_SC6_PA2_DEALLOC_WE = 0x0000030b,
15309PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 0x0000030c,
15310PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 0x0000030d,
15311PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 0x0000030e,
15312PH_PERF_SEL_SC6_PA3_FIFO_FULL = 0x0000030f,
15313PH_PERF_SEL_SC6_PA3_NULL_WE = 0x00000310,
15314PH_PERF_SEL_SC6_PA3_EVENT_WE = 0x00000311,
15315PH_PERF_SEL_SC6_PA3_FPOV_WE = 0x00000312,
15316PH_PERF_SEL_SC6_PA3_FPOP_WE = 0x00000313,
15317PH_PERF_SEL_SC6_PA3_EOP_WE = 0x00000314,
15318PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 0x00000315,
15319PH_PERF_SEL_SC6_PA3_EOPG_WE = 0x00000316,
15320PH_PERF_SEL_SC6_PA3_DEALLOC_WE = 0x00000317,
15321PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 0x00000318,
15322PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 0x00000319,
15323PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 0x0000031a,
15324PH_PERF_SEL_SC6_PA4_FIFO_FULL = 0x0000031b,
15325PH_PERF_SEL_SC6_PA4_NULL_WE = 0x0000031c,
15326PH_PERF_SEL_SC6_PA4_EVENT_WE = 0x0000031d,
15327PH_PERF_SEL_SC6_PA4_FPOV_WE = 0x0000031e,
15328PH_PERF_SEL_SC6_PA4_FPOP_WE = 0x0000031f,
15329PH_PERF_SEL_SC6_PA4_EOP_WE = 0x00000320,
15330PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 0x00000321,
15331PH_PERF_SEL_SC6_PA4_EOPG_WE = 0x00000322,
15332PH_PERF_SEL_SC6_PA4_DEALLOC_WE = 0x00000323,
15333PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 0x00000324,
15334PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 0x00000325,
15335PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 0x00000326,
15336PH_PERF_SEL_SC6_PA5_FIFO_FULL = 0x00000327,
15337PH_PERF_SEL_SC6_PA5_NULL_WE = 0x00000328,
15338PH_PERF_SEL_SC6_PA5_EVENT_WE = 0x00000329,
15339PH_PERF_SEL_SC6_PA5_FPOV_WE = 0x0000032a,
15340PH_PERF_SEL_SC6_PA5_FPOP_WE = 0x0000032b,
15341PH_PERF_SEL_SC6_PA5_EOP_WE = 0x0000032c,
15342PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 0x0000032d,
15343PH_PERF_SEL_SC6_PA5_EOPG_WE = 0x0000032e,
15344PH_PERF_SEL_SC6_PA5_DEALLOC_WE = 0x0000032f,
15345PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 0x00000330,
15346PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 0x00000331,
15347PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 0x00000332,
15348PH_PERF_SEL_SC6_PA6_FIFO_FULL = 0x00000333,
15349PH_PERF_SEL_SC6_PA6_NULL_WE = 0x00000334,
15350PH_PERF_SEL_SC6_PA6_EVENT_WE = 0x00000335,
15351PH_PERF_SEL_SC6_PA6_FPOV_WE = 0x00000336,
15352PH_PERF_SEL_SC6_PA6_FPOP_WE = 0x00000337,
15353PH_PERF_SEL_SC6_PA6_EOP_WE = 0x00000338,
15354PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 0x00000339,
15355PH_PERF_SEL_SC6_PA6_EOPG_WE = 0x0000033a,
15356PH_PERF_SEL_SC6_PA6_DEALLOC_WE = 0x0000033b,
15357PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 0x0000033c,
15358PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 0x0000033d,
15359PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 0x0000033e,
15360PH_PERF_SEL_SC6_PA7_FIFO_FULL = 0x0000033f,
15361PH_PERF_SEL_SC6_PA7_NULL_WE = 0x00000340,
15362PH_PERF_SEL_SC6_PA7_EVENT_WE = 0x00000341,
15363PH_PERF_SEL_SC6_PA7_FPOV_WE = 0x00000342,
15364PH_PERF_SEL_SC6_PA7_FPOP_WE = 0x00000343,
15365PH_PERF_SEL_SC6_PA7_EOP_WE = 0x00000344,
15366PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 0x00000345,
15367PH_PERF_SEL_SC6_PA7_EOPG_WE = 0x00000346,
15368PH_PERF_SEL_SC6_PA7_DEALLOC_WE = 0x00000347,
15369PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 0x00000348,
15370PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000349,
15371PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000034a,
15372PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000034b,
15373PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 0x0000034c,
15374PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 0x0000034d,
15375PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000034e,
15376PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000034f,
15377PH_PERF_SEL_SC7_ARB_BUSY = 0x00000350,
15378PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 0x00000351,
15379PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 0x00000352,
15380PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 0x00000353,
15381PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 0x00000354,
15382PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 0x00000355,
15383PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000356,
15384PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 0x00000357,
15385PH_PERF_SEL_SC7_SEND = 0x00000358,
15386PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000359,
15387PH_PERF_SEL_SC7_CREDIT_AT_MAX = 0x0000035a,
15388PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000035b,
15389PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 0x0000035c,
15390PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 0x0000035d,
15391PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000035e,
15392PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000035f,
15393PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 0x00000360,
15394PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 0x00000361,
15395PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 0x00000362,
15396PH_PERF_SEL_SC7_PA0_FIFO_FULL = 0x00000363,
15397PH_PERF_SEL_SC7_PA0_NULL_WE = 0x00000364,
15398PH_PERF_SEL_SC7_PA0_EVENT_WE = 0x00000365,
15399PH_PERF_SEL_SC7_PA0_FPOV_WE = 0x00000366,
15400PH_PERF_SEL_SC7_PA0_FPOP_WE = 0x00000367,
15401PH_PERF_SEL_SC7_PA0_EOP_WE = 0x00000368,
15402PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 0x00000369,
15403PH_PERF_SEL_SC7_PA0_EOPG_WE = 0x0000036a,
15404PH_PERF_SEL_SC7_PA0_DEALLOC_WE = 0x0000036b,
15405PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 0x0000036c,
15406PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 0x0000036d,
15407PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 0x0000036e,
15408PH_PERF_SEL_SC7_PA1_FIFO_FULL = 0x0000036f,
15409PH_PERF_SEL_SC7_PA1_NULL_WE = 0x00000370,
15410PH_PERF_SEL_SC7_PA1_EVENT_WE = 0x00000371,
15411PH_PERF_SEL_SC7_PA1_FPOV_WE = 0x00000372,
15412PH_PERF_SEL_SC7_PA1_FPOP_WE = 0x00000373,
15413PH_PERF_SEL_SC7_PA1_EOP_WE = 0x00000374,
15414PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 0x00000375,
15415PH_PERF_SEL_SC7_PA1_EOPG_WE = 0x00000376,
15416PH_PERF_SEL_SC7_PA1_DEALLOC_WE = 0x00000377,
15417PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 0x00000378,
15418PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 0x00000379,
15419PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 0x0000037a,
15420PH_PERF_SEL_SC7_PA2_FIFO_FULL = 0x0000037b,
15421PH_PERF_SEL_SC7_PA2_NULL_WE = 0x0000037c,
15422PH_PERF_SEL_SC7_PA2_EVENT_WE = 0x0000037d,
15423PH_PERF_SEL_SC7_PA2_FPOV_WE = 0x0000037e,
15424PH_PERF_SEL_SC7_PA2_FPOP_WE = 0x0000037f,
15425PH_PERF_SEL_SC7_PA2_EOP_WE = 0x00000380,
15426PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 0x00000381,
15427PH_PERF_SEL_SC7_PA2_EOPG_WE = 0x00000382,
15428PH_PERF_SEL_SC7_PA2_DEALLOC_WE = 0x00000383,
15429PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 0x00000384,
15430PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 0x00000385,
15431PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 0x00000386,
15432PH_PERF_SEL_SC7_PA3_FIFO_FULL = 0x00000387,
15433PH_PERF_SEL_SC7_PA3_NULL_WE = 0x00000388,
15434PH_PERF_SEL_SC7_PA3_EVENT_WE = 0x00000389,
15435PH_PERF_SEL_SC7_PA3_FPOV_WE = 0x0000038a,
15436PH_PERF_SEL_SC7_PA3_FPOP_WE = 0x0000038b,
15437PH_PERF_SEL_SC7_PA3_EOP_WE = 0x0000038c,
15438PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 0x0000038d,
15439PH_PERF_SEL_SC7_PA3_EOPG_WE = 0x0000038e,
15440PH_PERF_SEL_SC7_PA3_DEALLOC_WE = 0x0000038f,
15441PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 0x00000390,
15442PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 0x00000391,
15443PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 0x00000392,
15444PH_PERF_SEL_SC7_PA4_FIFO_FULL = 0x00000393,
15445PH_PERF_SEL_SC7_PA4_NULL_WE = 0x00000394,
15446PH_PERF_SEL_SC7_PA4_EVENT_WE = 0x00000395,
15447PH_PERF_SEL_SC7_PA4_FPOV_WE = 0x00000396,
15448PH_PERF_SEL_SC7_PA4_FPOP_WE = 0x00000397,
15449PH_PERF_SEL_SC7_PA4_EOP_WE = 0x00000398,
15450PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 0x00000399,
15451PH_PERF_SEL_SC7_PA4_EOPG_WE = 0x0000039a,
15452PH_PERF_SEL_SC7_PA4_DEALLOC_WE = 0x0000039b,
15453PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 0x0000039c,
15454PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 0x0000039d,
15455PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 0x0000039e,
15456PH_PERF_SEL_SC7_PA5_FIFO_FULL = 0x0000039f,
15457PH_PERF_SEL_SC7_PA5_NULL_WE = 0x000003a0,
15458PH_PERF_SEL_SC7_PA5_EVENT_WE = 0x000003a1,
15459PH_PERF_SEL_SC7_PA5_FPOV_WE = 0x000003a2,
15460PH_PERF_SEL_SC7_PA5_FPOP_WE = 0x000003a3,
15461PH_PERF_SEL_SC7_PA5_EOP_WE = 0x000003a4,
15462PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 0x000003a5,
15463PH_PERF_SEL_SC7_PA5_EOPG_WE = 0x000003a6,
15464PH_PERF_SEL_SC7_PA5_DEALLOC_WE = 0x000003a7,
15465PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 0x000003a8,
15466PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 0x000003a9,
15467PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 0x000003aa,
15468PH_PERF_SEL_SC7_PA6_FIFO_FULL = 0x000003ab,
15469PH_PERF_SEL_SC7_PA6_NULL_WE = 0x000003ac,
15470PH_PERF_SEL_SC7_PA6_EVENT_WE = 0x000003ad,
15471PH_PERF_SEL_SC7_PA6_FPOV_WE = 0x000003ae,
15472PH_PERF_SEL_SC7_PA6_FPOP_WE = 0x000003af,
15473PH_PERF_SEL_SC7_PA6_EOP_WE = 0x000003b0,
15474PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 0x000003b1,
15475PH_PERF_SEL_SC7_PA6_EOPG_WE = 0x000003b2,
15476PH_PERF_SEL_SC7_PA6_DEALLOC_WE = 0x000003b3,
15477PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 0x000003b4,
15478PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 0x000003b5,
15479PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 0x000003b6,
15480PH_PERF_SEL_SC7_PA7_FIFO_FULL = 0x000003b7,
15481PH_PERF_SEL_SC7_PA7_NULL_WE = 0x000003b8,
15482PH_PERF_SEL_SC7_PA7_EVENT_WE = 0x000003b9,
15483PH_PERF_SEL_SC7_PA7_FPOV_WE = 0x000003ba,
15484PH_PERF_SEL_SC7_PA7_FPOP_WE = 0x000003bb,
15485PH_PERF_SEL_SC7_PA7_EOP_WE = 0x000003bc,
15486PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 0x000003bd,
15487PH_PERF_SEL_SC7_PA7_EOPG_WE = 0x000003be,
15488PH_PERF_SEL_SC7_PA7_DEALLOC_WE = 0x000003bf,
15489PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 0x000003c0,
15490PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 0x000003c1,
15491PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 0x000003c2,
15492PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 0x000003c3,
15493PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 0x000003c4,
15494PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 0x000003c5,
15495PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 0x000003c6,
15496PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 0x000003c7,
15497PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 0x000003c8,
15498PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 0x000003c9,
15499PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 0x000003ca,
15500PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 0x000003cb,
15501PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 0x000003cc,
15502PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 0x000003cd,
15503PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 0x000003ce,
15504PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 0x000003cf,
15505PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d0,
15506PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d1,
15507PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d2,
15508PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d3,
15509PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d4,
15510PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d5,
15511PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d6,
15512PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d7,
15513PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003d8,
15514PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003d9,
15515PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003da,
15516PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003db,
15517PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003dc,
15518PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003dd,
15519PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003de,
15520PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003df,
15521PH_PERF_SC0_FIFO_STATUS_0 = 0x000003e0,
15522PH_PERF_SC0_FIFO_STATUS_1 = 0x000003e1,
15523PH_PERF_SC0_FIFO_STATUS_2 = 0x000003e2,
15524PH_PERF_SC0_FIFO_STATUS_3 = 0x000003e3,
15525PH_PERF_SC1_FIFO_STATUS_0 = 0x000003e4,
15526PH_PERF_SC1_FIFO_STATUS_1 = 0x000003e5,
15527PH_PERF_SC1_FIFO_STATUS_2 = 0x000003e6,
15528PH_PERF_SC1_FIFO_STATUS_3 = 0x000003e7,
15529PH_PERF_SC2_FIFO_STATUS_0 = 0x000003e8,
15530PH_PERF_SC2_FIFO_STATUS_1 = 0x000003e9,
15531PH_PERF_SC2_FIFO_STATUS_2 = 0x000003ea,
15532PH_PERF_SC2_FIFO_STATUS_3 = 0x000003eb,
15533PH_PERF_SC3_FIFO_STATUS_0 = 0x000003ec,
15534PH_PERF_SC3_FIFO_STATUS_1 = 0x000003ed,
15535PH_PERF_SC3_FIFO_STATUS_2 = 0x000003ee,
15536PH_PERF_SC3_FIFO_STATUS_3 = 0x000003ef,
15537PH_PERF_SC4_FIFO_STATUS_0 = 0x000003f0,
15538PH_PERF_SC4_FIFO_STATUS_1 = 0x000003f1,
15539PH_PERF_SC4_FIFO_STATUS_2 = 0x000003f2,
15540PH_PERF_SC4_FIFO_STATUS_3 = 0x000003f3,
15541PH_PERF_SC5_FIFO_STATUS_0 = 0x000003f4,
15542PH_PERF_SC5_FIFO_STATUS_1 = 0x000003f5,
15543PH_PERF_SC5_FIFO_STATUS_2 = 0x000003f6,
15544PH_PERF_SC5_FIFO_STATUS_3 = 0x000003f7,
15545PH_PERF_SC6_FIFO_STATUS_0 = 0x000003f8,
15546PH_PERF_SC6_FIFO_STATUS_1 = 0x000003f9,
15547PH_PERF_SC6_FIFO_STATUS_2 = 0x000003fa,
15548PH_PERF_SC6_FIFO_STATUS_3 = 0x000003fb,
15549PH_PERF_SC7_FIFO_STATUS_0 = 0x000003fc,
15550PH_PERF_SC7_FIFO_STATUS_1 = 0x000003fd,
15551PH_PERF_SC7_FIFO_STATUS_2 = 0x000003fe,
15552PH_PERF_SC7_FIFO_STATUS_3 = 0x000003ff,
15553} PH_PERFCNT_SEL;
15554
15555/*
15556 * PhSPIstatusMode enum
15557 */
15558
15559typedef enum PhSPIstatusMode {
15560PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0x00000000,
15561PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 0x00000001,
15562PH_SPI_MODE_DISABLED = 0x00000002,
15563} PhSPIstatusMode;
15564
15565/*******************************************************
15566 * SC Enums
15567 *******************************************************/
15568
15569/*
15570 * BinEventCntl enum
15571 */
15572
15573typedef enum BinEventCntl {
15574BINNER_BREAK_BATCH = 0x00000000,
15575BINNER_PIPELINE = 0x00000001,
15576BINNER_DROP = 0x00000002,
15577BINNER_PIPELINE_BREAK = 0x00000003,
15578} BinEventCntl;
15579
15580/*
15581 * BinMapMode enum
15582 */
15583
15584typedef enum BinMapMode {
15585BIN_MAP_MODE_NONE = 0x00000000,
15586BIN_MAP_MODE_RTA_INDEX = 0x00000001,
15587BIN_MAP_MODE_POPS = 0x00000002,
15588} BinMapMode;
15589
15590/*
15591 * BinSizeExtend enum
15592 */
15593
15594typedef enum BinSizeExtend {
15595BIN_SIZE_32_PIXELS = 0x00000000,
15596BIN_SIZE_64_PIXELS = 0x00000001,
15597BIN_SIZE_128_PIXELS = 0x00000002,
15598BIN_SIZE_256_PIXELS = 0x00000003,
15599BIN_SIZE_512_PIXELS = 0x00000004,
15600} BinSizeExtend;
15601
15602/*
15603 * BinningMode enum
15604 */
15605
15606typedef enum BinningMode {
15607BINNING_ALLOWED = 0x00000000,
15608FORCE_BINNING_ON = 0x00000001,
15609BINNING_ONE_PRIM_PER_BATCH = 0x00000002,
15610BINNING_DISABLED = 0x00000003,
15611} BinningMode;
15612
15613/*
15614 * PkrMap enum
15615 */
15616
15617typedef enum PkrMap {
15618RASTER_CONFIG_PKR_MAP_0 = 0x00000000,
15619RASTER_CONFIG_PKR_MAP_1 = 0x00000001,
15620RASTER_CONFIG_PKR_MAP_2 = 0x00000002,
15621RASTER_CONFIG_PKR_MAP_3 = 0x00000003,
15622} PkrMap;
15623
15624/*
15625 * PkrXsel enum
15626 */
15627
15628typedef enum PkrXsel {
15629RASTER_CONFIG_PKR_XSEL_0 = 0x00000000,
15630RASTER_CONFIG_PKR_XSEL_1 = 0x00000001,
15631RASTER_CONFIG_PKR_XSEL_2 = 0x00000002,
15632RASTER_CONFIG_PKR_XSEL_3 = 0x00000003,
15633} PkrXsel;
15634
15635/*
15636 * PkrXsel2 enum
15637 */
15638
15639typedef enum PkrXsel2 {
15640RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000,
15641RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001,
15642RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002,
15643RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003,
15644} PkrXsel2;
15645
15646/*
15647 * PkrYsel enum
15648 */
15649
15650typedef enum PkrYsel {
15651RASTER_CONFIG_PKR_YSEL_0 = 0x00000000,
15652RASTER_CONFIG_PKR_YSEL_1 = 0x00000001,
15653RASTER_CONFIG_PKR_YSEL_2 = 0x00000002,
15654RASTER_CONFIG_PKR_YSEL_3 = 0x00000003,
15655} PkrYsel;
15656
15657/*
15658 * RbMap enum
15659 */
15660
15661typedef enum RbMap {
15662RASTER_CONFIG_RB_MAP_0 = 0x00000000,
15663RASTER_CONFIG_RB_MAP_1 = 0x00000001,
15664RASTER_CONFIG_RB_MAP_2 = 0x00000002,
15665RASTER_CONFIG_RB_MAP_3 = 0x00000003,
15666} RbMap;
15667
15668/*
15669 * RbXsel enum
15670 */
15671
15672typedef enum RbXsel {
15673RASTER_CONFIG_RB_XSEL_0 = 0x00000000,
15674RASTER_CONFIG_RB_XSEL_1 = 0x00000001,
15675} RbXsel;
15676
15677/*
15678 * RbXsel2 enum
15679 */
15680
15681typedef enum RbXsel2 {
15682RASTER_CONFIG_RB_XSEL2_0 = 0x00000000,
15683RASTER_CONFIG_RB_XSEL2_1 = 0x00000001,
15684RASTER_CONFIG_RB_XSEL2_2 = 0x00000002,
15685RASTER_CONFIG_RB_XSEL2_3 = 0x00000003,
15686} RbXsel2;
15687
15688/*
15689 * RbYsel enum
15690 */
15691
15692typedef enum RbYsel {
15693RASTER_CONFIG_RB_YSEL_0 = 0x00000000,
15694RASTER_CONFIG_RB_YSEL_1 = 0x00000001,
15695} RbYsel;
15696
15697/*
15698 * SC_PERFCNT_SEL enum
15699 */
15700
15701typedef enum SC_PERFCNT_SEL {
15702SC_SRPS_WINDOW_VALID = 0x00000000,
15703SC_PSSW_WINDOW_VALID = 0x00000001,
15704SC_TPQZ_WINDOW_VALID = 0x00000002,
15705SC_QZQP_WINDOW_VALID = 0x00000003,
15706SC_TRPK_WINDOW_VALID = 0x00000004,
15707SC_SRPS_WINDOW_VALID_BUSY = 0x00000005,
15708SC_PSSW_WINDOW_VALID_BUSY = 0x00000006,
15709SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007,
15710SC_QZQP_WINDOW_VALID_BUSY = 0x00000008,
15711SC_TRPK_WINDOW_VALID_BUSY = 0x00000009,
15712SC_STARVED_BY_PA = 0x0000000a,
15713SC_STALLED_BY_PRIMFIFO = 0x0000000b,
15714SC_STALLED_BY_DB_TILE = 0x0000000c,
15715SC_STARVED_BY_DB_TILE = 0x0000000d,
15716SC_STALLED_BY_TILEORDERFIFO = 0x0000000e,
15717SC_STALLED_BY_TILEFIFO = 0x0000000f,
15718SC_STALLED_BY_DB_QUAD = 0x00000010,
15719SC_STARVED_BY_DB_QUAD = 0x00000011,
15720SC_STALLED_BY_QUADFIFO = 0x00000012,
15721SC_STALLED_BY_BCI = 0x00000013,
15722SC_STALLED_BY_SPI = 0x00000014,
15723SC_SCISSOR_DISCARD = 0x00000015,
15724SC_BB_DISCARD = 0x00000016,
15725SC_SUPERTILE_COUNT = 0x00000017,
15726SC_SUPERTILE_PER_PRIM_H0 = 0x00000018,
15727SC_SUPERTILE_PER_PRIM_H1 = 0x00000019,
15728SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a,
15729SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b,
15730SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c,
15731SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d,
15732SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e,
15733SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f,
15734SC_SUPERTILE_PER_PRIM_H8 = 0x00000020,
15735SC_SUPERTILE_PER_PRIM_H9 = 0x00000021,
15736SC_SUPERTILE_PER_PRIM_H10 = 0x00000022,
15737SC_SUPERTILE_PER_PRIM_H11 = 0x00000023,
15738SC_SUPERTILE_PER_PRIM_H12 = 0x00000024,
15739SC_SUPERTILE_PER_PRIM_H13 = 0x00000025,
15740SC_SUPERTILE_PER_PRIM_H14 = 0x00000026,
15741SC_SUPERTILE_PER_PRIM_H15 = 0x00000027,
15742SC_SUPERTILE_PER_PRIM_H16 = 0x00000028,
15743SC_TILE_PER_PRIM_H0 = 0x00000029,
15744SC_TILE_PER_PRIM_H1 = 0x0000002a,
15745SC_TILE_PER_PRIM_H2 = 0x0000002b,
15746SC_TILE_PER_PRIM_H3 = 0x0000002c,
15747SC_TILE_PER_PRIM_H4 = 0x0000002d,
15748SC_TILE_PER_PRIM_H5 = 0x0000002e,
15749SC_TILE_PER_PRIM_H6 = 0x0000002f,
15750SC_TILE_PER_PRIM_H7 = 0x00000030,
15751SC_TILE_PER_PRIM_H8 = 0x00000031,
15752SC_TILE_PER_PRIM_H9 = 0x00000032,
15753SC_TILE_PER_PRIM_H10 = 0x00000033,
15754SC_TILE_PER_PRIM_H11 = 0x00000034,
15755SC_TILE_PER_PRIM_H12 = 0x00000035,
15756SC_TILE_PER_PRIM_H13 = 0x00000036,
15757SC_TILE_PER_PRIM_H14 = 0x00000037,
15758SC_TILE_PER_PRIM_H15 = 0x00000038,
15759SC_TILE_PER_PRIM_H16 = 0x00000039,
15760SC_TILE_PER_SUPERTILE_H0 = 0x0000003a,
15761SC_TILE_PER_SUPERTILE_H1 = 0x0000003b,
15762SC_TILE_PER_SUPERTILE_H2 = 0x0000003c,
15763SC_TILE_PER_SUPERTILE_H3 = 0x0000003d,
15764SC_TILE_PER_SUPERTILE_H4 = 0x0000003e,
15765SC_TILE_PER_SUPERTILE_H5 = 0x0000003f,
15766SC_TILE_PER_SUPERTILE_H6 = 0x00000040,
15767SC_TILE_PER_SUPERTILE_H7 = 0x00000041,
15768SC_TILE_PER_SUPERTILE_H8 = 0x00000042,
15769SC_TILE_PER_SUPERTILE_H9 = 0x00000043,
15770SC_TILE_PER_SUPERTILE_H10 = 0x00000044,
15771SC_TILE_PER_SUPERTILE_H11 = 0x00000045,
15772SC_TILE_PER_SUPERTILE_H12 = 0x00000046,
15773SC_TILE_PER_SUPERTILE_H13 = 0x00000047,
15774SC_TILE_PER_SUPERTILE_H14 = 0x00000048,
15775SC_TILE_PER_SUPERTILE_H15 = 0x00000049,
15776SC_TILE_PER_SUPERTILE_H16 = 0x0000004a,
15777SC_TILE_PICKED_H1 = 0x0000004b,
15778SC_PERF_SEL_RESERVED_76 = 0x0000004c,
15779SC_PERF_SEL_RESERVED_77 = 0x0000004d,
15780SC_PERF_SEL_RESERVED_78 = 0x0000004e,
15781SC_QZ0_TILE_COUNT = 0x0000004f,
15782SC_PERF_SEL_RESERVED_80 = 0x00000050,
15783SC_PERF_SEL_RESERVED_81 = 0x00000051,
15784SC_PERF_SEL_RESERVED_82 = 0x00000052,
15785SC_QZ0_TILE_COVERED_COUNT = 0x00000053,
15786SC_PERF_SEL_RESERVED_84 = 0x00000054,
15787SC_PERF_SEL_RESERVED_85 = 0x00000055,
15788SC_PERF_SEL_RESERVED_86 = 0x00000056,
15789SC_QZ0_TILE_NOT_COVERED_COUNT = 0x00000057,
15790SC_PERF_SEL_RESERVED_88 = 0x00000058,
15791SC_PERF_SEL_RESERVED_89 = 0x00000059,
15792SC_PERF_SEL_RESERVED_90 = 0x0000005a,
15793SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005b,
15794SC_QZ0_QUAD_PER_TILE_H1 = 0x0000005c,
15795SC_QZ0_QUAD_PER_TILE_H2 = 0x0000005d,
15796SC_QZ0_QUAD_PER_TILE_H3 = 0x0000005e,
15797SC_QZ0_QUAD_PER_TILE_H4 = 0x0000005f,
15798SC_QZ0_QUAD_PER_TILE_H5 = 0x00000060,
15799SC_QZ0_QUAD_PER_TILE_H6 = 0x00000061,
15800SC_QZ0_QUAD_PER_TILE_H7 = 0x00000062,
15801SC_QZ0_QUAD_PER_TILE_H8 = 0x00000063,
15802SC_QZ0_QUAD_PER_TILE_H9 = 0x00000064,
15803SC_QZ0_QUAD_PER_TILE_H10 = 0x00000065,
15804SC_QZ0_QUAD_PER_TILE_H11 = 0x00000066,
15805SC_QZ0_QUAD_PER_TILE_H12 = 0x00000067,
15806SC_QZ0_QUAD_PER_TILE_H13 = 0x00000068,
15807SC_QZ0_QUAD_PER_TILE_H14 = 0x00000069,
15808SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006a,
15809SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006b,
15810SC_PERF_SEL_RESERVED_108 = 0x0000006c,
15811SC_PERF_SEL_RESERVED_109 = 0x0000006d,
15812SC_PERF_SEL_RESERVED_110 = 0x0000006e,
15813SC_PERF_SEL_RESERVED_111 = 0x0000006f,
15814SC_PERF_SEL_RESERVED_112 = 0x00000070,
15815SC_PERF_SEL_RESERVED_113 = 0x00000071,
15816SC_PERF_SEL_RESERVED_114 = 0x00000072,
15817SC_PERF_SEL_RESERVED_115 = 0x00000073,
15818SC_PERF_SEL_RESERVED_116 = 0x00000074,
15819SC_PERF_SEL_RESERVED_117 = 0x00000075,
15820SC_PERF_SEL_RESERVED_118 = 0x00000076,
15821SC_PERF_SEL_RESERVED_119 = 0x00000077,
15822SC_PERF_SEL_RESERVED_120 = 0x00000078,
15823SC_PERF_SEL_RESERVED_121 = 0x00000079,
15824SC_PERF_SEL_RESERVED_122 = 0x0000007a,
15825SC_PERF_SEL_RESERVED_123 = 0x0000007b,
15826SC_PERF_SEL_RESERVED_124 = 0x0000007c,
15827SC_PERF_SEL_RESERVED_125 = 0x0000007d,
15828SC_PERF_SEL_RESERVED_126 = 0x0000007e,
15829SC_PERF_SEL_RESERVED_127 = 0x0000007f,
15830SC_PERF_SEL_RESERVED_128 = 0x00000080,
15831SC_PERF_SEL_RESERVED_129 = 0x00000081,
15832SC_PERF_SEL_RESERVED_130 = 0x00000082,
15833SC_PERF_SEL_RESERVED_131 = 0x00000083,
15834SC_PERF_SEL_RESERVED_132 = 0x00000084,
15835SC_PERF_SEL_RESERVED_133 = 0x00000085,
15836SC_PERF_SEL_RESERVED_134 = 0x00000086,
15837SC_PERF_SEL_RESERVED_135 = 0x00000087,
15838SC_PERF_SEL_RESERVED_136 = 0x00000088,
15839SC_PERF_SEL_RESERVED_137 = 0x00000089,
15840SC_PERF_SEL_RESERVED_138 = 0x0000008a,
15841SC_PERF_SEL_RESERVED_139 = 0x0000008b,
15842SC_PERF_SEL_RESERVED_140 = 0x0000008c,
15843SC_PERF_SEL_RESERVED_141 = 0x0000008d,
15844SC_PERF_SEL_RESERVED_142 = 0x0000008e,
15845SC_PERF_SEL_RESERVED_143 = 0x0000008f,
15846SC_PERF_SEL_RESERVED_144 = 0x00000090,
15847SC_PERF_SEL_RESERVED_145 = 0x00000091,
15848SC_PERF_SEL_RESERVED_146 = 0x00000092,
15849SC_PERF_SEL_RESERVED_147 = 0x00000093,
15850SC_PERF_SEL_RESERVED_148 = 0x00000094,
15851SC_PERF_SEL_RESERVED_149 = 0x00000095,
15852SC_PERF_SEL_RESERVED_150 = 0x00000096,
15853SC_PERF_SEL_RESERVED_151 = 0x00000097,
15854SC_PERF_SEL_RESERVED_152 = 0x00000098,
15855SC_PERF_SEL_RESERVED_153 = 0x00000099,
15856SC_PERF_SEL_RESERVED_154 = 0x0000009a,
15857SC_PERF_SEL_RESERVED_155 = 0x0000009b,
15858SC_PERF_SEL_RESERVED_156 = 0x0000009c,
15859SC_PERF_SEL_RESERVED_157 = 0x0000009d,
15860SC_PERF_SEL_RESERVED_158 = 0x0000009e,
15861SC_QZ0_QUAD_COUNT = 0x0000009f,
15862SC_PERF_SEL_RESERVED_160 = 0x000000a0,
15863SC_PERF_SEL_RESERVED_161 = 0x000000a1,
15864SC_PERF_SEL_RESERVED_162 = 0x000000a2,
15865SC_P0_HIZ_TILE_COUNT = 0x000000a3,
15866SC_PERF_SEL_RESERVED_164 = 0x000000a4,
15867SC_PERF_SEL_RESERVED_165 = 0x000000a5,
15868SC_PERF_SEL_RESERVED_166 = 0x000000a6,
15869SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000a7,
15870SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000a8,
15871SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000a9,
15872SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000aa,
15873SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000ab,
15874SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000ac,
15875SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000ad,
15876SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000ae,
15877SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000af,
15878SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b0,
15879SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b1,
15880SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b2,
15881SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b3,
15882SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b4,
15883SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b5,
15884SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000b6,
15885SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000b7,
15886SC_PERF_SEL_RESERVED_184 = 0x000000b8,
15887SC_PERF_SEL_RESERVED_185 = 0x000000b9,
15888SC_PERF_SEL_RESERVED_186 = 0x000000ba,
15889SC_PERF_SEL_RESERVED_187 = 0x000000bb,
15890SC_PERF_SEL_RESERVED_188 = 0x000000bc,
15891SC_PERF_SEL_RESERVED_189 = 0x000000bd,
15892SC_PERF_SEL_RESERVED_190 = 0x000000be,
15893SC_PERF_SEL_RESERVED_191 = 0x000000bf,
15894SC_PERF_SEL_RESERVED_192 = 0x000000c0,
15895SC_PERF_SEL_RESERVED_193 = 0x000000c1,
15896SC_PERF_SEL_RESERVED_194 = 0x000000c2,
15897SC_PERF_SEL_RESERVED_195 = 0x000000c3,
15898SC_PERF_SEL_RESERVED_196 = 0x000000c4,
15899SC_PERF_SEL_RESERVED_197 = 0x000000c5,
15900SC_PERF_SEL_RESERVED_198 = 0x000000c6,
15901SC_PERF_SEL_RESERVED_199 = 0x000000c7,
15902SC_PERF_SEL_RESERVED_200 = 0x000000c8,
15903SC_PERF_SEL_RESERVED_201 = 0x000000c9,
15904SC_PERF_SEL_RESERVED_202 = 0x000000ca,
15905SC_PERF_SEL_RESERVED_203 = 0x000000cb,
15906SC_PERF_SEL_RESERVED_204 = 0x000000cc,
15907SC_PERF_SEL_RESERVED_205 = 0x000000cd,
15908SC_PERF_SEL_RESERVED_206 = 0x000000ce,
15909SC_PERF_SEL_RESERVED_207 = 0x000000cf,
15910SC_PERF_SEL_RESERVED_208 = 0x000000d0,
15911SC_PERF_SEL_RESERVED_209 = 0x000000d1,
15912SC_PERF_SEL_RESERVED_210 = 0x000000d2,
15913SC_PERF_SEL_RESERVED_211 = 0x000000d3,
15914SC_PERF_SEL_RESERVED_212 = 0x000000d4,
15915SC_PERF_SEL_RESERVED_213 = 0x000000d5,
15916SC_PERF_SEL_RESERVED_214 = 0x000000d6,
15917SC_PERF_SEL_RESERVED_215 = 0x000000d7,
15918SC_PERF_SEL_RESERVED_216 = 0x000000d8,
15919SC_PERF_SEL_RESERVED_217 = 0x000000d9,
15920SC_PERF_SEL_RESERVED_218 = 0x000000da,
15921SC_PERF_SEL_RESERVED_219 = 0x000000db,
15922SC_PERF_SEL_RESERVED_220 = 0x000000dc,
15923SC_PERF_SEL_RESERVED_221 = 0x000000dd,
15924SC_PERF_SEL_RESERVED_222 = 0x000000de,
15925SC_PERF_SEL_RESERVED_223 = 0x000000df,
15926SC_PERF_SEL_RESERVED_224 = 0x000000e0,
15927SC_PERF_SEL_RESERVED_225 = 0x000000e1,
15928SC_PERF_SEL_RESERVED_226 = 0x000000e2,
15929SC_PERF_SEL_RESERVED_227 = 0x000000e3,
15930SC_PERF_SEL_RESERVED_228 = 0x000000e4,
15931SC_PERF_SEL_RESERVED_229 = 0x000000e5,
15932SC_PERF_SEL_RESERVED_230 = 0x000000e6,
15933SC_PERF_SEL_RESERVED_231 = 0x000000e7,
15934SC_PERF_SEL_RESERVED_232 = 0x000000e8,
15935SC_PERF_SEL_RESERVED_233 = 0x000000e9,
15936SC_PERF_SEL_RESERVED_234 = 0x000000ea,
15937SC_P0_HIZ_QUAD_COUNT = 0x000000eb,
15938SC_PERF_SEL_RESERVED_236 = 0x000000ec,
15939SC_PERF_SEL_RESERVED_237 = 0x000000ed,
15940SC_PERF_SEL_RESERVED_238 = 0x000000ee,
15941SC_P0_DETAIL_QUAD_COUNT = 0x000000ef,
15942SC_PERF_SEL_RESERVED_240 = 0x000000f0,
15943SC_PERF_SEL_RESERVED_241 = 0x000000f1,
15944SC_PERF_SEL_RESERVED_242 = 0x000000f2,
15945SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f3,
15946SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f4,
15947SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f5,
15948SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000f6,
15949SC_PERF_SEL_RESERVED_247 = 0x000000f7,
15950SC_PERF_SEL_RESERVED_248 = 0x000000f8,
15951SC_PERF_SEL_RESERVED_249 = 0x000000f9,
15952SC_PERF_SEL_RESERVED_250 = 0x000000fa,
15953SC_PERF_SEL_RESERVED_251 = 0x000000fb,
15954SC_PERF_SEL_RESERVED_252 = 0x000000fc,
15955SC_PERF_SEL_RESERVED_253 = 0x000000fd,
15956SC_PERF_SEL_RESERVED_254 = 0x000000fe,
15957SC_PERF_SEL_RESERVED_255 = 0x000000ff,
15958SC_PERF_SEL_RESERVED_256 = 0x00000100,
15959SC_PERF_SEL_RESERVED_257 = 0x00000101,
15960SC_PERF_SEL_RESERVED_258 = 0x00000102,
15961SC_EARLYZ_QUAD_COUNT = 0x00000103,
15962SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000104,
15963SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000105,
15964SC_EARLYZ_QUAD_WITH_3_PIX = 0x00000106,
15965SC_EARLYZ_QUAD_WITH_4_PIX = 0x00000107,
15966SC_PKR_QUAD_PER_ROW_H1 = 0x00000108,
15967SC_PKR_QUAD_PER_ROW_H2 = 0x00000109,
15968SC_PKR_4X2_QUAD_SPLIT = 0x0000010a,
15969SC_PKR_4X2_FILL_QUAD = 0x0000010b,
15970SC_PKR_END_OF_VECTOR = 0x0000010c,
15971SC_PKR_CONTROL_XFER = 0x0000010d,
15972SC_PKR_DBHANG_FORCE_EOV = 0x0000010e,
15973SC_REG_SCLK_BUSY = 0x0000010f,
15974SC_GRP0_DYN_SCLK_BUSY = 0x00000110,
15975SC_GRP1_DYN_SCLK_BUSY = 0x00000111,
15976SC_GRP2_DYN_SCLK_BUSY = 0x00000112,
15977SC_GRP3_DYN_SCLK_BUSY = 0x00000113,
15978SC_GRP4_DYN_SCLK_BUSY = 0x00000114,
15979SC_PA0_SC_DATA_FIFO_RD = 0x00000115,
15980SC_PA0_SC_DATA_FIFO_WE = 0x00000116,
15981SC_PERF_SEL_RESERVED_279 = 0x00000117,
15982SC_PERF_SEL_RESERVED_280 = 0x00000118,
15983SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000119,
15984SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011a,
15985SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011b,
15986SC_PS_ARB_STALLED_FROM_BELOW = 0x0000011c,
15987SC_PS_ARB_STARVED_FROM_ABOVE = 0x0000011d,
15988SC_PS_ARB_SC_BUSY = 0x0000011e,
15989SC_PS_ARB_PA_SC_BUSY = 0x0000011f,
15990SC_PERF_SEL_RESERVED_288 = 0x00000120,
15991SC_PERF_SEL_RESERVED_289 = 0x00000121,
15992SC_PERF_SEL_RESERVED_290 = 0x00000122,
15993SC_PERF_SEL_RESERVED_291 = 0x00000123,
15994SC_PA_SC_DEALLOC_2_0_WE = 0x00000124,
15995SC_PERF_SEL_RESERVED_293 = 0x00000125,
15996SC_PERF_SEL_RESERVED_294 = 0x00000126,
15997SC_PERF_SEL_RESERVED_295 = 0x00000127,
15998SC_PERF_SEL_RESERVED_296 = 0x00000128,
15999SC_PERF_SEL_RESERVED_297 = 0x00000129,
16000SC_PERF_SEL_RESERVED_298 = 0x0000012a,
16001SC_PERF_SEL_RESERVED_299 = 0x0000012b,
16002SC_PA0_SC_EOP_WE = 0x0000012c,
16003SC_PERF_SEL_RESERVED_301 = 0x0000012d,
16004SC_PA0_SC_EVENT_WE = 0x0000012e,
16005SC_PERF_SEL_RESERVED_303 = 0x0000012f,
16006SC_PERF_SEL_RESERVED_304 = 0x00000130,
16007SC_PERF_SEL_RESERVED_305 = 0x00000131,
16008SC_PERF_SEL_RESERVED_306 = 0x00000132,
16009SC_PERF_SEL_RESERVED_307 = 0x00000133,
16010SC_PERF_SEL_RESERVED_308 = 0x00000134,
16011SC_PERF_SEL_RESERVED_309 = 0x00000135,
16012SC_PERF_SEL_RESERVED_310 = 0x00000136,
16013SC_PERF_SEL_RESERVED_311 = 0x00000137,
16014SC_PERF_SEL_RESERVED_312 = 0x00000138,
16015SC_PERF_SEL_RESERVED_313 = 0x00000139,
16016SC_PERF_SEL_RESERVED_314 = 0x0000013a,
16017SC_PERF_SEL_RESERVED_315 = 0x0000013b,
16018SC_PERF_SEL_RESERVED_316 = 0x0000013c,
16019SC_PERF_SEL_RESERVED_317 = 0x0000013d,
16020SC_PA_SC_FPOV_WE = 0x0000013e,
16021SC_PERF_SEL_RESERVED_319 = 0x0000013f,
16022SC_PERF_SEL_RESERVED_320 = 0x00000140,
16023SC_PERF_SEL_RESERVED_321 = 0x00000141,
16024SC_PERF_SEL_RESERVED_322 = 0x00000142,
16025SC_PERF_SEL_RESERVED_323 = 0x00000143,
16026SC_PERF_SEL_RESERVED_324 = 0x00000144,
16027SC_PERF_SEL_RESERVED_325 = 0x00000145,
16028SC_SPI_DEALLOC_4_0 = 0x00000146,
16029SC_SPI_DEALLOC_7_5 = 0x00000147,
16030SC_PERF_SEL_RESERVED_328 = 0x00000148,
16031SC_PERF_SEL_RESERVED_329 = 0x00000149,
16032SC_PERF_SEL_RESERVED_330 = 0x0000014a,
16033SC_PERF_SEL_RESERVED_331 = 0x0000014b,
16034SC_PERF_SEL_RESERVED_332 = 0x0000014c,
16035SC_PERF_SEL_RESERVED_333 = 0x0000014d,
16036SC_PERF_SEL_RESERVED_334 = 0x0000014e,
16037SC_PERF_SEL_RESERVED_335 = 0x0000014f,
16038SC_PERF_SEL_RESERVED_336 = 0x00000150,
16039SC_PERF_SEL_RESERVED_337 = 0x00000151,
16040SC_SPI_FPOV_4_0 = 0x00000152,
16041SC_SPI_FPOV_7_5 = 0x00000153,
16042SC_PERF_SEL_RESERVED_340 = 0x00000154,
16043SC_PERF_SEL_RESERVED_341 = 0x00000155,
16044SC_SPI_EVENT = 0x00000156,
16045SC_PS_TS_EVENT_FIFO_PUSH = 0x00000157,
16046SC_PS_TS_EVENT_FIFO_POP = 0x00000158,
16047SC_PS_CTX_DONE_FIFO_PUSH = 0x00000159,
16048SC_PS_CTX_DONE_FIFO_POP = 0x0000015a,
16049SC_PERF_SEL_RESERVED_347 = 0x0000015b,
16050SC_PERF_SEL_RESERVED_348 = 0x0000015c,
16051SC_PA0_SC_NULL_WE = 0x0000015d,
16052SC_PA0_SC_NULL_DEALLOC_WE = 0x0000015e,
16053SC_PERF_SEL_RESERVED_351 = 0x0000015f,
16054SC_PA0_SC_DATA_FIFO_EOP_RD = 0x00000160,
16055SC_PA0_SC_DEALLOC_2_0_RD = 0x00000161,
16056SC_PERF_SEL_RESERVED_354 = 0x00000162,
16057SC_PERF_SEL_RESERVED_355 = 0x00000163,
16058SC_PERF_SEL_RESERVED_356 = 0x00000164,
16059SC_PERF_SEL_RESERVED_357 = 0x00000165,
16060SC_PERF_SEL_RESERVED_358 = 0x00000166,
16061SC_PERF_SEL_RESERVED_359 = 0x00000167,
16062SC_PERF_SEL_RESERVED_360 = 0x00000168,
16063SC_PERF_SEL_RESERVED_361 = 0x00000169,
16064SC_PERF_SEL_RESERVED_362 = 0x0000016a,
16065SC_PERF_SEL_RESERVED_363 = 0x0000016b,
16066SC_PERF_SEL_RESERVED_364 = 0x0000016c,
16067SC_PERF_SEL_RESERVED_365 = 0x0000016d,
16068SC_PERF_SEL_RESERVED_366 = 0x0000016e,
16069SC_PERF_SEL_RESERVED_367 = 0x0000016f,
16070SC_PERF_SEL_RESERVED_368 = 0x00000170,
16071SC_PERF_SEL_RESERVED_369 = 0x00000171,
16072SC_PERF_SEL_RESERVED_370 = 0x00000172,
16073SC_PERF_SEL_RESERVED_371 = 0x00000173,
16074SC_PERF_SEL_RESERVED_372 = 0x00000174,
16075SC_PS_PA0_SC_FIFO_EMPTY = 0x00000175,
16076SC_PS_PA0_SC_FIFO_FULL = 0x00000176,
16077SC_PERF_SEL_RESERVED_375 = 0x00000177,
16078SC_PERF_SEL_RESERVED_376 = 0x00000178,
16079SC_PERF_SEL_RESERVED_377 = 0x00000179,
16080SC_PERF_SEL_RESERVED_378 = 0x0000017a,
16081SC_PERF_SEL_RESERVED_379 = 0x0000017b,
16082SC_PERF_SEL_RESERVED_380 = 0x0000017c,
16083SC_PERF_SEL_RESERVED_381 = 0x0000017d,
16084SC_PERF_SEL_RESERVED_382 = 0x0000017e,
16085SC_PERF_SEL_RESERVED_383 = 0x0000017f,
16086SC_PERF_SEL_RESERVED_384 = 0x00000180,
16087SC_PERF_SEL_RESERVED_385 = 0x00000181,
16088SC_BUSY_CNT_NOT_ZERO = 0x00000182,
16089SC_BM_BUSY = 0x00000183,
16090SC_BACKEND_BUSY = 0x00000184,
16091SC_SCF_SCB_INTERFACE_BUSY = 0x00000185,
16092SC_SCB_BUSY = 0x00000186,
16093SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x00000187,
16094SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x00000188,
16095SC_PBB_BIN_HIST_NUM_PRIMS = 0x00000189,
16096SC_PBB_BATCH_HIST_NUM_PRIMS = 0x0000018a,
16097SC_PBB_BIN_HIST_NUM_CONTEXTS = 0x0000018b,
16098SC_PBB_BATCH_HIST_NUM_CONTEXTS = 0x0000018c,
16099SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 0x0000018d,
16100SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 0x0000018e,
16101SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 0x0000018f,
16102SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000190,
16103SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 0x00000191,
16104SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 0x00000192,
16105SC_PBB_BUSY = 0x00000193,
16106SC_PBB_BUSY_AND_NO_SENDS = 0x00000194,
16107SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 0x00000195,
16108SC_PBB_NUM_BINS = 0x00000196,
16109SC_PBB_END_OF_BIN = 0x00000197,
16110SC_PBB_END_OF_BATCH = 0x00000198,
16111SC_PBB_PRIMBIN_PROCESSED = 0x00000199,
16112SC_PBB_PRIM_ADDED_TO_BATCH = 0x0000019a,
16113SC_PBB_NONBINNED_PRIM = 0x0000019b,
16114SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 0x0000019c,
16115SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 0x0000019d,
16116SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x0000019e,
16117SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x0000019f,
16118SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a0,
16119SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a1,
16120SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 0x000001a2,
16121SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 0x000001a3,
16122SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 0x000001a4,
16123SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 0x000001a5,
16124SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 0x000001a6,
16125SC_PERF_SEL_RESERVED_423 = 0x000001a7,
16126SC_PERF_SEL_RESERVED_424 = 0x000001a8,
16127SC_PERF_SEL_RESERVED_425 = 0x000001a9,
16128SC_PERF_SEL_RESERVED_426 = 0x000001aa,
16129SC_PERF_SEL_RESERVED_427 = 0x000001ab,
16130SC_PERF_SEL_RESERVED_428 = 0x000001ac,
16131SC_PERF_SEL_RESERVED_429 = 0x000001ad,
16132SC_PERF_SEL_RESERVED_430 = 0x000001ae,
16133SC_PERF_SEL_RESERVED_431 = 0x000001af,
16134SC_PERF_SEL_RESERVED_432 = 0x000001b0,
16135SC_PERF_SEL_RESERVED_433 = 0x000001b1,
16136SC_PERF_SEL_RESERVED_434 = 0x000001b2,
16137SC_PERF_SEL_RESERVED_435 = 0x000001b3,
16138SC_PERF_SEL_RESERVED_436 = 0x000001b4,
16139SC_GRP5_DYN_SCLK_BUSY = 0x000001b5,
16140SC_GRP6_DYN_SCLK_BUSY = 0x000001b6,
16141SC_GRP7_DYN_SCLK_BUSY = 0x000001b7,
16142SC_GRP8_DYN_SCLK_BUSY = 0x000001b8,
16143SC_GRP9_DYN_SCLK_BUSY = 0x000001b9,
16144SC_PS_TO_BE_SCLK_GATE_STALL = 0x000001ba,
16145SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 0x000001bb,
16146SC_PK_BUSY = 0x000001bc,
16147SC_PK_MAX_DEALLOC_FORCE_EOV = 0x000001bd,
16148SC_PK_DEALLOC_WAVE_BREAK = 0x000001be,
16149SC_SPI_SEND = 0x000001bf,
16150SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c0,
16151SC_SPI_CREDIT_AT_MAX = 0x000001c1,
16152SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c2,
16153SC_BCI_SEND = 0x000001c3,
16154SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c4,
16155SC_BCI_CREDIT_AT_MAX = 0x000001c5,
16156SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c6,
16157SC_SPIBC_FULL_FREEZE = 0x000001c7,
16158SC_PW_BM_PASS_EMPTY_PRIM = 0x000001c8,
16159SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 0x000001c9,
16160SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 0x000001ca,
16161SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 0x000001cb,
16162SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 0x000001cc,
16163SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 0x000001cd,
16164SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 0x000001ce,
16165SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 0x000001cf,
16166SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 0x000001d0,
16167SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 0x000001d1,
16168SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 0x000001d2,
16169SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 0x000001d3,
16170SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 0x000001d4,
16171SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 0x000001d5,
16172SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 0x000001d6,
16173SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 0x000001d7,
16174SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 0x000001d8,
16175SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 0x000001d9,
16176SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 0x000001da,
16177SC_DB0_TILE_INTERFACE_BUSY = 0x000001db,
16178SC_DB0_TILE_INTERFACE_SEND = 0x000001dc,
16179SC_DB0_TILE_INTERFACE_SEND_EVENT = 0x000001dd,
16180SC_PERF_SEL_RESERVED_478 = 0x000001de,
16181SC_PERF_SEL_RESERVED_479 = 0x000001df,
16182SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e0,
16183SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e1,
16184SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001e2,
16185SC_PERF_SEL_RESERVED_483 = 0x000001e3,
16186SC_PERF_SEL_RESERVED_484 = 0x000001e4,
16187SC_PERF_SEL_RESERVED_485 = 0x000001e5,
16188SC_PERF_SEL_RESERVED_486 = 0x000001e6,
16189SC_PERF_SEL_RESERVED_487 = 0x000001e7,
16190SC_PERF_SEL_RESERVED_488 = 0x000001e8,
16191SC_PERF_SEL_RESERVED_489 = 0x000001e9,
16192SC_PERF_SEL_RESERVED_490 = 0x000001ea,
16193SC_BACKEND_PRIM_FIFO_FULL = 0x000001eb,
16194SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 0x000001ec,
16195SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 0x000001ed,
16196SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 0x000001ee,
16197SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 0x000001ef,
16198SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 0x000001f0,
16199SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 0x000001f1,
16200SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 0x000001f2,
16201SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 0x000001f3,
16202SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 0x000001f4,
16203SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 0x000001f5,
16204SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 0x000001f6,
16205SC_STALLED_BY_DB0_TILEFIFO = 0x000001f7,
16206SC_DB0_QUAD_INTF_SEND = 0x000001f8,
16207SC_DB0_QUAD_INTF_BUSY = 0x000001f9,
16208SC_DB0_QUAD_INTF_STALLED_BY_DB = 0x000001fa,
16209SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 0x000001fb,
16210SC_DB0_QUAD_INTF_IDLE = 0x000001fc,
16211SC_PERF_SEL_RESERVED_509 = 0x000001fd,
16212SC_PERF_SEL_RESERVED_510 = 0x000001fe,
16213SC_PERF_SEL_RESERVED_511 = 0x000001ff,
16214SC_PERF_SEL_RESERVED_512 = 0x00000200,
16215SC_PERF_SEL_RESERVED_513 = 0x00000201,
16216SC_PERF_SEL_RESERVED_514 = 0x00000202,
16217SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 0x00000203,
16218SC_PKR_WAVE_BREAK_FULL_TILE = 0x00000204,
16219SC_RESERVED_60 = 0x00000205,
16220SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 0x00000206,
16221SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 0x00000207,
16222SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 0x00000208,
16223SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 0x00000209,
16224SC_DB0_TILE_MASK_FIFO_FULL = 0x0000020a,
16225SC_PERF_SEL_RESERVED_523 = 0x0000020b,
16226SC_PERF_SEL_RESERVED_524 = 0x0000020c,
16227SC_PERF_SEL_RESERVED_525 = 0x0000020d,
16228SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 0x0000020e,
16229SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 0x0000020f,
16230SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 0x00000210,
16231SC_PS_PM_PFF_PW_FULL = 0x00000211,
16232SC_PS_PM_ZFF_PW_FULL = 0x00000212,
16233SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 0x00000213,
16234SC_PERF_SEL_RESERVED_532 = 0x00000214,
16235SC_PERF_SEL_RESERVED_533 = 0x00000215,
16236SC_PERF_SEL_RESERVED_534 = 0x00000216,
16237SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 0x00000217,
16238SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 0x00000218,
16239SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 0x00000219,
16240SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 0x0000021a,
16241SC_PERF_SEL_RESERVED_539 = 0x0000021b,
16242SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 0x0000021c,
16243SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 0x0000021d,
16244SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 0x0000021e,
16245SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 0x0000021f,
16246SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 0x00000220,
16247SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 0x00000221,
16248SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 0x00000222,
16249SC_PK_PM_OREO_CONFLICT_QUAD_FORCE_EOV_WAVE_BRK_1H = 0x00000223,
16250SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 0x00000224,
16251SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 0x00000225,
16252SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 0x00000226,
16253SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 0x00000227,
16254SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 0x00000228,
16255SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 0x00000229,
16256SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 0x0000022a,
16257SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 0x0000022b,
16258SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 0x0000022c,
16259SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 0x0000022d,
16260SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 0x0000022e,
16261SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 0x0000022f,
16262SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 0x00000230,
16263SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 0x00000231,
16264SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 0x00000232,
16265SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 0x00000233,
16266SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 0x00000234,
16267SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 0x00000235,
16268SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 0x00000236,
16269SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 0x00000237,
16270SC_PERF_SEL_RESERVED_568 = 0x00000238,
16271SC_PBB_RESERVED = 0x00000239,
16272SC_BM_BE0_STALLED = 0x0000023a,
16273SC_BM_BE1_STALLED = 0x0000023b,
16274SC_BM_BE2_STALLED = 0x0000023c,
16275SC_BM_BE3_STALLED = 0x0000023d,
16276SC_BM_MULTI_ACCUM_1_BE_STALLED = 0x0000023e,
16277SC_BM_MULTI_ACCUM_2_BE_STALLED = 0x0000023f,
16278SC_BM_MULTI_ACCUM_3_BE_STALLED = 0x00000240,
16279SC_BM_MULTI_ACCUM_4_BE_STALLED = 0x00000241,
16280SC_PBB_READ_PH0 = 0x00000242,
16281SC_PBB_READ_DEALLOC_4_0 = 0x00000243,
16282SC_PBB_READ_DEALLOC_7_5 = 0x00000244,
16283SC_PBB_READ_FPOG_4_0 = 0x00000245,
16284SC_PBB_READ_FPOG_7_5 = 0x00000246,
16285SC_VRC_SECTOR_HIT = 0x00000247,
16286SC_VRC_TAG_MISS = 0x00000248,
16287SC_VRC_SECTOR_MISS = 0x00000249,
16288SC_VRC_LRU_EVICT_STALL = 0x0000024a,
16289SC_VRC_LRU_EVICT_SCHEDULED_EVICT_STALL = 0x0000024b,
16290SC_VRC_LRU_EVICT_PENDING_EVICT_STALL = 0x0000024c,
16291SC_VRC_REEVICTION_STALL = 0x0000024d,
16292SC_VRC_EVICT_NONZERO_INFLIGHT_STALL = 0x0000024e,
16293SC_VRC_REPLACE_SCHEDULED_EVICT_STALL = 0x0000024f,
16294SC_VRC_REPLACE_PENDING_EVICT_STALL = 0x00000250,
16295SC_VRC_REPLACE_FLUSH_IN_PROGRESS_STALL = 0x00000251,
16296SC_VRC_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000252,
16297SC_VRC_READ_OUTPUT_STALL = 0x00000253,
16298SC_VRC_WRITE_OUTPUT_STALL = 0x00000254,
16299SC_VRC_ACK_OUTPUT_STALL = 0x00000255,
16300SC_VRC_FLUSH_EVICT_STALL = 0x00000256,
16301SC_VRC_FLUSH_REFLUSH_STALL = 0x00000257,
16302SC_VRC_FLUSH_FIP_HIT_STALL = 0x00000258,
16303SC_VRC_FLUSH_WRREQ_DRAIN_STALL = 0x00000259,
16304SC_VRC_FLUSH_DONE_STALL = 0x0000025a,
16305SC_VRC_FLUSH_STALL = 0x0000025b,
16306SC_VRC_STALL = 0x0000025c,
16307SC_VRC_FLUSH = 0x0000025d,
16308SC_VRC_SECTORS_FLUSHED = 0x0000025e,
16309SC_VRC_DIRTY_SECTORS_FLUSHED = 0x0000025f,
16310SC_VRC_TAGS_FLUSHED = 0x00000260,
16311SC_VRC_HPF_REQ = 0x00000261,
16312SC_VRC_HPF_EVENT = 0x00000262,
16313SC_VRC_HPF_STALLED = 0x00000263,
16314SC_VRC_PROBE_ACK_TILES = 0x00000264,
16315SC_VRC_GL1X_RD_REQ = 0x00000265,
16316SC_VRC_GL1X_WR_REQ = 0x00000266,
16317SC_VRC_GL1X_SRC_XFR = 0x00000267,
16318SC_VRC_GL1X_RD_RET = 0x00000268,
16319SC_VRC_GL1X_WR_ACK = 0x00000269,
16320SC_VRC_GL1X_RD_XNACK = 0x0000026a,
16321SC_VRC_GL1X_WR_XNACK = 0x0000026b,
16322SC_VRC_GL1X_REQ_STALLED = 0x0000026c,
16323SC_VRC_GL1X_SRC_STALLED = 0x0000026d,
16324SC_VRC_RATEMEM_WE_CNT = 0x0000026e,
16325SC_VRC_RATEMEM_RE_CNT = 0x0000026f,
16326SC_VRC_HINTMEM_WE_CNT = 0x00000270,
16327SC_VRC_HINTMEM_RE_CNT = 0x00000271,
16328SC_VRC_BUSY = 0x00000272,
16329SC_GL1X_BUSY = 0x00000273,
16330SC_BE_VRS_RD_REQ = 0x00000274,
16331SC_BE_VRS_RD_REQ_STALLED = 0x00000275,
16332SC_BE_VRS_RD_REQ_HIT = 0x00000276,
16333SC_BE_VRS_RD_RET = 0x00000277,
16334SC_BE_VRS_RD_RET_STALLED = 0x00000278,
16335SC_BE_VRS_FB_RET = 0x00000279,
16336SC_BE_VRS_FB_RET_STALLED = 0x0000027a,
16337SC_BE_VRS_FB_RET_HIT = 0x0000027b,
16338SC_VRS_BE_BUSY = 0x0000027c,
16339SC_PWS_CS_EVENTS_PWS_ENABLE = 0x0000027d,
16340SC_PWS_PS_EVENTS_PWS_ENABLE = 0x0000027e,
16341SC_PWS_TS_EVENTS_PWS_ENABLE = 0x0000027f,
16342SC_PWS_STALLED = 0x00000280,
16343SC_PWS_P0_CS_SYNC_COMPLETE = 0x00000281,
16344SC_PWS_P0_PS_SYNC_COMPLETE = 0x00000282,
16345SC_PWS_P0_TS_SYNC_COMPLETE = 0x00000283,
16346SC_PWS_P1_CS_SYNC_COMPLETE = 0x00000284,
16347SC_PWS_P1_PS_SYNC_COMPLETE = 0x00000285,
16348SC_PWS_P1_TS_SYNC_COMPLETE = 0x00000286,
16349SC_PKR_PC_NO_CREDITS = 0x00000287,
16350SC_PKR_PC_STALLED = 0x00000288,
16351SC_PKR_PC_SEND = 0x00000289,
16352SC_PKR_PC_SEND_PRIM_VALID_1 = 0x0000028a,
16353SC_PKR_PC_SEND_PRIM_VALID_0 = 0x0000028b,
16354SC_PKR_PC_SEND_TRUE_PRIM = 0x0000028c,
16355SC_PKR_PC_SEND_EOV = 0x0000028d,
16356SC_PKR_PC_SEND_EVENT = 0x0000028e,
16357SC_PKR_DB_WAVE_STALL = 0x0000028f,
16358SC_PKR_PSINVOC_SEDC_FIFO_FULL = 0x00000290,
16359SC_PKR_OREO_STALLED_BY_NO_VALID_WAIVE_ID = 0x00000291,
16360SC_PKR_SPI_QUAD_COUNT = 0x00000292,
16361SC_PKR_DB_OREO_WAVE_QUAD_COUNT = 0x00000293,
16362SC_PKR_BCI_QUAD_NEW_PRIM = 0x00000294,
16363SC_SPI_WAVE_STALLED_BY_SPI = 0x00000295,
16364} SC_PERFCNT_SEL;
16365
16366/*
16367 * ScMap enum
16368 */
16369
16370typedef enum ScMap {
16371RASTER_CONFIG_SC_MAP_0 = 0x00000000,
16372RASTER_CONFIG_SC_MAP_1 = 0x00000001,
16373RASTER_CONFIG_SC_MAP_2 = 0x00000002,
16374RASTER_CONFIG_SC_MAP_3 = 0x00000003,
16375} ScMap;
16376
16377/*
16378 * ScUncertaintyRegionMode enum
16379 */
16380
16381typedef enum ScUncertaintyRegionMode {
16382SC_HALF_LSB = 0x00000000,
16383SC_LSB_ONE_SIDED = 0x00000001,
16384SC_LSB_TWO_SIDED = 0x00000002,
16385} ScUncertaintyRegionMode;
16386
16387/*
16388 * ScUncertaintyRegionMult enum
16389 */
16390
16391typedef enum ScUncertaintyRegionMult {
16392SC_UR_1X = 0x00000000,
16393SC_UR_2X = 0x00000001,
16394SC_UR_4X = 0x00000002,
16395SC_UR_8X = 0x00000003,
16396} ScUncertaintyRegionMult;
16397
16398/*
16399 * ScXsel enum
16400 */
16401
16402typedef enum ScXsel {
16403RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000,
16404RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001,
16405RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002,
16406RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003,
16407} ScXsel;
16408
16409/*
16410 * ScYsel enum
16411 */
16412
16413typedef enum ScYsel {
16414RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000,
16415RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001,
16416RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002,
16417RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003,
16418} ScYsel;
16419
16420/*
16421 * SeMap enum
16422 */
16423
16424typedef enum SeMap {
16425RASTER_CONFIG_SE_MAP_0 = 0x00000000,
16426RASTER_CONFIG_SE_MAP_1 = 0x00000001,
16427RASTER_CONFIG_SE_MAP_2 = 0x00000002,
16428RASTER_CONFIG_SE_MAP_3 = 0x00000003,
16429} SeMap;
16430
16431/*
16432 * SePairMap enum
16433 */
16434
16435typedef enum SePairMap {
16436RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000,
16437RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001,
16438RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002,
16439RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003,
16440} SePairMap;
16441
16442/*
16443 * SePairXsel enum
16444 */
16445
16446typedef enum SePairXsel {
16447RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000,
16448RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001,
16449RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002,
16450RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003,
16451} SePairXsel;
16452
16453/*
16454 * SePairYsel enum
16455 */
16456
16457typedef enum SePairYsel {
16458RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000,
16459RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001,
16460RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002,
16461RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003,
16462} SePairYsel;
16463
16464/*
16465 * SeXsel enum
16466 */
16467
16468typedef enum SeXsel {
16469RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000,
16470RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001,
16471RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002,
16472RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003,
16473} SeXsel;
16474
16475/*
16476 * SeYsel enum
16477 */
16478
16479typedef enum SeYsel {
16480RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000,
16481RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001,
16482RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002,
16483RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003,
16484} SeYsel;
16485
16486/*
16487 * VRSCombinerModeSC enum
16488 */
16489
16490typedef enum VRSCombinerModeSC {
16491SC_VRS_COMB_MODE_PASSTHRU = 0x00000000,
16492SC_VRS_COMB_MODE_OVERRIDE = 0x00000001,
16493SC_VRS_COMB_MODE_MIN = 0x00000002,
16494SC_VRS_COMB_MODE_MAX = 0x00000003,
16495SC_VRS_COMB_MODE_SATURATE = 0x00000004,
16496} VRSCombinerModeSC;
16497
16498/*
16499 * VRSrate enum
16500 */
16501
16502typedef enum VRSrate {
16503VRS_SHADING_RATE_1X1 = 0x00000000,
16504VRS_SHADING_RATE_1X2 = 0x00000001,
16505VRS_SHADING_RATE_UNDEFINED0 = 0x00000002,
16506VRS_SHADING_RATE_UNDEFINED1 = 0x00000003,
16507VRS_SHADING_RATE_2X1 = 0x00000004,
16508VRS_SHADING_RATE_2X2 = 0x00000005,
16509VRS_SHADING_RATE_2X4 = 0x00000006,
16510VRS_SHADING_RATE_UNDEFINED2 = 0x00000007,
16511VRS_SHADING_RATE_UNDEFINED3 = 0x00000008,
16512VRS_SHADING_RATE_4X2 = 0x00000009,
16513VRS_SHADING_RATE_4X4 = 0x0000000a,
16514VRS_SHADING_RATE_UNDEFINED4 = 0x0000000b,
16515VRS_SHADING_RATE_16X_SSAA = 0x0000000c,
16516VRS_SHADING_RATE_8X_SSAA = 0x0000000d,
16517VRS_SHADING_RATE_4X_SSAA = 0x0000000e,
16518VRS_SHADING_RATE_2X_SSAA = 0x0000000f,
16519} VRSrate;
16520
16521/*******************************************************
16522 * TC Enums
16523 *******************************************************/
16524
16525/*
16526 * TC_EA_CID enum
16527 */
16528
16529typedef enum TC_EA_CID {
16530TC_EA_CID_RT = 0x00000000,
16531TC_EA_CID_FMASK = 0x00000001,
16532TC_EA_CID_DCC = 0x00000002,
16533TC_EA_CID_TCPMETA = 0x00000003,
16534TC_EA_CID_Z = 0x00000004,
16535TC_EA_CID_STENCIL = 0x00000005,
16536TC_EA_CID_HTILE = 0x00000006,
16537TC_EA_CID_MISC = 0x00000007,
16538TC_EA_CID_TCP = 0x00000008,
16539TC_EA_CID_SQC = 0x00000009,
16540TC_EA_CID_CPF = 0x0000000a,
16541TC_EA_CID_CPG = 0x0000000b,
16542TC_EA_CID_IA = 0x0000000c,
16543TC_EA_CID_WD = 0x0000000d,
16544TC_EA_CID_PA = 0x0000000e,
16545TC_EA_CID_UTCL2_TPI = 0x0000000f,
16546} TC_EA_CID;
16547
16548/*
16549 * TC_NACKS enum
16550 */
16551
16552typedef enum TC_NACKS {
16553TC_NACK_NO_FAULT = 0x00000000,
16554TC_NACK_PAGE_FAULT = 0x00000001,
16555TC_NACK_PROTECTION_FAULT = 0x00000002,
16556TC_NACK_DATA_ERROR = 0x00000003,
16557} TC_NACKS;
16558
16559/*
16560 * TC_OP enum
16561 */
16562
16563typedef enum TC_OP {
16564TC_OP_READ = 0x00000000,
16565TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001,
16566TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002,
16567TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003,
16568TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004,
16569TC_OP_RESERVED_FADD_RTN_32 = 0x00000005,
16570TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006,
16571TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007,
16572TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008,
16573TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
16574TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a,
16575TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b,
16576TC_OP_PROBE_FILTER = 0x0000000c,
16577TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 0x0000000d,
16578TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
16579TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f,
16580TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010,
16581TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011,
16582TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012,
16583TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013,
16584TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014,
16585TC_OP_ATOMIC_AND_RTN_32 = 0x00000015,
16586TC_OP_ATOMIC_OR_RTN_32 = 0x00000016,
16587TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017,
16588TC_OP_ATOMIC_INC_RTN_32 = 0x00000018,
16589TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019,
16590TC_OP_WBINVL1_VOL = 0x0000001a,
16591TC_OP_WBINVL1_SD = 0x0000001b,
16592TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c,
16593TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d,
16594TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e,
16595TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f,
16596TC_OP_WRITE = 0x00000020,
16597TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021,
16598TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022,
16599TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023,
16600TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024,
16601TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025,
16602TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026,
16603TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027,
16604TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028,
16605TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
16606TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a,
16607TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b,
16608TC_OP_WBINVL2_SD = 0x0000002c,
16609TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d,
16610TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e,
16611TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f,
16612TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030,
16613TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031,
16614TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032,
16615TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033,
16616TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034,
16617TC_OP_ATOMIC_AND_RTN_64 = 0x00000035,
16618TC_OP_ATOMIC_OR_RTN_64 = 0x00000036,
16619TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037,
16620TC_OP_ATOMIC_INC_RTN_64 = 0x00000038,
16621TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039,
16622TC_OP_WBL2_NC = 0x0000003a,
16623TC_OP_WBL2_WC = 0x0000003b,
16624TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c,
16625TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d,
16626TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e,
16627TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f,
16628TC_OP_WBINVL1 = 0x00000040,
16629TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041,
16630TC_OP_ATOMIC_FMIN_32 = 0x00000042,
16631TC_OP_ATOMIC_FMAX_32 = 0x00000043,
16632TC_OP_RESERVED_FOP_32_0 = 0x00000044,
16633TC_OP_RESERVED_FADD_32 = 0x00000045,
16634TC_OP_RESERVED_FOP_32_2 = 0x00000046,
16635TC_OP_ATOMIC_SWAP_32 = 0x00000047,
16636TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048,
16637TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049,
16638TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a,
16639TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b,
16640TC_OP_INV_METADATA = 0x0000004c,
16641TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 0x0000004d,
16642TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e,
16643TC_OP_ATOMIC_ADD_32 = 0x0000004f,
16644TC_OP_ATOMIC_SUB_32 = 0x00000050,
16645TC_OP_ATOMIC_SMIN_32 = 0x00000051,
16646TC_OP_ATOMIC_UMIN_32 = 0x00000052,
16647TC_OP_ATOMIC_SMAX_32 = 0x00000053,
16648TC_OP_ATOMIC_UMAX_32 = 0x00000054,
16649TC_OP_ATOMIC_AND_32 = 0x00000055,
16650TC_OP_ATOMIC_OR_32 = 0x00000056,
16651TC_OP_ATOMIC_XOR_32 = 0x00000057,
16652TC_OP_ATOMIC_INC_32 = 0x00000058,
16653TC_OP_ATOMIC_DEC_32 = 0x00000059,
16654TC_OP_INVL2_NC = 0x0000005a,
16655TC_OP_NOP_RTN0 = 0x0000005b,
16656TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c,
16657TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d,
16658TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e,
16659TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f,
16660TC_OP_WBINVL2 = 0x00000060,
16661TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061,
16662TC_OP_ATOMIC_FMIN_64 = 0x00000062,
16663TC_OP_ATOMIC_FMAX_64 = 0x00000063,
16664TC_OP_RESERVED_FOP_64_0 = 0x00000064,
16665TC_OP_RESERVED_FOP_64_1 = 0x00000065,
16666TC_OP_RESERVED_FOP_64_2 = 0x00000066,
16667TC_OP_ATOMIC_SWAP_64 = 0x00000067,
16668TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068,
16669TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069,
16670TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a,
16671TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b,
16672TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c,
16673TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d,
16674TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e,
16675TC_OP_ATOMIC_ADD_64 = 0x0000006f,
16676TC_OP_ATOMIC_SUB_64 = 0x00000070,
16677TC_OP_ATOMIC_SMIN_64 = 0x00000071,
16678TC_OP_ATOMIC_UMIN_64 = 0x00000072,
16679TC_OP_ATOMIC_SMAX_64 = 0x00000073,
16680TC_OP_ATOMIC_UMAX_64 = 0x00000074,
16681TC_OP_ATOMIC_AND_64 = 0x00000075,
16682TC_OP_ATOMIC_OR_64 = 0x00000076,
16683TC_OP_ATOMIC_XOR_64 = 0x00000077,
16684TC_OP_ATOMIC_INC_64 = 0x00000078,
16685TC_OP_ATOMIC_DEC_64 = 0x00000079,
16686TC_OP_WBINVL2_NC = 0x0000007a,
16687TC_OP_NOP_ACK = 0x0000007b,
16688TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c,
16689TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d,
16690TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e,
16691TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f,
16692} TC_OP;
16693
16694/*
16695 * TC_OP_MASKS enum
16696 */
16697
16698typedef enum TC_OP_MASKS {
16699TC_OP_MASK_FLUSH_DENROM = 0x00000008,
16700TC_OP_MASK_64 = 0x00000020,
16701TC_OP_MASK_NO_RTN = 0x00000040,
16702} TC_OP_MASKS;
16703
16704/*******************************************************
16705 * SPI Enums
16706 *******************************************************/
16707
16708/*
16709 * CLKGATE_BASE_MODE enum
16710 */
16711
16712typedef enum CLKGATE_BASE_MODE {
16713MULT_8 = 0x00000000,
16714MULT_16 = 0x00000001,
16715} CLKGATE_BASE_MODE;
16716
16717/*
16718 * CLKGATE_SM_MODE enum
16719 */
16720
16721typedef enum CLKGATE_SM_MODE {
16722ON_SEQ = 0x00000000,
16723OFF_SEQ = 0x00000001,
16724PROG_SEQ = 0x00000002,
16725READ_SEQ = 0x00000003,
16726SM_MODE_RESERVED = 0x00000004,
16727} CLKGATE_SM_MODE;
16728
16729/*
16730 * CovToShaderSel enum
16731 */
16732
16733typedef enum CovToShaderSel {
16734INPUT_COVERAGE = 0x00000000,
16735INPUT_INNER_COVERAGE = 0x00000001,
16736INPUT_DEPTH_COVERAGE = 0x00000002,
16737RAW = 0x00000003,
16738} CovToShaderSel;
16739
16740/*
16741 * PC_PERFCNT_SEL enum
16742 */
16743
16744typedef enum PC_PERFCNT_SEL {
16745PC_PERF_SC_PC_PTR_SEND0 = 0x00000000,
16746PC_PERF_SC_PC_PTR_VALID0 = 0x00000001,
16747PC_PERF_SC_FPOSG0 = 0x00000002,
16748PC_PERF_SC_FPOSG_WAIT0 = 0x00000003,
16749PC_PERF_SC_WAIT_SYNC0 = 0x00000004,
16750PC_PERF_SC_PQ_FREEZE0 = 0x00000005,
16751PC_PERF_PKR0_FPOSG_EQ1 = 0x00000006,
16752PC_PERF_PKR0_FPOSG_GT1 = 0x00000007,
16753PC_PERF_PKR0_FPOSG_GT16 = 0x00000008,
16754PC_PERF_PKR0_FPOSG_GT64 = 0x00000009,
16755PC_PERF_PKR0_FPOSG_GT128 = 0x0000000a,
16756PC_PERF_PKR0_FPOSG_OUT_OF_WAVE = 0x0000000b,
16757PC_PERF_PKR0_NUM_PROBES = 0x0000000c,
16758PC_PERF_PKR0_PRIMS_PER_PROBE_EQ1 = 0x0000000d,
16759PC_PERF_PKR0_PRIMS_PER_PROBE_GT1 = 0x0000000e,
16760PC_PERF_PKR0_PRIMS_PER_PROBE_GT2 = 0x0000000f,
16761PC_PERF_PKR0_PRIMS_PER_PROBE_GT4 = 0x00000010,
16762PC_PERF_PKR0_PRIMS_PER_PROBE_GT8 = 0x00000011,
16763PC_PERF_PKR0_NUM_WAVES = 0x00000012,
16764PC_PERF_PKR0_PRIMS_PER_WAVE_EQ1 = 0x00000013,
16765PC_PERF_PKR0_PRIMS_PER_WAVE_GT1 = 0x00000014,
16766PC_PERF_PKR0_PRIMS_PER_WAVE_GT2 = 0x00000015,
16767PC_PERF_PKR0_PRIMS_PER_WAVE_GT4 = 0x00000016,
16768PC_PERF_PKR0_PRIMS_PER_WAVE_GT8 = 0x00000017,
16769PC_PERF_PKR0_PROBES_PER_WAVE_EQ1 = 0x00000018,
16770PC_PERF_PKR0_PROBES_PER_WAVE_GT1 = 0x00000019,
16771PC_PERF_PKR0_PROBES_PER_WAVE_GT2 = 0x0000001a,
16772PC_PERF_PKR0_PROBES_PER_WAVE_GT4 = 0x0000001b,
16773PC_PERF_PKR0_PROBES_PER_WAVE_GT8 = 0x0000001c,
16774PC_PERF_PKR0_PRIMS_REUSE = 0x0000001d,
16775PC_PERF_SC_PC_PTR_SEND1 = 0x0000001e,
16776PC_PERF_SC_PC_PTR_VALID1 = 0x0000001f,
16777PC_PERF_SC_FPOSG1 = 0x00000020,
16778PC_PERF_SC_FPOSG_WAIT1 = 0x00000021,
16779PC_PERF_SC_WAIT_SYNC1 = 0x00000022,
16780PC_PERF_SC_PQ_FREEZE1 = 0x00000023,
16781PC_PERF_PKR1_FPOSG_EQ1 = 0x00000024,
16782PC_PERF_PKR1_FPOSG_GT1 = 0x00000025,
16783PC_PERF_PKR1_FPOSG_GT16 = 0x00000026,
16784PC_PERF_PKR1_FPOSG_GT64 = 0x00000027,
16785PC_PERF_PKR1_FPOSG_GT128 = 0x00000028,
16786PC_PERF_PKR1_FPOSG_OUT_OF_WAVE = 0x00000029,
16787PC_PERF_PKR1_NUM_PROBES = 0x0000002a,
16788PC_PERF_PKR1_PRIMS_PER_PROBE_EQ1 = 0x0000002b,
16789PC_PERF_PKR1_PRIMS_PER_PROBE_GT1 = 0x0000002c,
16790PC_PERF_PKR1_PRIMS_PER_PROBE_GT2 = 0x0000002d,
16791PC_PERF_PKR1_PRIMS_PER_PROBE_GT4 = 0x0000002e,
16792PC_PERF_PKR1_PRIMS_PER_PROBE_GT8 = 0x0000002f,
16793PC_PERF_PKR1_NUM_WAVES = 0x00000030,
16794PC_PERF_PKR1_PRIMS_PER_WAVE_EQ1 = 0x00000031,
16795PC_PERF_PKR1_PRIMS_PER_WAVE_GT1 = 0x00000032,
16796PC_PERF_PKR1_PRIMS_PER_WAVE_GT2 = 0x00000033,
16797PC_PERF_PKR1_PRIMS_PER_WAVE_GT4 = 0x00000034,
16798PC_PERF_PKR1_PRIMS_PER_WAVE_GT8 = 0x00000035,
16799PC_PERF_PKR1_PROBES_PER_WAVE_EQ1 = 0x00000036,
16800PC_PERF_PKR1_PROBES_PER_WAVE_GT1 = 0x00000037,
16801PC_PERF_PKR1_PROBES_PER_WAVE_GT2 = 0x00000038,
16802PC_PERF_PKR1_PROBES_PER_WAVE_GT4 = 0x00000039,
16803PC_PERF_PKR1_PROBES_PER_WAVE_GT8 = 0x0000003a,
16804PC_PERF_PKR1_PRIMS_REUSE = 0x0000003b,
16805PC_PERF_SC_PC_PTR_SEND2 = 0x0000003c,
16806PC_PERF_SC_PC_PTR_VALID2 = 0x0000003d,
16807PC_PERF_SC_FPOSG2 = 0x0000003e,
16808PC_PERF_SC_FPOSG_WAIT2 = 0x0000003f,
16809PC_PERF_SC_WAIT_SYNC2 = 0x00000040,
16810PC_PERF_SC_PQ_FREEZE2 = 0x00000041,
16811PC_PERF_PKR2_FPOSG_EQ1 = 0x00000042,
16812PC_PERF_PKR2_FPOSG_GT1 = 0x00000043,
16813PC_PERF_PKR2_FPOSG_GT16 = 0x00000044,
16814PC_PERF_PKR2_FPOSG_GT64 = 0x00000045,
16815PC_PERF_PKR2_FPOSG_GT128 = 0x00000046,
16816PC_PERF_PKR2_FPOSG_OUT_OF_WAVE = 0x00000047,
16817PC_PERF_PKR2_NUM_PROBES = 0x00000048,
16818PC_PERF_PKR2_PRIMS_PER_PROBE_EQ1 = 0x00000049,
16819PC_PERF_PKR2_PRIMS_PER_PROBE_GT1 = 0x0000004a,
16820PC_PERF_PKR2_PRIMS_PER_PROBE_GT2 = 0x0000004b,
16821PC_PERF_PKR2_PRIMS_PER_PROBE_GT4 = 0x0000004c,
16822PC_PERF_PKR2_PRIMS_PER_PROBE_GT8 = 0x0000004d,
16823PC_PERF_PKR2_NUM_WAVES = 0x0000004e,
16824PC_PERF_PKR2_PRIMS_PER_WAVE_EQ1 = 0x0000004f,
16825PC_PERF_PKR2_PRIMS_PER_WAVE_GT1 = 0x00000050,
16826PC_PERF_PKR2_PRIMS_PER_WAVE_GT2 = 0x00000051,
16827PC_PERF_PKR2_PRIMS_PER_WAVE_GT4 = 0x00000052,
16828PC_PERF_PKR2_PRIMS_PER_WAVE_GT8 = 0x00000053,
16829PC_PERF_PKR2_PROBES_PER_WAVE_EQ1 = 0x00000054,
16830PC_PERF_PKR2_PROBES_PER_WAVE_GT1 = 0x00000055,
16831PC_PERF_PKR2_PROBES_PER_WAVE_GT2 = 0x00000056,
16832PC_PERF_PKR2_PROBES_PER_WAVE_GT4 = 0x00000057,
16833PC_PERF_PKR2_PROBES_PER_WAVE_GT8 = 0x00000058,
16834PC_PERF_PKR2_PRIMS_REUSE = 0x00000059,
16835PC_PERF_SC_PC_PTR_SEND3 = 0x0000005a,
16836PC_PERF_SC_PC_PTR_VALID3 = 0x0000005b,
16837PC_PERF_SC_FPOSG3 = 0x0000005c,
16838PC_PERF_SC_FPOSG_WAIT3 = 0x0000005d,
16839PC_PERF_SC_WAIT_SYNC3 = 0x0000005e,
16840PC_PERF_SC_PQ_FREEZE3 = 0x0000005f,
16841PC_PERF_PKR3_FPOSG_EQ1 = 0x00000060,
16842PC_PERF_PKR3_FPOSG_GT1 = 0x00000061,
16843PC_PERF_PKR3_FPOSG_GT16 = 0x00000062,
16844PC_PERF_PKR3_FPOSG_GT64 = 0x00000063,
16845PC_PERF_PKR3_FPOSG_GT128 = 0x00000064,
16846PC_PERF_PKR3_FPOSG_OUT_OF_WAVE = 0x00000065,
16847PC_PERF_PKR3_NUM_PROBES = 0x00000066,
16848PC_PERF_PKR3_PRIMS_PER_PROBE_EQ1 = 0x00000067,
16849PC_PERF_PKR3_PRIMS_PER_PROBE_GT1 = 0x00000068,
16850PC_PERF_PKR3_PRIMS_PER_PROBE_GT2 = 0x00000069,
16851PC_PERF_PKR3_PRIMS_PER_PROBE_GT4 = 0x0000006a,
16852PC_PERF_PKR3_PRIMS_PER_PROBE_GT8 = 0x0000006b,
16853PC_PERF_PKR3_NUM_WAVES = 0x0000006c,
16854PC_PERF_PKR3_PRIMS_PER_WAVE_EQ1 = 0x0000006d,
16855PC_PERF_PKR3_PRIMS_PER_WAVE_GT1 = 0x0000006e,
16856PC_PERF_PKR3_PRIMS_PER_WAVE_GT2 = 0x0000006f,
16857PC_PERF_PKR3_PRIMS_PER_WAVE_GT4 = 0x00000070,
16858PC_PERF_PKR3_PRIMS_PER_WAVE_GT8 = 0x00000071,
16859PC_PERF_PKR3_PROBES_PER_WAVE_EQ1 = 0x00000072,
16860PC_PERF_PKR3_PROBES_PER_WAVE_GT1 = 0x00000073,
16861PC_PERF_PKR3_PROBES_PER_WAVE_GT2 = 0x00000074,
16862PC_PERF_PKR3_PROBES_PER_WAVE_GT4 = 0x00000075,
16863PC_PERF_PKR3_PROBES_PER_WAVE_GT8 = 0x00000076,
16864PC_PERF_PKR3_PRIMS_REUSE = 0x00000077,
16865PC_PERF_SC_MW_FREEZE = 0x00000078,
16866PC_PERF_SC_NUM_PROBES = 0x00000079,
16867PC_PERF_SC_NUM_WAVES = 0x0000007a,
16868PC_PERF_SC_NUM_SPLIT_WAVES = 0x0000007b,
16869PC_PERF_GE_GSDONE = 0x0000007c,
16870PC_PERF_PKR0_GSDONE_WHILE_IDLE = 0x0000007d,
16871PC_PERF_PKR1_GSDONE_WHILE_IDLE = 0x0000007e,
16872PC_PERF_PKR2_GSDONE_WHILE_IDLE = 0x0000007f,
16873PC_PERF_PKR3_GSDONE_WHILE_IDLE = 0x00000080,
16874PC_PERF_PC_SPI_PROBE_FREEZE = 0x00000081,
16875PC_PERF_PC_SPI_PROBE_OUT_OF_CREDIT = 0x00000082,
16876PC_PERF_MW_RTN_ADDR_FREEZE = 0x00000083,
16877PC_PERF_MW_PROBE_CNT_FREEZE = 0x00000084,
16878PC_PERF_MW_GL1H_REQ_FREEZE = 0x00000085,
16879PC_PERF_MW_GL1H_NUM_REQS = 0x00000086,
16880PC_PERF_MW_DLINE_ALLOC = 0x00000087,
16881PC_PERF_MW_DLINE_DEALLOC = 0x00000088,
16882PC_PERF_MW_TAGLINE_ALLOC = 0x00000089,
16883PC_PERF_MW_TAGLINE_DEALLOC = 0x0000008a,
16884PC_PERF_MW_PHY_DLINE_FULL_STALL = 0x0000008b,
16885PC_PERF_MW_CACHE_CNTL_FULL_STALL = 0x0000008c,
16886PC_PERF_MW_STAMP_LIMIT_STALL = 0x0000008d,
16887PC_PERF_MW_CACHE_MISS = 0x0000008e,
16888PC_PERF_MW_CACHE_HIT = 0x0000008f,
16889PC_PERF_MW_CACHE_REUSE = 0x00000090,
16890PC_PERF_MW_DEALLOC_HIT = 0x00000091,
16891PC_PERF_PC_MEM_BANK_CONF0 = 0x00000092,
16892PC_PERF_PC_MEM_BANK_CONF1 = 0x00000093,
16893PC_PERF_PC_LDS_VERTEX_REUSE0 = 0x00000094,
16894PC_PERF_PC_LDS_CNTL_VALID0 = 0x00000095,
16895PC_PERF_PC_LDS_VERTEX_REUSE1 = 0x00000096,
16896PC_PERF_PC_LDS_CNTL_VALID1 = 0x00000097,
16897PC_PERF_GRBM_BUSY = 0x00000098,
16898PC_PERF_GL1_RTN_CNT_GTE1 = 0x00000099,
16899PC_PERF_GL1_RTN_CNT_GT512 = 0x0000009a,
16900PC_PERF_GL1_RTN_CNT_GT768 = 0x0000009b,
16901PC_PERF_LWC0_PROBE_ORDER_STALL = 0x0000009c,
16902PC_PERF_LWC0_PC_MEM_READ_STALL = 0x0000009d,
16903PC_PERF_LWC0_PKR2_SA_BDRY_CROSSING = 0x0000009e,
16904PC_PERF_LWC0_PKR3_SA_BDRY_CROSSING = 0x0000009f,
16905PC_PERF_LWC1_PROBE_ORDER_STALL = 0x000000a0,
16906PC_PERF_LWC1_PC_MEM_READ_STALL = 0x000000a1,
16907PC_PERF_LWC1_PKR0_SA_BDRY_CROSSING = 0x000000a2,
16908PC_PERF_LWC1_PKR1_SA_BDRY_CROSSING = 0x000000a3,
16909PC_PERF_NUM_PSWAVE = 0x000000a4,
16910} PC_PERFCNT_SEL;
16911
16912/*
16913 * SPI_FOG_MODE enum
16914 */
16915
16916typedef enum SPI_FOG_MODE {
16917SPI_FOG_NONE = 0x00000000,
16918SPI_FOG_EXP = 0x00000001,
16919SPI_FOG_EXP2 = 0x00000002,
16920SPI_FOG_LINEAR = 0x00000003,
16921} SPI_FOG_MODE;
16922
16923/*
16924 * SPI_LB_WAVES_SELECT enum
16925 */
16926
16927typedef enum SPI_LB_WAVES_SELECT {
16928HS_GS = 0x00000000,
16929PS = 0x00000001,
16930CS_NA = 0x00000002,
16931SPI_LB_WAVES_RSVD = 0x00000003,
16932} SPI_LB_WAVES_SELECT;
16933
16934/*
16935 * SPI_PERFCNT_SEL enum
16936 */
16937
16938typedef enum SPI_PERFCNT_SEL {
16939SPI_PERF_GS_WINDOW_VALID = 0x00000001,
16940SPI_PERF_GS_BUSY = 0x00000002,
16941SPI_PERF_GS_CRAWLER_STALL = 0x00000003,
16942SPI_PERF_GS_EVENT_WAVE = 0x00000004,
16943SPI_PERF_GS_WAVE = 0x00000005,
16944SPI_PERF_GS_PERS_UPD_FULL0 = 0x00000006,
16945SPI_PERF_GS_PERS_UPD_FULL1 = 0x00000007,
16946SPI_PERF_GS_FIRST_SUBGRP = 0x00000008,
16947SPI_PERF_GS_HS_DEALLOC = 0x00000009,
16948SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 0x0000000a,
16949SPI_PERF_GS_POS0_STALL = 0x0000000b,
16950SPI_PERF_GS_POS1_STALL = 0x0000000c,
16951SPI_PERF_GS_INDX0_STALL = 0x0000000d,
16952SPI_PERF_GS_INDX1_STALL = 0x0000000e,
16953SPI_PERF_GS_PWS_STALL = 0x0000000f,
16954SPI_PERF_GS_GRP_LIFETIME = 0x00000010,
16955SPI_PERF_GS_WAVE_IN_FLIGHT = 0x00000011,
16956SPI_PERF_GS_GRP_LIFETIME_SAMPLE = 0x00000012,
16957SPI_PERF_HS_WINDOW_VALID = 0x00000015,
16958SPI_PERF_HS_BUSY = 0x00000016,
16959SPI_PERF_HS_CRAWLER_STALL = 0x00000017,
16960SPI_PERF_HS_FIRST_WAVE = 0x00000018,
16961SPI_PERF_HS_EVENT_WAVE = 0x0000001a,
16962SPI_PERF_HS_WAVE = 0x0000001b,
16963SPI_PERF_HS_PERS_UPD_FULL0 = 0x0000001c,
16964SPI_PERF_HS_PERS_UPD_FULL1 = 0x0000001d,
16965SPI_PERF_HS_PWS_STALL = 0x0000001e,
16966SPI_PERF_HS_WAVE_IN_FLIGHT = 0x0000001f,
16967SPI_PERF_CSGN_WINDOW_VALID = 0x00000025,
16968SPI_PERF_CSGN_BUSY = 0x00000026,
16969SPI_PERF_CSGN_NUM_THREADGROUPS = 0x00000027,
16970SPI_PERF_CSGN_CRAWLER_STALL = 0x00000028,
16971SPI_PERF_CSGN_EVENT_WAVE = 0x00000029,
16972SPI_PERF_CSGN_WAVE = 0x0000002a,
16973SPI_PERF_CSGN_PWS_STALL = 0x0000002b,
16974SPI_PERF_CSGN_WAVE_IN_FLIGHT = 0x0000002c,
16975SPI_PERF_CSN_WINDOW_VALID = 0x0000002d,
16976SPI_PERF_CSN_BUSY = 0x0000002e,
16977SPI_PERF_CSN_NUM_THREADGROUPS = 0x0000002f,
16978SPI_PERF_CSN_CRAWLER_STALL = 0x00000030,
16979SPI_PERF_CSN_EVENT_WAVE = 0x00000031,
16980SPI_PERF_CSN_WAVE = 0x00000032,
16981SPI_PERF_CSN_WAVE_IN_FLIGHT = 0x00000033,
16982SPI_PERF_PS0_WINDOW_VALID = 0x00000035,
16983SPI_PERF_PS1_WINDOW_VALID = 0x00000036,
16984SPI_PERF_PS2_WINDOW_VALID = 0x00000037,
16985SPI_PERF_PS3_WINDOW_VALID = 0x00000038,
16986SPI_PERF_PS0_BUSY = 0x00000039,
16987SPI_PERF_PS1_BUSY = 0x0000003a,
16988SPI_PERF_PS2_BUSY = 0x0000003b,
16989SPI_PERF_PS3_BUSY = 0x0000003c,
16990SPI_PERF_PS0_ACTIVE = 0x0000003d,
16991SPI_PERF_PS1_ACTIVE = 0x0000003e,
16992SPI_PERF_PS2_ACTIVE = 0x0000003f,
16993SPI_PERF_PS3_ACTIVE = 0x00000040,
16994SPI_PERF_PS0_DEALLOC = 0x00000041,
16995SPI_PERF_PS1_DEALLOC = 0x00000042,
16996SPI_PERF_PS2_DEALLOC = 0x00000043,
16997SPI_PERF_PS3_DEALLOC = 0x00000044,
16998SPI_PERF_PS0_EVENT_WAVE = 0x00000045,
16999SPI_PERF_PS1_EVENT_WAVE = 0x00000046,
17000SPI_PERF_PS2_EVENT_WAVE = 0x00000047,
17001SPI_PERF_PS3_EVENT_WAVE = 0x00000048,
17002SPI_PERF_PS0_WAVE = 0x00000049,
17003SPI_PERF_PS1_WAVE = 0x0000004a,
17004SPI_PERF_PS2_WAVE = 0x0000004b,
17005SPI_PERF_PS3_WAVE = 0x0000004c,
17006SPI_PERF_PS0_OPT_WAVE = 0x0000004d,
17007SPI_PERF_PS1_OPT_WAVE = 0x0000004e,
17008SPI_PERF_PS2_OPT_WAVE = 0x0000004f,
17009SPI_PERF_PS3_OPT_WAVE = 0x00000050,
17010SPI_PERF_PS0_PRIM_BIN0 = 0x00000051,
17011SPI_PERF_PS1_PRIM_BIN0 = 0x00000052,
17012SPI_PERF_PS2_PRIM_BIN0 = 0x00000053,
17013SPI_PERF_PS3_PRIM_BIN0 = 0x00000054,
17014SPI_PERF_PS0_PRIM_BIN1 = 0x00000055,
17015SPI_PERF_PS1_PRIM_BIN1 = 0x00000056,
17016SPI_PERF_PS2_PRIM_BIN1 = 0x00000057,
17017SPI_PERF_PS3_PRIM_BIN1 = 0x00000058,
17018SPI_PERF_PS0_CRAWLER_STALL = 0x00000059,
17019SPI_PERF_PS1_CRAWLER_STALL = 0x0000005a,
17020SPI_PERF_PS2_CRAWLER_STALL = 0x0000005b,
17021SPI_PERF_PS3_CRAWLER_STALL = 0x0000005c,
17022SPI_PERF_PS_PERS_UPD_FULL0 = 0x0000005d,
17023SPI_PERF_PS_PERS_UPD_FULL1 = 0x0000005e,
17024SPI_PERF_PS0_2_WAVE_GROUPS = 0x0000005f,
17025SPI_PERF_PS1_2_WAVE_GROUPS = 0x00000060,
17026SPI_PERF_PS2_2_WAVE_GROUPS = 0x00000061,
17027SPI_PERF_PS3_2_WAVE_GROUPS = 0x00000062,
17028SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 0x00000063,
17029SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 0x00000064,
17030SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 0x00000065,
17031SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 0x00000066,
17032SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 0x00000067,
17033SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 0x00000068,
17034SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 0x00000069,
17035SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 0x0000006a,
17036SPI_PERF_PS_PWS_STALL = 0x0000006b,
17037SPI_PERF_PS0_LDS_DONE_FULL = 0x0000006c,
17038SPI_PERF_PS1_LDS_DONE_FULL = 0x0000006d,
17039SPI_PERF_PS2_LDS_DONE_FULL = 0x0000006e,
17040SPI_PERF_PS3_LDS_DONE_FULL = 0x0000006f,
17041SPI_PERF_PS0_DEALLOC_FULL = 0x00000070,
17042SPI_PERF_PS1_DEALLOC_FULL = 0x00000071,
17043SPI_PERF_PS2_DEALLOC_FULL = 0x00000072,
17044SPI_PERF_PS3_DEALLOC_FULL = 0x00000073,
17045SPI_PERF_PS0_WAVE_IN_FLIGHT = 0x00000074,
17046SPI_PERF_PS1_WAVE_IN_FLIGHT = 0x00000075,
17047SPI_PERF_PS2_WAVE_IN_FLIGHT = 0x00000076,
17048SPI_PERF_PS3_WAVE_IN_FLIGHT = 0x00000077,
17049SPI_PERF_RA_GS_LDS_OCCUPANCY = 0x00000085,
17050SPI_PERF_RA_GS_VGPR_OCCUPANCY = 0x00000086,
17051SPI_PERF_RA_PS_LDS_OCCUPANCY = 0x00000087,
17052SPI_PERF_RA_PS_VGPR_OCCUPANCY = 0x00000088,
17053SPI_PERF_RA_SPI_THROTTLE = 0x00000089,
17054SPI_PERF_RA_PH_THROTTLE = 0x0000008a,
17055SPI_PERF_RA_PC_PROBE_STALL_PS = 0x0000008b,
17056SPI_PERF_RA_PC_PSWAVE_STALL_PS = 0x0000008c,
17057SPI_PERF_RA_PIPE_REQ_BIN2 = 0x0000008d,
17058SPI_PERF_RA_TASK_REQ_BIN3 = 0x0000008e,
17059SPI_PERF_RA_WR_CTL_FULL = 0x0000008f,
17060SPI_PERF_RA_REQ_NO_ALLOC = 0x00000090,
17061SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x00000091,
17062SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x00000092,
17063SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x00000093,
17064SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x00000094,
17065SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x00000095,
17066SPI_PERF_RA_RES_STALL_PS = 0x00000096,
17067SPI_PERF_RA_RES_STALL_GS = 0x00000097,
17068SPI_PERF_RA_RES_STALL_HS = 0x00000098,
17069SPI_PERF_RA_RES_STALL_CSG = 0x00000099,
17070SPI_PERF_RA_RES_STALL_CSN = 0x0000009a,
17071SPI_PERF_RA_TMP_STALL_PS = 0x0000009b,
17072SPI_PERF_RA_TMP_STALL_GS = 0x0000009c,
17073SPI_PERF_RA_TMP_STALL_HS = 0x0000009d,
17074SPI_PERF_RA_TMP_STALL_CSG = 0x0000009e,
17075SPI_PERF_RA_TMP_STALL_CSN = 0x0000009f,
17076SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x000000a0,
17077SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x000000a1,
17078SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x000000a2,
17079SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x000000a3,
17080SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x000000a4,
17081SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x000000a5,
17082SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x000000a6,
17083SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x000000a7,
17084SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x000000a8,
17085SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x000000a9,
17086SPI_PERF_RA_LDS_CU_FULL_PS = 0x000000aa,
17087SPI_PERF_RA_LDS_CU_FULL_HS = 0x000000ab,
17088SPI_PERF_RA_LDS_CU_FULL_GS = 0x000000ac,
17089SPI_PERF_RA_LDS_CU_FULL_CSG = 0x000000ad,
17090SPI_PERF_RA_LDS_CU_FULL_CSN = 0x000000ae,
17091SPI_PERF_RA_BAR_CU_FULL_PS = 0x000000af,
17092SPI_PERF_RA_BAR_CU_FULL_GS = 0x000000b0,
17093SPI_PERF_RA_BAR_CU_FULL_HS = 0x000000b1,
17094SPI_PERF_RA_BAR_CU_FULL_CSG = 0x000000b2,
17095SPI_PERF_RA_BAR_CU_FULL_CSN = 0x000000b3,
17096SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x000000b4,
17097SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x000000b5,
17098SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x000000b6,
17099SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x000000b7,
17100SPI_PERF_RA_WVLIM_STALL_PS = 0x000000b8,
17101SPI_PERF_RA_WVLIM_STALL_GS = 0x000000b9,
17102SPI_PERF_RA_WVLIM_STALL_HS = 0x000000ba,
17103SPI_PERF_RA_WVLIM_STALL_CSG = 0x000000bb,
17104SPI_PERF_RA_WVLIM_STALL_CSN = 0x000000bc,
17105SPI_PERF_RA_GS_LOCK = 0x000000bd,
17106SPI_PERF_RA_HS_LOCK = 0x000000be,
17107SPI_PERF_RA_CSG_LOCK = 0x000000bf,
17108SPI_PERF_RA_CSN_LOCK = 0x000000c0,
17109SPI_PERF_RA_RSV_UPD = 0x000000c1,
17110SPI_PERF_RA_PRE_ALLOC_STALL = 0x000000c2,
17111SPI_PERF_RA_GFX_UNDER_TUNNEL = 0x000000c3,
17112SPI_PERF_RA_CSC_UNDER_TUNNEL = 0x000000c4,
17113SPI_PERF_RA_WVALLOC_STALL = 0x000000c5,
17114SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 0x000000c6,
17115SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 0x000000c7,
17116SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 0x000000c8,
17117SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 0x000000c9,
17118SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 0x000000ca,
17119SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 0x000000cb,
17120SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 0x000000cc,
17121SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 0x000000cd,
17122SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 0x000000ce,
17123SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 0x000000cf,
17124SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 0x000000d0,
17125SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 0x000000d1,
17126SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 0x000000d2,
17127SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 0x000000d3,
17128SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 0x000000d4,
17129SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 0x000000d5,
17130SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 0x000000d6,
17131SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 0x000000d7,
17132SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 0x000000d8,
17133SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 0x000000d9,
17134SPI_PERF_EXP_ARB_COL_CNT = 0x000000da,
17135SPI_PERF_EXP_ARB_POS_CNT = 0x000000db,
17136SPI_PERF_EXP_ARB_GDS_CNT = 0x000000dc,
17137SPI_PERF_EXP_ARB_IDX_CNT = 0x000000dd,
17138SPI_PERF_EXP_WITH_CONFLICT = 0x000000de,
17139SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 0x000000df,
17140SPI_PERF_GS_EXP_DONE = 0x000000e0,
17141SPI_PERF_PS_EXP_DONE = 0x000000e1,
17142SPI_PERF_PS_EXP_ARB_CONFLICT = 0x000000e2,
17143SPI_PERF_GS_SCBD_IDX_CLEANUP = 0x000000e3,
17144SPI_PERF_GS_SCBD_POS_CLEANUP = 0x000000e4,
17145SPI_PERF_PS_EXP_ALLOC = 0x000000e5,
17146SPI_PERF_PS0_WAVEID_STARVED = 0x000000e6,
17147SPI_PERF_PS1_WAVEID_STARVED = 0x000000e7,
17148SPI_PERF_PS2_WAVEID_STARVED = 0x000000e8,
17149SPI_PERF_PS3_WAVEID_STARVED = 0x000000e9,
17150SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 0x000000ea,
17151SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 0x000000eb,
17152SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 0x000000ec,
17153SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 0x000000ed,
17154SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 0x000000ee,
17155SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 0x000000ef,
17156SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 0x000000f0,
17157SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 0x000000f1,
17158SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 0x000000f2,
17159SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 0x000000f3,
17160SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 0x000000f4,
17161SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 0x000000f5,
17162SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 0x000000f6,
17163SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 0x000000f7,
17164SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 0x000000f8,
17165SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 0x000000f9,
17166SPI_PERF_NUM_EXPGRANT_EXPORTS = 0x000000fa,
17167SPI_PERF_GS_ALLOC_IDX = 0x000000fb,
17168SPI_PERF_GS_ALLOC_POS = 0x000000fc,
17169SPI_PERF_PIX_ALLOC_PEND_CNT = 0x000000fd,
17170SPI_PERF_EXPORT_SCB0_STALL = 0x000000fe,
17171SPI_PERF_EXPORT_SCB1_STALL = 0x000000ff,
17172SPI_PERF_EXPORT_SCB2_STALL = 0x00000100,
17173SPI_PERF_EXPORT_SCB3_STALL = 0x00000101,
17174SPI_PERF_EXPORT_DB0_STALL = 0x00000102,
17175SPI_PERF_EXPORT_DB1_STALL = 0x00000103,
17176SPI_PERF_EXPORT_DB2_STALL = 0x00000104,
17177SPI_PERF_EXPORT_DB3_STALL = 0x00000105,
17178SPI_PERF_EXPORT_DB4_STALL = 0x00000106,
17179SPI_PERF_EXPORT_DB5_STALL = 0x00000107,
17180SPI_PERF_EXPORT_DB6_STALL = 0x00000108,
17181SPI_PERF_EXPORT_DB7_STALL = 0x00000109,
17182SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 0x0000010a,
17183SPI_PERF_GS_NGG_STALL_MSG_VAL = 0x0000010b,
17184SPI_PERF_SWC_PS_WR = 0x0000010c,
17185SPI_PERF_SWC_GS_WR = 0x0000010d,
17186SPI_PERF_SWC_HS_WR = 0x0000010e,
17187SPI_PERF_SWC_CSGN_WR = 0x0000010f,
17188SPI_PERF_SWC_CSN_WR = 0x00000110,
17189SPI_PERF_VWC_PS_WR = 0x00000111,
17190SPI_PERF_VWC_ES_WR = 0x00000112,
17191SPI_PERF_VWC_GS_WR = 0x00000113,
17192SPI_PERF_VWC_LS_WR = 0x00000114,
17193SPI_PERF_VWC_HS_WR = 0x00000115,
17194SPI_PERF_VWC_CSGN_WR = 0x00000116,
17195SPI_PERF_VWC_CSN_WR = 0x00000117,
17196SPI_PERF_EXP_THROT_UPSTEP = 0x00000118,
17197SPI_PERF_EXP_THROT_DOWNSTEP = 0x00000119,
17198SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 0x0000011a,
17199SPI_PERF_BUSY = 0x0000011b,
17200SPI_PERF_ALL_PS_WAVE = 0x0000011c,
17201SPI_PERF_ALL_PS_WAVE_IN_FLIGHT = 0x0000011d,
17202SPI_PERF_ALL_WAVE = 0x0000011e,
17203SPI_PERF_ALL_WAVE_IN_FLIGHT = 0x0000011f,
17204SPI_PERF_RA_REQ_ALLOC = 0x00000120,
17205SPI_PERF_VGPR_INIT = 0x00000121,
17206SPI_PERF_SGPR_INIT = 0x00000122,
17207SPI_PERF_VGPR_ALLOC_LEVEL = 0x00000123,
17208SPI_PERF_LDS_ALLOC_LEVEL = 0x00000124,
17209SPI_PERF_GFX_TEMP_ALLOC_LEVEL = 0x00000125,
17210SPI_PERF_CSG_TEMP_ALLOC_LEVEL = 0x00000126,
17211SPI_PERF_CSN_TEMP_ALLOC_LEVEL = 0x00000127,
17212SPI_PERF_ALL_WAVE_RESTORED = 0x00000128,
17213SPI_PERF_ALL_WAVE_SAVED = 0x00000129,
17214SPI_PERF_ALL_WAVE_W32 = 0x0000012a,
17215SPI_PERF_ALL_WAVE_W64 = 0x0000012b,
17216SPI_PERF_ALL_WAVE_ITEMS = 0x0000012c,
17217SPI_PERF_ALL_WAVE_ITEMS_W32 = 0x0000012d,
17218SPI_PERF_ALL_WAVE_ITEMS_W64 = 0x0000012e,
17219SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_STALL = 0x0000012f,
17220SPI_PERF_RA_REQ_ALLOC_WGP_TAKEOVER_LEVEL = 0x00000130,
17221SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_STALL = 0x00000131,
17222SPI_PERF_RA_REQ_ALLOC_DYN_VGPR_CU_LEVEL = 0x00000132,
17223} SPI_PERFCNT_SEL;
17224
17225/*
17226 * SPI_PNT_SPRITE_OVERRIDE enum
17227 */
17228
17229typedef enum SPI_PNT_SPRITE_OVERRIDE {
17230SPI_PNT_SPRITE_SEL_0 = 0x00000000,
17231SPI_PNT_SPRITE_SEL_1 = 0x00000001,
17232SPI_PNT_SPRITE_SEL_S = 0x00000002,
17233SPI_PNT_SPRITE_SEL_T = 0x00000003,
17234SPI_PNT_SPRITE_SEL_NONE = 0x00000004,
17235} SPI_PNT_SPRITE_OVERRIDE;
17236
17237/*
17238 * SPI_PS_LDS_GROUP_SIZE enum
17239 */
17240
17241typedef enum SPI_PS_LDS_GROUP_SIZE {
17242SPI_PS_LDS_GROUP_1 = 0x00000000,
17243SPI_PS_LDS_GROUP_2 = 0x00000001,
17244SPI_PS_LDS_GROUP_4 = 0x00000002,
17245} SPI_PS_LDS_GROUP_SIZE;
17246
17247/*
17248 * SPI_SAMPLE_CNTL enum
17249 */
17250
17251typedef enum SPI_SAMPLE_CNTL {
17252CENTROIDS_ONLY = 0x00000000,
17253CENTERS_ONLY = 0x00000001,
17254CENTROIDS_AND_CENTERS = 0x00000002,
17255UNDEF = 0x00000003,
17256} SPI_SAMPLE_CNTL;
17257
17258/*
17259 * SPI_SHADER_EX_FORMAT enum
17260 */
17261
17262typedef enum SPI_SHADER_EX_FORMAT {
17263SPI_SHADER_ZERO = 0x00000000,
17264SPI_SHADER_32_R = 0x00000001,
17265SPI_SHADER_32_GR = 0x00000002,
17266SPI_SHADER_32_AR = 0x00000003,
17267SPI_SHADER_FP16_ABGR = 0x00000004,
17268SPI_SHADER_UNORM16_ABGR = 0x00000005,
17269SPI_SHADER_SNORM16_ABGR = 0x00000006,
17270SPI_SHADER_UINT16_ABGR = 0x00000007,
17271SPI_SHADER_SINT16_ABGR = 0x00000008,
17272SPI_SHADER_32_ABGR = 0x00000009,
17273} SPI_SHADER_EX_FORMAT;
17274
17275/*
17276 * SPI_SHADER_FORMAT enum
17277 */
17278
17279typedef enum SPI_SHADER_FORMAT {
17280SPI_SHADER_NONE = 0x00000000,
17281SPI_SHADER_1COMP = 0x00000001,
17282SPI_SHADER_2COMP = 0x00000002,
17283SPI_SHADER_4COMPRESS = 0x00000003,
17284SPI_SHADER_4COMP = 0x00000004,
17285} SPI_SHADER_FORMAT;
17286
17287/*******************************************************
17288 * SQ Enums
17289 *******************************************************/
17290
17291/*
17292 * SH_MEM_ADDRESS_MODE enum
17293 */
17294
17295typedef enum SH_MEM_ADDRESS_MODE {
17296SH_MEM_ADDRESS_MODE_64 = 0x00000000,
17297SH_MEM_ADDRESS_MODE_32 = 0x00000001,
17298} SH_MEM_ADDRESS_MODE;
17299
17300/*
17301 * SH_MEM_ALIGNMENT_MODE enum
17302 */
17303
17304typedef enum SH_MEM_ALIGNMENT_MODE {
17305SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000,
17306SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001,
17307SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002,
17308SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003,
17309} SH_MEM_ALIGNMENT_MODE;
17310
17311/*
17312 * SQG_PERF_SEL enum
17313 */
17314
17315typedef enum SQG_PERF_SEL {
17316SQG_PERF_SEL_NONE = 0x00000000,
17317SQG_PERF_SEL_MSG_BUS_BUSY = 0x00000001,
17318SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 0x00000002,
17319SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 0x00000003,
17320SQG_PERF_SEL_EXP_BUS0_BUSY = 0x00000004,
17321SQG_PERF_SEL_EXP_BUS1_BUSY = 0x00000005,
17322SQG_PERF_SEL_TTRACE_WRITE_DATA = 0x00000006,
17323SQG_PERF_SEL_TTRACE_STALL = 0x00000007,
17324SQG_PERF_SEL_TTRACE_LOST_PACKETS = 0x00000008,
17325SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 0x00000009,
17326SQG_PERF_SEL_EVENTS = 0x0000000a,
17327SQG_PERF_SEL_WAVES_RESTORED = 0x0000000b,
17328SQG_PERF_SEL_WAVES_SAVED = 0x0000000c,
17329SQG_PERF_SEL_ACCUM_PREV = 0x0000000d,
17330SQG_PERF_SEL_CYCLES = 0x0000000e,
17331SQG_PERF_SEL_BUSY_CYCLES = 0x0000000f,
17332SQG_PERF_SEL_WAVE_CYCLES = 0x00000010,
17333SQG_PERF_SEL_MSG = 0x00000011,
17334SQG_PERF_SEL_MSG_INTERRUPT = 0x00000012,
17335SQG_PERF_SEL_WAVES = 0x00000013,
17336SQG_PERF_SEL_WAVES_32 = 0x00000014,
17337SQG_PERF_SEL_WAVES_64 = 0x00000015,
17338SQG_PERF_SEL_LEVEL_WAVES = 0x00000016,
17339SQG_PERF_SEL_ITEMS = 0x00000017,
17340SQG_PERF_SEL_WAVE32_ITEMS = 0x00000018,
17341SQG_PERF_SEL_WAVE64_ITEMS = 0x00000019,
17342SQG_PERF_SEL_PS_QUADS = 0x0000001a,
17343SQG_PERF_SEL_WAVES_EQ_64 = 0x0000001b,
17344SQG_PERF_SEL_WAVES_EQ_32 = 0x0000001c,
17345SQG_PERF_SEL_WAVES_LT_64 = 0x0000001d,
17346SQG_PERF_SEL_WAVES_LT_48 = 0x0000001e,
17347SQG_PERF_SEL_WAVES_LT_32 = 0x0000001f,
17348SQG_PERF_SEL_WAVES_LT_16 = 0x00000020,
17349SQG_PERF_SEL_REFCLKS = 0x00000021,
17350SQG_PERF_SEL_WAVES_WGP_TAKEOVER = 0x00000022,
17351SQG_PERF_SEL_WAVES_DYN_VGPR = 0x00000023,
17352SQG_PERF_SEL_ITEMS_PS = 0x00000024,
17353SQG_PERF_SEL_ITEMS_GS = 0x00000025,
17354SQG_PERF_SEL_ITEMS_HS = 0x00000026,
17355SQG_PERF_SEL_ITEMS_CS = 0x00000027,
17356SQG_PERF_SEL_WAVES_VEC32 = 0x00000028,
17357SQG_PERF_SEL_WAVES_PS_VEC32 = 0x00000029,
17358SQG_PERF_SEL_WAVES_GS_VEC32 = 0x0000002a,
17359SQG_PERF_SEL_WAVES_HS_VEC32 = 0x0000002b,
17360SQG_PERF_SEL_WAVES_CS_VEC32 = 0x0000002c,
17361SQG_PERF_SEL_LEVEL_WGP_ACTIVE = 0x0000002d,
17362SQG_PERF_SEL_DUMMY_LAST = 0x0000002e,
17363} SQG_PERF_SEL;
17364
17365/*
17366 * SQ_CAC_POWER_SEL enum
17367 */
17368
17369typedef enum SQ_CAC_POWER_SEL {
17370SQ_CAC_POWER_VALU = 0x00000000,
17371SQ_CAC_POWER_VALU0 = 0x00000001,
17372SQ_CAC_POWER_VALU1 = 0x00000002,
17373SQ_CAC_POWER_VALU2 = 0x00000003,
17374SQ_CAC_POWER_GPR_RD = 0x00000004,
17375SQ_CAC_POWER_GPR_WR = 0x00000005,
17376SQ_CAC_POWER_LDS_BUSY = 0x00000006,
17377SQ_CAC_POWER_ALU_BUSY = 0x00000007,
17378SQ_CAC_POWER_TEX_BUSY = 0x00000008,
17379} SQ_CAC_POWER_SEL;
17380
17381/*
17382 * SQ_EDC_INFO_SOURCE enum
17383 */
17384
17385typedef enum SQ_EDC_INFO_SOURCE {
17386SQ_EDC_INFO_SOURCE_INVALID = 0x00000000,
17387SQ_EDC_INFO_SOURCE_INST = 0x00000001,
17388SQ_EDC_INFO_SOURCE_SGPR = 0x00000002,
17389SQ_EDC_INFO_SOURCE_VGPR = 0x00000003,
17390SQ_EDC_INFO_SOURCE_LDS = 0x00000004,
17391SQ_EDC_INFO_SOURCE_GDS = 0x00000005,
17392SQ_EDC_INFO_SOURCE_TA = 0x00000006,
17393} SQ_EDC_INFO_SOURCE;
17394
17395/*
17396 * SQ_IBUF_ST enum
17397 */
17398
17399typedef enum SQ_IBUF_ST {
17400SQ_IBUF_IB_IDLE = 0x00000000,
17401SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001,
17402SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002,
17403SQ_IBUF_IB_LE_4DW = 0x00000003,
17404SQ_IBUF_IB_WAIT_DRET = 0x00000004,
17405SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005,
17406SQ_IBUF_IB_DRET = 0x00000006,
17407SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007,
17408} SQ_IBUF_ST;
17409
17410/*
17411 * SQ_IMG_FILTER_TYPE enum
17412 */
17413
17414typedef enum SQ_IMG_FILTER_TYPE {
17415SQ_IMG_FILTER_MODE_BLEND = 0x00000000,
17416SQ_IMG_FILTER_MODE_MIN = 0x00000001,
17417SQ_IMG_FILTER_MODE_MAX = 0x00000002,
17418} SQ_IMG_FILTER_TYPE;
17419
17420/*
17421 * SQ_IND_CMD_CMD enum
17422 */
17423
17424typedef enum SQ_IND_CMD_CMD {
17425SQ_IND_CMD_CMD_NULL = 0x00000000,
17426SQ_IND_CMD_CMD_SETHALT = 0x00000001,
17427SQ_IND_CMD_CMD_SAVECTX = 0x00000002,
17428SQ_IND_CMD_CMD_KILL = 0x00000003,
17429SQ_IND_CMD_CMD_TRAP_AFTER_INST = 0x00000004,
17430SQ_IND_CMD_CMD_TRAP = 0x00000005,
17431SQ_IND_CMD_CMD_SET_SYS_PRIO = 0x00000006,
17432SQ_IND_CMD_CMD_SETFATALHALT = 0x00000007,
17433SQ_IND_CMD_CMD_SINGLE_STEP = 0x00000008,
17434} SQ_IND_CMD_CMD;
17435
17436/*
17437 * SQ_IND_CMD_MODE enum
17438 */
17439
17440typedef enum SQ_IND_CMD_MODE {
17441SQ_IND_CMD_MODE_SINGLE = 0x00000000,
17442SQ_IND_CMD_MODE_BROADCAST = 0x00000001,
17443SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002,
17444SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003,
17445SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004,
17446} SQ_IND_CMD_MODE;
17447
17448/*
17449 * SQ_INST_STR_ST enum
17450 */
17451
17452typedef enum SQ_INST_STR_ST {
17453SQ_INST_STR_IB_WAVE_NORML = 0x00000000,
17454SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001,
17455SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002,
17456SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003,
17457SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000004,
17458SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000005,
17459} SQ_INST_STR_ST;
17460
17461/*
17462 * SQ_INST_TYPE enum
17463 */
17464
17465typedef enum SQ_INST_TYPE {
17466SQ_INST_TYPE_VALU = 0x00000000,
17467SQ_INST_TYPE_SCALAR = 0x00000001,
17468SQ_INST_TYPE_TEX = 0x00000002,
17469SQ_INST_TYPE_LDS = 0x00000003,
17470SQ_INST_TYPE_LDS_DIRECT = 0x00000004,
17471SQ_INST_TYPE_EXP = 0x00000005,
17472SQ_INST_TYPE_MSG = 0x00000006,
17473SQ_INST_TYPE_BARRIER = 0x00000007,
17474SQ_INST_TYPE_BRANCH_NOT_TAKEN = 0x00000008,
17475SQ_INST_TYPE_BRANCH_TAKEN = 0x00000009,
17476SQ_INST_TYPE_JUMP = 0x0000000a,
17477SQ_INST_TYPE_OTHER = 0x0000000b,
17478SQ_INST_TYPE_NONE = 0x0000000c,
17479SQ_INST_TYPE_DUAL_VALU = 0x0000000d,
17480SQ_INST_TYPE_FLAT = 0x0000000e,
17481SQ_INST_TYPE_VALU_MATRIX = 0x0000000f,
17482} SQ_INST_TYPE;
17483
17484/*
17485 * SQ_LLC_CTL enum
17486 */
17487
17488typedef enum SQ_LLC_CTL {
17489SQ_LLC_0 = 0x00000000,
17490SQ_LLC_1 = 0x00000001,
17491SQ_LLC_RSVD_2 = 0x00000002,
17492SQ_LLC_BYPASS = 0x00000003,
17493} SQ_LLC_CTL;
17494
17495/*
17496 * SQ_NO_INST_ISSUE enum
17497 */
17498
17499typedef enum SQ_NO_INST_ISSUE {
17500SQ_NO_INST_ISSUE_NO_INSTS = 0x00000000,
17501SQ_NO_INST_ISSUE_ALU_DEP = 0x00000001,
17502SQ_NO_INST_ISSUE_S_WAITCNT = 0x00000002,
17503SQ_NO_INST_ISSUE_NO_ARB_WIN = 0x00000003,
17504SQ_NO_INST_ISSUE_SLEEP_WAIT = 0x00000004,
17505SQ_NO_INST_ISSUE_BARRIER_WAIT = 0x00000005,
17506SQ_NO_INST_ISSUE_OTHER = 0x00000006,
17507SQ_NO_INST_ISSUE_INTERNAL = 0x00000007,
17508} SQ_NO_INST_ISSUE;
17509
17510/*
17511 * SQ_OOB_SELECT enum
17512 */
17513
17514typedef enum SQ_OOB_SELECT {
17515SQ_OOB_INDEX_AND_OFFSET = 0x00000000,
17516SQ_OOB_INDEX_ONLY = 0x00000001,
17517SQ_OOB_NUM_RECORDS_0 = 0x00000002,
17518SQ_OOB_COMPLETE = 0x00000003,
17519} SQ_OOB_SELECT;
17520
17521/*
17522 * SQ_PERF_SEL enum
17523 */
17524
17525typedef enum SQ_PERF_SEL {
17526SQ_PERF_SEL_NONE = 0x00000000,
17527SQ_PERF_SEL_ACCUM_PREV = 0x00000001,
17528SQ_PERF_SEL_CYCLES = 0x00000002,
17529SQ_PERF_SEL_BUSY_CYCLES = 0x00000003,
17530SQ_PERF_SEL_WAVES = 0x00000004,
17531SQ_PERF_SEL_WAVES_32 = 0x00000005,
17532SQ_PERF_SEL_WAVES_64 = 0x00000006,
17533SQ_PERF_SEL_LEVEL_WAVES = 0x00000007,
17534SQ_PERF_SEL_ITEMS = 0x00000008,
17535SQ_PERF_SEL_WAVE32_ITEMS = 0x00000009,
17536SQ_PERF_SEL_WAVE64_ITEMS = 0x0000000a,
17537SQ_PERF_SEL_PS_QUADS = 0x0000000b,
17538SQ_PERF_SEL_EVENTS = 0x0000000c,
17539SQ_PERF_SEL_WAVES_EQ_32 = 0x0000000d,
17540SQ_PERF_SEL_WAVES_EQ_64 = 0x0000000e,
17541SQ_PERF_SEL_WAVES_LT_64 = 0x0000000f,
17542SQ_PERF_SEL_WAVES_LT_48 = 0x00000010,
17543SQ_PERF_SEL_WAVES_LT_32 = 0x00000011,
17544SQ_PERF_SEL_WAVES_LT_16 = 0x00000012,
17545SQ_PERF_SEL_WAVES_RESTORED = 0x00000013,
17546SQ_PERF_SEL_WAVES_SAVED = 0x00000014,
17547SQ_PERF_SEL_MSG = 0x00000015,
17548SQ_PERF_SEL_MSG_INTERRUPT = 0x00000016,
17549SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 0x00000017,
17550SQ_PERF_SEL_WAVE_CYCLES = 0x00000018,
17551SQ_PERF_SEL_WAVE_READY = 0x00000019,
17552SQ_PERF_SEL_WAIT_INST_ANY = 0x0000001a,
17553SQ_PERF_SEL_WAIT_ANY = 0x0000001b,
17554SQ_PERF_SEL_WAIT_CNT_ANY = 0x0000001c,
17555SQ_PERF_SEL_WAIT_CNT_LOAD = 0x0000001d,
17556SQ_PERF_SEL_WAIT_CNT_STORE = 0x0000001e,
17557SQ_PERF_SEL_WAIT_TTRACE = 0x0000001f,
17558SQ_PERF_SEL_WAIT_IFETCH = 0x00000020,
17559SQ_PERF_SEL_WAIT_BARRIER = 0x00000021,
17560SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x00000022,
17561SQ_PERF_SEL_WAIT_SLEEP = 0x00000023,
17562SQ_PERF_SEL_WAIT_DELAY_ALU = 0x00000024,
17563SQ_PERF_SEL_WAIT_DEPCTR = 0x00000025,
17564SQ_PERF_SEL_WAIT_OTHER = 0x00000026,
17565SQ_PERF_SEL_INSTS_ALL = 0x00000027,
17566SQ_PERF_SEL_INSTS_BRANCH = 0x00000028,
17567SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 0x00000029,
17568SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 0x0000002a,
17569SQ_PERF_SEL_INSTS_EXP = 0x0000002b,
17570SQ_PERF_SEL_INSTS_FLAT = 0x0000002c,
17571SQ_PERF_SEL_INSTS_LDS = 0x0000002d,
17572SQ_PERF_SEL_INSTS_SALU = 0x0000002e,
17573SQ_PERF_SEL_INSTS_SMEM = 0x0000002f,
17574SQ_PERF_SEL_INSTS_SMEM_NORM = 0x00000030,
17575SQ_PERF_SEL_INSTS_SENDMSG = 0x00000031,
17576SQ_PERF_SEL_INSTS_VALU = 0x00000032,
17577SQ_PERF_SEL_INSTS_VALU_TRANS32 = 0x00000033,
17578SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 0x00000034,
17579SQ_PERF_SEL_INSTS_TEX = 0x00000035,
17580SQ_PERF_SEL_INSTS_TEX_LOAD = 0x00000036,
17581SQ_PERF_SEL_INSTS_TEX_STORE = 0x00000037,
17582SQ_PERF_SEL_INSTS_DELAY_ALU = 0x00000038,
17583SQ_PERF_SEL_INSTS_INTERNAL = 0x00000039,
17584SQ_PERF_SEL_INSTS_VEC32 = 0x0000003a,
17585SQ_PERF_SEL_INSTS_VEC32_FLAT = 0x0000003b,
17586SQ_PERF_SEL_INSTS_VEC32_LDS = 0x0000003c,
17587SQ_PERF_SEL_INSTS_VEC32_VALU = 0x0000003d,
17588SQ_PERF_SEL_VEC32_INSTS_EXP = 0x0000003e,
17589SQ_PERF_SEL_INSTS_VEC32_VALU_TRANS32 = 0x0000003f,
17590SQ_PERF_SEL_INSTS_VEC32_VALU_NO_COEXEC = 0x00000040,
17591SQ_PERF_SEL_INSTS_VEC32_TEX = 0x00000041,
17592SQ_PERF_SEL_INSTS_VEC32_TEX_LOAD = 0x00000042,
17593SQ_PERF_SEL_INSTS_VEC32_TEX_STORE = 0x00000043,
17594SQ_PERF_SEL_ITEM_CYCLES_VALU = 0x00000044,
17595SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 0x00000045,
17596SQ_PERF_SEL_WAVE32_INSTS = 0x00000046,
17597SQ_PERF_SEL_WAVE64_INSTS = 0x00000047,
17598SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 0x00000048,
17599SQ_PERF_SEL_WAVE64_HALF_SKIP = 0x00000049,
17600SQ_PERF_SEL_INST_LEVEL_EXP = 0x0000004a,
17601SQ_PERF_SEL_INST_LEVEL_LDS = 0x0000004b,
17602SQ_PERF_SEL_INST_LEVEL_SMEM = 0x0000004c,
17603SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 0x0000004d,
17604SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 0x0000004e,
17605SQ_PERF_SEL_IFETCH_REQS = 0x0000004f,
17606SQ_PERF_SEL_IFETCH_LEVEL = 0x00000050,
17607SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 0x00000051,
17608SQ_PERF_SEL_VALU_SGATHER_STALL = 0x00000052,
17609SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 0x00000053,
17610SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 0x00000054,
17611SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 0x00000055,
17612SQ_PERF_SEL_SALU_SGATHER_STALL = 0x00000056,
17613SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 0x00000057,
17614SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 0x00000058,
17615SQ_PERF_SEL_INST_ISSUE_SMEM_STALL = 0x00000059,
17616SQ_PERF_SEL_INST_ISSUE_ALL_STALL = 0x0000005a,
17617SQ_PERF_SEL_INST_ISSUE_VALU_STALL = 0x0000005b,
17618SQ_PERF_SEL_INST_ISSUE_SALU_STALL = 0x0000005c,
17619SQ_PERF_SEL_INST_ISSUE_TEX_STALL = 0x0000005d,
17620SQ_PERF_SEL_INST_ISSUE_LDS_STALL = 0x0000005e,
17621SQ_PERF_SEL_INST_ISSUE_EXP_STALL = 0x00000060,
17622SQ_PERF_SEL_INST_WAITCNT_STALL = 0x00000061,
17623SQ_PERF_SEL_INST_BARRIER_STALL = 0x00000062,
17624SQ_PERF_SEL_INST_CYCLES_VALU = 0x00000063,
17625SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 0x00000064,
17626SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 0x00000065,
17627SQ_PERF_SEL_INST_CYCLES_VMEM = 0x00000066,
17628SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 0x00000067,
17629SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 0x00000068,
17630SQ_PERF_SEL_INST_CYCLES_LDS = 0x00000069,
17631SQ_PERF_SEL_INST_CYCLES_TEX = 0x0000006a,
17632SQ_PERF_SEL_INST_CYCLES_FLAT = 0x0000006b,
17633SQ_PERF_SEL_INST_CYCLES_EXP = 0x0000006c,
17634SQ_PERF_SEL_VALU_STARVE = 0x0000006d,
17635SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 0x0000006e,
17636SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 0x0000006f,
17637SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x00000070,
17638SQ_PERF_SEL_VMEM_BUS_ACTIVE = 0x00000071,
17639SQ_PERF_SEL_VMEM_BUS_STALL = 0x00000072,
17640SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 0x00000073,
17641SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 0x00000074,
17642SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 0x00000075,
17643SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 0x00000076,
17644SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 0x00000077,
17645SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 0x00000078,
17646SQ_PERF_SEL_SALU_PIPE_STALL = 0x00000079,
17647SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 0x0000007a,
17648SQ_PERF_SEL_MSG_BUS_BUSY = 0x0000007b,
17649SQ_PERF_SEL_EXP_REQ_BUS_STALL = 0x0000007c,
17650SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 0x0000007d,
17651SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 0x0000007e,
17652SQ_PERF_SEL_EXP_BUS0_BUSY = 0x0000007f,
17653SQ_PERF_SEL_EXP_BUS1_BUSY = 0x00000080,
17654SQ_PERF_SEL_INST_CACHE_REQ_STALL = 0x00000081,
17655SQ_PERF_SEL_USER0 = 0x00000082,
17656SQ_PERF_SEL_USER1 = 0x00000083,
17657SQ_PERF_SEL_USER2 = 0x00000084,
17658SQ_PERF_SEL_USER3 = 0x00000085,
17659SQ_PERF_SEL_USER4 = 0x00000086,
17660SQ_PERF_SEL_USER5 = 0x00000087,
17661SQ_PERF_SEL_USER6 = 0x00000088,
17662SQ_PERF_SEL_USER7 = 0x00000089,
17663SQ_PERF_SEL_USER8 = 0x0000008a,
17664SQ_PERF_SEL_USER9 = 0x0000008b,
17665SQ_PERF_SEL_USER10 = 0x0000008c,
17666SQ_PERF_SEL_USER11 = 0x0000008d,
17667SQ_PERF_SEL_USER12 = 0x0000008e,
17668SQ_PERF_SEL_USER13 = 0x0000008f,
17669SQ_PERF_SEL_USER14 = 0x00000090,
17670SQ_PERF_SEL_USER15 = 0x00000091,
17671SQ_PERF_SEL_USER_LEVEL0 = 0x00000092,
17672SQ_PERF_SEL_USER_LEVEL1 = 0x00000093,
17673SQ_PERF_SEL_USER_LEVEL2 = 0x00000094,
17674SQ_PERF_SEL_USER_LEVEL3 = 0x00000095,
17675SQ_PERF_SEL_USER_LEVEL4 = 0x00000096,
17676SQ_PERF_SEL_USER_LEVEL5 = 0x00000097,
17677SQ_PERF_SEL_USER_LEVEL6 = 0x00000098,
17678SQ_PERF_SEL_USER_LEVEL7 = 0x00000099,
17679SQ_PERF_SEL_USER_LEVEL8 = 0x0000009a,
17680SQ_PERF_SEL_USER_LEVEL9 = 0x0000009b,
17681SQ_PERF_SEL_USER_LEVEL10 = 0x0000009c,
17682SQ_PERF_SEL_USER_LEVEL11 = 0x0000009d,
17683SQ_PERF_SEL_USER_LEVEL12 = 0x0000009e,
17684SQ_PERF_SEL_USER_LEVEL13 = 0x0000009f,
17685SQ_PERF_SEL_USER_LEVEL14 = 0x000000a0,
17686SQ_PERF_SEL_USER_LEVEL15 = 0x000000a1,
17687SQ_PERF_SEL_VALU_RETURN_SDST = 0x000000a2,
17688SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 0x000000a3,
17689SQ_PERF_SEL_INSTS_VALU_TRANS = 0x000000a4,
17690SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 0x000000a5,
17691SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 0x000000a6,
17692SQ_PERF_SEL_INSTS_VEC32_LDS_PARAM_LOAD = 0x000000a7,
17693SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 0x000000a8,
17694SQ_PERF_SEL_INSTS_VALU_VINTERP = 0x000000a9,
17695SQ_PERF_SEL_INSTS_VEC32_VALU_VINTERP = 0x000000aa,
17696SQ_PERF_SEL_OVERFLOW_PREV = 0x000000ab,
17697SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 0x000000ac,
17698SQ_PERF_SEL_INSTS_VALU_1_PASS = 0x000000ad,
17699SQ_PERF_SEL_INSTS_VALU_2_PASS = 0x000000ae,
17700SQ_PERF_SEL_INSTS_VALU_4_PASS = 0x000000af,
17701SQ_PERF_SEL_INSTS_VALU_DP = 0x000000b0,
17702SQ_PERF_SEL_SP_CONST_CYCLES = 0x000000b1,
17703SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 0x000000b2,
17704SQ_PERF_SEL_ITEMS_VALU = 0x000000b3,
17705SQ_PERF_SEL_ITEMS_MAX_VALU = 0x000000b4,
17706SQ_PERF_SEL_ITEM_CYCLES_VMEM = 0x000000b5,
17707SQ_PERF_SEL_INSTS_DELAY_ALU_COISSUE = 0x000000b6,
17708SQ_PERF_SEL_INSTS_FLAT_LOAD = 0x000000b7,
17709SQ_PERF_SEL_INSTS_FLAT_STORE = 0x000000b8,
17710SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_16BIT = 0x000000b9,
17711SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64_32BIT = 0x000000ba,
17712SQ_PERF_SEL_INSTS_NON_VALU_EXEC_SKIPPED = 0x000000bb,
17713SQ_PERF_SEL_INSTS_BARRIER_LOCK = 0x000000bc,
17714SQ_PERF_SEL_INSTS_WAKEUP = 0x000000bd,
17715SQ_PERF_SEL_IS_CACHE_REQ = 0x000000be,
17716SQ_PERF_SEL_INSTS_SALU_PS = 0x000000bf,
17717SQ_PERF_SEL_INSTS_SALU_GS = 0x000000c0,
17718SQ_PERF_SEL_INSTS_SALU_HS = 0x000000c1,
17719SQ_PERF_SEL_INSTS_SALU_CS = 0x000000c2,
17720SQ_PERF_SEL_INSTS_SMEM_PS = 0x000000c3,
17721SQ_PERF_SEL_INSTS_SMEM_GS = 0x000000c4,
17722SQ_PERF_SEL_INSTS_SMEM_HS = 0x000000c5,
17723SQ_PERF_SEL_INSTS_SMEM_CS = 0x000000c6,
17724SQ_PERF_SEL_INSTS_VEC32_TEX_PS = 0x000000c7,
17725SQ_PERF_SEL_INSTS_VEC32_TEX_GS = 0x000000c8,
17726SQ_PERF_SEL_INSTS_VEC32_TEX_HS = 0x000000c9,
17727SQ_PERF_SEL_INSTS_VEC32_TEX_CS = 0x000000ca,
17728SQ_PERF_SEL_INSTS_VEC32_VALU_PS = 0x000000cb,
17729SQ_PERF_SEL_INSTS_VEC32_VALU_GS = 0x000000cc,
17730SQ_PERF_SEL_INSTS_VEC32_VALU_HS = 0x000000cd,
17731SQ_PERF_SEL_INSTS_VEC32_VALU_CS = 0x000000ce,
17732SQ_PERF_SEL_WAIT_CNT_SAMPLE = 0x000000cf,
17733SQ_PERF_SEL_WAIT_CNT_KM = 0x000000d1,
17734SQ_PERF_SEL_WAIT_CNT_DS = 0x000000d2,
17735SQ_PERF_SEL_WAIT_CNT_EXP = 0x000000d3,
17736SQ_PERF_SEL_INSTS_SALU_FLOAT = 0x000000d4,
17737SQ_PERF_SEL_INSTS_VGPR_ALLOC = 0x000000d5,
17738SQ_PERF_SEL_INSTS_VGPR_ALLOC_FAIL = 0x000000d6,
17739SQ_PERF_SEL_INSTS_LOCK = 0x000000d7,
17740SQ_PERF_SEL_INSTS_VALU_COISSUE = 0x000000d8,
17741SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_LOAD = 0x000000d9,
17742SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS_STORE = 0x000000da,
17743SQ_PERF_SEL_IS_CACHE_MISS = 0x000000db,
17744SQ_PERF_SEL_IS_CACHE_DUP_MISS = 0x000000dc,
17745SQ_PERF_SEL_INST_CYCLES_VMEM_ATOMIC = 0x000000dd,
17746SQ_PERF_SEL_INSTS_TEX_BLOCK_LOAD = 0x000000de,
17747SQ_PERF_SEL_INSTS_TEX_SAMPLE = 0x000000e0,
17748SQ_PERF_SEL_INSTS_TEX_ATOMIC_RTN = 0x000000e1,
17749SQ_PERF_SEL_INSTS_TEX_BLOCK_STORE = 0x000000e2,
17750SQ_PERF_SEL_INSTS_TEX_ATOMIC_NORTN = 0x000000e3,
17751SQ_PERF_SEL_INSTS_GLOBAL_SCRATCH = 0x000000e4,
17752SQ_PERF_SEL_INSTS_WMMA_LOAD = 0x000000e5,
17753SQ_PERF_SEL_INSTS_FLAT_ATOMIC = 0x000000e6,
17754SQ_PERF_SEL_INSTS_EXP_MRT = 0x000000e7,
17755SQ_PERF_SEL_INSTS_EXP_Z = 0x000000e8,
17756SQ_PERF_SEL_INSTS_VEC32_VALU_WMMA = 0x000000e9,
17757SQ_PERF_SEL_INSTS_VEC32_LDS_LOAD = 0x000000ea,
17758SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_RTN = 0x000000eb,
17759SQ_PERF_SEL_INSTS_VEC32_LDS_STORE = 0x000000ec,
17760SQ_PERF_SEL_INSTS_VEC32_LDS_ATOMIC_NORTN = 0x000000ed,
17761SQ_PERF_SEL_INSTS_VEC32_LDS_OTHER = 0x000000ef,
17762SQ_PERF_SEL_INSTS_VEC32_TEX_SAMPLE = 0x000000f1,
17763SQ_PERF_SEL_INSTS_VEC32_TEX_ATOMIC = 0x000000f2,
17764SQ_PERF_SEL_INSTS_VEC32_FLAT_LOAD = 0x000000f3,
17765SQ_PERF_SEL_INSTS_VEC32_FLAT_STORE = 0x000000f4,
17766SQ_PERF_SEL_INSTS_VEC32_FLAT_ATOMIC = 0x000000f5,
17767SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH = 0x000000f6,
17768SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_LOAD = 0x000000f7,
17769SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_STORE = 0x000000f8,
17770SQ_PERF_SEL_INSTS_VEC32_GLOBAL_SCRATCH_ATOMIC = 0x000000f9,
17771SQ_PERF_SEL_INSTS_VEC32_LEVEL_LDS = 0x000000fa,
17772SQ_PERF_SEL_DUMMY_END = 0x000000fb,
17773SQ_PERF_SEL_DUMMY_LAST = 0x0000011f,
17774SQC_PERF_SEL_LDS_BANK_CONFLICT = 0x00000120,
17775SQC_PERF_SEL_LDS_ADDR_CONFLICT = 0x00000121,
17776SQC_PERF_SEL_LDS_UNALIGNED_STALL = 0x00000122,
17777SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 0x00000123,
17778SQC_PERF_SEL_LDS_ATOMIC_RETURN = 0x00000124,
17779SQC_PERF_SEL_LDS_IDX_ACTIVE = 0x00000125,
17780SQC_PERF_SEL_LDS_ADDR_STALL = 0x00000126,
17781SQC_PERF_SEL_LDS_ADDR_ACTIVE = 0x00000127,
17782SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 0x00000128,
17783SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 0x00000129,
17784SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 0x0000012a,
17785SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 0x0000012b,
17786SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0x0000012c,
17787SQC_PERF_SEL_ICACHE_REQ = 0x0000012d,
17788SQC_PERF_SEL_ICACHE_HITS = 0x0000012e,
17789SQC_PERF_SEL_ICACHE_MISSES = 0x0000012f,
17790SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0x00000130,
17791SQC_PERF_SEL_ICACHE_INVAL_INST = 0x00000131,
17792SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0x00000132,
17793SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0x00000133,
17794SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0x00000134,
17795SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0x00000135,
17796SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0x00000136,
17797SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0x00000137,
17798SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0x00000138,
17799SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0x00000139,
17800SQC_PERF_SEL_TC_REQ = 0x0000013a,
17801SQC_PERF_SEL_TC_INST_REQ = 0x0000013b,
17802SQC_PERF_SEL_TC_DATA_READ_REQ = 0x0000013c,
17803SQC_PERF_SEL_TC_STALL = 0x0000013d,
17804SQC_PERF_SEL_TC_STARVE = 0x0000013e,
17805SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000013f,
17806SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000140,
17807SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0x00000141,
17808SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000142,
17809SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000143,
17810SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0x00000144,
17811SQC_PERF_SEL_DCACHE_REQ = 0x00000145,
17812SQC_PERF_SEL_DCACHE_HITS = 0x00000146,
17813SQC_PERF_SEL_DCACHE_MISSES = 0x00000147,
17814SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0x00000148,
17815SQC_PERF_SEL_DCACHE_INVAL_INST = 0x00000149,
17816SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0x0000014a,
17817SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0x0000014b,
17818SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000014c,
17819SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x0000014d,
17820SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0x0000014e,
17821SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x0000014f,
17822SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0x00000150,
17823SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000151,
17824SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0x00000152,
17825SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0x00000153,
17826SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0x00000154,
17827SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0x00000155,
17828SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0x00000156,
17829SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0x00000157,
17830SQC_PERF_SEL_SQ_DCACHE_REQS = 0x00000158,
17831SQC_PERF_SEL_DCACHE_FLAT_REQ = 0x00000159,
17832SQC_PERF_SEL_TD_VGPR_BUSY = 0x0000015a,
17833SQC_PERF_SEL_LDS_VGPR_BUSY = 0x0000015b,
17834SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 0x0000015c,
17835SQC_PERF_SEL_ICACHE_GCR = 0x0000015d,
17836SQC_PERF_SEL_ICACHE_GCR_HITS = 0x0000015e,
17837SQC_PERF_SEL_DCACHE_GCR = 0x0000015f,
17838SQC_PERF_SEL_DCACHE_GCR_HITS = 0x00000160,
17839SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 0x00000161,
17840SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 0x00000162,
17841SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 0x00000163,
17842SQC_PERF_SEL_ICACHE_PREFETCH_REQ_CACHELINES = 0x00000164,
17843SQC_PERF_SEL_DCACHE_PREFETCH_REQ_CACHELINES = 0x00000165,
17844SQC_PERF_SEL_ICACHE_PREFETCH_MISSES = 0x00000166,
17845SQC_PERF_SEL_DCACHE_PREFETCH_MISSES = 0x00000167,
17846SQC_PERF_SEL_LDS_BANKCONF_LOAD_CNT = 0x00000168,
17847SQC_PERF_SEL_LDS_BANKCONF_STORE_CNT = 0x00000169,
17848SQC_PERF_SEL_LDS_BANKCONF_ATOMIC_CNT = 0x0000016a,
17849SQC_PERF_SEL_LDS_ACTIVE_LOAD_CNT = 0x0000016b,
17850SQC_PERF_SEL_LDS_ACTIVE_STORE_CNT = 0x0000016c,
17851SQC_PERF_SEL_LDS_ACTIVE_ATOMIC_CNT = 0x0000016d,
17852SQC_PERF_SEL_LDS_STORE_DWORDS = 0x0000016e,
17853SQC_PERF_SEL_LDS_LOAD_DWORDS = 0x0000016f,
17854SQC_PERF_SEL_LDS_ATOMIC_DWORDS = 0x00000170,
17855SQC_PERF_SEL_LDS_LDS_EXECUTION_STALL = 0x00000171,
17856SQC_PERF_SEL_DUMMY_LAST = 0x00000172,
17857SP_PERF_SEL_DST_BUF_ALLOC_STALL = 0x000001c0,
17858SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 0x000001c1,
17859SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 0x000001c2,
17860SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 0x000001c3,
17861SP_PERF_SEL_DST_BUF_ODD_DIRTY = 0x000001c4,
17862SP_PERF_SEL_SRC_CACHE_HIT_B0 = 0x000001c5,
17863SP_PERF_SEL_SRC_CACHE_HIT_B1 = 0x000001c6,
17864SP_PERF_SEL_SRC_CACHE_HIT_B2 = 0x000001c7,
17865SP_PERF_SEL_SRC_CACHE_HIT_B3 = 0x000001c8,
17866SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 0x000001c9,
17867SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 0x000001ca,
17868SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 0x000001cb,
17869SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 0x000001cc,
17870SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 0x000001cd,
17871SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 0x000001ce,
17872SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 0x000001cf,
17873SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 0x000001d0,
17874SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 0x000001d1,
17875SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 0x000001d2,
17876SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 0x000001d3,
17877SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 0x000001d4,
17878SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 0x000001d5,
17879SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 0x000001d6,
17880SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 0x000001d7,
17881SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 0x000001d8,
17882SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 0x000001d9,
17883SP_PERF_SEL_VALU_OPERAND = 0x000001da,
17884SP_PERF_SEL_VALU_VGPR_OPERAND = 0x000001db,
17885SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 0x000001dc,
17886SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 0x000001dd,
17887SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 0x000001de,
17888SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 0x000001df,
17889SP_PERF_SEL_VALU_STALL = 0x000001e0,
17890SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 0x000001e1,
17891SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 0x000001e2,
17892SP_PERF_SEL_VALU_STALL_VDST_FWD = 0x000001e3,
17893SP_PERF_SEL_VALU_STALL_SDST_FWD = 0x000001e4,
17894SP_PERF_SEL_VALU_STALL_DST_STALL = 0x000001e5,
17895SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 0x000001e6,
17896SP_PERF_SEL_VGPR_VMEM_RD = 0x000001e7,
17897SP_PERF_SEL_VGPR_EXP_RD = 0x000001e8,
17898SP_PERF_SEL_VGPR_SPI_WR = 0x000001e9,
17899SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 0x000001ea,
17900SP_PERF_SEL_VGPR_WR = 0x000001eb,
17901SP_PERF_SEL_VGPR_RD = 0x000001ec,
17902SP_PERF_SEL_VGPR_WR_KILL = 0x000001ed,
17903SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_EXP = 0x000001ee,
17904SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_LDS = 0x000001ef,
17905SP_PERF_SEL_VALU_VGPR_RD_CONFLICT_TEX = 0x000001f0,
17906SP_PERF_SEL_DUMMY_LAST = 0x000001f1,
17907SQ_PERF_SEL_NONE2 = 0x000001ff,
17908} SQ_PERF_SEL;
17909
17910/*
17911 * SQ_ROUND_MODE enum
17912 */
17913
17914typedef enum SQ_ROUND_MODE {
17915SQ_ROUND_NEAREST_EVEN = 0x00000000,
17916SQ_ROUND_PLUS_INFINITY = 0x00000001,
17917SQ_ROUND_MINUS_INFINITY = 0x00000002,
17918SQ_ROUND_TO_ZERO = 0x00000003,
17919} SQ_ROUND_MODE;
17920
17921/*
17922 * SQ_RSRC_BUF_TYPE enum
17923 */
17924
17925typedef enum SQ_RSRC_BUF_TYPE {
17926SQ_RSRC_BUF = 0x00000000,
17927SQ_RSRC_BUF_RSVD_1 = 0x00000001,
17928SQ_RSRC_BUF_RSVD_2 = 0x00000002,
17929SQ_RSRC_BUF_RSVD_3 = 0x00000003,
17930} SQ_RSRC_BUF_TYPE;
17931
17932/*
17933 * SQ_RSRC_FLAT_TYPE enum
17934 */
17935
17936typedef enum SQ_RSRC_FLAT_TYPE {
17937SQ_RSRC_FLAT_RSVD_0 = 0x00000000,
17938SQ_RSRC_FLAT = 0x00000001,
17939SQ_RSRC_FLAT_RSVD_2 = 0x00000002,
17940SQ_RSRC_FLAT_RSVD_3 = 0x00000003,
17941} SQ_RSRC_FLAT_TYPE;
17942
17943/*
17944 * SQ_RSRC_IMG_TYPE enum
17945 */
17946
17947typedef enum SQ_RSRC_IMG_TYPE {
17948SQ_RSRC_IMG_RSVD_0 = 0x00000000,
17949SQ_RSRC_IMG_RSVD_1 = 0x00000001,
17950SQ_RSRC_IMG_RSVD_2 = 0x00000002,
17951SQ_RSRC_IMG_RSVD_3 = 0x00000003,
17952SQ_RSRC_IMG_RSVD_4 = 0x00000004,
17953SQ_RSRC_IMG_RSVD_5 = 0x00000005,
17954SQ_RSRC_IMG_RSVD_6 = 0x00000006,
17955SQ_RSRC_IMG_RSVD_7 = 0x00000007,
17956SQ_RSRC_IMG_1D = 0x00000008,
17957SQ_RSRC_IMG_2D = 0x00000009,
17958SQ_RSRC_IMG_3D = 0x0000000a,
17959SQ_RSRC_IMG_CUBE = 0x0000000b,
17960SQ_RSRC_IMG_1D_ARRAY = 0x0000000c,
17961SQ_RSRC_IMG_2D_ARRAY = 0x0000000d,
17962SQ_RSRC_IMG_2D_MSAA = 0x0000000e,
17963SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f,
17964} SQ_RSRC_IMG_TYPE;
17965
17966/*
17967 * SQ_SEL_XYZW01 enum
17968 */
17969
17970typedef enum SQ_SEL_XYZW01 {
17971SQ_SEL_0 = 0x00000000,
17972SQ_SEL_1 = 0x00000001,
17973SQ_SEL_N_BC_1 = 0x00000002,
17974SQ_SEL_RESERVED_1 = 0x00000003,
17975SQ_SEL_X = 0x00000004,
17976SQ_SEL_Y = 0x00000005,
17977SQ_SEL_Z = 0x00000006,
17978SQ_SEL_W = 0x00000007,
17979} SQ_SEL_XYZW01;
17980
17981/*
17982 * SQ_TEX_ANISO_RATIO enum
17983 */
17984
17985typedef enum SQ_TEX_ANISO_RATIO {
17986SQ_TEX_ANISO_RATIO_1 = 0x00000000,
17987SQ_TEX_ANISO_RATIO_2 = 0x00000001,
17988SQ_TEX_ANISO_RATIO_4 = 0x00000002,
17989SQ_TEX_ANISO_RATIO_8 = 0x00000003,
17990SQ_TEX_ANISO_RATIO_16 = 0x00000004,
17991} SQ_TEX_ANISO_RATIO;
17992
17993/*
17994 * SQ_TEX_BORDER_COLOR enum
17995 */
17996
17997typedef enum SQ_TEX_BORDER_COLOR {
17998SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000,
17999SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001,
18000SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002,
18001SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003,
18002} SQ_TEX_BORDER_COLOR;
18003
18004/*
18005 * SQ_TEX_CLAMP enum
18006 */
18007
18008typedef enum SQ_TEX_CLAMP {
18009SQ_TEX_WRAP = 0x00000000,
18010SQ_TEX_MIRROR = 0x00000001,
18011SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002,
18012SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003,
18013SQ_TEX_CLAMP_HALF_BORDER = 0x00000004,
18014SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005,
18015SQ_TEX_CLAMP_BORDER = 0x00000006,
18016SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007,
18017} SQ_TEX_CLAMP;
18018
18019/*
18020 * SQ_TEX_DEPTH_COMPARE enum
18021 */
18022
18023typedef enum SQ_TEX_DEPTH_COMPARE {
18024SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000,
18025SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001,
18026SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002,
18027SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003,
18028SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004,
18029SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005,
18030SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006,
18031SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007,
18032} SQ_TEX_DEPTH_COMPARE;
18033
18034/*
18035 * SQ_TEX_MIP_FILTER enum
18036 */
18037
18038typedef enum SQ_TEX_MIP_FILTER {
18039SQ_TEX_MIP_FILTER_NONE = 0x00000000,
18040SQ_TEX_MIP_FILTER_POINT = 0x00000001,
18041SQ_TEX_MIP_FILTER_LINEAR = 0x00000002,
18042SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x00000003,
18043} SQ_TEX_MIP_FILTER;
18044
18045/*
18046 * SQ_TEX_XY_FILTER enum
18047 */
18048
18049typedef enum SQ_TEX_XY_FILTER {
18050SQ_TEX_XY_FILTER_POINT = 0x00000000,
18051SQ_TEX_XY_FILTER_BILINEAR = 0x00000001,
18052SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002,
18053SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003,
18054} SQ_TEX_XY_FILTER;
18055
18056/*
18057 * SQ_TEX_Z_FILTER enum
18058 */
18059
18060typedef enum SQ_TEX_Z_FILTER {
18061SQ_TEX_Z_FILTER_NONE = 0x00000000,
18062SQ_TEX_Z_FILTER_POINT = 0x00000001,
18063SQ_TEX_Z_FILTER_LINEAR = 0x00000002,
18064} SQ_TEX_Z_FILTER;
18065
18066/*
18067 * SQ_WATCH_MODES enum
18068 */
18069
18070typedef enum SQ_WATCH_MODES {
18071SQ_WATCH_MODE_READ = 0x00000000,
18072SQ_WATCH_MODE_NONREAD = 0x00000001,
18073SQ_WATCH_MODE_ATOMIC = 0x00000002,
18074SQ_WATCH_MODE_ALL = 0x00000003,
18075} SQ_WATCH_MODES;
18076
18077/*
18078 * SQ_WAVE_FWD_PROG_INTERVAL enum
18079 */
18080
18081typedef enum SQ_WAVE_FWD_PROG_INTERVAL {
18082SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0x00000000,
18083SQ_WAVE_FWD_PROG_INTERVAL_256 = 0x00000001,
18084SQ_WAVE_FWD_PROG_INTERVAL_1024 = 0x00000002,
18085SQ_WAVE_FWD_PROG_INTERVAL_4096 = 0x00000003,
18086} SQ_WAVE_FWD_PROG_INTERVAL;
18087
18088/*
18089 * SQ_WAVE_SCHED_MODES enum
18090 */
18091
18092typedef enum SQ_WAVE_SCHED_MODES {
18093SQ_WAVE_SCHED_MODE_NORMAL = 0x00000000,
18094SQ_WAVE_SCHED_MODE_EXPERT = 0x00000001,
18095SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST_VM_VSRC = 0x00000002,
18096} SQ_WAVE_SCHED_MODES;
18097
18098/*
18099 * SQ_WAVE_TYPE enum
18100 */
18101
18102typedef enum SQ_WAVE_TYPE {
18103SQ_WAVE_TYPE_PS = 0x00000000,
18104SQ_WAVE_TYPE_RSVD0 = 0x00000001,
18105SQ_WAVE_TYPE_GS = 0x00000002,
18106SQ_WAVE_TYPE_RSVD1 = 0x00000003,
18107SQ_WAVE_TYPE_HS = 0x00000004,
18108SQ_WAVE_TYPE_RSVD2 = 0x00000005,
18109SQ_WAVE_TYPE_CS = 0x00000006,
18110SQ_WAVE_TYPE_PS1 = 0x00000007,
18111SQ_WAVE_TYPE_PS2 = 0x00000008,
18112SQ_WAVE_TYPE_PS3 = 0x00000009,
18113} SQ_WAVE_TYPE;
18114
18115/*
18116 * SQ_WAVE_TYPE value
18117 */
18118
18119#define SQ_WAVE_TYPE_PS0 0x00000000
18120
18121/*
18122 * SQ_SEG value
18123 */
18124
18125#define SQ_FLAT 0x00000000
18126#define SQ_SCRATCH 0x00000001
18127#define SQ_GLOBAL 0x00000002
18128
18129/*
18130 * SQIND_PARTITIONS value
18131 */
18132
18133#define SQIND_GLOBAL_REGS_OFFSET 0x00000000
18134#define SQIND_GLOBAL_REGS_SIZE 0x00000008
18135#define SQIND_LOCAL_REGS_OFFSET 0x00000008
18136#define SQIND_LOCAL_REGS_SIZE 0x00000008
18137#define SQIND_WAVE_HW_REGS_OFFSET 0x00000100
18138#define SQIND_WAVE_HW_REGS_SIZE 0x00000040
18139#define SQIND_WAVE_HOST_REGS_OFFSET 0x00000140
18140#define SQIND_WAVE_HOST_REGS_SIZE 0x000000c0
18141#define SQIND_WAVE_SGPRS_OFFSET 0x00000200
18142#define SQIND_WAVE_SGPRS_SIZE 0x00000200
18143#define SQIND_WAVE_VGPRS_OFFSET 0x00000400
18144#define SQIND_WAVE_VGPRS_SIZE 0x00000400
18145
18146/*
18147 * SQ_GFXDEC value
18148 */
18149
18150#define SQ_GFXDEC_BEGIN 0x0000a000
18151#define SQ_GFXDEC_END 0x0000c000
18152#define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a
18153
18154/*
18155 * SQDEC value
18156 */
18157
18158#define SQDEC_BEGIN 0x00002300
18159#define SQDEC_END 0x000023ff
18160
18161/*
18162 * PFVF_SQDEC value
18163 */
18164
18165#define PFVF_SQDEC_BEGIN 0x0000a9e0
18166#define PFVF_SQDEC_END 0x0000a9ff
18167
18168/*
18169 * SQPERFSDEC value
18170 */
18171
18172#define SQPERFSDEC_BEGIN 0x0000d9c0
18173#define SQPERFSDEC_END 0x0000da40
18174
18175/*
18176 * SQPERFDDEC value
18177 */
18178
18179#define SQPERFDDEC_BEGIN 0x0000d1c0
18180#define SQPERFDDEC_END 0x0000d240
18181
18182/*
18183 * SQGFXUDEC value
18184 */
18185
18186#define SQGFXUDEC_BEGIN 0x0000c330
18187#define SQGFXUDEC_END 0x0000c380
18188
18189/*
18190 * SQPWRDEC value
18191 */
18192
18193#define SQPWRDEC_BEGIN 0x0000f08c
18194#define SQPWRDEC_END 0x0000f094
18195
18196/*
18197 * SQ_DISPATCHER value
18198 */
18199
18200#define SQ_DISPATCHER_GFX_MIN 0x00000010
18201#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008
18202
18203/*
18204 * SQ_MAX value
18205 */
18206
18207#define SQ_MAX_PGM_SGPRS 0x00000068
18208#define SQ_MAX_PGM_VGPRS 0x00000100
18209
18210/*
18211 * SQ_EXCP_BITS value
18212 */
18213
18214#define SQ_EX_EXCP_VALU_BASE 0x00000000
18215#define SQ_EX_EXCP_VALU_SIZE 0x00000007
18216#define SQ_EX_EXCP_ALU_INVALID 0x00000000
18217#define SQ_EX_EXCP_ALU_INPUT_DENORM 0x00000001
18218#define SQ_EX_EXCP_ALU_FLOAT_DIV0 0x00000002
18219#define SQ_EX_EXCP_ALU_OVERFLOW 0x00000003
18220#define SQ_EX_EXCP_ALU_UNDERFLOW 0x00000004
18221#define SQ_EX_EXCP_ALU_INEXACT 0x00000005
18222#define SQ_EX_EXCP_ALU_INT_DIV0 0x00000006
18223#define SQ_EX_EXCP_ADDR_WATCH 0x00000007
18224
18225/*
18226 * HW_INSERTED_INST_ID value
18227 */
18228
18229#define INST_ID_PRIV_START 0x80000000
18230#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0
18231#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1
18232#define INST_ID_HW_TRAP 0xfffffff2
18233#define INST_ID_KILL_SEQ 0xfffffff3
18234#define INST_ID_SPI_WREXEC 0xfffffff4
18235#define INST_ID_HW_TRAP_GET_TBA 0xfffffff5
18236#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe
18237
18238/*
18239 * SIMM16_WAITCNT_PARTITIONS value
18240 */
18241
18242#define SIMM16_WAITCNT_EXP_CNT_START 0x00000000
18243#define SIMM16_WAITCNT_EXP_CNT_SIZE 0x00000003
18244#define SIMM16_WAITCNT_LGKM_CNT_START 0x00000004
18245#define SIMM16_WAITCNT_LGKM_CNT_SIZE 0x00000006
18246#define SIMM16_WAITCNT_VM_CNT_START 0x0000000a
18247#define SIMM16_WAITCNT_VM_CNT_SIZE 0x00000006
18248#define SIMM16_WAITCNT_DEPCTR_SA_SDST_START 0x00000000
18249#define SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE 0x00000001
18250#define SIMM16_WAITCNT_DEPCTR_VA_VCC_START 0x00000001
18251#define SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE 0x00000001
18252#define SIMM16_WAITCNT_DEPCTR_VM_VSRC_START 0x00000002
18253#define SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE 0x00000003
18254#define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START 0x00000007
18255#define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE 0x00000001
18256#define SIMM16_WAITCNT_DEPCTR_VA_SSRC_START 0x00000008
18257#define SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE 0x00000001
18258#define SIMM16_WAITCNT_DEPCTR_VA_SDST_START 0x00000009
18259#define SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE 0x00000003
18260#define SIMM16_WAITCNT_DEPCTR_VA_VDST_START 0x0000000c
18261#define SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE 0x00000004
18262
18263/*
18264 * SIMM16_WAIT_EVENT_PARTITIONS value
18265 */
18266
18267#define SIMM16_WAIT_EVENT_EXP_RDY_START 0x00000000
18268#define SIMM16_WAIT_EVENT_EXP_RDY_SIZE 0x00000001
18269
18270/*
18271 * SQ_WAVE_IB_DEP_COUNTER_SIZES value
18272 */
18273
18274#define SQ_WAVE_IB_DEP_SA_SDST_SIZE 0x00000004
18275#define SQ_WAVE_IB_DEP_SA_EXEC_SIZE 0x00000002
18276#define SQ_WAVE_IB_DEP_SA_M0_SIZE 0x00000001
18277#define SQ_WAVE_IB_DEP_VM_VSRC_SIZE 0x00000004
18278#define SQ_WAVE_IB_DEP_HOLD_CNT_SIZE 0x00000001
18279#define SQ_WAVE_IB_DEP_VA_SSRC_SIZE 0x00000003
18280#define SQ_WAVE_IB_DEP_VA_SDST_SIZE 0x00000004
18281#define SQ_WAVE_IB_DEP_VA_VCC_SIZE 0x00000003
18282#define SQ_WAVE_IB_DEP_VA_EXEC_SIZE 0x00000002
18283#define SQ_WAVE_IB_DEP_VA_VDST_SIZE 0x00000005
18284#define SQ_WAVE_IB_DEP_LDS_DIR_SIZE 0x00000003
18285
18286/*
18287 * SQ_ARB_STATE value
18288 */
18289
18290#define SQ_ARB_STATE_ISSUED_BRMSG 0x00000000
18291#define SQ_ARB_STATE_ISSUED_EXPORT 0x00000001
18292#define SQ_ARB_STATE_ISSUED_LDS_DIRECT 0x00000002
18293#define SQ_ARB_STATE_ISSUED_LDS 0x00000003
18294#define SQ_ARB_STATE_ISSUED_TEX 0x00000004
18295#define SQ_ARB_STATE_ISSUED_SCALAR 0x00000005
18296#define SQ_ARB_STATE_ISSUED_VALU 0x00000006
18297#define SQ_ARB_STATE_STALLED_BRMSG 0x00000008
18298#define SQ_ARB_STATE_STALLED_EXPORT 0x00000009
18299#define SQ_ARB_STATE_STALLED_LDS_DIRECT 0x0000000a
18300#define SQ_ARB_STATE_STALLED_LDS 0x0000000b
18301#define SQ_ARB_STATE_STALLED_TEX 0x0000000c
18302#define SQ_ARB_STATE_STALLED_SCALAR 0x0000000d
18303#define SQ_ARB_STATE_STALLED_VALU 0x0000000e
18304
18305/*******************************************************
18306 * GL1 Enums
18307 *******************************************************/
18308
18309/*
18310 * GL1A_PERF_SEL enum
18311 */
18312
18313typedef enum GL1A_PERF_SEL {
18314GL1A_PERF_SEL_BUSY = 0x00000000,
18315GL1A_PERF_SEL_STALL_GL1C0 = 0x00000001,
18316GL1A_PERF_SEL_STALL_GL1C1 = 0x00000002,
18317GL1A_PERF_SEL_STALL_GL1C2 = 0x00000003,
18318GL1A_PERF_SEL_STALL_GL1C3 = 0x00000004,
18319GL1A_PERF_SEL_REQUEST_GL1C0 = 0x00000005,
18320GL1A_PERF_SEL_REQUEST_GL1C1 = 0x00000006,
18321GL1A_PERF_SEL_REQUEST_GL1C2 = 0x00000007,
18322GL1A_PERF_SEL_REQUEST_GL1C3 = 0x00000008,
18323GL1A_PERF_SEL_WDS_32B_GL1C0 = 0x00000009,
18324GL1A_PERF_SEL_WDS_32B_GL1C1 = 0x0000000a,
18325GL1A_PERF_SEL_WDS_32B_GL1C2 = 0x0000000b,
18326GL1A_PERF_SEL_WDS_32B_GL1C3 = 0x0000000c,
18327GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 0x0000000d,
18328GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 0x0000000e,
18329GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 0x0000000f,
18330GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 0x00000010,
18331GL1A_PERF_SEL_ARB_REQUESTS = 0x00000011,
18332GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000012,
18333GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 0x00000013,
18334GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 0x00000014,
18335GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 0x00000015,
18336GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 0x00000016,
18337GL1A_PERF_SEL_CYCLE = 0x00000017,
18338} GL1A_PERF_SEL;
18339
18340/*
18341 * GL1C_PERF_SEL enum
18342 */
18343
18344typedef enum GL1C_PERF_SEL {
18345GL1C_PERF_SEL_CYCLE = 0x00000000,
18346GL1C_PERF_SEL_BUSY = 0x00000001,
18347GL1C_PERF_SEL_STARVE = 0x00000002,
18348GL1C_PERF_SEL_ARB_RET_LEVEL = 0x00000003,
18349GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000004,
18350GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x00000005,
18351GL1C_PERF_SEL_REQ = 0x00000006,
18352GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x00000007,
18353GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000008,
18354GL1C_PERF_SEL_REQ_NOP_ACK = 0x00000009,
18355GL1C_PERF_SEL_REQ_NOP_RTN0 = 0x0000000a,
18356GL1C_PERF_SEL_REQ_READ = 0x0000000b,
18357GL1C_PERF_SEL_REQ_READ_128B = 0x0000000c,
18358GL1C_PERF_SEL_REQ_READ_32B = 0x0000000d,
18359GL1C_PERF_SEL_REQ_READ_64B = 0x0000000e,
18360GL1C_PERF_SEL_REQ_WRITE = 0x0000000f,
18361GL1C_PERF_SEL_REQ_WRITE_32B = 0x00000010,
18362GL1C_PERF_SEL_REQ_WRITE_64B = 0x00000011,
18363GL1C_PERF_SEL_STALL_GL2_GL1 = 0x00000012,
18364GL1C_PERF_SEL_STALL_BUFFER_FULL = 0x00000013,
18365GL1C_PERF_SEL_STALL_VM = 0x00000014,
18366GL1C_PERF_SEL_REQ_CLIENT0 = 0x00000015,
18367GL1C_PERF_SEL_REQ_CLIENT1 = 0x00000016,
18368GL1C_PERF_SEL_REQ_CLIENT2 = 0x00000017,
18369GL1C_PERF_SEL_REQ_CLIENT3 = 0x00000018,
18370GL1C_PERF_SEL_REQ_CLIENT4 = 0x00000019,
18371GL1C_PERF_SEL_REQ_CLIENT5 = 0x0000001a,
18372GL1C_PERF_SEL_REQ_CLIENT6 = 0x0000001b,
18373GL1C_PERF_SEL_REQ_CLIENT7 = 0x0000001c,
18374GL1C_PERF_SEL_REQ_CLIENT8 = 0x0000001d,
18375GL1C_PERF_SEL_REQ_CLIENT9 = 0x0000001e,
18376GL1C_PERF_SEL_REQ_CLIENT10 = 0x0000001f,
18377GL1C_PERF_SEL_REQ_CLIENT11 = 0x00000020,
18378GL1C_PERF_SEL_REQ_CLIENT12 = 0x00000021,
18379GL1C_PERF_SEL_REQ_CLIENT13 = 0x00000022,
18380GL1C_PERF_SEL_REQ_CLIENT14 = 0x00000023,
18381GL1C_PERF_SEL_REQ_CLIENT15 = 0x00000024,
18382GL1C_PERF_SEL_REQ_CLIENT16 = 0x00000025,
18383GL1C_PERF_SEL_REQ_CLIENT17 = 0x00000026,
18384GL1C_PERF_SEL_REQ_CLIENT18 = 0x00000027,
18385GL1C_PERF_SEL_REQ_CLIENT19 = 0x00000028,
18386GL1C_PERF_SEL_REQ_CLIENT20 = 0x00000029,
18387GL1C_PERF_SEL_REQ_CLIENT21 = 0x0000002a,
18388GL1C_PERF_SEL_REQ_CLIENT22 = 0x0000002b,
18389GL1C_PERF_SEL_REQ_CLIENT23 = 0x0000002c,
18390GL1C_PERF_SEL_REQ_CLIENT24 = 0x0000002d,
18391GL1C_PERF_SEL_REQ_CLIENT25 = 0x0000002e,
18392GL1C_PERF_SEL_REQ_CLIENT26 = 0x0000002f,
18393GL1C_PERF_SEL_REQ_CLIENT27 = 0x00000030,
18394GL1C_PERF_SEL_UTCL0_REQUEST = 0x00000031,
18395GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 0x00000032,
18396GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 0x00000033,
18397GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 0x00000034,
18398GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 0x00000035,
18399GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 0x00000036,
18400GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 0x00000037,
18401GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 0x00000038,
18402GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 0x00000039,
18403GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 0x0000003a,
18404GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 0x0000003b,
18405GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x0000003c,
18406GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 0x0000003d,
18407GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 0x0000003e,
18408GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 0x0000003f,
18409GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 0x00000040,
18410GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 0x00000041,
18411GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 0x00000042,
18412GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 0x00000043,
18413GL1C_PERF_SEL_UTCL0_GPA3_REQUEST = 0x00000044,
18414} GL1C_PERF_SEL;
18415
18416/*
18417 * GL1XA_PERF_SEL enum
18418 */
18419
18420typedef enum GL1XA_PERF_SEL {
18421GL1XA_PERF_SEL_BUSY = 0x00000000,
18422GL1XA_PERF_SEL_STALL_GL1XC0 = 0x00000001,
18423GL1XA_PERF_SEL_STALL_GL1XC1 = 0x00000002,
18424GL1XA_PERF_SEL_STALL_GL1XC2 = 0x00000003,
18425GL1XA_PERF_SEL_STALL_GL1XC3 = 0x00000004,
18426GL1XA_PERF_SEL_REQUEST_GL1XC0 = 0x00000005,
18427GL1XA_PERF_SEL_REQUEST_GL1XC1 = 0x00000006,
18428GL1XA_PERF_SEL_REQUEST_GL1XC2 = 0x00000007,
18429GL1XA_PERF_SEL_REQUEST_GL1XC3 = 0x00000008,
18430GL1XA_PERF_SEL_WDS_32B_GL1XC0 = 0x00000009,
18431GL1XA_PERF_SEL_WDS_32B_GL1XC1 = 0x0000000a,
18432GL1XA_PERF_SEL_WDS_32B_GL1XC2 = 0x0000000b,
18433GL1XA_PERF_SEL_WDS_32B_GL1XC3 = 0x0000000c,
18434GL1XA_PERF_SEL_BURST_COUNT_GL1XC0 = 0x0000000d,
18435GL1XA_PERF_SEL_BURST_COUNT_GL1XC1 = 0x0000000e,
18436GL1XA_PERF_SEL_BURST_COUNT_GL1XC2 = 0x0000000f,
18437GL1XA_PERF_SEL_BURST_COUNT_GL1XC3 = 0x00000010,
18438GL1XA_PERF_SEL_ARB_REQUESTS = 0x00000011,
18439GL1XA_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000012,
18440GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC0 = 0x00000013,
18441GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC1 = 0x00000014,
18442GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC2 = 0x00000015,
18443GL1XA_PERF_SEL_STALL_RET_CONFLICT_GL1XC3 = 0x00000016,
18444GL1XA_PERF_SEL_CYCLE = 0x00000017,
18445} GL1XA_PERF_SEL;
18446
18447/*
18448 * GL1XC_PERF_SEL enum
18449 */
18450
18451typedef enum GL1XC_PERF_SEL {
18452GL1XC_PERF_SEL_CYCLE = 0x00000000,
18453GL1XC_PERF_SEL_BUSY = 0x00000001,
18454GL1XC_PERF_SEL_STARVE = 0x00000002,
18455GL1XC_PERF_SEL_ARB_RET_LEVEL = 0x00000003,
18456GL1XC_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000004,
18457GL1XC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x00000005,
18458GL1XC_PERF_SEL_REQ = 0x00000006,
18459GL1XC_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x00000007,
18460GL1XC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000008,
18461GL1XC_PERF_SEL_REQ_NOP_ACK = 0x00000009,
18462GL1XC_PERF_SEL_REQ_NOP_RTN0 = 0x0000000a,
18463GL1XC_PERF_SEL_REQ_READ = 0x0000000b,
18464GL1XC_PERF_SEL_REQ_READ_128B = 0x0000000c,
18465GL1XC_PERF_SEL_REQ_READ_32B = 0x0000000d,
18466GL1XC_PERF_SEL_REQ_READ_64B = 0x0000000e,
18467GL1XC_PERF_SEL_REQ_WRITE = 0x0000000f,
18468GL1XC_PERF_SEL_REQ_WRITE_32B = 0x00000010,
18469GL1XC_PERF_SEL_REQ_WRITE_64B = 0x00000011,
18470GL1XC_PERF_SEL_STALL_GL2_GL1 = 0x00000012,
18471GL1XC_PERF_SEL_STALL_BUFFER_FULL = 0x00000013,
18472GL1XC_PERF_SEL_STALL_VM = 0x00000014,
18473GL1XC_PERF_SEL_REQ_CLIENT0 = 0x00000015,
18474GL1XC_PERF_SEL_REQ_CLIENT1 = 0x00000016,
18475GL1XC_PERF_SEL_REQ_CLIENT2 = 0x00000017,
18476GL1XC_PERF_SEL_REQ_CLIENT3 = 0x00000018,
18477GL1XC_PERF_SEL_REQ_CLIENT4 = 0x00000019,
18478GL1XC_PERF_SEL_REQ_CLIENT5 = 0x0000001a,
18479GL1XC_PERF_SEL_REQ_CLIENT6 = 0x0000001b,
18480GL1XC_PERF_SEL_REQ_CLIENT7 = 0x0000001c,
18481GL1XC_PERF_SEL_REQ_CLIENT8 = 0x0000001d,
18482GL1XC_PERF_SEL_REQ_CLIENT9 = 0x0000001e,
18483GL1XC_PERF_SEL_REQ_CLIENT10 = 0x0000001f,
18484GL1XC_PERF_SEL_REQ_CLIENT11 = 0x00000020,
18485GL1XC_PERF_SEL_REQ_CLIENT12 = 0x00000021,
18486GL1XC_PERF_SEL_REQ_CLIENT13 = 0x00000022,
18487GL1XC_PERF_SEL_REQ_CLIENT14 = 0x00000023,
18488GL1XC_PERF_SEL_REQ_CLIENT15 = 0x00000024,
18489GL1XC_PERF_SEL_REQ_CLIENT16 = 0x00000025,
18490GL1XC_PERF_SEL_REQ_CLIENT17 = 0x00000026,
18491GL1XC_PERF_SEL_REQ_CLIENT18 = 0x00000027,
18492GL1XC_PERF_SEL_REQ_CLIENT19 = 0x00000028,
18493GL1XC_PERF_SEL_REQ_CLIENT20 = 0x00000029,
18494GL1XC_PERF_SEL_REQ_CLIENT21 = 0x0000002a,
18495GL1XC_PERF_SEL_REQ_CLIENT22 = 0x0000002b,
18496GL1XC_PERF_SEL_REQ_CLIENT23 = 0x0000002c,
18497GL1XC_PERF_SEL_REQ_CLIENT24 = 0x0000002d,
18498GL1XC_PERF_SEL_REQ_CLIENT25 = 0x0000002e,
18499GL1XC_PERF_SEL_REQ_CLIENT26 = 0x0000002f,
18500GL1XC_PERF_SEL_REQ_CLIENT27 = 0x00000030,
18501GL1XC_PERF_SEL_UTCL0_REQUEST = 0x00000031,
18502GL1XC_PERF_SEL_UTCL0_TRANSLATION_HIT = 0x00000032,
18503GL1XC_PERF_SEL_UTCL0_TRANSLATION_MISS = 0x00000033,
18504GL1XC_PERF_SEL_UTCL0_PERMISSION_MISS = 0x00000034,
18505GL1XC_PERF_SEL_UTCL0_MISS_UNDER_MISS = 0x00000035,
18506GL1XC_PERF_SEL_UTCL0_LFIFO_FULL = 0x00000036,
18507GL1XC_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 0x00000037,
18508GL1XC_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 0x00000038,
18509GL1XC_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 0x00000039,
18510GL1XC_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 0x0000003a,
18511GL1XC_PERF_SEL_UTCL0_STALL_MULTI_MISS = 0x0000003b,
18512GL1XC_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x0000003c,
18513GL1XC_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 0x0000003d,
18514GL1XC_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 0x0000003e,
18515GL1XC_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 0x0000003f,
18516GL1XC_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 0x00000040,
18517GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 0x00000041,
18518GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 0x00000042,
18519GL1XC_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 0x00000043,
18520GL1XC_PERF_SEL_UTCL0_GPA3_REQUEST = 0x00000044,
18521} GL1XC_PERF_SEL;
18522
18523/*******************************************************
18524 * GRBMH Enums
18525 *******************************************************/
18526
18527/*
18528 * GRBMH_PERF_SEL enum
18529 */
18530
18531typedef enum GRBMH_PERF_SEL {
18532GRBMH_PERF_SEL_COUNT = 0x00000000,
18533GRBMH_PERF_SEL_USER_DEFINED = 0x00000001,
18534GRBMH_PERF_SEL_CB_BUSY = 0x00000002,
18535GRBMH_PERF_SEL_CB_CLEAN = 0x00000003,
18536GRBMH_PERF_SEL_DB_BUSY = 0x00000004,
18537GRBMH_PERF_SEL_DB_CLEAN = 0x00000005,
18538GRBMH_PERF_SEL_SC_BUSY = 0x00000006,
18539GRBMH_PERF_SEL_SC_CLEAN = 0x00000007,
18540GRBMH_PERF_SEL_SPI_BUSY = 0x00000009,
18541GRBMH_PERF_SEL_SX_BUSY = 0x0000000a,
18542GRBMH_PERF_SEL_TA_BUSY = 0x0000000b,
18543GRBMH_PERF_SEL_EA_BUSY = 0x0000000c,
18544GRBMH_PERF_SEL_EA_LINK_BUSY = 0x0000000d,
18545GRBMH_PERF_SEL_PA_BUSY = 0x0000000e,
18546GRBMH_PERF_SEL_BCI_BUSY = 0x0000000f,
18547GRBMH_PERF_SEL_GL2A_BUSY = 0x00000010,
18548GRBMH_PERF_SEL_GL2C_BUSY = 0x00000011,
18549GRBMH_PERF_SEL_UTCL1_BUSY = 0x00000012,
18550GRBMH_PERF_SEL_TCP_BUSY = 0x00000013,
18551GRBMH_PERF_SEL_GL1A_BUSY = 0x00000014,
18552GRBMH_PERF_SEL_GL1CC_BUSY = 0x00000015,
18553GRBMH_PERF_SEL_GL1XCC_BUSY = 0x00000016,
18554GRBMH_PERF_SEL_PC_BUSY = 0x00000017,
18555GRBMH_PERF_SEL_GE_BUSY = 0x00000018,
18556GRBMH_PERF_SEL_RLC_BUSY = 0x00000019,
18557} GRBMH_PERF_SEL;
18558
18559/*******************************************************
18560 * TA Enums
18561 *******************************************************/
18562
18563/*
18564 * TA_PERFCOUNT_SEL enum
18565 */
18566
18567typedef enum TA_PERFCOUNT_SEL {
18568TA_PERF_SEL_NULL = 0x00000000,
18569TA_PERF_SEL_image_sampler_has_offset_instructions = 0x00000001,
18570TA_PERF_SEL_image_sampler_has_bias_instructions = 0x00000002,
18571TA_PERF_SEL_image_sampler_has_reference_instructions = 0x00000003,
18572TA_PERF_SEL_image_sampler_has_ds_instructions = 0x00000004,
18573TA_PERF_SEL_image_sampler_has_dt_instructions = 0x00000005,
18574TA_PERF_SEL_image_sampler_has_dr_instructions = 0x00000006,
18575TA_PERF_SEL_gradient_busy = 0x00000007,
18576TA_PERF_SEL_gradient_fifo_busy = 0x00000008,
18577TA_PERF_SEL_lod_busy = 0x00000009,
18578TA_PERF_SEL_lod_fifo_busy = 0x0000000a,
18579TA_PERF_SEL_addresser_busy = 0x0000000b,
18580TA_PERF_SEL_addresser_fifo_busy = 0x0000000c,
18581TA_PERF_SEL_aligner_busy = 0x0000000d,
18582TA_PERF_SEL_write_path_busy = 0x0000000e,
18583TA_PERF_SEL_ta_busy = 0x0000000f,
18584TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 0x00000010,
18585TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 0x00000011,
18586TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 0x00000012,
18587TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 0x00000013,
18588TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 0x00000014,
18589TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 0x00000015,
18590TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 0x00000016,
18591TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 0x00000017,
18592TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 0x00000018,
18593TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 0x00000019,
18594TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 0x0000001a,
18595TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 0x0000001b,
18596TA_PERF_SEL_image_sampler_has_t_instructions = 0x0000001c,
18597TA_PERF_SEL_image_sampler_has_r_instructions = 0x0000001d,
18598TA_PERF_SEL_image_sampler_has_q_instructions = 0x0000001e,
18599TA_PERF_SEL_total_wavefronts = 0x00000020,
18600TA_PERF_SEL_gradient_cycles = 0x00000021,
18601TA_PERF_SEL_walker_cycles = 0x00000022,
18602TA_PERF_SEL_aligner_cycles = 0x00000023,
18603TA_PERF_SEL_image_wavefronts = 0x00000024,
18604TA_PERF_SEL_image_read_wavefronts = 0x00000025,
18605TA_PERF_SEL_image_store_wavefronts = 0x00000026,
18606TA_PERF_SEL_image_atomic_wavefronts = 0x00000027,
18607TA_PERF_SEL_image_sampler_total_cycles = 0x00000028,
18608TA_PERF_SEL_image_nosampler_total_cycles = 0x00000029,
18609TA_PERF_SEL_flat_total_cycles = 0x0000002a,
18610TA_PERF_SEL_buffer_wavefronts = 0x0000002c,
18611TA_PERF_SEL_buffer_load_wavefronts = 0x0000002d,
18612TA_PERF_SEL_buffer_store_wavefronts = 0x0000002e,
18613TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f,
18614TA_PERF_SEL_buffer_total_cycles = 0x00000031,
18615TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 0x00000032,
18616TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 0x00000033,
18617TA_PERF_SEL_buffer_has_index_instructions = 0x00000034,
18618TA_PERF_SEL_buffer_has_offset_instructions = 0x00000035,
18619TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036,
18620TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037,
18621TA_PERF_SEL_image_sampler_wavefronts = 0x00000038,
18622TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039,
18623TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a,
18624TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b,
18625TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c,
18626TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d,
18627TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e,
18628TA_PERF_SEL_aniso_gt1_cycle_quads = 0x0000003f,
18629TA_PERF_SEL_color_1_cycle_quads = 0x00000040,
18630TA_PERF_SEL_color_2_cycle_quads = 0x00000041,
18631TA_PERF_SEL_color_3_cycle_quads = 0x00000042,
18632TA_PERF_SEL_mip_1_cycle_quads = 0x00000044,
18633TA_PERF_SEL_mip_2_cycle_quads = 0x00000045,
18634TA_PERF_SEL_vol_1_cycle_quads = 0x00000046,
18635TA_PERF_SEL_vol_2_cycle_quads = 0x00000047,
18636TA_PERF_SEL_sampler_op_quads = 0x00000048,
18637TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049,
18638TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a,
18639TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b,
18640TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c,
18641TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d,
18642TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e,
18643TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f,
18644TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050,
18645TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051,
18646TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052,
18647TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053,
18648TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054,
18649TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055,
18650TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056,
18651TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057,
18652TA_PERF_SEL_mipmap_invalid_samples = 0x00000058,
18653TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059,
18654TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a,
18655TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b,
18656TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c,
18657TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d,
18658TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e,
18659TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f,
18660TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060,
18661TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061,
18662TA_PERF_SEL_store_write_data_input_cycles = 0x00000062,
18663TA_PERF_SEL_store_write_data_output_cycles = 0x00000063,
18664TA_PERF_SEL_flat_wavefronts = 0x00000064,
18665TA_PERF_SEL_flat_load_wavefronts = 0x00000065,
18666TA_PERF_SEL_flat_store_wavefronts = 0x00000066,
18667TA_PERF_SEL_flat_atomic_wavefronts = 0x00000067,
18668TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 0x00000068,
18669TA_PERF_SEL_register_clk_valid_cycles = 0x00000069,
18670TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 0x0000006a,
18671TA_PERF_SEL_harvestable_clk_enabled_cycles = 0x0000006b,
18672TA_PERF_SEL_flat_2_address_input_vgpr_instructions = 0x0000006c,
18673TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 0x0000006d,
18674TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 0x0000006e,
18675TA_PERF_SEL_mipmap_lod_15_samples = 0x00000070,
18676TA_PERF_SEL_mipmap_lod_16_samples = 0x00000071,
18677TA_PERF_SEL_store_2_write_data_vgpr_instructions = 0x00000072,
18678TA_PERF_SEL_store_3_write_data_vgpr_instructions = 0x00000073,
18679TA_PERF_SEL_store_4_write_data_vgpr_instructions = 0x00000074,
18680TA_PERF_SEL_store_has_x_instructions = 0x00000075,
18681TA_PERF_SEL_store_has_y_instructions = 0x00000076,
18682TA_PERF_SEL_store_has_z_instructions = 0x00000077,
18683TA_PERF_SEL_store_has_w_instructions = 0x00000078,
18684TA_PERF_SEL_image_nosampler_has_t_instructions = 0x00000079,
18685TA_PERF_SEL_image_nosampler_has_r_instructions = 0x0000007a,
18686TA_PERF_SEL_image_nosampler_has_q_instructions = 0x0000007b,
18687TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 0x0000007c,
18688TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 0x0000007d,
18689TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 0x0000007e,
18690TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 0x0000007f,
18691TA_PERF_SEL_in_busy = 0x00000080,
18692TA_PERF_SEL_in_fifos_busy = 0x00000081,
18693TA_PERF_SEL_in_cfifo_busy = 0x00000082,
18694TA_PERF_SEL_in_qfifo_busy = 0x00000083,
18695TA_PERF_SEL_in_wfifo_busy = 0x00000084,
18696TA_PERF_SEL_in_rfifo_busy = 0x00000085,
18697TA_PERF_SEL_bf_busy = 0x00000086,
18698TA_PERF_SEL_ns_busy = 0x00000087,
18699TA_PERF_SEL_smp_busy_ns_idle = 0x00000088,
18700TA_PERF_SEL_smp_idle_ns_busy = 0x00000089,
18701TA_PERF_SEL_vmemcmd_cycles = 0x00000090,
18702TA_PERF_SEL_vmemreq_cycles = 0x00000091,
18703TA_PERF_SEL_in_waiting_on_req_cycles = 0x00000092,
18704TA_PERF_SEL_in_addr_cycles = 0x00000096,
18705TA_PERF_SEL_in_data_cycles = 0x00000097,
18706TA_PERF_SEL_point_sampled_quads = 0x000000a0,
18707TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 0x000000a2,
18708TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 0x000000a3,
18709TA_PERF_SEL_atomic_write_data_input_cycles = 0x000000a4,
18710TA_PERF_SEL_atomic_write_data_output_cycles = 0x000000a5,
18711TA_PERF_SEL_num_unlit_nodes_ta_opt = 0x000000ad,
18712TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 0x000000ae,
18713TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 0x000000af,
18714TA_PERF_SEL_image_sampler_1_op_burst = 0x000000c0,
18715TA_PERF_SEL_image_sampler_2to3_op_burst = 0x000000c1,
18716TA_PERF_SEL_image_sampler_4to7_op_burst = 0x000000c2,
18717TA_PERF_SEL_image_sampler_ge8_op_burst = 0x000000c3,
18718TA_PERF_SEL_image_linked_1_op_burst = 0x000000c4,
18719TA_PERF_SEL_image_linked_2to3_op_burst = 0x000000c5,
18720TA_PERF_SEL_image_linked_4to7_op_burst = 0x000000c6,
18721TA_PERF_SEL_image_linked_ge8_op_burst = 0x000000c7,
18722TA_PERF_SEL_image_nosampler_1_op_burst = 0x000000cc,
18723TA_PERF_SEL_image_nosampler_2to3_op_burst = 0x000000cd,
18724TA_PERF_SEL_image_nosampler_4to31_op_burst = 0x000000ce,
18725TA_PERF_SEL_image_nosampler_ge32_op_burst = 0x000000cf,
18726TA_PERF_SEL_buffer_flat_1_op_burst = 0x000000d0,
18727TA_PERF_SEL_buffer_flat_2to3_op_burst = 0x000000d1,
18728TA_PERF_SEL_buffer_flat_4to31_op_burst = 0x000000d2,
18729TA_PERF_SEL_buffer_flat_ge32_op_burst = 0x000000d3,
18730TA_PERF_SEL_write_1_op_burst = 0x000000d4,
18731TA_PERF_SEL_write_2to3_op_burst = 0x000000d5,
18732TA_PERF_SEL_write_4to31_op_burst = 0x000000d6,
18733TA_PERF_SEL_write_ge32_op_burst = 0x000000d7,
18734TA_PERF_SEL_ibubble_1_cycle_burst = 0x000000d8,
18735TA_PERF_SEL_ibubble_2to3_cycle_burst = 0x000000d9,
18736TA_PERF_SEL_ibubble_4to15_cycle_burst = 0x000000da,
18737TA_PERF_SEL_ibubble_16to31_cycle_burst = 0x000000db,
18738TA_PERF_SEL_ibubble_32to63_cycle_burst = 0x000000dc,
18739TA_PERF_SEL_ibubble_ge64_cycle_burst = 0x000000dd,
18740TA_PERF_SEL_sampler_clk_valid_cycles = 0x000000e0,
18741TA_PERF_SEL_nonsampler_clk_valid_cycles = 0x000000e1,
18742TA_PERF_SEL_buffer_flat_clk_valid_cycles = 0x000000e2,
18743TA_PERF_SEL_write_data_clk_valid_cycles = 0x000000e3,
18744TA_PERF_SEL_gradient_clk_valid_cycles = 0x000000e4,
18745TA_PERF_SEL_lod_aniso_clk_valid_cycles = 0x000000e5,
18746TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 0x000000e6,
18747TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 0x000000e7,
18748TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 0x000000e8,
18749TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 0x000000e9,
18750TA_PERF_SEL_aligner_clk_valid_cycles = 0x000000ea,
18751TA_PERF_SEL_tcreq_clk_valid_cycles = 0x000000eb,
18752} TA_PERFCOUNT_SEL;
18753
18754/*
18755 * TEX_BC_SWIZZLE enum
18756 */
18757
18758typedef enum TEX_BC_SWIZZLE {
18759TEX_BC_Swizzle_XYZW = 0x00000000,
18760TEX_BC_Swizzle_XWYZ = 0x00000001,
18761TEX_BC_Swizzle_WZYX = 0x00000002,
18762TEX_BC_Swizzle_WXYZ = 0x00000003,
18763TEX_BC_Swizzle_ZYXW = 0x00000004,
18764TEX_BC_Swizzle_YXWZ = 0x00000005,
18765} TEX_BC_SWIZZLE;
18766
18767/*
18768 * TEX_BORDER_COLOR_TYPE enum
18769 */
18770
18771typedef enum TEX_BORDER_COLOR_TYPE {
18772TEX_BorderColor_TransparentBlack = 0x00000000,
18773TEX_BorderColor_OpaqueBlack = 0x00000001,
18774TEX_BorderColor_OpaqueWhite = 0x00000002,
18775TEX_BorderColor_Register = 0x00000003,
18776} TEX_BORDER_COLOR_TYPE;
18777
18778/*
18779 * TEX_CHROMA_KEY enum
18780 */
18781
18782typedef enum TEX_CHROMA_KEY {
18783TEX_ChromaKey_Disabled = 0x00000000,
18784TEX_ChromaKey_Kill = 0x00000001,
18785TEX_ChromaKey_Blend = 0x00000002,
18786TEX_ChromaKey_RESERVED_3 = 0x00000003,
18787} TEX_CHROMA_KEY;
18788
18789/*
18790 * TEX_CLAMP enum
18791 */
18792
18793typedef enum TEX_CLAMP {
18794TEX_Clamp_Repeat = 0x00000000,
18795TEX_Clamp_Mirror = 0x00000001,
18796TEX_Clamp_ClampToLast = 0x00000002,
18797TEX_Clamp_MirrorOnceToLast = 0x00000003,
18798TEX_Clamp_ClampHalfToBorder = 0x00000004,
18799TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005,
18800TEX_Clamp_ClampToBorder = 0x00000006,
18801TEX_Clamp_MirrorOnceToBorder = 0x00000007,
18802} TEX_CLAMP;
18803
18804/*
18805 * TEX_COORD_TYPE enum
18806 */
18807
18808typedef enum TEX_COORD_TYPE {
18809TEX_CoordType_Unnormalized = 0x00000000,
18810TEX_CoordType_Normalized = 0x00000001,
18811} TEX_COORD_TYPE;
18812
18813/*
18814 * TEX_DEPTH_COMPARE_FUNCTION enum
18815 */
18816
18817typedef enum TEX_DEPTH_COMPARE_FUNCTION {
18818TEX_DepthCompareFunction_Never = 0x00000000,
18819TEX_DepthCompareFunction_Less = 0x00000001,
18820TEX_DepthCompareFunction_Equal = 0x00000002,
18821TEX_DepthCompareFunction_LessEqual = 0x00000003,
18822TEX_DepthCompareFunction_Greater = 0x00000004,
18823TEX_DepthCompareFunction_NotEqual = 0x00000005,
18824TEX_DepthCompareFunction_GreaterEqual = 0x00000006,
18825TEX_DepthCompareFunction_Always = 0x00000007,
18826} TEX_DEPTH_COMPARE_FUNCTION;
18827
18828/*
18829 * TEX_FORMAT_COMP enum
18830 */
18831
18832typedef enum TEX_FORMAT_COMP {
18833TEX_FormatComp_Unsigned = 0x00000000,
18834TEX_FormatComp_Signed = 0x00000001,
18835TEX_FormatComp_UnsignedBiased = 0x00000002,
18836TEX_FormatComp_RESERVED_3 = 0x00000003,
18837} TEX_FORMAT_COMP;
18838
18839/*
18840 * TEX_MAX_ANISO_RATIO enum
18841 */
18842
18843typedef enum TEX_MAX_ANISO_RATIO {
18844TEX_MaxAnisoRatio_1to1 = 0x00000000,
18845TEX_MaxAnisoRatio_2to1 = 0x00000001,
18846TEX_MaxAnisoRatio_4to1 = 0x00000002,
18847TEX_MaxAnisoRatio_8to1 = 0x00000003,
18848TEX_MaxAnisoRatio_16to1 = 0x00000004,
18849TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005,
18850TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006,
18851TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007,
18852} TEX_MAX_ANISO_RATIO;
18853
18854/*
18855 * TEX_MIP_FILTER enum
18856 */
18857
18858typedef enum TEX_MIP_FILTER {
18859TEX_MipFilter_None = 0x00000000,
18860TEX_MipFilter_Point = 0x00000001,
18861TEX_MipFilter_Linear = 0x00000002,
18862TEX_MipFilter_Point_Aniso_Adj = 0x00000003,
18863} TEX_MIP_FILTER;
18864
18865/*
18866 * TEX_REQUEST_SIZE enum
18867 */
18868
18869typedef enum TEX_REQUEST_SIZE {
18870TEX_RequestSize_32B = 0x00000000,
18871TEX_RequestSize_64B = 0x00000001,
18872TEX_RequestSize_128B = 0x00000002,
18873TEX_RequestSize_2X64B = 0x00000003,
18874} TEX_REQUEST_SIZE;
18875
18876/*
18877 * TEX_SAMPLER_TYPE enum
18878 */
18879
18880typedef enum TEX_SAMPLER_TYPE {
18881TEX_SamplerType_Invalid = 0x00000000,
18882TEX_SamplerType_Valid = 0x00000001,
18883} TEX_SAMPLER_TYPE;
18884
18885/*
18886 * TEX_XY_FILTER enum
18887 */
18888
18889typedef enum TEX_XY_FILTER {
18890TEX_XYFilter_Point = 0x00000000,
18891TEX_XYFilter_Linear = 0x00000001,
18892TEX_XYFilter_AnisoPoint = 0x00000002,
18893TEX_XYFilter_AnisoLinear = 0x00000003,
18894} TEX_XY_FILTER;
18895
18896/*
18897 * TEX_Z_FILTER enum
18898 */
18899
18900typedef enum TEX_Z_FILTER {
18901TEX_ZFilter_None = 0x00000000,
18902TEX_ZFilter_Point = 0x00000001,
18903TEX_ZFilter_Linear = 0x00000002,
18904TEX_ZFilter_RESERVED_3 = 0x00000003,
18905} TEX_Z_FILTER;
18906
18907/*
18908 * TVX_TYPE enum
18909 */
18910
18911typedef enum TVX_TYPE {
18912TVX_Type_InvalidTextureResource = 0x00000000,
18913TVX_Type_InvalidVertexBuffer = 0x00000001,
18914TVX_Type_ValidTextureResource = 0x00000002,
18915TVX_Type_ValidVertexBuffer = 0x00000003,
18916} TVX_TYPE;
18917
18918/*
18919 * TA_TC_ADDR_MODES enum
18920 */
18921
18922typedef enum TA_TC_ADDR_MODES {
18923TA_TC_ADDR_MODE_DEFAULT = 0x00000000,
18924TA_TC_ADDR_MODE_COMP0 = 0x00000001,
18925TA_TC_ADDR_MODE_COMP1 = 0x00000002,
18926TA_TC_ADDR_MODE_COMP2 = 0x00000003,
18927TA_TC_ADDR_MODE_COMP3 = 0x00000004,
18928TA_TC_ADDR_MODE_UNALIGNED = 0x00000005,
18929TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006,
18930} TA_TC_ADDR_MODES;
18931
18932/*
18933 * TA_TC_REQ_MODES enum
18934 */
18935
18936typedef enum TA_TC_REQ_MODES {
18937TA_TC_REQ_MODE_BORDER = 0x00000000,
18938TA_TC_REQ_MODE_TEX2 = 0x00000001,
18939TA_TC_REQ_MODE_TEX1 = 0x00000002,
18940TA_TC_REQ_MODE_TEX0 = 0x00000003,
18941TA_TC_REQ_MODE_NORMAL = 0x00000004,
18942TA_TC_REQ_MODE_DWORD = 0x00000005,
18943TA_TC_REQ_MODE_BYTE = 0x00000006,
18944TA_TC_REQ_MODE_BYTE_NV = 0x00000007,
18945} TA_TC_REQ_MODES;
18946
18947/*
18948 * TCP_CACHE_POLICIES enum
18949 */
18950
18951typedef enum TCP_CACHE_POLICIES {
18952TCP_CACHE_POLICY_MISS_LRU = 0x00000000,
18953TCP_CACHE_POLICY_MISS_EVICT = 0x00000001,
18954TCP_CACHE_POLICY_HIT_LRU = 0x00000002,
18955TCP_CACHE_POLICY_HIT_EVICT = 0x00000003,
18956} TCP_CACHE_POLICIES;
18957
18958/*
18959 * TCP_CACHE_STORE_POLICIES enum
18960 */
18961
18962typedef enum TCP_CACHE_STORE_POLICIES {
18963TCP_CACHE_STORE_POLICY_WT_LRU = 0x00000000,
18964TCP_CACHE_STORE_POLICY_WT_EVICT = 0x00000001,
18965} TCP_CACHE_STORE_POLICIES;
18966
18967/*
18968 * TCP_COMPRESSION_BYPASS enum
18969 */
18970
18971typedef enum TCP_COMPRESSION_BYPASS {
18972TCP_COMPRESSION_BYPASS_DIS = 0x00000000,
18973TCP_COMPRESSION_BYPASS_EN = 0x00000001,
18974} TCP_COMPRESSION_BYPASS;
18975
18976/*
18977 * TCP_COMPRESSION_OVERRIDE enum
18978 */
18979
18980typedef enum TCP_COMPRESSION_OVERRIDE {
18981TCP_COMPRESSION_OVERRIDE_DIS = 0x00000000,
18982TCP_COMPRESSION_OVERRIDE_EN = 0x00000001,
18983} TCP_COMPRESSION_OVERRIDE;
18984
18985/*
18986 * TCP_OPCODE_TYPE enum
18987 */
18988
18989typedef enum TCP_OPCODE_TYPE {
18990TCP_OPCODE_READ = 0x00000000,
18991TCP_OPCODE_WRITE = 0x00000001,
18992TCP_OPCODE_ATOMIC = 0x00000002,
18993TCP_OPCODE_INV = 0x00000003,
18994TCP_OPCODE_ATOMIC_CMPSWAP = 0x00000004,
18995TCP_OPCODE_SAMPLER = 0x00000005,
18996TCP_OPCODE_LOAD = 0x00000006,
18997TCP_OPCODE_GATHERH = 0x00000007,
18998} TCP_OPCODE_TYPE;
18999
19000/*
19001 * TCP_PERFCOUNT_SELECT enum
19002 */
19003
19004typedef enum TCP_PERFCOUNT_SELECT {
19005TCP_PERF_SEL_GATE_EN1 = 0x00000000,
19006TCP_PERF_SEL_GATE_EN2 = 0x00000001,
19007TCP_PERF_SEL_TA_REQ = 0x00000002,
19008TCP_PERF_SEL_TA_REQ_STATE_READ = 0x00000003,
19009TCP_PERF_SEL_TA_REQ_READ = 0x00000004,
19010TCP_PERF_SEL_TA_REQ_WRITE = 0x00000005,
19011TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 0x00000006,
19012TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 0x00000007,
19013TCP_PERF_SEL_TA_REQ_GL0_INV = 0x00000008,
19014TCP_PERF_SEL_REQ = 0x00000009,
19015TCP_PERF_SEL_REQ_READ = 0x0000000a,
19016TCP_PERF_SEL_REQ_READ_HIT_LRU = 0x0000000c,
19017TCP_PERF_SEL_REQ_READ_MISS_EVICT = 0x0000000d,
19018TCP_PERF_SEL_REQ_WRITE = 0x0000000e,
19019TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 0x0000000f,
19020TCP_PERF_SEL_REQ_NON_READ = 0x00000010,
19021TCP_PERF_SEL_REQ_MISS = 0x00000011,
19022TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 0x00000012,
19023TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 0x00000013,
19024TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 0x00000014,
19025TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 0x00000015,
19026TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 0x00000016,
19027TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 0x00000017,
19028TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 0x00000018,
19029TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 0x00000019,
19030TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 0x0000001a,
19031TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 0x0000001b,
19032TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 0x0000001c,
19033TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 0x0000001d,
19034TCP_PERF_SEL_GL1_REQ_READ = 0x0000001e,
19035TCP_PERF_SEL_GL1_REQ_READ_128B = 0x0000001f,
19036TCP_PERF_SEL_GL1_REQ_READ_64B = 0x00000020,
19037TCP_PERF_SEL_GL1_REQ_WRITE = 0x00000021,
19038TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 0x00000022,
19039TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 0x00000023,
19040TCP_PERF_SEL_GL1_READ_LATENCY = 0x00000024,
19041TCP_PERF_SEL_GL1_WRITE_LATENCY = 0x00000025,
19042TCP_PERF_SEL_TCP_LATENCY = 0x00000026,
19043TCP_PERF_SEL_TCP_TA_REQ_STALL = 0x00000027,
19044TCP_PERF_SEL_TA_TCP_REQ_STARVE = 0x00000028,
19045TCP_PERF_SEL_DATA_FIFO_STALL = 0x00000029,
19046TCP_PERF_SEL_LOD_STALL = 0x0000002a,
19047TCP_PERF_SEL_POWER_STALL = 0x0000002b,
19048TCP_PERF_SEL_ALLOC_STALL = 0x0000002c,
19049TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 0x0000002e,
19050TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 0x0000002f,
19051TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 0x00000030,
19052TCP_PERF_SEL_LFIFO_STALL = 0x00000031,
19053TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 0x00000032,
19054TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 0x00000033,
19055TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 0x00000034,
19056TCP_PERF_SEL_GL1_GRANT_READ_STALL = 0x00000035,
19057TCP_PERF_SEL_GL1_PENDING_STALL = 0x00000036,
19058TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 0x00000037,
19059TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 0x00000038,
19060TCP_PERF_SEL_READ_DATACONFLICT_STALL = 0x00000039,
19061TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 0x0000003a,
19062TCP_PERF_SEL_TD_TCP_STALL = 0x0000003b,
19063TCP_PERF_SEL_TA_REQ_BUFFERNOP = 0x0000003c,
19064TCP_PERF_SEL_WRITECOMBINE_ENDCLAUSE = 0x0000003d,
19065TCP_PERF_SEL_TAGFAKE_EOW = 0x0000003e,
19066TCP_PERF_SEL_REQ_TAG_MATCH_AND_NOT_VALID = 0x0000003f,
19067TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_0 = 0x00000040,
19068TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_1to2 = 0x00000041,
19069TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_3to4 = 0x00000042,
19070TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_5to8 = 0x00000043,
19071TCP_PERF_SEL_BURST_BIN_WRITECOMBINE_9to16 = 0x00000044,
19072TCP_PERF_SEL_BURST_BIN_READHIT_0 = 0x00000046,
19073TCP_PERF_SEL_BURST_BIN_READHIT_1 = 0x00000047,
19074TCP_PERF_SEL_BURST_BIN_READHIT_2to4 = 0x00000048,
19075TCP_PERF_SEL_BURST_BIN_READHIT_5to8 = 0x00000049,
19076TCP_PERF_SEL_BURST_BIN_READHIT_9to16 = 0x0000004a,
19077TCP_PERF_SEL_BURST_BIN_READHIT_gt16 = 0x0000004b,
19078TCP_PERF_SEL_TA_TC_REQ_EN_SUM = 0x0000004c,
19079TCP_PERF_SEL_GL1_REQ_LU = 0x0000004d,
19080TCP_PERF_SEL_REQ_TAG_MATCH_AND_LU_INVALIDATE = 0x0000004e,
19081} TCP_PERFCOUNT_SELECT;
19082
19083/*
19084 * TCP_WATCH_MODES enum
19085 */
19086
19087typedef enum TCP_WATCH_MODES {
19088TCP_WATCH_MODE_READ = 0x00000000,
19089TCP_WATCH_MODE_NONREAD = 0x00000001,
19090TCP_WATCH_MODE_ATOMIC = 0x00000002,
19091TCP_WATCH_MODE_ALL = 0x00000003,
19092} TCP_WATCH_MODES;
19093
19094/*
19095 * TCP_WRITE_COMPRESSION_DISABLE enum
19096 */
19097
19098typedef enum TCP_WRITE_COMPRESSION_DISABLE {
19099TCP_WRITE_COMPRESSION_DISABLE_DIS = 0x00000000,
19100TCP_WRITE_COMPRESSION_DISABLE_EN = 0x00000001,
19101} TCP_WRITE_COMPRESSION_DISABLE;
19102
19103/*******************************************************
19104 * TD Enums
19105 *******************************************************/
19106
19107/*
19108 * TD_PERFCOUNT_SEL enum
19109 */
19110
19111typedef enum TD_PERFCOUNT_SEL {
19112TD_PERF_SEL_none = 0x00000000,
19113TD_PERF_SEL_td_busy = 0x00000001,
19114TD_PERF_SEL_input_busy = 0x00000002,
19115TD_PERF_SEL_sampler_lerp_busy = 0x00000003,
19116TD_PERF_SEL_sampler_out_busy = 0x00000004,
19117TD_PERF_SEL_nofilter_busy = 0x00000005,
19118TD_PERF_SEL_sampler_core_sclk_en = 0x00000007,
19119TD_PERF_SEL_sampler_preformatter_sclk_en = 0x00000008,
19120TD_PERF_SEL_sampler_bilerp_sclk_en = 0x00000009,
19121TD_PERF_SEL_sampler_bypass_sclk_en = 0x0000000a,
19122TD_PERF_SEL_sampler_minmax_sclk_en = 0x0000000b,
19123TD_PERF_SEL_sampler_accum_sclk_en = 0x0000000c,
19124TD_PERF_SEL_sampler_format_flt_sclk_en = 0x0000000d,
19125TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 0x0000000e,
19126TD_PERF_SEL_sampler_out_sclk_en = 0x0000000f,
19127TD_PERF_SEL_nofilter_sclk_en = 0x00000010,
19128TD_PERF_SEL_nofilter_d32_sclk_en = 0x00000011,
19129TD_PERF_SEL_nofilter_d16_sclk_en = 0x00000012,
19130TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 0x0000001a,
19131TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 0x0000001b,
19132TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 0x0000001c,
19133TD_PERF_SEL_core_state_ram_max_cnt = 0x00000020,
19134TD_PERF_SEL_core_state_rams_read = 0x00000021,
19135TD_PERF_SEL_weight_data_rams_read = 0x00000022,
19136TD_PERF_SEL_reference_data_rams_read = 0x00000023,
19137TD_PERF_SEL_tc_td_ram_fifo_full = 0x00000024,
19138TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 0x00000025,
19139TD_PERF_SEL_tc_td_data_fifo_full = 0x00000026,
19140TD_PERF_SEL_input_state_fifo_full = 0x00000027,
19141TD_PERF_SEL_ta_data_stall = 0x00000028,
19142TD_PERF_SEL_tc_data_stall = 0x00000029,
19143TD_PERF_SEL_tc_ram_stall = 0x0000002a,
19144TD_PERF_SEL_lds_stall = 0x0000002b,
19145TD_PERF_SEL_sampler_pkr_full = 0x0000002c,
19146TD_PERF_SEL_sampler_pkr_full_due_to_arb = 0x0000002d,
19147TD_PERF_SEL_nofilter_pkr_full = 0x0000002e,
19148TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 0x0000002f,
19149TD_PERF_SEL_gather4_instr = 0x00000032,
19150TD_PERF_SEL_gather4h_instr = 0x00000033,
19151TD_PERF_SEL_getlod_instr = 0x00000034,
19152TD_PERF_SEL_sample_instr = 0x00000036,
19153TD_PERF_SEL_sample_c_instr = 0x00000037,
19154TD_PERF_SEL_load_instr = 0x00000038,
19155TD_PERF_SEL_ps_load_instr = 0x00000039,
19156TD_PERF_SEL_write_ack_instr = 0x0000003a,
19157TD_PERF_SEL_d16_en_instr = 0x0000003b,
19158TD_PERF_SEL_bypassLerp_instr = 0x0000003c,
19159TD_PERF_SEL_min_max_filter_instr = 0x0000003d,
19160TD_PERF_SEL_one_comp_return_instr = 0x0000003e,
19161TD_PERF_SEL_two_comp_return_instr = 0x0000003f,
19162TD_PERF_SEL_three_comp_return_instr = 0x00000040,
19163TD_PERF_SEL_four_comp_return_instr = 0x00000041,
19164TD_PERF_SEL_user_defined_border = 0x00000042,
19165TD_PERF_SEL_white_border = 0x00000043,
19166TD_PERF_SEL_opaque_black_border = 0x00000044,
19167TD_PERF_SEL_lod_warn_from_ta = 0x00000045,
19168TD_PERF_SEL_instruction_dest_is_lds = 0x00000046,
19169TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 0x00000047,
19170TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 0x00000048,
19171TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 0x00000049,
19172TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 0x0000004a,
19173TD_PERF_SEL_out_of_order_instr = 0x0000004b,
19174TD_PERF_SEL_total_num_instr = 0x0000004c,
19175TD_PERF_SEL_total_num_instr_with_perf_wdw = 0x0000004d,
19176TD_PERF_SEL_total_num_sampler_instr = 0x0000004e,
19177TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 0x0000004f,
19178TD_PERF_SEL_total_num_nofilter_instr = 0x00000050,
19179TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 0x00000051,
19180TD_PERF_SEL_mixmode_instr = 0x00000054,
19181TD_PERF_SEL_mixmode_resource = 0x00000055,
19182TD_PERF_SEL_status_packet = 0x00000056,
19183TD_PERF_SEL_done_scoreboard_max_stored_cnt = 0x00000059,
19184TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 0x0000005a,
19185TD_PERF_SEL_done_scoreboard_not_empty = 0x0000005b,
19186TD_PERF_SEL_done_scoreboard_is_full = 0x0000005c,
19187TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 0x0000005d,
19188TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 0x0000005e,
19189TD_PERF_SEL_nofilter_formatters_turned_on = 0x0000005f,
19190TD_PERF_SEL_nofilter_insert_extra_comps = 0x00000060,
19191TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 0x00000061,
19192TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 0x00000062,
19193TD_PERF_SEL_msaa_load_instr = 0x00000063,
19194TD_PERF_SEL_blend_prt_with_prt_default_0 = 0x00000064,
19195TD_PERF_SEL_resmap_instr = 0x00000066,
19196TD_PERF_SEL_prt_ack_instr = 0x00000067,
19197TD_PERF_SEL_resmap_with_volume_filtering = 0x00000068,
19198TD_PERF_SEL_resmap_with_aniso_filtering = 0x00000069,
19199TD_PERF_SEL_resmap_with_no_more_filtering = 0x0000006a,
19200TD_PERF_SEL_resmap_with_cubemap_corner = 0x0000006b,
19201TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 0x00000083,
19202TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 0x00000084,
19203TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 0x00000085,
19204TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 0x00000086,
19205TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 0x00000087,
19206TD_PERF_SEL_burst_bin_sampler_1 = 0x00000088,
19207TD_PERF_SEL_burst_bin_sampler_2to8 = 0x00000089,
19208TD_PERF_SEL_burst_bin_sampler_9to16 = 0x0000008a,
19209TD_PERF_SEL_burst_bin_sampler_gt16 = 0x0000008b,
19210TD_PERF_SEL_burst_bin_gather_1 = 0x0000008c,
19211TD_PERF_SEL_burst_bin_gather_2to8 = 0x0000008d,
19212TD_PERF_SEL_burst_bin_gather_9to16 = 0x0000008e,
19213TD_PERF_SEL_burst_bin_gather_gt16 = 0x0000008f,
19214TD_PERF_SEL_burst_bin_nofilter_1 = 0x00000090,
19215TD_PERF_SEL_burst_bin_nofilter_2to4 = 0x00000091,
19216TD_PERF_SEL_burst_bin_nofilter_5to7 = 0x00000092,
19217TD_PERF_SEL_burst_bin_nofilter_8to16 = 0x00000093,
19218TD_PERF_SEL_burst_bin_nofilter_gt16 = 0x00000094,
19219TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 0x000000aa,
19220TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 0x000000ab,
19221TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 0x000000ac,
19222TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 0x000000ad,
19223TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 0x000000ae,
19224TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 0x000000af,
19225TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 0x000000b0,
19226TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 0x000000b1,
19227TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 0x000000b2,
19228TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 0x000000b3,
19229TD_PERF_SEL_preempting_nofilter_max_cnt = 0x000000b4,
19230TD_PERF_SEL_sampler_lerp0_active = 0x000000b5,
19231TD_PERF_SEL_sampler_lerp1_active = 0x000000b6,
19232TD_PERF_SEL_sampler_lerp2_active = 0x000000b7,
19233TD_PERF_SEL_sampler_lerp3_active = 0x000000b8,
19234TD_PERF_SEL_sampler_lerp4_active = 0x000000b9,
19235TD_PERF_SEL_sampler_lerp5_active = 0x000000ba,
19236TD_PERF_SEL_sampler_lerp6_active = 0x000000bb,
19237TD_PERF_SEL_sampler_lerp7_active = 0x000000bc,
19238TD_PERF_SEL_nofilter_total_num_comps_to_lds = 0x000000bd,
19239TD_PERF_SEL_nofilter_byte_cycling_4cycles = 0x000000be,
19240TD_PERF_SEL_nofilter_byte_cycling_8cycles = 0x000000bf,
19241TD_PERF_SEL_nofilter_byte_cycling_16cycles = 0x000000c0,
19242TD_PERF_SEL_nofilter_dword_cycling_2cycles = 0x000000c1,
19243TD_PERF_SEL_nofilter_dword_cycling_4cycles = 0x000000c2,
19244TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 0x000000c3,
19245TD_PERF_SEL_store_preempts_a_load = 0x000000c8,
19246TD_PERF_SEL_sample_2x_instr = 0x000000c9,
19247TD_PERF_SEL_gather4_2x_instr = 0x000000ca,
19248TD_PERF_SEL_gather4h_2x_instr = 0x000000cb,
19249TD_PERF_SEL_getlod_2x_instr = 0x000000cc,
19250TD_PERF_SEL_resmap_2x_instr = 0x000000cd,
19251TD_PERF_SEL_2x_sampler_op_with_1_unlit_quad = 0x000000ce,
19252TD_PERF_SEL_2x_sampler_op_with_both_quads_unlit = 0x000000cf,
19253TD_PERF_SEL_tri_proc_node_override_slot0 = 0x000000d0,
19254TD_PERF_SEL_tri_run_intersect_ahs_slot0 = 0x000000d1,
19255TD_PERF_SEL_tri_run_ahs_slot0 = 0x000000d2,
19256TD_PERF_SEL_tri_proc_node_override_slot1 = 0x000000e7,
19257TD_PERF_SEL_tri_run_intersect_ahs_slot1 = 0x000000e8,
19258TD_PERF_SEL_tri_run_ahs_slot1 = 0x000000e9,
19259TD_PERF_SEL_instance_mask_culled = 0x000000f1,
19260TD_PERF_SEL_box_opaque_culled = 0x000000f2,
19261TD_PERF_SEL_box_non_opaque_culled = 0x000000f3,
19262TD_PERF_SEL_box_with_triangle_children_only_culled = 0x000000f4,
19263TD_PERF_SEL_box_with_procedural_children_only_culled = 0x000000f5,
19264TD_PERF_SEL_triangle_opaque_culled = 0x000000f6,
19265TD_PERF_SEL_triangle_non_opaque_culled = 0x000000f7,
19266TD_PERF_SEL_triangle_front_facing_culled = 0x000000f8,
19267TD_PERF_SEL_triangle_back_facing_culled = 0x000000f9,
19268} TD_PERFCOUNT_SEL;
19269
19270/*
19271 * GL2A_PERF_SEL enum
19272 */
19273
19274typedef enum GL2A_PERF_SEL {
19275GL2A_PERF_SEL_NONE = 0x00000000,
19276GL2A_PERF_SEL_CYCLE = 0x00000001,
19277GL2A_PERF_SEL_BUSY = 0x00000002,
19278GL2A_PERF_SEL_REQ_GL2C0 = 0x00000003,
19279GL2A_PERF_SEL_REQ_GL2C1 = 0x00000004,
19280GL2A_PERF_SEL_REQ_GL2C2 = 0x00000005,
19281GL2A_PERF_SEL_REQ_GL2C3 = 0x00000006,
19282GL2A_PERF_SEL_REQ_GL2C4 = 0x00000007,
19283GL2A_PERF_SEL_REQ_GL2C5 = 0x00000008,
19284GL2A_PERF_SEL_REQ_GL2C6 = 0x00000009,
19285GL2A_PERF_SEL_REQ_GL2C7 = 0x0000000a,
19286GL2A_PERF_SEL_REQ_BURST_GL2C0 = 0x00000013,
19287GL2A_PERF_SEL_REQ_BURST_GL2C1 = 0x00000014,
19288GL2A_PERF_SEL_REQ_BURST_GL2C2 = 0x00000015,
19289GL2A_PERF_SEL_REQ_BURST_GL2C3 = 0x00000016,
19290GL2A_PERF_SEL_REQ_BURST_GL2C4 = 0x00000017,
19291GL2A_PERF_SEL_REQ_BURST_GL2C5 = 0x00000018,
19292GL2A_PERF_SEL_REQ_BURST_GL2C6 = 0x00000019,
19293GL2A_PERF_SEL_REQ_BURST_GL2C7 = 0x0000001a,
19294GL2A_PERF_SEL_REQ_STALL_GL2C0 = 0x0000001b,
19295GL2A_PERF_SEL_REQ_STALL_GL2C1 = 0x0000001c,
19296GL2A_PERF_SEL_REQ_STALL_GL2C2 = 0x0000001d,
19297GL2A_PERF_SEL_REQ_STALL_GL2C3 = 0x0000001e,
19298GL2A_PERF_SEL_REQ_STALL_GL2C4 = 0x0000001f,
19299GL2A_PERF_SEL_REQ_STALL_GL2C5 = 0x00000020,
19300GL2A_PERF_SEL_REQ_STALL_GL2C6 = 0x00000021,
19301GL2A_PERF_SEL_REQ_STALL_GL2C7 = 0x00000022,
19302GL2A_PERF_SEL_RTN_STALL_GL2C0 = 0x00000023,
19303GL2A_PERF_SEL_RTN_STALL_GL2C1 = 0x00000024,
19304GL2A_PERF_SEL_RTN_STALL_GL2C2 = 0x00000025,
19305GL2A_PERF_SEL_RTN_STALL_GL2C3 = 0x00000026,
19306GL2A_PERF_SEL_RTN_STALL_GL2C4 = 0x00000027,
19307GL2A_PERF_SEL_RTN_STALL_GL2C5 = 0x00000028,
19308GL2A_PERF_SEL_RTN_STALL_GL2C6 = 0x00000029,
19309GL2A_PERF_SEL_RTN_STALL_GL2C7 = 0x0000002a,
19310GL2A_PERF_SEL_RTN_CLIENT0 = 0x0000002b,
19311GL2A_PERF_SEL_RTN_CLIENT1 = 0x0000002c,
19312GL2A_PERF_SEL_RTN_CLIENT2 = 0x0000002d,
19313GL2A_PERF_SEL_RTN_CLIENT3 = 0x0000002e,
19314GL2A_PERF_SEL_RTN_CLIENT4 = 0x0000002f,
19315GL2A_PERF_SEL_RTN_CLIENT5 = 0x00000030,
19316GL2A_PERF_SEL_RTN_CLIENT6 = 0x00000031,
19317GL2A_PERF_SEL_RTN_CLIENT7 = 0x00000032,
19318GL2A_PERF_SEL_RTN_CLIENT8 = 0x00000033,
19319GL2A_PERF_SEL_RTN_CLIENT9 = 0x00000034,
19320GL2A_PERF_SEL_RTN_CLIENT10 = 0x00000035,
19321GL2A_PERF_SEL_RTN_CLIENT11 = 0x00000036,
19322GL2A_PERF_SEL_RTN_CLIENT12 = 0x00000037,
19323GL2A_PERF_SEL_RTN_CLIENT13 = 0x00000038,
19324GL2A_PERF_SEL_RTN_CLIENT14 = 0x00000039,
19325GL2A_PERF_SEL_RTN_CLIENT15 = 0x0000003a,
19326GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 0x0000003b,
19327GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 0x0000003c,
19328GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 0x0000003d,
19329GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 0x0000003e,
19330GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 0x0000003f,
19331GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 0x00000040,
19332GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 0x00000041,
19333GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 0x00000042,
19334GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 0x00000043,
19335GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 0x00000044,
19336GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 0x00000045,
19337GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 0x00000046,
19338GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 0x00000047,
19339GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 0x00000048,
19340GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 0x00000049,
19341GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 0x0000004a,
19342GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 0x0000004b,
19343GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 0x0000004c,
19344GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 0x0000004d,
19345GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 0x0000004e,
19346GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 0x0000004f,
19347GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 0x00000050,
19348GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 0x00000051,
19349GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 0x00000052,
19350GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 0x00000053,
19351GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 0x00000054,
19352GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 0x00000055,
19353GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 0x00000056,
19354GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 0x00000057,
19355GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 0x00000058,
19356GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 0x00000059,
19357GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 0x0000005a,
19358GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 0x0000005b,
19359GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 0x0000005c,
19360GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 0x0000005d,
19361GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 0x0000005e,
19362GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 0x0000005f,
19363GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 0x00000060,
19364GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 0x00000061,
19365GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 0x00000062,
19366GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 0x00000063,
19367GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 0x00000064,
19368GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 0x00000065,
19369GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 0x00000067,
19370GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 0x00000068,
19371GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 0x00000069,
19372GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 0x0000006a,
19373GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 0x0000006b,
19374} GL2A_PERF_SEL;
19375
19376/*
19377 * GL2C_PERF_SEL enum
19378 */
19379
19380typedef enum GL2C_PERF_SEL {
19381GL2C_PERF_SEL_NONE = 0x00000000,
19382GL2C_PERF_SEL_CYCLE = 0x00000001,
19383GL2C_PERF_SEL_BUSY = 0x00000002,
19384GL2C_PERF_SEL_REQ = 0x00000003,
19385GL2C_PERF_SEL_VOL_REQ = 0x00000004,
19386GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 0x00000005,
19387GL2C_PERF_SEL_READ = 0x00000006,
19388GL2C_PERF_SEL_WRITE = 0x00000007,
19389GL2C_PERF_SEL_ATOMIC = 0x00000008,
19390GL2C_PERF_SEL_NOP_ACK = 0x00000009,
19391GL2C_PERF_SEL_NOP_RTN0 = 0x0000000a,
19392GL2C_PERF_SEL_COMPRESSED_READ_REQ = 0x0000000b,
19393GL2C_PERF_SEL_METADATA_READ_REQ = 0x0000000c,
19394GL2C_PERF_SEL_CLIENT0_REQ = 0x0000000d,
19395GL2C_PERF_SEL_CLIENT1_REQ = 0x0000000e,
19396GL2C_PERF_SEL_CLIENT2_REQ = 0x0000000f,
19397GL2C_PERF_SEL_CLIENT3_REQ = 0x00000010,
19398GL2C_PERF_SEL_CLIENT4_REQ = 0x00000011,
19399GL2C_PERF_SEL_CLIENT5_REQ = 0x00000012,
19400GL2C_PERF_SEL_CLIENT6_REQ = 0x00000013,
19401GL2C_PERF_SEL_CLIENT7_REQ = 0x00000014,
19402GL2C_PERF_SEL_CLIENT8_REQ = 0x00000015,
19403GL2C_PERF_SEL_CLIENT9_REQ = 0x00000016,
19404GL2C_PERF_SEL_CLIENT10_REQ = 0x00000017,
19405GL2C_PERF_SEL_CLIENT11_REQ = 0x00000018,
19406GL2C_PERF_SEL_CLIENT12_REQ = 0x00000019,
19407GL2C_PERF_SEL_CLIENT13_REQ = 0x0000001a,
19408GL2C_PERF_SEL_CLIENT14_REQ = 0x0000001b,
19409GL2C_PERF_SEL_CLIENT15_REQ = 0x0000001c,
19410GL2C_PERF_SEL_C_RW_S_REQ = 0x0000001d,
19411GL2C_PERF_SEL_C_RW_US_REQ = 0x0000001e,
19412GL2C_PERF_SEL_C_RO_S_REQ = 0x0000001f,
19413GL2C_PERF_SEL_C_RO_US_REQ = 0x00000020,
19414GL2C_PERF_SEL_UC_REQ = 0x00000021,
19415GL2C_PERF_SEL_LRU_REQ = 0x00000022,
19416GL2C_PERF_SEL_STREAM_REQ = 0x00000023,
19417GL2C_PERF_SEL_BYPASS_REQ = 0x00000024,
19418GL2C_PERF_SEL_NOA_REQ = 0x00000025,
19419GL2C_PERF_SEL_SHARED_REQ = 0x00000026,
19420GL2C_PERF_SEL_HIT = 0x00000027,
19421GL2C_PERF_SEL_MISS = 0x00000028,
19422GL2C_PERF_SEL_FULL_HIT = 0x00000029,
19423GL2C_PERF_SEL_PARTIAL_32B_HIT = 0x0000002a,
19424GL2C_PERF_SEL_PARTIAL_64B_HIT = 0x0000002b,
19425GL2C_PERF_SEL_PARTIAL_96B_HIT = 0x0000002c,
19426GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x0000002d,
19427GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 0x0000002e,
19428GL2C_PERF_SEL_UNCACHED_WRITE = 0x0000002f,
19429GL2C_PERF_SEL_WRITEBACK = 0x00000030,
19430GL2C_PERF_SEL_NORMAL_WRITEBACK = 0x00000031,
19431GL2C_PERF_SEL_EVICT = 0x00000032,
19432GL2C_PERF_SEL_NORMAL_EVICT = 0x00000033,
19433GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 0x00000034,
19434GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 0x00000035,
19435GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 0x00000036,
19436GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 0x00000037,
19437GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 0x00000038,
19438GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 0x00000039,
19439GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 0x0000003a,
19440GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 0x0000003b,
19441GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 0x0000003c,
19442GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 0x0000003d,
19443GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 0x0000003e,
19444GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 0x0000003f,
19445GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 0x00000040,
19446GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 0x00000041,
19447GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 0x00000042,
19448GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 0x00000043,
19449GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 0x00000044,
19450GL2C_PERF_SEL_READ_32_REQ = 0x00000045,
19451GL2C_PERF_SEL_READ_64_REQ = 0x00000046,
19452GL2C_PERF_SEL_READ_128_REQ = 0x00000047,
19453GL2C_PERF_SEL_WRITE_32_REQ = 0x00000048,
19454GL2C_PERF_SEL_WRITE_64_REQ = 0x00000049,
19455GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 0x0000004a,
19456GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 0x0000004b,
19457GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 0x0000004c,
19458GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 0x0000004d,
19459GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 0x0000004e,
19460GL2C_PERF_SEL_MC_WRREQ = 0x0000004f,
19461GL2C_PERF_SEL_EA_WRREQ_SNOOP = 0x00000050,
19462GL2C_PERF_SEL_EA_WRREQ_64B = 0x00000051,
19463GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 0x00000052,
19464GL2C_PERF_SEL_MC_WRREQ_STALL = 0x00000053,
19465GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 0x00000054,
19466GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 0x00000055,
19467GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 0x00000056,
19468GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 0x00000057,
19469GL2C_PERF_SEL_MC_WRREQ_LEVEL = 0x00000058,
19470GL2C_PERF_SEL_EA_ATOMIC = 0x00000059,
19471GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 0x0000005a,
19472GL2C_PERF_SEL_MC_RDREQ = 0x0000005b,
19473GL2C_PERF_SEL_EA_RDREQ_SNOOP = 0x0000005c,
19474GL2C_PERF_SEL_EA_RDREQ_SPLIT = 0x0000005d,
19475GL2C_PERF_SEL_EA_RDREQ_32B = 0x0000005e,
19476GL2C_PERF_SEL_EA_RDREQ_64B = 0x0000005f,
19477GL2C_PERF_SEL_EA_RDREQ_96B = 0x00000060,
19478GL2C_PERF_SEL_EA_RDREQ_128B = 0x00000061,
19479GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 0x00000062,
19480GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 0x00000063,
19481GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 0x00000064,
19482GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 0x00000065,
19483GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 0x00000066,
19484GL2C_PERF_SEL_MC_RDREQ_LEVEL = 0x00000067,
19485GL2C_PERF_SEL_EA_RDREQ_DRAM = 0x00000068,
19486GL2C_PERF_SEL_EA_WRREQ_DRAM = 0x00000069,
19487GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 0x0000006a,
19488GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 0x0000006b,
19489GL2C_PERF_SEL_ONION_READ = 0x0000006c,
19490GL2C_PERF_SEL_ONION_WRITE = 0x0000006d,
19491GL2C_PERF_SEL_IO_READ = 0x0000006e,
19492GL2C_PERF_SEL_IO_WRITE = 0x0000006f,
19493GL2C_PERF_SEL_GARLIC_READ = 0x00000070,
19494GL2C_PERF_SEL_GARLIC_WRITE = 0x00000071,
19495GL2C_PERF_SEL_EA_OUTSTANDING = 0x00000072,
19496GL2C_PERF_SEL_LATENCY_FIFO_FULL = 0x00000073,
19497GL2C_PERF_SEL_SRC_FIFO_FULL = 0x00000074,
19498GL2C_PERF_SEL_TAG_STALL = 0x00000075,
19499GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x00000076,
19500GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x00000077,
19501GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x00000078,
19502GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x00000079,
19503GL2C_PERF_SEL_TAG_READ_DST_STALL = 0x0000007a,
19504GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 0x0000007b,
19505GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x0000007c,
19506GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x0000007d,
19507GL2C_PERF_SEL_BUBBLE = 0x0000007e,
19508GL2C_PERF_SEL_IB_REQ = 0x0000007f,
19509GL2C_PERF_SEL_IB_STALL = 0x00000080,
19510GL2C_PERF_SEL_IB_TAG_STALL = 0x00000081,
19511GL2C_PERF_SEL_RETURN_ACK = 0x00000082,
19512GL2C_PERF_SEL_RETURN_DATA = 0x00000083,
19513GL2C_PERF_SEL_EA_RDRET_NACK = 0x00000084,
19514GL2C_PERF_SEL_EA_WRRET_NACK = 0x00000085,
19515GL2C_PERF_SEL_GL2A_LEVEL = 0x00000086,
19516GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x00000087,
19517GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 0x00000088,
19518GL2C_PERF_SEL_GCR_INV = 0x00000089,
19519GL2C_PERF_SEL_GCR_WB = 0x0000008a,
19520GL2C_PERF_SEL_GCR_DISCARD = 0x0000008b,
19521GL2C_PERF_SEL_GCR_RANGE = 0x0000008c,
19522GL2C_PERF_SEL_GCR_ALL = 0x0000008d,
19523GL2C_PERF_SEL_GCR_VOL = 0x0000008e,
19524GL2C_PERF_SEL_GCR_UNSHARED = 0x0000008f,
19525GL2C_PERF_SEL_GCR_GL2_INV_ALL = 0x00000090,
19526GL2C_PERF_SEL_GCR_GL2_WB_ALL = 0x00000091,
19527GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 0x00000092,
19528GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 0x00000093,
19529GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 0x00000094,
19530GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 0x00000095,
19531GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 0x00000096,
19532GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 0x00000097,
19533GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 0x00000098,
19534GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 0x00000099,
19535GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 0x0000009a,
19536GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 0x0000009b,
19537GL2C_PERF_SEL_GCR_INVL2_VOL_START = 0x0000009c,
19538GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 0x0000009d,
19539GL2C_PERF_SEL_GCR_WBL2_VOL_START = 0x0000009e,
19540GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 0x0000009f,
19541GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 0x000000a0,
19542GL2C_PERF_SEL_GCR_WBINVL2_START = 0x000000a1,
19543GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 0x000000a2,
19544GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 0x000000a3,
19545GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 0x000000a4,
19546GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 0x000000a5,
19547} GL2C_PERF_SEL;
19548
19549/*
19550 * SX_BLEND_OPT enum
19551 */
19552
19553typedef enum SX_BLEND_OPT {
19554BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000,
19555BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001,
19556BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002,
19557BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003,
19558BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004,
19559BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005,
19560BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006,
19561BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007,
19562} SX_BLEND_OPT;
19563
19564/*
19565 * SX_DOWNCONVERT_FORMAT enum
19566 */
19567
19568typedef enum SX_DOWNCONVERT_FORMAT {
19569SX_RT_EXPORT_NO_CONVERSION = 0x00000000,
19570SX_RT_EXPORT_32_R = 0x00000001,
19571SX_RT_EXPORT_32_A = 0x00000002,
19572SX_RT_EXPORT_10_11_11 = 0x00000003,
19573SX_RT_EXPORT_2_10_10_10 = 0x00000004,
19574SX_RT_EXPORT_8_8_8_8 = 0x00000005,
19575SX_RT_EXPORT_5_6_5 = 0x00000006,
19576SX_RT_EXPORT_1_5_5_5 = 0x00000007,
19577SX_RT_EXPORT_4_4_4_4 = 0x00000008,
19578SX_RT_EXPORT_16_16_GR = 0x00000009,
19579SX_RT_EXPORT_16_16_AR = 0x0000000a,
19580SX_RT_EXPORT_9_9_9_E5 = 0x0000000b,
19581SX_RT_EXPORT_2_10_10_10_7E3 = 0x0000000c,
19582SX_RT_EXPORT_2_10_10_10_6E4 = 0x0000000d,
19583} SX_DOWNCONVERT_FORMAT;
19584
19585/*
19586 * SX_OPT_COMB_FCN enum
19587 */
19588
19589typedef enum SX_OPT_COMB_FCN {
19590OPT_COMB_NONE = 0x00000000,
19591OPT_COMB_ADD = 0x00000001,
19592OPT_COMB_SUBTRACT = 0x00000002,
19593OPT_COMB_MIN = 0x00000003,
19594OPT_COMB_MAX = 0x00000004,
19595OPT_COMB_REVSUBTRACT = 0x00000005,
19596OPT_COMB_BLEND_DISABLED = 0x00000006,
19597OPT_COMB_SAFE_ADD = 0x00000007,
19598} SX_OPT_COMB_FCN;
19599
19600/*
19601 * SX_PERFCOUNTER_VALS enum
19602 */
19603
19604typedef enum SX_PERFCOUNTER_VALS {
19605SX_PERF_SEL_PA_IDLE_CYCLES = 0x00000000,
19606SX_PERF_SEL_PA_REQ = 0x00000001,
19607SX_PERF_SEL_PA_POS = 0x00000002,
19608SX_PERF_SEL_CLOCK = 0x00000003,
19609SX_PERF_SEL_GATE_EN1 = 0x00000004,
19610SX_PERF_SEL_GATE_EN2 = 0x00000005,
19611SX_PERF_SEL_GATE_EN3 = 0x00000006,
19612SX_PERF_SEL_GATE_EN4 = 0x00000007,
19613SX_PERF_SEL_SH_POS_STARVE = 0x00000008,
19614SX_PERF_SEL_SH_COLOR_STARVE = 0x00000009,
19615SX_PERF_SEL_SH_POS_STALL = 0x0000000a,
19616SX_PERF_SEL_SH_COLOR_STALL = 0x0000000b,
19617SX_PERF_SEL_DB0_PIXELS = 0x0000000c,
19618SX_PERF_SEL_DB0_HALF_QUADS = 0x0000000d,
19619SX_PERF_SEL_DB0_PIXEL_STALL = 0x0000000e,
19620SX_PERF_SEL_DB0_PIXEL_IDLE = 0x0000000f,
19621SX_PERF_SEL_DB0_PRED_PIXELS = 0x00000010,
19622SX_PERF_SEL_DB1_PIXELS = 0x00000011,
19623SX_PERF_SEL_DB1_HALF_QUADS = 0x00000012,
19624SX_PERF_SEL_DB1_PIXEL_STALL = 0x00000013,
19625SX_PERF_SEL_DB1_PIXEL_IDLE = 0x00000014,
19626SX_PERF_SEL_DB1_PRED_PIXELS = 0x00000015,
19627SX_PERF_SEL_DB2_PIXELS = 0x00000016,
19628SX_PERF_SEL_DB2_HALF_QUADS = 0x00000017,
19629SX_PERF_SEL_DB2_PIXEL_STALL = 0x00000018,
19630SX_PERF_SEL_DB2_PIXEL_IDLE = 0x00000019,
19631SX_PERF_SEL_DB2_PRED_PIXELS = 0x0000001a,
19632SX_PERF_SEL_DB3_PIXELS = 0x0000001b,
19633SX_PERF_SEL_DB3_HALF_QUADS = 0x0000001c,
19634SX_PERF_SEL_DB3_PIXEL_STALL = 0x0000001d,
19635SX_PERF_SEL_DB3_PIXEL_IDLE = 0x0000001e,
19636SX_PERF_SEL_DB3_PRED_PIXELS = 0x0000001f,
19637SX_PERF_SEL_COL_BUSY = 0x00000020,
19638SX_PERF_SEL_POS_BUSY = 0x00000021,
19639SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 0x00000022,
19640SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 0x00000023,
19641SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 0x00000024,
19642SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 0x00000025,
19643SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 0x00000026,
19644SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 0x00000027,
19645SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 0x00000028,
19646SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 0x00000029,
19647SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 0x0000002a,
19648SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 0x0000002b,
19649SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 0x0000002c,
19650SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 0x0000002d,
19651SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 0x0000002e,
19652SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 0x0000002f,
19653SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 0x00000030,
19654SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 0x00000031,
19655SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 0x00000032,
19656SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 0x00000033,
19657SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 0x00000034,
19658SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 0x00000035,
19659SX_PERF_SEL_PA_REQ_LATENCY = 0x00000036,
19660SX_PERF_SEL_POS_SCBD_STALL = 0x00000037,
19661SX_PERF_SEL_CLOCK_DROP_STALL = 0x00000038,
19662SX_PERF_SEL_GATE_EN5 = 0x00000039,
19663SX_PERF_SEL_GATE_EN6 = 0x0000003a,
19664SX_PERF_SEL_DB0_SIZE = 0x0000003b,
19665SX_PERF_SEL_DB1_SIZE = 0x0000003c,
19666SX_PERF_SEL_DB2_SIZE = 0x0000003d,
19667SX_PERF_SEL_DB3_SIZE = 0x0000003e,
19668SX_PERF_SEL_IDX_STALL_CYCLES = 0x0000003f,
19669SX_PERF_SEL_IDX_IDLE_CYCLES = 0x00000040,
19670SX_PERF_SEL_IDX_REQ = 0x00000041,
19671SX_PERF_SEL_IDX_RET = 0x00000042,
19672SX_PERF_SEL_IDX_REQ_LATENCY = 0x00000043,
19673SX_PERF_SEL_IDX_SCBD_STALL = 0x00000044,
19674SX_PERF_SEL_GATE_EN7 = 0x00000045,
19675SX_PERF_SEL_GATE_EN8 = 0x00000046,
19676SX_PERF_SEL_SH_IDX_STARVE = 0x00000047,
19677SX_PERF_SEL_IDX_BUSY = 0x00000048,
19678SX_PERF_SEL_PA_POS_BANK_CONF = 0x00000049,
19679SX_PERF_SEL_DB0_END_OF_WAVE = 0x0000004a,
19680SX_PERF_SEL_DB0_4X2_DISCARD = 0x0000004b,
19681SX_PERF_SEL_DB1_END_OF_WAVE = 0x0000004c,
19682SX_PERF_SEL_DB1_4X2_DISCARD = 0x0000004d,
19683SX_PERF_SEL_DB2_END_OF_WAVE = 0x0000004e,
19684SX_PERF_SEL_DB2_4X2_DISCARD = 0x0000004f,
19685SX_PERF_SEL_DB3_END_OF_WAVE = 0x00000050,
19686SX_PERF_SEL_DB3_4X2_DISCARD = 0x00000051,
19687} SX_PERFCOUNTER_VALS;
19688
19689/*
19690 * CompareFrag enum
19691 */
19692
19693typedef enum CompareFrag {
19694FRAG_NEVER = 0x00000000,
19695FRAG_LESS = 0x00000001,
19696FRAG_EQUAL = 0x00000002,
19697FRAG_LEQUAL = 0x00000003,
19698FRAG_GREATER = 0x00000004,
19699FRAG_NOTEQUAL = 0x00000005,
19700FRAG_GEQUAL = 0x00000006,
19701FRAG_ALWAYS = 0x00000007,
19702} CompareFrag;
19703
19704/*
19705 * ConservativeZExport enum
19706 */
19707
19708typedef enum ConservativeZExport {
19709EXPORT_ANY_Z = 0x00000000,
19710EXPORT_LESS_THAN_Z = 0x00000001,
19711EXPORT_GREATER_THAN_Z = 0x00000002,
19712EXPORT_RESERVED = 0x00000003,
19713} ConservativeZExport;
19714
19715/*
19716 * DbMemArbWatermarks enum
19717 */
19718
19719typedef enum DbMemArbWatermarks {
19720TRANSFERRED_64_BYTES = 0x00000000,
19721TRANSFERRED_128_BYTES = 0x00000001,
19722TRANSFERRED_256_BYTES = 0x00000002,
19723TRANSFERRED_512_BYTES = 0x00000003,
19724TRANSFERRED_1024_BYTES = 0x00000004,
19725TRANSFERRED_2048_BYTES = 0x00000005,
19726TRANSFERRED_4096_BYTES = 0x00000006,
19727TRANSFERRED_8192_BYTES = 0x00000007,
19728} DbMemArbWatermarks;
19729
19730/*
19731 * DbPRTFaultBehavior enum
19732 */
19733
19734typedef enum DbPRTFaultBehavior {
19735FAULT_ZERO = 0x00000000,
19736FAULT_ONE = 0x00000001,
19737FAULT_FAIL = 0x00000002,
19738FAULT_PASS = 0x00000003,
19739} DbPRTFaultBehavior;
19740
19741/*
19742 * DbPSLControl enum
19743 */
19744
19745typedef enum DbPSLControl {
19746PSLC_AUTO = 0x00000000,
19747PSLC_ON_HANG_ONLY = 0x00000001,
19748PSLC_ASAP = 0x00000002,
19749PSLC_COUNTDOWN = 0x00000003,
19750} DbPSLControl;
19751
19752/*
19753 * ForceControl enum
19754 */
19755
19756typedef enum ForceControl {
19757FORCE_OFF = 0x00000000,
19758FORCE_ENABLE = 0x00000001,
19759FORCE_DISABLE = 0x00000002,
19760FORCE_RESERVED = 0x00000003,
19761} ForceControl;
19762
19763/*
19764 * GLCompressionMode enum
19765 */
19766
19767typedef enum GLCompressionMode {
19768DB_DEFAULT = 0x00000000,
19769DB_BYPASS = 0x00000001,
19770DB_COMP_WR_DISABLE = 0x00000002,
19771DB_BYPASS_WR_DISABLE = 0x00000003,
19772} GLCompressionMode;
19773
19774/*
19775 * OreoMode enum
19776 */
19777
19778typedef enum OreoMode {
19779OMODE_BLEND = 0x00000000,
19780OMODE_O_THEN_B = 0x00000001,
19781OMODE_P_THEN_O_THEN_B = 0x00000002,
19782OMODE_RESERVED_3 = 0x00000003,
19783} OreoMode;
19784
19785/*
19786 * PerfCounter_Vals enum
19787 */
19788
19789typedef enum PerfCounter_Vals {
19790DB_PERF_SEL_SC_DB_tile_sends = 0x00000000,
19791DB_PERF_SEL_SC_DB_tile_busy = 0x00000001,
19792DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002,
19793DB_PERF_SEL_SC_DB_tile_events = 0x00000003,
19794DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004,
19795DB_PERF_SEL_SC_DB_tile_covered = 0x00000005,
19796DB_PERF_SEL_hiz_tc_read_starved = 0x00000006,
19797DB_PERF_SEL_hiz_tc_write_stall = 0x00000007,
19798DB_PERF_SEL_hiz_tile_culled = 0x00000008,
19799DB_PERF_SEL_his_tile_culled = 0x00000009,
19800DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a,
19801DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b,
19802DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c,
19803DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d,
19804DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e,
19805DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f,
19806DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010,
19807DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011,
19808DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012,
19809DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013,
19810DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014,
19811DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015,
19812DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016,
19813DB_PERF_SEL_SC_DB_quad_sends = 0x00000017,
19814DB_PERF_SEL_SC_DB_quad_busy = 0x00000018,
19815DB_PERF_SEL_SC_DB_quad_squads = 0x00000019,
19816DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a,
19817DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b,
19818DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c,
19819DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d,
19820DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e,
19821DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f,
19822DB_PERF_SEL_DB_SC_quad_tiles = 0x00000020,
19823DB_PERF_SEL_DB_SC_quad_lit_quad = 0x00000021,
19824DB_PERF_SEL_DB_CB_export_events = 0x00000022,
19825DB_PERF_SEL_SX_DB_quad_sends = 0x00000025,
19826DB_PERF_SEL_SX_DB_quad_busy = 0x00000026,
19827DB_PERF_SEL_SX_DB_quad_stalls = 0x00000027,
19828DB_PERF_SEL_SX_DB_quad_quads = 0x00000028,
19829DB_PERF_SEL_SX_DB_quad_pixels = 0x00000029,
19830DB_PERF_SEL_SX_DB_quad_exports = 0x0000002a,
19831DB_PERF_SEL_SH_quads_outstanding_sum = 0x0000002b,
19832DB_PERF_SEL_DB_CB_export_sends = 0x0000002c,
19833DB_PERF_SEL_DB_CB_export_busy = 0x0000002d,
19834DB_PERF_SEL_DB_CB_export_stalls = 0x0000002e,
19835DB_PERF_SEL_DB_CB_export_quads = 0x0000002f,
19836DB_PERF_SEL_tile_rd_sends = 0x00000030,
19837DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x00000031,
19838DB_PERF_SEL_quad_rd_sends = 0x00000032,
19839DB_PERF_SEL_quad_rd_busy = 0x00000033,
19840DB_PERF_SEL_quad_rd_mi_stall = 0x00000034,
19841DB_PERF_SEL_quad_rd_rw_collision = 0x00000035,
19842DB_PERF_SEL_quad_rd_tag_stall = 0x00000036,
19843DB_PERF_SEL_quad_rd_32byte_reqs = 0x00000037,
19844DB_PERF_SEL_quad_rd_panic = 0x00000038,
19845DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x00000039,
19846DB_PERF_SEL_quad_rdret_sends = 0x0000003a,
19847DB_PERF_SEL_quad_rdret_busy = 0x0000003b,
19848DB_PERF_SEL_tile_wr_sends = 0x0000003c,
19849DB_PERF_SEL_tile_wr_acks = 0x0000003d,
19850DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x0000003e,
19851DB_PERF_SEL_quad_wr_sends = 0x0000003f,
19852DB_PERF_SEL_quad_wr_busy = 0x00000040,
19853DB_PERF_SEL_quad_wr_mi_stall = 0x00000041,
19854DB_PERF_SEL_quad_wr_coherency_stall = 0x00000042,
19855DB_PERF_SEL_quad_wr_acks = 0x00000043,
19856DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x00000044,
19857DB_PERF_SEL_Tile_Cache_misses = 0x00000045,
19858DB_PERF_SEL_Tile_Cache_hits = 0x00000046,
19859DB_PERF_SEL_Tile_Cache_flushes = 0x00000047,
19860DB_PERF_SEL_Tile_Cache_surface_stall = 0x00000048,
19861DB_PERF_SEL_Tile_Cache_starves = 0x00000049,
19862DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a,
19863DB_PERF_SEL_tcp_dispatcher_reads = 0x0000004b,
19864DB_PERF_SEL_tcp_prefetcher_reads = 0x0000004c,
19865DB_PERF_SEL_tcp_preloader_reads = 0x0000004d,
19866DB_PERF_SEL_tcp_dispatcher_flushes = 0x0000004e,
19867DB_PERF_SEL_tcp_prefetcher_flushes = 0x0000004f,
19868DB_PERF_SEL_tcp_preloader_flushes = 0x00000050,
19869DB_PERF_SEL_Depth_Tile_Cache_sends = 0x00000051,
19870DB_PERF_SEL_Depth_Tile_Cache_busy = 0x00000052,
19871DB_PERF_SEL_Depth_Tile_Cache_starves = 0x00000053,
19872DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054,
19873DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055,
19874DB_PERF_SEL_Depth_Tile_Cache_misses = 0x00000056,
19875DB_PERF_SEL_Depth_Tile_Cache_hits = 0x00000057,
19876DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x00000058,
19877DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x00000059,
19878DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a,
19879DB_PERF_SEL_Depth_Tile_Cache_event = 0x0000005b,
19880DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x0000005c,
19881DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x0000005d,
19882DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e,
19883DB_PERF_SEL_Stencil_Cache_misses = 0x0000005f,
19884DB_PERF_SEL_Stencil_Cache_hits = 0x00000060,
19885DB_PERF_SEL_Stencil_Cache_flushes = 0x00000061,
19886DB_PERF_SEL_Stencil_Cache_starves = 0x00000062,
19887DB_PERF_SEL_Stencil_Cache_frees = 0x00000063,
19888DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x00000064,
19889DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x00000065,
19890DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x00000066,
19891DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x00000067,
19892DB_PERF_SEL_Z_Cache_pmask_misses = 0x00000068,
19893DB_PERF_SEL_Z_Cache_pmask_hits = 0x00000069,
19894DB_PERF_SEL_Z_Cache_pmask_flushes = 0x0000006a,
19895DB_PERF_SEL_Z_Cache_pmask_starves = 0x0000006b,
19896DB_PERF_SEL_Z_Cache_frees = 0x0000006c,
19897DB_PERF_SEL_Plane_Cache_misses = 0x0000006d,
19898DB_PERF_SEL_Plane_Cache_hits = 0x0000006e,
19899DB_PERF_SEL_Plane_Cache_flushes = 0x0000006f,
19900DB_PERF_SEL_Plane_Cache_starves = 0x00000070,
19901DB_PERF_SEL_Plane_Cache_frees = 0x00000071,
19902DB_PERF_SEL_flush_expanded_stencil = 0x00000072,
19903DB_PERF_SEL_flush_compressed_stencil = 0x00000073,
19904DB_PERF_SEL_flush_single_stencil = 0x00000074,
19905DB_PERF_SEL_planes_flushed = 0x00000075,
19906DB_PERF_SEL_flush_1plane = 0x00000076,
19907DB_PERF_SEL_flush_2plane = 0x00000077,
19908DB_PERF_SEL_flush_3plane = 0x00000078,
19909DB_PERF_SEL_flush_4plane = 0x00000079,
19910DB_PERF_SEL_flush_5plane = 0x0000007a,
19911DB_PERF_SEL_flush_6plane = 0x0000007b,
19912DB_PERF_SEL_flush_7plane = 0x0000007c,
19913DB_PERF_SEL_flush_8plane = 0x0000007d,
19914DB_PERF_SEL_flush_9plane = 0x0000007e,
19915DB_PERF_SEL_flush_10plane = 0x0000007f,
19916DB_PERF_SEL_flush_11plane = 0x00000080,
19917DB_PERF_SEL_flush_12plane = 0x00000081,
19918DB_PERF_SEL_flush_13plane = 0x00000082,
19919DB_PERF_SEL_flush_14plane = 0x00000083,
19920DB_PERF_SEL_flush_15plane = 0x00000084,
19921DB_PERF_SEL_flush_16plane = 0x00000085,
19922DB_PERF_SEL_flush_expanded_z = 0x00000086,
19923DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087,
19924DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x00000088,
19925DB_PERF_SEL_dk_tile_sends = 0x00000089,
19926DB_PERF_SEL_dk_tile_busy = 0x0000008a,
19927DB_PERF_SEL_dk_tile_quad_starves = 0x0000008b,
19928DB_PERF_SEL_dk_tile_stalls = 0x0000008c,
19929DB_PERF_SEL_dk_squad_sends = 0x0000008d,
19930DB_PERF_SEL_dk_squad_busy = 0x0000008e,
19931DB_PERF_SEL_dk_squad_stalls = 0x0000008f,
19932DB_PERF_SEL_Op_Pipe_Busy = 0x00000090,
19933DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x00000091,
19934DB_PERF_SEL_qc_busy = 0x00000092,
19935DB_PERF_SEL_qc_xfc = 0x00000093,
19936DB_PERF_SEL_qc_conflicts = 0x00000094,
19937DB_PERF_SEL_qc_full_stall = 0x00000095,
19938DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096,
19939DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097,
19940DB_PERF_SEL_tsc_insert_summarize_stall = 0x00000098,
19941DB_PERF_SEL_tl_busy = 0x00000099,
19942DB_PERF_SEL_tl_dtc_read_starved = 0x0000009a,
19943DB_PERF_SEL_tl_z_fetch_stall = 0x0000009b,
19944DB_PERF_SEL_tl_stencil_stall = 0x0000009c,
19945DB_PERF_SEL_tl_z_decompress_stall = 0x0000009d,
19946DB_PERF_SEL_tl_stencil_locked_stall = 0x0000009e,
19947DB_PERF_SEL_tl_events = 0x0000009f,
19948DB_PERF_SEL_tl_summarize_squads = 0x000000a0,
19949DB_PERF_SEL_tl_flush_expand_squads = 0x000000a1,
19950DB_PERF_SEL_tl_expand_squads = 0x000000a2,
19951DB_PERF_SEL_tl_preZ_squads = 0x000000a3,
19952DB_PERF_SEL_tl_postZ_squads = 0x000000a4,
19953DB_PERF_SEL_tl_preZ_noop_squads = 0x000000a5,
19954DB_PERF_SEL_tl_postZ_noop_squads = 0x000000a6,
19955DB_PERF_SEL_tl_tile_ops = 0x000000a7,
19956DB_PERF_SEL_tl_in_xfc = 0x000000a8,
19957DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9,
19958DB_PERF_SEL_tl_in_fast_z_stall = 0x000000aa,
19959DB_PERF_SEL_tl_out_xfc = 0x000000ab,
19960DB_PERF_SEL_tl_out_squads = 0x000000ac,
19961DB_PERF_SEL_zf_plane_multicycle = 0x000000ad,
19962DB_PERF_SEL_PostZ_Samples_passing_Z = 0x000000ae,
19963DB_PERF_SEL_PostZ_Samples_failing_Z = 0x000000af,
19964DB_PERF_SEL_PostZ_Samples_failing_S = 0x000000b0,
19965DB_PERF_SEL_PreZ_Samples_passing_Z = 0x000000b1,
19966DB_PERF_SEL_PreZ_Samples_failing_Z = 0x000000b2,
19967DB_PERF_SEL_PreZ_Samples_failing_S = 0x000000b3,
19968DB_PERF_SEL_ts_tc_update_stall = 0x000000b4,
19969DB_PERF_SEL_sc_kick_start = 0x000000b5,
19970DB_PERF_SEL_sc_kick_end = 0x000000b6,
19971DB_PERF_SEL_clock_reg_active = 0x000000b7,
19972DB_PERF_SEL_clock_main_active = 0x000000b8,
19973DB_PERF_SEL_clock_mem_export_active = 0x000000b9,
19974DB_PERF_SEL_esr_ps_out_busy = 0x000000ba,
19975DB_PERF_SEL_esr_ps_lqf_busy = 0x000000bb,
19976DB_PERF_SEL_esr_ps_lqf_stall = 0x000000bc,
19977DB_PERF_SEL_etr_out_send = 0x000000bd,
19978DB_PERF_SEL_etr_out_busy = 0x000000be,
19979DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf,
19980DB_PERF_SEL_etr_out_esr_stall = 0x000000c1,
19981DB_PERF_SEL_esr_ps_vic_busy = 0x000000c2,
19982DB_PERF_SEL_esr_ps_vic_stall = 0x000000c3,
19983DB_PERF_SEL_esr_eot_fwd_busy = 0x000000c4,
19984DB_PERF_SEL_esr_eot_fwd_holding_squad = 0x000000c5,
19985DB_PERF_SEL_esr_eot_fwd_forward = 0x000000c6,
19986DB_PERF_SEL_esr_sqq_zi_busy = 0x000000c7,
19987DB_PERF_SEL_esr_sqq_zi_stall = 0x000000c8,
19988DB_PERF_SEL_postzl_sq_pt_busy = 0x000000c9,
19989DB_PERF_SEL_postzl_sq_pt_stall = 0x000000ca,
19990DB_PERF_SEL_postzl_se_busy = 0x000000cb,
19991DB_PERF_SEL_postzl_se_stall = 0x000000cc,
19992DB_PERF_SEL_postzl_partial_launch = 0x000000cd,
19993DB_PERF_SEL_postzl_full_launch = 0x000000ce,
19994DB_PERF_SEL_postzl_partial_waiting = 0x000000cf,
19995DB_PERF_SEL_postzl_tile_mem_stall = 0x000000d0,
19996DB_PERF_SEL_postzl_tile_init_stall = 0x000000d1,
19997DB_PERF_SEL_prezl_tile_mem_stall = 0x000000d2,
19998DB_PERF_SEL_prezl_tile_init_stall = 0x000000d3,
19999DB_PERF_SEL_dtt_sm_clash_stall = 0x000000d4,
20000DB_PERF_SEL_dtt_sm_slot_stall = 0x000000d5,
20001DB_PERF_SEL_dtt_sm_miss_stall = 0x000000d6,
20002DB_PERF_SEL_mi_rdreq_busy = 0x000000d7,
20003DB_PERF_SEL_mi_rdreq_stall = 0x000000d8,
20004DB_PERF_SEL_mi_wrreq_busy = 0x000000d9,
20005DB_PERF_SEL_mi_wrreq_stall = 0x000000da,
20006DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db,
20007DB_PERF_SEL_dkg_tile_rate_tile = 0x000000dc,
20008DB_PERF_SEL_prezl_src_in_sends = 0x000000dd,
20009DB_PERF_SEL_prezl_src_in_stall = 0x000000de,
20010DB_PERF_SEL_prezl_src_in_squads = 0x000000df,
20011DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0,
20012DB_PERF_SEL_prezl_src_in_tile_rate = 0x000000e1,
20013DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2,
20014DB_PERF_SEL_prezl_src_out_stall = 0x000000e3,
20015DB_PERF_SEL_postzl_src_in_sends = 0x000000e4,
20016DB_PERF_SEL_postzl_src_in_stall = 0x000000e5,
20017DB_PERF_SEL_postzl_src_in_squads = 0x000000e6,
20018DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7,
20019DB_PERF_SEL_postzl_src_in_tile_rate = 0x000000e8,
20020DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9,
20021DB_PERF_SEL_postzl_src_out_stall = 0x000000ea,
20022DB_PERF_SEL_esr_ps_src_in_sends = 0x000000eb,
20023DB_PERF_SEL_esr_ps_src_in_stall = 0x000000ec,
20024DB_PERF_SEL_esr_ps_src_in_squads = 0x000000ed,
20025DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee,
20026DB_PERF_SEL_esr_ps_src_in_tile_rate = 0x000000ef,
20027DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0,
20028DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1,
20029DB_PERF_SEL_esr_ps_src_out_stall = 0x000000f2,
20030DB_PERF_SEL_depth_bounds_tile_culled = 0x000000f3,
20031DB_PERF_SEL_PreZ_Samples_failing_DB = 0x000000f4,
20032DB_PERF_SEL_PostZ_Samples_failing_DB = 0x000000f5,
20033DB_PERF_SEL_flush_compressed = 0x000000f6,
20034DB_PERF_SEL_flush_plane_le4 = 0x000000f7,
20035DB_PERF_SEL_tiles_z_fully_summarized = 0x000000f8,
20036DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9,
20037DB_PERF_SEL_tiles_z_clear_on_expclear = 0x000000fa,
20038DB_PERF_SEL_tiles_s_clear_on_expclear = 0x000000fb,
20039DB_PERF_SEL_tiles_decomp_on_expclear = 0x000000fc,
20040DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd,
20041DB_PERF_SEL_Op_Pipe_Prez_Busy = 0x000000fe,
20042DB_PERF_SEL_Op_Pipe_Postz_Busy = 0x000000ff,
20043DB_PERF_SEL_di_dt_stall = 0x00000100,
20044DB_PERF_SEL_DB_SC_s_tile_rate = 0x00000102,
20045DB_PERF_SEL_DB_SC_c_tile_rate = 0x00000103,
20046DB_PERF_SEL_DB_SC_z_tile_rate = 0x00000104,
20047DB_PERF_SEL_DB_CB_export_export_quads = 0x00000105,
20048DB_PERF_SEL_DB_CB_export_double_format = 0x00000106,
20049DB_PERF_SEL_DB_CB_export_fast_format = 0x00000107,
20050DB_PERF_SEL_DB_CB_export_slow_format = 0x00000108,
20051DB_PERF_SEL_CB_DB_rdreq_sends = 0x00000109,
20052DB_PERF_SEL_CB_DB_rdreq_prt_sends = 0x0000010a,
20053DB_PERF_SEL_CB_DB_wrreq_sends = 0x0000010b,
20054DB_PERF_SEL_CB_DB_wrreq_prt_sends = 0x0000010c,
20055DB_PERF_SEL_DB_CB_rdret_ack = 0x0000010d,
20056DB_PERF_SEL_DB_CB_rdret_nack = 0x0000010e,
20057DB_PERF_SEL_DB_CB_wrret_ack = 0x0000010f,
20058DB_PERF_SEL_DB_CB_wrret_nack = 0x00000110,
20059DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 0x00000111,
20060DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 0x00000112,
20061DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 0x00000113,
20062DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 0x00000114,
20063DB_PERF_SEL_unmapped_z_tile_culled = 0x00000115,
20064DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_DB_DATA_TS = 0x00000116,
20065DB_PERF_SEL_DB_CB_export_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000117,
20066DB_PERF_SEL_DB_CB_export_is_event_BOTTOM_OF_PIPE_TS = 0x00000118,
20067DB_PERF_SEL_DB_CB_export_waiting_for_perfcounter_stop_event = 0x00000119,
20068DB_PERF_SEL_DB_CB_export_fmt_32bpp_8pix = 0x0000011a,
20069DB_PERF_SEL_DB_CB_export_fmt_16_16_unsigned_8pix = 0x0000011b,
20070DB_PERF_SEL_DB_CB_export_fmt_16_16_signed_8pix = 0x0000011c,
20071DB_PERF_SEL_DB_CB_export_fmt_16_16_float_8pix = 0x0000011d,
20072DB_PERF_SEL_DB_CB_export_num_pixels_need_blending = 0x0000011e,
20073DB_PERF_SEL_DB_CB_context_dones = 0x0000011f,
20074DB_PERF_SEL_DB_CB_eop_dones = 0x00000120,
20075DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 0x00000121,
20076DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 0x00000122,
20077DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 0x00000123,
20078DB_PERF_SEL_SC_DB_tile_backface = 0x00000124,
20079DB_PERF_SEL_SC_DB_quad_quads = 0x00000125,
20080DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 0x00000126,
20081DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 0x00000127,
20082DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 0x00000128,
20083DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 0x00000129,
20084DB_PERF_SEL_DB_SC_quad_double_quad = 0x0000012a,
20085DB_PERF_SEL_SX_DB_quad_export_quads = 0x0000012b,
20086DB_PERF_SEL_SX_DB_quad_double_format = 0x0000012c,
20087DB_PERF_SEL_SX_DB_quad_fast_format = 0x0000012d,
20088DB_PERF_SEL_SX_DB_quad_slow_format = 0x0000012e,
20089DB_PERF_SEL_quad_rd_sends_unc = 0x0000012f,
20090DB_PERF_SEL_quad_rd_mi_stall_unc = 0x00000130,
20091DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 0x00000131,
20092DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 0x00000132,
20093DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 0x00000133,
20094DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 0x00000134,
20095DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 0x00000135,
20096DB_PERF_SEL_noz_waiting_for_postz_done = 0x00000136,
20097DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x1 = 0x00000137,
20098DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x1 = 0x00000138,
20099DB_PERF_SEL_DB_CB_export_quads_vrs_rate_1x2 = 0x00000139,
20100DB_PERF_SEL_DB_CB_export_quads_vrs_rate_2x2 = 0x0000013a,
20101DB_PERF_SEL_RMI_rd_tile_32byte_req = 0x0000013b,
20102DB_PERF_SEL_RMI_rd_z_32byte_req = 0x0000013c,
20103DB_PERF_SEL_RMI_rd_s_32byte_req = 0x0000013d,
20104DB_PERF_SEL_RMI_wr_tile_32byte_req = 0x0000013e,
20105DB_PERF_SEL_RMI_wr_z_32byte_req = 0x0000013f,
20106DB_PERF_SEL_RMI_wr_s_32byte_req = 0x00000140,
20107DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 0x00000141,
20108DB_PERF_SEL_RMI_rd_tile_32byte_ret = 0x00000142,
20109DB_PERF_SEL_RMI_rd_z_32byte_ret = 0x00000143,
20110DB_PERF_SEL_RMI_rd_s_32byte_ret = 0x00000144,
20111DB_PERF_SEL_RMI_wr_tile_32byte_ack = 0x00000145,
20112DB_PERF_SEL_RMI_wr_z_32byte_ack = 0x00000146,
20113DB_PERF_SEL_RMI_wr_s_32byte_ack = 0x00000147,
20114DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 0x00000148,
20115DB_PERF_SEL_esr_vic_sqq_busy = 0x00000149,
20116DB_PERF_SEL_esr_vic_sqq_stall = 0x0000014a,
20117DB_PERF_SEL_esr_psi_vic_tile_rate = 0x0000014b,
20118DB_PERF_SEL_esr_vic_footprint_match_2x2 = 0x0000014c,
20119DB_PERF_SEL_esr_vic_footprint_match_2x1 = 0x0000014d,
20120DB_PERF_SEL_esr_vic_footprint_match_1x2 = 0x0000014e,
20121DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 0x0000014f,
20122DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 0x00000150,
20123DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 0x00000151,
20124DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 0x00000152,
20125DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 0x00000153,
20126DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 0x00000154,
20127DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 0x00000155,
20128DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 0x00000156,
20129DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 0x00000157,
20130DB_PERF_SEL_ts_events_pws_enable = 0x00000158,
20131DB_PERF_SEL_ps_events_pws_enable = 0x00000159,
20132DB_PERF_SEL_cs_events_pws_enable = 0x0000015a,
20133DB_PERF_SEL_DB_SC_quad_noz_tiles = 0x0000015b,
20134DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 0x0000015c,
20135DB_PERF_SEL_DB_SC_quad_conflicts = 0x0000015d,
20136DB_PERF_SEL_SC_DB_quad_vrs_1x1 = 0x0000015e,
20137DB_PERF_SEL_SC_DB_quad_vrs_1x2 = 0x0000015f,
20138DB_PERF_SEL_SC_DB_quad_vrs_2x1 = 0x00000160,
20139DB_PERF_SEL_SC_DB_quad_vrs_2x2 = 0x00000161,
20140DB_PERF_SEL_SC_DB_quad_vrs_2x_ssaa = 0x00000162,
20141DB_PERF_SEL_SC_DB_quad_vrs_4x_ssaa = 0x00000163,
20142DB_PERF_SEL_SC_DB_quad_vrs_8x_ssaa = 0x00000164,
20143DB_PERF_SEL_SC_DB_wave_sends = 0x00000165,
20144DB_PERF_SEL_SC_DB_wave_busy = 0x00000166,
20145DB_PERF_SEL_SC_DB_wave_quads = 0x00000167,
20146DB_PERF_SEL_SC_DB_wave_id_wrapped = 0x00000168,
20147DB_PERF_SEL_DB_SC_wave_sends = 0x00000169,
20148DB_PERF_SEL_DB_SC_wave_busy = 0x0000016a,
20149DB_PERF_SEL_DB_SC_wave_stalls = 0x0000016b,
20150DB_PERF_SEL_DB_SC_wave_conflict = 0x0000016c,
20151DB_PERF_SEL_DB_SC_wave_hard_conflict = 0x0000016d,
20152DB_PERF_SEL_DB_SC_wave_id_wrapped = 0x0000016e,
20153DB_PERF_SEL_SX_DB_quad_waves = 0x0000016f,
20154DB_PERF_SEL_pws_stall = 0x00000170,
20155DB_PERF_SEL_pws_liveness_stall_dtt_tag = 0x00000171,
20156DB_PERF_SEL_pws_liveness_stall_tcp_cache_mgr = 0x00000172,
20157DB_PERF_SEL_OREO_TT_load = 0x00000173,
20158DB_PERF_SEL_OREO_TT_read = 0x00000174,
20159DB_PERF_SEL_OREO_TT_stalls = 0x00000175,
20160DB_PERF_SEL_OREO_ST_load = 0x00000176,
20161DB_PERF_SEL_OREO_ST_read = 0x00000177,
20162DB_PERF_SEL_OREO_ST_stalls = 0x00000178,
20163DB_PERF_SEL_OREO_WT_load = 0x00000179,
20164DB_PERF_SEL_OREO_WT_read = 0x0000017a,
20165DB_PERF_SEL_OREO_SB_misses = 0x0000017b,
20166DB_PERF_SEL_OREO_SB_hits = 0x0000017c,
20167DB_PERF_SEL_OREO_SB_evicts = 0x0000017d,
20168DB_PERF_SEL_OREO_SB_stalls = 0x0000017e,
20169DB_PERF_SEL_OREO_Events_load = 0x0000017f,
20170DB_PERF_SEL_OREO_Events_transition = 0x00000180,
20171DB_PERF_SEL_OREO_Events_non_transition = 0x00000181,
20172DB_PERF_SEL_OREO_Events_delayed = 0x00000182,
20173DB_PERF_SEL_OREO_Events_stalls = 0x00000183,
20174} PerfCounter_Vals;
20175
20176/*
20177 * PixelPipeCounterId enum
20178 */
20179
20180typedef enum PixelPipeCounterId {
20181PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000,
20182PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001,
20183PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002,
20184PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003,
20185PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x00000004,
20186PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x00000005,
20187PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x00000006,
20188PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x00000007,
20189} PixelPipeCounterId;
20190
20191/*
20192 * PixelPipeStride enum
20193 */
20194
20195typedef enum PixelPipeStride {
20196PIXEL_PIPE_STRIDE_32_BITS = 0x00000000,
20197PIXEL_PIPE_STRIDE_64_BITS = 0x00000001,
20198PIXEL_PIPE_STRIDE_128_BITS = 0x00000002,
20199PIXEL_PIPE_STRIDE_256_BITS = 0x00000003,
20200} PixelPipeStride;
20201
20202/*
20203 * RingCounterControl enum
20204 */
20205
20206typedef enum RingCounterControl {
20207COUNTER_RING_SPLIT = 0x00000000,
20208COUNTER_RING_0 = 0x00000001,
20209COUNTER_RING_1 = 0x00000002,
20210} RingCounterControl;
20211
20212/*
20213 * StencilOp enum
20214 */
20215
20216typedef enum StencilOp {
20217STENCIL_KEEP = 0x00000000,
20218STENCIL_ZERO = 0x00000001,
20219STENCIL_ONES = 0x00000002,
20220STENCIL_REPLACE_TEST = 0x00000003,
20221STENCIL_REPLACE_OP = 0x00000004,
20222STENCIL_ADD_CLAMP = 0x00000005,
20223STENCIL_SUB_CLAMP = 0x00000006,
20224STENCIL_INVERT = 0x00000007,
20225STENCIL_ADD_WRAP = 0x00000008,
20226STENCIL_SUB_WRAP = 0x00000009,
20227STENCIL_AND = 0x0000000a,
20228STENCIL_OR = 0x0000000b,
20229STENCIL_XOR = 0x0000000c,
20230STENCIL_NAND = 0x0000000d,
20231STENCIL_NOR = 0x0000000e,
20232STENCIL_XNOR = 0x0000000f,
20233} StencilOp;
20234
20235/*
20236 * ZLimitSumm enum
20237 */
20238
20239typedef enum ZLimitSumm {
20240FORCE_SUMM_OFF = 0x00000000,
20241FORCE_SUMM_MINZ = 0x00000001,
20242FORCE_SUMM_MAXZ = 0x00000002,
20243FORCE_SUMM_BOTH = 0x00000003,
20244} ZLimitSumm;
20245
20246/*
20247 * ZModeForce enum
20248 */
20249
20250typedef enum ZModeForce {
20251NO_FORCE = 0x00000000,
20252FORCE_EARLY_Z = 0x00000001,
20253FORCE_LATE_Z = 0x00000002,
20254FORCE_RE_Z = 0x00000003,
20255} ZModeForce;
20256
20257/*
20258 * ZOrder enum
20259 */
20260
20261typedef enum ZOrder {
20262LATE_Z = 0x00000000,
20263EARLY_Z_THEN_LATE_Z = 0x00000001,
20264RE_Z = 0x00000002,
20265EARLY_Z_THEN_RE_Z = 0x00000003,
20266} ZOrder;
20267
20268/*
20269 * ZSamplePosition enum
20270 */
20271
20272typedef enum ZSamplePosition {
20273Z_SAMPLE_CENTER = 0x00000000,
20274Z_SAMPLE_CENTROID = 0x00000001,
20275} ZSamplePosition;
20276
20277/*
20278 * SU_PERFCNT_SEL enum
20279 */
20280
20281typedef enum SU_PERFCNT_SEL {
20282PERF_PAPC_PASX_REQ = 0x00000000,
20283PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006,
20284PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007,
20285PERF_CLPR_INPUT_PRIM = 0x00000008,
20286PERF_CLPR_INPUT_NULL_PRIM = 0x00000009,
20287PERF_CLPR_INPUT_EVENT = 0x0000000a,
20288PERF_CLPR_INPUT_FIRST_OF_SUBGROUP = 0x0000000b,
20289PERF_CLPR_INPUT_END_OF_PACKET = 0x0000000c,
20290PERF_CLPR_INPUT_EXTENDED_EVENT = 0x0000000d,
20291PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e,
20292PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f,
20293PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010,
20294PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011,
20295PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012,
20296PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013,
20297PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014,
20298PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015,
20299PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016,
20300PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017,
20301PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018,
20302PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019,
20303PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a,
20304PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b,
20305PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c,
20306PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d,
20307PERF_CLPR_CLIP_PLANE_CNT_9_PLUS = 0x0000001e,
20308PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f,
20309PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020,
20310PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021,
20311PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022,
20312PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023,
20313PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024,
20314PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026,
20315PERF_PAPC_CLSM_NULL_PRIM = 0x00000027,
20316PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028,
20317PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029,
20318PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a,
20319PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b,
20320PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c,
20321PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d,
20322PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e,
20323PERF_PAPC_CLSM_OUT_PRIM_CNT_9_PLUS = 0x0000002f,
20324PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030,
20325PERF_PAPC_SU_INPUT_PRIM = 0x00000031,
20326PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032,
20327PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033,
20328PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034,
20329PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035,
20330PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036,
20331PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037,
20332PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038,
20333PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039,
20334PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a,
20335PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b,
20336PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c,
20337PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d,
20338PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e,
20339PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f,
20340PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040,
20341PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041,
20342PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042,
20343PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043,
20344PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044,
20345PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045,
20346PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046,
20347PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047,
20348PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048,
20349PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049,
20350PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a,
20351PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b,
20352PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c,
20353PERF_PAPC_PASX_REQ_IDLE = 0x0000004d,
20354PERF_PAPC_PASX_REQ_BUSY = 0x0000004e,
20355PERF_PAPC_PASX_REQ_STALLED = 0x0000004f,
20356PERF_PAPC_PASX_REC_IDLE = 0x00000050,
20357PERF_PAPC_PASX_REC_BUSY = 0x00000051,
20358PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052,
20359PERF_PAPC_PASX_REC_STALLED = 0x00000053,
20360PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054,
20361PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055,
20362PERF_PAPC_CCGSM_IDLE = 0x00000056,
20363PERF_PAPC_CCGSM_BUSY = 0x00000057,
20364PERF_PAPC_CCGSM_STALLED = 0x00000058,
20365PERF_PAPC_CLPRIM_IDLE = 0x00000059,
20366PERF_PAPC_CLPRIM_BUSY = 0x0000005a,
20367PERF_PAPC_CLPRIM_STALLED = 0x0000005b,
20368PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c,
20369PERF_PAPC_CLIPSM_IDLE = 0x0000005d,
20370PERF_PAPC_CLIPSM_BUSY = 0x0000005e,
20371PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f,
20372PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060,
20373PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061,
20374PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062,
20375PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063,
20376PERF_PAPC_CLIPGA_IDLE = 0x00000064,
20377PERF_PAPC_CLIPGA_BUSY = 0x00000065,
20378PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066,
20379PERF_PAPC_CLIPGA_STALLED = 0x00000067,
20380PERF_PAPC_CLIP_IDLE = 0x00000068,
20381PERF_PAPC_CLIP_BUSY = 0x00000069,
20382PERF_PAPC_SU_IDLE = 0x0000006a,
20383PERF_PAPC_SU_BUSY = 0x0000006b,
20384PERF_PAPC_SU_STARVED_CLIP = 0x0000006c,
20385PERF_PAPC_SU_STALLED_SC = 0x0000006d,
20386PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e,
20387PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f,
20388PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070,
20389PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078,
20390PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079,
20391PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b,
20392PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c,
20393PERF_PAPC_SU_ALL_OUTPUT_PRIM = 0x0000007d,
20394PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e,
20395PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f,
20396PERF_PAPC_SU_ALL_OUTPUT_NULL_PRIM = 0x00000080,
20397PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083,
20398PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084,
20399PERF_PAPC_SU_ALL_STALLED_SC = 0x00000085,
20400PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086,
20401PERF_PAPC_SU_CULLED_PRIM = 0x00000087,
20402PERF_PAPC_SU_OUTPUT_EOPG = 0x00000088,
20403PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x00000089,
20404PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x0000008a,
20405PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x0000008b,
20406PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x0000008c,
20407PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x0000008d,
20408PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x0000008e,
20409PERF_PAPC_SU_SE2_STALLED_SC = 0x00000097,
20410PERF_PAPC_SU_SE3_STALLED_SC = 0x00000098,
20411PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 0x00000099,
20412PERF_SMALL_PRIM_CULL_PRIM_1X1 = 0x0000009a,
20413PERF_SMALL_PRIM_CULL_PRIM_2X1 = 0x0000009b,
20414PERF_SMALL_PRIM_CULL_PRIM_1X2 = 0x0000009c,
20415PERF_SMALL_PRIM_CULL_PRIM_2X2 = 0x0000009d,
20416PERF_SMALL_PRIM_CULL_PRIM_3X1 = 0x0000009e,
20417PERF_SMALL_PRIM_CULL_PRIM_1X3 = 0x0000009f,
20418PERF_SMALL_PRIM_CULL_PRIM_3X2 = 0x000000a0,
20419PERF_SMALL_PRIM_CULL_PRIM_2X3 = 0x000000a1,
20420PERF_SMALL_PRIM_CULL_PRIM_NX1 = 0x000000a2,
20421PERF_SMALL_PRIM_CULL_PRIM_1XN = 0x000000a3,
20422PERF_SMALL_PRIM_CULL_PRIM_NX2 = 0x000000a4,
20423PERF_SMALL_PRIM_CULL_PRIM_2XN = 0x000000a5,
20424PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 0x000000a9,
20425PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000aa,
20426PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 0x000000ab,
20427PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ac,
20428PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 0x000000ad,
20429PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ae,
20430PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 0x000000af,
20431PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000b0,
20432PERF_PA_VERTEX_FIFO_FULL = 0x000000b1,
20433PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 0x000000b2,
20434PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 0x000000b3,
20435PERF_ENGG_CSB_MACHINE_IS_STARVED = 0x000000b7,
20436PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 0x000000b8,
20437PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 0x000000b9,
20438PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 0x000000ba,
20439PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 0x000000bc,
20440PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 0x000000bd,
20441PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 0x000000be,
20442PERF_ENGG_CSB_NULL_SUBGROUP = 0x000000bf,
20443PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 0x000000c0,
20444PERF_ENGG_CSB_GE_MEMORY_FULL = 0x000000c1,
20445PERF_ENGG_CSB_GE_MEMORY_EMPTY = 0x000000c2,
20446PERF_ENGG_CSB_SPI_MEMORY_FULL = 0x000000c3,
20447PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 0x000000c4,
20448PERF_ENGG_INDEX_REQ_NULL_REQUEST = 0x000000e0,
20449PERF_ENGG_INDEX_RET_0_NEW_VERTS_THIS_PRIM = 0x000000e1,
20450PERF_ENGG_INDEX_RET_1_NEW_VERTS_THIS_PRIM = 0x000000e2,
20451PERF_ENGG_INDEX_RET_2_NEW_VERTS_THIS_PRIM = 0x000000e3,
20452PERF_ENGG_INDEX_RET_3_NEW_VERTS_THIS_PRIM = 0x000000e4,
20453PERF_ENGG_INDEX_REQ_STARVED = 0x000000e5,
20454PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x000000e6,
20455PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x000000e7,
20456PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 0x000000e8,
20457PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 0x000000e9,
20458PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 0x000000ea,
20459PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 0x000000eb,
20460PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 0x000000ec,
20461PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 0x000000ed,
20462PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 0x000000ee,
20463PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 0x000000ef,
20464PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 0x000000f0,
20465PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 0x000000f1,
20466PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 0x000000f2,
20467PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 0x000000f3,
20468PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 0x000000f4,
20469PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 0x000000f5,
20470PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 0x000000f6,
20471PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 0x000000f7,
20472PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 0x000000f8,
20473PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 0x000000f9,
20474PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 0x000000fa,
20475PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 0x000000fb,
20476PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 0x000000fc,
20477PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 0x00000102,
20478PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 0x00000103,
20479PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 0x00000104,
20480PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 0x00000105,
20481PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 0x00000106,
20482PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 0x00000107,
20483PERF_ENGG_POS_REQ_STARVED = 0x00000108,
20484PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 0x00000109,
20485PERF_ENGG_BUSY = 0x0000010a,
20486PERF_CLIPSM_CULL_PRIMS_CNT = 0x0000010b,
20487PERF_PH_SEND_1_SC = 0x0000010c,
20488PERF_PH_SEND_2_SC = 0x0000010d,
20489PERF_PH_SEND_3_SC = 0x0000010e,
20490PERF_PH_SEND_4_SC = 0x0000010f,
20491PERF_OUTPUT_PRIM_1_SC = 0x00000110,
20492PERF_OUTPUT_PRIM_2_SC = 0x00000111,
20493PERF_OUTPUT_PRIM_3_SC = 0x00000112,
20494PERF_OUTPUT_PRIM_4_SC = 0x00000113,
20495PERF_PASX_POS_VECTOR = 0x00000114,
20496PERF_PASX_MISC_VECTOR = 0x00000115,
20497PERF_PASX_CCDIST0_VECTOR = 0x00000116,
20498PERF_PASX_CCDIST1_VECTOR = 0x00000117,
20499PERF_PASX_STEREO_POS_VECTOR = 0x00000118,
20500PERF_CLPR_INPUT_SEND = 0x00000119,
20501PERF_SU_INPUT_SEND = 0x0000011a,
20502PERF_SU_OUTPUT_SEND = 0x0000011b,
20503PERF_PAPC_SU_SE4_PRIM_FILTER_CULL = 0x0000011c,
20504PERF_PAPC_SU_SE5_PRIM_FILTER_CULL = 0x0000011d,
20505PERF_PAPC_SU_SE4_OUTPUT_PRIM = 0x0000011e,
20506PERF_PAPC_SU_SE5_OUTPUT_PRIM = 0x0000011f,
20507PERF_PAPC_SU_SE4_OUTPUT_NULL_PRIM = 0x00000120,
20508PERF_PAPC_SU_SE5_OUTPUT_NULL_PRIM = 0x00000121,
20509PERF_PAPC_SU_SE4_STALLED_SC = 0x00000122,
20510PERF_PAPC_SU_SE5_STALLED_SC = 0x00000123,
20511PERF_ENGG_INDEX_RET0_NEW_VERTS = 0x00000124,
20512PERF_ENGG_INDEX_RET1_NEW_VERTS = 0x00000125,
20513PERF_ENGG_INDEX_RET2_NEW_VERTS = 0x00000126,
20514PERF_ENGG_INDEX_RET3_NEW_VERTS = 0x00000127,
20515PERF_ENGG_INDEX_RET4_NEW_VERTS = 0x00000128,
20516PERF_ENGG_INDEX_RET5_NEW_VERTS = 0x00000129,
20517PERF_ENGG_INDEX_RET6_NEW_VERTS = 0x0000012a,
20518PERF_ENGG_INDEX_RET7_NEW_VERTS = 0x0000012b,
20519PERF_ENGG_INDEX_RET8_NEW_VERTS = 0x0000012c,
20520PERF_ENGG_INDEX_RET9_NEW_VERTS = 0x0000012d,
20521PERF_ENGG_INDEX_RET10_NEW_VERTS = 0x0000012e,
20522PERF_ENGG_INDEX_RET11_NEW_VERTS = 0x0000012f,
20523PERF_ENGG_INDEX_RET12_NEW_VERTS = 0x00000130,
20524PERF_PH_SEND_5_SC = 0x00000131,
20525PERF_PH_SEND_6_SC = 0x00000132,
20526PERF_OUTPUT_PRIM_5_SC = 0x00000133,
20527PERF_OUTPUT_PRIM_6_SC = 0x00000134,
20528PERF_CLPR_BACK_PRIM = 0x00000135,
20529PERF_PA_BUSY = 0x00000136,
20530} SU_PERFCNT_SEL;
20531
20532/*
20533 * RMIPerfSel enum
20534 */
20535
20536typedef enum RMIPerfSel {
20537RMI_PERF_SEL_NONE = 0x00000000,
20538RMI_PERF_SEL_BUSY = 0x00000001,
20539RMI_PERF_SEL_REG_CLK_VLD = 0x00000002,
20540RMI_PERF_SEL_DYN_CLK_CMN_VLD = 0x00000003,
20541RMI_PERF_SEL_DYN_CLK_RB_VLD = 0x00000004,
20542RMI_PERF_SEL_DYN_CLK_PERF_VLD = 0x00000005,
20543RMI_PERF_SEL_PERF_WINDOW = 0x00000006,
20544RMI_PERF_SEL_EVENT_SEND = 0x00000007,
20545RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0x00000008,
20546RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY = 0x00000009,
20547RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 0x0000000a,
20548RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 0x0000000b,
20549RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 0x0000000c,
20550RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 0x0000000d,
20551RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 0x0000000e,
20552RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 0x0000000f,
20553RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 0x00000010,
20554RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 0x00000011,
20555RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID = 0x00000012,
20556RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000013,
20557RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 0x00000014,
20558RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 0x00000015,
20559RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 0x00000016,
20560RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 0x00000017,
20561RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 0x00000018,
20562RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 0x00000019,
20563RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 0x0000001a,
20564RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 0x0000001b,
20565RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 0x0000001c,
20566RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 0x0000001d,
20567RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 0x0000001e,
20568RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 0x0000001f,
20569RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 0x00000020,
20570RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 0x00000021,
20571RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 0x00000022,
20572RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 0x00000023,
20573RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 0x00000024,
20574RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY = 0x00000025,
20575RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 0x00000026,
20576RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 0x00000027,
20577RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 0x00000028,
20578RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 0x00000029,
20579RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 0x0000002a,
20580RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 0x0000002b,
20581RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 0x0000002c,
20582RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 0x0000002d,
20583RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 0x0000002e,
20584RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 0x0000002f,
20585RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 0x00000030,
20586RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 0x00000031,
20587RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 0x00000032,
20588RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 0x00000033,
20589RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 0x00000034,
20590RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 0x00000035,
20591RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 0x00000036,
20592RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000037,
20593RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 0x00000038,
20594RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 0x00000039,
20595RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 0x0000003a,
20596RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 0x0000003b,
20597RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 0x0000003c,
20598RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 0x0000003d,
20599RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 0x0000003e,
20600RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 0x0000003f,
20601RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 0x00000040,
20602RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 0x00000041,
20603RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 0x00000042,
20604RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 0x00000043,
20605RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 0x00000044,
20606RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 0x00000045,
20607RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 0x00000046,
20608RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX = 0x00000047,
20609RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY = 0x00000048,
20610RMI_PERF_SEL_RB_RMI_WR_IDLE = 0x00000049,
20611RMI_PERF_SEL_RB_RMI_WR_STARVE = 0x0000004a,
20612RMI_PERF_SEL_RB_RMI_WR_STALL = 0x0000004b,
20613RMI_PERF_SEL_RB_RMI_WR_BUSY = 0x0000004c,
20614RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY = 0x0000004d,
20615RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX = 0x0000004e,
20616RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY = 0x0000004f,
20617RMI_PERF_SEL_RB_RMI_RD_IDLE = 0x00000050,
20618RMI_PERF_SEL_RB_RMI_RD_STARVE = 0x00000051,
20619RMI_PERF_SEL_RB_RMI_RD_STALL = 0x00000052,
20620RMI_PERF_SEL_RB_RMI_RD_BUSY = 0x00000053,
20621RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY = 0x00000054,
20622RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID = 0x00000055,
20623RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID = 0x00000056,
20624RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 0x00000057,
20625RMI_PERF_SEL_RMI_TC_REQ_BUSY = 0x00000058,
20626RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 0x00000059,
20627RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 0x0000005a,
20628RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 0x0000005b,
20629RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 0x0000005c,
20630RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 0x0000005d,
20631RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 0x0000005e,
20632RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 0x0000005f,
20633RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 0x00000060,
20634RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 0x00000061,
20635RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 0x00000062,
20636RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 0x00000063,
20637RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 0x00000064,
20638RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 0x00000065,
20639RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 0x00000066,
20640RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 0x00000067,
20641RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 0x00000068,
20642RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 0x00000069,
20643RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 0x0000006a,
20644RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 0x0000006b,
20645RMI_PERF_SEL_RMI_TC_STALL_RDREQ = 0x0000006c,
20646RMI_PERF_SEL_RMI_TC_STALL_WRREQ = 0x0000006d,
20647RMI_PERF_SEL_RMI_TC_STALL_ALLREQ = 0x0000006e,
20648RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND = 0x0000006f,
20649RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND = 0x00000070,
20650RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 0x00000071,
20651RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 0x00000072,
20652RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 0x00000073,
20653RMI_PERF_SEL_TCIW_REQ = 0x00000074,
20654RMI_PERF_SEL_TCIW_BUSY = 0x00000075,
20655RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 0x00000076,
20656RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 0x00000077,
20657RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 0x00000078,
20658RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 0x00000079,
20659RMI_PERF_SEL_REORDER_FIFO_REQ = 0x0000007a,
20660RMI_PERF_SEL_REORDER_FIFO_BUSY = 0x0000007b,
20661RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 0x0000007c,
20662RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 0x0000007d,
20663RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 0x0000007e,
20664RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 0x0000007f,
20665RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 0x00000080,
20666RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 0x00000081,
20667RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 0x00000082,
20668RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 0x00000083,
20669RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 0x00000084,
20670RMI_PERF_SEL_CONSUMER_PROBEGEN_READ_RTS_RTR = 0x00000085,
20671RMI_PERF_SEL_CONSUMER_PROBEGEN_WRITE_RTS_RTR = 0x00000086,
20672RMI_PERF_SEL_CONSUMER_PROBEGEN_IN0_RTS_RTR = 0x00000087,
20673RMI_PERF_SEL_CONSUMER_PROBEGEN_IN1_RTS_RTR = 0x00000088,
20674RMI_PERF_SEL_CONSUMER_PROBEGEN_CB_RTS_RTR = 0x00000089,
20675RMI_PERF_SEL_CONSUMER_PROBEGEN_DB_RTS_RTR = 0x0000008a,
20676} RMIPerfSel;
20677
20678/*
20679 * UTCL1PerfSel enum
20680 */
20681
20682typedef enum UTCL1PerfSel {
20683UTCL1_PERF_SEL_NONE = 0x00000000,
20684UTCL1_PERF_SEL_REQS = 0x00000001,
20685UTCL1_PERF_SEL_HITS = 0x00000002,
20686UTCL1_PERF_SEL_MISSES = 0x00000003,
20687UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 0x00000004,
20688UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 0x00000005,
20689UTCL1_PERF_SEL_UTCL2_REQS = 0x00000006,
20690UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 0x00000007,
20691UTCL1_PERF_SEL_UTCL2_RET_FAULT = 0x00000008,
20692UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 0x00000009,
20693UTCL1_PERF_SEL_STALL_MH_FULL = 0x0000000a,
20694UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 0x0000000b,
20695UTCL1_PERF_SEL_UTCL2_RET_CNT = 0x0000000c,
20696UTCL1_PERF_SEL_RTNS = 0x0000000d,
20697UTCL1_PERF_SEL_XLAT_REQ_BUSY = 0x0000000e,
20698UTCL1_PERF_SEL_RANGE_INVREQS = 0x0000000f,
20699UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 0x00000010,
20700UTCL1_PERF_SEL_BYPASS_REQS = 0x00000011,
20701UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 0x00000012,
20702UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 0x00000013,
20703UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 0x00000014,
20704UTCL1_PERF_SEL_CP_INVREQS = 0x00000015,
20705UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 0x00000016,
20706UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4K_64K = 0x00000017,
20707UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_64K_256K = 0x00000018,
20708UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_256K_512K = 0x00000019,
20709UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_512K_1M = 0x0000001a,
20710UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_1M_2M = 0x0000001b,
20711UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_2M_4M = 0x0000001c,
20712UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_4M_8M = 0x0000001d,
20713UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_8M_16M = 0x0000001e,
20714UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_16M_32M = 0x0000001f,
20715UTCL1_PERF_SEL_NUM_UTCL2_RTN_SIZE_32M_INF = 0x00000020,
20716UTCL1_PERF_SEL_UTCL2_REQ_SQUASHED_NUM = 0x00000021,
20717UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_0 = 0x00000022,
20718UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_1 = 0x00000023,
20719UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_2 = 0x00000024,
20720UTCL1_PERF_SEL_REQ_NUM_CACHE_CORE_3 = 0x00000025,
20721UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_0 = 0x00000026,
20722UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_1 = 0x00000027,
20723UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_2 = 0x00000028,
20724UTCL1_PERF_SEL_STALL_CYCLES_CACHE_CORE_3 = 0x00000029,
20725UTCL1_PERF_SEL_UTCL1_UTCL2_INVACKS = 0x0000002a,
20726UTCL1_PERF_SEL_UTCL0_UTCL1_INVACKS = 0x0000002b,
20727UTCL1_PERF_SEL_HITS_PG_SIZE_1 = 0x0000002c,
20728UTCL1_PERF_SEL_HITS_PG_SIZE_2 = 0x0000002d,
20729UTCL1_PERF_SEL_HITS_PG_SIZE_3 = 0x0000002e,
20730UTCL1_PERF_SEL_HITS_PG_SIZE_4 = 0x0000002f,
20731UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_0 = 0x00000030,
20732UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_1 = 0x00000031,
20733UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_2 = 0x00000032,
20734UTCL1_PERF_SEL_REQ_TO_MISS_HNDLR_3 = 0x00000033,
20735UTCL1_PERF_SEL_AVG_INV_LATENCY = 0x00000034,
20736UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC0 = 0x00000035,
20737UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC1 = 0x00000036,
20738UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC2 = 0x00000037,
20739UTCL1_PERF_SEL_NUM_OF_CYCLES_RQ_EXISTS_TO_CC3 = 0x00000038,
20740UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC0 = 0x00000039,
20741UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC1 = 0x0000003a,
20742UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC2 = 0x0000003b,
20743UTCL1_PERF_SEL_NUM_OF_CYCLES_W_COLLISION_CC3 = 0x0000003c,
20744UTCL1_PERF_SEL_EVICTIONS_NUM_CC0 = 0x0000003d,
20745UTCL1_PERF_SEL_EVICTIONS_NUM_CC1 = 0x0000003e,
20746UTCL1_PERF_SEL_EVICTIONS_NUM_CC2 = 0x0000003f,
20747UTCL1_PERF_SEL_EVICTIONS_NUM_CC3 = 0x00000040,
20748UTCL1_PERF_SEL_ALOG_INTERRUPT = 0x00000041,
20749UTCL1_PERF_SEL_ALOG_INTERRUPT_DROPPED = 0x00000042,
20750UTCL1_PERF_SEL_ALOG_CACHE_REQ = 0x00000043,
20751UTCL1_PERF_SEL_ALOG_CACHE_HIT = 0x00000044,
20752UTCL1_PERF_SEL_ALOG_STALL_PMM_CREDITS = 0x00000045,
20753} UTCL1PerfSel;
20754
20755/*
20756 * GC_EA_SE_PERFCOUNT_SEL enum
20757 */
20758
20759typedef enum GC_EA_SE_PERFCOUNT_SEL {
20760GC_EA_SE_PERF_SEL_ALWAYS_COUNT = 0x00000000,
20761GC_EA_SE_PERF_SEL_RDRAM_NUM_BANKS_VLD = 0x00000001,
20762GC_EA_SE_PERF_SEL_RDRAM_REQ_PER_CLIGRP = 0x00000002,
20763GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_CLIGRP = 0x00000003,
20764GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START0 = 0x00000004,
20765GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END0 = 0x00000005,
20766GC_EA_SE_PERF_SEL_RDRAM_LATENCY_START1 = 0x00000006,
20767GC_EA_SE_PERF_SEL_RDRAM_LATENCY_END1 = 0x00000007,
20768GC_EA_SE_PERF_SEL_WDRAM_NUM_BANKS_VLD = 0x00000008,
20769GC_EA_SE_PERF_SEL_WDRAM_REQ_PER_CLIGRP = 0x00000009,
20770GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_CLIGRP = 0x0000000a,
20771GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START0 = 0x0000000b,
20772GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END0 = 0x0000000c,
20773GC_EA_SE_PERF_SEL_WDRAM_LATENCY_START1 = 0x0000000d,
20774GC_EA_SE_PERF_SEL_WDRAM_LATENCY_END1 = 0x0000000e,
20775GC_EA_SE_PERF_SEL_RGMI_NUM_BANKS_VLD = 0x0000000f,
20776GC_EA_SE_PERF_SEL_RGMI_REQ_PER_CLIGRP = 0x00000010,
20777GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_CLIGR = 0x00000011,
20778GC_EA_SE_PERF_SEL_RGMI_LATENCY_START0 = 0x00000012,
20779GC_EA_SE_PERF_SEL_RGMI_LATENCY_END0 = 0x00000013,
20780GC_EA_SE_PERF_SEL_RGMI_LATENCY_START1 = 0x00000014,
20781GC_EA_SE_PERF_SEL_RGMI_LATENCY_END1 = 0x00000015,
20782GC_EA_SE_PERF_SEL_WGMI_NUM_BANKS_VLD = 0x00000016,
20783GC_EA_SE_PERF_SEL_WGMI_REQ_PER_CLIGRP = 0x00000017,
20784GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_CLIGRP = 0x00000018,
20785GC_EA_SE_PERF_SEL_WGMI_LATENCY_START0 = 0x00000019,
20786GC_EA_SE_PERF_SEL_WGMI_LATENCY_END0 = 0x0000001a,
20787GC_EA_SE_PERF_SEL_WGMI_LATENCY_START1 = 0x0000001b,
20788GC_EA_SE_PERF_SEL_WGMI_LATENCY_END1 = 0x0000001c,
20789GC_EA_SE_PERF_SEL_RIO_REQ_PER_CLIGRP = 0x0000001d,
20790GC_EA_SE_PERF_SEL_RIO_SIZE_REQ = 0x0000001e,
20791GC_EA_SE_PERF_SEL_RIO_GRP0_SIZE_REQ = 0x0000001f,
20792GC_EA_SE_PERF_SEL_RIO_GRP1_SIZE_REQ = 0x00000020,
20793GC_EA_SE_PERF_SEL_RIO_GRP2_SIZE_REQ = 0x00000021,
20794GC_EA_SE_PERF_SEL_RIO_GRP3_SIZE_REQ = 0x00000022,
20795GC_EA_SE_PERF_SEL_RIO_LATENCY_START0 = 0x00000023,
20796GC_EA_SE_PERF_SEL_RIO_LATENCY_END0 = 0x00000024,
20797GC_EA_SE_PERF_SEL_RIO_LATENCY_START1 = 0x00000025,
20798GC_EA_SE_PERF_SEL_RIO_LATENCY_END1 = 0x00000026,
20799GC_EA_SE_PERF_SEL_WIO_REQ_PER_CLIGRP = 0x00000027,
20800GC_EA_SE_PERF_SEL_WIO_CHAINED_REQ_PER_CLIGRP = 0x00000028,
20801GC_EA_SE_PERF_SEL_WIO_SIZE_REQ = 0x00000029,
20802GC_EA_SE_PERF_SEL_WIO_GRP0_SIZE_REQ = 0x0000002a,
20803GC_EA_SE_PERF_SEL_WIO_GRP1_SIZE_REQ = 0x0000002b,
20804GC_EA_SE_PERF_SEL_WIO_GRP2_SIZE_REQ = 0x0000002c,
20805GC_EA_SE_PERF_SEL_WIO_GRP3_SIZE_REQ = 0x0000002d,
20806GC_EA_SE_PERF_SEL_WIO_LATENCY_START0 = 0x0000002e,
20807GC_EA_SE_PERF_SEL_WIO_LATENCY_END0 = 0x0000002f,
20808GC_EA_SE_PERF_SEL_WIO_LATENCY_START1 = 0x00000030,
20809GC_EA_SE_PERF_SEL_WIO_LATENCY_END1 = 0x00000031,
20810GC_EA_SE_PERF_SEL_SARB_REQ_PER_VC = 0x00000032,
20811GC_EA_SE_PERF_SEL_SARB_DRAM_REQ_PER_VC = 0x00000033,
20812GC_EA_SE_PERF_SEL_SARB_GMI_REQ_PER_VC = 0x00000034,
20813GC_EA_SE_PERF_SEL_SARB_IO_REQ_PER_VC = 0x00000035,
20814GC_EA_SE_PERF_SEL_SARB_SIZE_REQ = 0x00000036,
20815GC_EA_SE_PERF_SEL_SARB_DRAM_SIZE_REQ = 0x00000037,
20816GC_EA_SE_PERF_SEL_SARB_GMI_SIZE_REQ = 0x00000038,
20817GC_EA_SE_PERF_SEL_SARB_IO_SIZE_REQ = 0x00000039,
20818GC_EA_SE_PERF_SEL_SARB_LATENCY_START0 = 0x0000003a,
20819GC_EA_SE_PERF_SEL_SARB_LATENCY_END0 = 0x0000003b,
20820GC_EA_SE_PERF_SEL_SARB_LATENCY_START1 = 0x0000003c,
20821GC_EA_SE_PERF_SEL_SARB_LATENCY_END1 = 0x0000003d,
20822GC_EA_SE_PERF_SEL_SARB_BUSY = 0x0000003e,
20823GC_EA_SE_PERF_SEL_SARB_STALLED = 0x0000003f,
20824GC_EA_SE_PERF_SEL_SARB_STARVING = 0x00000040,
20825GC_EA_SE_PERF_SEL_SARB_IDLE = 0x00000041,
20826GC_EA_SE_PERF_SEL_RRET_VLD = 0x00000042,
20827GC_EA_SE_PERF_SEL_WRET_VLD = 0x00000043,
20828GC_EA_SE_PERF_SEL_PRB_REQ = 0x00000044,
20829GC_EA_SE_PERF_SEL_MAM_ARAM_FA_EVICT = 0x00000045,
20830GC_EA_SE_PERF_SEL_MAM_ARAM_REQ_VLD = 0x00000046,
20831GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT = 0x00000047,
20832GC_EA_SE_PERF_SEL_MAM_NUM_DQRY = 0x00000048,
20833GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT = 0x00000049,
20834GC_EA_SE_PERF_SEL_MAM_AFLUSH_INTERRUPT_STALLED = 0x0000004a,
20835GC_EA_SE_PERF_SEL_MAM_AFLUSH_COMPLETED = 0x0000004b,
20836GC_EA_SE_PERF_SEL_MAM_AFLUSH_ONGOING = 0x0000004c,
20837GC_EA_SE_PERF_SEL_RDRAM_SIZE_REQ = 0x0000004d,
20838GC_EA_SE_PERF_SEL_WDRAM_SIZE_REQ = 0x0000004e,
20839GC_EA_SE_PERF_SEL_RGMI_SIZE_REQ = 0x0000004f,
20840GC_EA_SE_PERF_SEL_WGMI_SIZE_REQ = 0x00000050,
20841GC_EA_SE_PERF_SEL_SARB_DRAM_RW_TURN_AROUND = 0x00000051,
20842GC_EA_SE_PERF_SEL_SARB_GMI_RW_TURN_AROUND = 0x00000052,
20843GC_EA_SE_PERF_SEL_RDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000053,
20844GC_EA_SE_PERF_SEL_WDRAM_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000054,
20845GC_EA_SE_PERF_SEL_RGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000055,
20846GC_EA_SE_PERF_SEL_WGMI_CHAINED_REQ_PER_BURSTS_LENGTH = 0x00000056,
20847GC_EA_SE_PERF_SEL_MAM_DBIT_FA_EVICT = 0x00000057,
20848GC_EA_SE_PERF_SEL_MAM_DBIT_REQ_VLD = 0x00000058,
20849GC_EA_SE_PERF_SEL_SARB_COHERENT_SIZE_REQ = 0x00000059,
20850GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT_EVICT = 0x0000005a,
20851GC_EA_SE_PERF_SEL_MAM_ARAM_FA_LRU_EVICT = 0x0000005b,
20852GC_EA_SE_PERF_SEL_MAM_FLUSH_REQ = 0x0000005c,
20853GC_EA_SE_PERF_SEL_MAM_FLUSH_RESP = 0x0000005d,
20854GC_EA_SE_PERF_SEL_MAM_DBIT_FA_HIT_EVICT = 0x0000005e,
20855GC_EA_SE_PERF_SEL_MAM_DBIT_FA_LRU_EVICT = 0x0000005f,
20856GC_EA_SE_PERF_SEL_MAM_DQRY_ONGOING = 0x00000060,
20857GC_EA_SE_PERF_SEL_MAM_ARAM_FA_HIT = 0x00000061,
20858} GC_EA_SE_PERFCOUNT_SEL;
20859
20860/*
20861 * LSDMA_PERF_SEL enum
20862 */
20863
20864typedef enum LSDMA_PERF_SEL {
20865LSDMA_PERF_SEL_CYCLE = 0x00000000,
20866LSDMA_PERF_SEL_IDLE = 0x00000001,
20867LSDMA_PERF_SEL_REG_IDLE = 0x00000002,
20868LSDMA_PERF_SEL_RB_EMPTY = 0x00000003,
20869LSDMA_PERF_SEL_RB_FULL = 0x00000004,
20870LSDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005,
20871LSDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006,
20872LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007,
20873LSDMA_PERF_SEL_RB_RPTR_WB = 0x00000008,
20874LSDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009,
20875LSDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a,
20876LSDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b,
20877LSDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c,
20878LSDMA_PERF_SEL_EX_IDLE = 0x0000000d,
20879LSDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e,
20880LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
20881LSDMA_PERF_SEL_MC_WR_IDLE = 0x00000010,
20882LSDMA_PERF_SEL_MC_WR_COUNT = 0x00000011,
20883LSDMA_PERF_SEL_MC_RD_IDLE = 0x00000012,
20884LSDMA_PERF_SEL_MC_RD_COUNT = 0x00000013,
20885LSDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014,
20886LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015,
20887LSDMA_PERF_SEL_SEM_IDLE = 0x00000018,
20888LSDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019,
20889LSDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a,
20890LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b,
20891LSDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c,
20892LSDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d,
20893LSDMA_PERF_SEL_INT_IDLE = 0x0000001e,
20894LSDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f,
20895LSDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020,
20896LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021,
20897LSDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022,
20898LSDMA_PERF_SEL_NUM_PACKET = 0x00000023,
20899LSDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025,
20900LSDMA_PERF_SEL_CE_WR_IDLE = 0x00000026,
20901LSDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027,
20902LSDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028,
20903LSDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029,
20904LSDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a,
20905LSDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b,
20906LSDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e,
20907LSDMA_PERF_SEL_DUMMY_0 = 0x0000002f,
20908LSDMA_PERF_SEL_DUMMY_1 = 0x00000030,
20909LSDMA_PERF_SEL_CE_INFO_FULL = 0x00000031,
20910LSDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032,
20911LSDMA_PERF_SEL_CE_RD_STALL = 0x00000033,
20912LSDMA_PERF_SEL_CE_WR_STALL = 0x00000034,
20913LSDMA_PERF_SEL_GFX_SELECT = 0x00000035,
20914LSDMA_PERF_SEL_RLC0_SELECT = 0x00000036,
20915LSDMA_PERF_SEL_RLC1_SELECT = 0x00000037,
20916LSDMA_PERF_SEL_PAGE_SELECT = 0x00000038,
20917LSDMA_PERF_SEL_CTX_CHANGE = 0x00000039,
20918LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a,
20919LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b,
20920LSDMA_PERF_SEL_DOORBELL = 0x0000003c,
20921LSDMA_PERF_SEL_RD_BA_RTR = 0x0000003d,
20922LSDMA_PERF_SEL_WR_BA_RTR = 0x0000003e,
20923LSDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f,
20924LSDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040,
20925LSDMA_PERF_SEL_CE_L1_STALL = 0x00000041,
20926LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x00000042,
20927LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x00000043,
20928LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x00000044,
20929LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x00000045,
20930LSDMA_PERF_SEL_ATCL2_RET_XNACK = 0x00000046,
20931LSDMA_PERF_SEL_ATCL2_RET_ACK = 0x00000047,
20932LSDMA_PERF_SEL_ATCL2_FREE = 0x00000048,
20933LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x00000049,
20934LSDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004a,
20935LSDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004b,
20936LSDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004c,
20937LSDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004d,
20938LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x0000004e,
20939LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x0000004f,
20940LSDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000050,
20941LSDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000051,
20942LSDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000052,
20943LSDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000053,
20944LSDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000054,
20945LSDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000055,
20946LSDMA_PERF_SEL_L1_WR_INV_EN = 0x00000056,
20947LSDMA_PERF_SEL_L1_RD_INV_EN = 0x00000057,
20948LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x00000058,
20949LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x00000059,
20950LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x0000005a,
20951LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x0000005b,
20952LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x0000005c,
20953LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x0000005d,
20954LSDMA_PERF_SEL_L1_INV_MIDDLE = 0x0000005e,
20955LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 0x0000005f,
20956LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 0x00000060,
20957LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 0x00000061,
20958LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 0x00000062,
20959LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 0x00000063,
20960LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 0x00000064,
20961LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 0x00000065,
20962LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 0x00000066,
20963LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 0x00000067,
20964LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 0x00000068,
20965LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 0x00000069,
20966LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 0x0000006a,
20967LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 0x0000006b,
20968LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 0x0000006c,
20969LSDMA_PERF_SEL_CMD_OP_MATCH = 0x0000006d,
20970LSDMA_PERF_SEL_CMD_OP_START = 0x0000006e,
20971LSDMA_PERF_SEL_CMD_OP_END = 0x0000006f,
20972LSDMA_PERF_SEL_CE_BUSY = 0x00000070,
20973LSDMA_PERF_SEL_CE_BUSY_START = 0x00000071,
20974LSDMA_PERF_SEL_CE_BUSY_END = 0x00000072,
20975LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 0x00000073,
20976LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 0x00000074,
20977LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 0x00000075,
20978LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 0x00000076,
20979LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 0x00000077,
20980LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 0x00000078,
20981LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 0x00000079,
20982LSDMA_PERF_SEL_DRAM_ECC = 0x0000007a,
20983LSDMA_PERF_SEL_NACK_GEN_ERR = 0x0000007b,
20984} LSDMA_PERF_SEL;
20985
20986/*
20987 * ROM_SIGNATURE value
20988 */
20989
20990#define ROM_SIGNATURE 0x0000aa55
20991
20992/*
20993 * EFC_SURFACE_PIXEL_FORMAT enum
20994 */
20995
20996typedef enum EFC_SURFACE_PIXEL_FORMAT {
20997EFC_ARGB1555 = 0x00000001,
20998EFC_RGBA5551 = 0x00000002,
20999EFC_RGB565 = 0x00000003,
21000EFC_BGR565 = 0x00000004,
21001EFC_ARGB4444 = 0x00000005,
21002EFC_RGBA4444 = 0x00000006,
21003EFC_ARGB8888 = 0x00000008,
21004EFC_RGBA8888 = 0x00000009,
21005EFC_ARGB2101010 = 0x0000000a,
21006EFC_RGBA1010102 = 0x0000000b,
21007EFC_AYCrCb8888 = 0x0000000c,
21008EFC_YCrCbA8888 = 0x0000000d,
21009EFC_ACrYCb8888 = 0x0000000e,
21010EFC_CrYCbA8888 = 0x0000000f,
21011EFC_ARGB16161616_10MSB = 0x00000010,
21012EFC_RGBA16161616_10MSB = 0x00000011,
21013EFC_ARGB16161616_10LSB = 0x00000012,
21014EFC_RGBA16161616_10LSB = 0x00000013,
21015EFC_ARGB16161616_12MSB = 0x00000014,
21016EFC_RGBA16161616_12MSB = 0x00000015,
21017EFC_ARGB16161616_12LSB = 0x00000016,
21018EFC_RGBA16161616_12LSB = 0x00000017,
21019EFC_ARGB16161616_FLOAT = 0x00000018,
21020EFC_RGBA16161616_FLOAT = 0x00000019,
21021EFC_ARGB16161616_UNORM = 0x0000001a,
21022EFC_RGBA16161616_UNORM = 0x0000001b,
21023EFC_ARGB16161616_SNORM = 0x0000001c,
21024EFC_RGBA16161616_SNORM = 0x0000001d,
21025EFC_AYCrCb16161616_10MSB = 0x00000020,
21026EFC_AYCrCb16161616_10LSB = 0x00000021,
21027EFC_YCrCbA16161616_10MSB = 0x00000022,
21028EFC_YCrCbA16161616_10LSB = 0x00000023,
21029EFC_ACrYCb16161616_10MSB = 0x00000024,
21030EFC_ACrYCb16161616_10LSB = 0x00000025,
21031EFC_CrYCbA16161616_10MSB = 0x00000026,
21032EFC_CrYCbA16161616_10LSB = 0x00000027,
21033EFC_AYCrCb16161616_12MSB = 0x00000028,
21034EFC_AYCrCb16161616_12LSB = 0x00000029,
21035EFC_YCrCbA16161616_12MSB = 0x0000002a,
21036EFC_YCrCbA16161616_12LSB = 0x0000002b,
21037EFC_ACrYCb16161616_12MSB = 0x0000002c,
21038EFC_ACrYCb16161616_12LSB = 0x0000002d,
21039EFC_CrYCbA16161616_12MSB = 0x0000002e,
21040EFC_CrYCbA16161616_12LSB = 0x0000002f,
21041EFC_Y8_CrCb88_420_PLANAR = 0x00000040,
21042EFC_Y8_CbCr88_420_PLANAR = 0x00000041,
21043EFC_Y10_CrCb1010_420_PLANAR = 0x00000042,
21044EFC_Y10_CbCr1010_420_PLANAR = 0x00000043,
21045EFC_Y12_CrCb1212_420_PLANAR = 0x00000044,
21046EFC_Y12_CbCr1212_420_PLANAR = 0x00000045,
21047EFC_YCrYCb8888_422_PACKED = 0x00000048,
21048EFC_YCbYCr8888_422_PACKED = 0x00000049,
21049EFC_CrYCbY8888_422_PACKED = 0x0000004a,
21050EFC_CbYCrY8888_422_PACKED = 0x0000004b,
21051EFC_YCrYCb10101010_422_PACKED = 0x0000004c,
21052EFC_YCbYCr10101010_422_PACKED = 0x0000004d,
21053EFC_CrYCbY10101010_422_PACKED = 0x0000004e,
21054EFC_CbYCrY10101010_422_PACKED = 0x0000004f,
21055EFC_YCrYCb12121212_422_PACKED = 0x00000050,
21056EFC_YCbYCr12121212_422_PACKED = 0x00000051,
21057EFC_CrYCbY12121212_422_PACKED = 0x00000052,
21058EFC_CbYCrY12121212_422_PACKED = 0x00000053,
21059EFC_RGB111110_FIX = 0x00000070,
21060EFC_BGR101111_FIX = 0x00000071,
21061EFC_ACrYCb2101010 = 0x00000072,
21062EFC_CrYCbA1010102 = 0x00000073,
21063EFC_RGB111110_FLOAT = 0x00000076,
21064EFC_BGR101111_FLOAT = 0x00000077,
21065EFC_MONO_8 = 0x00000078,
21066EFC_MONO_10MSB = 0x00000079,
21067EFC_MONO_10LSB = 0x0000007a,
21068EFC_MONO_12MSB = 0x0000007b,
21069EFC_MONO_12LSB = 0x0000007c,
21070EFC_MONO_16 = 0x0000007d,
21071} EFC_SURFACE_PIXEL_FORMAT;
21072
21073#endif /*_soc24_ENUM_HEADER*/