1/* SPDX-License-Identifier: MIT */
   2/*
   3 * Copyright 2023 Advanced Micro Devices, Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: AMD
  24 *
  25 */
  26
  27#include "display_mode_core.h"
  28#include "dml2_internal_types.h"
  29#include "dml2_translation_helper.h"
  30
  31#define NUM_DCFCLK_STAS 5
 
  32
  33void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)
  34{
  35	switch (dml2->v20.dml_core_ctx.project) {
  36
  37	case dml_project_dcn32:
  38	case dml_project_dcn321:
  39	default:
  40		// Hardcoded values for DCN32x
  41		out->vblank_nom_default_us = 600;
  42		out->rob_buffer_size_kbytes = 128;
  43		out->config_return_buffer_size_in_kbytes = 1280;
  44		out->config_return_buffer_segment_size_in_kbytes = 64;
  45		out->compressed_buffer_segment_size_in_kbytes = 64;
  46		out->meta_fifo_size_in_kentries = 22;
  47		out->zero_size_buffer_entries = 512;
  48		out->dpte_buffer_size_in_pte_reqs_luma = 68;
  49		out->dpte_buffer_size_in_pte_reqs_chroma = 36;
  50		out->dcc_meta_buffer_size_bytes = 6272;
  51		out->gpuvm_max_page_table_levels = 4;
  52		out->hostvm_max_page_table_levels = 0;
  53		out->pixel_chunk_size_kbytes = 8;
  54		//out->alpha_pixel_chunk_size_kbytes;
  55		out->min_pixel_chunk_size_bytes = 1024;
  56		out->meta_chunk_size_kbytes = 2;
  57		out->min_meta_chunk_size_bytes = 256;
  58		out->writeback_chunk_size_kbytes = 8;
  59		out->line_buffer_size_bits = 1171920;
  60		out->max_line_buffer_lines = 32;
  61		out->writeback_interface_buffer_size_kbytes = 90;
  62		//Number of pipes after DCN Pipe harvesting
  63		out->max_num_dpp = dml2->config.dcn_pipe_count;
  64		out->max_num_otg = dml2->config.dcn_pipe_count;
  65		out->max_num_wb = 1;
  66		out->max_dchub_pscl_bw_pix_per_clk = 4;
  67		out->max_pscl_lb_bw_pix_per_clk = 2;
  68		out->max_lb_vscl_bw_pix_per_clk = 4;
  69		out->max_vscl_hscl_bw_pix_per_clk = 4;
  70		out->max_hscl_ratio = 6;
  71		out->max_vscl_ratio = 6;
  72		out->max_hscl_taps = 8;
  73		out->max_vscl_taps = 8;
  74		out->dispclk_ramp_margin_percent = 1;
  75		out->dppclk_delay_subtotal = 47;
  76		out->dppclk_delay_scl = 50;
  77		out->dppclk_delay_scl_lb_only = 16;
  78		out->dppclk_delay_cnvc_formatter = 28;
  79		out->dppclk_delay_cnvc_cursor = 6;
  80		out->cursor_buffer_size = 16;
  81		out->cursor_chunk_size = 2;
  82		out->dispclk_delay_subtotal = 125;
  83		out->max_inter_dcn_tile_repeaters = 8;
  84		out->writeback_max_hscl_ratio = 1;
  85		out->writeback_max_vscl_ratio = 1;
  86		out->writeback_min_hscl_ratio = 1;
  87		out->writeback_min_vscl_ratio = 1;
  88		out->writeback_max_hscl_taps = 1;
  89		out->writeback_max_vscl_taps = 1;
  90		out->writeback_line_buffer_buffer_size = 0;
  91		out->num_dsc = 4;
  92		out->maximum_dsc_bits_per_component = 12;
  93		out->maximum_pixels_per_line_per_dsc_unit = 6016;
  94		out->dsc422_native_support = true;
  95		out->dcc_supported = true;
  96		out->ptoi_supported = false;
  97
  98		out->gpuvm_enable = false;
  99		out->hostvm_enable = false;
 100		out->cursor_64bpp_support = false;
 101		out->dynamic_metadata_vm_enabled = false;
 102
 103		out->max_num_hdmi_frl_outputs = 1;
 104		out->max_num_dp2p0_outputs = 2;
 105		out->max_num_dp2p0_streams = 4;
 106		break;
 107
 108	case dml_project_dcn35:
 109	case dml_project_dcn351:
 110		out->rob_buffer_size_kbytes = 64;
 111		out->config_return_buffer_size_in_kbytes = 1792;
 112		out->compressed_buffer_segment_size_in_kbytes = 64;
 113		out->meta_fifo_size_in_kentries = 32;
 114		out->zero_size_buffer_entries = 512;
 115		out->pixel_chunk_size_kbytes = 8;
 116		out->alpha_pixel_chunk_size_kbytes = 4;
 117		out->min_pixel_chunk_size_bytes = 1024;
 118		out->meta_chunk_size_kbytes = 2;
 119		out->min_meta_chunk_size_bytes = 256;
 120		out->writeback_chunk_size_kbytes = 8;
 121		out->dpte_buffer_size_in_pte_reqs_luma = 68;
 122		out->dpte_buffer_size_in_pte_reqs_chroma = 36;
 123		out->dcc_meta_buffer_size_bytes = 6272;
 124		out->gpuvm_enable = 1;
 125		out->hostvm_enable = 1;
 126		out->gpuvm_max_page_table_levels = 1;
 127		out->hostvm_max_page_table_levels = 2;
 128		out->num_dsc = 4;
 129		out->maximum_dsc_bits_per_component = 12;
 130		out->maximum_pixels_per_line_per_dsc_unit = 6016;
 131		out->dsc422_native_support = 1;
 132		out->line_buffer_size_bits = 986880;
 133		out->dcc_supported = 1;
 134		out->max_line_buffer_lines = 32;
 135		out->writeback_interface_buffer_size_kbytes = 90;
 136		out->max_num_dpp = 4;
 137		out->max_num_otg = 4;
 138		out->max_num_hdmi_frl_outputs = 1;
 139		out->max_num_dp2p0_outputs = 2;
 140		out->max_num_dp2p0_streams = 4;
 141		out->max_num_wb = 1;
 142
 143		out->max_dchub_pscl_bw_pix_per_clk = 4;
 144		out->max_pscl_lb_bw_pix_per_clk = 2;
 145		out->max_lb_vscl_bw_pix_per_clk = 4;
 146		out->max_vscl_hscl_bw_pix_per_clk = 4;
 147		out->max_hscl_ratio = 6;
 148		out->max_vscl_ratio = 6;
 149		out->max_hscl_taps = 8;
 150		out->max_vscl_taps = 8;
 151		out->dispclk_ramp_margin_percent = 1.11;
 152
 153		out->dppclk_delay_subtotal = 47;
 154		out->dppclk_delay_scl = 50;
 155		out->dppclk_delay_scl_lb_only = 16;
 156		out->dppclk_delay_cnvc_formatter = 28;
 157		out->dppclk_delay_cnvc_cursor = 6;
 158		out->dispclk_delay_subtotal = 125;
 159
 160		out->dynamic_metadata_vm_enabled = false;
 161		out->max_inter_dcn_tile_repeaters = 8;
 162		out->cursor_buffer_size = 16; // kBytes
 163		out->cursor_chunk_size = 2; // kBytes
 164
 165		out->writeback_line_buffer_buffer_size = 0;
 166		out->writeback_max_hscl_ratio = 1;
 167		out->writeback_max_vscl_ratio = 1;
 168		out->writeback_min_hscl_ratio = 1;
 169		out->writeback_min_vscl_ratio = 1;
 170		out->writeback_max_hscl_taps  = 1;
 171		out->writeback_max_vscl_taps  = 1;
 172		out->ptoi_supported	= 0;
 173
 174		out->vblank_nom_default_us = 668; /*not in dml, but in programming guide, hard coded in dml2_translate_ip_params*/
 175		out->config_return_buffer_segment_size_in_kbytes = 64; /*required, but not exist,, hard coded in dml2_translate_ip_params*/
 176		break;
 177
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 178	}
 179}
 180
 181void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out)
 182{
 183	out->dprefclk_mhz = dml2->config.bbox_overrides.dprefclk_mhz;
 184	out->xtalclk_mhz = dml2->config.bbox_overrides.xtalclk_mhz;
 185	out->pcierefclk_mhz = 100;
 186	out->refclk_mhz = dml2->config.bbox_overrides.dchub_refclk_mhz;
 187
 188	out->max_outstanding_reqs = 512;
 189	out->pct_ideal_sdp_bw_after_urgent = 100;
 190	out->pct_ideal_fabric_bw_after_urgent = 67;
 191	out->pct_ideal_dram_bw_after_urgent_pixel_only = 20;
 192	out->pct_ideal_dram_bw_after_urgent_pixel_and_vm = 60;
 193	out->pct_ideal_dram_bw_after_urgent_vm_only = 30;
 194	out->pct_ideal_dram_bw_after_urgent_strobe = 67;
 195	out->max_avg_sdp_bw_use_normal_percent = 80;
 196	out->max_avg_fabric_bw_use_normal_percent = 60;
 197	out->max_avg_dram_bw_use_normal_percent = 15;
 198	out->max_avg_dram_bw_use_normal_strobe_percent = 50;
 199
 200	out->urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096;
 201	out->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096;
 202	out->urgent_out_of_order_return_per_channel_vm_only_bytes = 4096;
 203	out->return_bus_width_bytes = 64;
 204	out->dram_channel_width_bytes = 2;
 205	out->fabric_datapath_to_dcn_data_return_bytes = 64;
 206	out->hostvm_min_page_size_kbytes = 0;
 207	out->gpuvm_min_page_size_kbytes = 256;
 208	out->phy_downspread_percent = 0.38;
 209	out->dcn_downspread_percent = 0.5;
 210	out->dispclk_dppclk_vco_speed_mhz = dml2->config.bbox_overrides.disp_pll_vco_speed_mhz;
 211	out->mall_allocated_for_dcn_mbytes = dml2->config.mall_cfg.max_cab_allocation_bytes / 1048576; // 64 or 32 MB;
 212
 213	out->do_urgent_latency_adjustment = true;
 214
 215	switch (dml2->v20.dml_core_ctx.project) {
 216
 217	case dml_project_dcn32:
 218	default:
 219		out->num_chans = 24;
 220		out->round_trip_ping_latency_dcfclk_cycles = 263;
 221		out->smn_latency_us = 2;
 222		break;
 223
 224	case dml_project_dcn321:
 225		out->num_chans = 8;
 226		out->round_trip_ping_latency_dcfclk_cycles = 207;
 227		out->smn_latency_us = 0;
 228		break;
 229
 230	case dml_project_dcn35:
 231	case dml_project_dcn351:
 232		out->num_chans = 4;
 233		out->round_trip_ping_latency_dcfclk_cycles = 106;
 234		out->smn_latency_us = 2;
 235		out->dispclk_dppclk_vco_speed_mhz = 3600;
 
 236		break;
 237
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 238	}
 239	/* ---Overrides if available--- */
 240	if (dml2->config.bbox_overrides.dram_num_chan)
 241		out->num_chans = dml2->config.bbox_overrides.dram_num_chan;
 242
 243	if (dml2->config.bbox_overrides.dram_chanel_width_bytes)
 244		out->dram_channel_width_bytes = dml2->config.bbox_overrides.dram_chanel_width_bytes;
 245}
 246
 247void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
 248	const struct soc_bounding_box_st *in_bbox, struct soc_states_st *out)
 249{
 250	struct dml2_policy_build_synthetic_soc_states_scratch *s = &dml2->v20.scratch.create_scratch.build_synthetic_socbb_scratch;
 251	struct dml2_policy_build_synthetic_soc_states_params *p = &dml2->v20.scratch.build_synthetic_socbb_params;
 252	unsigned int dcfclk_stas_mhz[NUM_DCFCLK_STAS];
 
 
 
 253	unsigned int i = 0;
 254	unsigned int transactions_per_mem_clock = 16; // project specific, depends on used Memory type
 255
 256	p->dcfclk_stas_mhz = dcfclk_stas_mhz;
 257	p->num_dcfclk_stas = NUM_DCFCLK_STAS;
 
 
 
 
 
 
 258	p->in_bbox = in_bbox;
 259	p->out_states = out;
 260	p->in_states = &dml2->v20.scratch.create_scratch.in_states;
 261
 262
 263	/* Initial hardcoded values */
 264	switch (dml2->v20.dml_core_ctx.project) {
 265
 266	case dml_project_dcn32:
 267	default:
 268		p->in_states->num_states = 2;
 269		transactions_per_mem_clock = 16;
 270		p->in_states->state_array[0].socclk_mhz = 620.0;
 271		p->in_states->state_array[0].dscclk_mhz = 716.667;
 272		p->in_states->state_array[0].phyclk_mhz = 810;
 273		p->in_states->state_array[0].phyclk_d18_mhz = 667;
 274		p->in_states->state_array[0].phyclk_d32_mhz = 625;
 275		p->in_states->state_array[0].dtbclk_mhz = 1564.0;
 276		p->in_states->state_array[0].fabricclk_mhz = 450.0;
 277		p->in_states->state_array[0].dcfclk_mhz = 300.0;
 278		p->in_states->state_array[0].dispclk_mhz = 2150.0;
 279		p->in_states->state_array[0].dppclk_mhz = 2150.0;
 280		p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock;
 281
 282		p->in_states->state_array[0].urgent_latency_pixel_data_only_us = 4;
 283		p->in_states->state_array[0].urgent_latency_pixel_mixed_with_vm_data_us = 0;
 284		p->in_states->state_array[0].urgent_latency_vm_data_only_us = 0;
 285		p->in_states->state_array[0].writeback_latency_us = 12;
 286		p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_component_us = 1;
 287		p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_reference_mhz = 3000;
 288		p->in_states->state_array[0].sr_exit_z8_time_us = 0;
 289		p->in_states->state_array[0].sr_enter_plus_exit_z8_time_us = 0;
 290		p->in_states->state_array[0].dram_clock_change_latency_us = 400;
 291		p->in_states->state_array[0].use_ideal_dram_bw_strobe = true;
 292		p->in_states->state_array[0].sr_exit_time_us = 42.97;
 293		p->in_states->state_array[0].sr_enter_plus_exit_time_us = 49.94;
 294		p->in_states->state_array[0].fclk_change_latency_us = 20;
 295		p->in_states->state_array[0].usr_retraining_latency_us = 2;
 296
 297		p->in_states->state_array[1].socclk_mhz = 1200.0;
 298		p->in_states->state_array[1].fabricclk_mhz = 2500.0;
 299		p->in_states->state_array[1].dcfclk_mhz = 1564.0;
 300		p->in_states->state_array[1].dram_speed_mts = 1125 * transactions_per_mem_clock;
 301		break;
 302
 303	case dml_project_dcn321:
 304		p->in_states->num_states = 2;
 305		transactions_per_mem_clock = 16;
 306		p->in_states->state_array[0].socclk_mhz = 582.0;
 307		p->in_states->state_array[0].dscclk_mhz = 573.333;
 308		p->in_states->state_array[0].phyclk_mhz = 810;
 309		p->in_states->state_array[0].phyclk_d18_mhz = 667;
 310		p->in_states->state_array[0].phyclk_d32_mhz = 313;
 311		p->in_states->state_array[0].dtbclk_mhz = 1564.0;
 312		p->in_states->state_array[0].fabricclk_mhz = 450.0;
 313		p->in_states->state_array[0].dcfclk_mhz = 300.0;
 314		p->in_states->state_array[0].dispclk_mhz = 1720.0;
 315		p->in_states->state_array[0].dppclk_mhz = 1720.0;
 316		p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock;
 317
 318		p->in_states->state_array[0].urgent_latency_pixel_data_only_us = 4;
 319		p->in_states->state_array[0].urgent_latency_pixel_mixed_with_vm_data_us = 0;
 320		p->in_states->state_array[0].urgent_latency_vm_data_only_us = 0;
 321		p->in_states->state_array[0].writeback_latency_us = 12;
 322		p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_component_us = 1;
 323		p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_reference_mhz = 3000;
 324		p->in_states->state_array[0].sr_exit_z8_time_us = 0;
 325		p->in_states->state_array[0].sr_enter_plus_exit_z8_time_us = 0;
 326		p->in_states->state_array[0].dram_clock_change_latency_us = 400;
 327		p->in_states->state_array[0].use_ideal_dram_bw_strobe = true;
 328		p->in_states->state_array[0].sr_exit_time_us = 19.95;
 329		p->in_states->state_array[0].sr_enter_plus_exit_time_us = 24.36;
 330		p->in_states->state_array[0].fclk_change_latency_us = 7;
 331		p->in_states->state_array[0].usr_retraining_latency_us = 0;
 332
 333		p->in_states->state_array[1].socclk_mhz = 1200.0;
 334		p->in_states->state_array[1].fabricclk_mhz = 2250.0;
 335		p->in_states->state_array[1].dcfclk_mhz = 1434.0;
 336		p->in_states->state_array[1].dram_speed_mts = 1000 * transactions_per_mem_clock;
 337		break;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 338	}
 339
 340	/* Override from passed values, if available */
 341	for (i = 0; i < p->in_states->num_states; i++) {
 342		if (dml2->config.bbox_overrides.sr_exit_latency_us) {
 343			p->in_states->state_array[i].sr_exit_time_us =
 344				dml2->config.bbox_overrides.sr_exit_latency_us;
 345		}
 346
 347		if (dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us) {
 348			p->in_states->state_array[i].sr_enter_plus_exit_time_us =
 349				dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us;
 350		}
 351
 352		if (dml2->config.bbox_overrides.sr_exit_z8_time_us) {
 353			p->in_states->state_array[i].sr_exit_z8_time_us =
 354				dml2->config.bbox_overrides.sr_exit_z8_time_us;
 355		}
 356
 357		if (dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us) {
 358			p->in_states->state_array[i].sr_enter_plus_exit_z8_time_us =
 359				dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us;
 360		}
 361
 362		if (dml2->config.bbox_overrides.urgent_latency_us) {
 363			p->in_states->state_array[i].urgent_latency_pixel_data_only_us =
 364				dml2->config.bbox_overrides.urgent_latency_us;
 365		}
 366
 367		if (dml2->config.bbox_overrides.dram_clock_change_latency_us) {
 368			p->in_states->state_array[i].dram_clock_change_latency_us =
 369				dml2->config.bbox_overrides.dram_clock_change_latency_us;
 370		}
 371
 372		if (dml2->config.bbox_overrides.fclk_change_latency_us) {
 373			p->in_states->state_array[i].fclk_change_latency_us =
 374				dml2->config.bbox_overrides.fclk_change_latency_us;
 375		}
 376	}
 377
 378	/* DCFCLK stas values are project specific */
 379	if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) ||
 380		(dml2->v20.dml_core_ctx.project == dml_project_dcn321)) {
 381		p->dcfclk_stas_mhz[0] = p->in_states->state_array[0].dcfclk_mhz;
 382		p->dcfclk_stas_mhz[1] = 615;
 383		p->dcfclk_stas_mhz[2] = 906;
 384		p->dcfclk_stas_mhz[3] = 1324;
 385		p->dcfclk_stas_mhz[4] = p->in_states->state_array[1].dcfclk_mhz;
 386	} else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
 387			dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
 388		p->dcfclk_stas_mhz[0] = 300;
 389		p->dcfclk_stas_mhz[1] = 615;
 390		p->dcfclk_stas_mhz[2] = 906;
 391		p->dcfclk_stas_mhz[3] = 1324;
 392		p->dcfclk_stas_mhz[4] = 1500;
 393	}
 394	/* Copy clocks tables entries, if available */
 395	if (dml2->config.bbox_overrides.clks_table.num_states) {
 396		p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states;
 397		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++) {
 398			p->in_states->state_array[i].dcfclk_mhz = dml2->config.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz;
 399		}
 400
 401		p->dcfclk_stas_mhz[0] = dml2->config.bbox_overrides.clks_table.clk_entries[0].dcfclk_mhz;
 402		if (i > 1)
 403			p->dcfclk_stas_mhz[4] = dml2->config.bbox_overrides.clks_table.clk_entries[i-1].dcfclk_mhz;
 404
 405		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels; i++) {
 406			p->in_states->state_array[i].fabricclk_mhz =
 407				dml2->config.bbox_overrides.clks_table.clk_entries[i].fclk_mhz;
 408		}
 409
 410		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels; i++) {
 411			p->in_states->state_array[i].dram_speed_mts =
 412				dml2->config.bbox_overrides.clks_table.clk_entries[i].memclk_mhz * transactions_per_mem_clock;
 413		}
 414
 415		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels; i++) {
 416			p->in_states->state_array[i].socclk_mhz =
 417				dml2->config.bbox_overrides.clks_table.clk_entries[i].socclk_mhz;
 418		}
 419
 420		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels; i++) {
 421			if (dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz > 0)
 422				p->in_states->state_array[i].dtbclk_mhz =
 423					dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz;
 424		}
 425
 426		for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++) {
 427			p->in_states->state_array[i].dispclk_mhz =
 428				dml2->config.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz;
 429			p->in_states->state_array[i].dppclk_mhz =
 430				dml2->config.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz;
 431		}
 432	}
 433
 434	dml2_policy_build_synthetic_soc_states(s, p);
 435	if (dml2->v20.dml_core_ctx.project == dml_project_dcn35 ||
 436		dml2->v20.dml_core_ctx.project == dml_project_dcn351) {
 437		// Override last out_state with data from last in_state
 438		// This will ensure that out_state contains max fclk
 439		memcpy(&p->out_states->state_array[p->out_states->num_states - 1],
 440				&p->in_states->state_array[p->in_states->num_states - 1],
 441				sizeof(struct soc_state_bounding_box_st));
 442	}
 443}
 444
 445void dml2_translate_ip_params(const struct dc *in, struct ip_params_st *out)
 446{
 447	const struct _vcs_dpi_ip_params_st *in_ip_params = &in->dml.ip;
 448	/* Copy over the IP params tp dml2_ctx */
 449	out->compressed_buffer_segment_size_in_kbytes = in_ip_params->compressed_buffer_segment_size_in_kbytes;
 450	out->config_return_buffer_size_in_kbytes = in_ip_params->config_return_buffer_size_in_kbytes;
 451	out->cursor_buffer_size = in_ip_params->cursor_buffer_size;
 452	out->cursor_chunk_size = in_ip_params->cursor_chunk_size;
 453	out->dcc_meta_buffer_size_bytes = in_ip_params->dcc_meta_buffer_size_bytes;
 454	out->dcc_supported = in_ip_params->dcc_supported;
 455	out->dispclk_delay_subtotal = in_ip_params->dispclk_delay_subtotal;
 456	out->dispclk_ramp_margin_percent = in_ip_params->dispclk_ramp_margin_percent;
 457	out->dppclk_delay_cnvc_cursor = in_ip_params->dppclk_delay_cnvc_cursor;
 458	out->dppclk_delay_cnvc_formatter = in_ip_params->dppclk_delay_cnvc_formatter;
 459	out->dppclk_delay_scl = in_ip_params->dppclk_delay_scl;
 460	out->dppclk_delay_scl_lb_only = in_ip_params->dppclk_delay_scl_lb_only;
 461	out->dppclk_delay_subtotal = in_ip_params->dppclk_delay_subtotal;
 462	out->dpte_buffer_size_in_pte_reqs_chroma = in_ip_params->dpte_buffer_size_in_pte_reqs_chroma;
 463	out->dpte_buffer_size_in_pte_reqs_luma = in_ip_params->dpte_buffer_size_in_pte_reqs_luma;
 464	out->dsc422_native_support = in_ip_params->dsc422_native_support;
 465	out->dynamic_metadata_vm_enabled = in_ip_params->dynamic_metadata_vm_enabled;
 466	out->gpuvm_enable = in_ip_params->gpuvm_enable;
 467	out->gpuvm_max_page_table_levels = in_ip_params->gpuvm_max_page_table_levels;
 468	out->hostvm_enable = in_ip_params->hostvm_enable;
 469	out->hostvm_max_page_table_levels = in_ip_params->hostvm_max_page_table_levels;
 470	out->line_buffer_size_bits = in_ip_params->line_buffer_size_bits;
 471	out->maximum_dsc_bits_per_component = in_ip_params->maximum_dsc_bits_per_component;
 472	out->maximum_pixels_per_line_per_dsc_unit = in_ip_params->maximum_pixels_per_line_per_dsc_unit;
 473	out->max_dchub_pscl_bw_pix_per_clk = in_ip_params->max_dchub_pscl_bw_pix_per_clk;
 474	out->max_hscl_ratio = in_ip_params->max_hscl_ratio;
 475	out->max_hscl_taps = in_ip_params->max_hscl_taps;
 476	out->max_inter_dcn_tile_repeaters = in_ip_params->max_inter_dcn_tile_repeaters;
 477	out->max_lb_vscl_bw_pix_per_clk = in_ip_params->max_lb_vscl_bw_pix_per_clk;
 478	out->max_line_buffer_lines = in_ip_params->max_line_buffer_lines;
 479	out->max_num_dp2p0_outputs = in_ip_params->max_num_dp2p0_outputs;
 480	out->max_num_dp2p0_streams = in_ip_params->max_num_dp2p0_streams;
 481	out->max_num_dpp = in_ip_params->max_num_dpp;
 482	out->max_num_hdmi_frl_outputs = in_ip_params->max_num_hdmi_frl_outputs;
 483	out->max_num_otg = in_ip_params->max_num_otg;
 484	out->max_num_wb = in_ip_params->max_num_wb;
 485	out->max_pscl_lb_bw_pix_per_clk = in_ip_params->max_pscl_lb_bw_pix_per_clk;
 486	out->max_vscl_hscl_bw_pix_per_clk = in_ip_params->max_vscl_hscl_bw_pix_per_clk;
 487	out->max_vscl_ratio = in_ip_params->max_vscl_ratio;
 488	out->max_vscl_taps = in_ip_params->max_vscl_taps;
 489	out->meta_chunk_size_kbytes = in_ip_params->meta_chunk_size_kbytes;
 490	out->meta_fifo_size_in_kentries = in_ip_params->meta_fifo_size_in_kentries;
 491	out->min_meta_chunk_size_bytes = in_ip_params->min_meta_chunk_size_bytes;
 492	out->min_pixel_chunk_size_bytes = in_ip_params->min_pixel_chunk_size_bytes;
 493	out->num_dsc = in_ip_params->num_dsc;
 494	out->pixel_chunk_size_kbytes = in_ip_params->pixel_chunk_size_kbytes;
 495	out->ptoi_supported = in_ip_params->ptoi_supported;
 496	out->rob_buffer_size_kbytes = in_ip_params->rob_buffer_size_kbytes;
 497	out->writeback_chunk_size_kbytes = in_ip_params->writeback_chunk_size_kbytes;
 498	out->writeback_interface_buffer_size_kbytes = in_ip_params->writeback_interface_buffer_size_kbytes;
 499	out->writeback_line_buffer_buffer_size = in_ip_params->writeback_line_buffer_buffer_size;
 500	out->writeback_max_hscl_ratio = in_ip_params->writeback_max_hscl_ratio;
 501	out->writeback_max_hscl_taps = in_ip_params->writeback_max_hscl_taps;
 502	out->writeback_max_vscl_ratio = in_ip_params->writeback_max_vscl_ratio;
 503	out->writeback_max_vscl_taps = in_ip_params->writeback_max_vscl_taps;
 504	out->writeback_min_hscl_ratio = in_ip_params->writeback_min_hscl_ratio;
 505	out->writeback_min_vscl_ratio = in_ip_params->writeback_min_vscl_ratio;
 506	out->zero_size_buffer_entries = in_ip_params->zero_size_buffer_entries;
 507
 508	/* As per hardcoded reference / discussions */
 509	out->config_return_buffer_segment_size_in_kbytes = 64;
 510	//out->vblank_nom_default_us = 600;
 511	out->vblank_nom_default_us = in_ip_params->VBlankNomDefaultUS;
 512}
 513
 514void dml2_translate_socbb_params(const struct dc *in, struct soc_bounding_box_st *out)
 515{
 516	const struct _vcs_dpi_soc_bounding_box_st *in_soc_params = &in->dml.soc;
 517	/* Copy over the SOCBB params to dml2_ctx */
 518	out->dispclk_dppclk_vco_speed_mhz = in_soc_params->dispclk_dppclk_vco_speed_mhz;
 519	out->do_urgent_latency_adjustment = in_soc_params->do_urgent_latency_adjustment;
 520	out->dram_channel_width_bytes = (dml_uint_t)in_soc_params->dram_channel_width_bytes;
 521	out->fabric_datapath_to_dcn_data_return_bytes = (dml_uint_t)in_soc_params->fabric_datapath_to_dcn_data_return_bytes;
 522	out->gpuvm_min_page_size_kbytes = in_soc_params->gpuvm_min_page_size_bytes / 1024;
 523	out->hostvm_min_page_size_kbytes = in_soc_params->hostvm_min_page_size_bytes / 1024;
 524	out->mall_allocated_for_dcn_mbytes = (dml_uint_t)in_soc_params->mall_allocated_for_dcn_mbytes;
 525	out->max_avg_dram_bw_use_normal_percent = in_soc_params->max_avg_dram_bw_use_normal_percent;
 526	out->max_avg_fabric_bw_use_normal_percent = in_soc_params->max_avg_fabric_bw_use_normal_percent;
 527	out->max_avg_dram_bw_use_normal_strobe_percent = in_soc_params->max_avg_dram_bw_use_normal_strobe_percent;
 528	out->max_avg_sdp_bw_use_normal_percent = in_soc_params->max_avg_sdp_bw_use_normal_percent;
 529	out->max_outstanding_reqs = in_soc_params->max_request_size_bytes;
 530	out->num_chans = in_soc_params->num_chans;
 531	out->pct_ideal_dram_bw_after_urgent_strobe = in_soc_params->pct_ideal_dram_bw_after_urgent_strobe;
 532	out->pct_ideal_dram_bw_after_urgent_vm_only = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_vm_only;
 533	out->pct_ideal_fabric_bw_after_urgent = in_soc_params->pct_ideal_fabric_bw_after_urgent;
 534	out->pct_ideal_sdp_bw_after_urgent = in_soc_params->pct_ideal_sdp_bw_after_urgent;
 535	out->phy_downspread_percent = in_soc_params->downspread_percent;
 536	out->refclk_mhz = 50; // As per hardcoded reference.
 537	out->return_bus_width_bytes = in_soc_params->return_bus_width_bytes;
 538	out->round_trip_ping_latency_dcfclk_cycles = in_soc_params->round_trip_ping_latency_dcfclk_cycles;
 539	out->smn_latency_us = in_soc_params->smn_latency_us;
 540	out->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = in_soc_params->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
 541	out->urgent_out_of_order_return_per_channel_pixel_only_bytes = in_soc_params->urgent_out_of_order_return_per_channel_pixel_only_bytes;
 542	out->urgent_out_of_order_return_per_channel_vm_only_bytes = in_soc_params->urgent_out_of_order_return_per_channel_vm_only_bytes;
 543	out->pct_ideal_dram_bw_after_urgent_pixel_and_vm = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
 544	out->pct_ideal_dram_bw_after_urgent_pixel_only = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_pixel_only;
 545	out->dcn_downspread_percent = in_soc_params->dcn_downspread_percent;
 546}
 547
 548void dml2_translate_soc_states(const struct dc *dc, struct soc_states_st *out, int num_states)
 549{
 550	unsigned int i = 0;
 551	out->num_states = num_states;
 552
 553	for (i = 0; i < out->num_states; i++) {
 554		out->state_array[i].dcfclk_mhz = dc->dml.soc.clock_limits[i].dcfclk_mhz;
 555		out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz;
 556		out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz;
 557		out->state_array[i].dram_speed_mts = dc->dml.soc.clock_limits[i].dram_speed_mts;
 558		out->state_array[i].dtbclk_mhz = dc->dml.soc.clock_limits[i].dtbclk_mhz;
 559		out->state_array[i].socclk_mhz = dc->dml.soc.clock_limits[i].socclk_mhz;
 560		out->state_array[i].fabricclk_mhz = dc->dml.soc.clock_limits[i].fabricclk_mhz;
 561		out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz;
 562		out->state_array[i].phyclk_d18_mhz = dc->dml.soc.clock_limits[i].phyclk_d18_mhz;
 563		out->state_array[i].phyclk_d32_mhz = dc->dml.soc.clock_limits[i].phyclk_d32_mhz;
 564		out->state_array[i].phyclk_mhz = dc->dml.soc.clock_limits[i].phyclk_mhz;
 565		out->state_array[i].sr_enter_plus_exit_time_us = dc->dml.soc.sr_enter_plus_exit_time_us;
 566		out->state_array[i].sr_exit_time_us = dc->dml.soc.sr_exit_time_us;
 567		out->state_array[i].fclk_change_latency_us = dc->dml.soc.fclk_change_latency_us;
 568		out->state_array[i].dram_clock_change_latency_us = dc->dml.soc.dram_clock_change_latency_us;
 569		out->state_array[i].usr_retraining_latency_us = dc->dml.soc.usr_retraining_latency_us;
 570		out->state_array[i].writeback_latency_us = dc->dml.soc.writeback_latency_us;
 571		/* Driver initialized values for these are different than the spreadsheet. Use the
 572		 * spreadsheet ones for now. We need to decided which ones to use.
 573		 */
 574		out->state_array[i].sr_exit_z8_time_us = dc->dml.soc.sr_exit_z8_time_us;
 575		out->state_array[i].sr_enter_plus_exit_z8_time_us = dc->dml.soc.sr_enter_plus_exit_z8_time_us;
 576		//out->state_array[i].sr_exit_z8_time_us = 5.20;
 577		//out->state_array[i].sr_enter_plus_exit_z8_time_us = 9.60;
 578		out->state_array[i].use_ideal_dram_bw_strobe = true;
 579		out->state_array[i].urgent_latency_pixel_data_only_us = dc->dml.soc.urgent_latency_pixel_data_only_us;
 580		out->state_array[i].urgent_latency_pixel_mixed_with_vm_data_us = dc->dml.soc.urgent_latency_pixel_mixed_with_vm_data_us;
 581		out->state_array[i].urgent_latency_vm_data_only_us = dc->dml.soc.urgent_latency_vm_data_only_us;
 582		out->state_array[i].urgent_latency_adjustment_fabric_clock_component_us = dc->dml.soc.urgent_latency_adjustment_fabric_clock_component_us;
 583		out->state_array[i].urgent_latency_adjustment_fabric_clock_reference_mhz = dc->dml.soc.urgent_latency_adjustment_fabric_clock_reference_mhz;
 584	}
 585}
 586
 587static void populate_dml_timing_cfg_from_stream_state(struct dml_timing_cfg_st *out, unsigned int location, const struct dc_stream_state *in)
 588{
 589	dml_uint_t hblank_start, vblank_start;
 590
 591	out->HActive[location] = in->timing.h_addressable + in->timing.h_border_left + in->timing.h_border_right;
 592	out->VActive[location] = in->timing.v_addressable + in->timing.v_border_bottom + in->timing.v_border_top;
 593	out->RefreshRate[location] = ((in->timing.pix_clk_100hz * 100) / in->timing.h_total) / in->timing.v_total;
 594	out->VFrontPorch[location] = in->timing.v_front_porch;
 595	out->PixelClock[location] = in->timing.pix_clk_100hz / 10000.00;
 596	if (in->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
 597		out->PixelClock[location] *= 2;
 598	out->HTotal[location] = in->timing.h_total;
 599	out->VTotal[location] = in->timing.v_total;
 600	out->Interlace[location] = in->timing.flags.INTERLACE;
 601	hblank_start = in->timing.h_total - in->timing.h_front_porch;
 602	out->HBlankEnd[location] = hblank_start
 603					- in->timing.h_addressable
 604					- in->timing.h_border_left
 605					- in->timing.h_border_right;
 606	vblank_start = in->timing.v_total - in->timing.v_front_porch;
 607	out->VBlankEnd[location] = vblank_start
 608					- in->timing.v_addressable
 609					- in->timing.v_border_top
 610					- in->timing.v_border_bottom;
 611	out->DRRDisplay[location] = false;
 612}
 613
 614static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st *out, unsigned int location,
 615				const struct dc_stream_state *in, const struct pipe_ctx *pipe)
 616{
 617	unsigned int output_bpc;
 618
 619	out->DSCEnable[location] = (enum dml_dsc_enable)in->timing.flags.DSC;
 620	out->OutputLinkDPLanes[location] = 4; // As per code in dcn20_resource.c
 621	out->DSCInputBitPerComponent[location] = 12; // As per code in dcn20_resource.c
 
 622
 623	switch (in->signal) {
 624	case SIGNAL_TYPE_DISPLAY_PORT_MST:
 625	case SIGNAL_TYPE_DISPLAY_PORT:
 626		out->OutputEncoder[location] = dml_dp;
 627		if (is_dp2p0_output_encoder(pipe))
 628			out->OutputEncoder[location] = dml_dp2p0;
 629		break;
 630	case SIGNAL_TYPE_EDP:
 631		out->OutputEncoder[location] = dml_edp;
 632		break;
 633	case SIGNAL_TYPE_HDMI_TYPE_A:
 634	case SIGNAL_TYPE_DVI_SINGLE_LINK:
 635	case SIGNAL_TYPE_DVI_DUAL_LINK:
 636		out->OutputEncoder[location] = dml_hdmi;
 637		break;
 638	default:
 639		out->OutputEncoder[location] = dml_dp;
 640	}
 641
 642	switch (in->timing.display_color_depth) {
 643	case COLOR_DEPTH_666:
 644		output_bpc = 6;
 645		break;
 646	case COLOR_DEPTH_888:
 647		output_bpc = 8;
 648		break;
 649	case COLOR_DEPTH_101010:
 650		output_bpc = 10;
 651		break;
 652	case COLOR_DEPTH_121212:
 653		output_bpc = 12;
 654		break;
 655	case COLOR_DEPTH_141414:
 656		output_bpc = 14;
 657		break;
 658	case COLOR_DEPTH_161616:
 659		output_bpc = 16;
 660		break;
 661	case COLOR_DEPTH_999:
 662		output_bpc = 9;
 663		break;
 664	case COLOR_DEPTH_111111:
 665		output_bpc = 11;
 666		break;
 667	default:
 668		output_bpc = 8;
 669		break;
 670	}
 671
 672	switch (in->timing.pixel_encoding) {
 673	case PIXEL_ENCODING_RGB:
 674	case PIXEL_ENCODING_YCBCR444:
 675		out->OutputFormat[location] = dml_444;
 676		out->OutputBpp[location] = (dml_float_t)output_bpc * 3;
 677		break;
 678	case PIXEL_ENCODING_YCBCR420:
 679		out->OutputFormat[location] = dml_420;
 680		out->OutputBpp[location] = (output_bpc * 3.0) / 2;
 681		break;
 682	case PIXEL_ENCODING_YCBCR422:
 683		if (in->timing.flags.DSC && !in->timing.dsc_cfg.ycbcr422_simple)
 684			out->OutputFormat[location] = dml_n422;
 685		else
 686			out->OutputFormat[location] = dml_s422;
 687		out->OutputBpp[location] = (dml_float_t)output_bpc * 2;
 688		break;
 689	default:
 690		out->OutputFormat[location] = dml_444;
 691		out->OutputBpp[location] = (dml_float_t)output_bpc * 3;
 692		break;
 693	}
 694
 695	if (in->timing.flags.DSC) {
 696		out->OutputBpp[location] = in->timing.dsc_cfg.bits_per_pixel / 16.0;
 697	}
 698
 699	// This has been false throughout DCN32x development. If needed we can change this later on.
 700	out->OutputMultistreamEn[location] = false;
 701
 702	switch (in->signal) {
 703	case SIGNAL_TYPE_NONE:
 704	case SIGNAL_TYPE_DVI_SINGLE_LINK:
 705	case SIGNAL_TYPE_DVI_DUAL_LINK:
 706	case SIGNAL_TYPE_HDMI_TYPE_A:
 707	case SIGNAL_TYPE_LVDS:
 708	case SIGNAL_TYPE_RGB:
 709	case SIGNAL_TYPE_DISPLAY_PORT:
 710	case SIGNAL_TYPE_DISPLAY_PORT_MST:
 711	case SIGNAL_TYPE_EDP:
 712	case SIGNAL_TYPE_VIRTUAL:
 713	default:
 714		out->OutputLinkDPRate[location] = dml_dp_rate_na;
 715		break;
 716	}
 717
 718	out->PixelClockBackEnd[location] = in->timing.pix_clk_100hz / 10000.00;
 719
 720	out->AudioSampleLayout[location] = in->audio_info.modes->sample_size;
 721	out->AudioSampleRate[location] = in->audio_info.modes->max_bit_rate;
 722
 723	out->OutputDisabled[location] = true;
 724}
 725
 726static void populate_dummy_dml_surface_cfg(struct dml_surface_cfg_st *out, unsigned int location, const struct dc_stream_state *in)
 727{
 728	out->SurfaceWidthY[location] = in->timing.h_addressable;
 729	out->SurfaceHeightY[location] = in->timing.v_addressable;
 730	out->SurfaceWidthC[location] = in->timing.h_addressable;
 731	out->SurfaceHeightC[location] = in->timing.v_addressable;
 732	out->PitchY[location] = ((out->SurfaceWidthY[location] + 127) / 128) * 128;
 733	out->PitchC[location] = 0;
 734	out->DCCEnable[location] = false;
 735	out->DCCMetaPitchY[location] = 0;
 736	out->DCCMetaPitchC[location] = 0;
 737	out->DCCRateLuma[location] = 1.0;
 738	out->DCCRateChroma[location] = 1.0;
 739	out->DCCFractionOfZeroSizeRequestsLuma[location] = 0;
 740	out->DCCFractionOfZeroSizeRequestsChroma[location] = 0;
 741	out->SurfaceTiling[location] = dml_sw_64kb_r_x;
 742	out->SourcePixelFormat[location] = dml_444_32;
 743}
 744
 745static void populate_dml_surface_cfg_from_plane_state(enum dml_project_id dml2_project, struct dml_surface_cfg_st *out, unsigned int location, const struct dc_plane_state *in)
 746{
 747	out->PitchY[location] = in->plane_size.surface_pitch;
 748	out->SurfaceHeightY[location] = in->plane_size.surface_size.height;
 749	out->SurfaceWidthY[location] = in->plane_size.surface_size.width;
 750	out->SurfaceHeightC[location] = in->plane_size.chroma_size.height;
 751	out->SurfaceWidthC[location] = in->plane_size.chroma_size.width;
 752	out->PitchC[location] = in->plane_size.chroma_pitch;
 753	out->DCCEnable[location] = in->dcc.enable;
 754	out->DCCMetaPitchY[location] = in->dcc.meta_pitch;
 755	out->DCCMetaPitchC[location] = in->dcc.meta_pitch_c;
 756	out->DCCRateLuma[location] = 1.0;
 757	out->DCCRateChroma[location] = 1.0;
 758	out->DCCFractionOfZeroSizeRequestsLuma[location] = in->dcc.independent_64b_blks;
 759	out->DCCFractionOfZeroSizeRequestsChroma[location] = in->dcc.independent_64b_blks_c;
 760
 761	switch (dml2_project) {
 762	default:
 763		out->SurfaceTiling[location] = (enum dml_swizzle_mode)in->tiling_info.gfx9.swizzle;
 764		break;
 
 
 
 
 
 
 
 
 
 
 
 
 
 765	}
 766
 767	switch (in->format) {
 768	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 769	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 770		out->SourcePixelFormat[location] = dml_420_8;
 771		break;
 772	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 773	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 774		out->SourcePixelFormat[location] = dml_420_10;
 775		break;
 776	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 777	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 778	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 779		out->SourcePixelFormat[location] = dml_444_64;
 780		break;
 781	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 782	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 783		out->SourcePixelFormat[location] = dml_444_16;
 784		break;
 785	case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
 786		out->SourcePixelFormat[location] = dml_444_8;
 787		break;
 788	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
 789		out->SourcePixelFormat[location] = dml_rgbe_alpha;
 790		break;
 791	default:
 792		out->SourcePixelFormat[location] = dml_444_32;
 793		break;
 794	}
 795}
 796
 797static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_state *in, struct dc_state *context)
 798{
 799	int i;
 800	struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe;
 801
 802	memset(temp_pipe, 0, sizeof(struct pipe_ctx));
 803
 804	for (i = 0; i < MAX_PIPES; i++)	{
 805		const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 806
 807		if (pipe->plane_state == in && !pipe->prev_odm_pipe) {
 808			temp_pipe->stream = pipe->stream;
 809			temp_pipe->plane_state = pipe->plane_state;
 810			temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps;
 811
 812			resource_build_scaling_params(temp_pipe);
 813			break;
 814		}
 815	}
 816
 817	ASSERT(i < MAX_PIPES);
 818	return temp_pipe->plane_res.scl_data;
 819}
 820
 821static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_stream_state *in)
 
 
 822{
 823	dml_uint_t width, height;
 824
 825	if (in->timing.h_addressable > 3840)
 826		width = 3840;
 827	else
 828		width = in->timing.h_addressable;	// 4K max
 829
 830	if (in->timing.v_addressable > 2160)
 831		height = 2160;
 832	else
 833		height = in->timing.v_addressable;	// 4K max
 834
 835	out->CursorBPP[location] = dml_cur_32bit;
 836	out->CursorWidth[location] = 256;
 837
 838	out->GPUVMMinPageSizeKBytes[location] = 256;
 839
 840	out->ViewportWidth[location] = width;
 841	out->ViewportHeight[location] = height;
 842	out->ViewportStationary[location] = false;
 843	out->ViewportWidthChroma[location] = 0;
 844	out->ViewportHeightChroma[location] = 0;
 845	out->ViewportXStart[location] = 0;
 846	out->ViewportXStartC[location] = 0;
 847	out->ViewportYStart[location] = 0;
 848	out->ViewportYStartC[location] = 0;
 849
 850	out->ScalerEnabled[location] = false;
 851	out->HRatio[location] = 1.0;
 852	out->VRatio[location] = 1.0;
 853	out->HRatioChroma[location] = 0;
 854	out->VRatioChroma[location] = 0;
 855	out->HTaps[location] = 1;
 856	out->VTaps[location] = 1;
 857	out->HTapsChroma[location] = 0;
 858	out->VTapsChroma[location] = 0;
 859	out->SourceScan[location] = dml_rotation_0;
 860	out->ScalerRecoutWidth[location] = width;
 861
 862	out->LBBitPerPixel[location] = 57;
 863
 864	out->DynamicMetadataEnable[location] = false;
 865
 866	out->NumberOfCursors[location] = 1;
 867	out->UseMALLForStaticScreen[location] = dml_use_mall_static_screen_disable;
 868	out->UseMALLForPStateChange[location] = dml_use_mall_pstate_change_disable;
 869
 870	out->DETSizeOverride[location] = 256;
 871
 872	out->ScalerEnabled[location] = false;
 873}
 874
 875static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_plane_state *in, struct dc_state *context)
 
 
 876{
 877	const struct scaler_data scaler_data = get_scaler_data_for_plane(in, context);
 
 
 
 
 878
 879	out->CursorBPP[location] = dml_cur_32bit;
 880	out->CursorWidth[location] = 256;
 881
 882	out->GPUVMMinPageSizeKBytes[location] = 256;
 883
 884	out->ViewportWidth[location] = scaler_data.viewport.width;
 885	out->ViewportHeight[location] = scaler_data.viewport.height;
 886	out->ViewportWidthChroma[location] = scaler_data.viewport_c.width;
 887	out->ViewportHeightChroma[location] = scaler_data.viewport_c.height;
 888	out->ViewportXStart[location] = scaler_data.viewport.x;
 889	out->ViewportYStart[location] = scaler_data.viewport.y;
 890	out->ViewportXStartC[location] = scaler_data.viewport_c.x;
 891	out->ViewportYStartC[location] = scaler_data.viewport_c.y;
 892	out->ViewportStationary[location] = false;
 893
 894	out->ScalerEnabled[location] = scaler_data.ratios.horz.value != dc_fixpt_one.value ||
 895				scaler_data.ratios.horz_c.value != dc_fixpt_one.value ||
 896				scaler_data.ratios.vert.value != dc_fixpt_one.value ||
 897				scaler_data.ratios.vert_c.value != dc_fixpt_one.value;
 898
 899	/* Current driver code base uses LBBitPerPixel as 57. There is a discrepancy
 900	 * from the HW/DML teams about this value. Initialize LBBitPerPixel with the
 901	 * value current used in Navi3x .
 902	 */
 903
 904	out->LBBitPerPixel[location] = 57;
 905
 906	if (out->ScalerEnabled[location] == false) {
 907		out->HRatio[location] = 1;
 908		out->HRatioChroma[location] = 1;
 909		out->VRatio[location] = 1;
 910		out->VRatioChroma[location] = 1;
 911	} else {
 912		/* Follow the original dml_wrapper.c code direction to fix scaling issues */
 913		out->HRatio[location] = (dml_float_t)scaler_data.ratios.horz.value / (1ULL << 32);
 914		out->HRatioChroma[location] = (dml_float_t)scaler_data.ratios.horz_c.value / (1ULL << 32);
 915		out->VRatio[location] = (dml_float_t)scaler_data.ratios.vert.value / (1ULL << 32);
 916		out->VRatioChroma[location] = (dml_float_t)scaler_data.ratios.vert_c.value / (1ULL << 32);
 917	}
 918
 919	if (!scaler_data.taps.h_taps) {
 920		out->HTaps[location] = 1;
 921		out->HTapsChroma[location] = 1;
 922	} else {
 923		out->HTaps[location] = scaler_data.taps.h_taps;
 924		out->HTapsChroma[location] = scaler_data.taps.h_taps_c;
 925	}
 926	if (!scaler_data.taps.v_taps) {
 927		out->VTaps[location] = 1;
 928		out->VTapsChroma[location] = 1;
 929	} else {
 930		out->VTaps[location] = scaler_data.taps.v_taps;
 931		out->VTapsChroma[location] = scaler_data.taps.v_taps_c;
 932	}
 933
 934	out->SourceScan[location] = (enum dml_rotation_angle)in->rotation;
 935	out->ScalerRecoutWidth[location] = in->dst_rect.width;
 936
 937	out->DynamicMetadataEnable[location] = false;
 938	out->DynamicMetadataLinesBeforeActiveRequired[location] = 0;
 939	out->DynamicMetadataTransmittedBytes[location] = 0;
 940
 941	out->NumberOfCursors[location] = 1;
 
 
 942}
 943
 944static unsigned int map_stream_to_dml_display_cfg(const struct dml2_context *dml2,
 945		const struct dc_stream_state *stream, const struct dml_display_cfg_st *dml_dispcfg)
 946{
 947	int i = 0;
 948	int location = -1;
 949
 950	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
 951		if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i] == stream->stream_id) {
 952			location = i;
 953			break;
 954		}
 955	}
 956
 957	return location;
 958}
 959
 960static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *context, const struct dc_plane_state *plane,
 961		unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id)
 962{
 963	int i, j;
 964	bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;
 965
 966	if (!plane_id)
 967		return false;
 968
 969	for (i = 0; i < context->stream_count; i++) {
 970		if (context->streams[i]->stream_id == stream_id) {
 971			for (j = 0; j < context->stream_status[i].plane_count; j++) {
 972				if (context->stream_status[i].plane_states[j] == plane &&
 973					(!is_plane_duplicate || (is_plane_duplicate && (j == plane_index)))) {
 974					*plane_id = (i << 16) | j;
 975					return true;
 976				}
 977			}
 978		}
 979	}
 980
 981	return false;
 982}
 983
 984static unsigned int map_plane_to_dml_display_cfg(const struct dml2_context *dml2, const struct dc_plane_state *plane,
 985		const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index)
 986{
 987	unsigned int plane_id;
 988	int i = 0;
 989	int location = -1;
 990
 991	if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) {
 992		ASSERT(false);
 993		return -1;
 994	}
 995
 996	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
 997		if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i] == plane_id) {
 998			location = i;
 999			break;
1000		}
1001	}
1002
1003	return location;
1004}
1005
1006static void apply_legacy_svp_drr_settings(struct dml2_context *dml2, const struct dc_state *state, struct dml_display_cfg_st *dml_dispcfg)
1007{
1008	int i;
1009
1010	if (state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
1011		ASSERT(state->stream_count == 1);
1012		dml_dispcfg->timing.DRRDisplay[0] = true;
1013	} else if (state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid) {
1014
1015		for (i = 0; i < dml_dispcfg->num_timings; i++) {
1016			if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i] == state->streams[state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index]->stream_id)
1017				dml_dispcfg->timing.DRRDisplay[i] = true;
1018		}
1019	}
1020}
1021
1022static void dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2, struct dc_state *state)
1023{
1024	unsigned int i;
1025	unsigned int pipe_index = 0;
1026	unsigned int plane_index = 0;
1027	struct dml2_dml_to_dc_pipe_mapping *dml_to_dc_pipe_mapping = &dml2->v20.scratch.dml_to_dc_pipe_mapping;
1028
1029	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
1030		dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[i] = false;
1031		dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[i] = 0;
1032	}
1033
1034	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
1035		struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];
1036
1037		if (!pipe || !pipe->stream || !pipe->plane_state)
1038			continue;
1039
1040		while (pipe) {
1041			pipe_index = pipe->pipe_idx;
1042
1043			if (pipe->stream && dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] == false) {
1044				dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[pipe_index] = plane_index;
1045				plane_index++;
1046				dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] = true;
1047			}
1048
1049			pipe = pipe->bottom_pipe;
1050		}
1051
1052		plane_index = 0;
1053	}
1054}
1055
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1056void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg)
1057{
1058	int i = 0, j = 0, k = 0;
1059	int disp_cfg_stream_location, disp_cfg_plane_location;
1060	enum mall_stream_type stream_mall_type;
1061	struct pipe_ctx *current_pipe_context;
1062
1063	for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
1064		dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] = false;
1065		dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] = false;
1066		dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] = false;
1067		dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] = false;
1068	}
1069
1070	//Generally these are set by referencing our latest BB/IP params in dcn32_resource.c file
1071	dml_dispcfg->plane.GPUVMEnable = dml2->v20.dml_core_ctx.ip.gpuvm_enable;
1072	dml_dispcfg->plane.GPUVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.gpuvm_max_page_table_levels;
1073	dml_dispcfg->plane.HostVMEnable = dml2->v20.dml_core_ctx.ip.hostvm_enable;
1074	dml_dispcfg->plane.HostVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.hostvm_max_page_table_levels;
1075	if (dml2->v20.dml_core_ctx.ip.hostvm_enable)
1076		dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal = dml_prefetch_support_uclk_fclk_and_stutter;
1077
1078	dml2_populate_pipe_to_plane_index_mapping(dml2, context);
 
1079
1080	for (i = 0; i < context->stream_count; i++) {
1081		current_pipe_context = NULL;
1082		for (k = 0; k < MAX_PIPES; k++) {
1083			/* find one pipe allocated to this stream for the purpose of getting
1084			info about the link later */
1085			if (context->streams[i] == context->res_ctx.pipe_ctx[k].stream) {
1086				current_pipe_context = &context->res_ctx.pipe_ctx[k];
1087				break;
1088			}
1089		}
1090		disp_cfg_stream_location = map_stream_to_dml_display_cfg(dml2, context->streams[i], dml_dispcfg);
1091		stream_mall_type = dc_state_get_stream_subvp_type(context, context->streams[i]);
1092
1093		if (disp_cfg_stream_location < 0)
1094			disp_cfg_stream_location = dml_dispcfg->num_timings++;
1095
1096		ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1097
1098		populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]);
1099		populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context);
 
 
 
 
1100		switch (context->streams[i]->debug.force_odm_combine_segments) {
1101		case 2:
1102			dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_stream_location] = dml_odm_use_policy_combine_2to1;
1103			break;
1104		case 4:
1105			dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_stream_location] = dml_odm_use_policy_combine_4to1;
1106			break;
1107		default:
1108			break;
1109		}
1110
1111		dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_stream_location] = context->streams[i]->stream_id;
1112		dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_stream_location] = true;
1113
1114		if (context->stream_status[i].plane_count == 0) {
1115			disp_cfg_plane_location = dml_dispcfg->num_surfaces++;
1116
1117			populate_dummy_dml_surface_cfg(&dml_dispcfg->surface, disp_cfg_plane_location, context->streams[i]);
1118			populate_dummy_dml_plane_cfg(&dml_dispcfg->plane, disp_cfg_plane_location, context->streams[i]);
 
1119
1120			dml_dispcfg->plane.BlendingAndTiming[disp_cfg_plane_location] = disp_cfg_stream_location;
1121
1122			dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;
1123		} else {
1124			for (j = 0; j < context->stream_status[i].plane_count; j++) {
1125				disp_cfg_plane_location = map_plane_to_dml_display_cfg(dml2,
1126					context->stream_status[i].plane_states[j], context, dml_dispcfg, context->streams[i]->stream_id, j);
1127
1128				if (disp_cfg_plane_location < 0)
1129					disp_cfg_plane_location = dml_dispcfg->num_surfaces++;
1130
1131				ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1132
1133				populate_dml_surface_cfg_from_plane_state(dml2->v20.dml_core_ctx.project, &dml_dispcfg->surface, disp_cfg_plane_location, context->stream_status[i].plane_states[j]);
1134				populate_dml_plane_cfg_from_plane_state(&dml_dispcfg->plane, disp_cfg_plane_location, context->stream_status[i].plane_states[j], context);
 
 
 
1135
1136				if (stream_mall_type == SUBVP_MAIN) {
1137					dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_sub_viewport;
1138					dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_optimize;
1139				} else if (stream_mall_type == SUBVP_PHANTOM) {
1140					dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_phantom_pipe;
1141					dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_disable;
1142					dml2->v20.dml_core_ctx.policy.ImmediateFlipRequirement[disp_cfg_plane_location] = dml_immediate_flip_not_required;
1143				} else {
1144					dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_disable;
1145					dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_optimize;
1146				}
1147
1148				dml_dispcfg->plane.BlendingAndTiming[disp_cfg_plane_location] = disp_cfg_stream_location;
1149
1150				if (get_plane_id(dml2, context, context->stream_status[i].plane_states[j], context->streams[i]->stream_id, j,
1151					&dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[disp_cfg_plane_location]))
1152					dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;
1153
1154				if (j >= 1) {
1155					populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_plane_location, context->streams[i]);
1156					populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_plane_location, context->streams[i], current_pipe_context);
1157					switch (context->streams[i]->debug.force_odm_combine_segments) {
1158					case 2:
1159						dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] = dml_odm_use_policy_combine_2to1;
1160						break;
1161					case 4:
1162						dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] = dml_odm_use_policy_combine_4to1;
1163						break;
1164					default:
1165						break;
1166					}
1167
1168					if (stream_mall_type == SUBVP_MAIN)
1169						dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_sub_viewport;
1170					else if (stream_mall_type == SUBVP_PHANTOM)
1171						dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_phantom_pipe;
1172
1173					dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_plane_location] = context->streams[i]->stream_id;
1174					dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_plane_location] = true;
1175
1176					dml_dispcfg->num_timings++;
1177				}
1178			}
1179		}
1180	}
1181
1182	if (!dml2->config.use_native_pstate_optimization)
1183		apply_legacy_svp_drr_settings(dml2, context, dml_dispcfg);
1184}
1185
1186void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs,
1187	struct _vcs_dpi_dml_display_dlg_regs_st *disp_dlg_regs,
1188	struct _vcs_dpi_dml_display_ttu_regs_st *disp_ttu_regs,
1189	struct pipe_ctx *out)
1190{
1191	memset(&out->rq_regs, 0, sizeof(out->rq_regs));
1192	out->rq_regs.rq_regs_l.chunk_size = rq_regs->rq_regs_l.chunk_size;
1193	out->rq_regs.rq_regs_l.min_chunk_size = rq_regs->rq_regs_l.min_chunk_size;
1194	out->rq_regs.rq_regs_l.meta_chunk_size = rq_regs->rq_regs_l.meta_chunk_size;
1195	out->rq_regs.rq_regs_l.min_meta_chunk_size = rq_regs->rq_regs_l.min_meta_chunk_size;
1196	out->rq_regs.rq_regs_l.dpte_group_size = rq_regs->rq_regs_l.dpte_group_size;
1197	out->rq_regs.rq_regs_l.mpte_group_size = rq_regs->rq_regs_l.mpte_group_size;
1198	out->rq_regs.rq_regs_l.swath_height = rq_regs->rq_regs_l.swath_height;
1199	out->rq_regs.rq_regs_l.pte_row_height_linear = rq_regs->rq_regs_l.pte_row_height_linear;
1200
1201	out->rq_regs.rq_regs_c.chunk_size = rq_regs->rq_regs_c.chunk_size;
1202	out->rq_regs.rq_regs_c.min_chunk_size = rq_regs->rq_regs_c.min_chunk_size;
1203	out->rq_regs.rq_regs_c.meta_chunk_size = rq_regs->rq_regs_c.meta_chunk_size;
1204	out->rq_regs.rq_regs_c.min_meta_chunk_size = rq_regs->rq_regs_c.min_meta_chunk_size;
1205	out->rq_regs.rq_regs_c.dpte_group_size = rq_regs->rq_regs_c.dpte_group_size;
1206	out->rq_regs.rq_regs_c.mpte_group_size = rq_regs->rq_regs_c.mpte_group_size;
1207	out->rq_regs.rq_regs_c.swath_height = rq_regs->rq_regs_c.swath_height;
1208	out->rq_regs.rq_regs_c.pte_row_height_linear = rq_regs->rq_regs_c.pte_row_height_linear;
1209
1210	out->rq_regs.drq_expansion_mode = rq_regs->drq_expansion_mode;
1211	out->rq_regs.prq_expansion_mode = rq_regs->prq_expansion_mode;
1212	out->rq_regs.mrq_expansion_mode = rq_regs->mrq_expansion_mode;
1213	out->rq_regs.crq_expansion_mode = rq_regs->crq_expansion_mode;
1214	out->rq_regs.plane1_base_address = rq_regs->plane1_base_address;
1215
1216	memset(&out->dlg_regs, 0, sizeof(out->dlg_regs));
1217	out->dlg_regs.refcyc_h_blank_end = disp_dlg_regs->refcyc_h_blank_end;
1218	out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end;
1219	out->dlg_regs.min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start;
1220	out->dlg_regs.refcyc_per_htotal = disp_dlg_regs->refcyc_per_htotal;
1221	out->dlg_regs.refcyc_x_after_scaler = disp_dlg_regs->refcyc_x_after_scaler;
1222	out->dlg_regs.dst_y_after_scaler = disp_dlg_regs->dst_y_after_scaler;
1223	out->dlg_regs.dst_y_prefetch = disp_dlg_regs->dst_y_prefetch;
1224	out->dlg_regs.dst_y_per_vm_vblank = disp_dlg_regs->dst_y_per_vm_vblank;
1225	out->dlg_regs.dst_y_per_row_vblank = disp_dlg_regs->dst_y_per_row_vblank;
1226	out->dlg_regs.dst_y_per_vm_flip = disp_dlg_regs->dst_y_per_vm_flip;
1227	out->dlg_regs.dst_y_per_row_flip = disp_dlg_regs->dst_y_per_row_flip;
1228	out->dlg_regs.ref_freq_to_pix_freq = disp_dlg_regs->ref_freq_to_pix_freq;
1229	out->dlg_regs.vratio_prefetch = disp_dlg_regs->vratio_prefetch;
1230	out->dlg_regs.vratio_prefetch_c = disp_dlg_regs->vratio_prefetch_c;
1231	out->dlg_regs.refcyc_per_pte_group_vblank_l = disp_dlg_regs->refcyc_per_pte_group_vblank_l;
1232	out->dlg_regs.refcyc_per_pte_group_vblank_c = disp_dlg_regs->refcyc_per_pte_group_vblank_c;
1233	out->dlg_regs.refcyc_per_meta_chunk_vblank_l = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;
1234	out->dlg_regs.refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_c;
1235	out->dlg_regs.refcyc_per_pte_group_flip_l = disp_dlg_regs->refcyc_per_pte_group_flip_l;
1236	out->dlg_regs.refcyc_per_pte_group_flip_c = disp_dlg_regs->refcyc_per_pte_group_flip_c;
1237	out->dlg_regs.refcyc_per_meta_chunk_flip_l = disp_dlg_regs->refcyc_per_meta_chunk_flip_l;
1238	out->dlg_regs.refcyc_per_meta_chunk_flip_c = disp_dlg_regs->refcyc_per_meta_chunk_flip_c;
1239	out->dlg_regs.dst_y_per_pte_row_nom_l = disp_dlg_regs->dst_y_per_pte_row_nom_l;
1240	out->dlg_regs.dst_y_per_pte_row_nom_c = disp_dlg_regs->dst_y_per_pte_row_nom_c;
1241	out->dlg_regs.refcyc_per_pte_group_nom_l = disp_dlg_regs->refcyc_per_pte_group_nom_l;
1242	out->dlg_regs.refcyc_per_pte_group_nom_c = disp_dlg_regs->refcyc_per_pte_group_nom_c;
1243	out->dlg_regs.dst_y_per_meta_row_nom_l = disp_dlg_regs->dst_y_per_meta_row_nom_l;
1244	out->dlg_regs.dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_c;
1245	out->dlg_regs.refcyc_per_meta_chunk_nom_l = disp_dlg_regs->refcyc_per_meta_chunk_nom_l;
1246	out->dlg_regs.refcyc_per_meta_chunk_nom_c = disp_dlg_regs->refcyc_per_meta_chunk_nom_c;
1247	out->dlg_regs.refcyc_per_line_delivery_pre_l = disp_dlg_regs->refcyc_per_line_delivery_pre_l;
1248	out->dlg_regs.refcyc_per_line_delivery_pre_c = disp_dlg_regs->refcyc_per_line_delivery_pre_c;
1249	out->dlg_regs.refcyc_per_line_delivery_l = disp_dlg_regs->refcyc_per_line_delivery_l;
1250	out->dlg_regs.refcyc_per_line_delivery_c = disp_dlg_regs->refcyc_per_line_delivery_c;
1251	out->dlg_regs.refcyc_per_vm_group_vblank = disp_dlg_regs->refcyc_per_vm_group_vblank;
1252	out->dlg_regs.refcyc_per_vm_group_flip = disp_dlg_regs->refcyc_per_vm_group_flip;
1253	out->dlg_regs.refcyc_per_vm_req_vblank = disp_dlg_regs->refcyc_per_vm_req_vblank;
1254	out->dlg_regs.refcyc_per_vm_req_flip = disp_dlg_regs->refcyc_per_vm_req_flip;
1255	out->dlg_regs.dst_y_offset_cur0 = disp_dlg_regs->dst_y_offset_cur0;
1256	out->dlg_regs.chunk_hdl_adjust_cur0 = disp_dlg_regs->chunk_hdl_adjust_cur0;
1257	out->dlg_regs.dst_y_offset_cur1 = disp_dlg_regs->dst_y_offset_cur1;
1258	out->dlg_regs.chunk_hdl_adjust_cur1 = disp_dlg_regs->chunk_hdl_adjust_cur1;
1259	out->dlg_regs.vready_after_vcount0 = disp_dlg_regs->vready_after_vcount0;
1260	out->dlg_regs.dst_y_delta_drq_limit = disp_dlg_regs->dst_y_delta_drq_limit;
1261	out->dlg_regs.refcyc_per_vm_dmdata = disp_dlg_regs->refcyc_per_vm_dmdata;
1262	out->dlg_regs.dmdata_dl_delta = disp_dlg_regs->dmdata_dl_delta;
1263
1264	memset(&out->ttu_regs, 0, sizeof(out->ttu_regs));
1265	out->ttu_regs.qos_level_low_wm = disp_ttu_regs->qos_level_low_wm;
1266	out->ttu_regs.qos_level_high_wm = disp_ttu_regs->qos_level_high_wm;
1267	out->ttu_regs.min_ttu_vblank = disp_ttu_regs->min_ttu_vblank;
1268	out->ttu_regs.qos_level_flip = disp_ttu_regs->qos_level_flip;
1269	out->ttu_regs.refcyc_per_req_delivery_l = disp_ttu_regs->refcyc_per_req_delivery_l;
1270	out->ttu_regs.refcyc_per_req_delivery_c = disp_ttu_regs->refcyc_per_req_delivery_c;
1271	out->ttu_regs.refcyc_per_req_delivery_cur0 = disp_ttu_regs->refcyc_per_req_delivery_cur0;
1272	out->ttu_regs.refcyc_per_req_delivery_cur1 = disp_ttu_regs->refcyc_per_req_delivery_cur1;
1273	out->ttu_regs.refcyc_per_req_delivery_pre_l = disp_ttu_regs->refcyc_per_req_delivery_pre_l;
1274	out->ttu_regs.refcyc_per_req_delivery_pre_c = disp_ttu_regs->refcyc_per_req_delivery_pre_c;
1275	out->ttu_regs.refcyc_per_req_delivery_pre_cur0 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur0;
1276	out->ttu_regs.refcyc_per_req_delivery_pre_cur1 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur1;
1277	out->ttu_regs.qos_level_fixed_l = disp_ttu_regs->qos_level_fixed_l;
1278	out->ttu_regs.qos_level_fixed_c = disp_ttu_regs->qos_level_fixed_c;
1279	out->ttu_regs.qos_level_fixed_cur0 = disp_ttu_regs->qos_level_fixed_cur0;
1280	out->ttu_regs.qos_level_fixed_cur1 = disp_ttu_regs->qos_level_fixed_cur1;
1281	out->ttu_regs.qos_ramp_disable_l = disp_ttu_regs->qos_ramp_disable_l;
1282	out->ttu_regs.qos_ramp_disable_c = disp_ttu_regs->qos_ramp_disable_c;
1283	out->ttu_regs.qos_ramp_disable_cur0 = disp_ttu_regs->qos_ramp_disable_cur0;
1284	out->ttu_regs.qos_ramp_disable_cur1 = disp_ttu_regs->qos_ramp_disable_cur1;
1285}