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1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __MES_API_DEF_H__
25#define __MES_API_DEF_H__
26
27#pragma pack(push, 4)
28
29#define MES_API_VERSION 1
30
31/* Driver submits one API(cmd) as a single Frame and this command size is same
32 * for all API to ease the debugging and parsing of ring buffer.
33 */
34enum { API_FRAME_SIZE_IN_DWORDS = 64 };
35
36/* To avoid command in scheduler context to be overwritten whenenver mutilple
37 * interrupts come in, this creates another queue.
38 */
39enum { API_NUMBER_OF_COMMAND_MAX = 32 };
40
41enum MES_API_TYPE {
42 MES_API_TYPE_SCHEDULER = 1,
43 MES_API_TYPE_MAX
44};
45
46enum MES_SCH_API_OPCODE {
47 MES_SCH_API_SET_HW_RSRC = 0,
48 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */
49 MES_SCH_API_ADD_QUEUE = 2,
50 MES_SCH_API_REMOVE_QUEUE = 3,
51 MES_SCH_API_PERFORM_YIELD = 4,
52 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5,
53 MES_SCH_API_SUSPEND = 6,
54 MES_SCH_API_RESUME = 7,
55 MES_SCH_API_RESET = 8,
56 MES_SCH_API_SET_LOG_BUFFER = 9,
57 MES_SCH_API_CHANGE_GANG_PRORITY = 10,
58 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11,
59 MES_SCH_API_PROGRAM_GDS = 12,
60 MES_SCH_API_SET_DEBUG_VMID = 13,
61 MES_SCH_API_MISC = 14,
62 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15,
63 MES_SCH_API_AMD_LOG = 16,
64 MES_SCH_API_MAX = 0xFF
65};
66
67union MES_API_HEADER {
68 struct {
69 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
70 uint32_t opcode : 8;
71 uint32_t dwsize : 8; /* including header */
72 uint32_t reserved : 12;
73 };
74
75 uint32_t u32All;
76};
77
78enum MES_AMD_PRIORITY_LEVEL {
79 AMD_PRIORITY_LEVEL_LOW = 0,
80 AMD_PRIORITY_LEVEL_NORMAL = 1,
81 AMD_PRIORITY_LEVEL_MEDIUM = 2,
82 AMD_PRIORITY_LEVEL_HIGH = 3,
83 AMD_PRIORITY_LEVEL_REALTIME = 4,
84 AMD_PRIORITY_NUM_LEVELS
85};
86
87enum MES_QUEUE_TYPE {
88 MES_QUEUE_TYPE_GFX,
89 MES_QUEUE_TYPE_COMPUTE,
90 MES_QUEUE_TYPE_SDMA,
91 MES_QUEUE_TYPE_MAX,
92};
93
94struct MES_API_STATUS {
95 uint64_t api_completion_fence_addr;
96 uint64_t api_completion_fence_value;
97};
98
99enum { MAX_COMPUTE_PIPES = 8 };
100enum { MAX_GFX_PIPES = 2 };
101enum { MAX_SDMA_PIPES = 2 };
102
103enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
104enum { MAX_GFX_HQD_PER_PIPE = 8 };
105enum { MAX_SDMA_HQD_PER_PIPE = 10 };
106enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 };
107
108enum { MAX_QUEUES_IN_A_GANG = 8 };
109
110enum VM_HUB_TYPE {
111 VM_HUB_TYPE_GC = 0,
112 VM_HUB_TYPE_MM = 1,
113 VM_HUB_TYPE_MAX,
114};
115
116enum { VMID_INVALID = 0xffff };
117
118enum { MAX_VMID_GCHUB = 16 };
119enum { MAX_VMID_MMHUB = 16 };
120
121enum SET_DEBUG_VMID_OPERATIONS {
122 DEBUG_VMID_OP_PROGRAM = 0,
123 DEBUG_VMID_OP_ALLOCATE = 1,
124 DEBUG_VMID_OP_RELEASE = 2
125};
126
127enum MES_LOG_OPERATION {
128 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
129 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1,
130 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
131 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
132 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
133 MES_LOG_OPERATION_QUEUE_INVALID = 0xF,
134};
135
136enum MES_LOG_CONTEXT_STATE {
137 MES_LOG_CONTEXT_STATE_IDLE = 0,
138 MES_LOG_CONTEXT_STATE_RUNNING = 1,
139 MES_LOG_CONTEXT_STATE_READY = 2,
140 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
141 MES_LOG_CONTEXT_STATE_INVALID = 0xF,
142};
143
144struct MES_LOG_CONTEXT_STATE_CHANGE {
145 void *h_context;
146 enum MES_LOG_CONTEXT_STATE new_context_state;
147};
148
149struct MES_LOG_QUEUE_NEW_WORK {
150 uint64_t h_queue;
151 uint64_t reserved;
152};
153
154struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
155 uint64_t h_queue;
156 uint64_t h_sync_object;
157};
158
159struct MES_LOG_QUEUE_NO_MORE_WORK {
160 uint64_t h_queue;
161 uint64_t reserved;
162};
163
164struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
165 uint64_t h_queue;
166 uint64_t h_sync_object;
167};
168
169struct MES_LOG_ENTRY_HEADER {
170 uint32_t first_free_entry_index;
171 uint32_t wraparound_count;
172 uint64_t number_of_entries;
173 uint64_t reserved[2];
174};
175
176struct MES_LOG_ENTRY_DATA {
177 uint64_t gpu_time_stamp;
178 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
179 uint32_t reserved_operation_type_bits;
180 union {
181 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
182 struct MES_LOG_QUEUE_NEW_WORK queue_new_work;
183 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
184 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;
185 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;
186 uint64_t all[2];
187 };
188};
189
190struct MES_LOG_BUFFER {
191 struct MES_LOG_ENTRY_HEADER header;
192 struct MES_LOG_ENTRY_DATA entries[1];
193};
194
195enum MES_SWIP_TO_HWIP_DEF {
196 MES_MAX_HWIP_SEGMENT = 8,
197};
198
199union MESAPI_SET_HW_RESOURCES {
200 struct {
201 union MES_API_HEADER header;
202 uint32_t vmid_mask_mmhub;
203 uint32_t vmid_mask_gfxhub;
204 uint32_t gds_size;
205 uint32_t paging_vmid;
206 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES];
207 uint32_t gfx_hqd_mask[MAX_GFX_PIPES];
208 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES];
209 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
210 uint64_t g_sch_ctx_gpu_mc_ptr;
211 uint64_t query_status_fence_gpu_mc_ptr;
212 uint32_t gc_base[MES_MAX_HWIP_SEGMENT];
213 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT];
214 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT];
215 struct MES_API_STATUS api_status;
216 union {
217 struct {
218 uint32_t disable_reset : 1;
219 uint32_t use_different_vmid_compute : 1;
220 uint32_t disable_mes_log : 1;
221 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
222 uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
223 uint32_t second_gfx_pipe_enabled : 1;
224 uint32_t enable_level_process_quantum_check : 1;
225 uint32_t legacy_sch_mode : 1;
226 uint32_t disable_add_queue_wptr_mc_addr : 1;
227 uint32_t enable_mes_event_int_logging : 1;
228 uint32_t enable_reg_active_poll : 1;
229 uint32_t reserved : 21;
230 };
231 uint32_t uint32_t_all;
232 };
233 uint32_t oversubscription_timer;
234 uint64_t doorbell_info;
235 uint64_t event_intr_history_gpu_mc_ptr;
236 };
237
238 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
239};
240
241union MESAPI__ADD_QUEUE {
242 struct {
243 union MES_API_HEADER header;
244 uint32_t process_id;
245 uint64_t page_table_base_addr;
246 uint64_t process_va_start;
247 uint64_t process_va_end;
248 uint64_t process_quantum;
249 uint64_t process_context_addr;
250 uint64_t gang_quantum;
251 uint64_t gang_context_addr;
252 uint32_t inprocess_gang_priority;
253 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
254 uint32_t doorbell_offset;
255 uint64_t mqd_addr;
256 uint64_t wptr_addr;
257 uint64_t h_context;
258 uint64_t h_queue;
259 enum MES_QUEUE_TYPE queue_type;
260 uint32_t gds_base;
261 uint32_t gds_size;
262 uint32_t gws_base;
263 uint32_t gws_size;
264 uint32_t oa_mask;
265 uint64_t trap_handler_addr;
266 uint32_t vm_context_cntl;
267
268 struct {
269 uint32_t paging : 1;
270 uint32_t debug_vmid : 4;
271 uint32_t program_gds : 1;
272 uint32_t is_gang_suspended : 1;
273 uint32_t is_tmz_queue : 1;
274 uint32_t map_kiq_utility_queue : 1;
275 uint32_t is_kfd_process : 1;
276 uint32_t trap_en : 1;
277 uint32_t is_aql_queue : 1;
278 uint32_t skip_process_ctx_clear : 1;
279 uint32_t map_legacy_kq : 1;
280 uint32_t exclusively_scheduled : 1;
281 uint32_t reserved : 17;
282 };
283 struct MES_API_STATUS api_status;
284 uint64_t tma_addr;
285 };
286
287 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
288};
289
290union MESAPI__REMOVE_QUEUE {
291 struct {
292 union MES_API_HEADER header;
293 uint32_t doorbell_offset;
294 uint64_t gang_context_addr;
295
296 struct {
297 uint32_t unmap_legacy_gfx_queue : 1;
298 uint32_t unmap_kiq_utility_queue : 1;
299 uint32_t preempt_legacy_gfx_queue : 1;
300 uint32_t unmap_legacy_queue : 1;
301 uint32_t reserved : 28;
302 };
303 struct MES_API_STATUS api_status;
304
305 uint32_t pipe_id;
306 uint32_t queue_id;
307
308 uint64_t tf_addr;
309 uint32_t tf_data;
310
311 enum MES_QUEUE_TYPE queue_type;
312 };
313
314 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
315};
316
317union MESAPI__SET_SCHEDULING_CONFIG {
318 struct {
319 union MES_API_HEADER header;
320 /* Grace period when preempting another priority band for this
321 * priority band. The value for idle priority band is ignored,
322 * as it never preempts other bands.
323 */
324 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
325 /* Default quantum for scheduling across processes within
326 * a priority band.
327 */
328 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
329 /* Default grace period for processes that preempt each other
330 * within a priority band.
331 */
332 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
333 /* For normal level this field specifies the target GPU
334 * percentage in situations when it's starved by the high level.
335 * Valid values are between 0 and 50, with the default being 10.
336 */
337 uint32_t normal_yield_percent;
338 struct MES_API_STATUS api_status;
339 };
340
341 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
342};
343
344union MESAPI__PERFORM_YIELD {
345 struct {
346 union MES_API_HEADER header;
347 uint32_t dummy;
348 struct MES_API_STATUS api_status;
349 };
350
351 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
352};
353
354union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
355 struct {
356 union MES_API_HEADER header;
357 uint32_t inprocess_gang_priority;
358 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
359 uint64_t gang_quantum;
360 uint64_t gang_context_addr;
361 struct MES_API_STATUS api_status;
362 };
363
364 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
365};
366
367union MESAPI__SUSPEND {
368 struct {
369 union MES_API_HEADER header;
370 /* false - suspend all gangs; true - specific gang */
371 struct {
372 uint32_t suspend_all_gangs : 1;
373 uint32_t reserved : 31;
374 };
375 /* gang_context_addr is valid only if suspend_all = false */
376 uint64_t gang_context_addr;
377
378 uint64_t suspend_fence_addr;
379 uint32_t suspend_fence_value;
380
381 struct MES_API_STATUS api_status;
382 };
383
384 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
385};
386
387union MESAPI__RESUME {
388 struct {
389 union MES_API_HEADER header;
390 /* false - resume all gangs; true - specified gang */
391 struct {
392 uint32_t resume_all_gangs : 1;
393 uint32_t reserved : 31;
394 };
395 /* valid only if resume_all_gangs = false */
396 uint64_t gang_context_addr;
397
398 struct MES_API_STATUS api_status;
399 };
400
401 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
402};
403
404union MESAPI__RESET {
405 struct {
406 union MES_API_HEADER header;
407
408 struct {
409 /* Only reset the queue given by doorbell_offset (not entire gang) */
410 uint32_t reset_queue_only : 1;
411 /* Hang detection first then reset any queues that are hung */
412 uint32_t hang_detect_then_reset : 1;
413 /* Only do hang detection (no reset) */
414 uint32_t hang_detect_only : 1;
415 /* Rest HP and LP kernel queues not managed by MES */
416 uint32_t reset_legacy_gfx : 1;
417 uint32_t reserved : 28;
418 };
419
420 uint64_t gang_context_addr;
421
422 /* valid only if reset_queue_only = true */
423 uint32_t doorbell_offset;
424
425 /* valid only if hang_detect_then_reset = true */
426 uint64_t doorbell_offset_addr;
427 enum MES_QUEUE_TYPE queue_type;
428
429 /* valid only if reset_legacy_gfx = true */
430 uint32_t pipe_id_lp;
431 uint32_t queue_id_lp;
432 uint32_t vmid_id_lp;
433 uint64_t mqd_mc_addr_lp;
434 uint32_t doorbell_offset_lp;
435 uint64_t wptr_addr_lp;
436
437 uint32_t pipe_id_hp;
438 uint32_t queue_id_hp;
439 uint32_t vmid_id_hp;
440 uint64_t mqd_mc_addr_hp;
441 uint32_t doorbell_offset_hp;
442 uint64_t wptr_addr_hp;
443
444 struct MES_API_STATUS api_status;
445 };
446
447 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
448};
449
450union MESAPI__SET_LOGGING_BUFFER {
451 struct {
452 union MES_API_HEADER header;
453 /* There are separate log buffers for each queue type */
454 enum MES_QUEUE_TYPE log_type;
455 /* Log buffer GPU Address */
456 uint64_t logging_buffer_addr;
457 /* number of entries in the log buffer */
458 uint32_t number_of_entries;
459 /* Entry index at which CPU interrupt needs to be signalled */
460 uint32_t interrupt_entry;
461
462 struct MES_API_STATUS api_status;
463 };
464
465 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
466};
467
468union MESAPI__QUERY_MES_STATUS {
469 struct {
470 union MES_API_HEADER header;
471 bool mes_healthy; /* 0 - not healthy, 1 - healthy */
472 struct MES_API_STATUS api_status;
473 };
474
475 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
476};
477
478union MESAPI__PROGRAM_GDS {
479 struct {
480 union MES_API_HEADER header;
481 uint64_t process_context_addr;
482 uint32_t gds_base;
483 uint32_t gds_size;
484 uint32_t gws_base;
485 uint32_t gws_size;
486 uint32_t oa_mask;
487 struct MES_API_STATUS api_status;
488 };
489
490 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
491};
492
493union MESAPI__SET_DEBUG_VMID {
494 struct {
495 union MES_API_HEADER header;
496 struct MES_API_STATUS api_status;
497 union {
498 struct {
499 uint32_t use_gds : 1;
500 uint32_t operation : 2;
501 uint32_t reserved : 29;
502 } flags;
503 uint32_t u32All;
504 };
505 uint32_t reserved;
506 uint32_t debug_vmid;
507 uint64_t process_context_addr;
508 uint64_t page_table_base_addr;
509 uint64_t process_va_start;
510 uint64_t process_va_end;
511 uint32_t gds_base;
512 uint32_t gds_size;
513 uint32_t gws_base;
514 uint32_t gws_size;
515 uint32_t oa_mask;
516
517 /* output addr of the acquired vmid value */
518 uint64_t output_addr;
519 };
520
521 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
522};
523
524enum MESAPI_MISC_OPCODE {
525 MESAPI_MISC__WRITE_REG,
526 MESAPI_MISC__INV_GART,
527 MESAPI_MISC__QUERY_STATUS,
528 MESAPI_MISC__READ_REG,
529 MESAPI_MISC__WAIT_REG_MEM,
530 MESAPI_MISC__SET_SHADER_DEBUGGER,
531 MESAPI_MISC__MAX,
532};
533
534enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
535
536struct WRITE_REG {
537 uint32_t reg_offset;
538 uint32_t reg_value;
539};
540
541struct READ_REG {
542 uint32_t reg_offset;
543 uint64_t buffer_addr;
544};
545
546enum WRM_OPERATION {
547 WRM_OPERATION__WAIT_REG_MEM,
548 WRM_OPERATION__WR_WAIT_WR_REG,
549 WRM_OPERATION__MAX,
550};
551
552struct WAIT_REG_MEM {
553 enum WRM_OPERATION op;
554 uint32_t reference;
555 uint32_t mask;
556 uint32_t reg_offset1;
557 uint32_t reg_offset2;
558};
559
560struct INV_GART {
561 uint64_t inv_range_va_start;
562 uint64_t inv_range_size;
563};
564
565struct QUERY_STATUS {
566 uint32_t context_id;
567};
568
569struct SET_SHADER_DEBUGGER {
570 uint64_t process_context_addr;
571 union {
572 struct {
573 uint32_t single_memop : 1; /* SQ_DEBUG.single_memop */
574 uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */
575 uint32_t reserved : 29;
576 uint32_t process_ctx_flush : 1;
577 };
578 uint32_t u32all;
579 } flags;
580 uint32_t spi_gdbg_per_vmid_cntl;
581 uint32_t tcp_watch_cntl[4]; /* TCP_WATCHx_CNTL */
582 uint32_t trap_en;
583};
584
585union MESAPI__MISC {
586 struct {
587 union MES_API_HEADER header;
588 enum MESAPI_MISC_OPCODE opcode;
589 struct MES_API_STATUS api_status;
590
591 union {
592 struct WRITE_REG write_reg;
593 struct INV_GART inv_gart;
594 struct QUERY_STATUS query_status;
595 struct READ_REG read_reg;
596 struct WAIT_REG_MEM wait_reg_mem;
597 struct SET_SHADER_DEBUGGER set_shader_debugger;
598 enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
599
600 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
601 };
602 };
603
604 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
605};
606
607union MESAPI__UPDATE_ROOT_PAGE_TABLE {
608 struct {
609 union MES_API_HEADER header;
610 uint64_t page_table_base_addr;
611 uint64_t process_context_addr;
612 struct MES_API_STATUS api_status;
613 };
614
615 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
616};
617
618union MESAPI_AMD_LOG {
619 struct {
620 union MES_API_HEADER header;
621 uint64_t p_buffer_memory;
622 uint64_t p_buffer_size_used;
623 struct MES_API_STATUS api_status;
624 };
625
626 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
627};
628
629#pragma pack(pop)
630#endif
1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __MES_API_DEF_H__
25#define __MES_API_DEF_H__
26
27#pragma pack(push, 4)
28
29#define MES_API_VERSION 1
30
31/* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG */
32#define AMDGPU_MES_LOG_BUFFER_SIZE 0x4000
33
34/* Driver submits one API(cmd) as a single Frame and this command size is same
35 * for all API to ease the debugging and parsing of ring buffer.
36 */
37enum { API_FRAME_SIZE_IN_DWORDS = 64 };
38
39/* To avoid command in scheduler context to be overwritten whenenver mutilple
40 * interrupts come in, this creates another queue.
41 */
42enum { API_NUMBER_OF_COMMAND_MAX = 32 };
43
44enum MES_API_TYPE {
45 MES_API_TYPE_SCHEDULER = 1,
46 MES_API_TYPE_MAX
47};
48
49enum MES_SCH_API_OPCODE {
50 MES_SCH_API_SET_HW_RSRC = 0,
51 MES_SCH_API_SET_SCHEDULING_CONFIG = 1, /* agreegated db, quantums, etc */
52 MES_SCH_API_ADD_QUEUE = 2,
53 MES_SCH_API_REMOVE_QUEUE = 3,
54 MES_SCH_API_PERFORM_YIELD = 4,
55 MES_SCH_API_SET_GANG_PRIORITY_LEVEL = 5,
56 MES_SCH_API_SUSPEND = 6,
57 MES_SCH_API_RESUME = 7,
58 MES_SCH_API_RESET = 8,
59 MES_SCH_API_SET_LOG_BUFFER = 9,
60 MES_SCH_API_CHANGE_GANG_PRORITY = 10,
61 MES_SCH_API_QUERY_SCHEDULER_STATUS = 11,
62 MES_SCH_API_PROGRAM_GDS = 12,
63 MES_SCH_API_SET_DEBUG_VMID = 13,
64 MES_SCH_API_MISC = 14,
65 MES_SCH_API_UPDATE_ROOT_PAGE_TABLE = 15,
66 MES_SCH_API_AMD_LOG = 16,
67 MES_SCH_API_SET_HW_RSRC_1 = 19,
68 MES_SCH_API_MAX = 0xFF
69};
70
71union MES_API_HEADER {
72 struct {
73 uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
74 uint32_t opcode : 8;
75 uint32_t dwsize : 8; /* including header */
76 uint32_t reserved : 12;
77 };
78
79 uint32_t u32All;
80};
81
82enum MES_AMD_PRIORITY_LEVEL {
83 AMD_PRIORITY_LEVEL_LOW = 0,
84 AMD_PRIORITY_LEVEL_NORMAL = 1,
85 AMD_PRIORITY_LEVEL_MEDIUM = 2,
86 AMD_PRIORITY_LEVEL_HIGH = 3,
87 AMD_PRIORITY_LEVEL_REALTIME = 4,
88 AMD_PRIORITY_NUM_LEVELS
89};
90
91enum MES_QUEUE_TYPE {
92 MES_QUEUE_TYPE_GFX,
93 MES_QUEUE_TYPE_COMPUTE,
94 MES_QUEUE_TYPE_SDMA,
95 MES_QUEUE_TYPE_MAX,
96};
97
98struct MES_API_STATUS {
99 uint64_t api_completion_fence_addr;
100 uint64_t api_completion_fence_value;
101};
102
103enum { MAX_COMPUTE_PIPES = 8 };
104enum { MAX_GFX_PIPES = 2 };
105enum { MAX_SDMA_PIPES = 2 };
106
107enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
108enum { MAX_GFX_HQD_PER_PIPE = 8 };
109enum { MAX_SDMA_HQD_PER_PIPE = 10 };
110enum { MAX_SDMA_HQD_PER_PIPE_11_0 = 8 };
111
112enum { MAX_QUEUES_IN_A_GANG = 8 };
113
114enum VM_HUB_TYPE {
115 VM_HUB_TYPE_GC = 0,
116 VM_HUB_TYPE_MM = 1,
117 VM_HUB_TYPE_MAX,
118};
119
120enum { VMID_INVALID = 0xffff };
121
122enum { MAX_VMID_GCHUB = 16 };
123enum { MAX_VMID_MMHUB = 16 };
124
125enum SET_DEBUG_VMID_OPERATIONS {
126 DEBUG_VMID_OP_PROGRAM = 0,
127 DEBUG_VMID_OP_ALLOCATE = 1,
128 DEBUG_VMID_OP_RELEASE = 2
129};
130
131enum MES_LOG_OPERATION {
132 MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
133 MES_LOG_OPERATION_QUEUE_NEW_WORK = 1,
134 MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
135 MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
136 MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
137 MES_LOG_OPERATION_QUEUE_INVALID = 0xF,
138};
139
140enum MES_LOG_CONTEXT_STATE {
141 MES_LOG_CONTEXT_STATE_IDLE = 0,
142 MES_LOG_CONTEXT_STATE_RUNNING = 1,
143 MES_LOG_CONTEXT_STATE_READY = 2,
144 MES_LOG_CONTEXT_STATE_READY_STANDBY = 3,
145 MES_LOG_CONTEXT_STATE_INVALID = 0xF,
146};
147
148struct MES_LOG_CONTEXT_STATE_CHANGE {
149 void *h_context;
150 enum MES_LOG_CONTEXT_STATE new_context_state;
151};
152
153struct MES_LOG_QUEUE_NEW_WORK {
154 uint64_t h_queue;
155 uint64_t reserved;
156};
157
158struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
159 uint64_t h_queue;
160 uint64_t h_sync_object;
161};
162
163struct MES_LOG_QUEUE_NO_MORE_WORK {
164 uint64_t h_queue;
165 uint64_t reserved;
166};
167
168struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
169 uint64_t h_queue;
170 uint64_t h_sync_object;
171};
172
173struct MES_LOG_ENTRY_HEADER {
174 uint32_t first_free_entry_index;
175 uint32_t wraparound_count;
176 uint64_t number_of_entries;
177 uint64_t reserved[2];
178};
179
180struct MES_LOG_ENTRY_DATA {
181 uint64_t gpu_time_stamp;
182 uint32_t operation_type; /* operation_type is of MES_LOG_OPERATION type */
183 uint32_t reserved_operation_type_bits;
184 union {
185 struct MES_LOG_CONTEXT_STATE_CHANGE context_state_change;
186 struct MES_LOG_QUEUE_NEW_WORK queue_new_work;
187 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
188 struct MES_LOG_QUEUE_NO_MORE_WORK queue_no_more_work;
189 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT queue_wait_sync_object;
190 uint64_t all[2];
191 };
192};
193
194struct MES_LOG_BUFFER {
195 struct MES_LOG_ENTRY_HEADER header;
196 struct MES_LOG_ENTRY_DATA entries[1];
197};
198
199enum MES_SWIP_TO_HWIP_DEF {
200 MES_MAX_HWIP_SEGMENT = 8,
201};
202
203union MESAPI_SET_HW_RESOURCES {
204 struct {
205 union MES_API_HEADER header;
206 uint32_t vmid_mask_mmhub;
207 uint32_t vmid_mask_gfxhub;
208 uint32_t gds_size;
209 uint32_t paging_vmid;
210 uint32_t compute_hqd_mask[MAX_COMPUTE_PIPES];
211 uint32_t gfx_hqd_mask[MAX_GFX_PIPES];
212 uint32_t sdma_hqd_mask[MAX_SDMA_PIPES];
213 uint32_t aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
214 uint64_t g_sch_ctx_gpu_mc_ptr;
215 uint64_t query_status_fence_gpu_mc_ptr;
216 uint32_t gc_base[MES_MAX_HWIP_SEGMENT];
217 uint32_t mmhub_base[MES_MAX_HWIP_SEGMENT];
218 uint32_t osssys_base[MES_MAX_HWIP_SEGMENT];
219 struct MES_API_STATUS api_status;
220 union {
221 struct {
222 uint32_t disable_reset : 1;
223 uint32_t use_different_vmid_compute : 1;
224 uint32_t disable_mes_log : 1;
225 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
226 uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
227 uint32_t second_gfx_pipe_enabled : 1;
228 uint32_t enable_level_process_quantum_check : 1;
229 uint32_t legacy_sch_mode : 1;
230 uint32_t disable_add_queue_wptr_mc_addr : 1;
231 uint32_t enable_mes_event_int_logging : 1;
232 uint32_t enable_reg_active_poll : 1;
233 uint32_t use_disable_queue_in_legacy_uq_preemption : 1;
234 uint32_t send_write_data : 1;
235 uint32_t os_tdr_timeout_override : 1;
236 uint32_t use_rs64mem_for_proc_gang_ctx : 1;
237 uint32_t use_add_queue_unmap_flag_addr : 1;
238 uint32_t enable_mes_sch_stb_log : 1;
239 uint32_t limit_single_process : 1;
240 uint32_t is_strix_tmz_wa_enabled :1;
241 uint32_t reserved : 13;
242 };
243 uint32_t uint32_t_all;
244 };
245 uint32_t oversubscription_timer;
246 uint64_t doorbell_info;
247 uint64_t event_intr_history_gpu_mc_ptr;
248 uint64_t timestamp;
249 uint32_t os_tdr_timeout_in_sec;
250 };
251
252 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
253};
254
255union MESAPI_SET_HW_RESOURCES_1 {
256 struct {
257 union MES_API_HEADER header;
258 struct MES_API_STATUS api_status;
259 uint64_t timestamp;
260 union {
261 struct {
262 uint32_t enable_mes_info_ctx : 1;
263 uint32_t reserved : 31;
264 };
265 uint32_t uint32_all;
266 };
267 uint64_t mes_info_ctx_mc_addr;
268 uint32_t mes_info_ctx_size;
269 uint32_t mes_kiq_unmap_timeout; // unit is 100ms
270 };
271
272 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
273};
274
275union MESAPI__ADD_QUEUE {
276 struct {
277 union MES_API_HEADER header;
278 uint32_t process_id;
279 uint64_t page_table_base_addr;
280 uint64_t process_va_start;
281 uint64_t process_va_end;
282 uint64_t process_quantum;
283 uint64_t process_context_addr;
284 uint64_t gang_quantum;
285 uint64_t gang_context_addr;
286 uint32_t inprocess_gang_priority;
287 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
288 uint32_t doorbell_offset;
289 uint64_t mqd_addr;
290 uint64_t wptr_addr;
291 uint64_t h_context;
292 uint64_t h_queue;
293 enum MES_QUEUE_TYPE queue_type;
294 uint32_t gds_base;
295 uint32_t gds_size;
296 uint32_t gws_base;
297 uint32_t gws_size;
298 uint32_t oa_mask;
299 uint64_t trap_handler_addr;
300 uint32_t vm_context_cntl;
301
302 struct {
303 uint32_t paging : 1;
304 uint32_t debug_vmid : 4;
305 uint32_t program_gds : 1;
306 uint32_t is_gang_suspended : 1;
307 uint32_t is_tmz_queue : 1;
308 uint32_t map_kiq_utility_queue : 1;
309 uint32_t is_kfd_process : 1;
310 uint32_t trap_en : 1;
311 uint32_t is_aql_queue : 1;
312 uint32_t skip_process_ctx_clear : 1;
313 uint32_t map_legacy_kq : 1;
314 uint32_t exclusively_scheduled : 1;
315 uint32_t is_long_running : 1;
316 uint32_t is_dwm_queue : 1;
317 uint32_t is_video_blit_queue : 1;
318 uint32_t reserved : 14;
319 };
320 struct MES_API_STATUS api_status;
321 uint64_t tma_addr;
322 uint32_t sch_id;
323 uint64_t timestamp;
324 uint32_t process_context_array_index;
325 uint32_t gang_context_array_index;
326 uint32_t pipe_id;
327 uint32_t queue_id;
328 uint32_t alignment_mode_setting;
329 uint64_t unmap_flag_addr;
330 };
331
332 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
333};
334
335union MESAPI__REMOVE_QUEUE {
336 struct {
337 union MES_API_HEADER header;
338 uint32_t doorbell_offset;
339 uint64_t gang_context_addr;
340
341 struct {
342 uint32_t unmap_legacy_gfx_queue : 1;
343 uint32_t unmap_kiq_utility_queue : 1;
344 uint32_t preempt_legacy_gfx_queue : 1;
345 uint32_t unmap_legacy_queue : 1;
346 uint32_t reserved : 28;
347 };
348 struct MES_API_STATUS api_status;
349
350 uint32_t pipe_id;
351 uint32_t queue_id;
352
353 uint64_t tf_addr;
354 uint32_t tf_data;
355
356 enum MES_QUEUE_TYPE queue_type;
357 };
358
359 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
360};
361
362union MESAPI__SET_SCHEDULING_CONFIG {
363 struct {
364 union MES_API_HEADER header;
365 /* Grace period when preempting another priority band for this
366 * priority band. The value for idle priority band is ignored,
367 * as it never preempts other bands.
368 */
369 uint64_t grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
370 /* Default quantum for scheduling across processes within
371 * a priority band.
372 */
373 uint64_t process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
374 /* Default grace period for processes that preempt each other
375 * within a priority band.
376 */
377 uint64_t process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
378 /* For normal level this field specifies the target GPU
379 * percentage in situations when it's starved by the high level.
380 * Valid values are between 0 and 50, with the default being 10.
381 */
382 uint32_t normal_yield_percent;
383 struct MES_API_STATUS api_status;
384 };
385
386 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
387};
388
389union MESAPI__PERFORM_YIELD {
390 struct {
391 union MES_API_HEADER header;
392 uint32_t dummy;
393 struct MES_API_STATUS api_status;
394 };
395
396 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
397};
398
399union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
400 struct {
401 union MES_API_HEADER header;
402 uint32_t inprocess_gang_priority;
403 enum MES_AMD_PRIORITY_LEVEL gang_global_priority_level;
404 uint64_t gang_quantum;
405 uint64_t gang_context_addr;
406 struct MES_API_STATUS api_status;
407 };
408
409 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
410};
411
412union MESAPI__SUSPEND {
413 struct {
414 union MES_API_HEADER header;
415 /* false - suspend all gangs; true - specific gang */
416 struct {
417 uint32_t suspend_all_gangs : 1;
418 uint32_t reserved : 31;
419 };
420 /* gang_context_addr is valid only if suspend_all = false */
421 uint64_t gang_context_addr;
422
423 uint64_t suspend_fence_addr;
424 uint32_t suspend_fence_value;
425
426 struct MES_API_STATUS api_status;
427 };
428
429 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
430};
431
432union MESAPI__RESUME {
433 struct {
434 union MES_API_HEADER header;
435 /* false - resume all gangs; true - specified gang */
436 struct {
437 uint32_t resume_all_gangs : 1;
438 uint32_t reserved : 31;
439 };
440 /* valid only if resume_all_gangs = false */
441 uint64_t gang_context_addr;
442
443 struct MES_API_STATUS api_status;
444 };
445
446 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
447};
448
449union MESAPI__RESET {
450 struct {
451 union MES_API_HEADER header;
452
453 struct {
454 /* Only reset the queue given by doorbell_offset (not entire gang) */
455 uint32_t reset_queue_only : 1;
456 /* Hang detection first then reset any queues that are hung */
457 uint32_t hang_detect_then_reset : 1;
458 /* Only do hang detection (no reset) */
459 uint32_t hang_detect_only : 1;
460 /* Rest HP and LP kernel queues not managed by MES */
461 uint32_t reset_legacy_gfx : 1;
462 uint32_t reserved : 28;
463 };
464
465 uint64_t gang_context_addr;
466
467 /* valid only if reset_queue_only = true */
468 uint32_t doorbell_offset;
469
470 /* valid only if hang_detect_then_reset = true */
471 uint64_t doorbell_offset_addr;
472 enum MES_QUEUE_TYPE queue_type;
473
474 /* valid only if reset_legacy_gfx = true */
475 uint32_t pipe_id_lp;
476 uint32_t queue_id_lp;
477 uint32_t vmid_id_lp;
478 uint64_t mqd_mc_addr_lp;
479 uint32_t doorbell_offset_lp;
480 uint64_t wptr_addr_lp;
481
482 uint32_t pipe_id_hp;
483 uint32_t queue_id_hp;
484 uint32_t vmid_id_hp;
485 uint64_t mqd_mc_addr_hp;
486 uint32_t doorbell_offset_hp;
487 uint64_t wptr_addr_hp;
488
489 struct MES_API_STATUS api_status;
490 };
491
492 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
493};
494
495union MESAPI__SET_LOGGING_BUFFER {
496 struct {
497 union MES_API_HEADER header;
498 /* There are separate log buffers for each queue type */
499 enum MES_QUEUE_TYPE log_type;
500 /* Log buffer GPU Address */
501 uint64_t logging_buffer_addr;
502 /* number of entries in the log buffer */
503 uint32_t number_of_entries;
504 /* Entry index at which CPU interrupt needs to be signalled */
505 uint32_t interrupt_entry;
506
507 struct MES_API_STATUS api_status;
508 };
509
510 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
511};
512
513union MESAPI__QUERY_MES_STATUS {
514 struct {
515 union MES_API_HEADER header;
516 bool mes_healthy; /* 0 - not healthy, 1 - healthy */
517 struct MES_API_STATUS api_status;
518 };
519
520 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
521};
522
523union MESAPI__PROGRAM_GDS {
524 struct {
525 union MES_API_HEADER header;
526 uint64_t process_context_addr;
527 uint32_t gds_base;
528 uint32_t gds_size;
529 uint32_t gws_base;
530 uint32_t gws_size;
531 uint32_t oa_mask;
532 struct MES_API_STATUS api_status;
533 };
534
535 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
536};
537
538union MESAPI__SET_DEBUG_VMID {
539 struct {
540 union MES_API_HEADER header;
541 struct MES_API_STATUS api_status;
542 union {
543 struct {
544 uint32_t use_gds : 1;
545 uint32_t operation : 2;
546 uint32_t reserved : 29;
547 } flags;
548 uint32_t u32All;
549 };
550 uint32_t reserved;
551 uint32_t debug_vmid;
552 uint64_t process_context_addr;
553 uint64_t page_table_base_addr;
554 uint64_t process_va_start;
555 uint64_t process_va_end;
556 uint32_t gds_base;
557 uint32_t gds_size;
558 uint32_t gws_base;
559 uint32_t gws_size;
560 uint32_t oa_mask;
561
562 /* output addr of the acquired vmid value */
563 uint64_t output_addr;
564 };
565
566 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
567};
568
569enum MESAPI_MISC_OPCODE {
570 MESAPI_MISC__WRITE_REG,
571 MESAPI_MISC__INV_GART,
572 MESAPI_MISC__QUERY_STATUS,
573 MESAPI_MISC__READ_REG,
574 MESAPI_MISC__WAIT_REG_MEM,
575 MESAPI_MISC__SET_SHADER_DEBUGGER,
576 MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE,
577 MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES,
578 MESAPI_MISC__CHANGE_CONFIG,
579 MESAPI_MISC__LAUNCH_CLEANER_SHADER,
580
581 MESAPI_MISC__MAX,
582};
583
584enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
585
586struct WRITE_REG {
587 uint32_t reg_offset;
588 uint32_t reg_value;
589};
590
591struct READ_REG {
592 uint32_t reg_offset;
593 uint64_t buffer_addr;
594};
595
596enum WRM_OPERATION {
597 WRM_OPERATION__WAIT_REG_MEM,
598 WRM_OPERATION__WR_WAIT_WR_REG,
599 WRM_OPERATION__MAX,
600};
601
602struct WAIT_REG_MEM {
603 enum WRM_OPERATION op;
604 uint32_t reference;
605 uint32_t mask;
606 uint32_t reg_offset1;
607 uint32_t reg_offset2;
608};
609
610struct INV_GART {
611 uint64_t inv_range_va_start;
612 uint64_t inv_range_size;
613};
614
615struct QUERY_STATUS {
616 uint32_t context_id;
617};
618
619struct SET_SHADER_DEBUGGER {
620 uint64_t process_context_addr;
621 union {
622 struct {
623 uint32_t single_memop : 1; /* SQ_DEBUG.single_memop */
624 uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */
625 uint32_t reserved : 29;
626 uint32_t process_ctx_flush : 1;
627 };
628 uint32_t u32all;
629 } flags;
630 uint32_t spi_gdbg_per_vmid_cntl;
631 uint32_t tcp_watch_cntl[4]; /* TCP_WATCHx_CNTL */
632 uint32_t trap_en;
633};
634
635enum MESAPI_MISC__CHANGE_CONFIG_OPTION {
636 MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0,
637 MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1,
638 MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG = 2,
639
640 MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F
641};
642
643struct CHANGE_CONFIG {
644 enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode;
645 union {
646 struct {
647 uint32_t limit_single_process : 1;
648 uint32_t enable_hws_logging_buffer : 1;
649 uint32_t reserved : 31;
650 } bits;
651 uint32_t all;
652 } option;
653
654 struct {
655 uint32_t tdr_level;
656 uint32_t tdr_delay;
657 } tdr_config;
658};
659
660union MESAPI__MISC {
661 struct {
662 union MES_API_HEADER header;
663 enum MESAPI_MISC_OPCODE opcode;
664 struct MES_API_STATUS api_status;
665
666 union {
667 struct WRITE_REG write_reg;
668 struct INV_GART inv_gart;
669 struct QUERY_STATUS query_status;
670 struct READ_REG read_reg;
671 struct WAIT_REG_MEM wait_reg_mem;
672 struct SET_SHADER_DEBUGGER set_shader_debugger;
673 enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
674 struct CHANGE_CONFIG change_config;
675
676 uint32_t data[MISC_DATA_MAX_SIZE_IN_DWORDS];
677 };
678 };
679
680 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
681};
682
683union MESAPI__UPDATE_ROOT_PAGE_TABLE {
684 struct {
685 union MES_API_HEADER header;
686 uint64_t page_table_base_addr;
687 uint64_t process_context_addr;
688 struct MES_API_STATUS api_status;
689 };
690
691 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
692};
693
694union MESAPI_AMD_LOG {
695 struct {
696 union MES_API_HEADER header;
697 uint64_t p_buffer_memory;
698 uint64_t p_buffer_size_used;
699 struct MES_API_STATUS api_status;
700 };
701
702 uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
703};
704
705#pragma pack(pop)
706#endif