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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2013 - 2021 Intel Corporation. */
3
4#ifndef _I40E_H_
5#define _I40E_H_
6
7#include <linux/pci.h>
8#include <linux/ptp_clock_kernel.h>
9#include <linux/types.h>
10#include <linux/avf/virtchnl.h>
11#include <linux/net/intel/i40e_client.h>
12#include <net/devlink.h>
13#include <net/pkt_cls.h>
14#include <net/udp_tunnel.h>
15#include "i40e_dcb.h"
16#include "i40e_debug.h"
17#include "i40e_devlink.h"
18#include "i40e_io.h"
19#include "i40e_prototype.h"
20#include "i40e_register.h"
21#include "i40e_txrx.h"
22
23/* Useful i40e defaults */
24#define I40E_MAX_VEB 16
25
26#define I40E_MAX_NUM_DESCRIPTORS 4096
27#define I40E_MAX_NUM_DESCRIPTORS_XL710 8160
28#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
29#define I40E_DEFAULT_NUM_DESCRIPTORS 512
30#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
31#define I40E_MIN_NUM_DESCRIPTORS 64
32#define I40E_MIN_MSIX 2
33#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
34#define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
35/* max 16 qps */
36#define i40e_default_queues_per_vmdq(pf) \
37 (test_bit(I40E_HW_CAP_RSS_AQ, (pf)->hw.caps) ? 4 : 1)
38#define I40E_DEFAULT_QUEUES_PER_VF 4
39#define I40E_MAX_VF_QUEUES 16
40#define i40e_pf_get_max_q_per_tc(pf) \
41 (test_bit(I40E_HW_CAP_128_QP_RSS, (pf)->hw.caps) ? 128 : 64)
42#define I40E_FDIR_RING_COUNT 32
43#define I40E_MAX_AQ_BUF_SIZE 4096
44#define I40E_AQ_LEN 256
45#define I40E_MIN_ARQ_LEN 1
46#define I40E_MIN_ASQ_LEN 2
47#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
48#define I40E_MAX_USER_PRIORITY 8
49#define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
50#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
51#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
52
53#define I40E_PHY_DEBUG_ALL \
54 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
55 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
56
57#define I40E_OEM_EETRACK_ID 0xffffffff
58#define I40E_NVM_VERSION_LO_MASK GENMASK(7, 0)
59#define I40E_NVM_VERSION_HI_MASK GENMASK(15, 12)
60#define I40E_OEM_VER_BUILD_MASK GENMASK(23, 8)
61#define I40E_OEM_VER_PATCH_MASK GENMASK(7, 0)
62#define I40E_OEM_VER_MASK GENMASK(31, 24)
63#define I40E_OEM_GEN_MASK GENMASK(31, 24)
64#define I40E_OEM_SNAP_MASK GENMASK(23, 16)
65#define I40E_OEM_RELEASE_MASK GENMASK(15, 0)
66
67#define I40E_RX_DESC(R, i) \
68 (&(((union i40e_rx_desc *)((R)->desc))[i]))
69#define I40E_TX_DESC(R, i) \
70 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
71#define I40E_TX_CTXTDESC(R, i) \
72 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
73#define I40E_TX_FDIRDESC(R, i) \
74 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
75
76/* BW rate limiting */
77#define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
78#define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
79#define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */
80
81/* driver state flags */
82enum i40e_state {
83 __I40E_TESTING,
84 __I40E_CONFIG_BUSY,
85 __I40E_CONFIG_DONE,
86 __I40E_DOWN,
87 __I40E_SERVICE_SCHED,
88 __I40E_ADMINQ_EVENT_PENDING,
89 __I40E_MDD_EVENT_PENDING,
90 __I40E_VFLR_EVENT_PENDING,
91 __I40E_RESET_RECOVERY_PENDING,
92 __I40E_TIMEOUT_RECOVERY_PENDING,
93 __I40E_MISC_IRQ_REQUESTED,
94 __I40E_RESET_INTR_RECEIVED,
95 __I40E_REINIT_REQUESTED,
96 __I40E_PF_RESET_REQUESTED,
97 __I40E_PF_RESET_AND_REBUILD_REQUESTED,
98 __I40E_CORE_RESET_REQUESTED,
99 __I40E_GLOBAL_RESET_REQUESTED,
100 __I40E_EMP_RESET_INTR_RECEIVED,
101 __I40E_SUSPENDED,
102 __I40E_PTP_TX_IN_PROGRESS,
103 __I40E_BAD_EEPROM,
104 __I40E_DOWN_REQUESTED,
105 __I40E_FD_FLUSH_REQUESTED,
106 __I40E_FD_ATR_AUTO_DISABLED,
107 __I40E_FD_SB_AUTO_DISABLED,
108 __I40E_RESET_FAILED,
109 __I40E_PORT_SUSPENDED,
110 __I40E_VF_DISABLE,
111 __I40E_MACVLAN_SYNC_PENDING,
112 __I40E_TEMP_LINK_POLLING,
113 __I40E_CLIENT_SERVICE_REQUESTED,
114 __I40E_CLIENT_L2_CHANGE,
115 __I40E_CLIENT_RESET,
116 __I40E_VIRTCHNL_OP_PENDING,
117 __I40E_RECOVERY_MODE,
118 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */
119 __I40E_IN_REMOVE,
120 __I40E_VFS_RELEASING,
121 /* This must be last as it determines the size of the BITMAP */
122 __I40E_STATE_SIZE__,
123};
124
125#define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
126#define I40E_PF_RESET_AND_REBUILD_FLAG \
127 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)
128
129/* VSI state flags */
130enum i40e_vsi_state {
131 __I40E_VSI_DOWN,
132 __I40E_VSI_NEEDS_RESTART,
133 __I40E_VSI_SYNCING_FILTERS,
134 __I40E_VSI_OVERFLOW_PROMISC,
135 __I40E_VSI_REINIT_REQUESTED,
136 __I40E_VSI_DOWN_REQUESTED,
137 __I40E_VSI_RELEASING,
138 /* This must be last as it determines the size of the BITMAP */
139 __I40E_VSI_STATE_SIZE__,
140};
141
142enum i40e_pf_flags {
143 I40E_FLAG_MSI_ENA,
144 I40E_FLAG_MSIX_ENA,
145 I40E_FLAG_RSS_ENA,
146 I40E_FLAG_VMDQ_ENA,
147 I40E_FLAG_SRIOV_ENA,
148 I40E_FLAG_DCB_CAPABLE,
149 I40E_FLAG_DCB_ENA,
150 I40E_FLAG_FD_SB_ENA,
151 I40E_FLAG_FD_ATR_ENA,
152 I40E_FLAG_MFP_ENA,
153 I40E_FLAG_HW_ATR_EVICT_ENA,
154 I40E_FLAG_VEB_MODE_ENA,
155 I40E_FLAG_VEB_STATS_ENA,
156 I40E_FLAG_LINK_POLLING_ENA,
157 I40E_FLAG_TRUE_PROMISC_ENA,
158 I40E_FLAG_LEGACY_RX_ENA,
159 I40E_FLAG_PTP_ENA,
160 I40E_FLAG_IWARP_ENA,
161 I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA,
162 I40E_FLAG_SOURCE_PRUNING_DIS,
163 I40E_FLAG_TC_MQPRIO_ENA,
164 I40E_FLAG_FD_SB_INACTIVE,
165 I40E_FLAG_FD_SB_TO_CLOUD_FILTER,
166 I40E_FLAG_FW_LLDP_DIS,
167 I40E_FLAG_RS_FEC,
168 I40E_FLAG_BASE_R_FEC,
169 /* TOTAL_PORT_SHUTDOWN_ENA
170 * Allows to physically disable the link on the NIC's port.
171 * If enabled, (after link down request from the OS)
172 * no link, traffic or led activity is possible on that port.
173 *
174 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA is set, the
175 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA must be explicitly forced
176 * to true and cannot be disabled by system admin at that time.
177 * The functionalities are exclusive in terms of configuration, but
178 * they also have similar behavior (allowing to disable physical
179 * link of the port), with following differences:
180 * - LINK_DOWN_ON_CLOSE_ENA is configurable at host OS run-time and
181 * is supported by whole family of 7xx Intel Ethernet Controllers
182 * - TOTAL_PORT_SHUTDOWN_ENA may be enabled only before OS loads
183 * (in BIOS) only if motherboard's BIOS and NIC's FW has support of it
184 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought
185 * down by sending phy_type=0 to NIC's FW
186 * - when TOTAL_PORT_SHUTDOWN_ENA is used, phy_type is not altered,
187 * instead the link is being brought down by clearing
188 * bit (I40E_AQ_PHY_ENABLE_LINK) in abilities field of
189 * i40e_aq_set_phy_config structure
190 */
191 I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA,
192 I40E_FLAG_VF_VLAN_PRUNING_ENA,
193 I40E_PF_FLAGS_NBITS, /* must be last */
194};
195
196enum i40e_interrupt_policy {
197 I40E_INTERRUPT_BEST_CASE,
198 I40E_INTERRUPT_MEDIUM,
199 I40E_INTERRUPT_LOWEST
200};
201
202struct i40e_lump_tracking {
203 u16 num_entries;
204 u16 list[];
205#define I40E_PILE_VALID_BIT 0x8000
206#define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
207};
208
209#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
210#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
211#define I40E_FDIR_BUFFER_FULL_MARGIN 10
212#define I40E_FDIR_BUFFER_HEAD_ROOM 32
213#define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
214
215#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
216#define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
217#define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
218
219enum i40e_fd_stat_idx {
220 I40E_FD_STAT_ATR,
221 I40E_FD_STAT_SB,
222 I40E_FD_STAT_ATR_TUNNEL,
223 I40E_FD_STAT_PF_COUNT
224};
225#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
226#define I40E_FD_ATR_STAT_IDX(pf_id) \
227 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
228#define I40E_FD_SB_STAT_IDX(pf_id) \
229 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
230#define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
231 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
232
233/* The following structure contains the data parsed from the user-defined
234 * field of the ethtool_rx_flow_spec structure.
235 */
236struct i40e_rx_flow_userdef {
237 bool flex_filter;
238 u16 flex_word;
239 u16 flex_offset;
240};
241
242struct i40e_fdir_filter {
243 struct hlist_node fdir_node;
244 /* filter ipnut set */
245 u8 flow_type;
246 u8 ipl4_proto;
247 /* TX packet view of src and dst */
248 __be32 dst_ip;
249 __be32 src_ip;
250 __be32 dst_ip6[4];
251 __be32 src_ip6[4];
252 __be16 src_port;
253 __be16 dst_port;
254 __be32 sctp_v_tag;
255
256 __be16 vlan_etype;
257 __be16 vlan_tag;
258 /* Flexible data to match within the packet payload */
259 __be16 flex_word;
260 u16 flex_offset;
261 bool flex_filter;
262
263 /* filter control */
264 u16 q_index;
265 u8 flex_off;
266 u8 pctype;
267 u16 dest_vsi;
268 u8 dest_ctl;
269 u8 fd_status;
270 u16 cnt_index;
271 u32 fd_id;
272};
273
274#define I40E_CLOUD_FIELD_OMAC BIT(0)
275#define I40E_CLOUD_FIELD_IMAC BIT(1)
276#define I40E_CLOUD_FIELD_IVLAN BIT(2)
277#define I40E_CLOUD_FIELD_TEN_ID BIT(3)
278#define I40E_CLOUD_FIELD_IIP BIT(4)
279
280#define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
281#define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
282#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
283 I40E_CLOUD_FIELD_IVLAN)
284#define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
285 I40E_CLOUD_FIELD_TEN_ID)
286#define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
287 I40E_CLOUD_FIELD_IMAC | \
288 I40E_CLOUD_FIELD_TEN_ID)
289#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
290 I40E_CLOUD_FIELD_IVLAN | \
291 I40E_CLOUD_FIELD_TEN_ID)
292#define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
293
294struct i40e_cloud_filter {
295 struct hlist_node cloud_node;
296 unsigned long cookie;
297 /* cloud filter input set follows */
298 u8 dst_mac[ETH_ALEN];
299 u8 src_mac[ETH_ALEN];
300 __be16 vlan_id;
301 u16 seid; /* filter control */
302 __be16 dst_port;
303 __be16 src_port;
304 u32 tenant_id;
305 union {
306 struct {
307 struct in_addr dst_ip;
308 struct in_addr src_ip;
309 } v4;
310 struct {
311 struct in6_addr dst_ip6;
312 struct in6_addr src_ip6;
313 } v6;
314 } ip;
315#define dst_ipv6 ip.v6.dst_ip6.s6_addr32
316#define src_ipv6 ip.v6.src_ip6.s6_addr32
317#define dst_ipv4 ip.v4.dst_ip.s_addr
318#define src_ipv4 ip.v4.src_ip.s_addr
319 u16 n_proto; /* Ethernet Protocol */
320 u8 ip_proto; /* IPPROTO value */
321 u8 flags;
322#define I40E_CLOUD_TNL_TYPE_NONE 0xff
323 u8 tunnel_type;
324};
325
326#define I40E_DCB_PRIO_TYPE_STRICT 0
327#define I40E_DCB_PRIO_TYPE_ETS 1
328#define I40E_DCB_STRICT_PRIO_CREDITS 127
329/* DCB per TC information data structure */
330struct i40e_tc_info {
331 u16 qoffset; /* Queue offset from base queue */
332 u16 qcount; /* Total Queues */
333 u8 netdev_tc; /* Netdev TC index if netdev associated */
334};
335
336/* TC configuration data structure */
337struct i40e_tc_configuration {
338 u8 numtc; /* Total number of enabled TCs */
339 u8 enabled_tc; /* TC map */
340 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
341};
342
343#define I40E_UDP_PORT_INDEX_UNUSED 255
344struct i40e_udp_port_config {
345 /* AdminQ command interface expects port number in Host byte order */
346 u16 port;
347 u8 type;
348 u8 filter_index;
349};
350
351/* macros related to FLX_PIT */
352#define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
353 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
354 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
355#define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
356 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
357 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
358#define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
359 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
360 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
361#define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
362 I40E_FLEX_SET_FSIZE(fsize) | \
363 I40E_FLEX_SET_SRC_WORD(src))
364
365
366#define I40E_MAX_FLEX_SRC_OFFSET 0x1F
367
368/* macros related to GLQF_ORT */
369#define I40E_ORT_SET_IDX(idx) (((idx) << \
370 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
371 I40E_GLQF_ORT_PIT_INDX_MASK)
372
373#define I40E_ORT_SET_COUNT(count) (((count) << \
374 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
375 I40E_GLQF_ORT_FIELD_CNT_MASK)
376
377#define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
378 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
379 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
380
381#define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
382 I40E_ORT_SET_COUNT(count) | \
383 I40E_ORT_SET_PAYLOAD(payload))
384
385#define I40E_L3_GLQF_ORT_IDX 34
386#define I40E_L4_GLQF_ORT_IDX 35
387
388/* Flex PIT register index */
389#define I40E_FLEX_PIT_IDX_START_L3 3
390#define I40E_FLEX_PIT_IDX_START_L4 6
391
392#define I40E_FLEX_PIT_TABLE_SIZE 3
393
394#define I40E_FLEX_DEST_UNUSED 63
395
396#define I40E_FLEX_INDEX_ENTRIES 8
397
398/* Flex MASK to disable all flexible entries */
399#define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
400 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
401 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
402 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
403
404#define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \
405 (I40E_QINT_TQCTL_CAUSE_ENA_MASK | \
406 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \
407 ((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \
408 ((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \
409 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT))
410
411#define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \
412 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \
413 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
414 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \
415 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \
416 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))
417
418struct i40e_flex_pit {
419 struct list_head list;
420 u16 src_offset;
421 u8 pit_index;
422};
423
424struct i40e_fwd_adapter {
425 struct net_device *netdev;
426 int bit_no;
427};
428
429struct i40e_channel {
430 struct list_head list;
431 bool initialized;
432 u8 type;
433 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
434 u16 stat_counter_idx;
435 u16 base_queue;
436 u16 num_queue_pairs; /* Requested by user */
437 u16 seid;
438
439 u8 enabled_tc;
440 struct i40e_aqc_vsi_properties_data info;
441
442 u64 max_tx_rate;
443 struct i40e_fwd_adapter *fwd;
444
445 /* track this channel belongs to which VSI */
446 struct i40e_vsi *parent_vsi;
447};
448
449struct i40e_ptp_pins_settings;
450
451static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)
452{
453 return !!ch->fwd;
454}
455
456static inline const u8 *i40e_channel_mac(struct i40e_channel *ch)
457{
458 if (i40e_is_channel_macvlan(ch))
459 return ch->fwd->netdev->dev_addr;
460 else
461 return NULL;
462}
463
464/* struct that defines the Ethernet device */
465struct i40e_pf {
466 struct pci_dev *pdev;
467 struct devlink_port devlink_port;
468 struct i40e_hw hw;
469 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
470 struct msix_entry *msix_entries;
471
472 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
473 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
474 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
475 u16 num_req_vfs; /* num VFs requested for this PF */
476 u16 num_vf_qps; /* num queue pairs per VF */
477 u16 num_lan_qps; /* num lan queues this PF has set up */
478 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
479 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
480 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
481 int iwarp_base_vector;
482 int queues_left; /* queues left unclaimed */
483 u16 alloc_rss_size; /* allocated RSS queues */
484 u16 rss_size_max; /* HW defined max RSS queues */
485 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
486 u16 num_alloc_vsi; /* num VSIs this driver supports */
487 bool wol_en;
488
489 struct hlist_head fdir_filter_list;
490 u16 fdir_pf_active_filters;
491 unsigned long fd_flush_timestamp;
492 u32 fd_flush_cnt;
493 u32 fd_add_err;
494 u32 fd_atr_cnt;
495
496 /* Book-keeping of side-band filter count per flow-type.
497 * This is used to detect and handle input set changes for
498 * respective flow-type.
499 */
500 u16 fd_tcp4_filter_cnt;
501 u16 fd_udp4_filter_cnt;
502 u16 fd_sctp4_filter_cnt;
503 u16 fd_ip4_filter_cnt;
504
505 u16 fd_tcp6_filter_cnt;
506 u16 fd_udp6_filter_cnt;
507 u16 fd_sctp6_filter_cnt;
508 u16 fd_ip6_filter_cnt;
509
510 /* Flexible filter table values that need to be programmed into
511 * hardware, which expects L3 and L4 to be programmed separately. We
512 * need to ensure that the values are in ascended order and don't have
513 * duplicates, so we track each L3 and L4 values in separate lists.
514 */
515 struct list_head l3_flex_pit_list;
516 struct list_head l4_flex_pit_list;
517
518 struct udp_tunnel_nic_shared udp_tunnel_shared;
519 struct udp_tunnel_nic_info udp_tunnel_nic;
520
521 struct hlist_head cloud_filter_list;
522 u16 num_cloud_filters;
523
524 u16 rx_itr_default;
525 u16 tx_itr_default;
526 u32 msg_enable;
527 char int_name[I40E_INT_NAME_STR_LEN];
528 unsigned long service_timer_period;
529 unsigned long service_timer_previous;
530 struct timer_list service_timer;
531 struct work_struct service_task;
532
533 DECLARE_BITMAP(flags, I40E_PF_FLAGS_NBITS);
534 struct i40e_client_instance *cinst;
535 bool stat_offsets_loaded;
536 struct i40e_hw_port_stats stats;
537 struct i40e_hw_port_stats stats_offsets;
538 u32 tx_timeout_count;
539 u32 tx_timeout_recovery_level;
540 unsigned long tx_timeout_last_recovery;
541 u32 hw_csum_rx_error;
542 u32 led_status;
543 u16 corer_count; /* Core reset count */
544 u16 globr_count; /* Global reset count */
545 u16 empr_count; /* EMP reset count */
546 u16 pfr_count; /* PF reset count */
547 u16 sw_int_count; /* SW interrupt count */
548
549 struct mutex switch_mutex;
550 u16 lan_vsi; /* our default LAN VSI */
551 u16 lan_veb; /* initial relay, if exists */
552#define I40E_NO_VEB 0xffff
553#define I40E_NO_VSI 0xffff
554 u16 next_vsi; /* Next unallocated VSI - 0-based! */
555 struct i40e_vsi **vsi;
556 struct i40e_veb *veb[I40E_MAX_VEB];
557
558 struct i40e_lump_tracking *qp_pile;
559 struct i40e_lump_tracking *irq_pile;
560
561 /* switch config info */
562 u16 main_vsi_seid;
563 u16 mac_seid;
564#ifdef CONFIG_DEBUG_FS
565 struct dentry *i40e_dbg_pf;
566#endif /* CONFIG_DEBUG_FS */
567 bool cur_promisc;
568
569 /* sr-iov config info */
570 struct i40e_vf *vf;
571 int num_alloc_vfs; /* actual number of VFs allocated */
572 u32 vf_aq_requests;
573 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
574
575 /* DCBx/DCBNL capability for PF that indicates
576 * whether DCBx is managed by firmware or host
577 * based agent (LLDPAD). Also, indicates what
578 * flavor of DCBx protocol (IEEE/CEE) is supported
579 * by the device. For now we're supporting IEEE
580 * mode only.
581 */
582 u16 dcbx_cap;
583
584 struct i40e_filter_control_settings filter_settings;
585 struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */
586 struct i40e_dcbx_config tmp_cfg;
587
588/* GPIO defines used by PTP */
589#define I40E_SDP3_2 18
590#define I40E_SDP3_3 19
591#define I40E_GPIO_4 20
592#define I40E_LED2_0 26
593#define I40E_LED2_1 27
594#define I40E_LED3_0 28
595#define I40E_LED3_1 29
596#define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \
597 (1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
598#define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \
599 (1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
600#define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \
601 (0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
602#define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \
603 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
604#define I40E_GLGEN_GPIO_CTL_RESERVED BIT(2)
605#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \
606 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
607#define I40E_GLGEN_GPIO_CTL_DIR_OUT \
608 (1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
609#define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \
610 (1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
611#define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \
612 (1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
613#define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \
614 (3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
615#define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \
616 (4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
617#define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \
618 (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
619#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \
620 (1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
621#define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \
622 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
623 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
624 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
625#define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \
626 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
627 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
628 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
629#define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \
630 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
631 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
632 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
633 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
634#define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \
635 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
636 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
637 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
638 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
639#define I40E_GLGEN_GPIO_CTL_LED_INIT \
640 (I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \
641 I40E_GLGEN_GPIO_CTL_DIR_OUT | \
642 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \
643 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
644 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \
645 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN)
646#define I40E_PRTTSYN_AUX_1_INSTNT \
647 (1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
648#define I40E_PRTTSYN_AUX_0_OUT_ENABLE \
649 (1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
650#define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD (3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
651#define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \
652 (I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD)
653#define I40E_PTP_HALF_SECOND 500000000LL /* nano seconds */
654#define I40E_PTP_2_SEC_DELAY 2
655
656 struct ptp_clock *ptp_clock;
657 struct ptp_clock_info ptp_caps;
658 struct sk_buff *ptp_tx_skb;
659 unsigned long ptp_tx_start;
660 struct hwtstamp_config tstamp_config;
661 struct timespec64 ptp_prev_hw_time;
662 struct work_struct ptp_extts0_work;
663 ktime_t ptp_reset_start;
664 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
665 u32 ptp_adj_mult;
666 u32 tx_hwtstamp_timeouts;
667 u32 tx_hwtstamp_skipped;
668 u32 rx_hwtstamp_cleared;
669 u32 latch_event_flags;
670 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
671 unsigned long latch_events[4];
672 bool ptp_tx;
673 bool ptp_rx;
674 struct i40e_ptp_pins_settings *ptp_pins;
675 u16 rss_table_size; /* HW RSS table size */
676 u32 max_bw;
677 u32 min_bw;
678
679 u32 ioremap_len;
680 u32 fd_inv;
681 u16 phy_led_val;
682
683 u16 last_sw_conf_flags;
684 u16 last_sw_conf_valid_flags;
685 /* List to keep previous DDP profiles to be rolled back in the future */
686 struct list_head ddp_old_prof;
687};
688
689/**
690 * __i40e_pf_next_vsi - get next valid VSI
691 * @pf: pointer to the PF struct
692 * @idx: pointer to start position number
693 *
694 * Find and return next non-NULL VSI pointer in pf->vsi array and
695 * updates idx position. Returns NULL if no VSI is found.
696 **/
697static __always_inline struct i40e_vsi *
698__i40e_pf_next_vsi(struct i40e_pf *pf, int *idx)
699{
700 while (*idx < pf->num_alloc_vsi) {
701 if (pf->vsi[*idx])
702 return pf->vsi[*idx];
703 (*idx)++;
704 }
705 return NULL;
706}
707
708#define i40e_pf_for_each_vsi(_pf, _i, _vsi) \
709 for (_i = 0, _vsi = __i40e_pf_next_vsi(_pf, &_i); \
710 _vsi; \
711 _i++, _vsi = __i40e_pf_next_vsi(_pf, &_i))
712
713/**
714 * __i40e_pf_next_veb - get next valid VEB
715 * @pf: pointer to the PF struct
716 * @idx: pointer to start position number
717 *
718 * Find and return next non-NULL VEB pointer in pf->veb array and
719 * updates idx position. Returns NULL if no VEB is found.
720 **/
721static __always_inline struct i40e_veb *
722__i40e_pf_next_veb(struct i40e_pf *pf, int *idx)
723{
724 while (*idx < I40E_MAX_VEB) {
725 if (pf->veb[*idx])
726 return pf->veb[*idx];
727 (*idx)++;
728 }
729 return NULL;
730}
731
732#define i40e_pf_for_each_veb(_pf, _i, _veb) \
733 for (_i = 0, _veb = __i40e_pf_next_veb(_pf, &_i); \
734 _veb; \
735 _i++, _veb = __i40e_pf_next_veb(_pf, &_i))
736
737/**
738 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
739 * @macaddr: the MAC Address as the base key
740 *
741 * Simply copies the address and returns it as a u64 for hashing
742 **/
743static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
744{
745 u64 key = 0;
746
747 ether_addr_copy((u8 *)&key, macaddr);
748 return key;
749}
750
751enum i40e_filter_state {
752 I40E_FILTER_INVALID = 0, /* Invalid state */
753 I40E_FILTER_NEW, /* New, not sent to FW yet */
754 I40E_FILTER_ACTIVE, /* Added to switch by FW */
755 I40E_FILTER_FAILED, /* Rejected by FW */
756 I40E_FILTER_REMOVE, /* To be removed */
757/* There is no 'removed' state; the filter struct is freed */
758};
759struct i40e_mac_filter {
760 struct hlist_node hlist;
761 u8 macaddr[ETH_ALEN];
762#define I40E_VLAN_ANY -1
763 s16 vlan;
764 enum i40e_filter_state state;
765};
766
767/* Wrapper structure to keep track of filters while we are preparing to send
768 * firmware commands. We cannot send firmware commands while holding a
769 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
770 * a separate structure, which will track the state change and update the real
771 * filter while under lock. We can't simply hold the filters in a separate
772 * list, as this opens a window for a race condition when adding new MAC
773 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
774 */
775struct i40e_new_mac_filter {
776 struct hlist_node hlist;
777 struct i40e_mac_filter *f;
778
779 /* Track future changes to state separately */
780 enum i40e_filter_state state;
781};
782
783struct i40e_veb {
784 struct i40e_pf *pf;
785 u16 idx;
786 u16 seid;
787 u16 uplink_seid;
788 u16 stats_idx; /* index of VEB parent */
789 u8 enabled_tc;
790 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
791 u16 flags;
792 u16 bw_limit;
793 u8 bw_max_quanta;
794 bool is_abs_credits;
795 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
796 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
797 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
798 struct kobject *kobj;
799 bool stat_offsets_loaded;
800 struct i40e_eth_stats stats;
801 struct i40e_eth_stats stats_offsets;
802 struct i40e_veb_tc_stats tc_stats;
803 struct i40e_veb_tc_stats tc_stats_offsets;
804};
805
806/* struct that defines a VSI, associated with a dev */
807struct i40e_vsi {
808 struct net_device *netdev;
809 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
810 bool netdev_registered;
811 bool stat_offsets_loaded;
812
813 u32 current_netdev_flags;
814 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
815#define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
816#define I40E_VSI_FLAG_VEB_OWNER BIT(1)
817 unsigned long flags;
818
819 /* Per VSI lock to protect elements/hash (MAC filter) */
820 spinlock_t mac_filter_hash_lock;
821 /* Fixed size hash table with 2^8 buckets for MAC filters */
822 DECLARE_HASHTABLE(mac_filter_hash, 8);
823 bool has_vlan_filter;
824
825 /* VSI stats */
826 struct rtnl_link_stats64 net_stats;
827 struct rtnl_link_stats64 net_stats_offsets;
828 struct i40e_eth_stats eth_stats;
829 struct i40e_eth_stats eth_stats_offsets;
830 u64 tx_restart;
831 u64 tx_busy;
832 u64 tx_linearize;
833 u64 tx_force_wb;
834 u64 tx_stopped;
835 u64 rx_buf_failed;
836 u64 rx_page_failed;
837 u64 rx_page_reuse;
838 u64 rx_page_alloc;
839 u64 rx_page_waive;
840 u64 rx_page_busy;
841
842 /* These are containers of ring pointers, allocated at run-time */
843 struct i40e_ring **rx_rings;
844 struct i40e_ring **tx_rings;
845 struct i40e_ring **xdp_rings; /* XDP Tx rings */
846
847 u32 active_filters;
848 u32 promisc_threshold;
849
850 u16 work_limit;
851 u16 int_rate_limit; /* value in usecs */
852
853 u16 rss_table_size; /* HW RSS table size */
854 u16 rss_size; /* Allocated RSS queues */
855 u8 *rss_hkey_user; /* User configured hash keys */
856 u8 *rss_lut_user; /* User configured lookup table entries */
857
858
859 u16 max_frame;
860 u16 rx_buf_len;
861
862 struct bpf_prog *xdp_prog;
863
864 /* List of q_vectors allocated to this VSI */
865 struct i40e_q_vector **q_vectors;
866 int num_q_vectors;
867 int base_vector;
868 bool irqs_ready;
869
870 u16 seid; /* HW index of this VSI (absolute index) */
871 u16 id; /* VSI number */
872 u16 uplink_seid;
873
874 u16 base_queue; /* vsi's first queue in hw array */
875 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
876 u16 req_queue_pairs; /* User requested queue pairs */
877 u16 num_queue_pairs; /* Used tx and rx pairs */
878 u16 num_tx_desc;
879 u16 num_rx_desc;
880 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
881 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
882
883 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
884 struct i40e_tc_configuration tc_config;
885 struct i40e_aqc_vsi_properties_data info;
886
887 /* VSI BW limit (absolute across all TCs) */
888 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
889 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
890
891 /* Relative TC credits across VSIs */
892 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
893 /* TC BW limit credits within VSI */
894 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
895 /* TC BW limit max quanta within VSI */
896 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
897
898 struct i40e_pf *back; /* Backreference to associated PF */
899 u16 idx; /* index in pf->vsi[] */
900 u16 veb_idx; /* index of VEB parent */
901 struct kobject *kobj; /* sysfs object */
902 bool current_isup; /* Sync 'link up' logging */
903 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
904
905 /* channel specific fields */
906 u16 cnt_q_avail; /* num of queues available for channel usage */
907 u16 orig_rss_size;
908 u16 current_rss_size;
909 bool reconfig_rss;
910
911 u16 next_base_queue; /* next queue to be used for channel setup */
912
913 struct list_head ch_list;
914 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
915
916 /* macvlan fields */
917#define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */
918#define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */
919 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS);
920 struct list_head macvlan_list;
921 int macvlan_cnt;
922
923 void *priv; /* client driver data reference. */
924
925 /* VSI specific handlers */
926 irqreturn_t (*irq_handler)(int irq, void *data);
927
928 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */
929} ____cacheline_internodealigned_in_smp;
930
931struct i40e_netdev_priv {
932 struct i40e_vsi *vsi;
933};
934
935extern struct ida i40e_client_ida;
936
937/* struct that defines an interrupt vector */
938struct i40e_q_vector {
939 struct i40e_vsi *vsi;
940
941 u16 v_idx; /* index in the vsi->q_vector array. */
942 u16 reg_idx; /* register index of the interrupt */
943
944 struct napi_struct napi;
945
946 struct i40e_ring_container rx;
947 struct i40e_ring_container tx;
948
949 u8 itr_countdown; /* when 0 should adjust adaptive ITR */
950 u8 num_ringpairs; /* total number of ring pairs in vector */
951
952 cpumask_t affinity_mask;
953 struct irq_affinity_notify affinity_notify;
954
955 struct rcu_head rcu; /* to avoid race with update stats on free */
956 char name[I40E_INT_NAME_STR_LEN];
957 bool arm_wb_state;
958 bool in_busy_poll;
959 int irq_num; /* IRQ assigned to this q_vector */
960} ____cacheline_internodealigned_in_smp;
961
962/* lan device */
963struct i40e_device {
964 struct list_head list;
965 struct i40e_pf *pf;
966};
967
968/**
969 * i40e_info_nvm_ver - format the NVM version string
970 * @hw: ptr to the hardware info
971 * @buf: string buffer to store
972 * @len: buffer size
973 *
974 * Formats NVM version string as:
975 * <gen>.<snap>.<release> when eetrackid == I40E_OEM_EETRACK_ID
976 * <nvm_major>.<nvm_minor> otherwise
977 **/
978static inline void i40e_info_nvm_ver(struct i40e_hw *hw, char *buf, size_t len)
979{
980 struct i40e_nvm_info *nvm = &hw->nvm;
981
982 if (nvm->eetrack == I40E_OEM_EETRACK_ID) {
983 u32 full_ver = nvm->oem_ver;
984 u8 gen, snap;
985 u16 release;
986
987 gen = FIELD_GET(I40E_OEM_GEN_MASK, full_ver);
988 snap = FIELD_GET(I40E_OEM_SNAP_MASK, full_ver);
989 release = FIELD_GET(I40E_OEM_RELEASE_MASK, full_ver);
990 snprintf(buf, len, "%x.%x.%x", gen, snap, release);
991 } else {
992 u8 major, minor;
993
994 major = FIELD_GET(I40E_NVM_VERSION_HI_MASK, nvm->version);
995 minor = FIELD_GET(I40E_NVM_VERSION_LO_MASK, nvm->version);
996 snprintf(buf, len, "%x.%02x", major, minor);
997 }
998}
999
1000/**
1001 * i40e_info_eetrack - format the EETrackID string
1002 * @hw: ptr to the hardware info
1003 * @buf: string buffer to store
1004 * @len: buffer size
1005 *
1006 * Returns hexadecimally formated EETrackID if it is
1007 * different from I40E_OEM_EETRACK_ID or empty string.
1008 **/
1009static inline void i40e_info_eetrack(struct i40e_hw *hw, char *buf, size_t len)
1010{
1011 struct i40e_nvm_info *nvm = &hw->nvm;
1012
1013 buf[0] = '\0';
1014 if (nvm->eetrack != I40E_OEM_EETRACK_ID)
1015 snprintf(buf, len, "0x%08x", nvm->eetrack);
1016}
1017
1018/**
1019 * i40e_info_civd_ver - format the NVM version strings
1020 * @hw: ptr to the hardware info
1021 * @buf: string buffer to store
1022 * @len: buffer size
1023 *
1024 * Returns formated combo image version if adapter's EETrackID is
1025 * different from I40E_OEM_EETRACK_ID or empty string.
1026 **/
1027static inline void i40e_info_civd_ver(struct i40e_hw *hw, char *buf, size_t len)
1028{
1029 struct i40e_nvm_info *nvm = &hw->nvm;
1030
1031 buf[0] = '\0';
1032 if (nvm->eetrack != I40E_OEM_EETRACK_ID) {
1033 u32 full_ver = nvm->oem_ver;
1034 u8 major, minor;
1035 u16 build;
1036
1037 major = FIELD_GET(I40E_OEM_VER_MASK, full_ver);
1038 build = FIELD_GET(I40E_OEM_VER_BUILD_MASK, full_ver);
1039 minor = FIELD_GET(I40E_OEM_VER_PATCH_MASK, full_ver);
1040 snprintf(buf, len, "%d.%d.%d", major, build, minor);
1041 }
1042}
1043
1044/**
1045 * i40e_nvm_version_str - format the NVM version strings
1046 * @hw: ptr to the hardware info
1047 * @buf: string buffer to store
1048 * @len: buffer size
1049 **/
1050static inline char *i40e_nvm_version_str(struct i40e_hw *hw, char *buf,
1051 size_t len)
1052{
1053 char ver[16] = " ";
1054
1055 /* Get NVM version */
1056 i40e_info_nvm_ver(hw, buf, len);
1057
1058 /* Append EETrackID if provided */
1059 i40e_info_eetrack(hw, &ver[1], sizeof(ver) - 1);
1060 if (strlen(ver) > 1)
1061 strlcat(buf, ver, len);
1062
1063 /* Append combo image version if provided */
1064 i40e_info_civd_ver(hw, &ver[1], sizeof(ver) - 1);
1065 if (strlen(ver) > 1)
1066 strlcat(buf, ver, len);
1067
1068 return buf;
1069}
1070
1071/**
1072 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
1073 * @netdev: the corresponding netdev
1074 *
1075 * Return the PF struct for the given netdev
1076 **/
1077static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
1078{
1079 struct i40e_netdev_priv *np = netdev_priv(netdev);
1080 struct i40e_vsi *vsi = np->vsi;
1081
1082 return vsi->back;
1083}
1084
1085static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
1086 irqreturn_t (*irq_handler)(int, void *))
1087{
1088 vsi->irq_handler = irq_handler;
1089}
1090
1091/**
1092 * i40e_get_fd_cnt_all - get the total FD filter space available
1093 * @pf: pointer to the PF struct
1094 **/
1095static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
1096{
1097 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
1098}
1099
1100/**
1101 * i40e_read_fd_input_set - reads value of flow director input set register
1102 * @pf: pointer to the PF struct
1103 * @addr: register addr
1104 *
1105 * This function reads value of flow director input set register
1106 * specified by 'addr' (which is specific to flow-type)
1107 **/
1108static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
1109{
1110 u64 val;
1111
1112 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
1113 val <<= 32;
1114 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
1115
1116 return val;
1117}
1118
1119/**
1120 * i40e_write_fd_input_set - writes value into flow director input set register
1121 * @pf: pointer to the PF struct
1122 * @addr: register addr
1123 * @val: value to be written
1124 *
1125 * This function writes specified value to the register specified by 'addr'.
1126 * This register is input set register based on flow-type.
1127 **/
1128static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
1129 u16 addr, u64 val)
1130{
1131 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
1132 (u32)(val >> 32));
1133 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
1134 (u32)(val & 0xFFFFFFFFULL));
1135}
1136
1137/**
1138 * i40e_get_pf_count - get PCI PF count.
1139 * @hw: pointer to a hw.
1140 *
1141 * Reports the function number of the highest PCI physical
1142 * function plus 1 as it is loaded from the NVM.
1143 *
1144 * Return: PCI PF count.
1145 **/
1146static inline u32 i40e_get_pf_count(struct i40e_hw *hw)
1147{
1148 return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK,
1149 rd32(hw, I40E_GLGEN_PCIFCNCNT));
1150}
1151
1152/* needed by i40e_ethtool.c */
1153int i40e_up(struct i40e_vsi *vsi);
1154void i40e_down(struct i40e_vsi *vsi);
1155extern const char i40e_driver_name[];
1156void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
1157void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
1158int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1159int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1160void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
1161 u16 rss_table_size, u16 rss_size);
1162struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
1163/**
1164 * i40e_find_vsi_by_type - Find and return Flow Director VSI
1165 * @pf: PF to search for VSI
1166 * @type: Value indicating type of VSI we are looking for
1167 **/
1168static inline struct i40e_vsi *
1169i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
1170{
1171 struct i40e_vsi *vsi;
1172 int i;
1173
1174 i40e_pf_for_each_vsi(pf, i, vsi)
1175 if (vsi->type == type)
1176 return vsi;
1177
1178 return NULL;
1179}
1180void i40e_update_stats(struct i40e_vsi *vsi);
1181void i40e_update_veb_stats(struct i40e_veb *veb);
1182void i40e_update_eth_stats(struct i40e_vsi *vsi);
1183struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
1184int i40e_fetch_switch_configuration(struct i40e_pf *pf,
1185 bool printconfig);
1186
1187int i40e_add_del_fdir(struct i40e_vsi *vsi,
1188 struct i40e_fdir_filter *input, bool add);
1189void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
1190u32 i40e_get_current_fd_count(struct i40e_pf *pf);
1191u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1192u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
1193u32 i40e_get_global_fd_count(struct i40e_pf *pf);
1194bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
1195void i40e_set_ethtool_ops(struct net_device *netdev);
1196struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1197 const u8 *macaddr, s16 vlan);
1198void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1199void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1200int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1201struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1202 u16 uplink, u32 param1);
1203int i40e_vsi_release(struct i40e_vsi *vsi);
1204void i40e_service_event_schedule(struct i40e_pf *pf);
1205void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1206 u8 *msg, u16 len);
1207
1208int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
1209 bool enable);
1210int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
1211int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1212void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1213void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
1214int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1215int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1216struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1217 u16 downlink_seid, u8 enabled_tc);
1218void i40e_veb_release(struct i40e_veb *veb);
1219
1220int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1221int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1222void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1223void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1224void i40e_pf_reset_stats(struct i40e_pf *pf);
1225#ifdef CONFIG_DEBUG_FS
1226void i40e_dbg_pf_init(struct i40e_pf *pf);
1227void i40e_dbg_pf_exit(struct i40e_pf *pf);
1228void i40e_dbg_init(void);
1229void i40e_dbg_exit(void);
1230#else
1231static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
1232static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
1233static inline void i40e_dbg_init(void) {}
1234static inline void i40e_dbg_exit(void) {}
1235#endif /* CONFIG_DEBUG_FS*/
1236/* needed by client drivers */
1237int i40e_lan_add_device(struct i40e_pf *pf);
1238int i40e_lan_del_device(struct i40e_pf *pf);
1239void i40e_client_subtask(struct i40e_pf *pf);
1240void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1241void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1242void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1243void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1244void i40e_client_update_msix_info(struct i40e_pf *pf);
1245int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1246/**
1247 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1248 * @vsi: pointer to a vsi
1249 * @vector: enable a particular Hw Interrupt vector, without base_vector
1250 **/
1251static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1252{
1253 struct i40e_pf *pf = vsi->back;
1254 struct i40e_hw *hw = &pf->hw;
1255 u32 val;
1256
1257 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1258 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1259 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1260 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1261 /* skip the flush */
1262}
1263
1264void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1265void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1266int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1267int i40e_open(struct net_device *netdev);
1268int i40e_close(struct net_device *netdev);
1269int i40e_vsi_open(struct i40e_vsi *vsi);
1270void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1271int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1272int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1273void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1274void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1275struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1276 const u8 *macaddr);
1277int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1278bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1279int i40e_count_filters(struct i40e_vsi *vsi);
1280struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1281void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1282static inline bool i40e_is_sw_dcb(struct i40e_pf *pf)
1283{
1284 return test_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags);
1285}
1286
1287#ifdef CONFIG_I40E_DCB
1288void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1289 struct i40e_dcbx_config *old_cfg,
1290 struct i40e_dcbx_config *new_cfg);
1291void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1292void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1293bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1294 struct i40e_dcbx_config *old_cfg,
1295 struct i40e_dcbx_config *new_cfg);
1296int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg);
1297int i40e_dcb_sw_default_config(struct i40e_pf *pf);
1298#endif /* CONFIG_I40E_DCB */
1299void i40e_ptp_rx_hang(struct i40e_pf *pf);
1300void i40e_ptp_tx_hang(struct i40e_pf *pf);
1301void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1302void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1303void i40e_ptp_set_increment(struct i40e_pf *pf);
1304int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1305int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1306void i40e_ptp_save_hw_time(struct i40e_pf *pf);
1307void i40e_ptp_restore_hw_time(struct i40e_pf *pf);
1308void i40e_ptp_init(struct i40e_pf *pf);
1309void i40e_ptp_stop(struct i40e_pf *pf);
1310int i40e_ptp_alloc_pins(struct i40e_pf *pf);
1311int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset);
1312int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1313int i40e_get_partition_bw_setting(struct i40e_pf *pf);
1314int i40e_set_partition_bw_setting(struct i40e_pf *pf);
1315int i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1316void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1317
1318void i40e_set_fec_in_flags(u8 fec_cfg, unsigned long *flags);
1319
1320static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1321{
1322 return !!READ_ONCE(vsi->xdp_prog);
1323}
1324
1325int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1326int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1327int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1328 struct i40e_cloud_filter *filter,
1329 bool add);
1330int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1331 struct i40e_cloud_filter *filter,
1332 bool add);
1333
1334/**
1335 * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF
1336 * @pf: pointer to a pf.
1337 *
1338 * Check and return state of flag I40E_FLAG_TC_MQPRIO.
1339 *
1340 * Return: true/false if I40E_FLAG_TC_MQPRIO is set or not
1341 **/
1342static inline bool i40e_is_tc_mqprio_enabled(struct i40e_pf *pf)
1343{
1344 return test_bit(I40E_FLAG_TC_MQPRIO_ENA, pf->flags);
1345}
1346
1347/**
1348 * i40e_hw_to_pf - get pf pointer from the hardware structure
1349 * @hw: pointer to the device HW structure
1350 **/
1351static inline struct i40e_pf *i40e_hw_to_pf(struct i40e_hw *hw)
1352{
1353 return container_of(hw, struct i40e_pf, hw);
1354}
1355
1356struct device *i40e_hw_to_dev(struct i40e_hw *hw);
1357
1358/**
1359 * i40e_pf_get_vsi_by_seid - find VSI by SEID
1360 * @pf: pointer to a PF
1361 * @seid: SEID of the VSI
1362 **/
1363static inline struct i40e_vsi *
1364i40e_pf_get_vsi_by_seid(struct i40e_pf *pf, u16 seid)
1365{
1366 struct i40e_vsi *vsi;
1367 int i;
1368
1369 i40e_pf_for_each_vsi(pf, i, vsi)
1370 if (vsi->seid == seid)
1371 return vsi;
1372
1373 return NULL;
1374}
1375
1376/**
1377 * i40e_pf_get_veb_by_seid - find VEB by SEID
1378 * @pf: pointer to a PF
1379 * @seid: SEID of the VSI
1380 **/
1381static inline struct i40e_veb *
1382i40e_pf_get_veb_by_seid(struct i40e_pf *pf, u16 seid)
1383{
1384 struct i40e_veb *veb;
1385 int i;
1386
1387 i40e_pf_for_each_veb(pf, i, veb)
1388 if (veb->seid == seid)
1389 return veb;
1390
1391 return NULL;
1392}
1393
1394#endif /* _I40E_H_ */
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4#ifndef _I40E_H_
5#define _I40E_H_
6
7#include <net/tcp.h>
8#include <net/udp.h>
9#include <linux/types.h>
10#include <linux/errno.h>
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/aer.h>
14#include <linux/netdevice.h>
15#include <linux/ioport.h>
16#include <linux/iommu.h>
17#include <linux/slab.h>
18#include <linux/list.h>
19#include <linux/hashtable.h>
20#include <linux/string.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/sctp.h>
24#include <linux/pkt_sched.h>
25#include <linux/ipv6.h>
26#include <net/checksum.h>
27#include <net/ip6_checksum.h>
28#include <linux/ethtool.h>
29#include <linux/if_vlan.h>
30#include <linux/if_macvlan.h>
31#include <linux/if_bridge.h>
32#include <linux/clocksource.h>
33#include <linux/net_tstamp.h>
34#include <linux/ptp_clock_kernel.h>
35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
37#include <net/tc_act/tc_mirred.h>
38#include <net/xdp_sock.h>
39#include "i40e_type.h"
40#include "i40e_prototype.h"
41#include <linux/net/intel/i40e_client.h>
42#include <linux/avf/virtchnl.h>
43#include "i40e_virtchnl_pf.h"
44#include "i40e_txrx.h"
45#include "i40e_dcb.h"
46
47/* Useful i40e defaults */
48#define I40E_MAX_VEB 16
49
50#define I40E_MAX_NUM_DESCRIPTORS 4096
51#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
52#define I40E_DEFAULT_NUM_DESCRIPTORS 512
53#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
54#define I40E_MIN_NUM_DESCRIPTORS 64
55#define I40E_MIN_MSIX 2
56#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
57#define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
58/* max 16 qps */
59#define i40e_default_queues_per_vmdq(pf) \
60 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
61#define I40E_DEFAULT_QUEUES_PER_VF 4
62#define I40E_MAX_VF_QUEUES 16
63#define i40e_pf_get_max_q_per_tc(pf) \
64 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
65#define I40E_FDIR_RING_COUNT 32
66#define I40E_MAX_AQ_BUF_SIZE 4096
67#define I40E_AQ_LEN 256
68#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
69#define I40E_MAX_USER_PRIORITY 8
70#define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
71#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
72#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
73
74#define I40E_NVM_VERSION_LO_SHIFT 0
75#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
76#define I40E_NVM_VERSION_HI_SHIFT 12
77#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
78#define I40E_OEM_VER_BUILD_MASK 0xffff
79#define I40E_OEM_VER_PATCH_MASK 0xff
80#define I40E_OEM_VER_BUILD_SHIFT 8
81#define I40E_OEM_VER_SHIFT 24
82#define I40E_PHY_DEBUG_ALL \
83 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
84 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
85
86#define I40E_OEM_EETRACK_ID 0xffffffff
87#define I40E_OEM_GEN_SHIFT 24
88#define I40E_OEM_SNAP_MASK 0x00ff0000
89#define I40E_OEM_SNAP_SHIFT 16
90#define I40E_OEM_RELEASE_MASK 0x0000ffff
91
92#define I40E_RX_DESC(R, i) \
93 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))
94#define I40E_TX_DESC(R, i) \
95 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
96#define I40E_TX_CTXTDESC(R, i) \
97 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
98#define I40E_TX_FDIRDESC(R, i) \
99 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
100
101/* BW rate limiting */
102#define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
103#define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
104#define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */
105
106/* driver state flags */
107enum i40e_state_t {
108 __I40E_TESTING,
109 __I40E_CONFIG_BUSY,
110 __I40E_CONFIG_DONE,
111 __I40E_DOWN,
112 __I40E_SERVICE_SCHED,
113 __I40E_ADMINQ_EVENT_PENDING,
114 __I40E_MDD_EVENT_PENDING,
115 __I40E_VFLR_EVENT_PENDING,
116 __I40E_RESET_RECOVERY_PENDING,
117 __I40E_TIMEOUT_RECOVERY_PENDING,
118 __I40E_MISC_IRQ_REQUESTED,
119 __I40E_RESET_INTR_RECEIVED,
120 __I40E_REINIT_REQUESTED,
121 __I40E_PF_RESET_REQUESTED,
122 __I40E_CORE_RESET_REQUESTED,
123 __I40E_GLOBAL_RESET_REQUESTED,
124 __I40E_EMP_RESET_INTR_RECEIVED,
125 __I40E_SUSPENDED,
126 __I40E_PTP_TX_IN_PROGRESS,
127 __I40E_BAD_EEPROM,
128 __I40E_DOWN_REQUESTED,
129 __I40E_FD_FLUSH_REQUESTED,
130 __I40E_FD_ATR_AUTO_DISABLED,
131 __I40E_FD_SB_AUTO_DISABLED,
132 __I40E_RESET_FAILED,
133 __I40E_PORT_SUSPENDED,
134 __I40E_VF_DISABLE,
135 __I40E_MACVLAN_SYNC_PENDING,
136 __I40E_UDP_FILTER_SYNC_PENDING,
137 __I40E_TEMP_LINK_POLLING,
138 __I40E_CLIENT_SERVICE_REQUESTED,
139 __I40E_CLIENT_L2_CHANGE,
140 __I40E_CLIENT_RESET,
141 __I40E_VIRTCHNL_OP_PENDING,
142 __I40E_RECOVERY_MODE,
143 /* This must be last as it determines the size of the BITMAP */
144 __I40E_STATE_SIZE__,
145};
146
147#define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
148
149/* VSI state flags */
150enum i40e_vsi_state_t {
151 __I40E_VSI_DOWN,
152 __I40E_VSI_NEEDS_RESTART,
153 __I40E_VSI_SYNCING_FILTERS,
154 __I40E_VSI_OVERFLOW_PROMISC,
155 __I40E_VSI_REINIT_REQUESTED,
156 __I40E_VSI_DOWN_REQUESTED,
157 /* This must be last as it determines the size of the BITMAP */
158 __I40E_VSI_STATE_SIZE__,
159};
160
161enum i40e_interrupt_policy {
162 I40E_INTERRUPT_BEST_CASE,
163 I40E_INTERRUPT_MEDIUM,
164 I40E_INTERRUPT_LOWEST
165};
166
167struct i40e_lump_tracking {
168 u16 num_entries;
169 u16 search_hint;
170 u16 list[0];
171#define I40E_PILE_VALID_BIT 0x8000
172#define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
173};
174
175#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
176#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
177#define I40E_FDIR_BUFFER_FULL_MARGIN 10
178#define I40E_FDIR_BUFFER_HEAD_ROOM 32
179#define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
180
181#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
182#define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
183#define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
184
185enum i40e_fd_stat_idx {
186 I40E_FD_STAT_ATR,
187 I40E_FD_STAT_SB,
188 I40E_FD_STAT_ATR_TUNNEL,
189 I40E_FD_STAT_PF_COUNT
190};
191#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
192#define I40E_FD_ATR_STAT_IDX(pf_id) \
193 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
194#define I40E_FD_SB_STAT_IDX(pf_id) \
195 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
196#define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
197 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
198
199/* The following structure contains the data parsed from the user-defined
200 * field of the ethtool_rx_flow_spec structure.
201 */
202struct i40e_rx_flow_userdef {
203 bool flex_filter;
204 u16 flex_word;
205 u16 flex_offset;
206};
207
208struct i40e_fdir_filter {
209 struct hlist_node fdir_node;
210 /* filter ipnut set */
211 u8 flow_type;
212 u8 ip4_proto;
213 /* TX packet view of src and dst */
214 __be32 dst_ip;
215 __be32 src_ip;
216 __be16 src_port;
217 __be16 dst_port;
218 __be32 sctp_v_tag;
219
220 /* Flexible data to match within the packet payload */
221 __be16 flex_word;
222 u16 flex_offset;
223 bool flex_filter;
224
225 /* filter control */
226 u16 q_index;
227 u8 flex_off;
228 u8 pctype;
229 u16 dest_vsi;
230 u8 dest_ctl;
231 u8 fd_status;
232 u16 cnt_index;
233 u32 fd_id;
234};
235
236#define I40E_CLOUD_FIELD_OMAC BIT(0)
237#define I40E_CLOUD_FIELD_IMAC BIT(1)
238#define I40E_CLOUD_FIELD_IVLAN BIT(2)
239#define I40E_CLOUD_FIELD_TEN_ID BIT(3)
240#define I40E_CLOUD_FIELD_IIP BIT(4)
241
242#define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
243#define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
244#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
245 I40E_CLOUD_FIELD_IVLAN)
246#define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
247 I40E_CLOUD_FIELD_TEN_ID)
248#define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
249 I40E_CLOUD_FIELD_IMAC | \
250 I40E_CLOUD_FIELD_TEN_ID)
251#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
252 I40E_CLOUD_FIELD_IVLAN | \
253 I40E_CLOUD_FIELD_TEN_ID)
254#define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
255
256struct i40e_cloud_filter {
257 struct hlist_node cloud_node;
258 unsigned long cookie;
259 /* cloud filter input set follows */
260 u8 dst_mac[ETH_ALEN];
261 u8 src_mac[ETH_ALEN];
262 __be16 vlan_id;
263 u16 seid; /* filter control */
264 __be16 dst_port;
265 __be16 src_port;
266 u32 tenant_id;
267 union {
268 struct {
269 struct in_addr dst_ip;
270 struct in_addr src_ip;
271 } v4;
272 struct {
273 struct in6_addr dst_ip6;
274 struct in6_addr src_ip6;
275 } v6;
276 } ip;
277#define dst_ipv6 ip.v6.dst_ip6.s6_addr32
278#define src_ipv6 ip.v6.src_ip6.s6_addr32
279#define dst_ipv4 ip.v4.dst_ip.s_addr
280#define src_ipv4 ip.v4.src_ip.s_addr
281 u16 n_proto; /* Ethernet Protocol */
282 u8 ip_proto; /* IPPROTO value */
283 u8 flags;
284#define I40E_CLOUD_TNL_TYPE_NONE 0xff
285 u8 tunnel_type;
286};
287
288/* DCB per TC information data structure */
289struct i40e_tc_info {
290 u16 qoffset; /* Queue offset from base queue */
291 u16 qcount; /* Total Queues */
292 u8 netdev_tc; /* Netdev TC index if netdev associated */
293};
294
295/* TC configuration data structure */
296struct i40e_tc_configuration {
297 u8 numtc; /* Total number of enabled TCs */
298 u8 enabled_tc; /* TC map */
299 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
300};
301
302#define I40E_UDP_PORT_INDEX_UNUSED 255
303struct i40e_udp_port_config {
304 /* AdminQ command interface expects port number in Host byte order */
305 u16 port;
306 u8 type;
307 u8 filter_index;
308};
309
310#define I40_DDP_FLASH_REGION 100
311#define I40E_PROFILE_INFO_SIZE 48
312#define I40E_MAX_PROFILE_NUM 16
313#define I40E_PROFILE_LIST_SIZE \
314 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4)
315#define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/"
316#define I40E_DDP_PROFILE_NAME_MAX 64
317
318int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size,
319 bool is_add);
320int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash);
321
322struct i40e_ddp_profile_list {
323 u32 p_count;
324 struct i40e_profile_info p_info[];
325};
326
327struct i40e_ddp_old_profile_list {
328 struct list_head list;
329 size_t old_ddp_size;
330 u8 old_ddp_buf[];
331};
332
333/* macros related to FLX_PIT */
334#define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
335 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
336 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
337#define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
338 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
339 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
340#define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
341 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
342 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
343#define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
344 I40E_FLEX_SET_FSIZE(fsize) | \
345 I40E_FLEX_SET_SRC_WORD(src))
346
347
348#define I40E_MAX_FLEX_SRC_OFFSET 0x1F
349
350/* macros related to GLQF_ORT */
351#define I40E_ORT_SET_IDX(idx) (((idx) << \
352 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
353 I40E_GLQF_ORT_PIT_INDX_MASK)
354
355#define I40E_ORT_SET_COUNT(count) (((count) << \
356 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
357 I40E_GLQF_ORT_FIELD_CNT_MASK)
358
359#define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
360 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
361 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
362
363#define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
364 I40E_ORT_SET_COUNT(count) | \
365 I40E_ORT_SET_PAYLOAD(payload))
366
367#define I40E_L3_GLQF_ORT_IDX 34
368#define I40E_L4_GLQF_ORT_IDX 35
369
370/* Flex PIT register index */
371#define I40E_FLEX_PIT_IDX_START_L3 3
372#define I40E_FLEX_PIT_IDX_START_L4 6
373
374#define I40E_FLEX_PIT_TABLE_SIZE 3
375
376#define I40E_FLEX_DEST_UNUSED 63
377
378#define I40E_FLEX_INDEX_ENTRIES 8
379
380/* Flex MASK to disable all flexible entries */
381#define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
382 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
383 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
384 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
385
386struct i40e_flex_pit {
387 struct list_head list;
388 u16 src_offset;
389 u8 pit_index;
390};
391
392struct i40e_fwd_adapter {
393 struct net_device *netdev;
394 int bit_no;
395};
396
397struct i40e_channel {
398 struct list_head list;
399 bool initialized;
400 u8 type;
401 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
402 u16 stat_counter_idx;
403 u16 base_queue;
404 u16 num_queue_pairs; /* Requested by user */
405 u16 seid;
406
407 u8 enabled_tc;
408 struct i40e_aqc_vsi_properties_data info;
409
410 u64 max_tx_rate;
411 struct i40e_fwd_adapter *fwd;
412
413 /* track this channel belongs to which VSI */
414 struct i40e_vsi *parent_vsi;
415};
416
417static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)
418{
419 return !!ch->fwd;
420}
421
422static inline u8 *i40e_channel_mac(struct i40e_channel *ch)
423{
424 if (i40e_is_channel_macvlan(ch))
425 return ch->fwd->netdev->dev_addr;
426 else
427 return NULL;
428}
429
430/* struct that defines the Ethernet device */
431struct i40e_pf {
432 struct pci_dev *pdev;
433 struct i40e_hw hw;
434 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
435 struct msix_entry *msix_entries;
436 bool fc_autoneg_status;
437
438 u16 eeprom_version;
439 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
440 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
441 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
442 u16 num_req_vfs; /* num VFs requested for this PF */
443 u16 num_vf_qps; /* num queue pairs per VF */
444 u16 num_lan_qps; /* num lan queues this PF has set up */
445 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
446 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
447 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
448 int iwarp_base_vector;
449 int queues_left; /* queues left unclaimed */
450 u16 alloc_rss_size; /* allocated RSS queues */
451 u16 rss_size_max; /* HW defined max RSS queues */
452 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
453 u16 num_alloc_vsi; /* num VSIs this driver supports */
454 u8 atr_sample_rate;
455 bool wol_en;
456
457 struct hlist_head fdir_filter_list;
458 u16 fdir_pf_active_filters;
459 unsigned long fd_flush_timestamp;
460 u32 fd_flush_cnt;
461 u32 fd_add_err;
462 u32 fd_atr_cnt;
463
464 /* Book-keeping of side-band filter count per flow-type.
465 * This is used to detect and handle input set changes for
466 * respective flow-type.
467 */
468 u16 fd_tcp4_filter_cnt;
469 u16 fd_udp4_filter_cnt;
470 u16 fd_sctp4_filter_cnt;
471 u16 fd_ip4_filter_cnt;
472
473 /* Flexible filter table values that need to be programmed into
474 * hardware, which expects L3 and L4 to be programmed separately. We
475 * need to ensure that the values are in ascended order and don't have
476 * duplicates, so we track each L3 and L4 values in separate lists.
477 */
478 struct list_head l3_flex_pit_list;
479 struct list_head l4_flex_pit_list;
480
481 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
482 u16 pending_udp_bitmap;
483
484 struct hlist_head cloud_filter_list;
485 u16 num_cloud_filters;
486
487 enum i40e_interrupt_policy int_policy;
488 u16 rx_itr_default;
489 u16 tx_itr_default;
490 u32 msg_enable;
491 char int_name[I40E_INT_NAME_STR_LEN];
492 u16 adminq_work_limit; /* num of admin receive queue desc to process */
493 unsigned long service_timer_period;
494 unsigned long service_timer_previous;
495 struct timer_list service_timer;
496 struct work_struct service_task;
497
498 u32 hw_features;
499#define I40E_HW_RSS_AQ_CAPABLE BIT(0)
500#define I40E_HW_128_QP_RSS_CAPABLE BIT(1)
501#define I40E_HW_ATR_EVICT_CAPABLE BIT(2)
502#define I40E_HW_WB_ON_ITR_CAPABLE BIT(3)
503#define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4)
504#define I40E_HW_NO_PCI_LINK_CHECK BIT(5)
505#define I40E_HW_100M_SGMII_CAPABLE BIT(6)
506#define I40E_HW_NO_DCB_SUPPORT BIT(7)
507#define I40E_HW_USE_SET_LLDP_MIB BIT(8)
508#define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9)
509#define I40E_HW_PTP_L4_CAPABLE BIT(10)
510#define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11)
511#define I40E_HW_HAVE_CRT_RETIMER BIT(13)
512#define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14)
513#define I40E_HW_PHY_CONTROLS_LEDS BIT(15)
514#define I40E_HW_STOP_FW_LLDP BIT(16)
515#define I40E_HW_PORT_ID_VALID BIT(17)
516#define I40E_HW_RESTART_AUTONEG BIT(18)
517
518 u32 flags;
519#define I40E_FLAG_RX_CSUM_ENABLED BIT(0)
520#define I40E_FLAG_MSI_ENABLED BIT(1)
521#define I40E_FLAG_MSIX_ENABLED BIT(2)
522#define I40E_FLAG_RSS_ENABLED BIT(3)
523#define I40E_FLAG_VMDQ_ENABLED BIT(4)
524#define I40E_FLAG_SRIOV_ENABLED BIT(5)
525#define I40E_FLAG_DCB_CAPABLE BIT(6)
526#define I40E_FLAG_DCB_ENABLED BIT(7)
527#define I40E_FLAG_FD_SB_ENABLED BIT(8)
528#define I40E_FLAG_FD_ATR_ENABLED BIT(9)
529#define I40E_FLAG_MFP_ENABLED BIT(10)
530#define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11)
531#define I40E_FLAG_VEB_MODE_ENABLED BIT(12)
532#define I40E_FLAG_VEB_STATS_ENABLED BIT(13)
533#define I40E_FLAG_LINK_POLLING_ENABLED BIT(14)
534#define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15)
535#define I40E_FLAG_LEGACY_RX BIT(16)
536#define I40E_FLAG_PTP BIT(17)
537#define I40E_FLAG_IWARP_ENABLED BIT(18)
538#define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19)
539#define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20)
540#define I40E_FLAG_TC_MQPRIO BIT(21)
541#define I40E_FLAG_FD_SB_INACTIVE BIT(22)
542#define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23)
543#define I40E_FLAG_DISABLE_FW_LLDP BIT(24)
544#define I40E_FLAG_RS_FEC BIT(25)
545#define I40E_FLAG_BASE_R_FEC BIT(26)
546/* TOTAL_PORT_SHUTDOWN
547 * Allows to physically disable the link on the NIC's port.
548 * If enabled, (after link down request from the OS)
549 * no link, traffic or led activity is possible on that port.
550 *
551 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED is set, the
552 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED must be explicitly forced to true
553 * and cannot be disabled by system admin at that time.
554 * The functionalities are exclusive in terms of configuration, but they also
555 * have similar behavior (allowing to disable physical link of the port),
556 * with following differences:
557 * - LINK_DOWN_ON_CLOSE_ENABLED is configurable at host OS run-time and is
558 * supported by whole family of 7xx Intel Ethernet Controllers
559 * - TOTAL_PORT_SHUTDOWN may be enabled only before OS loads (in BIOS)
560 * only if motherboard's BIOS and NIC's FW has support of it
561 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought down
562 * by sending phy_type=0 to NIC's FW
563 * - when TOTAL_PORT_SHUTDOWN is used, phy_type is not altered, instead
564 * the link is being brought down by clearing bit (I40E_AQ_PHY_ENABLE_LINK)
565 * in abilities field of i40e_aq_set_phy_config structure
566 */
567#define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED BIT(27)
568
569 struct i40e_client_instance *cinst;
570 bool stat_offsets_loaded;
571 struct i40e_hw_port_stats stats;
572 struct i40e_hw_port_stats stats_offsets;
573 u32 tx_timeout_count;
574 u32 tx_timeout_recovery_level;
575 unsigned long tx_timeout_last_recovery;
576 u32 tx_sluggish_count;
577 u32 hw_csum_rx_error;
578 u32 led_status;
579 u16 corer_count; /* Core reset count */
580 u16 globr_count; /* Global reset count */
581 u16 empr_count; /* EMP reset count */
582 u16 pfr_count; /* PF reset count */
583 u16 sw_int_count; /* SW interrupt count */
584
585 struct mutex switch_mutex;
586 u16 lan_vsi; /* our default LAN VSI */
587 u16 lan_veb; /* initial relay, if exists */
588#define I40E_NO_VEB 0xffff
589#define I40E_NO_VSI 0xffff
590 u16 next_vsi; /* Next unallocated VSI - 0-based! */
591 struct i40e_vsi **vsi;
592 struct i40e_veb *veb[I40E_MAX_VEB];
593
594 struct i40e_lump_tracking *qp_pile;
595 struct i40e_lump_tracking *irq_pile;
596
597 /* switch config info */
598 u16 pf_seid;
599 u16 main_vsi_seid;
600 u16 mac_seid;
601 struct kobject *switch_kobj;
602#ifdef CONFIG_DEBUG_FS
603 struct dentry *i40e_dbg_pf;
604#endif /* CONFIG_DEBUG_FS */
605 bool cur_promisc;
606
607 u16 instance; /* A unique number per i40e_pf instance in the system */
608
609 /* sr-iov config info */
610 struct i40e_vf *vf;
611 int num_alloc_vfs; /* actual number of VFs allocated */
612 u32 vf_aq_requests;
613 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
614
615 /* DCBx/DCBNL capability for PF that indicates
616 * whether DCBx is managed by firmware or host
617 * based agent (LLDPAD). Also, indicates what
618 * flavor of DCBx protocol (IEEE/CEE) is supported
619 * by the device. For now we're supporting IEEE
620 * mode only.
621 */
622 u16 dcbx_cap;
623
624 struct i40e_filter_control_settings filter_settings;
625
626 struct ptp_clock *ptp_clock;
627 struct ptp_clock_info ptp_caps;
628 struct sk_buff *ptp_tx_skb;
629 unsigned long ptp_tx_start;
630 struct hwtstamp_config tstamp_config;
631 struct timespec64 ptp_prev_hw_time;
632 ktime_t ptp_reset_start;
633 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
634 u32 ptp_adj_mult;
635 u32 tx_hwtstamp_timeouts;
636 u32 tx_hwtstamp_skipped;
637 u32 rx_hwtstamp_cleared;
638 u32 latch_event_flags;
639 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
640 unsigned long latch_events[4];
641 bool ptp_tx;
642 bool ptp_rx;
643 u16 rss_table_size; /* HW RSS table size */
644 u32 max_bw;
645 u32 min_bw;
646
647 u32 ioremap_len;
648 u32 fd_inv;
649 u16 phy_led_val;
650
651 u16 override_q_count;
652 u16 last_sw_conf_flags;
653 u16 last_sw_conf_valid_flags;
654 /* List to keep previous DDP profiles to be rolled back in the future */
655 struct list_head ddp_old_prof;
656};
657
658/**
659 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
660 * @macaddr: the MAC Address as the base key
661 *
662 * Simply copies the address and returns it as a u64 for hashing
663 **/
664static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
665{
666 u64 key = 0;
667
668 ether_addr_copy((u8 *)&key, macaddr);
669 return key;
670}
671
672enum i40e_filter_state {
673 I40E_FILTER_INVALID = 0, /* Invalid state */
674 I40E_FILTER_NEW, /* New, not sent to FW yet */
675 I40E_FILTER_ACTIVE, /* Added to switch by FW */
676 I40E_FILTER_FAILED, /* Rejected by FW */
677 I40E_FILTER_REMOVE, /* To be removed */
678/* There is no 'removed' state; the filter struct is freed */
679};
680struct i40e_mac_filter {
681 struct hlist_node hlist;
682 u8 macaddr[ETH_ALEN];
683#define I40E_VLAN_ANY -1
684 s16 vlan;
685 enum i40e_filter_state state;
686};
687
688/* Wrapper structure to keep track of filters while we are preparing to send
689 * firmware commands. We cannot send firmware commands while holding a
690 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
691 * a separate structure, which will track the state change and update the real
692 * filter while under lock. We can't simply hold the filters in a separate
693 * list, as this opens a window for a race condition when adding new MAC
694 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
695 */
696struct i40e_new_mac_filter {
697 struct hlist_node hlist;
698 struct i40e_mac_filter *f;
699
700 /* Track future changes to state separately */
701 enum i40e_filter_state state;
702};
703
704struct i40e_veb {
705 struct i40e_pf *pf;
706 u16 idx;
707 u16 veb_idx; /* index of VEB parent */
708 u16 seid;
709 u16 uplink_seid;
710 u16 stats_idx; /* index of VEB parent */
711 u8 enabled_tc;
712 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
713 u16 flags;
714 u16 bw_limit;
715 u8 bw_max_quanta;
716 bool is_abs_credits;
717 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
718 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
719 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
720 struct kobject *kobj;
721 bool stat_offsets_loaded;
722 struct i40e_eth_stats stats;
723 struct i40e_eth_stats stats_offsets;
724 struct i40e_veb_tc_stats tc_stats;
725 struct i40e_veb_tc_stats tc_stats_offsets;
726};
727
728/* struct that defines a VSI, associated with a dev */
729struct i40e_vsi {
730 struct net_device *netdev;
731 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
732 bool netdev_registered;
733 bool stat_offsets_loaded;
734
735 u32 current_netdev_flags;
736 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
737#define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
738#define I40E_VSI_FLAG_VEB_OWNER BIT(1)
739 unsigned long flags;
740
741 /* Per VSI lock to protect elements/hash (MAC filter) */
742 spinlock_t mac_filter_hash_lock;
743 /* Fixed size hash table with 2^8 buckets for MAC filters */
744 DECLARE_HASHTABLE(mac_filter_hash, 8);
745 bool has_vlan_filter;
746
747 /* VSI stats */
748 struct rtnl_link_stats64 net_stats;
749 struct rtnl_link_stats64 net_stats_offsets;
750 struct i40e_eth_stats eth_stats;
751 struct i40e_eth_stats eth_stats_offsets;
752 u32 tx_restart;
753 u32 tx_busy;
754 u64 tx_linearize;
755 u64 tx_force_wb;
756 u32 rx_buf_failed;
757 u32 rx_page_failed;
758
759 /* These are containers of ring pointers, allocated at run-time */
760 struct i40e_ring **rx_rings;
761 struct i40e_ring **tx_rings;
762 struct i40e_ring **xdp_rings; /* XDP Tx rings */
763
764 u32 active_filters;
765 u32 promisc_threshold;
766
767 u16 work_limit;
768 u16 int_rate_limit; /* value in usecs */
769
770 u16 rss_table_size; /* HW RSS table size */
771 u16 rss_size; /* Allocated RSS queues */
772 u8 *rss_hkey_user; /* User configured hash keys */
773 u8 *rss_lut_user; /* User configured lookup table entries */
774
775
776 u16 max_frame;
777 u16 rx_buf_len;
778
779 struct bpf_prog *xdp_prog;
780
781 /* List of q_vectors allocated to this VSI */
782 struct i40e_q_vector **q_vectors;
783 int num_q_vectors;
784 int base_vector;
785 bool irqs_ready;
786
787 u16 seid; /* HW index of this VSI (absolute index) */
788 u16 id; /* VSI number */
789 u16 uplink_seid;
790
791 u16 base_queue; /* vsi's first queue in hw array */
792 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
793 u16 req_queue_pairs; /* User requested queue pairs */
794 u16 num_queue_pairs; /* Used tx and rx pairs */
795 u16 num_tx_desc;
796 u16 num_rx_desc;
797 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
798 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
799
800 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
801 struct i40e_tc_configuration tc_config;
802 struct i40e_aqc_vsi_properties_data info;
803
804 /* VSI BW limit (absolute across all TCs) */
805 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
806 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
807
808 /* Relative TC credits across VSIs */
809 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
810 /* TC BW limit credits within VSI */
811 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
812 /* TC BW limit max quanta within VSI */
813 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
814
815 struct i40e_pf *back; /* Backreference to associated PF */
816 u16 idx; /* index in pf->vsi[] */
817 u16 veb_idx; /* index of VEB parent */
818 struct kobject *kobj; /* sysfs object */
819 bool current_isup; /* Sync 'link up' logging */
820 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
821
822 /* channel specific fields */
823 u16 cnt_q_avail; /* num of queues available for channel usage */
824 u16 orig_rss_size;
825 u16 current_rss_size;
826 bool reconfig_rss;
827
828 u16 next_base_queue; /* next queue to be used for channel setup */
829
830 struct list_head ch_list;
831 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
832
833 /* macvlan fields */
834#define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */
835#define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */
836 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS);
837 struct list_head macvlan_list;
838 int macvlan_cnt;
839
840 void *priv; /* client driver data reference. */
841
842 /* VSI specific handlers */
843 irqreturn_t (*irq_handler)(int irq, void *data);
844
845 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */
846} ____cacheline_internodealigned_in_smp;
847
848struct i40e_netdev_priv {
849 struct i40e_vsi *vsi;
850};
851
852/* struct that defines an interrupt vector */
853struct i40e_q_vector {
854 struct i40e_vsi *vsi;
855
856 u16 v_idx; /* index in the vsi->q_vector array. */
857 u16 reg_idx; /* register index of the interrupt */
858
859 struct napi_struct napi;
860
861 struct i40e_ring_container rx;
862 struct i40e_ring_container tx;
863
864 u8 itr_countdown; /* when 0 should adjust adaptive ITR */
865 u8 num_ringpairs; /* total number of ring pairs in vector */
866
867 cpumask_t affinity_mask;
868 struct irq_affinity_notify affinity_notify;
869
870 struct rcu_head rcu; /* to avoid race with update stats on free */
871 char name[I40E_INT_NAME_STR_LEN];
872 bool arm_wb_state;
873} ____cacheline_internodealigned_in_smp;
874
875/* lan device */
876struct i40e_device {
877 struct list_head list;
878 struct i40e_pf *pf;
879};
880
881/**
882 * i40e_nvm_version_str - format the NVM version strings
883 * @hw: ptr to the hardware info
884 **/
885static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
886{
887 static char buf[32];
888 u32 full_ver;
889
890 full_ver = hw->nvm.oem_ver;
891
892 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
893 u8 gen, snap;
894 u16 release;
895
896 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
897 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
898 I40E_OEM_SNAP_SHIFT);
899 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
900
901 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
902 } else {
903 u8 ver, patch;
904 u16 build;
905
906 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
907 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
908 I40E_OEM_VER_BUILD_MASK);
909 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
910
911 snprintf(buf, sizeof(buf),
912 "%x.%02x 0x%x %d.%d.%d",
913 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
914 I40E_NVM_VERSION_HI_SHIFT,
915 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
916 I40E_NVM_VERSION_LO_SHIFT,
917 hw->nvm.eetrack, ver, build, patch);
918 }
919
920 return buf;
921}
922
923/**
924 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
925 * @netdev: the corresponding netdev
926 *
927 * Return the PF struct for the given netdev
928 **/
929static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
930{
931 struct i40e_netdev_priv *np = netdev_priv(netdev);
932 struct i40e_vsi *vsi = np->vsi;
933
934 return vsi->back;
935}
936
937static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
938 irqreturn_t (*irq_handler)(int, void *))
939{
940 vsi->irq_handler = irq_handler;
941}
942
943/**
944 * i40e_get_fd_cnt_all - get the total FD filter space available
945 * @pf: pointer to the PF struct
946 **/
947static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
948{
949 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
950}
951
952/**
953 * i40e_read_fd_input_set - reads value of flow director input set register
954 * @pf: pointer to the PF struct
955 * @addr: register addr
956 *
957 * This function reads value of flow director input set register
958 * specified by 'addr' (which is specific to flow-type)
959 **/
960static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
961{
962 u64 val;
963
964 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
965 val <<= 32;
966 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
967
968 return val;
969}
970
971/**
972 * i40e_write_fd_input_set - writes value into flow director input set register
973 * @pf: pointer to the PF struct
974 * @addr: register addr
975 * @val: value to be written
976 *
977 * This function writes specified value to the register specified by 'addr'.
978 * This register is input set register based on flow-type.
979 **/
980static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
981 u16 addr, u64 val)
982{
983 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
984 (u32)(val >> 32));
985 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
986 (u32)(val & 0xFFFFFFFFULL));
987}
988
989/* needed by i40e_ethtool.c */
990int i40e_up(struct i40e_vsi *vsi);
991void i40e_down(struct i40e_vsi *vsi);
992extern const char i40e_driver_name[];
993void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
994void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
995int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
996int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
997void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
998 u16 rss_table_size, u16 rss_size);
999struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
1000/**
1001 * i40e_find_vsi_by_type - Find and return Flow Director VSI
1002 * @pf: PF to search for VSI
1003 * @type: Value indicating type of VSI we are looking for
1004 **/
1005static inline struct i40e_vsi *
1006i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
1007{
1008 int i;
1009
1010 for (i = 0; i < pf->num_alloc_vsi; i++) {
1011 struct i40e_vsi *vsi = pf->vsi[i];
1012
1013 if (vsi && vsi->type == type)
1014 return vsi;
1015 }
1016
1017 return NULL;
1018}
1019void i40e_update_stats(struct i40e_vsi *vsi);
1020void i40e_update_veb_stats(struct i40e_veb *veb);
1021void i40e_update_eth_stats(struct i40e_vsi *vsi);
1022struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
1023int i40e_fetch_switch_configuration(struct i40e_pf *pf,
1024 bool printconfig);
1025
1026int i40e_add_del_fdir(struct i40e_vsi *vsi,
1027 struct i40e_fdir_filter *input, bool add);
1028void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
1029u32 i40e_get_current_fd_count(struct i40e_pf *pf);
1030u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1031u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
1032u32 i40e_get_global_fd_count(struct i40e_pf *pf);
1033bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
1034void i40e_set_ethtool_ops(struct net_device *netdev);
1035struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1036 const u8 *macaddr, s16 vlan);
1037void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1038void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1039int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1040struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1041 u16 uplink, u32 param1);
1042int i40e_vsi_release(struct i40e_vsi *vsi);
1043void i40e_service_event_schedule(struct i40e_pf *pf);
1044void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1045 u8 *msg, u16 len);
1046
1047int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
1048 bool enable);
1049int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
1050int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1051void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1052void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
1053int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1054int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1055struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1056 u16 downlink_seid, u8 enabled_tc);
1057void i40e_veb_release(struct i40e_veb *veb);
1058
1059int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1060int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1061void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1062void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1063void i40e_pf_reset_stats(struct i40e_pf *pf);
1064#ifdef CONFIG_DEBUG_FS
1065void i40e_dbg_pf_init(struct i40e_pf *pf);
1066void i40e_dbg_pf_exit(struct i40e_pf *pf);
1067void i40e_dbg_init(void);
1068void i40e_dbg_exit(void);
1069#else
1070static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
1071static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
1072static inline void i40e_dbg_init(void) {}
1073static inline void i40e_dbg_exit(void) {}
1074#endif /* CONFIG_DEBUG_FS*/
1075/* needed by client drivers */
1076int i40e_lan_add_device(struct i40e_pf *pf);
1077int i40e_lan_del_device(struct i40e_pf *pf);
1078void i40e_client_subtask(struct i40e_pf *pf);
1079void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1080void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1081void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1082void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1083void i40e_client_update_msix_info(struct i40e_pf *pf);
1084int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1085/**
1086 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1087 * @vsi: pointer to a vsi
1088 * @vector: enable a particular Hw Interrupt vector, without base_vector
1089 **/
1090static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1091{
1092 struct i40e_pf *pf = vsi->back;
1093 struct i40e_hw *hw = &pf->hw;
1094 u32 val;
1095
1096 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1097 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1098 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1099 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1100 /* skip the flush */
1101}
1102
1103void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1104void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1105int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1106int i40e_open(struct net_device *netdev);
1107int i40e_close(struct net_device *netdev);
1108int i40e_vsi_open(struct i40e_vsi *vsi);
1109void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1110int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1111int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1112void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1113void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1114struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1115 const u8 *macaddr);
1116int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1117bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1118int i40e_count_filters(struct i40e_vsi *vsi);
1119struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1120void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1121#ifdef CONFIG_I40E_DCB
1122void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1123 struct i40e_dcbx_config *old_cfg,
1124 struct i40e_dcbx_config *new_cfg);
1125void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1126void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1127bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1128 struct i40e_dcbx_config *old_cfg,
1129 struct i40e_dcbx_config *new_cfg);
1130#endif /* CONFIG_I40E_DCB */
1131void i40e_ptp_rx_hang(struct i40e_pf *pf);
1132void i40e_ptp_tx_hang(struct i40e_pf *pf);
1133void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1134void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1135void i40e_ptp_set_increment(struct i40e_pf *pf);
1136int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1137int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1138void i40e_ptp_save_hw_time(struct i40e_pf *pf);
1139void i40e_ptp_restore_hw_time(struct i40e_pf *pf);
1140void i40e_ptp_init(struct i40e_pf *pf);
1141void i40e_ptp_stop(struct i40e_pf *pf);
1142int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1143i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
1144i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
1145i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1146void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1147
1148void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags);
1149
1150static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1151{
1152 return !!READ_ONCE(vsi->xdp_prog);
1153}
1154
1155int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1156int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1157int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1158 struct i40e_cloud_filter *filter,
1159 bool add);
1160int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1161 struct i40e_cloud_filter *filter,
1162 bool add);
1163#endif /* _I40E_H_ */