Loading...
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4 */
5
6#ifndef __MT7530_H
7#define __MT7530_H
8
9#define MT7530_NUM_PORTS 7
10#define MT7530_NUM_PHYS 5
11#define MT7530_NUM_FDB_RECORDS 2048
12#define MT7530_ALL_MEMBERS 0xff
13
14#define MTK_HDR_LEN 4
15#define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
16
17enum mt753x_id {
18 ID_MT7530 = 0,
19 ID_MT7621 = 1,
20 ID_MT7531 = 2,
21 ID_MT7988 = 3,
22};
23
24#define NUM_TRGMII_CTRL 5
25
26#define TRGMII_BASE(x) (0x10000 + (x))
27
28/* Registers to ethsys access */
29#define ETHSYS_CLKCFG0 0x2c
30#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
31
32#define SYSC_REG_RSTCTRL 0x34
33#define RESET_MCM BIT(2)
34
35/* Register for ARL global control */
36#define MT753X_AGC 0xc
37#define LOCAL_EN BIT(7)
38
39/* Registers to mac forward control for unknown frames */
40#define MT7530_MFC 0x10
41#define BC_FFP(x) (((x) & 0xff) << 24)
42#define BC_FFP_MASK BC_FFP(~0)
43#define UNM_FFP(x) (((x) & 0xff) << 16)
44#define UNM_FFP_MASK UNM_FFP(~0)
45#define UNU_FFP(x) (((x) & 0xff) << 8)
46#define UNU_FFP_MASK UNU_FFP(~0)
47#define CPU_EN BIT(7)
48#define CPU_PORT_MASK GENMASK(6, 4)
49#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x)
50#define MIRROR_EN BIT(3)
51#define MIRROR_PORT(x) ((x) & 0x7)
52#define MIRROR_MASK 0x7
53
54/* Registers for CPU forward control */
55#define MT7531_CFC 0x4
56#define MT7531_MIRROR_EN BIT(19)
57#define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
58#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
59#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
60#define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
61#define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
62
63#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
64 MT7531_CFC : MT7530_MFC)
65#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
66 MT7531_MIRROR_EN : MIRROR_EN)
67#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
68 MT7531_MIRROR_MASK : MIRROR_MASK)
69
70/* Registers for BPDU and PAE frame control*/
71#define MT753X_BPC 0x24
72#define MT753X_PAE_BPDU_FR BIT(25)
73#define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22)
74#define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
75#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16)
76#define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x)
77#define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6)
78#define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x)
79#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
80
81/* Register for :01 and :02 MAC DA frame control */
82#define MT753X_RGAC1 0x28
83#define MT753X_R02_BPDU_FR BIT(25)
84#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22)
85#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
86#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16)
87#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
88#define MT753X_R01_BPDU_FR BIT(9)
89#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6)
90#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
91#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
92
93/* Register for :03 and :0E MAC DA frame control */
94#define MT753X_RGAC2 0x2c
95#define MT753X_R0E_BPDU_FR BIT(25)
96#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22)
97#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
98#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
99#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
100#define MT753X_R03_BPDU_FR BIT(9)
101#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6)
102#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
103#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)
104
105enum mt753x_bpdu_port_fw {
106 MT753X_BPDU_FOLLOW_MFC,
107 MT753X_BPDU_CPU_EXCLUDE = 4,
108 MT753X_BPDU_CPU_INCLUDE = 5,
109 MT753X_BPDU_CPU_ONLY = 6,
110 MT753X_BPDU_DROP = 7,
111};
112
113/* Registers for address table access */
114#define MT7530_ATA1 0x74
115#define STATIC_EMP 0
116#define STATIC_ENT 3
117#define MT7530_ATA2 0x78
118#define ATA2_IVL BIT(15)
119#define ATA2_FID(x) (((x) & 0x7) << 12)
120
121/* Register for address table write data */
122#define MT7530_ATWD 0x7c
123
124/* Register for address table control */
125#define MT7530_ATC 0x80
126#define ATC_HASH (((x) & 0xfff) << 16)
127#define ATC_BUSY BIT(15)
128#define ATC_SRCH_END BIT(14)
129#define ATC_SRCH_HIT BIT(13)
130#define ATC_INVALID BIT(12)
131#define ATC_MAT(x) (((x) & 0xf) << 8)
132#define ATC_MAT_MACTAB ATC_MAT(0)
133
134enum mt7530_fdb_cmd {
135 MT7530_FDB_READ = 0,
136 MT7530_FDB_WRITE = 1,
137 MT7530_FDB_FLUSH = 2,
138 MT7530_FDB_START = 4,
139 MT7530_FDB_NEXT = 5,
140};
141
142/* Registers for table search read address */
143#define MT7530_TSRA1 0x84
144#define MAC_BYTE_0 24
145#define MAC_BYTE_1 16
146#define MAC_BYTE_2 8
147#define MAC_BYTE_3 0
148#define MAC_BYTE_MASK 0xff
149
150#define MT7530_TSRA2 0x88
151#define MAC_BYTE_4 24
152#define MAC_BYTE_5 16
153#define CVID 0
154#define CVID_MASK 0xfff
155
156#define MT7530_ATRD 0x8C
157#define AGE_TIMER 24
158#define AGE_TIMER_MASK 0xff
159#define PORT_MAP 4
160#define PORT_MAP_MASK 0xff
161#define ENT_STATUS 2
162#define ENT_STATUS_MASK 0x3
163
164/* Register for vlan table control */
165#define MT7530_VTCR 0x90
166#define VTCR_BUSY BIT(31)
167#define VTCR_INVALID BIT(16)
168#define VTCR_FUNC(x) (((x) & 0xf) << 12)
169#define VTCR_VID ((x) & 0xfff)
170
171enum mt7530_vlan_cmd {
172 /* Read/Write the specified VID entry from VAWD register based
173 * on VID.
174 */
175 MT7530_VTCR_RD_VID = 0,
176 MT7530_VTCR_WR_VID = 1,
177};
178
179/* Register for setup vlan and acl write data */
180#define MT7530_VAWD1 0x94
181#define PORT_STAG BIT(31)
182/* Independent VLAN Learning */
183#define IVL_MAC BIT(30)
184/* Egress Tag Consistent */
185#define EG_CON BIT(29)
186/* Per VLAN Egress Tag Control */
187#define VTAG_EN BIT(28)
188/* VLAN Member Control */
189#define PORT_MEM(x) (((x) & 0xff) << 16)
190/* Filter ID */
191#define FID(x) (((x) & 0x7) << 1)
192/* VLAN Entry Valid */
193#define VLAN_VALID BIT(0)
194#define PORT_MEM_SHFT 16
195#define PORT_MEM_MASK 0xff
196
197enum mt7530_fid {
198 FID_STANDALONE = 0,
199 FID_BRIDGED = 1,
200};
201
202#define MT7530_VAWD2 0x98
203/* Egress Tag Control */
204#define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
205#define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
206
207enum mt7530_vlan_egress_attr {
208 MT7530_VLAN_EGRESS_UNTAG = 0,
209 MT7530_VLAN_EGRESS_TAG = 2,
210 MT7530_VLAN_EGRESS_STACK = 3,
211};
212
213/* Register for address age control */
214#define MT7530_AAC 0xa0
215/* Disable ageing */
216#define AGE_DIS BIT(20)
217/* Age count */
218#define AGE_CNT_MASK GENMASK(19, 12)
219#define AGE_CNT_MAX 0xff
220#define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12))
221/* Age unit */
222#define AGE_UNIT_MASK GENMASK(11, 0)
223#define AGE_UNIT_MAX 0xfff
224#define AGE_UNIT(x) (AGE_UNIT_MASK & (x))
225
226/* Register for port STP state control */
227#define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
228#define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2))
229#define FID_PST_MASK(fid) FID_PST(fid, 0x3)
230
231enum mt7530_stp_state {
232 MT7530_STP_DISABLED = 0,
233 MT7530_STP_BLOCKING = 1,
234 MT7530_STP_LISTENING = 1,
235 MT7530_STP_LEARNING = 2,
236 MT7530_STP_FORWARDING = 3
237};
238
239/* Register for port control */
240#define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
241#define PORT_TX_MIR BIT(9)
242#define PORT_RX_MIR BIT(8)
243#define PORT_VLAN(x) ((x) & 0x3)
244
245enum mt7530_port_mode {
246 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
247 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
248
249 /* Fallback Mode: Forward received frames with ingress ports that do
250 * not belong to the VLAN member. Frames whose VID is not listed on
251 * the VLAN table are forwarded by the PCR_MATRIX members.
252 */
253 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
254
255 /* Security Mode: Discard any frame due to ingress membership
256 * violation or VID missed on the VLAN table.
257 */
258 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
259};
260
261#define PCR_MATRIX(x) (((x) & 0xff) << 16)
262#define PORT_PRI(x) (((x) & 0x7) << 24)
263#define EG_TAG(x) (((x) & 0x3) << 28)
264#define PCR_MATRIX_MASK PCR_MATRIX(0xff)
265#define PCR_MATRIX_CLR PCR_MATRIX(0)
266#define PCR_PORT_VLAN_MASK PORT_VLAN(3)
267
268/* Register for port security control */
269#define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
270#define SA_DIS BIT(4)
271
272/* Register for port vlan control */
273#define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
274#define PORT_SPEC_TAG BIT(5)
275#define PVC_EG_TAG(x) (((x) & 0x7) << 8)
276#define PVC_EG_TAG_MASK PVC_EG_TAG(7)
277#define VLAN_ATTR(x) (((x) & 0x3) << 6)
278#define VLAN_ATTR_MASK VLAN_ATTR(3)
279#define ACC_FRM_MASK GENMASK(1, 0)
280
281enum mt7530_vlan_port_eg_tag {
282 MT7530_VLAN_EG_DISABLED = 0,
283 MT7530_VLAN_EG_CONSISTENT = 1,
284 MT7530_VLAN_EG_UNTAGGED = 4,
285};
286
287enum mt7530_vlan_port_attr {
288 MT7530_VLAN_USER = 0,
289 MT7530_VLAN_TRANSPARENT = 3,
290};
291
292enum mt7530_vlan_port_acc_frm {
293 MT7530_VLAN_ACC_ALL = 0,
294 MT7530_VLAN_ACC_TAGGED = 1,
295 MT7530_VLAN_ACC_UNTAGGED = 2,
296};
297
298#define STAG_VPID (((x) & 0xffff) << 16)
299
300/* Register for port port-and-protocol based vlan 1 control */
301#define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
302#define G0_PORT_VID(x) (((x) & 0xfff) << 0)
303#define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
304#define G0_PORT_VID_DEF G0_PORT_VID(0)
305
306/* Register for port MAC control register */
307#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
308#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
309#define PMCR_EXT_PHY BIT(17)
310#define PMCR_MAC_MODE BIT(16)
311#define PMCR_FORCE_MODE BIT(15)
312#define PMCR_TX_EN BIT(14)
313#define PMCR_RX_EN BIT(13)
314#define PMCR_BACKOFF_EN BIT(9)
315#define PMCR_BACKPR_EN BIT(8)
316#define PMCR_FORCE_EEE1G BIT(7)
317#define PMCR_FORCE_EEE100 BIT(6)
318#define PMCR_TX_FC_EN BIT(5)
319#define PMCR_RX_FC_EN BIT(4)
320#define PMCR_FORCE_SPEED_1000 BIT(3)
321#define PMCR_FORCE_SPEED_100 BIT(2)
322#define PMCR_FORCE_FDX BIT(1)
323#define PMCR_FORCE_LNK BIT(0)
324#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
325 PMCR_FORCE_SPEED_1000)
326#define MT7531_FORCE_LNK BIT(31)
327#define MT7531_FORCE_SPD BIT(30)
328#define MT7531_FORCE_DPX BIT(29)
329#define MT7531_FORCE_RX_FC BIT(28)
330#define MT7531_FORCE_TX_FC BIT(27)
331#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
332 MT7531_FORCE_SPD | \
333 MT7531_FORCE_DPX | \
334 MT7531_FORCE_RX_FC | \
335 MT7531_FORCE_TX_FC)
336#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
337 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
338 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
339 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
340 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
341
342#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
343#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
344#define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16)
345#define LPI_THRESH_MASK GENMASK(15, 4)
346#define LPI_THRESH_SHT 4
347#define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK)
348#define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT)
349#define LPI_MODE_EN BIT(0)
350
351#define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
352#define PMSR_EEE1G BIT(7)
353#define PMSR_EEE100M BIT(6)
354#define PMSR_RX_FC BIT(5)
355#define PMSR_TX_FC BIT(4)
356#define PMSR_SPEED_1000 BIT(3)
357#define PMSR_SPEED_100 BIT(2)
358#define PMSR_SPEED_10 0x00
359#define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000)
360#define PMSR_DPX BIT(1)
361#define PMSR_LINK BIT(0)
362
363/* Register for port debug count */
364#define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
365#define MT7531_DIS_CLR BIT(31)
366
367#define MT7530_GMACCR 0x30e0
368#define MAX_RX_JUMBO(x) ((x) << 2)
369#define MAX_RX_JUMBO_MASK GENMASK(5, 2)
370#define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
371#define MAX_RX_PKT_LEN_1522 0x0
372#define MAX_RX_PKT_LEN_1536 0x1
373#define MAX_RX_PKT_LEN_1552 0x2
374#define MAX_RX_PKT_LEN_JUMBO 0x3
375
376/* Register for MIB */
377#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
378#define MT7530_MIB_CCR 0x4fe0
379#define CCR_MIB_ENABLE BIT(31)
380#define CCR_RX_OCT_CNT_GOOD BIT(7)
381#define CCR_RX_OCT_CNT_BAD BIT(6)
382#define CCR_TX_OCT_CNT_GOOD BIT(5)
383#define CCR_TX_OCT_CNT_BAD BIT(4)
384#define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \
385 CCR_RX_OCT_CNT_BAD | \
386 CCR_TX_OCT_CNT_GOOD | \
387 CCR_TX_OCT_CNT_BAD)
388#define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \
389 CCR_RX_OCT_CNT_GOOD | \
390 CCR_RX_OCT_CNT_BAD | \
391 CCR_TX_OCT_CNT_GOOD | \
392 CCR_TX_OCT_CNT_BAD)
393
394/* MT7531 SGMII register group */
395#define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000)
396#define MT7531_PHYA_CTRL_SIGNAL3 0x128
397
398/* Register for system reset */
399#define MT7530_SYS_CTRL 0x7000
400#define SYS_CTRL_PHY_RST BIT(2)
401#define SYS_CTRL_SW_RST BIT(1)
402#define SYS_CTRL_REG_RST BIT(0)
403
404/* Register for system interrupt */
405#define MT7530_SYS_INT_EN 0x7008
406
407/* Register for system interrupt status */
408#define MT7530_SYS_INT_STS 0x700c
409
410/* Register for PHY Indirect Access Control */
411#define MT7531_PHY_IAC 0x701C
412#define MT7531_PHY_ACS_ST BIT(31)
413#define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
414#define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
415#define MT7531_MDIO_CMD_MASK (0x3 << 18)
416#define MT7531_MDIO_ST_MASK (0x3 << 16)
417#define MT7531_MDIO_RW_DATA_MASK (0xffff)
418#define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
419#define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
420#define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
421#define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
422#define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
423
424enum mt7531_phy_iac_cmd {
425 MT7531_MDIO_ADDR = 0,
426 MT7531_MDIO_WRITE = 1,
427 MT7531_MDIO_READ = 2,
428 MT7531_MDIO_READ_CL45 = 3,
429};
430
431/* MDIO_ST: MDIO start field */
432enum mt7531_mdio_st {
433 MT7531_MDIO_ST_CL45 = 0,
434 MT7531_MDIO_ST_CL22 = 1,
435};
436
437#define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
438 MT7531_MDIO_CMD(MT7531_MDIO_READ))
439#define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
440 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
441#define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
442 MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
443#define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
444 MT7531_MDIO_CMD(MT7531_MDIO_READ))
445#define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
446 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
447
448/* Register for RGMII clock phase */
449#define MT7531_CLKGEN_CTRL 0x7500
450#define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
451#define CLK_SKEW_OUT_MASK GENMASK(9, 8)
452#define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
453#define CLK_SKEW_IN_MASK GENMASK(7, 6)
454#define RXCLK_NO_DELAY BIT(5)
455#define TXCLK_NO_REVERSE BIT(4)
456#define GP_MODE(x) (((x) & 0x3) << 1)
457#define GP_MODE_MASK GENMASK(2, 1)
458#define GP_CLK_EN BIT(0)
459
460enum mt7531_gp_mode {
461 MT7531_GP_MODE_RGMII = 0,
462 MT7531_GP_MODE_MII = 1,
463 MT7531_GP_MODE_REV_MII = 2
464};
465
466enum mt7531_clk_skew {
467 MT7531_CLK_SKEW_NO_CHG = 0,
468 MT7531_CLK_SKEW_DLY_100PPS = 1,
469 MT7531_CLK_SKEW_DLY_200PPS = 2,
470 MT7531_CLK_SKEW_REVERSE = 3,
471};
472
473/* Register for hw trap status */
474#define MT7530_HWTRAP 0x7800
475#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
476#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
477#define HWTRAP_XTAL_40MHZ (BIT(10))
478#define HWTRAP_XTAL_20MHZ (BIT(9))
479
480#define MT7531_HWTRAP 0x7800
481#define HWTRAP_XTAL_FSEL_MASK BIT(7)
482#define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
483#define HWTRAP_XTAL_FSEL_40MHZ 0
484/* Unique fields of (M)HWSTRAP for MT7531 */
485#define XTAL_FSEL_S 7
486#define XTAL_FSEL_M BIT(7)
487#define PHY_EN BIT(6)
488#define CHG_STRAP BIT(8)
489
490/* Register for hw trap modification */
491#define MT7530_MHWTRAP 0x7804
492#define MHWTRAP_PHY0_SEL BIT(20)
493#define MHWTRAP_MANUAL BIT(16)
494#define MHWTRAP_P5_MAC_SEL BIT(13)
495#define MHWTRAP_P6_DIS BIT(8)
496#define MHWTRAP_P5_RGMII_MODE BIT(7)
497#define MHWTRAP_P5_DIS BIT(6)
498#define MHWTRAP_PHY_ACCESS BIT(5)
499
500/* Register for TOP signal control */
501#define MT7530_TOP_SIG_CTRL 0x7808
502#define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
503
504#define MT7531_TOP_SIG_SR 0x780c
505#define PAD_DUAL_SGMII_EN BIT(1)
506#define PAD_MCM_SMI_EN BIT(0)
507
508#define MT7530_IO_DRV_CR 0x7810
509#define P5_IO_CLK_DRV(x) ((x) & 0x3)
510#define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
511
512#define MT7531_CHIP_REV 0x781C
513
514#define MT7531_PLLGP_EN 0x7820
515#define EN_COREPLL BIT(2)
516#define SW_CLKSW BIT(1)
517#define SW_PLLGP BIT(0)
518
519#define MT7530_P6ECR 0x7830
520#define P6_INTF_MODE_MASK 0x3
521#define P6_INTF_MODE(x) ((x) & 0x3)
522
523#define MT7531_PLLGP_CR0 0x78a8
524#define RG_COREPLL_EN BIT(22)
525#define RG_COREPLL_POSDIV_S 23
526#define RG_COREPLL_POSDIV_M 0x3800000
527#define RG_COREPLL_SDM_PCW_S 1
528#define RG_COREPLL_SDM_PCW_M 0x3ffffe
529#define RG_COREPLL_SDM_PCW_CHG BIT(0)
530
531/* Registers for RGMII and SGMII PLL clock */
532#define MT7531_ANA_PLLGP_CR2 0x78b0
533#define MT7531_ANA_PLLGP_CR5 0x78bc
534
535/* Registers for TRGMII on the both side */
536#define MT7530_TRGMII_RCK_CTRL 0x7a00
537#define RX_RST BIT(31)
538#define RXC_DQSISEL BIT(30)
539#define DQSI1_TAP_MASK (0x7f << 8)
540#define DQSI0_TAP_MASK 0x7f
541#define DQSI1_TAP(x) (((x) & 0x7f) << 8)
542#define DQSI0_TAP(x) ((x) & 0x7f)
543
544#define MT7530_TRGMII_RCK_RTT 0x7a04
545#define DQS1_GATE BIT(31)
546#define DQS0_GATE BIT(30)
547
548#define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
549#define BSLIP_EN BIT(31)
550#define EDGE_CHK BIT(30)
551#define RD_TAP_MASK 0x7f
552#define RD_TAP(x) ((x) & 0x7f)
553
554#define MT7530_TRGMII_TXCTRL 0x7a40
555#define TRAIN_TXEN BIT(31)
556#define TXC_INV BIT(30)
557#define TX_RST BIT(28)
558
559#define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
560#define TD_DM_DRVP(x) ((x) & 0xf)
561#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
562
563#define MT7530_TRGMII_TCK_CTRL 0x7a78
564#define TCK_TAP(x) (((x) & 0xf) << 8)
565
566#define MT7530_P5RGMIIRXCR 0x7b00
567#define CSR_RGMII_EDGE_ALIGN BIT(8)
568#define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
569
570#define MT7530_P5RGMIITXCR 0x7b04
571#define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
572
573/* Registers for GPIO mode */
574#define MT7531_GPIO_MODE0 0x7c0c
575#define MT7531_GPIO0_MASK GENMASK(3, 0)
576#define MT7531_GPIO0_INTERRUPT 1
577
578#define MT7531_GPIO_MODE1 0x7c10
579#define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
580#define MT7531_EXT_P_MDC_11 (2 << 12)
581#define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
582#define MT7531_EXT_P_MDIO_12 (2 << 16)
583
584/* Registers for LED GPIO control (MT7530 only)
585 * All registers follow this pattern:
586 * [ 2: 0] port 0
587 * [ 6: 4] port 1
588 * [10: 8] port 2
589 * [14:12] port 3
590 * [18:16] port 4
591 */
592
593/* LED enable, 0: Disable, 1: Enable (Default) */
594#define MT7530_LED_EN 0x7d00
595/* LED mode, 0: GPIO mode, 1: PHY mode (Default) */
596#define MT7530_LED_IO_MODE 0x7d04
597/* GPIO direction, 0: Input, 1: Output */
598#define MT7530_LED_GPIO_DIR 0x7d10
599/* GPIO output enable, 0: Disable, 1: Enable */
600#define MT7530_LED_GPIO_OE 0x7d14
601/* GPIO value, 0: Low, 1: High */
602#define MT7530_LED_GPIO_DATA 0x7d18
603
604#define MT7530_CREV 0x7ffc
605#define CHIP_NAME_SHIFT 16
606#define MT7530_ID 0x7530
607
608#define MT7531_CREV 0x781C
609#define CHIP_REV_M 0x0f
610#define MT7531_ID 0x7531
611
612/* Registers for core PLL access through mmd indirect */
613#define CORE_PLL_GROUP2 0x401
614#define RG_SYSPLL_EN_NORMAL BIT(15)
615#define RG_SYSPLL_VODEN BIT(14)
616#define RG_SYSPLL_LF BIT(13)
617#define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
618#define RG_SYSPLL_LVROD_EN BIT(10)
619#define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
620#define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
621#define RG_SYSPLL_FBKSEL BIT(4)
622#define RT_SYSPLL_EN_AFE_OLT BIT(0)
623
624#define CORE_PLL_GROUP4 0x403
625#define RG_SYSPLL_DDSFBK_EN BIT(12)
626#define RG_SYSPLL_BIAS_EN BIT(11)
627#define RG_SYSPLL_BIAS_LPF_EN BIT(10)
628#define MT7531_RG_SYSPLL_DMY2 BIT(6)
629#define MT7531_PHY_PLL_OFF BIT(5)
630#define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
631
632#define MT753X_CTRL_PHY_ADDR 0
633
634#define CORE_PLL_GROUP5 0x404
635#define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
636
637#define CORE_PLL_GROUP6 0x405
638#define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
639
640#define CORE_PLL_GROUP7 0x406
641#define RG_LCDDS_PWDB BIT(15)
642#define RG_LCDDS_ISO_EN BIT(13)
643#define RG_LCCDS_C(x) (((x) & 0x7) << 4)
644#define RG_LCDDS_PCW_NCPO_CHG BIT(3)
645
646#define CORE_PLL_GROUP10 0x409
647#define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
648
649#define CORE_PLL_GROUP11 0x40a
650#define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
651
652#define CORE_GSWPLL_GRP1 0x40d
653#define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
654#define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
655#define RG_GSWPLL_EN_PRE BIT(11)
656#define RG_GSWPLL_FBKSEL BIT(10)
657#define RG_GSWPLL_BP BIT(9)
658#define RG_GSWPLL_BR BIT(8)
659#define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
660
661#define CORE_GSWPLL_GRP2 0x40e
662#define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
663#define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
664
665#define CORE_TRGMII_GSW_CLK_CG 0x410
666#define REG_GSWCK_EN BIT(0)
667#define REG_TRGMIICK_EN BIT(1)
668
669#define MIB_DESC(_s, _o, _n) \
670 { \
671 .size = (_s), \
672 .offset = (_o), \
673 .name = (_n), \
674 }
675
676struct mt7530_mib_desc {
677 unsigned int size;
678 unsigned int offset;
679 const char *name;
680};
681
682struct mt7530_fdb {
683 u16 vid;
684 u8 port_mask;
685 u8 aging;
686 u8 mac[6];
687 bool noarp;
688};
689
690/* struct mt7530_port - This is the main data structure for holding the state
691 * of the port.
692 * @enable: The status used for show port is enabled or not.
693 * @pm: The matrix used to show all connections with the port.
694 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
695 * untagged frames will be assigned to the related VLAN.
696 * @sgmii_pcs: Pointer to PCS instance for SerDes ports
697 */
698struct mt7530_port {
699 bool enable;
700 u32 pm;
701 u16 pvid;
702 struct phylink_pcs *sgmii_pcs;
703};
704
705/* Port 5 interface select definitions */
706enum p5_interface_select {
707 P5_DISABLED,
708 P5_INTF_SEL_PHY_P0,
709 P5_INTF_SEL_PHY_P4,
710 P5_INTF_SEL_GMAC5,
711};
712
713struct mt7530_priv;
714
715struct mt753x_pcs {
716 struct phylink_pcs pcs;
717 struct mt7530_priv *priv;
718 int port;
719};
720
721/* struct mt753x_info - This is the main data structure for holding the specific
722 * part for each supported device
723 * @sw_setup: Holding the handler to a device initialization
724 * @phy_read_c22: Holding the way reading PHY port using C22
725 * @phy_write_c22: Holding the way writing PHY port using C22
726 * @phy_read_c45: Holding the way reading PHY port using C45
727 * @phy_write_c45: Holding the way writing PHY port using C45
728 * @phy_mode_supported: Check if the PHY type is being supported on a certain
729 * port
730 * @mac_port_validate: Holding the way to set addition validate type for a
731 * certan MAC port
732 * @mac_port_config: Holding the way setting up the PHY attribute to a
733 * certain MAC port
734 */
735struct mt753x_info {
736 enum mt753x_id id;
737
738 const struct phylink_pcs_ops *pcs_ops;
739
740 int (*sw_setup)(struct dsa_switch *ds);
741 int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum);
742 int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum,
743 u16 val);
744 int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad,
745 int regnum);
746 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
747 int regnum, u16 val);
748 void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
749 struct phylink_config *config);
750 void (*mac_port_validate)(struct dsa_switch *ds, int port,
751 phy_interface_t interface,
752 unsigned long *supported);
753 void (*mac_port_config)(struct dsa_switch *ds, int port,
754 unsigned int mode,
755 phy_interface_t interface);
756};
757
758/* struct mt7530_priv - This is the main data structure for holding the state
759 * of the driver
760 * @dev: The device pointer
761 * @ds: The pointer to the dsa core structure
762 * @bus: The bus used for the device and built-in PHY
763 * @regmap: The regmap instance representing all switch registers
764 * @rstc: The pointer to reset control used by MCM
765 * @core_pwr: The power supplied into the core
766 * @io_pwr: The power supplied into the I/O
767 * @reset: The descriptor for GPIO line tied to its reset pin
768 * @mcm: Flag for distinguishing if standalone IC or module
769 * coupling
770 * @ports: Holding the state among ports
771 * @reg_mutex: The lock for protecting among process accessing
772 * registers
773 * @p5_intf_sel: Holding the current port 5 interface select
774 * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
775 * has got SGMII
776 * @irq: IRQ number of the switch
777 * @irq_domain: IRQ domain of the switch irq_chip
778 * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
779 * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
780 * @active_cpu_ports: Holding the active CPU ports
781 */
782struct mt7530_priv {
783 struct device *dev;
784 struct dsa_switch *ds;
785 struct mii_bus *bus;
786 struct regmap *regmap;
787 struct reset_control *rstc;
788 struct regulator *core_pwr;
789 struct regulator *io_pwr;
790 struct gpio_desc *reset;
791 const struct mt753x_info *info;
792 unsigned int id;
793 bool mcm;
794 enum p5_interface_select p5_intf_sel;
795 bool p5_sgmii;
796 u8 mirror_rx;
797 u8 mirror_tx;
798 struct mt7530_port ports[MT7530_NUM_PORTS];
799 struct mt753x_pcs pcs[MT7530_NUM_PORTS];
800 /* protect among processes for registers access*/
801 struct mutex reg_mutex;
802 int irq;
803 struct irq_domain *irq_domain;
804 u32 irq_enable;
805 int (*create_sgmii)(struct mt7530_priv *priv);
806 u8 active_cpu_ports;
807};
808
809struct mt7530_hw_vlan_entry {
810 int port;
811 u8 old_members;
812 bool untagged;
813};
814
815static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
816 int port, bool untagged)
817{
818 e->port = port;
819 e->untagged = untagged;
820}
821
822typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
823 struct mt7530_hw_vlan_entry *);
824
825struct mt7530_hw_stats {
826 const char *string;
827 u16 reg;
828 u8 sizeof_stat;
829};
830
831struct mt7530_dummy_poll {
832 struct mt7530_priv *priv;
833 u32 reg;
834};
835
836static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
837 struct mt7530_priv *priv, u32 reg)
838{
839 p->priv = priv;
840 p->reg = reg;
841}
842
843int mt7530_probe_common(struct mt7530_priv *priv);
844void mt7530_remove_common(struct mt7530_priv *priv);
845
846extern const struct dsa_switch_ops mt7530_switch_ops;
847extern const struct mt753x_info mt753x_table[];
848
849#endif /* __MT7530_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4 */
5
6#ifndef __MT7530_H
7#define __MT7530_H
8
9#define MT7530_NUM_PORTS 7
10#define MT7530_CPU_PORT 6
11#define MT7530_NUM_FDB_RECORDS 2048
12#define MT7530_ALL_MEMBERS 0xff
13
14enum {
15 ID_MT7530 = 0,
16 ID_MT7621 = 1,
17};
18
19#define NUM_TRGMII_CTRL 5
20
21#define TRGMII_BASE(x) (0x10000 + (x))
22
23/* Registers to ethsys access */
24#define ETHSYS_CLKCFG0 0x2c
25#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
26
27#define SYSC_REG_RSTCTRL 0x34
28#define RESET_MCM BIT(2)
29
30/* Registers to mac forward control for unknown frames */
31#define MT7530_MFC 0x10
32#define BC_FFP(x) (((x) & 0xff) << 24)
33#define UNM_FFP(x) (((x) & 0xff) << 16)
34#define UNM_FFP_MASK UNM_FFP(~0)
35#define UNU_FFP(x) (((x) & 0xff) << 8)
36#define UNU_FFP_MASK UNU_FFP(~0)
37#define CPU_EN BIT(7)
38#define CPU_PORT(x) ((x) << 4)
39#define CPU_MASK (0xf << 4)
40#define MIRROR_EN BIT(3)
41#define MIRROR_PORT(x) ((x) & 0x7)
42#define MIRROR_MASK 0x7
43
44/* Registers for address table access */
45#define MT7530_ATA1 0x74
46#define STATIC_EMP 0
47#define STATIC_ENT 3
48#define MT7530_ATA2 0x78
49
50/* Register for address table write data */
51#define MT7530_ATWD 0x7c
52
53/* Register for address table control */
54#define MT7530_ATC 0x80
55#define ATC_HASH (((x) & 0xfff) << 16)
56#define ATC_BUSY BIT(15)
57#define ATC_SRCH_END BIT(14)
58#define ATC_SRCH_HIT BIT(13)
59#define ATC_INVALID BIT(12)
60#define ATC_MAT(x) (((x) & 0xf) << 8)
61#define ATC_MAT_MACTAB ATC_MAT(0)
62
63enum mt7530_fdb_cmd {
64 MT7530_FDB_READ = 0,
65 MT7530_FDB_WRITE = 1,
66 MT7530_FDB_FLUSH = 2,
67 MT7530_FDB_START = 4,
68 MT7530_FDB_NEXT = 5,
69};
70
71/* Registers for table search read address */
72#define MT7530_TSRA1 0x84
73#define MAC_BYTE_0 24
74#define MAC_BYTE_1 16
75#define MAC_BYTE_2 8
76#define MAC_BYTE_3 0
77#define MAC_BYTE_MASK 0xff
78
79#define MT7530_TSRA2 0x88
80#define MAC_BYTE_4 24
81#define MAC_BYTE_5 16
82#define CVID 0
83#define CVID_MASK 0xfff
84
85#define MT7530_ATRD 0x8C
86#define AGE_TIMER 24
87#define AGE_TIMER_MASK 0xff
88#define PORT_MAP 4
89#define PORT_MAP_MASK 0xff
90#define ENT_STATUS 2
91#define ENT_STATUS_MASK 0x3
92
93/* Register for vlan table control */
94#define MT7530_VTCR 0x90
95#define VTCR_BUSY BIT(31)
96#define VTCR_INVALID BIT(16)
97#define VTCR_FUNC(x) (((x) & 0xf) << 12)
98#define VTCR_VID ((x) & 0xfff)
99
100enum mt7530_vlan_cmd {
101 /* Read/Write the specified VID entry from VAWD register based
102 * on VID.
103 */
104 MT7530_VTCR_RD_VID = 0,
105 MT7530_VTCR_WR_VID = 1,
106};
107
108/* Register for setup vlan and acl write data */
109#define MT7530_VAWD1 0x94
110#define PORT_STAG BIT(31)
111/* Independent VLAN Learning */
112#define IVL_MAC BIT(30)
113/* Per VLAN Egress Tag Control */
114#define VTAG_EN BIT(28)
115/* VLAN Member Control */
116#define PORT_MEM(x) (((x) & 0xff) << 16)
117/* VLAN Entry Valid */
118#define VLAN_VALID BIT(0)
119#define PORT_MEM_SHFT 16
120#define PORT_MEM_MASK 0xff
121
122#define MT7530_VAWD2 0x98
123/* Egress Tag Control */
124#define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
125#define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
126
127enum mt7530_vlan_egress_attr {
128 MT7530_VLAN_EGRESS_UNTAG = 0,
129 MT7530_VLAN_EGRESS_TAG = 2,
130 MT7530_VLAN_EGRESS_STACK = 3,
131};
132
133/* Register for port STP state control */
134#define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
135#define FID_PST(x) ((x) & 0x3)
136#define FID_PST_MASK FID_PST(0x3)
137
138enum mt7530_stp_state {
139 MT7530_STP_DISABLED = 0,
140 MT7530_STP_BLOCKING = 1,
141 MT7530_STP_LISTENING = 1,
142 MT7530_STP_LEARNING = 2,
143 MT7530_STP_FORWARDING = 3
144};
145
146/* Register for port control */
147#define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
148#define PORT_TX_MIR BIT(9)
149#define PORT_RX_MIR BIT(8)
150#define PORT_VLAN(x) ((x) & 0x3)
151
152enum mt7530_port_mode {
153 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
154 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
155
156 /* Fallback Mode: Forward received frames with ingress ports that do
157 * not belong to the VLAN member. Frames whose VID is not listed on
158 * the VLAN table are forwarded by the PCR_MATRIX members.
159 */
160 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
161
162 /* Security Mode: Discard any frame due to ingress membership
163 * violation or VID missed on the VLAN table.
164 */
165 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
166};
167
168#define PCR_MATRIX(x) (((x) & 0xff) << 16)
169#define PORT_PRI(x) (((x) & 0x7) << 24)
170#define EG_TAG(x) (((x) & 0x3) << 28)
171#define PCR_MATRIX_MASK PCR_MATRIX(0xff)
172#define PCR_MATRIX_CLR PCR_MATRIX(0)
173#define PCR_PORT_VLAN_MASK PORT_VLAN(3)
174
175/* Register for port security control */
176#define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
177#define SA_DIS BIT(4)
178
179/* Register for port vlan control */
180#define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
181#define PORT_SPEC_TAG BIT(5)
182#define PVC_EG_TAG(x) (((x) & 0x7) << 8)
183#define PVC_EG_TAG_MASK PVC_EG_TAG(7)
184#define VLAN_ATTR(x) (((x) & 0x3) << 6)
185#define VLAN_ATTR_MASK VLAN_ATTR(3)
186
187enum mt7530_vlan_port_eg_tag {
188 MT7530_VLAN_EG_DISABLED = 0,
189 MT7530_VLAN_EG_CONSISTENT = 1,
190};
191
192enum mt7530_vlan_port_attr {
193 MT7530_VLAN_USER = 0,
194 MT7530_VLAN_TRANSPARENT = 3,
195};
196
197#define STAG_VPID (((x) & 0xffff) << 16)
198
199/* Register for port port-and-protocol based vlan 1 control */
200#define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
201#define G0_PORT_VID(x) (((x) & 0xfff) << 0)
202#define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
203#define G0_PORT_VID_DEF G0_PORT_VID(1)
204
205/* Register for port MAC control register */
206#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
207#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
208#define PMCR_EXT_PHY BIT(17)
209#define PMCR_MAC_MODE BIT(16)
210#define PMCR_FORCE_MODE BIT(15)
211#define PMCR_TX_EN BIT(14)
212#define PMCR_RX_EN BIT(13)
213#define PMCR_BACKOFF_EN BIT(9)
214#define PMCR_BACKPR_EN BIT(8)
215#define PMCR_TX_FC_EN BIT(5)
216#define PMCR_RX_FC_EN BIT(4)
217#define PMCR_FORCE_SPEED_1000 BIT(3)
218#define PMCR_FORCE_SPEED_100 BIT(2)
219#define PMCR_FORCE_FDX BIT(1)
220#define PMCR_FORCE_LNK BIT(0)
221#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
222 PMCR_FORCE_SPEED_1000)
223#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
224 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
225 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
226 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
227
228#define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
229#define PMSR_EEE1G BIT(7)
230#define PMSR_EEE100M BIT(6)
231#define PMSR_RX_FC BIT(5)
232#define PMSR_TX_FC BIT(4)
233#define PMSR_SPEED_1000 BIT(3)
234#define PMSR_SPEED_100 BIT(2)
235#define PMSR_SPEED_10 0x00
236#define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000)
237#define PMSR_DPX BIT(1)
238#define PMSR_LINK BIT(0)
239
240/* Register for MIB */
241#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
242#define MT7530_MIB_CCR 0x4fe0
243#define CCR_MIB_ENABLE BIT(31)
244#define CCR_RX_OCT_CNT_GOOD BIT(7)
245#define CCR_RX_OCT_CNT_BAD BIT(6)
246#define CCR_TX_OCT_CNT_GOOD BIT(5)
247#define CCR_TX_OCT_CNT_BAD BIT(4)
248#define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \
249 CCR_RX_OCT_CNT_BAD | \
250 CCR_TX_OCT_CNT_GOOD | \
251 CCR_TX_OCT_CNT_BAD)
252#define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \
253 CCR_RX_OCT_CNT_GOOD | \
254 CCR_RX_OCT_CNT_BAD | \
255 CCR_TX_OCT_CNT_GOOD | \
256 CCR_TX_OCT_CNT_BAD)
257/* Register for system reset */
258#define MT7530_SYS_CTRL 0x7000
259#define SYS_CTRL_PHY_RST BIT(2)
260#define SYS_CTRL_SW_RST BIT(1)
261#define SYS_CTRL_REG_RST BIT(0)
262
263/* Register for hw trap status */
264#define MT7530_HWTRAP 0x7800
265#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
266#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
267#define HWTRAP_XTAL_40MHZ (BIT(10))
268#define HWTRAP_XTAL_20MHZ (BIT(9))
269
270/* Register for hw trap modification */
271#define MT7530_MHWTRAP 0x7804
272#define MHWTRAP_PHY0_SEL BIT(20)
273#define MHWTRAP_MANUAL BIT(16)
274#define MHWTRAP_P5_MAC_SEL BIT(13)
275#define MHWTRAP_P6_DIS BIT(8)
276#define MHWTRAP_P5_RGMII_MODE BIT(7)
277#define MHWTRAP_P5_DIS BIT(6)
278#define MHWTRAP_PHY_ACCESS BIT(5)
279
280/* Register for TOP signal control */
281#define MT7530_TOP_SIG_CTRL 0x7808
282#define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
283
284#define MT7530_IO_DRV_CR 0x7810
285#define P5_IO_CLK_DRV(x) ((x) & 0x3)
286#define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
287
288#define MT7530_P6ECR 0x7830
289#define P6_INTF_MODE_MASK 0x3
290#define P6_INTF_MODE(x) ((x) & 0x3)
291
292/* Registers for TRGMII on the both side */
293#define MT7530_TRGMII_RCK_CTRL 0x7a00
294#define RX_RST BIT(31)
295#define RXC_DQSISEL BIT(30)
296#define DQSI1_TAP_MASK (0x7f << 8)
297#define DQSI0_TAP_MASK 0x7f
298#define DQSI1_TAP(x) (((x) & 0x7f) << 8)
299#define DQSI0_TAP(x) ((x) & 0x7f)
300
301#define MT7530_TRGMII_RCK_RTT 0x7a04
302#define DQS1_GATE BIT(31)
303#define DQS0_GATE BIT(30)
304
305#define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
306#define BSLIP_EN BIT(31)
307#define EDGE_CHK BIT(30)
308#define RD_TAP_MASK 0x7f
309#define RD_TAP(x) ((x) & 0x7f)
310
311#define MT7530_TRGMII_TXCTRL 0x7a40
312#define TRAIN_TXEN BIT(31)
313#define TXC_INV BIT(30)
314#define TX_RST BIT(28)
315
316#define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
317#define TD_DM_DRVP(x) ((x) & 0xf)
318#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
319
320#define MT7530_TRGMII_TCK_CTRL 0x7a78
321#define TCK_TAP(x) (((x) & 0xf) << 8)
322
323#define MT7530_P5RGMIIRXCR 0x7b00
324#define CSR_RGMII_EDGE_ALIGN BIT(8)
325#define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
326
327#define MT7530_P5RGMIITXCR 0x7b04
328#define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
329
330#define MT7530_CREV 0x7ffc
331#define CHIP_NAME_SHIFT 16
332#define MT7530_ID 0x7530
333
334/* Registers for core PLL access through mmd indirect */
335#define CORE_PLL_GROUP2 0x401
336#define RG_SYSPLL_EN_NORMAL BIT(15)
337#define RG_SYSPLL_VODEN BIT(14)
338#define RG_SYSPLL_LF BIT(13)
339#define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
340#define RG_SYSPLL_LVROD_EN BIT(10)
341#define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
342#define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
343#define RG_SYSPLL_FBKSEL BIT(4)
344#define RT_SYSPLL_EN_AFE_OLT BIT(0)
345
346#define CORE_PLL_GROUP4 0x403
347#define RG_SYSPLL_DDSFBK_EN BIT(12)
348#define RG_SYSPLL_BIAS_EN BIT(11)
349#define RG_SYSPLL_BIAS_LPF_EN BIT(10)
350
351#define CORE_PLL_GROUP5 0x404
352#define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
353
354#define CORE_PLL_GROUP6 0x405
355#define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
356
357#define CORE_PLL_GROUP7 0x406
358#define RG_LCDDS_PWDB BIT(15)
359#define RG_LCDDS_ISO_EN BIT(13)
360#define RG_LCCDS_C(x) (((x) & 0x7) << 4)
361#define RG_LCDDS_PCW_NCPO_CHG BIT(3)
362
363#define CORE_PLL_GROUP10 0x409
364#define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
365
366#define CORE_PLL_GROUP11 0x40a
367#define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
368
369#define CORE_GSWPLL_GRP1 0x40d
370#define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
371#define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
372#define RG_GSWPLL_EN_PRE BIT(11)
373#define RG_GSWPLL_FBKSEL BIT(10)
374#define RG_GSWPLL_BP BIT(9)
375#define RG_GSWPLL_BR BIT(8)
376#define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
377
378#define CORE_GSWPLL_GRP2 0x40e
379#define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
380#define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
381
382#define CORE_TRGMII_GSW_CLK_CG 0x410
383#define REG_GSWCK_EN BIT(0)
384#define REG_TRGMIICK_EN BIT(1)
385
386#define MIB_DESC(_s, _o, _n) \
387 { \
388 .size = (_s), \
389 .offset = (_o), \
390 .name = (_n), \
391 }
392
393struct mt7530_mib_desc {
394 unsigned int size;
395 unsigned int offset;
396 const char *name;
397};
398
399struct mt7530_fdb {
400 u16 vid;
401 u8 port_mask;
402 u8 aging;
403 u8 mac[6];
404 bool noarp;
405};
406
407/* struct mt7530_port - This is the main data structure for holding the state
408 * of the port.
409 * @enable: The status used for show port is enabled or not.
410 * @pm: The matrix used to show all connections with the port.
411 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
412 * untagged frames will be assigned to the related VLAN.
413 * @vlan_filtering: The flags indicating whether the port that can recognize
414 * VLAN-tagged frames.
415 */
416struct mt7530_port {
417 bool enable;
418 u32 pm;
419 u16 pvid;
420};
421
422/* Port 5 interface select definitions */
423enum p5_interface_select {
424 P5_DISABLED = 0,
425 P5_INTF_SEL_PHY_P0,
426 P5_INTF_SEL_PHY_P4,
427 P5_INTF_SEL_GMAC5,
428};
429
430static const char *p5_intf_modes(unsigned int p5_interface)
431{
432 switch (p5_interface) {
433 case P5_DISABLED:
434 return "DISABLED";
435 case P5_INTF_SEL_PHY_P0:
436 return "PHY P0";
437 case P5_INTF_SEL_PHY_P4:
438 return "PHY P4";
439 case P5_INTF_SEL_GMAC5:
440 return "GMAC5";
441 default:
442 return "unknown";
443 }
444}
445
446/* struct mt7530_priv - This is the main data structure for holding the state
447 * of the driver
448 * @dev: The device pointer
449 * @ds: The pointer to the dsa core structure
450 * @bus: The bus used for the device and built-in PHY
451 * @rstc: The pointer to reset control used by MCM
452 * @core_pwr: The power supplied into the core
453 * @io_pwr: The power supplied into the I/O
454 * @reset: The descriptor for GPIO line tied to its reset pin
455 * @mcm: Flag for distinguishing if standalone IC or module
456 * coupling
457 * @ports: Holding the state among ports
458 * @reg_mutex: The lock for protecting among process accessing
459 * registers
460 * @p6_interface Holding the current port 6 interface
461 * @p5_intf_sel: Holding the current port 5 interface select
462 */
463struct mt7530_priv {
464 struct device *dev;
465 struct dsa_switch *ds;
466 struct mii_bus *bus;
467 struct reset_control *rstc;
468 struct regulator *core_pwr;
469 struct regulator *io_pwr;
470 struct gpio_desc *reset;
471 unsigned int id;
472 bool mcm;
473 phy_interface_t p6_interface;
474 phy_interface_t p5_interface;
475 unsigned int p5_intf_sel;
476 u8 mirror_rx;
477 u8 mirror_tx;
478
479 struct mt7530_port ports[MT7530_NUM_PORTS];
480 /* protect among processes for registers access*/
481 struct mutex reg_mutex;
482};
483
484struct mt7530_hw_vlan_entry {
485 int port;
486 u8 old_members;
487 bool untagged;
488};
489
490static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
491 int port, bool untagged)
492{
493 e->port = port;
494 e->untagged = untagged;
495}
496
497typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
498 struct mt7530_hw_vlan_entry *);
499
500struct mt7530_hw_stats {
501 const char *string;
502 u16 reg;
503 u8 sizeof_stat;
504};
505
506struct mt7530_dummy_poll {
507 struct mt7530_priv *priv;
508 u32 reg;
509};
510
511static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
512 struct mt7530_priv *priv, u32 reg)
513{
514 p->priv = priv;
515 p->reg = reg;
516}
517
518#endif /* __MT7530_H */