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1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/slab.h>
27
28#include "dm_services.h"
29
30#include "link_encoder.h"
31#include "stream_encoder.h"
32
33#include "resource.h"
34#include "include/irq_service_interface.h"
35#include "../virtual/virtual_stream_encoder.h"
36#include "dce110/dce110_resource.h"
37#include "dce110/dce110_timing_generator.h"
38#include "irq/dce110/irq_service_dce110.h"
39#include "dce/dce_link_encoder.h"
40#include "dce/dce_stream_encoder.h"
41#include "dce/dce_mem_input.h"
42#include "dce/dce_ipp.h"
43#include "dce/dce_transform.h"
44#include "dce/dce_opp.h"
45#include "dce/dce_clock_source.h"
46#include "dce/dce_audio.h"
47#include "dce/dce_hwseq.h"
48#include "dce100/dce100_hw_sequencer.h"
49#include "dce/dce_panel_cntl.h"
50
51#include "reg_helper.h"
52
53#include "dce/dce_10_0_d.h"
54#include "dce/dce_10_0_sh_mask.h"
55
56#include "dce/dce_dmcu.h"
57#include "dce/dce_aux.h"
58#include "dce/dce_abm.h"
59#include "dce/dce_i2c.h"
60
61#ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
62#include "gmc/gmc_8_2_d.h"
63#include "gmc/gmc_8_2_sh_mask.h"
64#endif
65
66#ifndef mmDP_DPHY_INTERNAL_CTRL
67 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
68 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
69 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
70 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
71 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
72 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
73 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
74 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
75 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
76 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
77#endif
78
79#ifndef mmBIOS_SCRATCH_2
80 #define mmBIOS_SCRATCH_2 0x05CB
81 #define mmBIOS_SCRATCH_3 0x05CC
82 #define mmBIOS_SCRATCH_6 0x05CF
83#endif
84
85#ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
86 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
87 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
88 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
89 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
90 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
91 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
92 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
93 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
94#endif
95
96#ifndef mmDP_DPHY_FAST_TRAINING
97 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
98 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
99 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
100 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
101 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
102 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
103 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
104 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
105#endif
106
107static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
108 {
109 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
110 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
111 },
112 {
113 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
114 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
115 },
116 {
117 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
118 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
119 },
120 {
121 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
122 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
123 },
124 {
125 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
126 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
127 },
128 {
129 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
130 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
131 }
132};
133
134/* set register offset */
135#define SR(reg_name)\
136 .reg_name = mm ## reg_name
137
138/* set register offset with instance */
139#define SRI(reg_name, block, id)\
140 .reg_name = mm ## block ## id ## _ ## reg_name
141
142#define ipp_regs(id)\
143[id] = {\
144 IPP_DCE100_REG_LIST_DCE_BASE(id)\
145}
146
147static const struct dce_ipp_registers ipp_regs[] = {
148 ipp_regs(0),
149 ipp_regs(1),
150 ipp_regs(2),
151 ipp_regs(3),
152 ipp_regs(4),
153 ipp_regs(5)
154};
155
156static const struct dce_ipp_shift ipp_shift = {
157 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
158};
159
160static const struct dce_ipp_mask ipp_mask = {
161 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
162};
163
164#define transform_regs(id)\
165[id] = {\
166 XFM_COMMON_REG_LIST_DCE100(id)\
167}
168
169static const struct dce_transform_registers xfm_regs[] = {
170 transform_regs(0),
171 transform_regs(1),
172 transform_regs(2),
173 transform_regs(3),
174 transform_regs(4),
175 transform_regs(5)
176};
177
178static const struct dce_transform_shift xfm_shift = {
179 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
180};
181
182static const struct dce_transform_mask xfm_mask = {
183 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
184};
185
186#define aux_regs(id)\
187[id] = {\
188 AUX_REG_LIST(id)\
189}
190
191static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
192 aux_regs(0),
193 aux_regs(1),
194 aux_regs(2),
195 aux_regs(3),
196 aux_regs(4),
197 aux_regs(5)
198};
199
200#define hpd_regs(id)\
201[id] = {\
202 HPD_REG_LIST(id)\
203}
204
205static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
206 hpd_regs(0),
207 hpd_regs(1),
208 hpd_regs(2),
209 hpd_regs(3),
210 hpd_regs(4),
211 hpd_regs(5)
212};
213
214#define link_regs(id)\
215[id] = {\
216 LE_DCE100_REG_LIST(id)\
217}
218
219static const struct dce110_link_enc_registers link_enc_regs[] = {
220 link_regs(0),
221 link_regs(1),
222 link_regs(2),
223 link_regs(3),
224 link_regs(4),
225 link_regs(5),
226 link_regs(6),
227};
228
229#define stream_enc_regs(id)\
230[id] = {\
231 SE_COMMON_REG_LIST_DCE_BASE(id),\
232 .AFMT_CNTL = 0,\
233}
234
235static const struct dce110_stream_enc_registers stream_enc_regs[] = {
236 stream_enc_regs(0),
237 stream_enc_regs(1),
238 stream_enc_regs(2),
239 stream_enc_regs(3),
240 stream_enc_regs(4),
241 stream_enc_regs(5),
242 stream_enc_regs(6)
243};
244
245static const struct dce_stream_encoder_shift se_shift = {
246 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
247};
248
249static const struct dce_stream_encoder_mask se_mask = {
250 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
251};
252
253static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
254 { DCE_PANEL_CNTL_REG_LIST() }
255};
256
257static const struct dce_panel_cntl_shift panel_cntl_shift = {
258 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
259};
260
261static const struct dce_panel_cntl_mask panel_cntl_mask = {
262 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
263};
264
265#define opp_regs(id)\
266[id] = {\
267 OPP_DCE_100_REG_LIST(id),\
268}
269
270static const struct dce_opp_registers opp_regs[] = {
271 opp_regs(0),
272 opp_regs(1),
273 opp_regs(2),
274 opp_regs(3),
275 opp_regs(4),
276 opp_regs(5)
277};
278
279static const struct dce_opp_shift opp_shift = {
280 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT)
281};
282
283static const struct dce_opp_mask opp_mask = {
284 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
285};
286#define aux_engine_regs(id)\
287[id] = {\
288 AUX_COMMON_REG_LIST(id), \
289 .AUX_RESET_MASK = 0 \
290}
291
292static const struct dce110_aux_registers aux_engine_regs[] = {
293 aux_engine_regs(0),
294 aux_engine_regs(1),
295 aux_engine_regs(2),
296 aux_engine_regs(3),
297 aux_engine_regs(4),
298 aux_engine_regs(5)
299};
300
301#define audio_regs(id)\
302[id] = {\
303 AUD_COMMON_REG_LIST(id)\
304}
305
306static const struct dce_audio_registers audio_regs[] = {
307 audio_regs(0),
308 audio_regs(1),
309 audio_regs(2),
310 audio_regs(3),
311 audio_regs(4),
312 audio_regs(5),
313 audio_regs(6),
314};
315
316static const struct dce_audio_shift audio_shift = {
317 AUD_COMMON_MASK_SH_LIST(__SHIFT)
318};
319
320static const struct dce_audio_mask audio_mask = {
321 AUD_COMMON_MASK_SH_LIST(_MASK)
322};
323
324#define clk_src_regs(id)\
325[id] = {\
326 CS_COMMON_REG_LIST_DCE_100_110(id),\
327}
328
329static const struct dce110_clk_src_regs clk_src_regs[] = {
330 clk_src_regs(0),
331 clk_src_regs(1),
332 clk_src_regs(2)
333};
334
335static const struct dce110_clk_src_shift cs_shift = {
336 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
337};
338
339static const struct dce110_clk_src_mask cs_mask = {
340 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
341};
342
343static const struct dce_dmcu_registers dmcu_regs = {
344 DMCU_DCE110_COMMON_REG_LIST()
345};
346
347static const struct dce_dmcu_shift dmcu_shift = {
348 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
349};
350
351static const struct dce_dmcu_mask dmcu_mask = {
352 DMCU_MASK_SH_LIST_DCE110(_MASK)
353};
354
355static const struct dce_abm_registers abm_regs = {
356 ABM_DCE110_COMMON_REG_LIST()
357};
358
359static const struct dce_abm_shift abm_shift = {
360 ABM_MASK_SH_LIST_DCE110(__SHIFT)
361};
362
363static const struct dce_abm_mask abm_mask = {
364 ABM_MASK_SH_LIST_DCE110(_MASK)
365};
366
367#define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
368
369static const struct bios_registers bios_regs = {
370 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
371 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
372};
373
374static const struct resource_caps res_cap = {
375 .num_timing_generator = 6,
376 .num_audio = 6,
377 .num_stream_encoder = 6,
378 .num_pll = 3,
379 .num_ddc = 6,
380};
381
382static const struct dc_plane_cap plane_cap = {
383 .type = DC_PLANE_TYPE_DCE_RGB,
384
385 .pixel_format_support = {
386 .argb8888 = true,
387 .nv12 = false,
388 .fp16 = false
389 },
390
391 .max_upscale_factor = {
392 .argb8888 = 16000,
393 .nv12 = 1,
394 .fp16 = 1
395 },
396
397 .max_downscale_factor = {
398 .argb8888 = 250,
399 .nv12 = 1,
400 .fp16 = 1
401 }
402};
403
404#define CTX ctx
405#define REG(reg) mm ## reg
406
407#ifndef mmCC_DC_HDMI_STRAPS
408#define mmCC_DC_HDMI_STRAPS 0x1918
409#define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
410#define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
411#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
412#define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
413#endif
414
415static int map_transmitter_id_to_phy_instance(
416 enum transmitter transmitter)
417{
418 switch (transmitter) {
419 case TRANSMITTER_UNIPHY_A:
420 return 0;
421 break;
422 case TRANSMITTER_UNIPHY_B:
423 return 1;
424 break;
425 case TRANSMITTER_UNIPHY_C:
426 return 2;
427 break;
428 case TRANSMITTER_UNIPHY_D:
429 return 3;
430 break;
431 case TRANSMITTER_UNIPHY_E:
432 return 4;
433 break;
434 case TRANSMITTER_UNIPHY_F:
435 return 5;
436 break;
437 case TRANSMITTER_UNIPHY_G:
438 return 6;
439 break;
440 default:
441 ASSERT(0);
442 return 0;
443 }
444}
445
446static void read_dce_straps(
447 struct dc_context *ctx,
448 struct resource_straps *straps)
449{
450 REG_GET_2(CC_DC_HDMI_STRAPS,
451 HDMI_DISABLE, &straps->hdmi_disable,
452 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
453
454 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
455}
456
457static struct audio *create_audio(
458 struct dc_context *ctx, unsigned int inst)
459{
460 return dce_audio_create(ctx, inst,
461 &audio_regs[inst], &audio_shift, &audio_mask);
462}
463
464static struct timing_generator *dce100_timing_generator_create(
465 struct dc_context *ctx,
466 uint32_t instance,
467 const struct dce110_timing_generator_offsets *offsets)
468{
469 struct dce110_timing_generator *tg110 =
470 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
471
472 if (!tg110)
473 return NULL;
474
475 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
476 return &tg110->base;
477}
478
479static struct stream_encoder *dce100_stream_encoder_create(
480 enum engine_id eng_id,
481 struct dc_context *ctx)
482{
483 struct dce110_stream_encoder *enc110 =
484 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
485
486 if (!enc110)
487 return NULL;
488
489 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
490 &stream_enc_regs[eng_id], &se_shift, &se_mask);
491 return &enc110->base;
492}
493
494#define SRII(reg_name, block, id)\
495 .reg_name[id] = mm ## block ## id ## _ ## reg_name
496
497static const struct dce_hwseq_registers hwseq_reg = {
498 HWSEQ_DCE10_REG_LIST()
499};
500
501static const struct dce_hwseq_shift hwseq_shift = {
502 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT)
503};
504
505static const struct dce_hwseq_mask hwseq_mask = {
506 HWSEQ_DCE10_MASK_SH_LIST(_MASK)
507};
508
509static struct dce_hwseq *dce100_hwseq_create(
510 struct dc_context *ctx)
511{
512 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
513
514 if (hws) {
515 hws->ctx = ctx;
516 hws->regs = &hwseq_reg;
517 hws->shifts = &hwseq_shift;
518 hws->masks = &hwseq_mask;
519 }
520 return hws;
521}
522
523static const struct resource_create_funcs res_create_funcs = {
524 .read_dce_straps = read_dce_straps,
525 .create_audio = create_audio,
526 .create_stream_encoder = dce100_stream_encoder_create,
527 .create_hwseq = dce100_hwseq_create,
528};
529
530#define mi_inst_regs(id) { \
531 MI_DCE8_REG_LIST(id), \
532 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
533}
534static const struct dce_mem_input_registers mi_regs[] = {
535 mi_inst_regs(0),
536 mi_inst_regs(1),
537 mi_inst_regs(2),
538 mi_inst_regs(3),
539 mi_inst_regs(4),
540 mi_inst_regs(5),
541};
542
543static const struct dce_mem_input_shift mi_shifts = {
544 MI_DCE8_MASK_SH_LIST(__SHIFT),
545 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
546};
547
548static const struct dce_mem_input_mask mi_masks = {
549 MI_DCE8_MASK_SH_LIST(_MASK),
550 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
551};
552
553static const struct dce110_aux_registers_shift aux_shift = {
554 DCE10_AUX_MASK_SH_LIST(__SHIFT)
555};
556
557static const struct dce110_aux_registers_mask aux_mask = {
558 DCE10_AUX_MASK_SH_LIST(_MASK)
559};
560
561static struct mem_input *dce100_mem_input_create(
562 struct dc_context *ctx,
563 uint32_t inst)
564{
565 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
566 GFP_KERNEL);
567
568 if (!dce_mi) {
569 BREAK_TO_DEBUGGER();
570 return NULL;
571 }
572
573 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
574 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
575 return &dce_mi->base;
576}
577
578static void dce100_transform_destroy(struct transform **xfm)
579{
580 kfree(TO_DCE_TRANSFORM(*xfm));
581 *xfm = NULL;
582}
583
584static struct transform *dce100_transform_create(
585 struct dc_context *ctx,
586 uint32_t inst)
587{
588 struct dce_transform *transform =
589 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
590
591 if (!transform)
592 return NULL;
593
594 dce_transform_construct(transform, ctx, inst,
595 &xfm_regs[inst], &xfm_shift, &xfm_mask);
596 return &transform->base;
597}
598
599static struct input_pixel_processor *dce100_ipp_create(
600 struct dc_context *ctx, uint32_t inst)
601{
602 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
603
604 if (!ipp) {
605 BREAK_TO_DEBUGGER();
606 return NULL;
607 }
608
609 dce_ipp_construct(ipp, ctx, inst,
610 &ipp_regs[inst], &ipp_shift, &ipp_mask);
611 return &ipp->base;
612}
613
614static const struct encoder_feature_support link_enc_feature = {
615 .max_hdmi_deep_color = COLOR_DEPTH_121212,
616 .max_hdmi_pixel_clock = 300000,
617 .flags.bits.IS_HBR2_CAPABLE = true,
618 .flags.bits.IS_TPS3_CAPABLE = true
619};
620
621struct link_encoder *dce100_link_encoder_create(
622 const struct encoder_init_data *enc_init_data)
623{
624 struct dce110_link_encoder *enc110 =
625 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
626 int link_regs_id;
627
628 if (!enc110)
629 return NULL;
630
631 link_regs_id =
632 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
633
634 dce110_link_encoder_construct(enc110,
635 enc_init_data,
636 &link_enc_feature,
637 &link_enc_regs[link_regs_id],
638 &link_enc_aux_regs[enc_init_data->channel - 1],
639 &link_enc_hpd_regs[enc_init_data->hpd_source]);
640 return &enc110->base;
641}
642
643static struct panel_cntl *dce100_panel_cntl_create(const struct panel_cntl_init_data *init_data)
644{
645 struct dce_panel_cntl *panel_cntl =
646 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
647
648 if (!panel_cntl)
649 return NULL;
650
651 dce_panel_cntl_construct(panel_cntl,
652 init_data,
653 &panel_cntl_regs[init_data->inst],
654 &panel_cntl_shift,
655 &panel_cntl_mask);
656
657 return &panel_cntl->base;
658}
659
660struct output_pixel_processor *dce100_opp_create(
661 struct dc_context *ctx,
662 uint32_t inst)
663{
664 struct dce110_opp *opp =
665 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
666
667 if (!opp)
668 return NULL;
669
670 dce110_opp_construct(opp,
671 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
672 return &opp->base;
673}
674
675struct dce_aux *dce100_aux_engine_create(
676 struct dc_context *ctx,
677 uint32_t inst)
678{
679 struct aux_engine_dce110 *aux_engine =
680 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
681
682 if (!aux_engine)
683 return NULL;
684
685 dce110_aux_engine_construct(aux_engine, ctx, inst,
686 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
687 &aux_engine_regs[inst],
688 &aux_mask,
689 &aux_shift,
690 ctx->dc->caps.extended_aux_timeout_support);
691
692 return &aux_engine->base;
693}
694#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
695
696static const struct dce_i2c_registers i2c_hw_regs[] = {
697 i2c_inst_regs(1),
698 i2c_inst_regs(2),
699 i2c_inst_regs(3),
700 i2c_inst_regs(4),
701 i2c_inst_regs(5),
702 i2c_inst_regs(6),
703};
704
705static const struct dce_i2c_shift i2c_shifts = {
706 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
707};
708
709static const struct dce_i2c_mask i2c_masks = {
710 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
711};
712
713struct dce_i2c_hw *dce100_i2c_hw_create(
714 struct dc_context *ctx,
715 uint32_t inst)
716{
717 struct dce_i2c_hw *dce_i2c_hw =
718 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
719
720 if (!dce_i2c_hw)
721 return NULL;
722
723 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
724 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
725
726 return dce_i2c_hw;
727}
728struct clock_source *dce100_clock_source_create(
729 struct dc_context *ctx,
730 struct dc_bios *bios,
731 enum clock_source_id id,
732 const struct dce110_clk_src_regs *regs,
733 bool dp_clk_src)
734{
735 struct dce110_clk_src *clk_src =
736 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
737
738 if (!clk_src)
739 return NULL;
740
741 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
742 regs, &cs_shift, &cs_mask)) {
743 clk_src->base.dp_clk_src = dp_clk_src;
744 return &clk_src->base;
745 }
746
747 kfree(clk_src);
748 BREAK_TO_DEBUGGER();
749 return NULL;
750}
751
752void dce100_clock_source_destroy(struct clock_source **clk_src)
753{
754 kfree(TO_DCE110_CLK_SRC(*clk_src));
755 *clk_src = NULL;
756}
757
758static void dce100_resource_destruct(struct dce110_resource_pool *pool)
759{
760 unsigned int i;
761
762 for (i = 0; i < pool->base.pipe_count; i++) {
763 if (pool->base.opps[i] != NULL)
764 dce110_opp_destroy(&pool->base.opps[i]);
765
766 if (pool->base.transforms[i] != NULL)
767 dce100_transform_destroy(&pool->base.transforms[i]);
768
769 if (pool->base.ipps[i] != NULL)
770 dce_ipp_destroy(&pool->base.ipps[i]);
771
772 if (pool->base.mis[i] != NULL) {
773 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
774 pool->base.mis[i] = NULL;
775 }
776
777 if (pool->base.timing_generators[i] != NULL) {
778 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
779 pool->base.timing_generators[i] = NULL;
780 }
781 }
782
783 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
784 if (pool->base.engines[i] != NULL)
785 dce110_engine_destroy(&pool->base.engines[i]);
786 if (pool->base.hw_i2cs[i] != NULL) {
787 kfree(pool->base.hw_i2cs[i]);
788 pool->base.hw_i2cs[i] = NULL;
789 }
790 if (pool->base.sw_i2cs[i] != NULL) {
791 kfree(pool->base.sw_i2cs[i]);
792 pool->base.sw_i2cs[i] = NULL;
793 }
794 }
795
796 for (i = 0; i < pool->base.stream_enc_count; i++) {
797 if (pool->base.stream_enc[i] != NULL)
798 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
799 }
800
801 for (i = 0; i < pool->base.clk_src_count; i++) {
802 if (pool->base.clock_sources[i] != NULL)
803 dce100_clock_source_destroy(&pool->base.clock_sources[i]);
804 }
805
806 if (pool->base.dp_clock_source != NULL)
807 dce100_clock_source_destroy(&pool->base.dp_clock_source);
808
809 for (i = 0; i < pool->base.audio_count; i++) {
810 if (pool->base.audios[i] != NULL)
811 dce_aud_destroy(&pool->base.audios[i]);
812 }
813
814 if (pool->base.abm != NULL)
815 dce_abm_destroy(&pool->base.abm);
816
817 if (pool->base.dmcu != NULL)
818 dce_dmcu_destroy(&pool->base.dmcu);
819
820 if (pool->base.irqs != NULL)
821 dal_irq_service_destroy(&pool->base.irqs);
822}
823
824static enum dc_status build_mapped_resource(
825 const struct dc *dc,
826 struct dc_state *context,
827 struct dc_stream_state *stream)
828{
829 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
830
831 if (!pipe_ctx)
832 return DC_ERROR_UNEXPECTED;
833
834 dce110_resource_build_pipe_hw_param(pipe_ctx);
835
836 resource_build_info_frame(pipe_ctx);
837
838 return DC_OK;
839}
840
841bool dce100_validate_bandwidth(
842 struct dc *dc,
843 struct dc_state *context,
844 bool fast_validate)
845{
846 int i;
847 bool at_least_one_pipe = false;
848
849 for (i = 0; i < dc->res_pool->pipe_count; i++) {
850 if (context->res_ctx.pipe_ctx[i].stream)
851 at_least_one_pipe = true;
852 }
853
854 if (at_least_one_pipe) {
855 /* TODO implement when needed but for now hardcode max value*/
856 context->bw_ctx.bw.dce.dispclk_khz = 681000;
857 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
858 } else {
859 context->bw_ctx.bw.dce.dispclk_khz = 0;
860 context->bw_ctx.bw.dce.yclk_khz = 0;
861 }
862
863 return true;
864}
865
866static bool dce100_validate_surface_sets(
867 struct dc_state *context)
868{
869 int i;
870
871 for (i = 0; i < context->stream_count; i++) {
872 if (context->stream_status[i].plane_count == 0)
873 continue;
874
875 if (context->stream_status[i].plane_count > 1)
876 return false;
877
878 if (context->stream_status[i].plane_states[0]->format
879 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
880 return false;
881 }
882
883 return true;
884}
885
886enum dc_status dce100_validate_global(
887 struct dc *dc,
888 struct dc_state *context)
889{
890 if (!dce100_validate_surface_sets(context))
891 return DC_FAIL_SURFACE_VALIDATE;
892
893 return DC_OK;
894}
895
896enum dc_status dce100_add_stream_to_ctx(
897 struct dc *dc,
898 struct dc_state *new_ctx,
899 struct dc_stream_state *dc_stream)
900{
901 enum dc_status result = DC_ERROR_UNEXPECTED;
902
903 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
904
905 if (result == DC_OK)
906 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
907
908 if (result == DC_OK)
909 result = build_mapped_resource(dc, new_ctx, dc_stream);
910
911 return result;
912}
913
914static void dce100_destroy_resource_pool(struct resource_pool **pool)
915{
916 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
917
918 dce100_resource_destruct(dce110_pool);
919 kfree(dce110_pool);
920 *pool = NULL;
921}
922
923enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
924{
925
926 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
927 return DC_OK;
928
929 return DC_FAIL_SURFACE_VALIDATE;
930}
931
932struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(
933 struct resource_context *res_ctx,
934 const struct resource_pool *pool,
935 struct dc_stream_state *stream)
936{
937 int i;
938 int j = -1;
939 struct dc_link *link = stream->link;
940
941 for (i = 0; i < pool->stream_enc_count; i++) {
942 if (!res_ctx->is_stream_enc_acquired[i] &&
943 pool->stream_enc[i]) {
944 /* Store first available for MST second display
945 * in daisy chain use case
946 */
947 j = i;
948 if (pool->stream_enc[i]->id ==
949 link->link_enc->preferred_engine)
950 return pool->stream_enc[i];
951 }
952 }
953
954 /*
955 * below can happen in cases when stream encoder is acquired:
956 * 1) for second MST display in chain, so preferred engine already
957 * acquired;
958 * 2) for another link, which preferred engine already acquired by any
959 * MST configuration.
960 *
961 * If signal is of DP type and preferred engine not found, return last available
962 *
963 * TODO - This is just a patch up and a generic solution is
964 * required for non DP connectors.
965 */
966
967 if (j >= 0 && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT)
968 return pool->stream_enc[j];
969
970 return NULL;
971}
972
973static const struct resource_funcs dce100_res_pool_funcs = {
974 .destroy = dce100_destroy_resource_pool,
975 .link_enc_create = dce100_link_encoder_create,
976 .panel_cntl_create = dce100_panel_cntl_create,
977 .validate_bandwidth = dce100_validate_bandwidth,
978 .validate_plane = dce100_validate_plane,
979 .add_stream_to_ctx = dce100_add_stream_to_ctx,
980 .validate_global = dce100_validate_global,
981 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
982};
983
984static bool dce100_resource_construct(
985 uint8_t num_virtual_links,
986 struct dc *dc,
987 struct dce110_resource_pool *pool)
988{
989 unsigned int i;
990 struct dc_context *ctx = dc->ctx;
991 struct dc_bios *bp;
992
993 ctx->dc_bios->regs = &bios_regs;
994
995 pool->base.res_cap = &res_cap;
996 pool->base.funcs = &dce100_res_pool_funcs;
997 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
998
999 bp = ctx->dc_bios;
1000
1001 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
1002 pool->base.dp_clock_source =
1003 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1004
1005 pool->base.clock_sources[0] =
1006 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1007 pool->base.clock_sources[1] =
1008 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1009 pool->base.clock_sources[2] =
1010 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1011 pool->base.clk_src_count = 3;
1012
1013 } else {
1014 pool->base.dp_clock_source =
1015 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1016
1017 pool->base.clock_sources[0] =
1018 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1019 pool->base.clock_sources[1] =
1020 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1021 pool->base.clk_src_count = 2;
1022 }
1023
1024 if (pool->base.dp_clock_source == NULL) {
1025 dm_error("DC: failed to create dp clock source!\n");
1026 BREAK_TO_DEBUGGER();
1027 goto res_create_fail;
1028 }
1029
1030 for (i = 0; i < pool->base.clk_src_count; i++) {
1031 if (pool->base.clock_sources[i] == NULL) {
1032 dm_error("DC: failed to create clock sources!\n");
1033 BREAK_TO_DEBUGGER();
1034 goto res_create_fail;
1035 }
1036 }
1037
1038 pool->base.dmcu = dce_dmcu_create(ctx,
1039 &dmcu_regs,
1040 &dmcu_shift,
1041 &dmcu_mask);
1042 if (pool->base.dmcu == NULL) {
1043 dm_error("DC: failed to create dmcu!\n");
1044 BREAK_TO_DEBUGGER();
1045 goto res_create_fail;
1046 }
1047
1048 pool->base.abm = dce_abm_create(ctx,
1049 &abm_regs,
1050 &abm_shift,
1051 &abm_mask);
1052 if (pool->base.abm == NULL) {
1053 dm_error("DC: failed to create abm!\n");
1054 BREAK_TO_DEBUGGER();
1055 goto res_create_fail;
1056 }
1057
1058 {
1059 struct irq_service_init_data init_data;
1060 init_data.ctx = dc->ctx;
1061 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1062 if (!pool->base.irqs)
1063 goto res_create_fail;
1064 }
1065
1066 /*************************************************
1067 * Resource + asic cap harcoding *
1068 *************************************************/
1069 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1070 pool->base.pipe_count = res_cap.num_timing_generator;
1071 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1072 dc->caps.max_downscale_ratio = 200;
1073 dc->caps.i2c_speed_in_khz = 40;
1074 dc->caps.max_cursor_size = 128;
1075 dc->caps.dual_link_dvi = true;
1076 dc->caps.disable_dp_clk_share = true;
1077 dc->caps.extended_aux_timeout_support = false;
1078
1079 for (i = 0; i < pool->base.pipe_count; i++) {
1080 pool->base.timing_generators[i] =
1081 dce100_timing_generator_create(
1082 ctx,
1083 i,
1084 &dce100_tg_offsets[i]);
1085 if (pool->base.timing_generators[i] == NULL) {
1086 BREAK_TO_DEBUGGER();
1087 dm_error("DC: failed to create tg!\n");
1088 goto res_create_fail;
1089 }
1090
1091 pool->base.mis[i] = dce100_mem_input_create(ctx, i);
1092 if (pool->base.mis[i] == NULL) {
1093 BREAK_TO_DEBUGGER();
1094 dm_error(
1095 "DC: failed to create memory input!\n");
1096 goto res_create_fail;
1097 }
1098
1099 pool->base.ipps[i] = dce100_ipp_create(ctx, i);
1100 if (pool->base.ipps[i] == NULL) {
1101 BREAK_TO_DEBUGGER();
1102 dm_error(
1103 "DC: failed to create input pixel processor!\n");
1104 goto res_create_fail;
1105 }
1106
1107 pool->base.transforms[i] = dce100_transform_create(ctx, i);
1108 if (pool->base.transforms[i] == NULL) {
1109 BREAK_TO_DEBUGGER();
1110 dm_error(
1111 "DC: failed to create transform!\n");
1112 goto res_create_fail;
1113 }
1114
1115 pool->base.opps[i] = dce100_opp_create(ctx, i);
1116 if (pool->base.opps[i] == NULL) {
1117 BREAK_TO_DEBUGGER();
1118 dm_error(
1119 "DC: failed to create output pixel processor!\n");
1120 goto res_create_fail;
1121 }
1122 }
1123
1124 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1125 pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
1126 if (pool->base.engines[i] == NULL) {
1127 BREAK_TO_DEBUGGER();
1128 dm_error(
1129 "DC:failed to create aux engine!!\n");
1130 goto res_create_fail;
1131 }
1132 pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i);
1133 if (pool->base.hw_i2cs[i] == NULL) {
1134 BREAK_TO_DEBUGGER();
1135 dm_error(
1136 "DC:failed to create i2c engine!!\n");
1137 goto res_create_fail;
1138 }
1139 pool->base.sw_i2cs[i] = NULL;
1140 }
1141
1142 dc->caps.max_planes = pool->base.pipe_count;
1143
1144 for (i = 0; i < dc->caps.max_planes; ++i)
1145 dc->caps.planes[i] = plane_cap;
1146
1147 if (!resource_construct(num_virtual_links, dc, &pool->base,
1148 &res_create_funcs))
1149 goto res_create_fail;
1150
1151 /* Create hardware sequencer */
1152 dce100_hw_sequencer_construct(dc);
1153 return true;
1154
1155res_create_fail:
1156 dce100_resource_destruct(pool);
1157
1158 return false;
1159}
1160
1161struct resource_pool *dce100_create_resource_pool(
1162 uint8_t num_virtual_links,
1163 struct dc *dc)
1164{
1165 struct dce110_resource_pool *pool =
1166 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1167
1168 if (!pool)
1169 return NULL;
1170
1171 if (dce100_resource_construct(num_virtual_links, dc, pool))
1172 return &pool->base;
1173
1174 kfree(pool);
1175 BREAK_TO_DEBUGGER();
1176 return NULL;
1177}
1178