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1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "reg_helper.h"
27#include "dce_audio.h"
28#include "dce/dce_11_0_d.h"
29#include "dce/dce_11_0_sh_mask.h"
30
31#define DCE_AUD(audio)\
32 container_of(audio, struct dce_audio, base)
33
34#define CTX \
35 aud->base.ctx
36
37#define DC_LOGGER_INIT()
38
39#define REG(reg)\
40 (aud->regs->reg)
41
42#undef FN
43#define FN(reg_name, field_name) \
44 aud->shifts->field_name, aud->masks->field_name
45
46#define IX_REG(reg)\
47 ix ## reg
48
49#define AZ_REG_READ(reg_name) \
50 read_indirect_azalia_reg(audio, IX_REG(reg_name))
51
52#define AZ_REG_WRITE(reg_name, value) \
53 write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
54
55static void write_indirect_azalia_reg(struct audio *audio,
56 uint32_t reg_index,
57 uint32_t reg_data)
58{
59 struct dce_audio *aud = DCE_AUD(audio);
60
61 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
62 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
63 AZALIA_ENDPOINT_REG_INDEX, reg_index);
64
65 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
66 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
67 AZALIA_ENDPOINT_REG_DATA, reg_data);
68}
69
70static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)
71{
72 struct dce_audio *aud = DCE_AUD(audio);
73
74 uint32_t value = 0;
75
76 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
77 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
78 AZALIA_ENDPOINT_REG_INDEX, reg_index);
79
80 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
81 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
82
83 return value;
84}
85
86static bool is_audio_format_supported(
87 const struct audio_info *audio_info,
88 enum audio_format_code audio_format_code,
89 uint32_t *format_index)
90{
91 uint32_t index;
92 uint32_t max_channe_index = 0;
93 bool found = false;
94
95 if (audio_info == NULL)
96 return found;
97
98 /* pass through whole array */
99 for (index = 0; index < audio_info->mode_count; index++) {
100 if (audio_info->modes[index].format_code == audio_format_code) {
101 if (found) {
102 /* format has multiply entries, choose one with
103 * highst number of channels */
104 if (audio_info->modes[index].channel_count >
105 audio_info->modes[max_channe_index].channel_count) {
106 max_channe_index = index;
107 }
108 } else {
109 /* format found, save it's index */
110 found = true;
111 max_channe_index = index;
112 }
113 }
114 }
115
116 /* return index */
117 if (found && format_index != NULL)
118 *format_index = max_channe_index;
119
120 return found;
121}
122
123/*For HDMI, calculate if specified sample rates can fit into a given timing */
124static void check_audio_bandwidth_hdmi(
125 const struct audio_crtc_info *crtc_info,
126 uint32_t channel_count,
127 union audio_sample_rates *sample_rates)
128{
129 uint32_t samples;
130 uint32_t h_blank;
131 bool limit_freq_to_48_khz = false;
132 bool limit_freq_to_88_2_khz = false;
133 bool limit_freq_to_96_khz = false;
134 bool limit_freq_to_174_4_khz = false;
135 if (!crtc_info)
136 return;
137
138 /* For two channels supported return whatever sink support,unmodified*/
139 if (channel_count > 2) {
140
141 /* Based on HDMI spec 1.3 Table 7.5 */
142 if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
143 (crtc_info->v_active <= 576) &&
144 !(crtc_info->interlaced) &&
145 !(crtc_info->pixel_repetition == 2 ||
146 crtc_info->pixel_repetition == 4)) {
147 limit_freq_to_48_khz = true;
148
149 } else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
150 (crtc_info->v_active <= 576) &&
151 (crtc_info->interlaced) &&
152 (crtc_info->pixel_repetition == 2)) {
153 limit_freq_to_88_2_khz = true;
154
155 } else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) &&
156 (crtc_info->v_active <= 576) &&
157 !(crtc_info->interlaced)) {
158 limit_freq_to_174_4_khz = true;
159 }
160 }
161
162 /* Also do some calculation for the available Audio Bandwidth for the
163 * 8 ch (i.e. for the Layout 1 => ch > 2)
164 */
165 h_blank = crtc_info->h_total - crtc_info->h_active;
166
167 if (crtc_info->pixel_repetition)
168 h_blank *= crtc_info->pixel_repetition;
169
170 /*based on HDMI spec 1.3 Table 7.5 */
171 h_blank -= 58;
172 /*for Control Period */
173 h_blank -= 16;
174
175 samples = h_blank * 10;
176 /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
177 * of Audio samples per line multiplied by 10 - Layout 1)
178 */
179 samples /= 32;
180 samples *= crtc_info->v_active;
181 /*Number of samples multiplied by 10, per second */
182 samples *= crtc_info->refresh_rate;
183 /*Number of Audio samples per second */
184 samples /= 10;
185
186 /* @todo do it after deep color is implemented
187 * 8xx - deep color bandwidth scaling
188 * Extra bandwidth is avaliable in deep color b/c link runs faster than
189 * pixel rate. This has the effect of allowing more tmds characters to
190 * be transmitted during blank
191 */
192
193 switch (crtc_info->color_depth) {
194 case COLOR_DEPTH_888:
195 samples *= 4;
196 break;
197 case COLOR_DEPTH_101010:
198 samples *= 5;
199 break;
200 case COLOR_DEPTH_121212:
201 samples *= 6;
202 break;
203 default:
204 samples *= 4;
205 break;
206 }
207
208 samples /= 4;
209
210 /*check limitation*/
211 if (samples < 88200)
212 limit_freq_to_48_khz = true;
213 else if (samples < 96000)
214 limit_freq_to_88_2_khz = true;
215 else if (samples < 176400)
216 limit_freq_to_96_khz = true;
217 else if (samples < 192000)
218 limit_freq_to_174_4_khz = true;
219
220 if (sample_rates != NULL) {
221 /* limit frequencies */
222 if (limit_freq_to_174_4_khz)
223 sample_rates->rate.RATE_192 = 0;
224
225 if (limit_freq_to_96_khz) {
226 sample_rates->rate.RATE_192 = 0;
227 sample_rates->rate.RATE_176_4 = 0;
228 }
229 if (limit_freq_to_88_2_khz) {
230 sample_rates->rate.RATE_192 = 0;
231 sample_rates->rate.RATE_176_4 = 0;
232 sample_rates->rate.RATE_96 = 0;
233 }
234 if (limit_freq_to_48_khz) {
235 sample_rates->rate.RATE_192 = 0;
236 sample_rates->rate.RATE_176_4 = 0;
237 sample_rates->rate.RATE_96 = 0;
238 sample_rates->rate.RATE_88_2 = 0;
239 }
240 }
241}
242static struct fixed31_32 get_link_symbol_clk_freq_mhz(enum dc_link_rate link_rate)
243{
244 switch (link_rate) {
245 case LINK_RATE_LOW:
246 return dc_fixpt_from_int(162); /* 162 MHz */
247 case LINK_RATE_HIGH:
248 return dc_fixpt_from_int(270); /* 270 MHz */
249 case LINK_RATE_HIGH2:
250 return dc_fixpt_from_int(540); /* 540 MHz */
251 case LINK_RATE_HIGH3:
252 return dc_fixpt_from_int(810); /* 810 MHz */
253 case LINK_RATE_UHBR10:
254 return dc_fixpt_from_fraction(3125, 10); /* 312.5 MHz */
255 case LINK_RATE_UHBR13_5:
256 return dc_fixpt_from_fraction(421875, 1000); /* 421.875 MHz */
257 case LINK_RATE_UHBR20:
258 return dc_fixpt_from_int(625); /* 625 MHz */
259 default:
260 /* Unexpected case, this requires debug if encountered. */
261 ASSERT(0);
262 return dc_fixpt_from_int(0);
263 }
264}
265
266struct dp_audio_layout_config {
267 uint8_t layouts_per_sample_denom;
268 uint8_t symbols_per_layout;
269 uint8_t max_layouts_per_audio_sdp;
270};
271
272static void get_audio_layout_config(
273 uint32_t channel_count,
274 enum dp_link_encoding encoding,
275 struct dp_audio_layout_config *output)
276{
277 /* Assuming L-PCM audio. Current implementation uses max 1 layout per SDP,
278 * with each layout being the same size (8ch layout).
279 */
280 if (encoding == DP_8b_10b_ENCODING) {
281 if (channel_count == 2) {
282 output->layouts_per_sample_denom = 4;
283 output->symbols_per_layout = 40;
284 output->max_layouts_per_audio_sdp = 1;
285 } else if (channel_count == 8 || channel_count == 6) {
286 output->layouts_per_sample_denom = 1;
287 output->symbols_per_layout = 40;
288 output->max_layouts_per_audio_sdp = 1;
289 }
290 } else if (encoding == DP_128b_132b_ENCODING) {
291 if (channel_count == 2) {
292 output->layouts_per_sample_denom = 4;
293 output->symbols_per_layout = 10;
294 output->max_layouts_per_audio_sdp = 1;
295 } else if (channel_count == 8 || channel_count == 6) {
296 output->layouts_per_sample_denom = 1;
297 output->symbols_per_layout = 10;
298 output->max_layouts_per_audio_sdp = 1;
299 }
300 }
301}
302
303static uint32_t get_av_stream_map_lane_count(
304 enum dp_link_encoding encoding,
305 enum dc_lane_count lane_count,
306 bool is_mst)
307{
308 uint32_t av_stream_map_lane_count = 0;
309
310 if (encoding == DP_8b_10b_ENCODING) {
311 if (!is_mst)
312 av_stream_map_lane_count = lane_count;
313 else
314 av_stream_map_lane_count = 4;
315 } else if (encoding == DP_128b_132b_ENCODING) {
316 av_stream_map_lane_count = 4;
317 }
318
319 ASSERT(av_stream_map_lane_count != 0);
320
321 return av_stream_map_lane_count;
322}
323
324static uint32_t get_audio_sdp_overhead(
325 enum dp_link_encoding encoding,
326 enum dc_lane_count lane_count,
327 bool is_mst)
328{
329 uint32_t audio_sdp_overhead = 0;
330
331 if (encoding == DP_8b_10b_ENCODING) {
332 if (is_mst)
333 audio_sdp_overhead = 16; /* 4 * 2 + 8 */
334 else
335 audio_sdp_overhead = lane_count * 2 + 8;
336 } else if (encoding == DP_128b_132b_ENCODING) {
337 audio_sdp_overhead = 10; /* 4 x 2.5 */
338 }
339
340 ASSERT(audio_sdp_overhead != 0);
341
342 return audio_sdp_overhead;
343}
344
345static uint32_t calculate_required_audio_bw_in_symbols(
346 const struct audio_crtc_info *crtc_info,
347 const struct dp_audio_layout_config *layout_config,
348 uint32_t channel_count,
349 uint32_t sample_rate_hz,
350 uint32_t av_stream_map_lane_count,
351 uint32_t audio_sdp_overhead)
352{
353 /* DP spec recommends between 1.05 to 1.1 safety margin to prevent sample under-run */
354 struct fixed31_32 audio_sdp_margin = dc_fixpt_from_fraction(110, 100);
355 struct fixed31_32 horizontal_line_freq_khz = dc_fixpt_from_fraction(
356 crtc_info->requested_pixel_clock_100Hz, crtc_info->h_total * 10);
357 struct fixed31_32 samples_per_line;
358 struct fixed31_32 layouts_per_line;
359 struct fixed31_32 symbols_per_sdp_max_layout;
360 struct fixed31_32 remainder;
361 uint32_t num_sdp_with_max_layouts;
362 uint32_t required_symbols_per_hblank;
363
364 samples_per_line = dc_fixpt_from_fraction(sample_rate_hz, 1000);
365 samples_per_line = dc_fixpt_div(samples_per_line, horizontal_line_freq_khz);
366 layouts_per_line = dc_fixpt_div_int(samples_per_line, layout_config->layouts_per_sample_denom);
367
368 num_sdp_with_max_layouts = dc_fixpt_floor(
369 dc_fixpt_div_int(layouts_per_line, layout_config->max_layouts_per_audio_sdp));
370 symbols_per_sdp_max_layout = dc_fixpt_from_int(
371 layout_config->max_layouts_per_audio_sdp * layout_config->symbols_per_layout);
372 symbols_per_sdp_max_layout = dc_fixpt_add_int(symbols_per_sdp_max_layout, audio_sdp_overhead);
373 symbols_per_sdp_max_layout = dc_fixpt_mul(symbols_per_sdp_max_layout, audio_sdp_margin);
374 required_symbols_per_hblank = num_sdp_with_max_layouts;
375 required_symbols_per_hblank *= ((dc_fixpt_ceil(symbols_per_sdp_max_layout) + av_stream_map_lane_count) /
376 av_stream_map_lane_count) * av_stream_map_lane_count;
377
378 if (num_sdp_with_max_layouts != dc_fixpt_ceil(
379 dc_fixpt_div_int(layouts_per_line, layout_config->max_layouts_per_audio_sdp))) {
380 remainder = dc_fixpt_sub_int(layouts_per_line,
381 num_sdp_with_max_layouts * layout_config->max_layouts_per_audio_sdp);
382 remainder = dc_fixpt_mul_int(remainder, layout_config->symbols_per_layout);
383 remainder = dc_fixpt_add_int(remainder, audio_sdp_overhead);
384 remainder = dc_fixpt_mul(remainder, audio_sdp_margin);
385 required_symbols_per_hblank += ((dc_fixpt_ceil(remainder) + av_stream_map_lane_count) /
386 av_stream_map_lane_count) * av_stream_map_lane_count;
387 }
388
389 return required_symbols_per_hblank;
390}
391
392/* Current calculation only applicable for 8b/10b MST and 128b/132b SST/MST.
393 */
394static uint32_t calculate_available_hblank_bw_in_symbols(
395 const struct audio_crtc_info *crtc_info,
396 const struct audio_dp_link_info *dp_link_info)
397{
398 uint64_t hblank = crtc_info->h_total - crtc_info->h_active;
399 struct fixed31_32 hblank_time_msec =
400 dc_fixpt_from_fraction(hblank * 10, crtc_info->requested_pixel_clock_100Hz);
401 struct fixed31_32 lsclkfreq_mhz =
402 get_link_symbol_clk_freq_mhz(dp_link_info->link_rate);
403 struct fixed31_32 average_stream_sym_bw_frac;
404 struct fixed31_32 peak_stream_bw_kbps;
405 struct fixed31_32 bits_per_pixel;
406 struct fixed31_32 link_bw_kbps;
407 struct fixed31_32 available_stream_sym_count;
408 uint32_t available_hblank_bw = 0; /* in stream symbols */
409
410 if (crtc_info->dsc_bits_per_pixel) {
411 bits_per_pixel = dc_fixpt_from_fraction(crtc_info->dsc_bits_per_pixel, 16);
412 } else {
413 switch (crtc_info->color_depth) {
414 case COLOR_DEPTH_666:
415 bits_per_pixel = dc_fixpt_from_int(6);
416 break;
417 case COLOR_DEPTH_888:
418 bits_per_pixel = dc_fixpt_from_int(8);
419 break;
420 case COLOR_DEPTH_101010:
421 bits_per_pixel = dc_fixpt_from_int(10);
422 break;
423 case COLOR_DEPTH_121212:
424 bits_per_pixel = dc_fixpt_from_int(12);
425 break;
426 default:
427 /* Default to commonly supported color depth. */
428 bits_per_pixel = dc_fixpt_from_int(8);
429 break;
430 }
431
432 bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 3);
433
434 if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
435 bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 3);
436 bits_per_pixel = dc_fixpt_mul_int(bits_per_pixel, 2);
437 } else if (crtc_info->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
438 bits_per_pixel = dc_fixpt_div_int(bits_per_pixel, 2);
439 }
440 }
441
442 /* Use simple stream BW calculation because mainlink overhead is
443 * accounted for separately in the audio BW calculations.
444 */
445 peak_stream_bw_kbps = dc_fixpt_from_fraction(crtc_info->requested_pixel_clock_100Hz, 10);
446 peak_stream_bw_kbps = dc_fixpt_mul(peak_stream_bw_kbps, bits_per_pixel);
447 link_bw_kbps = dc_fixpt_from_int(dp_link_info->link_bandwidth_kbps);
448 average_stream_sym_bw_frac = dc_fixpt_div(peak_stream_bw_kbps, link_bw_kbps);
449
450 available_stream_sym_count = dc_fixpt_mul_int(hblank_time_msec, 1000);
451 available_stream_sym_count = dc_fixpt_mul(available_stream_sym_count, lsclkfreq_mhz);
452 available_stream_sym_count = dc_fixpt_mul(available_stream_sym_count, average_stream_sym_bw_frac);
453 available_hblank_bw = dc_fixpt_floor(available_stream_sym_count);
454 available_hblank_bw *= dp_link_info->lane_count;
455 available_hblank_bw -= crtc_info->dsc_num_slices * 4; /* EOC overhead */
456
457 if (available_hblank_bw < dp_link_info->hblank_min_symbol_width)
458 available_hblank_bw = dp_link_info->hblank_min_symbol_width;
459
460 if (available_hblank_bw < 12)
461 available_hblank_bw = 0;
462 else
463 available_hblank_bw -= 12; /* Main link overhead */
464
465 return available_hblank_bw;
466}
467
468static void check_audio_bandwidth_dp(
469 const struct audio_crtc_info *crtc_info,
470 const struct audio_dp_link_info *dp_link_info,
471 uint32_t channel_count,
472 union audio_sample_rates *sample_rates)
473{
474 struct dp_audio_layout_config layout_config = {0};
475 uint32_t available_hblank_bw;
476 uint32_t av_stream_map_lane_count;
477 uint32_t audio_sdp_overhead;
478
479 /* TODO: Add validation for SST 8b/10 case */
480 if (!dp_link_info->is_mst && dp_link_info->encoding == DP_8b_10b_ENCODING)
481 return;
482
483 available_hblank_bw = calculate_available_hblank_bw_in_symbols(
484 crtc_info, dp_link_info);
485 av_stream_map_lane_count = get_av_stream_map_lane_count(
486 dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst);
487 audio_sdp_overhead = get_audio_sdp_overhead(
488 dp_link_info->encoding, dp_link_info->lane_count, dp_link_info->is_mst);
489 get_audio_layout_config(
490 channel_count, dp_link_info->encoding, &layout_config);
491
492 if (layout_config.max_layouts_per_audio_sdp == 0 ||
493 layout_config.symbols_per_layout == 0 ||
494 layout_config.layouts_per_sample_denom == 0) {
495 return;
496 }
497 if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
498 crtc_info, &layout_config, channel_count, 192000,
499 av_stream_map_lane_count, audio_sdp_overhead))
500 sample_rates->rate.RATE_192 = 0;
501 if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
502 crtc_info, &layout_config, channel_count, 176400,
503 av_stream_map_lane_count, audio_sdp_overhead))
504 sample_rates->rate.RATE_176_4 = 0;
505 if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
506 crtc_info, &layout_config, channel_count, 96000,
507 av_stream_map_lane_count, audio_sdp_overhead))
508 sample_rates->rate.RATE_96 = 0;
509 if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
510 crtc_info, &layout_config, channel_count, 88200,
511 av_stream_map_lane_count, audio_sdp_overhead))
512 sample_rates->rate.RATE_88_2 = 0;
513 if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
514 crtc_info, &layout_config, channel_count, 48000,
515 av_stream_map_lane_count, audio_sdp_overhead))
516 sample_rates->rate.RATE_48 = 0;
517 if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
518 crtc_info, &layout_config, channel_count, 44100,
519 av_stream_map_lane_count, audio_sdp_overhead))
520 sample_rates->rate.RATE_44_1 = 0;
521 if (available_hblank_bw < calculate_required_audio_bw_in_symbols(
522 crtc_info, &layout_config, channel_count, 32000,
523 av_stream_map_lane_count, audio_sdp_overhead))
524 sample_rates->rate.RATE_32 = 0;
525}
526
527static void check_audio_bandwidth(
528 const struct audio_crtc_info *crtc_info,
529 const struct audio_dp_link_info *dp_link_info,
530 uint32_t channel_count,
531 enum signal_type signal,
532 union audio_sample_rates *sample_rates)
533{
534 switch (signal) {
535 case SIGNAL_TYPE_HDMI_TYPE_A:
536 check_audio_bandwidth_hdmi(
537 crtc_info, channel_count, sample_rates);
538 break;
539 case SIGNAL_TYPE_EDP:
540 case SIGNAL_TYPE_DISPLAY_PORT:
541 case SIGNAL_TYPE_DISPLAY_PORT_MST:
542 check_audio_bandwidth_dp(
543 crtc_info, dp_link_info, channel_count, sample_rates);
544 break;
545 default:
546 break;
547 }
548}
549
550/* expose/not expose HBR capability to Audio driver */
551static void set_high_bit_rate_capable(
552 struct audio *audio,
553 bool capable)
554{
555 uint32_t value = 0;
556
557 /* set high bit rate audio capable*/
558 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
559
560 set_reg_field_value(value, capable,
561 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
562 HBR_CAPABLE);
563
564 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value);
565}
566
567/* set video latency in ms/2+1 */
568static void set_video_latency(
569 struct audio *audio,
570 int latency_in_ms)
571{
572 uint32_t value = 0;
573
574 if ((latency_in_ms < 0) || (latency_in_ms > 255))
575 return;
576
577 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
578
579 set_reg_field_value(value, latency_in_ms,
580 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
581 VIDEO_LIPSYNC);
582
583 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
584 value);
585}
586
587/* set audio latency in ms/2+1 */
588static void set_audio_latency(
589 struct audio *audio,
590 int latency_in_ms)
591{
592 uint32_t value = 0;
593
594 if (latency_in_ms < 0)
595 latency_in_ms = 0;
596
597 if (latency_in_ms > 255)
598 latency_in_ms = 255;
599
600 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
601
602 set_reg_field_value(value, latency_in_ms,
603 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
604 AUDIO_LIPSYNC);
605
606 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
607 value);
608}
609
610void dce_aud_az_enable(struct audio *audio)
611{
612 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
613 DC_LOGGER_INIT();
614
615 set_reg_field_value(value, 1,
616 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
617 CLOCK_GATING_DISABLE);
618 set_reg_field_value(value, 1,
619 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
620 AUDIO_ENABLED);
621
622 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
623 set_reg_field_value(value, 0,
624 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
625 CLOCK_GATING_DISABLE);
626 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
627
628 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n",
629 audio->inst, value);
630}
631
632void dce_aud_az_disable(struct audio *audio)
633{
634 uint32_t value;
635 DC_LOGGER_INIT();
636
637 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
638 set_reg_field_value(value, 1,
639 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
640 CLOCK_GATING_DISABLE);
641 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
642
643 set_reg_field_value(value, 0,
644 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
645 AUDIO_ENABLED);
646 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
647
648 set_reg_field_value(value, 0,
649 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
650 CLOCK_GATING_DISABLE);
651 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
652 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
653 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n",
654 audio->inst, value);
655}
656
657void dce_aud_az_configure(
658 struct audio *audio,
659 enum signal_type signal,
660 const struct audio_crtc_info *crtc_info,
661 const struct audio_info *audio_info,
662 const struct audio_dp_link_info *dp_link_info)
663{
664 struct dce_audio *aud = DCE_AUD(audio);
665
666 uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
667 uint32_t value;
668 uint32_t field = 0;
669 enum audio_format_code audio_format_code;
670 uint32_t format_index;
671 uint32_t index;
672 bool is_ac3_supported = false;
673 union audio_sample_rates sample_rate;
674 uint32_t strlen = 0;
675
676 if (signal == SIGNAL_TYPE_VIRTUAL)
677 return;
678
679 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
680 set_reg_field_value(value, 1,
681 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
682 CLOCK_GATING_DISABLE);
683 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
684
685 /* Speaker Allocation */
686 /*
687 uint32_t value;
688 uint32_t field = 0;*/
689 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
690
691 set_reg_field_value(value,
692 speakers,
693 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
694 SPEAKER_ALLOCATION);
695
696 /* LFE_PLAYBACK_LEVEL = LFEPBL
697 * LFEPBL = 0 : Unknown or refer to other information
698 * LFEPBL = 1 : 0dB playback
699 * LFEPBL = 2 : +10dB playback
700 * LFE_BL = 3 : Reserved
701 */
702 set_reg_field_value(value,
703 0,
704 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
705 LFE_PLAYBACK_LEVEL);
706 /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only.
707 * why are we writing to it? DCE8 does not write this */
708
709
710 set_reg_field_value(value,
711 0,
712 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
713 HDMI_CONNECTION);
714
715 set_reg_field_value(value,
716 0,
717 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
718 DP_CONNECTION);
719
720 field = get_reg_field_value(value,
721 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
722 EXTRA_CONNECTION_INFO);
723
724 field &= ~0x1;
725
726 set_reg_field_value(value,
727 field,
728 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
729 EXTRA_CONNECTION_INFO);
730
731 /* set audio for output signal */
732 switch (signal) {
733 case SIGNAL_TYPE_HDMI_TYPE_A:
734 set_reg_field_value(value,
735 1,
736 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
737 HDMI_CONNECTION);
738
739 break;
740
741 case SIGNAL_TYPE_EDP:
742 case SIGNAL_TYPE_DISPLAY_PORT:
743 case SIGNAL_TYPE_DISPLAY_PORT_MST:
744 set_reg_field_value(value,
745 1,
746 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
747 DP_CONNECTION);
748 break;
749 default:
750 BREAK_TO_DEBUGGER();
751 break;
752 }
753
754 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value);
755
756 /* ACP Data - Supports AI */
757 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA);
758
759 set_reg_field_value(
760 value,
761 audio_info->flags.info.SUPPORT_AI,
762 AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA,
763 SUPPORTS_AI);
764
765 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA, value);
766
767 /* Audio Descriptors */
768 /* pass through all formats */
769 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
770 format_index++) {
771 audio_format_code =
772 (AUDIO_FORMAT_CODE_FIRST + format_index);
773
774 /* those are unsupported, skip programming */
775 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
776 audio_format_code == AUDIO_FORMAT_CODE_DST)
777 continue;
778
779 value = 0;
780
781 /* check if supported */
782 if (is_audio_format_supported(
783 audio_info, audio_format_code, &index)) {
784 const struct audio_mode *audio_mode =
785 &audio_info->modes[index];
786 union audio_sample_rates sample_rates =
787 audio_mode->sample_rates;
788 uint8_t byte2 = audio_mode->max_bit_rate;
789 uint8_t channel_count = audio_mode->channel_count;
790
791 /* adjust specific properties */
792 switch (audio_format_code) {
793 case AUDIO_FORMAT_CODE_LINEARPCM: {
794
795 check_audio_bandwidth(
796 crtc_info,
797 dp_link_info,
798 channel_count,
799 signal,
800 &sample_rates);
801
802 byte2 = audio_mode->sample_size;
803
804 set_reg_field_value(value,
805 sample_rates.all,
806 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
807 SUPPORTED_FREQUENCIES_STEREO);
808 }
809 break;
810 case AUDIO_FORMAT_CODE_AC3:
811 is_ac3_supported = true;
812 break;
813 case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
814 case AUDIO_FORMAT_CODE_DTS_HD:
815 case AUDIO_FORMAT_CODE_MAT_MLP:
816 case AUDIO_FORMAT_CODE_DST:
817 case AUDIO_FORMAT_CODE_WMAPRO:
818 byte2 = audio_mode->vendor_specific;
819 break;
820 default:
821 break;
822 }
823
824 /* fill audio format data */
825 set_reg_field_value(value,
826 channel_count - 1,
827 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
828 MAX_CHANNELS);
829
830 set_reg_field_value(value,
831 sample_rates.all,
832 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
833 SUPPORTED_FREQUENCIES);
834
835 set_reg_field_value(value,
836 byte2,
837 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
838 DESCRIPTOR_BYTE_2);
839 } /* if */
840
841 AZ_REG_WRITE(
842 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index,
843 value);
844 } /* for */
845
846 if (is_ac3_supported)
847 /* todo: this reg global. why program global register? */
848 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
849 0x05);
850
851 /* check for 192khz/8-Ch support for HBR requirements */
852 sample_rate.all = 0;
853 sample_rate.rate.RATE_192 = 1;
854
855 check_audio_bandwidth(
856 crtc_info,
857 dp_link_info,
858 8,
859 signal,
860 &sample_rate);
861
862 set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192);
863
864 /* Audio and Video Lipsync */
865 set_video_latency(audio, audio_info->video_latency);
866 set_audio_latency(audio, audio_info->audio_latency);
867
868 value = 0;
869 set_reg_field_value(value, audio_info->manufacture_id,
870 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
871 MANUFACTURER_ID);
872
873 set_reg_field_value(value, audio_info->product_id,
874 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
875 PRODUCT_ID);
876
877 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
878 value);
879
880 value = 0;
881
882 /*get display name string length */
883 while (audio_info->display_name[strlen++] != '\0') {
884 if (strlen >=
885 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
886 break;
887 }
888 set_reg_field_value(value, strlen,
889 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
890 SINK_DESCRIPTION_LEN);
891
892 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
893 value);
894 DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n",
895 audio->inst, value, audio_info->display_name);
896
897 /*
898 *write the port ID:
899 *PORT_ID0 = display index
900 *PORT_ID1 = 16bit BDF
901 *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
902 */
903
904 value = 0;
905
906 set_reg_field_value(value, audio_info->port_id[0],
907 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
908 PORT_ID0);
909
910 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value);
911
912 value = 0;
913 set_reg_field_value(value, audio_info->port_id[1],
914 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
915 PORT_ID1);
916
917 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value);
918
919 /*write the 18 char monitor string */
920
921 value = 0;
922 set_reg_field_value(value, audio_info->display_name[0],
923 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
924 DESCRIPTION0);
925
926 set_reg_field_value(value, audio_info->display_name[1],
927 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
928 DESCRIPTION1);
929
930 set_reg_field_value(value, audio_info->display_name[2],
931 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
932 DESCRIPTION2);
933
934 set_reg_field_value(value, audio_info->display_name[3],
935 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
936 DESCRIPTION3);
937
938 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value);
939
940 value = 0;
941 set_reg_field_value(value, audio_info->display_name[4],
942 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
943 DESCRIPTION4);
944
945 set_reg_field_value(value, audio_info->display_name[5],
946 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
947 DESCRIPTION5);
948
949 set_reg_field_value(value, audio_info->display_name[6],
950 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
951 DESCRIPTION6);
952
953 set_reg_field_value(value, audio_info->display_name[7],
954 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
955 DESCRIPTION7);
956
957 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value);
958
959 value = 0;
960 set_reg_field_value(value, audio_info->display_name[8],
961 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
962 DESCRIPTION8);
963
964 set_reg_field_value(value, audio_info->display_name[9],
965 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
966 DESCRIPTION9);
967
968 set_reg_field_value(value, audio_info->display_name[10],
969 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
970 DESCRIPTION10);
971
972 set_reg_field_value(value, audio_info->display_name[11],
973 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
974 DESCRIPTION11);
975
976 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value);
977
978 value = 0;
979 set_reg_field_value(value, audio_info->display_name[12],
980 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
981 DESCRIPTION12);
982
983 set_reg_field_value(value, audio_info->display_name[13],
984 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
985 DESCRIPTION13);
986
987 set_reg_field_value(value, audio_info->display_name[14],
988 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
989 DESCRIPTION14);
990
991 set_reg_field_value(value, audio_info->display_name[15],
992 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
993 DESCRIPTION15);
994
995 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value);
996
997 value = 0;
998 set_reg_field_value(value, audio_info->display_name[16],
999 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
1000 DESCRIPTION16);
1001
1002 set_reg_field_value(value, audio_info->display_name[17],
1003 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
1004 DESCRIPTION17);
1005
1006 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value);
1007 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
1008 set_reg_field_value(value, 0,
1009 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1010 CLOCK_GATING_DISABLE);
1011 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
1012}
1013
1014/*
1015* todo: wall clk related functionality probably belong to clock_src.
1016*/
1017
1018/* search pixel clock value for Azalia HDMI Audio */
1019static void get_azalia_clock_info_hdmi(
1020 uint32_t crtc_pixel_clock_100hz,
1021 uint32_t actual_pixel_clock_100Hz,
1022 struct azalia_clock_info *azalia_clock_info)
1023{
1024 /* audio_dto_phase= 24 * 10,000;
1025 * 24MHz in [100Hz] units */
1026 azalia_clock_info->audio_dto_phase =
1027 24 * 10000;
1028
1029 /* audio_dto_module = PCLKFrequency * 10,000;
1030 * [khz] -> [100Hz] */
1031 azalia_clock_info->audio_dto_module =
1032 actual_pixel_clock_100Hz;
1033}
1034
1035static void get_azalia_clock_info_dp(
1036 uint32_t requested_pixel_clock_100Hz,
1037 const struct audio_pll_info *pll_info,
1038 struct azalia_clock_info *azalia_clock_info)
1039{
1040 /* Reported dpDtoSourceClockInkhz value for
1041 * DCE8 already adjusted for SS, do not need any
1042 * adjustment here anymore
1043 */
1044
1045 /*audio_dto_phase = 24 * 10,000;
1046 * 24MHz in [100Hz] units */
1047 azalia_clock_info->audio_dto_phase = 24 * 10000;
1048
1049 /*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
1050 * [khz] ->[100Hz] */
1051 azalia_clock_info->audio_dto_module =
1052 pll_info->audio_dto_source_clock_in_khz * 10;
1053}
1054
1055void dce_aud_wall_dto_setup(
1056 struct audio *audio,
1057 enum signal_type signal,
1058 const struct audio_crtc_info *crtc_info,
1059 const struct audio_pll_info *pll_info)
1060{
1061 struct dce_audio *aud = DCE_AUD(audio);
1062
1063 struct azalia_clock_info clock_info = { 0 };
1064
1065 if (dc_is_hdmi_tmds_signal(signal)) {
1066 uint32_t src_sel;
1067
1068 /*DTO0 Programming goal:
1069 -generate 24MHz, 128*Fs from 24MHz
1070 -use DTO0 when an active HDMI port is connected
1071 (optionally a DP is connected) */
1072
1073 /* calculate DTO settings */
1074 get_azalia_clock_info_hdmi(
1075 crtc_info->requested_pixel_clock_100Hz,
1076 crtc_info->calculated_pixel_clock_100Hz,
1077 &clock_info);
1078
1079 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
1080 "calculated_pixel_clock_100Hz =%d\n"\
1081 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
1082 crtc_info->requested_pixel_clock_100Hz,\
1083 crtc_info->calculated_pixel_clock_100Hz,\
1084 clock_info.audio_dto_module,\
1085 clock_info.audio_dto_phase);
1086
1087 /* On TN/SI, Program DTO source select and DTO select before
1088 programming DTO modulo and DTO phase. These bits must be
1089 programmed first, otherwise there will be no HDMI audio at boot
1090 up. This is a HW sequence change (different from old ASICs).
1091 Caution when changing this programming sequence.
1092
1093 HDMI enabled, using DTO0
1094 program master CRTC for DTO0 */
1095 src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
1096 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
1097 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
1098 DCCG_AUDIO_DTO_SEL, 0);
1099
1100 /* module */
1101 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
1102 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
1103
1104 /* phase */
1105 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
1106 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
1107 } else {
1108 /*DTO1 Programming goal:
1109 -generate 24MHz, 512*Fs, 128*Fs from 24MHz
1110 -default is to used DTO1, and switch to DTO0 when an audio
1111 master HDMI port is connected
1112 -use as default for DP
1113
1114 calculate DTO settings */
1115 get_azalia_clock_info_dp(
1116 crtc_info->requested_pixel_clock_100Hz,
1117 pll_info,
1118 &clock_info);
1119
1120 /* Program DTO select before programming DTO modulo and DTO
1121 phase. default to use DTO1 */
1122
1123 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
1124 DCCG_AUDIO_DTO_SEL, 1);
1125
1126 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
1127 * Select 512fs for DP TODO: web register definition
1128 * does not match register header file
1129 * DCE11 version it's commented out while DCE8 it's set to 1
1130 */
1131
1132 /* module */
1133 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
1134 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
1135
1136 /* phase */
1137 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
1138 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
1139
1140 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
1141 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);
1142
1143 }
1144}
1145
1146#if defined(CONFIG_DRM_AMD_DC_SI)
1147static void dce60_aud_wall_dto_setup(
1148 struct audio *audio,
1149 enum signal_type signal,
1150 const struct audio_crtc_info *crtc_info,
1151 const struct audio_pll_info *pll_info)
1152{
1153 struct dce_audio *aud = DCE_AUD(audio);
1154
1155 struct azalia_clock_info clock_info = { 0 };
1156
1157 if (dc_is_hdmi_signal(signal)) {
1158 uint32_t src_sel;
1159
1160 /*DTO0 Programming goal:
1161 -generate 24MHz, 128*Fs from 24MHz
1162 -use DTO0 when an active HDMI port is connected
1163 (optionally a DP is connected) */
1164
1165 /* calculate DTO settings */
1166 get_azalia_clock_info_hdmi(
1167 crtc_info->requested_pixel_clock_100Hz,
1168 crtc_info->calculated_pixel_clock_100Hz,
1169 &clock_info);
1170
1171 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
1172 "calculated_pixel_clock_100Hz =%d\n"\
1173 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
1174 crtc_info->requested_pixel_clock_100Hz,\
1175 crtc_info->calculated_pixel_clock_100Hz,\
1176 clock_info.audio_dto_module,\
1177 clock_info.audio_dto_phase);
1178
1179 /* On TN/SI, Program DTO source select and DTO select before
1180 programming DTO modulo and DTO phase. These bits must be
1181 programmed first, otherwise there will be no HDMI audio at boot
1182 up. This is a HW sequence change (different from old ASICs).
1183 Caution when changing this programming sequence.
1184
1185 HDMI enabled, using DTO0
1186 program master CRTC for DTO0 */
1187 src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
1188 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
1189 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
1190 DCCG_AUDIO_DTO_SEL, 0);
1191
1192 /* module */
1193 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
1194 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
1195
1196 /* phase */
1197 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
1198 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
1199 } else {
1200 /*DTO1 Programming goal:
1201 -generate 24MHz, 128*Fs from 24MHz (DCE6 does not support 512*Fs)
1202 -default is to used DTO1, and switch to DTO0 when an audio
1203 master HDMI port is connected
1204 -use as default for DP
1205
1206 calculate DTO settings */
1207 get_azalia_clock_info_dp(
1208 crtc_info->requested_pixel_clock_100Hz,
1209 pll_info,
1210 &clock_info);
1211
1212 /* Program DTO select before programming DTO modulo and DTO
1213 phase. default to use DTO1 */
1214
1215 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
1216 DCCG_AUDIO_DTO_SEL, 1);
1217
1218 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
1219 * Cannot select 512fs for DP
1220 *
1221 * DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask
1222 */
1223
1224 /* module */
1225 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
1226 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
1227
1228 /* phase */
1229 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
1230 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
1231
1232 /* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE reg */
1233
1234 }
1235}
1236#endif
1237
1238static bool dce_aud_endpoint_valid(struct audio *audio)
1239{
1240 uint32_t value;
1241 uint32_t port_connectivity;
1242
1243 value = AZ_REG_READ(
1244 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1245
1246 port_connectivity = get_reg_field_value(value,
1247 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
1248 PORT_CONNECTIVITY);
1249
1250 return !(port_connectivity == 1);
1251}
1252
1253/* initialize HW state */
1254void dce_aud_hw_init(
1255 struct audio *audio)
1256{
1257 uint32_t value;
1258 struct dce_audio *aud = DCE_AUD(audio);
1259
1260 /* we only need to program the following registers once, so we only do
1261 it for the inst 0*/
1262 if (audio->inst != 0)
1263 return;
1264
1265 /* Suport R5 - 32khz
1266 * Suport R6 - 44.1khz
1267 * Suport R7 - 48khz
1268 */
1269 /*disable clock gating before write to endpoint register*/
1270 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
1271 set_reg_field_value(value, 1,
1272 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1273 CLOCK_GATING_DISABLE);
1274 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
1275 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
1276 AUDIO_RATE_CAPABILITIES, 0x70);
1277
1278 /*Keep alive bit to verify HW block in BU. */
1279 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
1280 CLKSTOP, 1,
1281 EPSS, 1);
1282 set_reg_field_value(value, 0,
1283 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1284 CLOCK_GATING_DISABLE);
1285 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
1286}
1287
1288static const struct audio_funcs funcs = {
1289 .endpoint_valid = dce_aud_endpoint_valid,
1290 .hw_init = dce_aud_hw_init,
1291 .wall_dto_setup = dce_aud_wall_dto_setup,
1292 .az_enable = dce_aud_az_enable,
1293 .az_disable = dce_aud_az_disable,
1294 .az_configure = dce_aud_az_configure,
1295 .destroy = dce_aud_destroy,
1296};
1297
1298#if defined(CONFIG_DRM_AMD_DC_SI)
1299static const struct audio_funcs dce60_funcs = {
1300 .endpoint_valid = dce_aud_endpoint_valid,
1301 .hw_init = dce_aud_hw_init,
1302 .wall_dto_setup = dce60_aud_wall_dto_setup,
1303 .az_enable = dce_aud_az_enable,
1304 .az_disable = dce_aud_az_disable,
1305 .az_configure = dce_aud_az_configure,
1306 .destroy = dce_aud_destroy,
1307};
1308#endif
1309
1310void dce_aud_destroy(struct audio **audio)
1311{
1312 struct dce_audio *aud = DCE_AUD(*audio);
1313
1314 kfree(aud);
1315 *audio = NULL;
1316}
1317
1318struct audio *dce_audio_create(
1319 struct dc_context *ctx,
1320 unsigned int inst,
1321 const struct dce_audio_registers *reg,
1322 const struct dce_audio_shift *shifts,
1323 const struct dce_audio_mask *masks
1324 )
1325{
1326 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
1327
1328 if (audio == NULL) {
1329 ASSERT_CRITICAL(audio);
1330 return NULL;
1331 }
1332
1333 audio->base.ctx = ctx;
1334 audio->base.inst = inst;
1335 audio->base.funcs = &funcs;
1336
1337 audio->regs = reg;
1338 audio->shifts = shifts;
1339 audio->masks = masks;
1340 return &audio->base;
1341}
1342
1343#if defined(CONFIG_DRM_AMD_DC_SI)
1344struct audio *dce60_audio_create(
1345 struct dc_context *ctx,
1346 unsigned int inst,
1347 const struct dce_audio_registers *reg,
1348 const struct dce_audio_shift *shifts,
1349 const struct dce_audio_mask *masks
1350 )
1351{
1352 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
1353
1354 if (audio == NULL) {
1355 ASSERT_CRITICAL(audio);
1356 return NULL;
1357 }
1358
1359 audio->base.ctx = ctx;
1360 audio->base.inst = inst;
1361 audio->base.funcs = &dce60_funcs;
1362
1363 audio->regs = reg;
1364 audio->shifts = shifts;
1365 audio->masks = masks;
1366 return &audio->base;
1367}
1368#endif
1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include <linux/slab.h>
27
28#include "reg_helper.h"
29#include "dce_audio.h"
30#include "dce/dce_11_0_d.h"
31#include "dce/dce_11_0_sh_mask.h"
32
33#define DCE_AUD(audio)\
34 container_of(audio, struct dce_audio, base)
35
36#define CTX \
37 aud->base.ctx
38
39#define DC_LOGGER_INIT()
40
41#define REG(reg)\
42 (aud->regs->reg)
43
44#undef FN
45#define FN(reg_name, field_name) \
46 aud->shifts->field_name, aud->masks->field_name
47
48#define IX_REG(reg)\
49 ix ## reg
50
51#define AZ_REG_READ(reg_name) \
52 read_indirect_azalia_reg(audio, IX_REG(reg_name))
53
54#define AZ_REG_WRITE(reg_name, value) \
55 write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
56
57static void write_indirect_azalia_reg(struct audio *audio,
58 uint32_t reg_index,
59 uint32_t reg_data)
60{
61 struct dce_audio *aud = DCE_AUD(audio);
62
63 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
64 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
65 AZALIA_ENDPOINT_REG_INDEX, reg_index);
66
67 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
68 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
69 AZALIA_ENDPOINT_REG_DATA, reg_data);
70
71 DC_LOG_HW_AUDIO("AUDIO:write_indirect_azalia_reg: index: %u data: %u\n",
72 reg_index, reg_data);
73}
74
75static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)
76{
77 struct dce_audio *aud = DCE_AUD(audio);
78
79 uint32_t value = 0;
80
81 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
82 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
83 AZALIA_ENDPOINT_REG_INDEX, reg_index);
84
85 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
86 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
87
88 DC_LOG_HW_AUDIO("AUDIO:read_indirect_azalia_reg: index: %u data: %u\n",
89 reg_index, value);
90
91 return value;
92}
93
94static bool is_audio_format_supported(
95 const struct audio_info *audio_info,
96 enum audio_format_code audio_format_code,
97 uint32_t *format_index)
98{
99 uint32_t index;
100 uint32_t max_channe_index = 0;
101 bool found = false;
102
103 if (audio_info == NULL)
104 return found;
105
106 /* pass through whole array */
107 for (index = 0; index < audio_info->mode_count; index++) {
108 if (audio_info->modes[index].format_code == audio_format_code) {
109 if (found) {
110 /* format has multiply entries, choose one with
111 * highst number of channels */
112 if (audio_info->modes[index].channel_count >
113 audio_info->modes[max_channe_index].channel_count) {
114 max_channe_index = index;
115 }
116 } else {
117 /* format found, save it's index */
118 found = true;
119 max_channe_index = index;
120 }
121 }
122 }
123
124 /* return index */
125 if (found && format_index != NULL)
126 *format_index = max_channe_index;
127
128 return found;
129}
130
131/*For HDMI, calculate if specified sample rates can fit into a given timing */
132static void check_audio_bandwidth_hdmi(
133 const struct audio_crtc_info *crtc_info,
134 uint32_t channel_count,
135 union audio_sample_rates *sample_rates)
136{
137 uint32_t samples;
138 uint32_t h_blank;
139 bool limit_freq_to_48_khz = false;
140 bool limit_freq_to_88_2_khz = false;
141 bool limit_freq_to_96_khz = false;
142 bool limit_freq_to_174_4_khz = false;
143 if (!crtc_info)
144 return;
145
146 /* For two channels supported return whatever sink support,unmodified*/
147 if (channel_count > 2) {
148
149 /* Based on HDMI spec 1.3 Table 7.5 */
150 if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
151 (crtc_info->v_active <= 576) &&
152 !(crtc_info->interlaced) &&
153 !(crtc_info->pixel_repetition == 2 ||
154 crtc_info->pixel_repetition == 4)) {
155 limit_freq_to_48_khz = true;
156
157 } else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) &&
158 (crtc_info->v_active <= 576) &&
159 (crtc_info->interlaced) &&
160 (crtc_info->pixel_repetition == 2)) {
161 limit_freq_to_88_2_khz = true;
162
163 } else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) &&
164 (crtc_info->v_active <= 576) &&
165 !(crtc_info->interlaced)) {
166 limit_freq_to_174_4_khz = true;
167 }
168 }
169
170 /* Also do some calculation for the available Audio Bandwidth for the
171 * 8 ch (i.e. for the Layout 1 => ch > 2)
172 */
173 h_blank = crtc_info->h_total - crtc_info->h_active;
174
175 if (crtc_info->pixel_repetition)
176 h_blank *= crtc_info->pixel_repetition;
177
178 /*based on HDMI spec 1.3 Table 7.5 */
179 h_blank -= 58;
180 /*for Control Period */
181 h_blank -= 16;
182
183 samples = h_blank * 10;
184 /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number
185 * of Audio samples per line multiplied by 10 - Layout 1)
186 */
187 samples /= 32;
188 samples *= crtc_info->v_active;
189 /*Number of samples multiplied by 10, per second */
190 samples *= crtc_info->refresh_rate;
191 /*Number of Audio samples per second */
192 samples /= 10;
193
194 /* @todo do it after deep color is implemented
195 * 8xx - deep color bandwidth scaling
196 * Extra bandwidth is avaliable in deep color b/c link runs faster than
197 * pixel rate. This has the effect of allowing more tmds characters to
198 * be transmitted during blank
199 */
200
201 switch (crtc_info->color_depth) {
202 case COLOR_DEPTH_888:
203 samples *= 4;
204 break;
205 case COLOR_DEPTH_101010:
206 samples *= 5;
207 break;
208 case COLOR_DEPTH_121212:
209 samples *= 6;
210 break;
211 default:
212 samples *= 4;
213 break;
214 }
215
216 samples /= 4;
217
218 /*check limitation*/
219 if (samples < 88200)
220 limit_freq_to_48_khz = true;
221 else if (samples < 96000)
222 limit_freq_to_88_2_khz = true;
223 else if (samples < 176400)
224 limit_freq_to_96_khz = true;
225 else if (samples < 192000)
226 limit_freq_to_174_4_khz = true;
227
228 if (sample_rates != NULL) {
229 /* limit frequencies */
230 if (limit_freq_to_174_4_khz)
231 sample_rates->rate.RATE_192 = 0;
232
233 if (limit_freq_to_96_khz) {
234 sample_rates->rate.RATE_192 = 0;
235 sample_rates->rate.RATE_176_4 = 0;
236 }
237 if (limit_freq_to_88_2_khz) {
238 sample_rates->rate.RATE_192 = 0;
239 sample_rates->rate.RATE_176_4 = 0;
240 sample_rates->rate.RATE_96 = 0;
241 }
242 if (limit_freq_to_48_khz) {
243 sample_rates->rate.RATE_192 = 0;
244 sample_rates->rate.RATE_176_4 = 0;
245 sample_rates->rate.RATE_96 = 0;
246 sample_rates->rate.RATE_88_2 = 0;
247 }
248 }
249}
250
251/*For DP SST, calculate if specified sample rates can fit into a given timing */
252static void check_audio_bandwidth_dpsst(
253 const struct audio_crtc_info *crtc_info,
254 uint32_t channel_count,
255 union audio_sample_rates *sample_rates)
256{
257 /* do nothing */
258}
259
260/*For DP MST, calculate if specified sample rates can fit into a given timing */
261static void check_audio_bandwidth_dpmst(
262 const struct audio_crtc_info *crtc_info,
263 uint32_t channel_count,
264 union audio_sample_rates *sample_rates)
265{
266 /* do nothing */
267}
268
269static void check_audio_bandwidth(
270 const struct audio_crtc_info *crtc_info,
271 uint32_t channel_count,
272 enum signal_type signal,
273 union audio_sample_rates *sample_rates)
274{
275 switch (signal) {
276 case SIGNAL_TYPE_HDMI_TYPE_A:
277 check_audio_bandwidth_hdmi(
278 crtc_info, channel_count, sample_rates);
279 break;
280 case SIGNAL_TYPE_EDP:
281 case SIGNAL_TYPE_DISPLAY_PORT:
282 check_audio_bandwidth_dpsst(
283 crtc_info, channel_count, sample_rates);
284 break;
285 case SIGNAL_TYPE_DISPLAY_PORT_MST:
286 check_audio_bandwidth_dpmst(
287 crtc_info, channel_count, sample_rates);
288 break;
289 default:
290 break;
291 }
292}
293
294/* expose/not expose HBR capability to Audio driver */
295static void set_high_bit_rate_capable(
296 struct audio *audio,
297 bool capable)
298{
299 uint32_t value = 0;
300
301 /* set high bit rate audio capable*/
302 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR);
303
304 set_reg_field_value(value, capable,
305 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR,
306 HBR_CAPABLE);
307
308 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value);
309}
310
311/* set video latency in in ms/2+1 */
312static void set_video_latency(
313 struct audio *audio,
314 int latency_in_ms)
315{
316 uint32_t value = 0;
317
318 if ((latency_in_ms < 0) || (latency_in_ms > 255))
319 return;
320
321 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
322
323 set_reg_field_value(value, latency_in_ms,
324 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
325 VIDEO_LIPSYNC);
326
327 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
328 value);
329}
330
331/* set audio latency in in ms/2+1 */
332static void set_audio_latency(
333 struct audio *audio,
334 int latency_in_ms)
335{
336 uint32_t value = 0;
337
338 if (latency_in_ms < 0)
339 latency_in_ms = 0;
340
341 if (latency_in_ms > 255)
342 latency_in_ms = 255;
343
344 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC);
345
346 set_reg_field_value(value, latency_in_ms,
347 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
348 AUDIO_LIPSYNC);
349
350 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
351 value);
352}
353
354void dce_aud_az_enable(struct audio *audio)
355{
356 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
357 DC_LOGGER_INIT();
358
359 set_reg_field_value(value, 1,
360 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
361 CLOCK_GATING_DISABLE);
362 set_reg_field_value(value, 1,
363 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
364 AUDIO_ENABLED);
365
366 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
367 set_reg_field_value(value, 0,
368 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
369 CLOCK_GATING_DISABLE);
370 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
371
372 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n",
373 audio->inst, value);
374}
375
376void dce_aud_az_disable(struct audio *audio)
377{
378 uint32_t value;
379 DC_LOGGER_INIT();
380
381 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
382 set_reg_field_value(value, 1,
383 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
384 CLOCK_GATING_DISABLE);
385 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
386
387 set_reg_field_value(value, 0,
388 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
389 AUDIO_ENABLED);
390 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
391
392 set_reg_field_value(value, 0,
393 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
394 CLOCK_GATING_DISABLE);
395 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
396 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
397 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n",
398 audio->inst, value);
399}
400
401void dce_aud_az_configure(
402 struct audio *audio,
403 enum signal_type signal,
404 const struct audio_crtc_info *crtc_info,
405 const struct audio_info *audio_info)
406{
407 struct dce_audio *aud = DCE_AUD(audio);
408
409 uint32_t speakers = audio_info->flags.info.ALLSPEAKERS;
410 uint32_t value;
411 uint32_t field = 0;
412 enum audio_format_code audio_format_code;
413 uint32_t format_index;
414 uint32_t index;
415 bool is_ac3_supported = false;
416 union audio_sample_rates sample_rate;
417 uint32_t strlen = 0;
418 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
419 set_reg_field_value(value, 1,
420 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
421 CLOCK_GATING_DISABLE);
422 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
423
424 /* Speaker Allocation */
425 /*
426 uint32_t value;
427 uint32_t field = 0;*/
428 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
429
430 set_reg_field_value(value,
431 speakers,
432 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
433 SPEAKER_ALLOCATION);
434
435 /* LFE_PLAYBACK_LEVEL = LFEPBL
436 * LFEPBL = 0 : Unknown or refer to other information
437 * LFEPBL = 1 : 0dB playback
438 * LFEPBL = 2 : +10dB playback
439 * LFE_BL = 3 : Reserved
440 */
441 set_reg_field_value(value,
442 0,
443 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
444 LFE_PLAYBACK_LEVEL);
445 /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only.
446 * why are we writing to it? DCE8 does not write this */
447
448
449 set_reg_field_value(value,
450 0,
451 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
452 HDMI_CONNECTION);
453
454 set_reg_field_value(value,
455 0,
456 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
457 DP_CONNECTION);
458
459 field = get_reg_field_value(value,
460 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
461 EXTRA_CONNECTION_INFO);
462
463 field &= ~0x1;
464
465 set_reg_field_value(value,
466 field,
467 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
468 EXTRA_CONNECTION_INFO);
469
470 /* set audio for output signal */
471 switch (signal) {
472 case SIGNAL_TYPE_HDMI_TYPE_A:
473 set_reg_field_value(value,
474 1,
475 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
476 HDMI_CONNECTION);
477
478 break;
479
480 case SIGNAL_TYPE_EDP:
481 case SIGNAL_TYPE_DISPLAY_PORT:
482 case SIGNAL_TYPE_DISPLAY_PORT_MST:
483 set_reg_field_value(value,
484 1,
485 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
486 DP_CONNECTION);
487 break;
488 default:
489 BREAK_TO_DEBUGGER();
490 break;
491 }
492
493 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value);
494
495 /* Audio Descriptors */
496 /* pass through all formats */
497 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT;
498 format_index++) {
499 audio_format_code =
500 (AUDIO_FORMAT_CODE_FIRST + format_index);
501
502 /* those are unsupported, skip programming */
503 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO ||
504 audio_format_code == AUDIO_FORMAT_CODE_DST)
505 continue;
506
507 value = 0;
508
509 /* check if supported */
510 if (is_audio_format_supported(
511 audio_info, audio_format_code, &index)) {
512 const struct audio_mode *audio_mode =
513 &audio_info->modes[index];
514 union audio_sample_rates sample_rates =
515 audio_mode->sample_rates;
516 uint8_t byte2 = audio_mode->max_bit_rate;
517
518 /* adjust specific properties */
519 switch (audio_format_code) {
520 case AUDIO_FORMAT_CODE_LINEARPCM: {
521 check_audio_bandwidth(
522 crtc_info,
523 audio_mode->channel_count,
524 signal,
525 &sample_rates);
526
527 byte2 = audio_mode->sample_size;
528
529 set_reg_field_value(value,
530 sample_rates.all,
531 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
532 SUPPORTED_FREQUENCIES_STEREO);
533 }
534 break;
535 case AUDIO_FORMAT_CODE_AC3:
536 is_ac3_supported = true;
537 break;
538 case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS:
539 case AUDIO_FORMAT_CODE_DTS_HD:
540 case AUDIO_FORMAT_CODE_MAT_MLP:
541 case AUDIO_FORMAT_CODE_DST:
542 case AUDIO_FORMAT_CODE_WMAPRO:
543 byte2 = audio_mode->vendor_specific;
544 break;
545 default:
546 break;
547 }
548
549 /* fill audio format data */
550 set_reg_field_value(value,
551 audio_mode->channel_count - 1,
552 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
553 MAX_CHANNELS);
554
555 set_reg_field_value(value,
556 sample_rates.all,
557 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
558 SUPPORTED_FREQUENCIES);
559
560 set_reg_field_value(value,
561 byte2,
562 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
563 DESCRIPTOR_BYTE_2);
564 } /* if */
565
566 AZ_REG_WRITE(
567 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index,
568 value);
569 } /* for */
570
571 if (is_ac3_supported)
572 /* todo: this reg global. why program global register? */
573 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS,
574 0x05);
575
576 /* check for 192khz/8-Ch support for HBR requirements */
577 sample_rate.all = 0;
578 sample_rate.rate.RATE_192 = 1;
579
580 check_audio_bandwidth(
581 crtc_info,
582 8,
583 signal,
584 &sample_rate);
585
586 set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192);
587
588 /* Audio and Video Lipsync */
589 set_video_latency(audio, audio_info->video_latency);
590 set_audio_latency(audio, audio_info->audio_latency);
591
592 value = 0;
593 set_reg_field_value(value, audio_info->manufacture_id,
594 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
595 MANUFACTURER_ID);
596
597 set_reg_field_value(value, audio_info->product_id,
598 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
599 PRODUCT_ID);
600
601 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0,
602 value);
603
604 value = 0;
605
606 /*get display name string length */
607 while (audio_info->display_name[strlen++] != '\0') {
608 if (strlen >=
609 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS)
610 break;
611 }
612 set_reg_field_value(value, strlen,
613 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
614 SINK_DESCRIPTION_LEN);
615
616 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1,
617 value);
618 DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n",
619 audio->inst, value, audio_info->display_name);
620
621 /*
622 *write the port ID:
623 *PORT_ID0 = display index
624 *PORT_ID1 = 16bit BDF
625 *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function)
626 */
627
628 value = 0;
629
630 set_reg_field_value(value, audio_info->port_id[0],
631 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2,
632 PORT_ID0);
633
634 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value);
635
636 value = 0;
637 set_reg_field_value(value, audio_info->port_id[1],
638 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3,
639 PORT_ID1);
640
641 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value);
642
643 /*write the 18 char monitor string */
644
645 value = 0;
646 set_reg_field_value(value, audio_info->display_name[0],
647 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
648 DESCRIPTION0);
649
650 set_reg_field_value(value, audio_info->display_name[1],
651 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
652 DESCRIPTION1);
653
654 set_reg_field_value(value, audio_info->display_name[2],
655 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
656 DESCRIPTION2);
657
658 set_reg_field_value(value, audio_info->display_name[3],
659 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4,
660 DESCRIPTION3);
661
662 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value);
663
664 value = 0;
665 set_reg_field_value(value, audio_info->display_name[4],
666 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
667 DESCRIPTION4);
668
669 set_reg_field_value(value, audio_info->display_name[5],
670 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
671 DESCRIPTION5);
672
673 set_reg_field_value(value, audio_info->display_name[6],
674 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
675 DESCRIPTION6);
676
677 set_reg_field_value(value, audio_info->display_name[7],
678 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5,
679 DESCRIPTION7);
680
681 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value);
682
683 value = 0;
684 set_reg_field_value(value, audio_info->display_name[8],
685 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
686 DESCRIPTION8);
687
688 set_reg_field_value(value, audio_info->display_name[9],
689 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
690 DESCRIPTION9);
691
692 set_reg_field_value(value, audio_info->display_name[10],
693 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
694 DESCRIPTION10);
695
696 set_reg_field_value(value, audio_info->display_name[11],
697 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6,
698 DESCRIPTION11);
699
700 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value);
701
702 value = 0;
703 set_reg_field_value(value, audio_info->display_name[12],
704 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
705 DESCRIPTION12);
706
707 set_reg_field_value(value, audio_info->display_name[13],
708 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
709 DESCRIPTION13);
710
711 set_reg_field_value(value, audio_info->display_name[14],
712 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
713 DESCRIPTION14);
714
715 set_reg_field_value(value, audio_info->display_name[15],
716 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7,
717 DESCRIPTION15);
718
719 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value);
720
721 value = 0;
722 set_reg_field_value(value, audio_info->display_name[16],
723 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
724 DESCRIPTION16);
725
726 set_reg_field_value(value, audio_info->display_name[17],
727 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8,
728 DESCRIPTION17);
729
730 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value);
731 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
732 set_reg_field_value(value, 0,
733 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
734 CLOCK_GATING_DISABLE);
735 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
736}
737
738/*
739* todo: wall clk related functionality probably belong to clock_src.
740*/
741
742/* search pixel clock value for Azalia HDMI Audio */
743static void get_azalia_clock_info_hdmi(
744 uint32_t crtc_pixel_clock_100hz,
745 uint32_t actual_pixel_clock_100Hz,
746 struct azalia_clock_info *azalia_clock_info)
747{
748 /* audio_dto_phase= 24 * 10,000;
749 * 24MHz in [100Hz] units */
750 azalia_clock_info->audio_dto_phase =
751 24 * 10000;
752
753 /* audio_dto_module = PCLKFrequency * 10,000;
754 * [khz] -> [100Hz] */
755 azalia_clock_info->audio_dto_module =
756 actual_pixel_clock_100Hz;
757}
758
759static void get_azalia_clock_info_dp(
760 uint32_t requested_pixel_clock_100Hz,
761 const struct audio_pll_info *pll_info,
762 struct azalia_clock_info *azalia_clock_info)
763{
764 /* Reported dpDtoSourceClockInkhz value for
765 * DCE8 already adjusted for SS, do not need any
766 * adjustment here anymore
767 */
768
769 /*audio_dto_phase = 24 * 10,000;
770 * 24MHz in [100Hz] units */
771 azalia_clock_info->audio_dto_phase = 24 * 10000;
772
773 /*audio_dto_module = dpDtoSourceClockInkhz * 10,000;
774 * [khz] ->[100Hz] */
775 azalia_clock_info->audio_dto_module =
776 pll_info->dp_dto_source_clock_in_khz * 10;
777}
778
779void dce_aud_wall_dto_setup(
780 struct audio *audio,
781 enum signal_type signal,
782 const struct audio_crtc_info *crtc_info,
783 const struct audio_pll_info *pll_info)
784{
785 struct dce_audio *aud = DCE_AUD(audio);
786
787 struct azalia_clock_info clock_info = { 0 };
788
789 if (dc_is_hdmi_tmds_signal(signal)) {
790 uint32_t src_sel;
791
792 /*DTO0 Programming goal:
793 -generate 24MHz, 128*Fs from 24MHz
794 -use DTO0 when an active HDMI port is connected
795 (optionally a DP is connected) */
796
797 /* calculate DTO settings */
798 get_azalia_clock_info_hdmi(
799 crtc_info->requested_pixel_clock_100Hz,
800 crtc_info->calculated_pixel_clock_100Hz,
801 &clock_info);
802
803 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\
804 "calculated_pixel_clock_100Hz =%d\n"\
805 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\
806 crtc_info->requested_pixel_clock_100Hz,\
807 crtc_info->calculated_pixel_clock_100Hz,\
808 clock_info.audio_dto_module,\
809 clock_info.audio_dto_phase);
810
811 /* On TN/SI, Program DTO source select and DTO select before
812 programming DTO modulo and DTO phase. These bits must be
813 programmed first, otherwise there will be no HDMI audio at boot
814 up. This is a HW sequence change (different from old ASICs).
815 Caution when changing this programming sequence.
816
817 HDMI enabled, using DTO0
818 program master CRTC for DTO0 */
819 src_sel = pll_info->dto_source - DTO_SOURCE_ID0;
820 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE,
821 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel,
822 DCCG_AUDIO_DTO_SEL, 0);
823
824 /* module */
825 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE,
826 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module);
827
828 /* phase */
829 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE,
830 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase);
831 } else {
832 /*DTO1 Programming goal:
833 -generate 24MHz, 512*Fs, 128*Fs from 24MHz
834 -default is to used DTO1, and switch to DTO0 when an audio
835 master HDMI port is connected
836 -use as default for DP
837
838 calculate DTO settings */
839 get_azalia_clock_info_dp(
840 crtc_info->requested_pixel_clock_100Hz,
841 pll_info,
842 &clock_info);
843
844 /* Program DTO select before programming DTO modulo and DTO
845 phase. default to use DTO1 */
846
847 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
848 DCCG_AUDIO_DTO_SEL, 1);
849
850 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
851 * Select 512fs for DP TODO: web register definition
852 * does not match register header file
853 * DCE11 version it's commented out while DCE8 it's set to 1
854 */
855
856 /* module */
857 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE,
858 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module);
859
860 /* phase */
861 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE,
862 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase);
863
864 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
865 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1);
866
867 }
868}
869
870static bool dce_aud_endpoint_valid(struct audio *audio)
871{
872 uint32_t value;
873 uint32_t port_connectivity;
874
875 value = AZ_REG_READ(
876 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
877
878 port_connectivity = get_reg_field_value(value,
879 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
880 PORT_CONNECTIVITY);
881
882 return !(port_connectivity == 1);
883}
884
885/* initialize HW state */
886void dce_aud_hw_init(
887 struct audio *audio)
888{
889 uint32_t value;
890 struct dce_audio *aud = DCE_AUD(audio);
891
892 /* we only need to program the following registers once, so we only do
893 it for the inst 0*/
894 if (audio->inst != 0)
895 return;
896
897 /* Suport R5 - 32khz
898 * Suport R6 - 44.1khz
899 * Suport R7 - 48khz
900 */
901 /*disable clock gating before write to endpoint register*/
902 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL);
903 set_reg_field_value(value, 1,
904 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
905 CLOCK_GATING_DISABLE);
906 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
907 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES,
908 AUDIO_RATE_CAPABILITIES, 0x70);
909
910 /*Keep alive bit to verify HW block in BU. */
911 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES,
912 CLKSTOP, 1,
913 EPSS, 1);
914 set_reg_field_value(value, 0,
915 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
916 CLOCK_GATING_DISABLE);
917 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value);
918}
919
920static const struct audio_funcs funcs = {
921 .endpoint_valid = dce_aud_endpoint_valid,
922 .hw_init = dce_aud_hw_init,
923 .wall_dto_setup = dce_aud_wall_dto_setup,
924 .az_enable = dce_aud_az_enable,
925 .az_disable = dce_aud_az_disable,
926 .az_configure = dce_aud_az_configure,
927 .destroy = dce_aud_destroy,
928};
929void dce_aud_destroy(struct audio **audio)
930{
931 struct dce_audio *aud = DCE_AUD(*audio);
932
933 kfree(aud);
934 *audio = NULL;
935}
936
937struct audio *dce_audio_create(
938 struct dc_context *ctx,
939 unsigned int inst,
940 const struct dce_audio_registers *reg,
941 const struct dce_audio_shift *shifts,
942 const struct dce_audio_mask *masks
943 )
944{
945 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL);
946
947 if (audio == NULL) {
948 ASSERT_CRITICAL(audio);
949 return NULL;
950 }
951
952 audio->base.ctx = ctx;
953 audio->base.inst = inst;
954 audio->base.funcs = &funcs;
955
956 audio->regs = reg;
957 audio->shifts = shifts;
958 audio->masks = masks;
959 return &audio->base;
960}
961