Loading...
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __SOC15_H__
25#define __SOC15_H__
26
27#include "nbio_v6_1.h"
28#include "nbio_v7_0.h"
29#include "nbio_v7_4.h"
30#include "amdgpu_reg_state.h"
31
32extern const struct amdgpu_ip_block_version vega10_common_ip_block;
33
34#define SOC15_FLUSH_GPU_TLB_NUM_WREG 6
35#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 3
36
37struct soc15_reg_golden {
38 u32 hwip;
39 u32 instance;
40 u32 segment;
41 u32 reg;
42 u32 and_mask;
43 u32 or_mask;
44};
45
46struct soc15_reg_rlcg {
47 u32 hwip;
48 u32 instance;
49 u32 segment;
50 u32 reg;
51};
52
53struct soc15_reg {
54 uint32_t hwip;
55 uint32_t inst;
56 uint32_t seg;
57 uint32_t reg_offset;
58};
59
60struct soc15_reg_entry {
61 uint32_t hwip;
62 uint32_t inst;
63 uint32_t seg;
64 uint32_t reg_offset;
65 uint32_t reg_value;
66 uint32_t se_num;
67 uint32_t instance;
68};
69
70struct soc15_allowed_register_entry {
71 uint32_t hwip;
72 uint32_t inst;
73 uint32_t seg;
74 uint32_t reg_offset;
75 bool grbm_indexed;
76};
77
78struct soc15_ras_field_entry {
79 const char *name;
80 uint32_t hwip;
81 uint32_t inst;
82 uint32_t seg;
83 uint32_t reg_offset;
84 uint32_t sec_count_mask;
85 uint32_t sec_count_shift;
86 uint32_t ded_count_mask;
87 uint32_t ded_count_shift;
88};
89
90#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
91
92#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
93
94#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
95 { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
96
97#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT
98
99#define SOC15_REG_FIELD_VAL(val, mask, shift) (((val) & mask) >> shift)
100
101#define SOC15_RAS_REG_FIELD_VAL(val, entry, field) SOC15_REG_FIELD_VAL((val), (entry).field##_count_mask, (entry).field##_count_shift)
102
103void soc15_grbm_select(struct amdgpu_device *adev,
104 u32 me, u32 pipe, u32 queue, u32 vmid, int xcc_id);
105void soc15_set_virt_ops(struct amdgpu_device *adev);
106
107void soc15_program_register_sequence(struct amdgpu_device *adev,
108 const struct soc15_reg_golden *registers,
109 const u32 array_size);
110
111int vega10_reg_base_init(struct amdgpu_device *adev);
112int vega20_reg_base_init(struct amdgpu_device *adev);
113int arct_reg_base_init(struct amdgpu_device *adev);
114int aldebaran_reg_base_init(struct amdgpu_device *adev);
115void aqua_vanjaram_ip_map_init(struct amdgpu_device *adev);
116u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id);
117int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev);
118ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev,
119 enum amdgpu_reg_state reg_state, void *buf,
120 size_t max_size);
121
122void vega10_doorbell_index_init(struct amdgpu_device *adev);
123void vega20_doorbell_index_init(struct amdgpu_device *adev);
124void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev);
125#endif
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __SOC15_H__
25#define __SOC15_H__
26
27#include "nbio_v6_1.h"
28#include "nbio_v7_0.h"
29#include "nbio_v7_4.h"
30
31#define SOC15_FLUSH_GPU_TLB_NUM_WREG 6
32#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 3
33
34extern const struct amd_ip_funcs soc15_common_ip_funcs;
35
36struct soc15_reg_golden {
37 u32 hwip;
38 u32 instance;
39 u32 segment;
40 u32 reg;
41 u32 and_mask;
42 u32 or_mask;
43};
44
45struct soc15_reg_rlcg {
46 u32 hwip;
47 u32 instance;
48 u32 segment;
49 u32 reg;
50};
51
52struct soc15_reg_entry {
53 uint32_t hwip;
54 uint32_t inst;
55 uint32_t seg;
56 uint32_t reg_offset;
57 uint32_t reg_value;
58 uint32_t se_num;
59 uint32_t instance;
60};
61
62struct soc15_allowed_register_entry {
63 uint32_t hwip;
64 uint32_t inst;
65 uint32_t seg;
66 uint32_t reg_offset;
67 bool grbm_indexed;
68};
69
70struct soc15_ras_field_entry {
71 const char *name;
72 uint32_t hwip;
73 uint32_t inst;
74 uint32_t seg;
75 uint32_t reg_offset;
76 uint32_t sec_count_mask;
77 uint32_t sec_count_shift;
78 uint32_t ded_count_mask;
79 uint32_t ded_count_shift;
80};
81
82#define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg
83
84#define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset)
85
86#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
87 { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
88
89#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT
90
91void soc15_grbm_select(struct amdgpu_device *adev,
92 u32 me, u32 pipe, u32 queue, u32 vmid);
93void soc15_set_virt_ops(struct amdgpu_device *adev);
94int soc15_set_ip_blocks(struct amdgpu_device *adev);
95
96void soc15_program_register_sequence(struct amdgpu_device *adev,
97 const struct soc15_reg_golden *registers,
98 const u32 array_size);
99
100int vega10_reg_base_init(struct amdgpu_device *adev);
101int vega20_reg_base_init(struct amdgpu_device *adev);
102int arct_reg_base_init(struct amdgpu_device *adev);
103
104void vega10_doorbell_index_init(struct amdgpu_device *adev);
105void vega20_doorbell_index_init(struct amdgpu_device *adev);
106#endif