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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Monk.liu@amd.com
23 */
24#ifndef AMDGPU_VIRT_H
25#define AMDGPU_VIRT_H
26
27#include "amdgv_sriovmsg.h"
28
29#define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
30#define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */
31#define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */
32#define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
33#define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
34#define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */
35
36/* flags for indirect register access path supported by rlcg for sriov */
37#define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28)
38#define AMDGPU_RLCG_GC_WRITE (0x0 << 28)
39#define AMDGPU_RLCG_GC_READ (0x1 << 28)
40#define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28)
41
42/* error code for indirect register access path supported by rlcg for sriov */
43#define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000
44#define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000
45#define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000
46
47#define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF
48#define AMDGPU_RLCG_SCRATCH1_ERROR_MASK 0xF000000
49
50/* all asic after AI use this offset */
51#define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
52/* tonga/fiji use this offset */
53#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
54
55enum amdgpu_sriov_vf_mode {
56 SRIOV_VF_MODE_BARE_METAL = 0,
57 SRIOV_VF_MODE_ONE_VF,
58 SRIOV_VF_MODE_MULTI_VF,
59};
60
61struct amdgpu_mm_table {
62 struct amdgpu_bo *bo;
63 uint32_t *cpu_addr;
64 uint64_t gpu_addr;
65};
66
67#define AMDGPU_VF_ERROR_ENTRY_SIZE 16
68
69/* struct error_entry - amdgpu VF error information. */
70struct amdgpu_vf_error_buffer {
71 struct mutex lock;
72 int read_count;
73 int write_count;
74 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
75 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
76 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
77};
78
79enum idh_request;
80
81/**
82 * struct amdgpu_virt_ops - amdgpu device virt operations
83 */
84struct amdgpu_virt_ops {
85 int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
86 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
87 int (*req_init_data)(struct amdgpu_device *adev);
88 int (*reset_gpu)(struct amdgpu_device *adev);
89 int (*wait_reset)(struct amdgpu_device *adev);
90 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req,
91 u32 data1, u32 data2, u32 data3);
92 void (*ras_poison_handler)(struct amdgpu_device *adev,
93 enum amdgpu_ras_block block);
94};
95
96/*
97 * Firmware Reserve Frame buffer
98 */
99struct amdgpu_virt_fw_reserve {
100 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
101 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
102 unsigned int checksum_key;
103};
104
105/*
106 * Legacy GIM header
107 *
108 * Defination between PF and VF
109 * Structures forcibly aligned to 4 to keep the same style as PF.
110 */
111#define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024)
112
113#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
114 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
115
116enum AMDGIM_FEATURE_FLAG {
117 /* GIM supports feature of Error log collecting */
118 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
119 /* GIM supports feature of loading uCodes */
120 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
121 /* VRAM LOST by GIM */
122 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
123 /* MM bandwidth */
124 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
125 /* PP ONE VF MODE in GIM */
126 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
127 /* Indirect Reg Access enabled */
128 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
129 /* AV1 Support MODE*/
130 AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6),
131 /* VCN RB decouple */
132 AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7),
133};
134
135enum AMDGIM_REG_ACCESS_FLAG {
136 /* Use PSP to program IH_RB_CNTL */
137 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
138 /* Use RLC to program MMHUB regs */
139 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1),
140 /* Use RLC to program GC regs */
141 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2),
142};
143
144struct amdgim_pf2vf_info_v1 {
145 /* header contains size and version */
146 struct amd_sriov_msg_pf2vf_info_header header;
147 /* max_width * max_height */
148 unsigned int uvd_enc_max_pixels_count;
149 /* 16x16 pixels/sec, codec independent */
150 unsigned int uvd_enc_max_bandwidth;
151 /* max_width * max_height */
152 unsigned int vce_enc_max_pixels_count;
153 /* 16x16 pixels/sec, codec independent */
154 unsigned int vce_enc_max_bandwidth;
155 /* MEC FW position in kb from the start of visible frame buffer */
156 unsigned int mecfw_kboffset;
157 /* The features flags of the GIM driver supports. */
158 unsigned int feature_flags;
159 /* use private key from mailbox 2 to create chueksum */
160 unsigned int checksum;
161} __aligned(4);
162
163struct amdgim_vf2pf_info_v1 {
164 /* header contains size and version */
165 struct amd_sriov_msg_vf2pf_info_header header;
166 /* driver version */
167 char driver_version[64];
168 /* driver certification, 1=WHQL, 0=None */
169 unsigned int driver_cert;
170 /* guest OS type and version: need a define */
171 unsigned int os_info;
172 /* in the unit of 1M */
173 unsigned int fb_usage;
174 /* guest gfx engine usage percentage */
175 unsigned int gfx_usage;
176 /* guest gfx engine health percentage */
177 unsigned int gfx_health;
178 /* guest compute engine usage percentage */
179 unsigned int compute_usage;
180 /* guest compute engine health percentage */
181 unsigned int compute_health;
182 /* guest vce engine usage percentage. 0xffff means N/A. */
183 unsigned int vce_enc_usage;
184 /* guest vce engine health percentage. 0xffff means N/A. */
185 unsigned int vce_enc_health;
186 /* guest uvd engine usage percentage. 0xffff means N/A. */
187 unsigned int uvd_enc_usage;
188 /* guest uvd engine usage percentage. 0xffff means N/A. */
189 unsigned int uvd_enc_health;
190 unsigned int checksum;
191} __aligned(4);
192
193struct amdgim_vf2pf_info_v2 {
194 /* header contains size and version */
195 struct amd_sriov_msg_vf2pf_info_header header;
196 uint32_t checksum;
197 /* driver version */
198 uint8_t driver_version[64];
199 /* driver certification, 1=WHQL, 0=None */
200 uint32_t driver_cert;
201 /* guest OS type and version: need a define */
202 uint32_t os_info;
203 /* in the unit of 1M */
204 uint32_t fb_usage;
205 /* guest gfx engine usage percentage */
206 uint32_t gfx_usage;
207 /* guest gfx engine health percentage */
208 uint32_t gfx_health;
209 /* guest compute engine usage percentage */
210 uint32_t compute_usage;
211 /* guest compute engine health percentage */
212 uint32_t compute_health;
213 /* guest vce engine usage percentage. 0xffff means N/A. */
214 uint32_t vce_enc_usage;
215 /* guest vce engine health percentage. 0xffff means N/A. */
216 uint32_t vce_enc_health;
217 /* guest uvd engine usage percentage. 0xffff means N/A. */
218 uint32_t uvd_enc_usage;
219 /* guest uvd engine usage percentage. 0xffff means N/A. */
220 uint32_t uvd_enc_health;
221 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
222} __aligned(4);
223
224struct amdgpu_virt_ras_err_handler_data {
225 /* point to bad page records array */
226 struct eeprom_table_record *bps;
227 /* point to reserved bo array */
228 struct amdgpu_bo **bps_bo;
229 /* the count of entries */
230 int count;
231 /* last reserved entry's index + 1 */
232 int last_reserved;
233};
234
235/* GPU virtualization */
236struct amdgpu_virt {
237 uint32_t caps;
238 struct amdgpu_bo *csa_obj;
239 void *csa_cpu_addr;
240 bool chained_ib_support;
241 uint32_t reg_val_offs;
242 struct amdgpu_irq_src ack_irq;
243 struct amdgpu_irq_src rcv_irq;
244 struct work_struct flr_work;
245 struct amdgpu_mm_table mm_table;
246 const struct amdgpu_virt_ops *ops;
247 struct amdgpu_vf_error_buffer vf_errors;
248 struct amdgpu_virt_fw_reserve fw_reserve;
249 uint32_t gim_feature;
250 uint32_t reg_access_mode;
251 int req_init_data_ver;
252 bool tdr_debug;
253 struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
254 bool ras_init_done;
255 uint32_t reg_access;
256
257 /* vf2pf message */
258 struct delayed_work vf2pf_work;
259 uint32_t vf2pf_update_interval_ms;
260
261 /* multimedia bandwidth config */
262 bool is_mm_bw_enabled;
263 uint32_t decode_max_dimension_pixels;
264 uint32_t decode_max_frame_pixels;
265 uint32_t encode_max_dimension_pixels;
266 uint32_t encode_max_frame_pixels;
267
268 /* the ucode id to signal the autoload */
269 uint32_t autoload_ucode_id;
270};
271
272struct amdgpu_video_codec_info;
273
274#define amdgpu_sriov_enabled(adev) \
275((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
276
277#define amdgpu_sriov_vf(adev) \
278((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
279
280#define amdgpu_sriov_bios(adev) \
281((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
282
283#define amdgpu_sriov_runtime(adev) \
284((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
285
286#define amdgpu_sriov_fullaccess(adev) \
287(amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
288
289#define amdgpu_sriov_reg_indirect_en(adev) \
290(amdgpu_sriov_vf((adev)) && \
291 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))
292
293#define amdgpu_sriov_reg_indirect_ih(adev) \
294(amdgpu_sriov_vf((adev)) && \
295 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))
296
297#define amdgpu_sriov_reg_indirect_mmhub(adev) \
298(amdgpu_sriov_vf((adev)) && \
299 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))
300
301#define amdgpu_sriov_reg_indirect_gc(adev) \
302(amdgpu_sriov_vf((adev)) && \
303 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
304
305#define amdgpu_sriov_rlcg_error_report_enabled(adev) \
306 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
307
308#define amdgpu_passthrough(adev) \
309((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
310
311#define amdgpu_sriov_vf_mmio_access_protection(adev) \
312((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
313
314static inline bool is_virtual_machine(void)
315{
316#if defined(CONFIG_X86)
317 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
318#elif defined(CONFIG_ARM64)
319 return !is_kernel_in_hyp_mode();
320#else
321 return false;
322#endif
323}
324
325#define amdgpu_sriov_is_pp_one_vf(adev) \
326 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
327#define amdgpu_sriov_is_debug(adev) \
328 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
329#define amdgpu_sriov_is_normal(adev) \
330 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
331#define amdgpu_sriov_is_av1_support(adev) \
332 ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
333#define amdgpu_sriov_is_vcn_rb_decouple(adev) \
334 ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE)
335bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
336void amdgpu_virt_init_setting(struct amdgpu_device *adev);
337int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
338int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
339int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
340void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
341int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
342int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
343void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
344void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
345void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
346void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
347void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
348void amdgpu_detect_virtualization(struct amdgpu_device *adev);
349
350bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
351int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
352void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
353
354enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
355
356void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
357 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
358 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
359void amdgpu_sriov_wreg(struct amdgpu_device *adev,
360 u32 offset, u32 value,
361 u32 acc_flags, u32 hwip, u32 xcc_id);
362u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
363 u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);
364bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
365 uint32_t ucode_id);
366void amdgpu_virt_post_reset(struct amdgpu_device *adev);
367bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev);
368bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
369 u32 acc_flags, u32 hwip,
370 bool write, u32 *rlcg_flag);
371u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);
372#endif
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Monk.liu@amd.com
23 */
24#ifndef AMDGPU_VIRT_H
25#define AMDGPU_VIRT_H
26
27#define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
28#define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */
29#define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */
30#define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
31#define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
32
33/* all asic after AI use this offset */
34#define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
35/* tonga/fiji use this offset */
36#define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
37
38enum amdgpu_sriov_vf_mode {
39 SRIOV_VF_MODE_BARE_METAL = 0,
40 SRIOV_VF_MODE_ONE_VF,
41 SRIOV_VF_MODE_MULTI_VF,
42};
43
44struct amdgpu_mm_table {
45 struct amdgpu_bo *bo;
46 uint32_t *cpu_addr;
47 uint64_t gpu_addr;
48};
49
50#define AMDGPU_VF_ERROR_ENTRY_SIZE 16
51
52/* struct error_entry - amdgpu VF error information. */
53struct amdgpu_vf_error_buffer {
54 struct mutex lock;
55 int read_count;
56 int write_count;
57 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
58 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
59 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
60};
61
62/**
63 * struct amdgpu_virt_ops - amdgpu device virt operations
64 */
65struct amdgpu_virt_ops {
66 int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
67 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
68 int (*req_init_data)(struct amdgpu_device *adev);
69 int (*reset_gpu)(struct amdgpu_device *adev);
70 int (*wait_reset)(struct amdgpu_device *adev);
71 void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
72};
73
74/*
75 * Firmware Reserve Frame buffer
76 */
77struct amdgpu_virt_fw_reserve {
78 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
79 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
80 unsigned int checksum_key;
81};
82/*
83 * Defination between PF and VF
84 * Structures forcibly aligned to 4 to keep the same style as PF.
85 */
86#define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024)
87
88#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
89 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
90
91enum AMDGIM_FEATURE_FLAG {
92 /* GIM supports feature of Error log collecting */
93 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
94 /* GIM supports feature of loading uCodes */
95 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
96 /* VRAM LOST by GIM */
97 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
98 /* MM bandwidth */
99 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
100 /* PP ONE VF MODE in GIM */
101 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
102};
103
104struct amd_sriov_msg_pf2vf_info_header {
105 /* the total structure size in byte. */
106 uint32_t size;
107 /* version of this structure, written by the GIM */
108 uint32_t version;
109 /* reserved */
110 uint32_t reserved[2];
111} __aligned(4);
112struct amdgim_pf2vf_info_v1 {
113 /* header contains size and version */
114 struct amd_sriov_msg_pf2vf_info_header header;
115 /* max_width * max_height */
116 unsigned int uvd_enc_max_pixels_count;
117 /* 16x16 pixels/sec, codec independent */
118 unsigned int uvd_enc_max_bandwidth;
119 /* max_width * max_height */
120 unsigned int vce_enc_max_pixels_count;
121 /* 16x16 pixels/sec, codec independent */
122 unsigned int vce_enc_max_bandwidth;
123 /* MEC FW position in kb from the start of visible frame buffer */
124 unsigned int mecfw_kboffset;
125 /* The features flags of the GIM driver supports. */
126 unsigned int feature_flags;
127 /* use private key from mailbox 2 to create chueksum */
128 unsigned int checksum;
129} __aligned(4);
130
131struct amdgim_pf2vf_info_v2 {
132 /* header contains size and version */
133 struct amd_sriov_msg_pf2vf_info_header header;
134 /* use private key from mailbox 2 to create chueksum */
135 uint32_t checksum;
136 /* The features flags of the GIM driver supports. */
137 uint32_t feature_flags;
138 /* max_width * max_height */
139 uint32_t uvd_enc_max_pixels_count;
140 /* 16x16 pixels/sec, codec independent */
141 uint32_t uvd_enc_max_bandwidth;
142 /* max_width * max_height */
143 uint32_t vce_enc_max_pixels_count;
144 /* 16x16 pixels/sec, codec independent */
145 uint32_t vce_enc_max_bandwidth;
146 /* Bad pages block position in BYTE */
147 uint32_t bp_block_offset_L;
148 uint32_t bp_block_offset_H;
149 /* Bad pages block size in BYTE */
150 uint32_t bp_block_size;
151 /* MEC FW position in kb from the start of VF visible frame buffer */
152 uint32_t mecfw_kboffset_L;
153 uint32_t mecfw_kboffset_H;
154 /* MEC FW size in KB */
155 uint32_t mecfw_ksize;
156 /* UVD FW position in kb from the start of VF visible frame buffer */
157 uint32_t uvdfw_kboffset_L;
158 uint32_t uvdfw_kboffset_H;
159 /* UVD FW size in KB */
160 uint32_t uvdfw_ksize;
161 /* VCE FW position in kb from the start of VF visible frame buffer */
162 uint32_t vcefw_kboffset_L;
163 uint32_t vcefw_kboffset_H;
164 /* VCE FW size in KB */
165 uint32_t vcefw_ksize;
166 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 0, 0, (18 + sizeof(struct amd_sriov_msg_pf2vf_info_header)/sizeof(uint32_t)), 0)];
167} __aligned(4);
168
169
170struct amd_sriov_msg_vf2pf_info_header {
171 /* the total structure size in byte. */
172 uint32_t size;
173 /*version of this structure, written by the guest */
174 uint32_t version;
175 /* reserved */
176 uint32_t reserved[2];
177} __aligned(4);
178
179struct amdgim_vf2pf_info_v1 {
180 /* header contains size and version */
181 struct amd_sriov_msg_vf2pf_info_header header;
182 /* driver version */
183 char driver_version[64];
184 /* driver certification, 1=WHQL, 0=None */
185 unsigned int driver_cert;
186 /* guest OS type and version: need a define */
187 unsigned int os_info;
188 /* in the unit of 1M */
189 unsigned int fb_usage;
190 /* guest gfx engine usage percentage */
191 unsigned int gfx_usage;
192 /* guest gfx engine health percentage */
193 unsigned int gfx_health;
194 /* guest compute engine usage percentage */
195 unsigned int compute_usage;
196 /* guest compute engine health percentage */
197 unsigned int compute_health;
198 /* guest vce engine usage percentage. 0xffff means N/A. */
199 unsigned int vce_enc_usage;
200 /* guest vce engine health percentage. 0xffff means N/A. */
201 unsigned int vce_enc_health;
202 /* guest uvd engine usage percentage. 0xffff means N/A. */
203 unsigned int uvd_enc_usage;
204 /* guest uvd engine usage percentage. 0xffff means N/A. */
205 unsigned int uvd_enc_health;
206 unsigned int checksum;
207} __aligned(4);
208
209struct amdgim_vf2pf_info_v2 {
210 /* header contains size and version */
211 struct amd_sriov_msg_vf2pf_info_header header;
212 uint32_t checksum;
213 /* driver version */
214 uint8_t driver_version[64];
215 /* driver certification, 1=WHQL, 0=None */
216 uint32_t driver_cert;
217 /* guest OS type and version: need a define */
218 uint32_t os_info;
219 /* in the unit of 1M */
220 uint32_t fb_usage;
221 /* guest gfx engine usage percentage */
222 uint32_t gfx_usage;
223 /* guest gfx engine health percentage */
224 uint32_t gfx_health;
225 /* guest compute engine usage percentage */
226 uint32_t compute_usage;
227 /* guest compute engine health percentage */
228 uint32_t compute_health;
229 /* guest vce engine usage percentage. 0xffff means N/A. */
230 uint32_t vce_enc_usage;
231 /* guest vce engine health percentage. 0xffff means N/A. */
232 uint32_t vce_enc_health;
233 /* guest uvd engine usage percentage. 0xffff means N/A. */
234 uint32_t uvd_enc_usage;
235 /* guest uvd engine usage percentage. 0xffff means N/A. */
236 uint32_t uvd_enc_health;
237 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
238} __aligned(4);
239
240#define AMDGPU_FW_VRAM_VF2PF_VER 2
241typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
242
243#define AMDGPU_FW_VRAM_VF2PF_WRITE(adev, field, val) \
244 do { \
245 ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field = (val); \
246 } while (0)
247
248#define AMDGPU_FW_VRAM_VF2PF_READ(adev, field, val) \
249 do { \
250 (*val) = ((amdgim_vf2pf_info *)adev->virt.fw_reserve.p_vf2pf)->field; \
251 } while (0)
252
253#define AMDGPU_FW_VRAM_PF2VF_READ(adev, field, val) \
254 do { \
255 if (!adev->virt.fw_reserve.p_pf2vf) \
256 *(val) = 0; \
257 else { \
258 if (adev->virt.fw_reserve.p_pf2vf->version == 1) \
259 *(val) = ((struct amdgim_pf2vf_info_v1 *)adev->virt.fw_reserve.p_pf2vf)->field; \
260 if (adev->virt.fw_reserve.p_pf2vf->version == 2) \
261 *(val) = ((struct amdgim_pf2vf_info_v2 *)adev->virt.fw_reserve.p_pf2vf)->field; \
262 } \
263 } while (0)
264
265struct amdgpu_virt_ras_err_handler_data {
266 /* point to bad page records array */
267 struct eeprom_table_record *bps;
268 /* point to reserved bo array */
269 struct amdgpu_bo **bps_bo;
270 /* the count of entries */
271 int count;
272 /* last reserved entry's index + 1 */
273 int last_reserved;
274};
275
276/* GPU virtualization */
277struct amdgpu_virt {
278 uint32_t caps;
279 struct amdgpu_bo *csa_obj;
280 void *csa_cpu_addr;
281 bool chained_ib_support;
282 uint32_t reg_val_offs;
283 struct amdgpu_irq_src ack_irq;
284 struct amdgpu_irq_src rcv_irq;
285 struct work_struct flr_work;
286 struct amdgpu_mm_table mm_table;
287 const struct amdgpu_virt_ops *ops;
288 struct amdgpu_vf_error_buffer vf_errors;
289 struct amdgpu_virt_fw_reserve fw_reserve;
290 uint32_t gim_feature;
291 uint32_t reg_access_mode;
292 int req_init_data_ver;
293 bool tdr_debug;
294 struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
295 bool ras_init_done;
296};
297
298#define amdgpu_sriov_enabled(adev) \
299((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
300
301#define amdgpu_sriov_vf(adev) \
302((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
303
304#define amdgpu_sriov_bios(adev) \
305((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
306
307#define amdgpu_sriov_runtime(adev) \
308((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
309
310#define amdgpu_sriov_fullaccess(adev) \
311(amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
312
313#define amdgpu_passthrough(adev) \
314((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
315
316static inline bool is_virtual_machine(void)
317{
318#ifdef CONFIG_X86
319 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
320#else
321 return false;
322#endif
323}
324
325#define amdgpu_sriov_is_pp_one_vf(adev) \
326 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
327#define amdgpu_sriov_is_debug(adev) \
328 ((!adev->in_gpu_reset) && adev->virt.tdr_debug)
329#define amdgpu_sriov_is_normal(adev) \
330 ((!adev->in_gpu_reset) && (!adev->virt.tdr_debug))
331
332bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
333void amdgpu_virt_init_setting(struct amdgpu_device *adev);
334void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
335 uint32_t reg0, uint32_t rreg1,
336 uint32_t ref, uint32_t mask);
337int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
338int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
339int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
340void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
341int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
342int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
343void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
344int amdgpu_virt_fw_reserve_get_checksum(void *obj, unsigned long obj_size,
345 unsigned int key,
346 unsigned int chksum);
347void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
348void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
349void amdgpu_detect_virtualization(struct amdgpu_device *adev);
350
351bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
352int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
353void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
354
355enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
356#endif