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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __ASM_POWERPC_CPUTABLE_H
3#define __ASM_POWERPC_CPUTABLE_H
4
5
6#include <linux/types.h>
7#include <uapi/asm/cputable.h>
8#include <asm/asm-const.h>
9
10#ifndef __ASSEMBLY__
11
12/* This structure can grow, it's real size is used by head.S code
13 * via the mkdefs mechanism.
14 */
15struct cpu_spec;
16
17typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
18typedef void (*cpu_restore_t)(void);
19
20enum powerpc_pmc_type {
21 PPC_PMC_DEFAULT = 0,
22 PPC_PMC_IBM = 1,
23 PPC_PMC_PA6T = 2,
24 PPC_PMC_G4 = 3,
25};
26
27struct pt_regs;
28
29extern int machine_check_generic(struct pt_regs *regs);
30extern int machine_check_4xx(struct pt_regs *regs);
31extern int machine_check_440A(struct pt_regs *regs);
32extern int machine_check_e500mc(struct pt_regs *regs);
33extern int machine_check_e500(struct pt_regs *regs);
34extern int machine_check_47x(struct pt_regs *regs);
35int machine_check_8xx(struct pt_regs *regs);
36int machine_check_83xx(struct pt_regs *regs);
37
38extern void cpu_down_flush_e500v2(void);
39extern void cpu_down_flush_e500mc(void);
40extern void cpu_down_flush_e5500(void);
41extern void cpu_down_flush_e6500(void);
42
43/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
44struct cpu_spec {
45 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
46 unsigned int pvr_mask;
47 unsigned int pvr_value;
48
49 char *cpu_name;
50 unsigned long cpu_features; /* Kernel features */
51 unsigned int cpu_user_features; /* Userland features */
52 unsigned int cpu_user_features2; /* Userland features v2 */
53 unsigned int mmu_features; /* MMU features */
54
55 /* cache line sizes */
56 unsigned int icache_bsize;
57 unsigned int dcache_bsize;
58
59 /* flush caches inside the current cpu */
60 void (*cpu_down_flush)(void);
61
62 /* number of performance monitor counters */
63 unsigned int num_pmcs;
64 enum powerpc_pmc_type pmc_type;
65
66 /* this is called to initialize various CPU bits like L1 cache,
67 * BHT, SPD, etc... from head.S before branching to identify_machine
68 */
69 cpu_setup_t cpu_setup;
70 /* Used to restore cpu setup on secondary processors and at resume */
71 cpu_restore_t cpu_restore;
72
73 /* Name of processor class, for the ELF AT_PLATFORM entry */
74 char *platform;
75
76 /* Processor specific machine check handling. Return negative
77 * if the error is fatal, 1 if it was fully recovered and 0 to
78 * pass up (not CPU originated) */
79 int (*machine_check)(struct pt_regs *regs);
80
81 /*
82 * Processor specific early machine check handler which is
83 * called in real mode to handle SLB and TLB errors.
84 */
85 long (*machine_check_early)(struct pt_regs *regs);
86};
87
88extern struct cpu_spec *cur_cpu_spec;
89
90extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
91
92extern void set_cur_cpu_spec(struct cpu_spec *s);
93extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
94extern void identify_cpu_name(unsigned int pvr);
95extern void do_feature_fixups(unsigned long value, void *fixup_start,
96 void *fixup_end);
97
98extern const char *powerpc_base_platform;
99
100#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
101extern void cpu_feature_keys_init(void);
102#else
103static inline void cpu_feature_keys_init(void) { }
104#endif
105
106#endif /* __ASSEMBLY__ */
107
108/* CPU kernel features */
109
110/* Definitions for features that we have on both 32-bit and 64-bit chips */
111#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
112#define CPU_FTR_ALTIVEC ASM_CONST(0x00000002)
113#define CPU_FTR_DBELL ASM_CONST(0x00000004)
114#define CPU_FTR_CAN_NAP ASM_CONST(0x00000008)
115#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010)
116// ASM_CONST(0x00000020) Free
117#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040)
118#define CPU_FTR_LWSYNC ASM_CONST(0x00000080)
119#define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100)
120#define CPU_FTR_EMB_HV ASM_CONST(0x00000200)
121
122/* Definitions for features that only exist on 32-bit chips */
123#ifdef CONFIG_PPC32
124#define CPU_FTR_L2CR ASM_CONST(0x00002000)
125#define CPU_FTR_SPEC7450 ASM_CONST(0x00004000)
126#define CPU_FTR_TAU ASM_CONST(0x00008000)
127#define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000)
128#define CPU_FTR_L3CR ASM_CONST(0x00040000)
129#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000)
130#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000)
131#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000)
132#define CPU_FTR_NO_DPM ASM_CONST(0x00400000)
133#define CPU_FTR_476_DD2 ASM_CONST(0x00800000)
134#define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000)
135#define CPU_FTR_NO_BTIC ASM_CONST(0x02000000)
136#define CPU_FTR_PPC_LE ASM_CONST(0x04000000)
137#define CPU_FTR_SPE ASM_CONST(0x10000000)
138#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000)
139#define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000)
140
141#else /* CONFIG_PPC32 */
142/* Define these to 0 for the sake of tests in common code */
143#define CPU_FTR_PPC_LE (0)
144#define CPU_FTR_SPE (0)
145#endif
146
147/*
148 * Definitions for the 64-bit processor unique features;
149 * on 32-bit, make the names available but defined to be 0.
150 */
151#ifdef __powerpc64__
152#define LONG_ASM_CONST(x) ASM_CONST(x)
153#else
154#define LONG_ASM_CONST(x) 0
155#endif
156
157#define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000)
158#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000)
159#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000)
160#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000)
161#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000)
162#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000)
163#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000)
164#define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000)
165#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000)
166#define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000)
167#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000)
168#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)
169#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)
170#define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)
171#define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000)
172#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)
173#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)
174#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)
175#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000)
176#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000)
177#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000)
178/* LONG_ASM_CONST(0x0000000400000000) Free */
179#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000)
180#define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000)
181#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000)
182#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000)
183#define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000)
184#define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000)
185#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000)
186#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000)
187#define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000)
188#define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000)
189#define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000)
190#define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000)
191#define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000)
192#define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000)
193#define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000)
194#define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000)
195#define CPU_FTR_DEXCR_NPHIE LONG_ASM_CONST(0x0010000000000000)
196
197#ifndef __ASSEMBLY__
198
199#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE)
200
201/* We only set the altivec features if the kernel was compiled with altivec
202 * support
203 */
204#ifdef CONFIG_ALTIVEC
205#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
206#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
207#else
208#define CPU_FTR_ALTIVEC_COMP 0
209#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
210#endif
211
212/* We only set the VSX features if the kernel was compiled with VSX
213 * support
214 */
215#ifdef CONFIG_VSX
216#define CPU_FTR_VSX_COMP CPU_FTR_VSX
217#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
218#else
219#define CPU_FTR_VSX_COMP 0
220#define PPC_FEATURE_HAS_VSX_COMP 0
221#endif
222
223/* We only set the spe features if the kernel was compiled with spe
224 * support
225 */
226#ifdef CONFIG_SPE
227#define CPU_FTR_SPE_COMP CPU_FTR_SPE
228#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
229#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
230#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
231#else
232#define CPU_FTR_SPE_COMP 0
233#define PPC_FEATURE_HAS_SPE_COMP 0
234#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
235#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
236#endif
237
238/* We only set the TM feature if the kernel was compiled with TM supprt */
239#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
240#define CPU_FTR_TM_COMP CPU_FTR_TM
241#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
242#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
243#else
244#define CPU_FTR_TM_COMP 0
245#define PPC_FEATURE2_HTM_COMP 0
246#define PPC_FEATURE2_HTM_NOSC_COMP 0
247#endif
248
249/* We need to mark all pages as being coherent if we're SMP or we have a
250 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
251 * require it for PCI "streaming/prefetch" to work properly.
252 * This is also required by 52xx family.
253 */
254#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
255 || defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_82xx) \
256 || defined(CONFIG_PPC_MPC52xx)
257#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
258#else
259#define CPU_FTR_COMMON 0
260#endif
261
262/* The powersave features NAP & DOZE seems to confuse BDI when
263 debugging. So if a BDI is used, disable theses
264 */
265#ifndef CONFIG_BDI_SWITCH
266#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
267#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
268#else
269#define CPU_FTR_MAYBE_CAN_DOZE 0
270#define CPU_FTR_MAYBE_CAN_NAP 0
271#endif
272
273#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
274 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE)
275#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE)
276#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
277 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
278 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
279#define CPU_FTRS_740 (CPU_FTR_COMMON | \
280 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
281 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
282 CPU_FTR_PPC_LE)
283#define CPU_FTRS_750 (CPU_FTR_COMMON | \
284 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
285 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
286 CPU_FTR_PPC_LE)
287#define CPU_FTRS_750CL (CPU_FTRS_750)
288#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
289#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
290#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
291#define CPU_FTRS_750GX (CPU_FTRS_750FX)
292#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
293 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
294 CPU_FTR_ALTIVEC_COMP | \
295 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
296#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
297 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
298 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
299 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
300#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
301 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
302 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
303 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
304#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
305 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
306 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
307 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
308 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
309#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
310 CPU_FTR_NEED_PAIRED_STWCX | \
311 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
312 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
313 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
314#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
315 CPU_FTR_NEED_PAIRED_STWCX | \
316 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
317 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
318#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
319 CPU_FTR_NEED_PAIRED_STWCX | \
320 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
321 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
322 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
323 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
324#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
325 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
326 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
327 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
328#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
329 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
330 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
331 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
332 CPU_FTR_NEED_PAIRED_STWCX)
333#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
334 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
335 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
336 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
337#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
338 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
339 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
340 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
341#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
342 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
343 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
344 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
345#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
346#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
347 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NOEXECUTE)
348#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
349 CPU_FTR_MAYBE_CAN_NAP | \
350 CPU_FTR_COMMON | CPU_FTR_NOEXECUTE)
351#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
352 CPU_FTR_MAYBE_CAN_NAP | \
353 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE)
354#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON)
355#define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE)
356#define CPU_FTRS_40X (CPU_FTR_NOEXECUTE)
357#define CPU_FTRS_44X (CPU_FTR_NOEXECUTE)
358#define CPU_FTRS_440x6 (CPU_FTR_NOEXECUTE | \
359 CPU_FTR_INDEXED_DCR)
360#define CPU_FTRS_47X (CPU_FTRS_440x6)
361#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \
362 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
363 CPU_FTR_NOEXECUTE)
364#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \
365 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
366 CPU_FTR_NOEXECUTE)
367#define CPU_FTRS_E500MC ( \
368 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
369 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
370/*
371 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
372 * same workaround as CPU_FTR_CELL_TB_BUG.
373 */
374#define CPU_FTRS_E5500 ( \
375 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
376 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
377 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
378#define CPU_FTRS_E6500 ( \
379 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
380 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
381 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
382 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
383
384/* 64-bit CPUs */
385#define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
386 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
387 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
388 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
389 CPU_FTR_HVMODE | CPU_FTR_DABRX)
390#define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \
391 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
392 CPU_FTR_MMCRA | CPU_FTR_SMT | \
393 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
394 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
395#define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \
396 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
397 CPU_FTR_MMCRA | CPU_FTR_SMT | \
398 CPU_FTR_COHERENT_ICACHE | \
399 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
400 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
401 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
402 CPU_FTR_DABRX)
403#define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \
404 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
405 CPU_FTR_MMCRA | CPU_FTR_SMT | \
406 CPU_FTR_COHERENT_ICACHE | \
407 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
408 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
409 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
410 CPU_FTR_CFAR | CPU_FTR_HVMODE | \
411 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX )
412#define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
413 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
414 CPU_FTR_MMCRA | CPU_FTR_SMT | \
415 CPU_FTR_COHERENT_ICACHE | \
416 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
417 CPU_FTR_DSCR | CPU_FTR_SAO | \
418 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
419 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
420 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
421 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP )
422#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
423#define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
424 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
425 CPU_FTR_MMCRA | CPU_FTR_SMT | \
426 CPU_FTR_COHERENT_ICACHE | \
427 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
428 CPU_FTR_DSCR | CPU_FTR_SAO | \
429 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
430 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
431 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
432 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \
433 CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR)
434#define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG)
435#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \
436 CPU_FTR_P9_RADIX_PREFETCH_BUG | \
437 CPU_FTR_POWER9_DD2_1)
438#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
439 CPU_FTR_P9_TM_HV_ASSIST | \
440 CPU_FTR_P9_TM_XER_SO_BUG)
441#define CPU_FTRS_POWER9_DD2_3 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
442 CPU_FTR_P9_TM_HV_ASSIST | \
443 CPU_FTR_P9_TM_XER_SO_BUG | \
444 CPU_FTR_DAWR)
445#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
446 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
447 CPU_FTR_MMCRA | CPU_FTR_SMT | \
448 CPU_FTR_COHERENT_ICACHE | \
449 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
450 CPU_FTR_DSCR | CPU_FTR_SAO | \
451 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
452 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
453 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
454 CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
455 CPU_FTR_DAWR | CPU_FTR_DAWR1 | \
456 CPU_FTR_DEXCR_NPHIE)
457
458#define CPU_FTRS_POWER11 CPU_FTRS_POWER10
459
460#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
461 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
462 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
463 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
464 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
465#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
466 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
467 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
468#define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2)
469
470#ifdef CONFIG_PPC64
471#ifdef CONFIG_PPC_BOOK3E_64
472#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
473#else
474#ifdef CONFIG_CPU_LITTLE_ENDIAN
475#define CPU_FTRS_POSSIBLE \
476 (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
477 CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
478 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | \
479 CPU_FTRS_POWER9_DD2_3 | CPU_FTRS_POWER10)
480#else
481#define CPU_FTRS_POSSIBLE \
482 (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
483 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
484 CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
485 CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
486 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | \
487 CPU_FTRS_POWER9_DD2_3 | CPU_FTRS_POWER10)
488#endif /* CONFIG_CPU_LITTLE_ENDIAN */
489#endif
490#else
491enum {
492 CPU_FTRS_POSSIBLE =
493#ifdef CONFIG_PPC_BOOK3S_604
494 CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
495 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
496 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
497 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
498 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
499 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
500 CPU_FTRS_7447 | CPU_FTRS_7447A |
501 CPU_FTRS_CLASSIC32 |
502#endif
503#ifdef CONFIG_PPC_BOOK3S_603
504 CPU_FTRS_603 | CPU_FTRS_82XX |
505 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
506#endif
507#ifdef CONFIG_PPC_8xx
508 CPU_FTRS_8XX |
509#endif
510#ifdef CONFIG_40x
511 CPU_FTRS_40X |
512#endif
513#ifdef CONFIG_PPC_47x
514 CPU_FTRS_47X | CPU_FTR_476_DD2 |
515#elif defined(CONFIG_44x)
516 CPU_FTRS_44X | CPU_FTRS_440x6 |
517#endif
518#ifdef CONFIG_PPC_E500
519 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
520#endif
521#ifdef CONFIG_PPC_E500MC
522 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
523#endif
524 0,
525};
526#endif /* __powerpc64__ */
527
528#ifdef CONFIG_PPC64
529#ifdef CONFIG_PPC_BOOK3E_64
530#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
531#else
532
533#ifdef CONFIG_PPC_DT_CPU_FTRS
534#define CPU_FTRS_DT_CPU_BASE \
535 (CPU_FTR_LWSYNC | \
536 CPU_FTR_FPU_UNAVAILABLE | \
537 CPU_FTR_NOEXECUTE | \
538 CPU_FTR_COHERENT_ICACHE | \
539 CPU_FTR_STCX_CHECKS_ADDRESS | \
540 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
541 CPU_FTR_DAWR | \
542 CPU_FTR_ARCH_206 | \
543 CPU_FTR_ARCH_207S)
544#else
545#define CPU_FTRS_DT_CPU_BASE (~0ul)
546#endif
547
548/* pseries may disable DBELL with ibm,pi-features */
549#ifdef CONFIG_CPU_LITTLE_ENDIAN
550#define CPU_FTRS_ALWAYS \
551 (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & ~CPU_FTR_DBELL & \
552 CPU_FTRS_POWER7 & CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & \
553 CPU_FTRS_POWER9 & CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_POWER9_DD2_2 & \
554 CPU_FTRS_POWER10 & CPU_FTRS_DT_CPU_BASE)
555#else
556#define CPU_FTRS_ALWAYS \
557 (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
558 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
559 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
560 ~CPU_FTR_HVMODE & ~CPU_FTR_DBELL & CPU_FTRS_POSSIBLE & \
561 CPU_FTRS_POWER9 & CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_POWER9_DD2_2 & \
562 CPU_FTRS_POWER10 & CPU_FTRS_DT_CPU_BASE)
563#endif /* CONFIG_CPU_LITTLE_ENDIAN */
564#endif
565#else
566enum {
567 CPU_FTRS_ALWAYS =
568#ifdef CONFIG_PPC_BOOK3S_604
569 CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
570 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
571 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
572 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
573 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
574 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
575 CPU_FTRS_7447 & CPU_FTRS_7447A &
576 CPU_FTRS_CLASSIC32 &
577#endif
578#ifdef CONFIG_PPC_BOOK3S_603
579 CPU_FTRS_603 & CPU_FTRS_82XX &
580 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
581#endif
582#ifdef CONFIG_PPC_8xx
583 CPU_FTRS_8XX &
584#endif
585#ifdef CONFIG_40x
586 CPU_FTRS_40X &
587#endif
588#ifdef CONFIG_PPC_47x
589 CPU_FTRS_47X &
590#elif defined(CONFIG_44x)
591 CPU_FTRS_44X & CPU_FTRS_440x6 &
592#endif
593#ifdef CONFIG_PPC_E500
594 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
595#endif
596#ifdef CONFIG_PPC_E500MC
597 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
598#endif
599 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
600 CPU_FTRS_POSSIBLE,
601};
602#endif /* __powerpc64__ */
603
604/*
605 * Maximum number of hw breakpoint supported on powerpc. Number of
606 * breakpoints supported by actual hw might be less than this, which
607 * is decided at run time in nr_wp_slots().
608 */
609#define HBP_NUM_MAX 2
610
611#endif /* !__ASSEMBLY__ */
612
613#endif /* __ASM_POWERPC_CPUTABLE_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __ASM_POWERPC_CPUTABLE_H
3#define __ASM_POWERPC_CPUTABLE_H
4
5
6#include <linux/types.h>
7#include <uapi/asm/cputable.h>
8#include <asm/asm-const.h>
9
10#ifndef __ASSEMBLY__
11
12/*
13 * Added to include __machine_check_early_realmode_* functions
14 */
15#include <asm/mce.h>
16
17/* This structure can grow, it's real size is used by head.S code
18 * via the mkdefs mechanism.
19 */
20struct cpu_spec;
21
22typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
23typedef void (*cpu_restore_t)(void);
24
25enum powerpc_oprofile_type {
26 PPC_OPROFILE_INVALID = 0,
27 PPC_OPROFILE_RS64 = 1,
28 PPC_OPROFILE_POWER4 = 2,
29 PPC_OPROFILE_G4 = 3,
30 PPC_OPROFILE_FSL_EMB = 4,
31 PPC_OPROFILE_CELL = 5,
32 PPC_OPROFILE_PA6T = 6,
33};
34
35enum powerpc_pmc_type {
36 PPC_PMC_DEFAULT = 0,
37 PPC_PMC_IBM = 1,
38 PPC_PMC_PA6T = 2,
39 PPC_PMC_G4 = 3,
40};
41
42struct pt_regs;
43
44extern int machine_check_generic(struct pt_regs *regs);
45extern int machine_check_4xx(struct pt_regs *regs);
46extern int machine_check_440A(struct pt_regs *regs);
47extern int machine_check_e500mc(struct pt_regs *regs);
48extern int machine_check_e500(struct pt_regs *regs);
49extern int machine_check_e200(struct pt_regs *regs);
50extern int machine_check_47x(struct pt_regs *regs);
51int machine_check_8xx(struct pt_regs *regs);
52int machine_check_83xx(struct pt_regs *regs);
53
54extern void cpu_down_flush_e500v2(void);
55extern void cpu_down_flush_e500mc(void);
56extern void cpu_down_flush_e5500(void);
57extern void cpu_down_flush_e6500(void);
58
59/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
60struct cpu_spec {
61 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
62 unsigned int pvr_mask;
63 unsigned int pvr_value;
64
65 char *cpu_name;
66 unsigned long cpu_features; /* Kernel features */
67 unsigned int cpu_user_features; /* Userland features */
68 unsigned int cpu_user_features2; /* Userland features v2 */
69 unsigned int mmu_features; /* MMU features */
70
71 /* cache line sizes */
72 unsigned int icache_bsize;
73 unsigned int dcache_bsize;
74
75 /* flush caches inside the current cpu */
76 void (*cpu_down_flush)(void);
77
78 /* number of performance monitor counters */
79 unsigned int num_pmcs;
80 enum powerpc_pmc_type pmc_type;
81
82 /* this is called to initialize various CPU bits like L1 cache,
83 * BHT, SPD, etc... from head.S before branching to identify_machine
84 */
85 cpu_setup_t cpu_setup;
86 /* Used to restore cpu setup on secondary processors and at resume */
87 cpu_restore_t cpu_restore;
88
89 /* Used by oprofile userspace to select the right counters */
90 char *oprofile_cpu_type;
91
92 /* Processor specific oprofile operations */
93 enum powerpc_oprofile_type oprofile_type;
94
95 /* Bit locations inside the mmcra change */
96 unsigned long oprofile_mmcra_sihv;
97 unsigned long oprofile_mmcra_sipr;
98
99 /* Bits to clear during an oprofile exception */
100 unsigned long oprofile_mmcra_clear;
101
102 /* Name of processor class, for the ELF AT_PLATFORM entry */
103 char *platform;
104
105 /* Processor specific machine check handling. Return negative
106 * if the error is fatal, 1 if it was fully recovered and 0 to
107 * pass up (not CPU originated) */
108 int (*machine_check)(struct pt_regs *regs);
109
110 /*
111 * Processor specific early machine check handler which is
112 * called in real mode to handle SLB and TLB errors.
113 */
114 long (*machine_check_early)(struct pt_regs *regs);
115};
116
117extern struct cpu_spec *cur_cpu_spec;
118
119extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
120
121extern void set_cur_cpu_spec(struct cpu_spec *s);
122extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
123extern void identify_cpu_name(unsigned int pvr);
124extern void do_feature_fixups(unsigned long value, void *fixup_start,
125 void *fixup_end);
126
127extern const char *powerpc_base_platform;
128
129#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
130extern void cpu_feature_keys_init(void);
131#else
132static inline void cpu_feature_keys_init(void) { }
133#endif
134
135#endif /* __ASSEMBLY__ */
136
137/* CPU kernel features */
138
139/* Definitions for features that we have on both 32-bit and 64-bit chips */
140#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
141#define CPU_FTR_ALTIVEC ASM_CONST(0x00000002)
142#define CPU_FTR_DBELL ASM_CONST(0x00000004)
143#define CPU_FTR_CAN_NAP ASM_CONST(0x00000008)
144#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010)
145#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00000020)
146#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040)
147#define CPU_FTR_LWSYNC ASM_CONST(0x00000080)
148#define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100)
149#define CPU_FTR_EMB_HV ASM_CONST(0x00000200)
150
151/* Definitions for features that only exist on 32-bit chips */
152#ifdef CONFIG_PPC32
153#define CPU_FTR_L2CR ASM_CONST(0x00002000)
154#define CPU_FTR_SPEC7450 ASM_CONST(0x00004000)
155#define CPU_FTR_TAU ASM_CONST(0x00008000)
156#define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000)
157#define CPU_FTR_L3CR ASM_CONST(0x00040000)
158#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000)
159#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000)
160#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000)
161#define CPU_FTR_NO_DPM ASM_CONST(0x00400000)
162#define CPU_FTR_476_DD2 ASM_CONST(0x00800000)
163#define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000)
164#define CPU_FTR_NO_BTIC ASM_CONST(0x02000000)
165#define CPU_FTR_PPC_LE ASM_CONST(0x04000000)
166#define CPU_FTR_SPE ASM_CONST(0x10000000)
167#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000)
168#define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000)
169
170#else /* CONFIG_PPC32 */
171/* Define these to 0 for the sake of tests in common code */
172#define CPU_FTR_PPC_LE (0)
173#endif
174
175/*
176 * Definitions for the 64-bit processor unique features;
177 * on 32-bit, make the names available but defined to be 0.
178 */
179#ifdef __powerpc64__
180#define LONG_ASM_CONST(x) ASM_CONST(x)
181#else
182#define LONG_ASM_CONST(x) 0
183#endif
184
185#define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000)
186#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000)
187#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000)
188#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000)
189#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000)
190#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000)
191#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000)
192#define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000)
193#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000)
194#define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000)
195#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000)
196#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)
197#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)
198#define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)
199#define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000)
200#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)
201#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)
202#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)
203#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000)
204#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000)
205#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000)
206/* LONG_ASM_CONST(0x0000000400000000) Free */
207#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000)
208#define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000)
209#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000)
210#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000)
211#define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000)
212#define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000)
213#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000)
214#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000)
215#define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000)
216#define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000)
217#define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000)
218#define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000)
219#define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000)
220#define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000)
221#define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000)
222#define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000)
223
224#ifndef __ASSEMBLY__
225
226#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
227
228#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
229
230/* We only set the altivec features if the kernel was compiled with altivec
231 * support
232 */
233#ifdef CONFIG_ALTIVEC
234#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
235#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
236#else
237#define CPU_FTR_ALTIVEC_COMP 0
238#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
239#endif
240
241/* We only set the VSX features if the kernel was compiled with VSX
242 * support
243 */
244#ifdef CONFIG_VSX
245#define CPU_FTR_VSX_COMP CPU_FTR_VSX
246#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
247#else
248#define CPU_FTR_VSX_COMP 0
249#define PPC_FEATURE_HAS_VSX_COMP 0
250#endif
251
252/* We only set the spe features if the kernel was compiled with spe
253 * support
254 */
255#ifdef CONFIG_SPE
256#define CPU_FTR_SPE_COMP CPU_FTR_SPE
257#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
258#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
259#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
260#else
261#define CPU_FTR_SPE_COMP 0
262#define PPC_FEATURE_HAS_SPE_COMP 0
263#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
264#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
265#endif
266
267/* We only set the TM feature if the kernel was compiled with TM supprt */
268#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
269#define CPU_FTR_TM_COMP CPU_FTR_TM
270#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
271#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
272#else
273#define CPU_FTR_TM_COMP 0
274#define PPC_FEATURE2_HTM_COMP 0
275#define PPC_FEATURE2_HTM_NOSC_COMP 0
276#endif
277
278/* We need to mark all pages as being coherent if we're SMP or we have a
279 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
280 * require it for PCI "streaming/prefetch" to work properly.
281 * This is also required by 52xx family.
282 */
283#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
284 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
285 || defined(CONFIG_PPC_MPC52xx)
286#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
287#else
288#define CPU_FTR_COMMON 0
289#endif
290
291/* The powersave features NAP & DOZE seems to confuse BDI when
292 debugging. So if a BDI is used, disable theses
293 */
294#ifndef CONFIG_BDI_SWITCH
295#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
296#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
297#else
298#define CPU_FTR_MAYBE_CAN_DOZE 0
299#define CPU_FTR_MAYBE_CAN_NAP 0
300#endif
301
302#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | \
303 CPU_FTR_COHERENT_ICACHE)
304#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
305 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE)
306#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE)
307#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
308 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
309 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
310#define CPU_FTRS_740 (CPU_FTR_COMMON | \
311 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
312 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
313 CPU_FTR_PPC_LE)
314#define CPU_FTRS_750 (CPU_FTR_COMMON | \
315 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
316 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
317 CPU_FTR_PPC_LE)
318#define CPU_FTRS_750CL (CPU_FTRS_750)
319#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
320#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
321#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
322#define CPU_FTRS_750GX (CPU_FTRS_750FX)
323#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
324 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
325 CPU_FTR_ALTIVEC_COMP | \
326 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
327#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
328 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
329 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
330 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
331#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
332 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
333 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
334 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
335#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
336 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
337 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
338 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
339 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
340#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
341 CPU_FTR_NEED_PAIRED_STWCX | \
342 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
343 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
344 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
345#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
346 CPU_FTR_NEED_PAIRED_STWCX | \
347 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
348 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
349#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
350 CPU_FTR_NEED_PAIRED_STWCX | \
351 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
352 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
353 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
354 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
355#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
356 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
357 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
358 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
359#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
360 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
361 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
362 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
363 CPU_FTR_NEED_PAIRED_STWCX)
364#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
365 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
366 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
367 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
368#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
369 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
370 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
371 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
372#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
373 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
374 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
375 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
376#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
377#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
378 CPU_FTR_MAYBE_CAN_NAP)
379#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
380 CPU_FTR_MAYBE_CAN_NAP | \
381 CPU_FTR_COMMON | CPU_FTR_NOEXECUTE)
382#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
383 CPU_FTR_MAYBE_CAN_NAP | \
384 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE)
385#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON)
386#define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE)
387#define CPU_FTRS_40X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
388#define CPU_FTRS_44X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
389#define CPU_FTRS_440x6 (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
390 CPU_FTR_INDEXED_DCR)
391#define CPU_FTRS_47X (CPU_FTRS_440x6)
392#define CPU_FTRS_E200 (CPU_FTR_SPE_COMP | \
393 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
394 CPU_FTR_NOEXECUTE | \
395 CPU_FTR_DEBUG_LVL_EXC)
396#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \
397 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
398 CPU_FTR_NOEXECUTE)
399#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \
400 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
401 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
402#define CPU_FTRS_E500MC (CPU_FTR_NODSISRALIGN | \
403 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
404 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
405/*
406 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
407 * same workaround as CPU_FTR_CELL_TB_BUG.
408 */
409#define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \
410 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
411 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
412 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
413#define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \
414 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
415 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
416 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
417 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
418#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
419
420/* 64-bit CPUs */
421#define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
422 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
423 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
424 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
425 CPU_FTR_HVMODE | CPU_FTR_DABRX)
426#define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \
427 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
428 CPU_FTR_MMCRA | CPU_FTR_SMT | \
429 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
430 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
431#define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \
432 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
433 CPU_FTR_MMCRA | CPU_FTR_SMT | \
434 CPU_FTR_COHERENT_ICACHE | \
435 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
436 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
437 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
438 CPU_FTR_DABRX)
439#define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \
440 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
441 CPU_FTR_MMCRA | CPU_FTR_SMT | \
442 CPU_FTR_COHERENT_ICACHE | \
443 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
444 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
445 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
446 CPU_FTR_CFAR | CPU_FTR_HVMODE | \
447 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX )
448#define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
449 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
450 CPU_FTR_MMCRA | CPU_FTR_SMT | \
451 CPU_FTR_COHERENT_ICACHE | \
452 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
453 CPU_FTR_DSCR | CPU_FTR_SAO | \
454 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
455 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
456 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
457 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP )
458#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
459#define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
460 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
461 CPU_FTR_MMCRA | CPU_FTR_SMT | \
462 CPU_FTR_COHERENT_ICACHE | \
463 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
464 CPU_FTR_DSCR | CPU_FTR_SAO | \
465 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
466 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
467 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
468 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \
469 CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR)
470#define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG)
471#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \
472 CPU_FTR_P9_RADIX_PREFETCH_BUG | \
473 CPU_FTR_POWER9_DD2_1)
474#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
475 CPU_FTR_P9_TM_HV_ASSIST | \
476 CPU_FTR_P9_TM_XER_SO_BUG)
477#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
478 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
479 CPU_FTR_MMCRA | CPU_FTR_SMT | \
480 CPU_FTR_COHERENT_ICACHE | \
481 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
482 CPU_FTR_DSCR | CPU_FTR_SAO | \
483 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
484 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
485 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
486 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
487 CPU_FTR_DAWR | CPU_FTR_DAWR1)
488#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
489 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
490 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
491 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
492 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
493#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
494 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
495 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
496#define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2)
497
498#ifdef __powerpc64__
499#ifdef CONFIG_PPC_BOOK3E
500#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
501#else
502#ifdef CONFIG_CPU_LITTLE_ENDIAN
503#define CPU_FTRS_POSSIBLE \
504 (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
505 CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
506 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
507#else
508#define CPU_FTRS_POSSIBLE \
509 (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
510 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
511 CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
512 CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
513 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
514#endif /* CONFIG_CPU_LITTLE_ENDIAN */
515#endif
516#else
517enum {
518 CPU_FTRS_POSSIBLE =
519#ifdef CONFIG_PPC_BOOK3S_601
520 CPU_FTRS_PPC601 |
521#elif defined(CONFIG_PPC_BOOK3S_32)
522 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
523 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
524 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
525 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
526 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
527 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
528 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
529 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
530 CPU_FTRS_CLASSIC32 |
531#else
532 CPU_FTRS_GENERIC_32 |
533#endif
534#ifdef CONFIG_PPC_8xx
535 CPU_FTRS_8XX |
536#endif
537#ifdef CONFIG_40x
538 CPU_FTRS_40X |
539#endif
540#ifdef CONFIG_44x
541 CPU_FTRS_44X | CPU_FTRS_440x6 |
542#endif
543#ifdef CONFIG_PPC_47x
544 CPU_FTRS_47X | CPU_FTR_476_DD2 |
545#endif
546#ifdef CONFIG_E200
547 CPU_FTRS_E200 |
548#endif
549#ifdef CONFIG_E500
550 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
551#endif
552#ifdef CONFIG_PPC_E500MC
553 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
554#endif
555 0,
556};
557#endif /* __powerpc64__ */
558
559#ifdef __powerpc64__
560#ifdef CONFIG_PPC_BOOK3E
561#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
562#else
563
564#ifdef CONFIG_PPC_DT_CPU_FTRS
565#define CPU_FTRS_DT_CPU_BASE \
566 (CPU_FTR_LWSYNC | \
567 CPU_FTR_FPU_UNAVAILABLE | \
568 CPU_FTR_NODSISRALIGN | \
569 CPU_FTR_NOEXECUTE | \
570 CPU_FTR_COHERENT_ICACHE | \
571 CPU_FTR_STCX_CHECKS_ADDRESS | \
572 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
573 CPU_FTR_DAWR | \
574 CPU_FTR_ARCH_206 | \
575 CPU_FTR_ARCH_207S)
576#else
577#define CPU_FTRS_DT_CPU_BASE (~0ul)
578#endif
579
580#ifdef CONFIG_CPU_LITTLE_ENDIAN
581#define CPU_FTRS_ALWAYS \
582 (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \
583 CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \
584 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
585#else
586#define CPU_FTRS_ALWAYS \
587 (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
588 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
589 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
590 ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \
591 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
592#endif /* CONFIG_CPU_LITTLE_ENDIAN */
593#endif
594#else
595enum {
596 CPU_FTRS_ALWAYS =
597#ifdef CONFIG_PPC_BOOK3S_601
598 CPU_FTRS_PPC601 &
599#elif defined(CONFIG_PPC_BOOK3S_32)
600 CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
601 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
602 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
603 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
604 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
605 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
606 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
607 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
608 CPU_FTRS_CLASSIC32 &
609#else
610 CPU_FTRS_GENERIC_32 &
611#endif
612#ifdef CONFIG_PPC_8xx
613 CPU_FTRS_8XX &
614#endif
615#ifdef CONFIG_40x
616 CPU_FTRS_40X &
617#endif
618#ifdef CONFIG_44x
619 CPU_FTRS_44X & CPU_FTRS_440x6 &
620#endif
621#ifdef CONFIG_E200
622 CPU_FTRS_E200 &
623#endif
624#ifdef CONFIG_E500
625 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
626#endif
627#ifdef CONFIG_PPC_E500MC
628 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
629#endif
630 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
631 CPU_FTRS_POSSIBLE,
632};
633#endif /* __powerpc64__ */
634
635/*
636 * Maximum number of hw breakpoint supported on powerpc. Number of
637 * breakpoints supported by actual hw might be less than this, which
638 * is decided at run time in nr_wp_slots().
639 */
640#define HBP_NUM_MAX 2
641
642#endif /* !__ASSEMBLY__ */
643
644#endif /* __ASM_POWERPC_CPUTABLE_H */