Loading...
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#define gf100_dmaobj(p) container_of((p), struct gf100_dmaobj, base)
25#include "user.h"
26
27#include <core/client.h>
28#include <core/gpuobj.h>
29#include <subdev/fb.h>
30
31#include <nvif/cl0002.h>
32#include <nvif/unpack.h>
33
34struct gf100_dmaobj {
35 struct nvkm_dmaobj base;
36 u32 flags0;
37 u32 flags5;
38};
39
40static int
41gf100_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent,
42 int align, struct nvkm_gpuobj **pgpuobj)
43{
44 struct gf100_dmaobj *dmaobj = gf100_dmaobj(base);
45 struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
46 int ret;
47
48 ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj);
49 if (ret == 0) {
50 nvkm_kmap(*pgpuobj);
51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
55 upper_32_bits(dmaobj->base.start));
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
58 nvkm_done(*pgpuobj);
59 }
60
61 return ret;
62}
63
64static const struct nvkm_dmaobj_func
65gf100_dmaobj_func = {
66 .bind = gf100_dmaobj_bind,
67};
68
69int
70gf100_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
71 void *data, u32 size, struct nvkm_dmaobj **pdmaobj)
72{
73 union {
74 struct gf100_dma_v0 v0;
75 } *args;
76 struct nvkm_object *parent = oclass->parent;
77 struct gf100_dmaobj *dmaobj;
78 u32 kind, user, unkn;
79 int ret;
80
81 if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
82 return -ENOMEM;
83 *pdmaobj = &dmaobj->base;
84
85 ret = nvkm_dmaobj_ctor(&gf100_dmaobj_func, dma, oclass,
86 &data, &size, &dmaobj->base);
87 if (ret)
88 return ret;
89
90 ret = -ENOSYS;
91 args = data;
92
93 nvif_ioctl(parent, "create gf100 dma size %d\n", size);
94 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
95 nvif_ioctl(parent,
96 "create gf100 dma vers %d priv %d kind %02x\n",
97 args->v0.version, args->v0.priv, args->v0.kind);
98 kind = args->v0.kind;
99 user = args->v0.priv;
100 unkn = 0;
101 } else
102 if (size == 0) {
103 if (dmaobj->base.target != NV_MEM_TARGET_VM) {
104 kind = GF100_DMA_V0_KIND_PITCH;
105 user = GF100_DMA_V0_PRIV_US;
106 unkn = 2;
107 } else {
108 kind = GF100_DMA_V0_KIND_VM;
109 user = GF100_DMA_V0_PRIV_VM;
110 unkn = 0;
111 }
112 } else
113 return ret;
114
115 if (user > 2)
116 return -EINVAL;
117 dmaobj->flags0 |= (kind << 22) | (user << 20) | oclass->base.oclass;
118 dmaobj->flags5 |= (unkn << 16);
119
120 switch (dmaobj->base.target) {
121 case NV_MEM_TARGET_VM:
122 dmaobj->flags0 |= 0x00000000;
123 break;
124 case NV_MEM_TARGET_VRAM:
125 dmaobj->flags0 |= 0x00010000;
126 break;
127 case NV_MEM_TARGET_PCI:
128 dmaobj->flags0 |= 0x00020000;
129 break;
130 case NV_MEM_TARGET_PCI_NOSNOOP:
131 dmaobj->flags0 |= 0x00030000;
132 break;
133 default:
134 return -EINVAL;
135 }
136
137 switch (dmaobj->base.access) {
138 case NV_MEM_ACCESS_VM:
139 break;
140 case NV_MEM_ACCESS_RO:
141 dmaobj->flags0 |= 0x00040000;
142 break;
143 case NV_MEM_ACCESS_WO:
144 case NV_MEM_ACCESS_RW:
145 dmaobj->flags0 |= 0x00080000;
146 break;
147 }
148
149 return 0;
150}
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#define gf100_dmaobj(p) container_of((p), struct gf100_dmaobj, base)
25#include "user.h"
26
27#include <core/client.h>
28#include <core/gpuobj.h>
29#include <subdev/fb.h>
30
31#include <nvif/cl0002.h>
32#include <nvif/unpack.h>
33
34struct gf100_dmaobj {
35 struct nvkm_dmaobj base;
36 u32 flags0;
37 u32 flags5;
38};
39
40static int
41gf100_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent,
42 int align, struct nvkm_gpuobj **pgpuobj)
43{
44 struct gf100_dmaobj *dmaobj = gf100_dmaobj(base);
45 struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;
46 int ret;
47
48 ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj);
49 if (ret == 0) {
50 nvkm_kmap(*pgpuobj);
51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
55 upper_32_bits(dmaobj->base.start));
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
58 nvkm_done(*pgpuobj);
59 }
60
61 return ret;
62}
63
64static const struct nvkm_dmaobj_func
65gf100_dmaobj_func = {
66 .bind = gf100_dmaobj_bind,
67};
68
69int
70gf100_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass,
71 void *data, u32 size, struct nvkm_dmaobj **pdmaobj)
72{
73 union {
74 struct gf100_dma_v0 v0;
75 } *args;
76 struct nvkm_object *parent = oclass->parent;
77 struct gf100_dmaobj *dmaobj;
78 u32 kind, user, unkn;
79 int ret;
80
81 if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))
82 return -ENOMEM;
83 *pdmaobj = &dmaobj->base;
84
85 ret = nvkm_dmaobj_ctor(&gf100_dmaobj_func, dma, oclass,
86 &data, &size, &dmaobj->base);
87 if (ret)
88 return ret;
89
90 ret = -ENOSYS;
91 args = data;
92
93 nvif_ioctl(parent, "create gf100 dma size %d\n", size);
94 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
95 nvif_ioctl(parent,
96 "create gf100 dma vers %d priv %d kind %02x\n",
97 args->v0.version, args->v0.priv, args->v0.kind);
98 kind = args->v0.kind;
99 user = args->v0.priv;
100 unkn = 0;
101 } else
102 if (size == 0) {
103 if (dmaobj->base.target != NV_MEM_TARGET_VM) {
104 kind = GF100_DMA_V0_KIND_PITCH;
105 user = GF100_DMA_V0_PRIV_US;
106 unkn = 2;
107 } else {
108 kind = GF100_DMA_V0_KIND_VM;
109 user = GF100_DMA_V0_PRIV_VM;
110 unkn = 0;
111 }
112 } else
113 return ret;
114
115 if (user > 2)
116 return -EINVAL;
117 dmaobj->flags0 |= (kind << 22) | (user << 20) | oclass->base.oclass;
118 dmaobj->flags5 |= (unkn << 16);
119
120 switch (dmaobj->base.target) {
121 case NV_MEM_TARGET_VM:
122 dmaobj->flags0 |= 0x00000000;
123 break;
124 case NV_MEM_TARGET_VRAM:
125 dmaobj->flags0 |= 0x00010000;
126 break;
127 case NV_MEM_TARGET_PCI:
128 dmaobj->flags0 |= 0x00020000;
129 break;
130 case NV_MEM_TARGET_PCI_NOSNOOP:
131 dmaobj->flags0 |= 0x00030000;
132 break;
133 default:
134 return -EINVAL;
135 }
136
137 switch (dmaobj->base.access) {
138 case NV_MEM_ACCESS_VM:
139 break;
140 case NV_MEM_ACCESS_RO:
141 dmaobj->flags0 |= 0x00040000;
142 break;
143 case NV_MEM_ACCESS_WO:
144 case NV_MEM_ACCESS_RW:
145 dmaobj->flags0 |= 0x00080000;
146 break;
147 }
148
149 return 0;
150}