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1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#ifndef __DAL_DPP_H__
28#define __DAL_DPP_H__
29
30/**
31 * DOC: overview
32 *
33 * The DPP (Display Pipe and Plane) block is the unified display data
34 * processing engine in DCN for processing graphic or video data on per DPP
35 * rectangle base. This rectangle can be a part of SLS (Single Large Surface),
36 * or a layer to be blended with other DPP, or a rectangle associated with a
37 * display tile.
38 *
39 * It provides various functions including:
40 * - graphic color keyer
41 * - graphic cursor compositing
42 * - graphic or video image source to destination scaling
43 * - image sharping
44 * - video format conversion from 4:2:0 or 4:2:2 to 4:4:4
45 * - Color Space Conversion
46 * - Host LUT gamma adjustment
47 * - Color Gamut Remap
48 * - brightness and contrast adjustment.
49 *
50 * DPP pipe consists of Converter and Cursor (CNVC), Scaler (DSCL), Color
51 * Management (CM), Output Buffer (OBUF) and Digital Bypass (DPB) module
52 * connected in a video/graphics pipeline.
53 */
54
55#include "transform.h"
56#include "cursor_reg_cache.h"
57
58union defer_reg_writes {
59 struct {
60 bool disable_blnd_lut:1;
61 bool disable_3dlut:1;
62 bool disable_shaper:1;
63 bool disable_gamcor:1;
64 bool disable_dscl:1;
65 } bits;
66 uint32_t raw;
67};
68
69struct dpp {
70 const struct dpp_funcs *funcs;
71 struct dc_context *ctx;
72 /**
73 * @inst:
74 *
75 * inst stands for "instance," and it is an id number that references a
76 * specific DPP.
77 */
78 int inst;
79 struct dpp_caps *caps;
80 struct pwl_params regamma_params;
81 struct pwl_params degamma_params;
82 struct dpp_cursor_attributes cur_attr;
83 union defer_reg_writes deferred_reg_writes;
84
85 struct pwl_params shaper_params;
86 bool cm_bypass_mode;
87
88 struct cursor_position_cache_dpp pos;
89 struct cursor_attribute_cache_dpp att;
90};
91
92struct dpp_input_csc_matrix {
93 enum dc_color_space color_space;
94 uint16_t regval[12];
95};
96
97static const struct dpp_input_csc_matrix __maybe_unused dpp_input_csc_matrix[] = {
98 { COLOR_SPACE_SRGB,
99 { 0x2000, 0, 0, 0,
100 0, 0x2000, 0, 0,
101 0, 0, 0x2000, 0 } },
102 { COLOR_SPACE_SRGB_LIMITED,
103 { 0x2000, 0, 0, 0,
104 0, 0x2000, 0, 0,
105 0, 0, 0x2000, 0 } },
106 { COLOR_SPACE_YCBCR601,
107 { 0x2cdd, 0x2000, 0, 0xe991,
108 0xe926, 0x2000, 0xf4fd, 0x10ef,
109 0, 0x2000, 0x38b4, 0xe3a6 } },
110 { COLOR_SPACE_YCBCR601_LIMITED,
111 { 0x3353, 0x2568, 0, 0xe400,
112 0xe5dc, 0x2568, 0xf367, 0x1108,
113 0, 0x2568, 0x40de, 0xdd3a } },
114 { COLOR_SPACE_YCBCR709,
115 { 0x3265, 0x2000, 0, 0xe6ce,
116 0xf105, 0x2000, 0xfa01, 0xa7d,
117 0, 0x2000, 0x3b61, 0xe24f } },
118 { COLOR_SPACE_YCBCR709_LIMITED,
119 { 0x39a6, 0x2568, 0, 0xe0d6,
120 0xeedd, 0x2568, 0xf925, 0x9a8,
121 0, 0x2568, 0x43ee, 0xdbb2 } },
122 { COLOR_SPACE_2020_YCBCR,
123 { 0x2F30, 0x2000, 0, 0xE869,
124 0xEDB7, 0x2000, 0xFABC, 0xBC6,
125 0, 0x2000, 0x3C34, 0xE1E6 } },
126 { COLOR_SPACE_2020_RGB_LIMITEDRANGE,
127 { 0x35E0, 0x255F, 0, 0xE2B3,
128 0xEB20, 0x255F, 0xF9FD, 0xB1E,
129 0, 0x255F, 0x44BD, 0xDB43 } }
130};
131
132struct dpp_grph_csc_adjustment {
133 struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
134 enum graphics_gamut_adjust_type gamut_adjust_type;
135};
136
137struct cnv_color_keyer_params {
138 int color_keyer_en;
139 int color_keyer_mode;
140 int color_keyer_alpha_low;
141 int color_keyer_alpha_high;
142 int color_keyer_red_low;
143 int color_keyer_red_high;
144 int color_keyer_green_low;
145 int color_keyer_green_high;
146 int color_keyer_blue_low;
147 int color_keyer_blue_high;
148};
149
150/* new for dcn2: set the 8bit alpha values based on the 2 bit alpha
151 *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0 default: 0b00000000
152 *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1 default: 0b01010101
153 *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2 default: 0b10101010
154 *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3 default: 0b11111111
155 */
156struct cnv_alpha_2bit_lut {
157 int lut0;
158 int lut1;
159 int lut2;
160 int lut3;
161};
162
163struct dcn_dpp_state {
164 uint32_t is_enabled;
165 uint32_t igam_lut_mode;
166 uint32_t igam_input_format;
167 uint32_t dgam_lut_mode;
168 uint32_t rgam_lut_mode;
169 // gamut_remap data for dcn10_get_cm_states()
170 uint32_t gamut_remap_mode;
171 uint32_t gamut_remap_c11_c12;
172 uint32_t gamut_remap_c13_c14;
173 uint32_t gamut_remap_c21_c22;
174 uint32_t gamut_remap_c23_c24;
175 uint32_t gamut_remap_c31_c32;
176 uint32_t gamut_remap_c33_c34;
177 // gamut_remap data for dcn*_log_color_state()
178 struct dpp_grph_csc_adjustment gamut_remap;
179 uint32_t shaper_lut_mode;
180 uint32_t lut3d_mode;
181 uint32_t lut3d_bit_depth;
182 uint32_t lut3d_size;
183 uint32_t blnd_lut_mode;
184 uint32_t pre_dgam_mode;
185 uint32_t pre_dgam_select;
186 uint32_t gamcor_mode;
187};
188
189struct CM_bias_params {
190 uint32_t cm_bias_cr_r;
191 uint32_t cm_bias_y_g;
192 uint32_t cm_bias_cb_b;
193 uint32_t cm_bias_format;
194};
195
196struct dpp_funcs {
197 bool (*dpp_program_gamcor_lut)(
198 struct dpp *dpp_base, const struct pwl_params *params);
199
200 void (*dpp_set_pre_degam)(struct dpp *dpp_base,
201 enum dc_transfer_func_predefined tr);
202
203 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
204 uint32_t enable, uint32_t additive_blending);
205
206 void (*dpp_program_cm_bias)(
207 struct dpp *dpp_base,
208 struct CM_bias_params *bias_params);
209
210 void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);
211
212 void (*dpp_reset)(struct dpp *dpp);
213
214 void (*dpp_set_scaler)(struct dpp *dpp,
215 const struct scaler_data *scl_data);
216
217 void (*dpp_set_pixel_storage_depth)(
218 struct dpp *dpp,
219 enum lb_pixel_depth depth,
220 const struct bit_depth_reduction_params *bit_depth_params);
221
222 bool (*dpp_get_optimal_number_of_taps)(
223 struct dpp *dpp,
224 struct scaler_data *scl_data,
225 const struct scaling_taps *in_taps);
226
227 void (*dpp_set_gamut_remap)(
228 struct dpp *dpp,
229 const struct dpp_grph_csc_adjustment *adjust);
230
231 void (*dpp_set_csc_default)(
232 struct dpp *dpp,
233 enum dc_color_space colorspace);
234
235 void (*dpp_set_csc_adjustment)(
236 struct dpp *dpp,
237 const uint16_t *regval);
238
239 void (*dpp_power_on_regamma_lut)(
240 struct dpp *dpp,
241 bool power_on);
242
243 void (*dpp_program_regamma_lut)(
244 struct dpp *dpp,
245 const struct pwl_result_data *rgb,
246 uint32_t num);
247
248 void (*dpp_configure_regamma_lut)(
249 struct dpp *dpp,
250 bool is_ram_a);
251
252 void (*dpp_program_regamma_lutb_settings)(
253 struct dpp *dpp,
254 const struct pwl_params *params);
255
256 void (*dpp_program_regamma_luta_settings)(
257 struct dpp *dpp,
258 const struct pwl_params *params);
259
260 void (*dpp_program_regamma_pwl)(
261 struct dpp *dpp,
262 const struct pwl_params *params,
263 enum opp_regamma mode);
264
265 void (*dpp_program_bias_and_scale)(
266 struct dpp *dpp,
267 struct dc_bias_and_scale *params);
268
269 void (*dpp_set_degamma)(
270 struct dpp *dpp_base,
271 enum ipp_degamma_mode mode);
272
273 void (*dpp_program_input_lut)(
274 struct dpp *dpp_base,
275 const struct dc_gamma *gamma);
276
277 void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,
278 const struct pwl_params *params);
279
280 void (*dpp_setup)(
281 struct dpp *dpp_base,
282 enum surface_pixel_format format,
283 enum expansion_mode mode,
284 struct dc_csc_transform input_csc_color_matrix,
285 enum dc_color_space input_color_space,
286 struct cnv_alpha_2bit_lut *alpha_2bit_lut);
287
288 void (*dpp_full_bypass)(struct dpp *dpp_base);
289
290 void (*set_cursor_attributes)(
291 struct dpp *dpp_base,
292 struct dc_cursor_attributes *cursor_attributes);
293
294 void (*set_cursor_position)(
295 struct dpp *dpp_base,
296 const struct dc_cursor_position *pos,
297 const struct dc_cursor_mi_param *param,
298 uint32_t width,
299 uint32_t height
300 );
301
302 void (*dpp_set_hdr_multiplier)(
303 struct dpp *dpp_base,
304 uint32_t multiplier);
305
306 void (*set_optional_cursor_attributes)(
307 struct dpp *dpp_base,
308 struct dpp_cursor_attributes *attr);
309
310 void (*dpp_dppclk_control)(
311 struct dpp *dpp_base,
312 bool dppclk_div,
313 bool enable);
314
315 void (*dpp_deferred_update)(
316 struct dpp *dpp);
317 bool (*dpp_program_blnd_lut)(
318 struct dpp *dpp,
319 const struct pwl_params *params);
320 bool (*dpp_program_shaper_lut)(
321 struct dpp *dpp,
322 const struct pwl_params *params);
323 bool (*dpp_program_3dlut)(
324 struct dpp *dpp,
325 struct tetrahedral_params *params);
326 void (*dpp_cnv_set_alpha_keyer)(
327 struct dpp *dpp_base,
328 struct cnv_color_keyer_params *color_keyer);
329
330 void (*dpp_get_gamut_remap)(struct dpp *dpp_base,
331 struct dpp_grph_csc_adjustment *adjust);
332};
333
334
335
336#endif
1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#ifndef __DAL_DPP_H__
28#define __DAL_DPP_H__
29
30#include "transform.h"
31
32struct dpp {
33 const struct dpp_funcs *funcs;
34 struct dc_context *ctx;
35 int inst;
36 struct dpp_caps *caps;
37 struct pwl_params regamma_params;
38 struct pwl_params degamma_params;
39 struct dpp_cursor_attributes cur_attr;
40
41 struct pwl_params shaper_params;
42 bool cm_bypass_mode;
43};
44
45struct dpp_input_csc_matrix {
46 enum dc_color_space color_space;
47 uint16_t regval[12];
48};
49
50static const struct dpp_input_csc_matrix dpp_input_csc_matrix[] = {
51 {COLOR_SPACE_SRGB,
52 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
53 {COLOR_SPACE_SRGB_LIMITED,
54 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
55 {COLOR_SPACE_YCBCR601,
56 {0x2cdd, 0x2000, 0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
57 0, 0x2000, 0x38b4, 0xe3a6} },
58 {COLOR_SPACE_YCBCR601_LIMITED,
59 {0x3353, 0x2568, 0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108,
60 0, 0x2568, 0x40de, 0xdd3a} },
61 {COLOR_SPACE_YCBCR709,
62 {0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
63 0x2000, 0x3b61, 0xe24f} },
64
65 {COLOR_SPACE_YCBCR709_LIMITED,
66 {0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
67 0x2568, 0x43ee, 0xdbb2} }
68};
69
70struct dpp_grph_csc_adjustment {
71 struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE];
72 enum graphics_gamut_adjust_type gamut_adjust_type;
73};
74
75struct cnv_color_keyer_params {
76 int color_keyer_en;
77 int color_keyer_mode;
78 int color_keyer_alpha_low;
79 int color_keyer_alpha_high;
80 int color_keyer_red_low;
81 int color_keyer_red_high;
82 int color_keyer_green_low;
83 int color_keyer_green_high;
84 int color_keyer_blue_low;
85 int color_keyer_blue_high;
86};
87
88/* new for dcn2: set the 8bit alpha values based on the 2 bit alpha
89 *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0 default: 0b00000000
90 *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1 default: 0b01010101
91 *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2 default: 0b10101010
92 *ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3 default: 0b11111111
93 */
94struct cnv_alpha_2bit_lut {
95 int lut0;
96 int lut1;
97 int lut2;
98 int lut3;
99};
100
101struct dcn_dpp_state {
102 uint32_t is_enabled;
103 uint32_t igam_lut_mode;
104 uint32_t igam_input_format;
105 uint32_t dgam_lut_mode;
106 uint32_t rgam_lut_mode;
107 uint32_t gamut_remap_mode;
108 uint32_t gamut_remap_c11_c12;
109 uint32_t gamut_remap_c13_c14;
110 uint32_t gamut_remap_c21_c22;
111 uint32_t gamut_remap_c23_c24;
112 uint32_t gamut_remap_c31_c32;
113 uint32_t gamut_remap_c33_c34;
114};
115
116struct CM_bias_params {
117 uint32_t cm_bias_cr_r;
118 uint32_t cm_bias_y_g;
119 uint32_t cm_bias_cb_b;
120 uint32_t cm_bias_format;
121};
122
123struct dpp_funcs {
124#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
125 bool (*dpp_program_gamcor_lut)(
126 struct dpp *dpp_base, const struct pwl_params *params);
127
128 void (*dpp_set_pre_degam)(struct dpp *dpp_base,
129 enum dc_transfer_func_predefined tr);
130#endif
131
132 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
133 uint32_t enable, uint32_t additive_blending);
134
135 void (*dpp_program_cm_bias)(
136 struct dpp *dpp_base,
137 struct CM_bias_params *bias_params);
138
139 void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);
140
141 void (*dpp_reset)(struct dpp *dpp);
142
143 void (*dpp_set_scaler)(struct dpp *dpp,
144 const struct scaler_data *scl_data);
145
146 void (*dpp_set_pixel_storage_depth)(
147 struct dpp *dpp,
148 enum lb_pixel_depth depth,
149 const struct bit_depth_reduction_params *bit_depth_params);
150
151 bool (*dpp_get_optimal_number_of_taps)(
152 struct dpp *dpp,
153 struct scaler_data *scl_data,
154 const struct scaling_taps *in_taps);
155
156 void (*dpp_set_gamut_remap)(
157 struct dpp *dpp,
158 const struct dpp_grph_csc_adjustment *adjust);
159
160 void (*dpp_set_csc_default)(
161 struct dpp *dpp,
162 enum dc_color_space colorspace);
163
164 void (*dpp_set_csc_adjustment)(
165 struct dpp *dpp,
166 const uint16_t *regval);
167
168 void (*dpp_power_on_regamma_lut)(
169 struct dpp *dpp,
170 bool power_on);
171
172 void (*dpp_program_regamma_lut)(
173 struct dpp *dpp,
174 const struct pwl_result_data *rgb,
175 uint32_t num);
176
177 void (*dpp_configure_regamma_lut)(
178 struct dpp *dpp,
179 bool is_ram_a);
180
181 void (*dpp_program_regamma_lutb_settings)(
182 struct dpp *dpp,
183 const struct pwl_params *params);
184
185 void (*dpp_program_regamma_luta_settings)(
186 struct dpp *dpp,
187 const struct pwl_params *params);
188
189 void (*dpp_program_regamma_pwl)(
190 struct dpp *dpp,
191 const struct pwl_params *params,
192 enum opp_regamma mode);
193
194 void (*dpp_program_bias_and_scale)(
195 struct dpp *dpp,
196 struct dc_bias_and_scale *params);
197
198 void (*dpp_set_degamma)(
199 struct dpp *dpp_base,
200 enum ipp_degamma_mode mode);
201
202 void (*dpp_program_input_lut)(
203 struct dpp *dpp_base,
204 const struct dc_gamma *gamma);
205
206 void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,
207 const struct pwl_params *params);
208
209 void (*dpp_setup)(
210 struct dpp *dpp_base,
211 enum surface_pixel_format format,
212 enum expansion_mode mode,
213 struct dc_csc_transform input_csc_color_matrix,
214 enum dc_color_space input_color_space,
215 struct cnv_alpha_2bit_lut *alpha_2bit_lut);
216
217 void (*dpp_full_bypass)(struct dpp *dpp_base);
218
219 void (*set_cursor_attributes)(
220 struct dpp *dpp_base,
221 struct dc_cursor_attributes *cursor_attributes);
222
223 void (*set_cursor_position)(
224 struct dpp *dpp_base,
225 const struct dc_cursor_position *pos,
226 const struct dc_cursor_mi_param *param,
227 uint32_t width,
228 uint32_t height
229 );
230
231 void (*dpp_set_hdr_multiplier)(
232 struct dpp *dpp_base,
233 uint32_t multiplier);
234
235 void (*set_optional_cursor_attributes)(
236 struct dpp *dpp_base,
237 struct dpp_cursor_attributes *attr);
238
239 void (*dpp_dppclk_control)(
240 struct dpp *dpp_base,
241 bool dppclk_div,
242 bool enable);
243
244 bool (*dpp_program_blnd_lut)(
245 struct dpp *dpp,
246 const struct pwl_params *params);
247 bool (*dpp_program_shaper_lut)(
248 struct dpp *dpp,
249 const struct pwl_params *params);
250 bool (*dpp_program_3dlut)(
251 struct dpp *dpp,
252 struct tetrahedral_params *params);
253 void (*dpp_cnv_set_alpha_keyer)(
254 struct dpp *dpp_base,
255 struct cnv_color_keyer_params *color_keyer);
256};
257
258
259
260#endif