Loading...
1/* SPDX-License-Identifier: GPL-2.0-only */
2#ifndef _ASM_X86_APIC_H
3#define _ASM_X86_APIC_H
4
5#include <linux/cpumask.h>
6#include <linux/static_call.h>
7
8#include <asm/alternative.h>
9#include <asm/cpufeature.h>
10#include <asm/apicdef.h>
11#include <linux/atomic.h>
12#include <asm/fixmap.h>
13#include <asm/mpspec.h>
14#include <asm/msr.h>
15#include <asm/hardirq.h>
16#include <asm/io.h>
17
18#define ARCH_APICTIMER_STOPS_ON_C3 1
19
20/*
21 * Debugging macros
22 */
23#define APIC_QUIET 0
24#define APIC_VERBOSE 1
25#define APIC_DEBUG 2
26
27/* Macros for apic_extnmi which controls external NMI masking */
28#define APIC_EXTNMI_BSP 0 /* Default */
29#define APIC_EXTNMI_ALL 1
30#define APIC_EXTNMI_NONE 2
31
32/*
33 * Define the default level of output to be very little
34 * This can be turned up by using apic=verbose for more
35 * information and apic=debug for _lots_ of information.
36 * apic_verbosity is defined in apic.c
37 */
38#define apic_printk(v, s, a...) do { \
39 if ((v) <= apic_verbosity) \
40 printk(s, ##a); \
41 } while (0)
42
43
44#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
45extern void x86_32_probe_apic(void);
46#else
47static inline void x86_32_probe_apic(void) { }
48#endif
49
50extern u32 cpuid_to_apicid[];
51
52#define CPU_ACPIID_INVALID U32_MAX
53
54#ifdef CONFIG_X86_LOCAL_APIC
55
56extern int apic_verbosity;
57extern int local_apic_timer_c2_ok;
58
59extern bool apic_is_disabled;
60extern unsigned int lapic_timer_period;
61
62extern enum apic_intr_mode_id apic_intr_mode;
63enum apic_intr_mode_id {
64 APIC_PIC,
65 APIC_VIRTUAL_WIRE,
66 APIC_VIRTUAL_WIRE_NO_CONFIG,
67 APIC_SYMMETRIC_IO,
68 APIC_SYMMETRIC_IO_NO_ROUTING
69};
70
71/*
72 * With 82489DX we can't rely on apic feature bit
73 * retrieved via cpuid but still have to deal with
74 * such an apic chip so we assume that SMP configuration
75 * is found from MP table (64bit case uses ACPI mostly
76 * which set smp presence flag as well so we are safe
77 * to use this helper too).
78 */
79static inline bool apic_from_smp_config(void)
80{
81 return smp_found_config && !apic_is_disabled;
82}
83
84/*
85 * Basic functions accessing APICs.
86 */
87#ifdef CONFIG_PARAVIRT
88#include <asm/paravirt.h>
89#endif
90
91static inline void native_apic_mem_write(u32 reg, u32 v)
92{
93 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
94
95 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
96 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
97 ASM_OUTPUT2("0" (v), "m" (*addr)));
98}
99
100static inline u32 native_apic_mem_read(u32 reg)
101{
102 return readl((void __iomem *)(APIC_BASE + reg));
103}
104
105static inline void native_apic_mem_eoi(void)
106{
107 native_apic_mem_write(APIC_EOI, APIC_EOI_ACK);
108}
109
110extern void native_apic_icr_write(u32 low, u32 id);
111extern u64 native_apic_icr_read(void);
112
113static inline bool apic_is_x2apic_enabled(void)
114{
115 u64 msr;
116
117 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
118 return false;
119 return msr & X2APIC_ENABLE;
120}
121
122extern void enable_IR_x2apic(void);
123
124extern int get_physical_broadcast(void);
125
126extern int lapic_get_maxlvt(void);
127extern void clear_local_APIC(void);
128extern void disconnect_bsp_APIC(int virt_wire_setup);
129extern void disable_local_APIC(void);
130extern void apic_soft_disable(void);
131extern void lapic_shutdown(void);
132extern void sync_Arb_IDs(void);
133extern void init_bsp_APIC(void);
134extern void apic_intr_mode_select(void);
135extern void apic_intr_mode_init(void);
136extern void init_apic_mappings(void);
137void register_lapic_address(unsigned long address);
138extern void setup_boot_APIC_clock(void);
139extern void setup_secondary_APIC_clock(void);
140extern void lapic_update_tsc_freq(void);
141
142#ifdef CONFIG_X86_64
143static inline bool apic_force_enable(unsigned long addr)
144{
145 return false;
146}
147#else
148extern bool apic_force_enable(unsigned long addr);
149#endif
150
151extern void apic_ap_setup(void);
152
153/*
154 * On 32bit this is mach-xxx local
155 */
156#ifdef CONFIG_X86_64
157extern int apic_is_clustered_box(void);
158#else
159static inline int apic_is_clustered_box(void)
160{
161 return 0;
162}
163#endif
164
165extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
166extern void lapic_assign_system_vectors(void);
167extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
168extern void lapic_update_legacy_vectors(void);
169extern void lapic_online(void);
170extern void lapic_offline(void);
171extern bool apic_needs_pit(void);
172
173extern void apic_send_IPI_allbutself(unsigned int vector);
174
175extern void topology_register_apic(u32 apic_id, u32 acpi_id, bool present);
176extern void topology_register_boot_apic(u32 apic_id);
177extern int topology_hotplug_apic(u32 apic_id, u32 acpi_id);
178extern void topology_hotunplug_apic(unsigned int cpu);
179extern void topology_apply_cmdline_limits_early(void);
180extern void topology_init_possible_cpus(void);
181extern void topology_reset_possible_cpus_up(void);
182
183#else /* !CONFIG_X86_LOCAL_APIC */
184static inline void lapic_shutdown(void) { }
185#define local_apic_timer_c2_ok 1
186static inline void init_apic_mappings(void) { }
187static inline void disable_local_APIC(void) { }
188# define setup_boot_APIC_clock x86_init_noop
189# define setup_secondary_APIC_clock x86_init_noop
190static inline void lapic_update_tsc_freq(void) { }
191static inline void init_bsp_APIC(void) { }
192static inline void apic_intr_mode_select(void) { }
193static inline void apic_intr_mode_init(void) { }
194static inline void lapic_assign_system_vectors(void) { }
195static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
196static inline bool apic_needs_pit(void) { return true; }
197static inline void topology_apply_cmdline_limits_early(void) { }
198static inline void topology_init_possible_cpus(void) { }
199#endif /* !CONFIG_X86_LOCAL_APIC */
200
201#ifdef CONFIG_X86_X2APIC
202static inline void native_apic_msr_write(u32 reg, u32 v)
203{
204 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
205 reg == APIC_LVR)
206 return;
207
208 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
209}
210
211static inline void native_apic_msr_eoi(void)
212{
213 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
214}
215
216static inline u32 native_apic_msr_read(u32 reg)
217{
218 u64 msr;
219
220 if (reg == APIC_DFR)
221 return -1;
222
223 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
224 return (u32)msr;
225}
226
227static inline void native_x2apic_icr_write(u32 low, u32 id)
228{
229 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
230}
231
232static inline u64 native_x2apic_icr_read(void)
233{
234 unsigned long val;
235
236 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
237 return val;
238}
239
240extern int x2apic_mode;
241extern int x2apic_phys;
242extern void __init x2apic_set_max_apicid(u32 apicid);
243extern void x2apic_setup(void);
244static inline int x2apic_enabled(void)
245{
246 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
247}
248
249#define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
250#else /* !CONFIG_X86_X2APIC */
251static inline void x2apic_setup(void) { }
252static inline int x2apic_enabled(void) { return 0; }
253static inline u32 native_apic_msr_read(u32 reg) { BUG(); }
254#define x2apic_mode (0)
255#define x2apic_supported() (0)
256#endif /* !CONFIG_X86_X2APIC */
257extern void __init check_x2apic(void);
258
259struct irq_data;
260
261/*
262 * Copyright 2004 James Cleverdon, IBM.
263 *
264 * Generic APIC sub-arch data struct.
265 *
266 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
267 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
268 * James Cleverdon.
269 */
270struct apic {
271 /* Hotpath functions first */
272 void (*eoi)(void);
273 void (*native_eoi)(void);
274 void (*write)(u32 reg, u32 v);
275 u32 (*read)(u32 reg);
276
277 /* IPI related functions */
278 void (*wait_icr_idle)(void);
279 u32 (*safe_wait_icr_idle)(void);
280
281 void (*send_IPI)(int cpu, int vector);
282 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
283 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
284 void (*send_IPI_allbutself)(int vector);
285 void (*send_IPI_all)(int vector);
286 void (*send_IPI_self)(int vector);
287
288 u32 disable_esr : 1,
289 dest_mode_logical : 1,
290 x2apic_set_max_apicid : 1,
291 nmi_to_offline_cpu : 1;
292
293 u32 (*calc_dest_apicid)(unsigned int cpu);
294
295 /* ICR related functions */
296 u64 (*icr_read)(void);
297 void (*icr_write)(u32 low, u32 high);
298
299 /* The limit of the APIC ID space. */
300 u32 max_apic_id;
301
302 /* Probe, setup and smpboot functions */
303 int (*probe)(void);
304 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
305
306 void (*init_apic_ldr)(void);
307 u32 (*cpu_present_to_apicid)(int mps_cpu);
308
309 u32 (*get_apic_id)(u32 id);
310
311 /* wakeup_secondary_cpu */
312 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip);
313 /* wakeup secondary CPU using 64-bit wakeup point */
314 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip);
315
316 char *name;
317};
318
319struct apic_override {
320 void (*eoi)(void);
321 void (*native_eoi)(void);
322 void (*write)(u32 reg, u32 v);
323 u32 (*read)(u32 reg);
324 void (*send_IPI)(int cpu, int vector);
325 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
326 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
327 void (*send_IPI_allbutself)(int vector);
328 void (*send_IPI_all)(int vector);
329 void (*send_IPI_self)(int vector);
330 u64 (*icr_read)(void);
331 void (*icr_write)(u32 low, u32 high);
332 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip);
333 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip);
334};
335
336/*
337 * Pointer to the local APIC driver in use on this system (there's
338 * always just one such driver in use - the kernel decides via an
339 * early probing process which one it picks - and then sticks to it):
340 */
341extern struct apic *apic;
342
343/*
344 * APIC drivers are probed based on how they are listed in the .apicdrivers
345 * section. So the order is important and enforced by the ordering
346 * of different apic driver files in the Makefile.
347 *
348 * For the files having two apic drivers, we use apic_drivers()
349 * to enforce the order with in them.
350 */
351#define apic_driver(sym) \
352 static const struct apic *__apicdrivers_##sym __used \
353 __aligned(sizeof(struct apic *)) \
354 __section(".apicdrivers") = { &sym }
355
356#define apic_drivers(sym1, sym2) \
357 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
358 __aligned(sizeof(struct apic *)) \
359 __section(".apicdrivers") = { &sym1, &sym2 }
360
361extern struct apic *__apicdrivers[], *__apicdrivers_end[];
362
363/*
364 * APIC functionality to boot other CPUs - only used on SMP:
365 */
366#ifdef CONFIG_SMP
367extern int lapic_can_unplug_cpu(void);
368#endif
369
370#ifdef CONFIG_X86_LOCAL_APIC
371extern struct apic_override __x86_apic_override;
372
373void __init apic_setup_apic_calls(void);
374void __init apic_install_driver(struct apic *driver);
375
376#define apic_update_callback(_callback, _fn) { \
377 __x86_apic_override._callback = _fn; \
378 apic->_callback = _fn; \
379 static_call_update(apic_call_##_callback, _fn); \
380 pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \
381}
382
383#define DECLARE_APIC_CALL(__cb) \
384 DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb)
385
386DECLARE_APIC_CALL(eoi);
387DECLARE_APIC_CALL(native_eoi);
388DECLARE_APIC_CALL(icr_read);
389DECLARE_APIC_CALL(icr_write);
390DECLARE_APIC_CALL(read);
391DECLARE_APIC_CALL(send_IPI);
392DECLARE_APIC_CALL(send_IPI_mask);
393DECLARE_APIC_CALL(send_IPI_mask_allbutself);
394DECLARE_APIC_CALL(send_IPI_allbutself);
395DECLARE_APIC_CALL(send_IPI_all);
396DECLARE_APIC_CALL(send_IPI_self);
397DECLARE_APIC_CALL(wait_icr_idle);
398DECLARE_APIC_CALL(wakeup_secondary_cpu);
399DECLARE_APIC_CALL(wakeup_secondary_cpu_64);
400DECLARE_APIC_CALL(write);
401
402static __always_inline u32 apic_read(u32 reg)
403{
404 return static_call(apic_call_read)(reg);
405}
406
407static __always_inline void apic_write(u32 reg, u32 val)
408{
409 static_call(apic_call_write)(reg, val);
410}
411
412static __always_inline void apic_eoi(void)
413{
414 static_call(apic_call_eoi)();
415}
416
417static __always_inline void apic_native_eoi(void)
418{
419 static_call(apic_call_native_eoi)();
420}
421
422static __always_inline u64 apic_icr_read(void)
423{
424 return static_call(apic_call_icr_read)();
425}
426
427static __always_inline void apic_icr_write(u32 low, u32 high)
428{
429 static_call(apic_call_icr_write)(low, high);
430}
431
432static __always_inline void __apic_send_IPI(int cpu, int vector)
433{
434 static_call(apic_call_send_IPI)(cpu, vector);
435}
436
437static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector)
438{
439 static_call_mod(apic_call_send_IPI_mask)(mask, vector);
440}
441
442static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
443{
444 static_call(apic_call_send_IPI_mask_allbutself)(mask, vector);
445}
446
447static __always_inline void __apic_send_IPI_allbutself(int vector)
448{
449 static_call(apic_call_send_IPI_allbutself)(vector);
450}
451
452static __always_inline void __apic_send_IPI_all(int vector)
453{
454 static_call(apic_call_send_IPI_all)(vector);
455}
456
457static __always_inline void __apic_send_IPI_self(int vector)
458{
459 static_call_mod(apic_call_send_IPI_self)(vector);
460}
461
462static __always_inline void apic_wait_icr_idle(void)
463{
464 static_call_cond(apic_call_wait_icr_idle)();
465}
466
467static __always_inline u32 safe_apic_wait_icr_idle(void)
468{
469 return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0;
470}
471
472static __always_inline bool apic_id_valid(u32 apic_id)
473{
474 return apic_id <= apic->max_apic_id;
475}
476
477#else /* CONFIG_X86_LOCAL_APIC */
478
479static inline u32 apic_read(u32 reg) { return 0; }
480static inline void apic_write(u32 reg, u32 val) { }
481static inline void apic_eoi(void) { }
482static inline u64 apic_icr_read(void) { return 0; }
483static inline void apic_icr_write(u32 low, u32 high) { }
484static inline void apic_wait_icr_idle(void) { }
485static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
486static inline void apic_set_eoi_cb(void (*eoi)(void)) {}
487static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); }
488static inline void apic_setup_apic_calls(void) { }
489
490#define apic_update_callback(_callback, _fn) do { } while (0)
491
492#endif /* CONFIG_X86_LOCAL_APIC */
493
494extern void apic_ack_irq(struct irq_data *data);
495
496static inline bool lapic_vector_set_in_irr(unsigned int vector)
497{
498 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
499
500 return !!(irr & (1U << (vector % 32)));
501}
502
503/*
504 * Warm reset vector position:
505 */
506#define TRAMPOLINE_PHYS_LOW 0x467
507#define TRAMPOLINE_PHYS_HIGH 0x469
508
509extern void generic_bigsmp_probe(void);
510
511#ifdef CONFIG_X86_LOCAL_APIC
512
513#include <asm/smp.h>
514
515extern struct apic apic_noop;
516
517static inline u32 read_apic_id(void)
518{
519 u32 reg = apic_read(APIC_ID);
520
521 return apic->get_apic_id(reg);
522}
523
524#ifdef CONFIG_X86_64
525typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip);
526extern int default_acpi_madt_oem_check(char *, char *);
527extern void x86_64_probe_apic(void);
528#else
529static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; }
530static inline void x86_64_probe_apic(void) { }
531#endif
532
533extern int default_apic_id_valid(u32 apicid);
534
535extern u32 apic_default_calc_apicid(unsigned int cpu);
536extern u32 apic_flat_calc_apicid(unsigned int cpu);
537
538extern u32 default_cpu_present_to_apicid(int mps_cpu);
539
540void apic_send_nmi_to_offline_cpu(unsigned int cpu);
541
542#else /* CONFIG_X86_LOCAL_APIC */
543
544static inline u32 read_apic_id(void) { return 0; }
545
546#endif /* !CONFIG_X86_LOCAL_APIC */
547
548#ifdef CONFIG_SMP
549void apic_smt_update(void);
550#else
551static inline void apic_smt_update(void) { }
552#endif
553
554struct msi_msg;
555struct irq_cfg;
556
557extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
558 bool dmar);
559
560extern void ioapic_zap_locks(void);
561
562#endif /* _ASM_X86_APIC_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2#ifndef _ASM_X86_APIC_H
3#define _ASM_X86_APIC_H
4
5#include <linux/cpumask.h>
6
7#include <asm/alternative.h>
8#include <asm/cpufeature.h>
9#include <asm/apicdef.h>
10#include <linux/atomic.h>
11#include <asm/fixmap.h>
12#include <asm/mpspec.h>
13#include <asm/msr.h>
14#include <asm/hardirq.h>
15
16#define ARCH_APICTIMER_STOPS_ON_C3 1
17
18/*
19 * Debugging macros
20 */
21#define APIC_QUIET 0
22#define APIC_VERBOSE 1
23#define APIC_DEBUG 2
24
25/* Macros for apic_extnmi which controls external NMI masking */
26#define APIC_EXTNMI_BSP 0 /* Default */
27#define APIC_EXTNMI_ALL 1
28#define APIC_EXTNMI_NONE 2
29
30/*
31 * Define the default level of output to be very little
32 * This can be turned up by using apic=verbose for more
33 * information and apic=debug for _lots_ of information.
34 * apic_verbosity is defined in apic.c
35 */
36#define apic_printk(v, s, a...) do { \
37 if ((v) <= apic_verbosity) \
38 printk(s, ##a); \
39 } while (0)
40
41
42#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
43extern void generic_apic_probe(void);
44#else
45static inline void generic_apic_probe(void)
46{
47}
48#endif
49
50#ifdef CONFIG_X86_LOCAL_APIC
51
52extern int apic_verbosity;
53extern int local_apic_timer_c2_ok;
54
55extern int disable_apic;
56extern unsigned int lapic_timer_period;
57
58extern enum apic_intr_mode_id apic_intr_mode;
59enum apic_intr_mode_id {
60 APIC_PIC,
61 APIC_VIRTUAL_WIRE,
62 APIC_VIRTUAL_WIRE_NO_CONFIG,
63 APIC_SYMMETRIC_IO,
64 APIC_SYMMETRIC_IO_NO_ROUTING
65};
66
67#ifdef CONFIG_SMP
68extern void __inquire_remote_apic(int apicid);
69#else /* CONFIG_SMP */
70static inline void __inquire_remote_apic(int apicid)
71{
72}
73#endif /* CONFIG_SMP */
74
75static inline void default_inquire_remote_apic(int apicid)
76{
77 if (apic_verbosity >= APIC_DEBUG)
78 __inquire_remote_apic(apicid);
79}
80
81/*
82 * With 82489DX we can't rely on apic feature bit
83 * retrieved via cpuid but still have to deal with
84 * such an apic chip so we assume that SMP configuration
85 * is found from MP table (64bit case uses ACPI mostly
86 * which set smp presence flag as well so we are safe
87 * to use this helper too).
88 */
89static inline bool apic_from_smp_config(void)
90{
91 return smp_found_config && !disable_apic;
92}
93
94/*
95 * Basic functions accessing APICs.
96 */
97#ifdef CONFIG_PARAVIRT
98#include <asm/paravirt.h>
99#endif
100
101extern int setup_profiling_timer(unsigned int);
102
103static inline void native_apic_mem_write(u32 reg, u32 v)
104{
105 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
106
107 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
108 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
109 ASM_OUTPUT2("0" (v), "m" (*addr)));
110}
111
112static inline u32 native_apic_mem_read(u32 reg)
113{
114 return *((volatile u32 *)(APIC_BASE + reg));
115}
116
117extern void native_apic_wait_icr_idle(void);
118extern u32 native_safe_apic_wait_icr_idle(void);
119extern void native_apic_icr_write(u32 low, u32 id);
120extern u64 native_apic_icr_read(void);
121
122static inline bool apic_is_x2apic_enabled(void)
123{
124 u64 msr;
125
126 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
127 return false;
128 return msr & X2APIC_ENABLE;
129}
130
131extern void enable_IR_x2apic(void);
132
133extern int get_physical_broadcast(void);
134
135extern int lapic_get_maxlvt(void);
136extern void clear_local_APIC(void);
137extern void disconnect_bsp_APIC(int virt_wire_setup);
138extern void disable_local_APIC(void);
139extern void apic_soft_disable(void);
140extern void lapic_shutdown(void);
141extern void sync_Arb_IDs(void);
142extern void init_bsp_APIC(void);
143extern void apic_intr_mode_select(void);
144extern void apic_intr_mode_init(void);
145extern void init_apic_mappings(void);
146void register_lapic_address(unsigned long address);
147extern void setup_boot_APIC_clock(void);
148extern void setup_secondary_APIC_clock(void);
149extern void lapic_update_tsc_freq(void);
150
151#ifdef CONFIG_X86_64
152static inline int apic_force_enable(unsigned long addr)
153{
154 return -1;
155}
156#else
157extern int apic_force_enable(unsigned long addr);
158#endif
159
160extern void apic_ap_setup(void);
161
162/*
163 * On 32bit this is mach-xxx local
164 */
165#ifdef CONFIG_X86_64
166extern int apic_is_clustered_box(void);
167#else
168static inline int apic_is_clustered_box(void)
169{
170 return 0;
171}
172#endif
173
174extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
175extern void lapic_assign_system_vectors(void);
176extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
177extern void lapic_online(void);
178extern void lapic_offline(void);
179extern bool apic_needs_pit(void);
180
181extern void apic_send_IPI_allbutself(unsigned int vector);
182
183#else /* !CONFIG_X86_LOCAL_APIC */
184static inline void lapic_shutdown(void) { }
185#define local_apic_timer_c2_ok 1
186static inline void init_apic_mappings(void) { }
187static inline void disable_local_APIC(void) { }
188# define setup_boot_APIC_clock x86_init_noop
189# define setup_secondary_APIC_clock x86_init_noop
190static inline void lapic_update_tsc_freq(void) { }
191static inline void init_bsp_APIC(void) { }
192static inline void apic_intr_mode_select(void) { }
193static inline void apic_intr_mode_init(void) { }
194static inline void lapic_assign_system_vectors(void) { }
195static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
196static inline bool apic_needs_pit(void) { return true; }
197#endif /* !CONFIG_X86_LOCAL_APIC */
198
199#ifdef CONFIG_X86_X2APIC
200/*
201 * Make previous memory operations globally visible before
202 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
203 * mfence for this.
204 */
205static inline void x2apic_wrmsr_fence(void)
206{
207 asm volatile("mfence" : : : "memory");
208}
209
210static inline void native_apic_msr_write(u32 reg, u32 v)
211{
212 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
213 reg == APIC_LVR)
214 return;
215
216 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
217}
218
219static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
220{
221 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
222}
223
224static inline u32 native_apic_msr_read(u32 reg)
225{
226 u64 msr;
227
228 if (reg == APIC_DFR)
229 return -1;
230
231 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
232 return (u32)msr;
233}
234
235static inline void native_x2apic_wait_icr_idle(void)
236{
237 /* no need to wait for icr idle in x2apic */
238 return;
239}
240
241static inline u32 native_safe_x2apic_wait_icr_idle(void)
242{
243 /* no need to wait for icr idle in x2apic */
244 return 0;
245}
246
247static inline void native_x2apic_icr_write(u32 low, u32 id)
248{
249 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
250}
251
252static inline u64 native_x2apic_icr_read(void)
253{
254 unsigned long val;
255
256 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
257 return val;
258}
259
260extern int x2apic_mode;
261extern int x2apic_phys;
262extern void __init check_x2apic(void);
263extern void x2apic_setup(void);
264static inline int x2apic_enabled(void)
265{
266 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
267}
268
269#define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
270#else /* !CONFIG_X86_X2APIC */
271static inline void check_x2apic(void) { }
272static inline void x2apic_setup(void) { }
273static inline int x2apic_enabled(void) { return 0; }
274
275#define x2apic_mode (0)
276#define x2apic_supported() (0)
277#endif /* !CONFIG_X86_X2APIC */
278
279struct irq_data;
280
281/*
282 * Copyright 2004 James Cleverdon, IBM.
283 *
284 * Generic APIC sub-arch data struct.
285 *
286 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
287 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
288 * James Cleverdon.
289 */
290struct apic {
291 /* Hotpath functions first */
292 void (*eoi_write)(u32 reg, u32 v);
293 void (*native_eoi_write)(u32 reg, u32 v);
294 void (*write)(u32 reg, u32 v);
295 u32 (*read)(u32 reg);
296
297 /* IPI related functions */
298 void (*wait_icr_idle)(void);
299 u32 (*safe_wait_icr_idle)(void);
300
301 void (*send_IPI)(int cpu, int vector);
302 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
303 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
304 void (*send_IPI_allbutself)(int vector);
305 void (*send_IPI_all)(int vector);
306 void (*send_IPI_self)(int vector);
307
308 /* dest_logical is used by the IPI functions */
309 u32 dest_logical;
310 u32 disable_esr;
311 u32 irq_delivery_mode;
312 u32 irq_dest_mode;
313
314 u32 (*calc_dest_apicid)(unsigned int cpu);
315
316 /* ICR related functions */
317 u64 (*icr_read)(void);
318 void (*icr_write)(u32 low, u32 high);
319
320 /* Probe, setup and smpboot functions */
321 int (*probe)(void);
322 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
323 int (*apic_id_valid)(u32 apicid);
324 int (*apic_id_registered)(void);
325
326 bool (*check_apicid_used)(physid_mask_t *map, int apicid);
327 void (*init_apic_ldr)(void);
328 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
329 void (*setup_apic_routing)(void);
330 int (*cpu_present_to_apicid)(int mps_cpu);
331 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
332 int (*check_phys_apicid_present)(int phys_apicid);
333 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
334
335 u32 (*get_apic_id)(unsigned long x);
336 u32 (*set_apic_id)(unsigned int id);
337
338 /* wakeup_secondary_cpu */
339 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
340
341 void (*inquire_remote_apic)(int apicid);
342
343#ifdef CONFIG_X86_32
344 /*
345 * Called very early during boot from get_smp_config(). It should
346 * return the logical apicid. x86_[bios]_cpu_to_apicid is
347 * initialized before this function is called.
348 *
349 * If logical apicid can't be determined that early, the function
350 * may return BAD_APICID. Logical apicid will be configured after
351 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
352 * won't be applied properly during early boot in this case.
353 */
354 int (*x86_32_early_logical_apicid)(int cpu);
355#endif
356 char *name;
357};
358
359/*
360 * Pointer to the local APIC driver in use on this system (there's
361 * always just one such driver in use - the kernel decides via an
362 * early probing process which one it picks - and then sticks to it):
363 */
364extern struct apic *apic;
365
366/*
367 * APIC drivers are probed based on how they are listed in the .apicdrivers
368 * section. So the order is important and enforced by the ordering
369 * of different apic driver files in the Makefile.
370 *
371 * For the files having two apic drivers, we use apic_drivers()
372 * to enforce the order with in them.
373 */
374#define apic_driver(sym) \
375 static const struct apic *__apicdrivers_##sym __used \
376 __aligned(sizeof(struct apic *)) \
377 __section(.apicdrivers) = { &sym }
378
379#define apic_drivers(sym1, sym2) \
380 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
381 __aligned(sizeof(struct apic *)) \
382 __section(.apicdrivers) = { &sym1, &sym2 }
383
384extern struct apic *__apicdrivers[], *__apicdrivers_end[];
385
386/*
387 * APIC functionality to boot other CPUs - only used on SMP:
388 */
389#ifdef CONFIG_SMP
390extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
391extern int lapic_can_unplug_cpu(void);
392#endif
393
394#ifdef CONFIG_X86_LOCAL_APIC
395
396static inline u32 apic_read(u32 reg)
397{
398 return apic->read(reg);
399}
400
401static inline void apic_write(u32 reg, u32 val)
402{
403 apic->write(reg, val);
404}
405
406static inline void apic_eoi(void)
407{
408 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
409}
410
411static inline u64 apic_icr_read(void)
412{
413 return apic->icr_read();
414}
415
416static inline void apic_icr_write(u32 low, u32 high)
417{
418 apic->icr_write(low, high);
419}
420
421static inline void apic_wait_icr_idle(void)
422{
423 apic->wait_icr_idle();
424}
425
426static inline u32 safe_apic_wait_icr_idle(void)
427{
428 return apic->safe_wait_icr_idle();
429}
430
431extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
432
433#else /* CONFIG_X86_LOCAL_APIC */
434
435static inline u32 apic_read(u32 reg) { return 0; }
436static inline void apic_write(u32 reg, u32 val) { }
437static inline void apic_eoi(void) { }
438static inline u64 apic_icr_read(void) { return 0; }
439static inline void apic_icr_write(u32 low, u32 high) { }
440static inline void apic_wait_icr_idle(void) { }
441static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
442static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
443
444#endif /* CONFIG_X86_LOCAL_APIC */
445
446extern void apic_ack_irq(struct irq_data *data);
447
448static inline void ack_APIC_irq(void)
449{
450 /*
451 * ack_APIC_irq() actually gets compiled as a single instruction
452 * ... yummie.
453 */
454 apic_eoi();
455}
456
457
458static inline bool lapic_vector_set_in_irr(unsigned int vector)
459{
460 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
461
462 return !!(irr & (1U << (vector % 32)));
463}
464
465static inline unsigned default_get_apic_id(unsigned long x)
466{
467 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
468
469 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
470 return (x >> 24) & 0xFF;
471 else
472 return (x >> 24) & 0x0F;
473}
474
475/*
476 * Warm reset vector position:
477 */
478#define TRAMPOLINE_PHYS_LOW 0x467
479#define TRAMPOLINE_PHYS_HIGH 0x469
480
481extern void generic_bigsmp_probe(void);
482
483#ifdef CONFIG_X86_LOCAL_APIC
484
485#include <asm/smp.h>
486
487#define APIC_DFR_VALUE (APIC_DFR_FLAT)
488
489DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
490
491extern struct apic apic_noop;
492
493static inline unsigned int read_apic_id(void)
494{
495 unsigned int reg = apic_read(APIC_ID);
496
497 return apic->get_apic_id(reg);
498}
499
500extern int default_apic_id_valid(u32 apicid);
501extern int default_acpi_madt_oem_check(char *, char *);
502extern void default_setup_apic_routing(void);
503
504extern u32 apic_default_calc_apicid(unsigned int cpu);
505extern u32 apic_flat_calc_apicid(unsigned int cpu);
506
507extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
508extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
509extern int default_cpu_present_to_apicid(int mps_cpu);
510extern int default_check_phys_apicid_present(int phys_apicid);
511
512#endif /* CONFIG_X86_LOCAL_APIC */
513
514#ifdef CONFIG_SMP
515bool apic_id_is_primary_thread(unsigned int id);
516void apic_smt_update(void);
517#else
518static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
519static inline void apic_smt_update(void) { }
520#endif
521
522extern void ioapic_zap_locks(void);
523
524#endif /* _ASM_X86_APIC_H */