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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2006 Intel Corporation. */
3
4/*
5 * e100.c: Intel(R) PRO/100 ethernet driver
6 *
7 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
8 * original e100 driver, but better described as a munging of
9 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
10 *
11 * References:
12 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
13 * Open Source Software Developers Manual,
14 * http://sourceforge.net/projects/e1000
15 *
16 *
17 * Theory of Operation
18 *
19 * I. General
20 *
21 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
22 * controller family, which includes the 82557, 82558, 82559, 82550,
23 * 82551, and 82562 devices. 82558 and greater controllers
24 * integrate the Intel 82555 PHY. The controllers are used in
25 * server and client network interface cards, as well as in
26 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
27 * configurations. 8255x supports a 32-bit linear addressing
28 * mode and operates at 33Mhz PCI clock rate.
29 *
30 * II. Driver Operation
31 *
32 * Memory-mapped mode is used exclusively to access the device's
33 * shared-memory structure, the Control/Status Registers (CSR). All
34 * setup, configuration, and control of the device, including queuing
35 * of Tx, Rx, and configuration commands is through the CSR.
36 * cmd_lock serializes accesses to the CSR command register. cb_lock
37 * protects the shared Command Block List (CBL).
38 *
39 * 8255x is highly MII-compliant and all access to the PHY go
40 * through the Management Data Interface (MDI). Consequently, the
41 * driver leverages the mii.c library shared with other MII-compliant
42 * devices.
43 *
44 * Big- and Little-Endian byte order as well as 32- and 64-bit
45 * archs are supported. Weak-ordered memory and non-cache-coherent
46 * archs are supported.
47 *
48 * III. Transmit
49 *
50 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
51 * together in a fixed-size ring (CBL) thus forming the flexible mode
52 * memory structure. A TCB marked with the suspend-bit indicates
53 * the end of the ring. The last TCB processed suspends the
54 * controller, and the controller can be restarted by issue a CU
55 * resume command to continue from the suspend point, or a CU start
56 * command to start at a given position in the ring.
57 *
58 * Non-Tx commands (config, multicast setup, etc) are linked
59 * into the CBL ring along with Tx commands. The common structure
60 * used for both Tx and non-Tx commands is the Command Block (CB).
61 *
62 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
63 * is the next CB to check for completion; cb_to_send is the first
64 * CB to start on in case of a previous failure to resume. CB clean
65 * up happens in interrupt context in response to a CU interrupt.
66 * cbs_avail keeps track of number of free CB resources available.
67 *
68 * Hardware padding of short packets to minimum packet size is
69 * enabled. 82557 pads with 7Eh, while the later controllers pad
70 * with 00h.
71 *
72 * IV. Receive
73 *
74 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
75 * Descriptors (RFD) + data buffer, thus forming the simplified mode
76 * memory structure. Rx skbs are allocated to contain both the RFD
77 * and the data buffer, but the RFD is pulled off before the skb is
78 * indicated. The data buffer is aligned such that encapsulated
79 * protocol headers are u32-aligned. Since the RFD is part of the
80 * mapped shared memory, and completion status is contained within
81 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
82 * view from software and hardware.
83 *
84 * In order to keep updates to the RFD link field from colliding with
85 * hardware writes to mark packets complete, we use the feature that
86 * hardware will not write to a size 0 descriptor and mark the previous
87 * packet as end-of-list (EL). After updating the link, we remove EL
88 * and only then restore the size such that hardware may use the
89 * previous-to-end RFD.
90 *
91 * Under typical operation, the receive unit (RU) is start once,
92 * and the controller happily fills RFDs as frames arrive. If
93 * replacement RFDs cannot be allocated, or the RU goes non-active,
94 * the RU must be restarted. Frame arrival generates an interrupt,
95 * and Rx indication and re-allocation happen in the same context,
96 * therefore no locking is required. A software-generated interrupt
97 * is generated from the watchdog to recover from a failed allocation
98 * scenario where all Rx resources have been indicated and none re-
99 * placed.
100 *
101 * V. Miscellaneous
102 *
103 * VLAN offloading of tagging, stripping and filtering is not
104 * supported, but driver will accommodate the extra 4-byte VLAN tag
105 * for processing by upper layers. Tx/Rx Checksum offloading is not
106 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
107 * not supported (hardware limitation).
108 *
109 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
110 *
111 * Thanks to JC (jchapman@katalix.com) for helping with
112 * testing/troubleshooting the development driver.
113 *
114 * TODO:
115 * o several entry points race with dev->close
116 * o check for tx-no-resources/stop Q races with tx clean/wake Q
117 *
118 * FIXES:
119 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
120 * - Stratus87247: protect MDI control register manipulations
121 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
122 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
123 */
124
125#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
126
127#include <linux/hardirq.h>
128#include <linux/interrupt.h>
129#include <linux/module.h>
130#include <linux/moduleparam.h>
131#include <linux/kernel.h>
132#include <linux/types.h>
133#include <linux/sched.h>
134#include <linux/slab.h>
135#include <linux/delay.h>
136#include <linux/init.h>
137#include <linux/pci.h>
138#include <linux/dma-mapping.h>
139#include <linux/dmapool.h>
140#include <linux/netdevice.h>
141#include <linux/etherdevice.h>
142#include <linux/mii.h>
143#include <linux/if_vlan.h>
144#include <linux/skbuff.h>
145#include <linux/ethtool.h>
146#include <linux/string.h>
147#include <linux/firmware.h>
148#include <linux/rtnetlink.h>
149#include <asm/unaligned.h>
150
151
152#define DRV_NAME "e100"
153#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
154#define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
155
156#define E100_WATCHDOG_PERIOD (2 * HZ)
157#define E100_NAPI_WEIGHT 16
158
159#define FIRMWARE_D101M "e100/d101m_ucode.bin"
160#define FIRMWARE_D101S "e100/d101s_ucode.bin"
161#define FIRMWARE_D102E "e100/d102e_ucode.bin"
162
163MODULE_DESCRIPTION(DRV_DESCRIPTION);
164MODULE_AUTHOR(DRV_COPYRIGHT);
165MODULE_LICENSE("GPL v2");
166MODULE_FIRMWARE(FIRMWARE_D101M);
167MODULE_FIRMWARE(FIRMWARE_D101S);
168MODULE_FIRMWARE(FIRMWARE_D102E);
169
170static int debug = 3;
171static int eeprom_bad_csum_allow = 0;
172static int use_io = 0;
173module_param(debug, int, 0);
174module_param(eeprom_bad_csum_allow, int, 0444);
175module_param(use_io, int, 0444);
176MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
177MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
178MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
179
180#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
181 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
182 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
183static const struct pci_device_id e100_id_table[] = {
184 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
185 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
186 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
187 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
188 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
189 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
190 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
191 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
192 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
193 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
194 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
196 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
197 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
198 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
199 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
200 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
204 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
205 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
206 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
207 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
208 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
209 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
213 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
214 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
215 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
216 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
217 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
218 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
219 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
220 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
221 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
222 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
223 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
224 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
225 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
226 { 0, }
227};
228MODULE_DEVICE_TABLE(pci, e100_id_table);
229
230enum mac {
231 mac_82557_D100_A = 0,
232 mac_82557_D100_B = 1,
233 mac_82557_D100_C = 2,
234 mac_82558_D101_A4 = 4,
235 mac_82558_D101_B0 = 5,
236 mac_82559_D101M = 8,
237 mac_82559_D101S = 9,
238 mac_82550_D102 = 12,
239 mac_82550_D102_C = 13,
240 mac_82551_E = 14,
241 mac_82551_F = 15,
242 mac_82551_10 = 16,
243 mac_unknown = 0xFF,
244};
245
246enum phy {
247 phy_100a = 0x000003E0,
248 phy_100c = 0x035002A8,
249 phy_82555_tx = 0x015002A8,
250 phy_nsc_tx = 0x5C002000,
251 phy_82562_et = 0x033002A8,
252 phy_82562_em = 0x032002A8,
253 phy_82562_ek = 0x031002A8,
254 phy_82562_eh = 0x017002A8,
255 phy_82552_v = 0xd061004d,
256 phy_unknown = 0xFFFFFFFF,
257};
258
259/* CSR (Control/Status Registers) */
260struct csr {
261 struct {
262 u8 status;
263 u8 stat_ack;
264 u8 cmd_lo;
265 u8 cmd_hi;
266 u32 gen_ptr;
267 } scb;
268 u32 port;
269 u16 flash_ctrl;
270 u8 eeprom_ctrl_lo;
271 u8 eeprom_ctrl_hi;
272 u32 mdi_ctrl;
273 u32 rx_dma_count;
274};
275
276enum scb_status {
277 rus_no_res = 0x08,
278 rus_ready = 0x10,
279 rus_mask = 0x3C,
280};
281
282enum ru_state {
283 RU_SUSPENDED = 0,
284 RU_RUNNING = 1,
285 RU_UNINITIALIZED = -1,
286};
287
288enum scb_stat_ack {
289 stat_ack_not_ours = 0x00,
290 stat_ack_sw_gen = 0x04,
291 stat_ack_rnr = 0x10,
292 stat_ack_cu_idle = 0x20,
293 stat_ack_frame_rx = 0x40,
294 stat_ack_cu_cmd_done = 0x80,
295 stat_ack_not_present = 0xFF,
296 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
297 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
298};
299
300enum scb_cmd_hi {
301 irq_mask_none = 0x00,
302 irq_mask_all = 0x01,
303 irq_sw_gen = 0x02,
304};
305
306enum scb_cmd_lo {
307 cuc_nop = 0x00,
308 ruc_start = 0x01,
309 ruc_load_base = 0x06,
310 cuc_start = 0x10,
311 cuc_resume = 0x20,
312 cuc_dump_addr = 0x40,
313 cuc_dump_stats = 0x50,
314 cuc_load_base = 0x60,
315 cuc_dump_reset = 0x70,
316};
317
318enum cuc_dump {
319 cuc_dump_complete = 0x0000A005,
320 cuc_dump_reset_complete = 0x0000A007,
321};
322
323enum port {
324 software_reset = 0x0000,
325 selftest = 0x0001,
326 selective_reset = 0x0002,
327};
328
329enum eeprom_ctrl_lo {
330 eesk = 0x01,
331 eecs = 0x02,
332 eedi = 0x04,
333 eedo = 0x08,
334};
335
336enum mdi_ctrl {
337 mdi_write = 0x04000000,
338 mdi_read = 0x08000000,
339 mdi_ready = 0x10000000,
340};
341
342enum eeprom_op {
343 op_write = 0x05,
344 op_read = 0x06,
345 op_ewds = 0x10,
346 op_ewen = 0x13,
347};
348
349enum eeprom_offsets {
350 eeprom_cnfg_mdix = 0x03,
351 eeprom_phy_iface = 0x06,
352 eeprom_id = 0x0A,
353 eeprom_config_asf = 0x0D,
354 eeprom_smbus_addr = 0x90,
355};
356
357enum eeprom_cnfg_mdix {
358 eeprom_mdix_enabled = 0x0080,
359};
360
361enum eeprom_phy_iface {
362 NoSuchPhy = 0,
363 I82553AB,
364 I82553C,
365 I82503,
366 DP83840,
367 S80C240,
368 S80C24,
369 I82555,
370 DP83840A = 10,
371};
372
373enum eeprom_id {
374 eeprom_id_wol = 0x0020,
375};
376
377enum eeprom_config_asf {
378 eeprom_asf = 0x8000,
379 eeprom_gcl = 0x4000,
380};
381
382enum cb_status {
383 cb_complete = 0x8000,
384 cb_ok = 0x2000,
385};
386
387/*
388 * cb_command - Command Block flags
389 * @cb_tx_nc: 0: controller does CRC (normal), 1: CRC from skb memory
390 */
391enum cb_command {
392 cb_nop = 0x0000,
393 cb_iaaddr = 0x0001,
394 cb_config = 0x0002,
395 cb_multi = 0x0003,
396 cb_tx = 0x0004,
397 cb_ucode = 0x0005,
398 cb_dump = 0x0006,
399 cb_tx_sf = 0x0008,
400 cb_tx_nc = 0x0010,
401 cb_cid = 0x1f00,
402 cb_i = 0x2000,
403 cb_s = 0x4000,
404 cb_el = 0x8000,
405};
406
407struct rfd {
408 __le16 status;
409 __le16 command;
410 __le32 link;
411 __le32 rbd;
412 __le16 actual_size;
413 __le16 size;
414};
415
416struct rx {
417 struct rx *next, *prev;
418 struct sk_buff *skb;
419 dma_addr_t dma_addr;
420};
421
422#if defined(__BIG_ENDIAN_BITFIELD)
423#define X(a,b) b,a
424#else
425#define X(a,b) a,b
426#endif
427struct config {
428/*0*/ u8 X(byte_count:6, pad0:2);
429/*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
430/*2*/ u8 adaptive_ifs;
431/*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
432 term_write_cache_line:1), pad3:4);
433/*4*/ u8 X(rx_dma_max_count:7, pad4:1);
434/*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
435/*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
436 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
437 rx_save_overruns : 1), rx_save_bad_frames : 1);
438/*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
439 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
440 tx_dynamic_tbd:1);
441/*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
442/*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
443 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
444/*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
445 loopback:2);
446/*11*/ u8 X(linear_priority:3, pad11:5);
447/*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
448/*13*/ u8 ip_addr_lo;
449/*14*/ u8 ip_addr_hi;
450/*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
451 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
452 pad15_2:1), crs_or_cdt:1);
453/*16*/ u8 fc_delay_lo;
454/*17*/ u8 fc_delay_hi;
455/*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
456 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
457/*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
458 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
459 full_duplex_force:1), full_duplex_pin:1);
460/*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
461/*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
462/*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
463 u8 pad_d102[9];
464};
465
466#define E100_MAX_MULTICAST_ADDRS 64
467struct multi {
468 __le16 count;
469 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
470};
471
472/* Important: keep total struct u32-aligned */
473#define UCODE_SIZE 134
474struct cb {
475 __le16 status;
476 __le16 command;
477 __le32 link;
478 union {
479 u8 iaaddr[ETH_ALEN];
480 __le32 ucode[UCODE_SIZE];
481 struct config config;
482 struct multi multi;
483 struct {
484 u32 tbd_array;
485 u16 tcb_byte_count;
486 u8 threshold;
487 u8 tbd_count;
488 struct {
489 __le32 buf_addr;
490 __le16 size;
491 u16 eol;
492 } tbd;
493 } tcb;
494 __le32 dump_buffer_addr;
495 } u;
496 struct cb *next, *prev;
497 dma_addr_t dma_addr;
498 struct sk_buff *skb;
499};
500
501enum loopback {
502 lb_none = 0, lb_mac = 1, lb_phy = 3,
503};
504
505struct stats {
506 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
507 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
508 tx_multiple_collisions, tx_total_collisions;
509 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
510 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
511 rx_short_frame_errors;
512 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
513 __le16 xmt_tco_frames, rcv_tco_frames;
514 __le32 complete;
515};
516
517struct mem {
518 struct {
519 u32 signature;
520 u32 result;
521 } selftest;
522 struct stats stats;
523 u8 dump_buf[596];
524};
525
526struct param_range {
527 u32 min;
528 u32 max;
529 u32 count;
530};
531
532struct params {
533 struct param_range rfds;
534 struct param_range cbs;
535};
536
537struct nic {
538 /* Begin: frequently used values: keep adjacent for cache effect */
539 u32 msg_enable ____cacheline_aligned;
540 struct net_device *netdev;
541 struct pci_dev *pdev;
542 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
543
544 struct rx *rxs ____cacheline_aligned;
545 struct rx *rx_to_use;
546 struct rx *rx_to_clean;
547 struct rfd blank_rfd;
548 enum ru_state ru_running;
549
550 spinlock_t cb_lock ____cacheline_aligned;
551 spinlock_t cmd_lock;
552 struct csr __iomem *csr;
553 enum scb_cmd_lo cuc_cmd;
554 unsigned int cbs_avail;
555 struct napi_struct napi;
556 struct cb *cbs;
557 struct cb *cb_to_use;
558 struct cb *cb_to_send;
559 struct cb *cb_to_clean;
560 __le16 tx_command;
561 /* End: frequently used values: keep adjacent for cache effect */
562
563 enum {
564 ich = (1 << 0),
565 promiscuous = (1 << 1),
566 multicast_all = (1 << 2),
567 wol_magic = (1 << 3),
568 ich_10h_workaround = (1 << 4),
569 } flags ____cacheline_aligned;
570
571 enum mac mac;
572 enum phy phy;
573 struct params params;
574 struct timer_list watchdog;
575 struct mii_if_info mii;
576 struct work_struct tx_timeout_task;
577 enum loopback loopback;
578
579 struct mem *mem;
580 dma_addr_t dma_addr;
581
582 struct dma_pool *cbs_pool;
583 dma_addr_t cbs_dma_addr;
584 u8 adaptive_ifs;
585 u8 tx_threshold;
586 u32 tx_frames;
587 u32 tx_collisions;
588 u32 tx_deferred;
589 u32 tx_single_collisions;
590 u32 tx_multiple_collisions;
591 u32 tx_fc_pause;
592 u32 tx_tco_frames;
593
594 u32 rx_fc_pause;
595 u32 rx_fc_unsupported;
596 u32 rx_tco_frames;
597 u32 rx_short_frame_errors;
598 u32 rx_over_length_errors;
599
600 u16 eeprom_wc;
601 __le16 eeprom[256];
602 spinlock_t mdio_lock;
603 const struct firmware *fw;
604};
605
606static inline void e100_write_flush(struct nic *nic)
607{
608 /* Flush previous PCI writes through intermediate bridges
609 * by doing a benign read */
610 (void)ioread8(&nic->csr->scb.status);
611}
612
613static void e100_enable_irq(struct nic *nic)
614{
615 unsigned long flags;
616
617 spin_lock_irqsave(&nic->cmd_lock, flags);
618 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
619 e100_write_flush(nic);
620 spin_unlock_irqrestore(&nic->cmd_lock, flags);
621}
622
623static void e100_disable_irq(struct nic *nic)
624{
625 unsigned long flags;
626
627 spin_lock_irqsave(&nic->cmd_lock, flags);
628 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
629 e100_write_flush(nic);
630 spin_unlock_irqrestore(&nic->cmd_lock, flags);
631}
632
633static void e100_hw_reset(struct nic *nic)
634{
635 /* Put CU and RU into idle with a selective reset to get
636 * device off of PCI bus */
637 iowrite32(selective_reset, &nic->csr->port);
638 e100_write_flush(nic); udelay(20);
639
640 /* Now fully reset device */
641 iowrite32(software_reset, &nic->csr->port);
642 e100_write_flush(nic); udelay(20);
643
644 /* Mask off our interrupt line - it's unmasked after reset */
645 e100_disable_irq(nic);
646}
647
648static int e100_self_test(struct nic *nic)
649{
650 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
651
652 /* Passing the self-test is a pretty good indication
653 * that the device can DMA to/from host memory */
654
655 nic->mem->selftest.signature = 0;
656 nic->mem->selftest.result = 0xFFFFFFFF;
657
658 iowrite32(selftest | dma_addr, &nic->csr->port);
659 e100_write_flush(nic);
660 /* Wait 10 msec for self-test to complete */
661 msleep(10);
662
663 /* Interrupts are enabled after self-test */
664 e100_disable_irq(nic);
665
666 /* Check results of self-test */
667 if (nic->mem->selftest.result != 0) {
668 netif_err(nic, hw, nic->netdev,
669 "Self-test failed: result=0x%08X\n",
670 nic->mem->selftest.result);
671 return -ETIMEDOUT;
672 }
673 if (nic->mem->selftest.signature == 0) {
674 netif_err(nic, hw, nic->netdev, "Self-test failed: timed out\n");
675 return -ETIMEDOUT;
676 }
677
678 return 0;
679}
680
681static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
682{
683 u32 cmd_addr_data[3];
684 u8 ctrl;
685 int i, j;
686
687 /* Three cmds: write/erase enable, write data, write/erase disable */
688 cmd_addr_data[0] = op_ewen << (addr_len - 2);
689 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
690 le16_to_cpu(data);
691 cmd_addr_data[2] = op_ewds << (addr_len - 2);
692
693 /* Bit-bang cmds to write word to eeprom */
694 for (j = 0; j < 3; j++) {
695
696 /* Chip select */
697 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
698 e100_write_flush(nic); udelay(4);
699
700 for (i = 31; i >= 0; i--) {
701 ctrl = (cmd_addr_data[j] & (1 << i)) ?
702 eecs | eedi : eecs;
703 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
704 e100_write_flush(nic); udelay(4);
705
706 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
707 e100_write_flush(nic); udelay(4);
708 }
709 /* Wait 10 msec for cmd to complete */
710 msleep(10);
711
712 /* Chip deselect */
713 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
714 e100_write_flush(nic); udelay(4);
715 }
716};
717
718/* General technique stolen from the eepro100 driver - very clever */
719static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
720{
721 u32 cmd_addr_data;
722 u16 data = 0;
723 u8 ctrl;
724 int i;
725
726 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
727
728 /* Chip select */
729 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
730 e100_write_flush(nic); udelay(4);
731
732 /* Bit-bang to read word from eeprom */
733 for (i = 31; i >= 0; i--) {
734 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
735 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
736 e100_write_flush(nic); udelay(4);
737
738 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
739 e100_write_flush(nic); udelay(4);
740
741 /* Eeprom drives a dummy zero to EEDO after receiving
742 * complete address. Use this to adjust addr_len. */
743 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
744 if (!(ctrl & eedo) && i > 16) {
745 *addr_len -= (i - 16);
746 i = 17;
747 }
748
749 data = (data << 1) | (ctrl & eedo ? 1 : 0);
750 }
751
752 /* Chip deselect */
753 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
754 e100_write_flush(nic); udelay(4);
755
756 return cpu_to_le16(data);
757};
758
759/* Load entire EEPROM image into driver cache and validate checksum */
760static int e100_eeprom_load(struct nic *nic)
761{
762 u16 addr, addr_len = 8, checksum = 0;
763
764 /* Try reading with an 8-bit addr len to discover actual addr len */
765 e100_eeprom_read(nic, &addr_len, 0);
766 nic->eeprom_wc = 1 << addr_len;
767
768 for (addr = 0; addr < nic->eeprom_wc; addr++) {
769 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
770 if (addr < nic->eeprom_wc - 1)
771 checksum += le16_to_cpu(nic->eeprom[addr]);
772 }
773
774 /* The checksum, stored in the last word, is calculated such that
775 * the sum of words should be 0xBABA */
776 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
777 netif_err(nic, probe, nic->netdev, "EEPROM corrupted\n");
778 if (!eeprom_bad_csum_allow)
779 return -EAGAIN;
780 }
781
782 return 0;
783}
784
785/* Save (portion of) driver EEPROM cache to device and update checksum */
786static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
787{
788 u16 addr, addr_len = 8, checksum = 0;
789
790 /* Try reading with an 8-bit addr len to discover actual addr len */
791 e100_eeprom_read(nic, &addr_len, 0);
792 nic->eeprom_wc = 1 << addr_len;
793
794 if (start + count >= nic->eeprom_wc)
795 return -EINVAL;
796
797 for (addr = start; addr < start + count; addr++)
798 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
799
800 /* The checksum, stored in the last word, is calculated such that
801 * the sum of words should be 0xBABA */
802 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
803 checksum += le16_to_cpu(nic->eeprom[addr]);
804 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
805 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
806 nic->eeprom[nic->eeprom_wc - 1]);
807
808 return 0;
809}
810
811#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
812#define E100_WAIT_SCB_FAST 20 /* delay like the old code */
813static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
814{
815 unsigned long flags;
816 unsigned int i;
817 int err = 0;
818
819 spin_lock_irqsave(&nic->cmd_lock, flags);
820
821 /* Previous command is accepted when SCB clears */
822 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
823 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
824 break;
825 cpu_relax();
826 if (unlikely(i > E100_WAIT_SCB_FAST))
827 udelay(5);
828 }
829 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
830 err = -EAGAIN;
831 goto err_unlock;
832 }
833
834 if (unlikely(cmd != cuc_resume))
835 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
836 iowrite8(cmd, &nic->csr->scb.cmd_lo);
837
838err_unlock:
839 spin_unlock_irqrestore(&nic->cmd_lock, flags);
840
841 return err;
842}
843
844static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
845 int (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
846{
847 struct cb *cb;
848 unsigned long flags;
849 int err;
850
851 spin_lock_irqsave(&nic->cb_lock, flags);
852
853 if (unlikely(!nic->cbs_avail)) {
854 err = -ENOMEM;
855 goto err_unlock;
856 }
857
858 cb = nic->cb_to_use;
859 nic->cb_to_use = cb->next;
860 nic->cbs_avail--;
861 cb->skb = skb;
862
863 err = cb_prepare(nic, cb, skb);
864 if (err)
865 goto err_unlock;
866
867 if (unlikely(!nic->cbs_avail))
868 err = -ENOSPC;
869
870
871 /* Order is important otherwise we'll be in a race with h/w:
872 * set S-bit in current first, then clear S-bit in previous. */
873 cb->command |= cpu_to_le16(cb_s);
874 dma_wmb();
875 cb->prev->command &= cpu_to_le16(~cb_s);
876
877 while (nic->cb_to_send != nic->cb_to_use) {
878 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
879 nic->cb_to_send->dma_addr))) {
880 /* Ok, here's where things get sticky. It's
881 * possible that we can't schedule the command
882 * because the controller is too busy, so
883 * let's just queue the command and try again
884 * when another command is scheduled. */
885 if (err == -ENOSPC) {
886 //request a reset
887 schedule_work(&nic->tx_timeout_task);
888 }
889 break;
890 } else {
891 nic->cuc_cmd = cuc_resume;
892 nic->cb_to_send = nic->cb_to_send->next;
893 }
894 }
895
896err_unlock:
897 spin_unlock_irqrestore(&nic->cb_lock, flags);
898
899 return err;
900}
901
902static int mdio_read(struct net_device *netdev, int addr, int reg)
903{
904 struct nic *nic = netdev_priv(netdev);
905 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
906}
907
908static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
909{
910 struct nic *nic = netdev_priv(netdev);
911
912 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
913}
914
915/* the standard mdio_ctrl() function for usual MII-compliant hardware */
916static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
917{
918 u32 data_out = 0;
919 unsigned int i;
920 unsigned long flags;
921
922
923 /*
924 * Stratus87247: we shouldn't be writing the MDI control
925 * register until the Ready bit shows True. Also, since
926 * manipulation of the MDI control registers is a multi-step
927 * procedure it should be done under lock.
928 */
929 spin_lock_irqsave(&nic->mdio_lock, flags);
930 for (i = 100; i; --i) {
931 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
932 break;
933 udelay(20);
934 }
935 if (unlikely(!i)) {
936 netdev_err(nic->netdev, "e100.mdio_ctrl won't go Ready\n");
937 spin_unlock_irqrestore(&nic->mdio_lock, flags);
938 return 0; /* No way to indicate timeout error */
939 }
940 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
941
942 for (i = 0; i < 100; i++) {
943 udelay(20);
944 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
945 break;
946 }
947 spin_unlock_irqrestore(&nic->mdio_lock, flags);
948 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
949 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
950 dir == mdi_read ? "READ" : "WRITE",
951 addr, reg, data, data_out);
952 return (u16)data_out;
953}
954
955/* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
956static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
957 u32 addr,
958 u32 dir,
959 u32 reg,
960 u16 data)
961{
962 if ((reg == MII_BMCR) && (dir == mdi_write)) {
963 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
964 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
965 MII_ADVERTISE);
966
967 /*
968 * Workaround Si issue where sometimes the part will not
969 * autoneg to 100Mbps even when advertised.
970 */
971 if (advert & ADVERTISE_100FULL)
972 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
973 else if (advert & ADVERTISE_100HALF)
974 data |= BMCR_SPEED100;
975 }
976 }
977 return mdio_ctrl_hw(nic, addr, dir, reg, data);
978}
979
980/* Fully software-emulated mdio_ctrl() function for cards without
981 * MII-compliant PHYs.
982 * For now, this is mainly geared towards 80c24 support; in case of further
983 * requirements for other types (i82503, ...?) either extend this mechanism
984 * or split it, whichever is cleaner.
985 */
986static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
987 u32 addr,
988 u32 dir,
989 u32 reg,
990 u16 data)
991{
992 /* might need to allocate a netdev_priv'ed register array eventually
993 * to be able to record state changes, but for now
994 * some fully hardcoded register handling ought to be ok I guess. */
995
996 if (dir == mdi_read) {
997 switch (reg) {
998 case MII_BMCR:
999 /* Auto-negotiation, right? */
1000 return BMCR_ANENABLE |
1001 BMCR_FULLDPLX;
1002 case MII_BMSR:
1003 return BMSR_LSTATUS /* for mii_link_ok() */ |
1004 BMSR_ANEGCAPABLE |
1005 BMSR_10FULL;
1006 case MII_ADVERTISE:
1007 /* 80c24 is a "combo card" PHY, right? */
1008 return ADVERTISE_10HALF |
1009 ADVERTISE_10FULL;
1010 default:
1011 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1012 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1013 dir == mdi_read ? "READ" : "WRITE",
1014 addr, reg, data);
1015 return 0xFFFF;
1016 }
1017 } else {
1018 switch (reg) {
1019 default:
1020 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1021 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1022 dir == mdi_read ? "READ" : "WRITE",
1023 addr, reg, data);
1024 return 0xFFFF;
1025 }
1026 }
1027}
1028static inline int e100_phy_supports_mii(struct nic *nic)
1029{
1030 /* for now, just check it by comparing whether we
1031 are using MII software emulation.
1032 */
1033 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1034}
1035
1036static void e100_get_defaults(struct nic *nic)
1037{
1038 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1039 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1040
1041 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
1042 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
1043 if (nic->mac == mac_unknown)
1044 nic->mac = mac_82557_D100_A;
1045
1046 nic->params.rfds = rfds;
1047 nic->params.cbs = cbs;
1048
1049 /* Quadwords to DMA into FIFO before starting frame transmit */
1050 nic->tx_threshold = 0xE0;
1051
1052 /* no interrupt for every tx completion, delay = 256us if not 557 */
1053 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1054 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1055
1056 /* Template for a freshly allocated RFD */
1057 nic->blank_rfd.command = 0;
1058 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1059 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN);
1060
1061 /* MII setup */
1062 nic->mii.phy_id_mask = 0x1F;
1063 nic->mii.reg_num_mask = 0x1F;
1064 nic->mii.dev = nic->netdev;
1065 nic->mii.mdio_read = mdio_read;
1066 nic->mii.mdio_write = mdio_write;
1067}
1068
1069static int e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1070{
1071 struct config *config = &cb->u.config;
1072 u8 *c = (u8 *)config;
1073 struct net_device *netdev = nic->netdev;
1074
1075 cb->command = cpu_to_le16(cb_config);
1076
1077 memset(config, 0, sizeof(struct config));
1078
1079 config->byte_count = 0x16; /* bytes in this struct */
1080 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1081 config->direct_rx_dma = 0x1; /* reserved */
1082 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1083 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1084 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1085 config->tx_underrun_retry = 0x3; /* # of underrun retries */
1086 if (e100_phy_supports_mii(nic))
1087 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1088 config->pad10 = 0x6;
1089 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1090 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1091 config->ifs = 0x6; /* x16 = inter frame spacing */
1092 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1093 config->pad15_1 = 0x1;
1094 config->pad15_2 = 0x1;
1095 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1096 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1097 config->tx_padding = 0x1; /* 1=pad short frames */
1098 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1099 config->pad18 = 0x1;
1100 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1101 config->pad20_1 = 0x1F;
1102 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1103 config->pad21_1 = 0x5;
1104
1105 config->adaptive_ifs = nic->adaptive_ifs;
1106 config->loopback = nic->loopback;
1107
1108 if (nic->mii.force_media && nic->mii.full_duplex)
1109 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1110
1111 if (nic->flags & promiscuous || nic->loopback) {
1112 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1113 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1114 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1115 }
1116
1117 if (unlikely(netdev->features & NETIF_F_RXFCS))
1118 config->rx_crc_transfer = 0x1; /* 1=save, 0=discard */
1119
1120 if (nic->flags & multicast_all)
1121 config->multicast_all = 0x1; /* 1=accept, 0=no */
1122
1123 /* disable WoL when up */
1124 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1125 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1126
1127 if (nic->mac >= mac_82558_D101_A4) {
1128 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1129 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1130 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1131 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1132 if (nic->mac >= mac_82559_D101M) {
1133 config->tno_intr = 0x1; /* TCO stats enable */
1134 /* Enable TCO in extended config */
1135 if (nic->mac >= mac_82551_10) {
1136 config->byte_count = 0x20; /* extended bytes */
1137 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1138 }
1139 } else {
1140 config->standard_stat_counter = 0x0;
1141 }
1142 }
1143
1144 if (netdev->features & NETIF_F_RXALL) {
1145 config->rx_save_overruns = 0x1; /* 1=save, 0=discard */
1146 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1147 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1148 }
1149
1150 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[00-07]=%8ph\n",
1151 c + 0);
1152 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[08-15]=%8ph\n",
1153 c + 8);
1154 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[16-23]=%8ph\n",
1155 c + 16);
1156 return 0;
1157}
1158
1159/*************************************************************************
1160* CPUSaver parameters
1161*
1162* All CPUSaver parameters are 16-bit literals that are part of a
1163* "move immediate value" instruction. By changing the value of
1164* the literal in the instruction before the code is loaded, the
1165* driver can change the algorithm.
1166*
1167* INTDELAY - This loads the dead-man timer with its initial value.
1168* When this timer expires the interrupt is asserted, and the
1169* timer is reset each time a new packet is received. (see
1170* BUNDLEMAX below to set the limit on number of chained packets)
1171* The current default is 0x600 or 1536. Experiments show that
1172* the value should probably stay within the 0x200 - 0x1000.
1173*
1174* BUNDLEMAX -
1175* This sets the maximum number of frames that will be bundled. In
1176* some situations, such as the TCP windowing algorithm, it may be
1177* better to limit the growth of the bundle size than let it go as
1178* high as it can, because that could cause too much added latency.
1179* The default is six, because this is the number of packets in the
1180* default TCP window size. A value of 1 would make CPUSaver indicate
1181* an interrupt for every frame received. If you do not want to put
1182* a limit on the bundle size, set this value to xFFFF.
1183*
1184* BUNDLESMALL -
1185* This contains a bit-mask describing the minimum size frame that
1186* will be bundled. The default masks the lower 7 bits, which means
1187* that any frame less than 128 bytes in length will not be bundled,
1188* but will instead immediately generate an interrupt. This does
1189* not affect the current bundle in any way. Any frame that is 128
1190* bytes or large will be bundled normally. This feature is meant
1191* to provide immediate indication of ACK frames in a TCP environment.
1192* Customers were seeing poor performance when a machine with CPUSaver
1193* enabled was sending but not receiving. The delay introduced when
1194* the ACKs were received was enough to reduce total throughput, because
1195* the sender would sit idle until the ACK was finally seen.
1196*
1197* The current default is 0xFF80, which masks out the lower 7 bits.
1198* This means that any frame which is x7F (127) bytes or smaller
1199* will cause an immediate interrupt. Because this value must be a
1200* bit mask, there are only a few valid values that can be used. To
1201* turn this feature off, the driver can write the value xFFFF to the
1202* lower word of this instruction (in the same way that the other
1203* parameters are used). Likewise, a value of 0xF800 (2047) would
1204* cause an interrupt to be generated for every frame, because all
1205* standard Ethernet frames are <= 2047 bytes in length.
1206*************************************************************************/
1207
1208/* if you wish to disable the ucode functionality, while maintaining the
1209 * workarounds it provides, set the following defines to:
1210 * BUNDLESMALL 0
1211 * BUNDLEMAX 1
1212 * INTDELAY 1
1213 */
1214#define BUNDLESMALL 1
1215#define BUNDLEMAX (u16)6
1216#define INTDELAY (u16)1536 /* 0x600 */
1217
1218/* Initialize firmware */
1219static const struct firmware *e100_request_firmware(struct nic *nic)
1220{
1221 const char *fw_name;
1222 const struct firmware *fw = nic->fw;
1223 u8 timer, bundle, min_size;
1224 int err = 0;
1225 bool required = false;
1226
1227 /* do not load u-code for ICH devices */
1228 if (nic->flags & ich)
1229 return NULL;
1230
1231 /* Search for ucode match against h/w revision
1232 *
1233 * Based on comments in the source code for the FreeBSD fxp
1234 * driver, the FIRMWARE_D102E ucode includes both CPUSaver and
1235 *
1236 * "fixes for bugs in the B-step hardware (specifically, bugs
1237 * with Inline Receive)."
1238 *
1239 * So we must fail if it cannot be loaded.
1240 *
1241 * The other microcode files are only required for the optional
1242 * CPUSaver feature. Nice to have, but no reason to fail.
1243 */
1244 if (nic->mac == mac_82559_D101M) {
1245 fw_name = FIRMWARE_D101M;
1246 } else if (nic->mac == mac_82559_D101S) {
1247 fw_name = FIRMWARE_D101S;
1248 } else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10) {
1249 fw_name = FIRMWARE_D102E;
1250 required = true;
1251 } else { /* No ucode on other devices */
1252 return NULL;
1253 }
1254
1255 /* If the firmware has not previously been loaded, request a pointer
1256 * to it. If it was previously loaded, we are reinitializing the
1257 * adapter, possibly in a resume from hibernate, in which case
1258 * request_firmware() cannot be used.
1259 */
1260 if (!fw)
1261 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1262
1263 if (err) {
1264 if (required) {
1265 netif_err(nic, probe, nic->netdev,
1266 "Failed to load firmware \"%s\": %d\n",
1267 fw_name, err);
1268 return ERR_PTR(err);
1269 } else {
1270 netif_info(nic, probe, nic->netdev,
1271 "CPUSaver disabled. Needs \"%s\": %d\n",
1272 fw_name, err);
1273 return NULL;
1274 }
1275 }
1276
1277 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1278 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1279 if (fw->size != UCODE_SIZE * 4 + 3) {
1280 netif_err(nic, probe, nic->netdev,
1281 "Firmware \"%s\" has wrong size %zu\n",
1282 fw_name, fw->size);
1283 release_firmware(fw);
1284 return ERR_PTR(-EINVAL);
1285 }
1286
1287 /* Read timer, bundle and min_size from end of firmware blob */
1288 timer = fw->data[UCODE_SIZE * 4];
1289 bundle = fw->data[UCODE_SIZE * 4 + 1];
1290 min_size = fw->data[UCODE_SIZE * 4 + 2];
1291
1292 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1293 min_size >= UCODE_SIZE) {
1294 netif_err(nic, probe, nic->netdev,
1295 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1296 fw_name, timer, bundle, min_size);
1297 release_firmware(fw);
1298 return ERR_PTR(-EINVAL);
1299 }
1300
1301 /* OK, firmware is validated and ready to use. Save a pointer
1302 * to it in the nic */
1303 nic->fw = fw;
1304 return fw;
1305}
1306
1307static int e100_setup_ucode(struct nic *nic, struct cb *cb,
1308 struct sk_buff *skb)
1309{
1310 const struct firmware *fw = (void *)skb;
1311 u8 timer, bundle, min_size;
1312
1313 /* It's not a real skb; we just abused the fact that e100_exec_cb
1314 will pass it through to here... */
1315 cb->skb = NULL;
1316
1317 /* firmware is stored as little endian already */
1318 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1319
1320 /* Read timer, bundle and min_size from end of firmware blob */
1321 timer = fw->data[UCODE_SIZE * 4];
1322 bundle = fw->data[UCODE_SIZE * 4 + 1];
1323 min_size = fw->data[UCODE_SIZE * 4 + 2];
1324
1325 /* Insert user-tunable settings in cb->u.ucode */
1326 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1327 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1328 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1329 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1330 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1331 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1332
1333 cb->command = cpu_to_le16(cb_ucode | cb_el);
1334 return 0;
1335}
1336
1337static inline int e100_load_ucode_wait(struct nic *nic)
1338{
1339 const struct firmware *fw;
1340 int err = 0, counter = 50;
1341 struct cb *cb = nic->cb_to_clean;
1342
1343 fw = e100_request_firmware(nic);
1344 /* If it's NULL, then no ucode is required */
1345 if (IS_ERR_OR_NULL(fw))
1346 return PTR_ERR_OR_ZERO(fw);
1347
1348 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
1349 netif_err(nic, probe, nic->netdev,
1350 "ucode cmd failed with error %d\n", err);
1351
1352 /* must restart cuc */
1353 nic->cuc_cmd = cuc_start;
1354
1355 /* wait for completion */
1356 e100_write_flush(nic);
1357 udelay(10);
1358
1359 /* wait for possibly (ouch) 500ms */
1360 while (!(cb->status & cpu_to_le16(cb_complete))) {
1361 msleep(10);
1362 if (!--counter) break;
1363 }
1364
1365 /* ack any interrupts, something could have been set */
1366 iowrite8(~0, &nic->csr->scb.stat_ack);
1367
1368 /* if the command failed, or is not OK, notify and return */
1369 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1370 netif_err(nic, probe, nic->netdev, "ucode load failed\n");
1371 err = -EPERM;
1372 }
1373
1374 return err;
1375}
1376
1377static int e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1378 struct sk_buff *skb)
1379{
1380 cb->command = cpu_to_le16(cb_iaaddr);
1381 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1382 return 0;
1383}
1384
1385static int e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1386{
1387 cb->command = cpu_to_le16(cb_dump);
1388 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1389 offsetof(struct mem, dump_buf));
1390 return 0;
1391}
1392
1393static int e100_phy_check_without_mii(struct nic *nic)
1394{
1395 u8 phy_type;
1396 int without_mii;
1397
1398 phy_type = (le16_to_cpu(nic->eeprom[eeprom_phy_iface]) >> 8) & 0x0f;
1399
1400 switch (phy_type) {
1401 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1402 case I82503: /* Non-MII PHY; UNTESTED! */
1403 case S80C24: /* Non-MII PHY; tested and working */
1404 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1405 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1406 * doesn't have a programming interface of any sort. The
1407 * media is sensed automatically based on how the link partner
1408 * is configured. This is, in essence, manual configuration.
1409 */
1410 netif_info(nic, probe, nic->netdev,
1411 "found MII-less i82503 or 80c24 or other PHY\n");
1412
1413 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1414 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1415
1416 /* these might be needed for certain MII-less cards...
1417 * nic->flags |= ich;
1418 * nic->flags |= ich_10h_workaround; */
1419
1420 without_mii = 1;
1421 break;
1422 default:
1423 without_mii = 0;
1424 break;
1425 }
1426 return without_mii;
1427}
1428
1429#define NCONFIG_AUTO_SWITCH 0x0080
1430#define MII_NSC_CONG MII_RESV1
1431#define NSC_CONG_ENABLE 0x0100
1432#define NSC_CONG_TXREADY 0x0400
1433static int e100_phy_init(struct nic *nic)
1434{
1435 struct net_device *netdev = nic->netdev;
1436 u32 addr;
1437 u16 bmcr, stat, id_lo, id_hi, cong;
1438
1439 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1440 for (addr = 0; addr < 32; addr++) {
1441 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1442 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1443 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1444 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1445 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1446 break;
1447 }
1448 if (addr == 32) {
1449 /* uhoh, no PHY detected: check whether we seem to be some
1450 * weird, rare variant which is *known* to not have any MII.
1451 * But do this AFTER MII checking only, since this does
1452 * lookup of EEPROM values which may easily be unreliable. */
1453 if (e100_phy_check_without_mii(nic))
1454 return 0; /* simply return and hope for the best */
1455 else {
1456 /* for unknown cases log a fatal error */
1457 netif_err(nic, hw, nic->netdev,
1458 "Failed to locate any known PHY, aborting\n");
1459 return -EAGAIN;
1460 }
1461 } else
1462 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1463 "phy_addr = %d\n", nic->mii.phy_id);
1464
1465 /* Get phy ID */
1466 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1467 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1468 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1469 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1470 "phy ID = 0x%08X\n", nic->phy);
1471
1472 /* Select the phy and isolate the rest */
1473 for (addr = 0; addr < 32; addr++) {
1474 if (addr != nic->mii.phy_id) {
1475 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1476 } else if (nic->phy != phy_82552_v) {
1477 bmcr = mdio_read(netdev, addr, MII_BMCR);
1478 mdio_write(netdev, addr, MII_BMCR,
1479 bmcr & ~BMCR_ISOLATE);
1480 }
1481 }
1482 /*
1483 * Workaround for 82552:
1484 * Clear the ISOLATE bit on selected phy_id last (mirrored on all
1485 * other phy_id's) using bmcr value from addr discovery loop above.
1486 */
1487 if (nic->phy == phy_82552_v)
1488 mdio_write(netdev, nic->mii.phy_id, MII_BMCR,
1489 bmcr & ~BMCR_ISOLATE);
1490
1491 /* Handle National tx phys */
1492#define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1493 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1494 /* Disable congestion control */
1495 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1496 cong |= NSC_CONG_TXREADY;
1497 cong &= ~NSC_CONG_ENABLE;
1498 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1499 }
1500
1501 if (nic->phy == phy_82552_v) {
1502 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1503
1504 /* assign special tweaked mdio_ctrl() function */
1505 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1506
1507 /* Workaround Si not advertising flow-control during autoneg */
1508 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1509 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1510
1511 /* Reset for the above changes to take effect */
1512 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1513 bmcr |= BMCR_RESET;
1514 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1515 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1516 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1517 (le16_to_cpu(nic->eeprom[eeprom_cnfg_mdix]) & eeprom_mdix_enabled))) {
1518 /* enable/disable MDI/MDI-X auto-switching. */
1519 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1520 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1521 }
1522
1523 return 0;
1524}
1525
1526static int e100_hw_init(struct nic *nic)
1527{
1528 int err = 0;
1529
1530 e100_hw_reset(nic);
1531
1532 netif_err(nic, hw, nic->netdev, "e100_hw_init\n");
1533 if ((err = e100_self_test(nic)))
1534 return err;
1535
1536 if ((err = e100_phy_init(nic)))
1537 return err;
1538 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1539 return err;
1540 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1541 return err;
1542 if ((err = e100_load_ucode_wait(nic)))
1543 return err;
1544 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1545 return err;
1546 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1547 return err;
1548 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1549 nic->dma_addr + offsetof(struct mem, stats))))
1550 return err;
1551 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1552 return err;
1553
1554 e100_disable_irq(nic);
1555
1556 return 0;
1557}
1558
1559static int e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1560{
1561 struct net_device *netdev = nic->netdev;
1562 struct netdev_hw_addr *ha;
1563 u16 i, count = min(netdev_mc_count(netdev), E100_MAX_MULTICAST_ADDRS);
1564
1565 cb->command = cpu_to_le16(cb_multi);
1566 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1567 i = 0;
1568 netdev_for_each_mc_addr(ha, netdev) {
1569 if (i == count)
1570 break;
1571 memcpy(&cb->u.multi.addr[i++ * ETH_ALEN], &ha->addr,
1572 ETH_ALEN);
1573 }
1574 return 0;
1575}
1576
1577static void e100_set_multicast_list(struct net_device *netdev)
1578{
1579 struct nic *nic = netdev_priv(netdev);
1580
1581 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1582 "mc_count=%d, flags=0x%04X\n",
1583 netdev_mc_count(netdev), netdev->flags);
1584
1585 if (netdev->flags & IFF_PROMISC)
1586 nic->flags |= promiscuous;
1587 else
1588 nic->flags &= ~promiscuous;
1589
1590 if (netdev->flags & IFF_ALLMULTI ||
1591 netdev_mc_count(netdev) > E100_MAX_MULTICAST_ADDRS)
1592 nic->flags |= multicast_all;
1593 else
1594 nic->flags &= ~multicast_all;
1595
1596 e100_exec_cb(nic, NULL, e100_configure);
1597 e100_exec_cb(nic, NULL, e100_multi);
1598}
1599
1600static void e100_update_stats(struct nic *nic)
1601{
1602 struct net_device *dev = nic->netdev;
1603 struct net_device_stats *ns = &dev->stats;
1604 struct stats *s = &nic->mem->stats;
1605 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1606 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1607 &s->complete;
1608
1609 /* Device's stats reporting may take several microseconds to
1610 * complete, so we're always waiting for results of the
1611 * previous command. */
1612
1613 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1614 *complete = 0;
1615 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1616 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1617 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1618 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1619 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1620 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1621 ns->collisions += nic->tx_collisions;
1622 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1623 le32_to_cpu(s->tx_lost_crs);
1624 nic->rx_short_frame_errors +=
1625 le32_to_cpu(s->rx_short_frame_errors);
1626 ns->rx_length_errors = nic->rx_short_frame_errors +
1627 nic->rx_over_length_errors;
1628 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1629 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1630 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1631 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1632 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1633 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1634 le32_to_cpu(s->rx_alignment_errors) +
1635 le32_to_cpu(s->rx_short_frame_errors) +
1636 le32_to_cpu(s->rx_cdt_errors);
1637 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1638 nic->tx_single_collisions +=
1639 le32_to_cpu(s->tx_single_collisions);
1640 nic->tx_multiple_collisions +=
1641 le32_to_cpu(s->tx_multiple_collisions);
1642 if (nic->mac >= mac_82558_D101_A4) {
1643 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1644 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1645 nic->rx_fc_unsupported +=
1646 le32_to_cpu(s->fc_rcv_unsupported);
1647 if (nic->mac >= mac_82559_D101M) {
1648 nic->tx_tco_frames +=
1649 le16_to_cpu(s->xmt_tco_frames);
1650 nic->rx_tco_frames +=
1651 le16_to_cpu(s->rcv_tco_frames);
1652 }
1653 }
1654 }
1655
1656
1657 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1658 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1659 "exec cuc_dump_reset failed\n");
1660}
1661
1662static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1663{
1664 /* Adjust inter-frame-spacing (IFS) between two transmits if
1665 * we're getting collisions on a half-duplex connection. */
1666
1667 if (duplex == DUPLEX_HALF) {
1668 u32 prev = nic->adaptive_ifs;
1669 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1670
1671 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1672 (nic->tx_frames > min_frames)) {
1673 if (nic->adaptive_ifs < 60)
1674 nic->adaptive_ifs += 5;
1675 } else if (nic->tx_frames < min_frames) {
1676 if (nic->adaptive_ifs >= 5)
1677 nic->adaptive_ifs -= 5;
1678 }
1679 if (nic->adaptive_ifs != prev)
1680 e100_exec_cb(nic, NULL, e100_configure);
1681 }
1682}
1683
1684static void e100_watchdog(struct timer_list *t)
1685{
1686 struct nic *nic = from_timer(nic, t, watchdog);
1687 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1688 u32 speed;
1689
1690 netif_printk(nic, timer, KERN_DEBUG, nic->netdev,
1691 "right now = %ld\n", jiffies);
1692
1693 /* mii library handles link maintenance tasks */
1694
1695 mii_ethtool_gset(&nic->mii, &cmd);
1696 speed = ethtool_cmd_speed(&cmd);
1697
1698 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1699 netdev_info(nic->netdev, "NIC Link is Up %u Mbps %s Duplex\n",
1700 speed == SPEED_100 ? 100 : 10,
1701 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1702 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1703 netdev_info(nic->netdev, "NIC Link is Down\n");
1704 }
1705
1706 mii_check_link(&nic->mii);
1707
1708 /* Software generated interrupt to recover from (rare) Rx
1709 * allocation failure.
1710 * Unfortunately have to use a spinlock to not re-enable interrupts
1711 * accidentally, due to hardware that shares a register between the
1712 * interrupt mask bit and the SW Interrupt generation bit */
1713 spin_lock_irq(&nic->cmd_lock);
1714 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1715 e100_write_flush(nic);
1716 spin_unlock_irq(&nic->cmd_lock);
1717
1718 e100_update_stats(nic);
1719 e100_adjust_adaptive_ifs(nic, speed, cmd.duplex);
1720
1721 if (nic->mac <= mac_82557_D100_C)
1722 /* Issue a multicast command to workaround a 557 lock up */
1723 e100_set_multicast_list(nic->netdev);
1724
1725 if (nic->flags & ich && speed == SPEED_10 && cmd.duplex == DUPLEX_HALF)
1726 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1727 nic->flags |= ich_10h_workaround;
1728 else
1729 nic->flags &= ~ich_10h_workaround;
1730
1731 mod_timer(&nic->watchdog,
1732 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1733}
1734
1735static int e100_xmit_prepare(struct nic *nic, struct cb *cb,
1736 struct sk_buff *skb)
1737{
1738 dma_addr_t dma_addr;
1739 cb->command = nic->tx_command;
1740
1741 dma_addr = dma_map_single(&nic->pdev->dev, skb->data, skb->len,
1742 DMA_TO_DEVICE);
1743 /* If we can't map the skb, have the upper layer try later */
1744 if (dma_mapping_error(&nic->pdev->dev, dma_addr))
1745 return -ENOMEM;
1746
1747 /*
1748 * Use the last 4 bytes of the SKB payload packet as the CRC, used for
1749 * testing, ie sending frames with bad CRC.
1750 */
1751 if (unlikely(skb->no_fcs))
1752 cb->command |= cpu_to_le16(cb_tx_nc);
1753 else
1754 cb->command &= ~cpu_to_le16(cb_tx_nc);
1755
1756 /* interrupt every 16 packets regardless of delay */
1757 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
1758 cb->command |= cpu_to_le16(cb_i);
1759 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1760 cb->u.tcb.tcb_byte_count = 0;
1761 cb->u.tcb.threshold = nic->tx_threshold;
1762 cb->u.tcb.tbd_count = 1;
1763 cb->u.tcb.tbd.buf_addr = cpu_to_le32(dma_addr);
1764 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1765 skb_tx_timestamp(skb);
1766 return 0;
1767}
1768
1769static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1770 struct net_device *netdev)
1771{
1772 struct nic *nic = netdev_priv(netdev);
1773 int err;
1774
1775 if (nic->flags & ich_10h_workaround) {
1776 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1777 Issue a NOP command followed by a 1us delay before
1778 issuing the Tx command. */
1779 if (e100_exec_cmd(nic, cuc_nop, 0))
1780 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1781 "exec cuc_nop failed\n");
1782 udelay(1);
1783 }
1784
1785 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1786
1787 switch (err) {
1788 case -ENOSPC:
1789 /* We queued the skb, but now we're out of space. */
1790 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1791 "No space for CB\n");
1792 netif_stop_queue(netdev);
1793 break;
1794 case -ENOMEM:
1795 /* This is a hard error - log it. */
1796 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1797 "Out of Tx resources, returning skb\n");
1798 netif_stop_queue(netdev);
1799 return NETDEV_TX_BUSY;
1800 }
1801
1802 return NETDEV_TX_OK;
1803}
1804
1805static int e100_tx_clean(struct nic *nic)
1806{
1807 struct net_device *dev = nic->netdev;
1808 struct cb *cb;
1809 int tx_cleaned = 0;
1810
1811 spin_lock(&nic->cb_lock);
1812
1813 /* Clean CBs marked complete */
1814 for (cb = nic->cb_to_clean;
1815 cb->status & cpu_to_le16(cb_complete);
1816 cb = nic->cb_to_clean = cb->next) {
1817 dma_rmb(); /* read skb after status */
1818 netif_printk(nic, tx_done, KERN_DEBUG, nic->netdev,
1819 "cb[%d]->status = 0x%04X\n",
1820 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1821 cb->status);
1822
1823 if (likely(cb->skb != NULL)) {
1824 dev->stats.tx_packets++;
1825 dev->stats.tx_bytes += cb->skb->len;
1826
1827 dma_unmap_single(&nic->pdev->dev,
1828 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1829 le16_to_cpu(cb->u.tcb.tbd.size),
1830 DMA_TO_DEVICE);
1831 dev_kfree_skb_any(cb->skb);
1832 cb->skb = NULL;
1833 tx_cleaned = 1;
1834 }
1835 cb->status = 0;
1836 nic->cbs_avail++;
1837 }
1838
1839 spin_unlock(&nic->cb_lock);
1840
1841 /* Recover from running out of Tx resources in xmit_frame */
1842 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1843 netif_wake_queue(nic->netdev);
1844
1845 return tx_cleaned;
1846}
1847
1848static void e100_clean_cbs(struct nic *nic)
1849{
1850 if (nic->cbs) {
1851 while (nic->cbs_avail != nic->params.cbs.count) {
1852 struct cb *cb = nic->cb_to_clean;
1853 if (cb->skb) {
1854 dma_unmap_single(&nic->pdev->dev,
1855 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1856 le16_to_cpu(cb->u.tcb.tbd.size),
1857 DMA_TO_DEVICE);
1858 dev_kfree_skb(cb->skb);
1859 }
1860 nic->cb_to_clean = nic->cb_to_clean->next;
1861 nic->cbs_avail++;
1862 }
1863 dma_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
1864 nic->cbs = NULL;
1865 nic->cbs_avail = 0;
1866 }
1867 nic->cuc_cmd = cuc_start;
1868 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1869 nic->cbs;
1870}
1871
1872static int e100_alloc_cbs(struct nic *nic)
1873{
1874 struct cb *cb;
1875 unsigned int i, count = nic->params.cbs.count;
1876
1877 nic->cuc_cmd = cuc_start;
1878 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1879 nic->cbs_avail = 0;
1880
1881 nic->cbs = dma_pool_zalloc(nic->cbs_pool, GFP_KERNEL,
1882 &nic->cbs_dma_addr);
1883 if (!nic->cbs)
1884 return -ENOMEM;
1885
1886 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1887 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1888 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1889
1890 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1891 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1892 ((i+1) % count) * sizeof(struct cb));
1893 }
1894
1895 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1896 nic->cbs_avail = count;
1897
1898 return 0;
1899}
1900
1901static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1902{
1903 if (!nic->rxs) return;
1904 if (RU_SUSPENDED != nic->ru_running) return;
1905
1906 /* handle init time starts */
1907 if (!rx) rx = nic->rxs;
1908
1909 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1910 if (rx->skb) {
1911 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1912 nic->ru_running = RU_RUNNING;
1913 }
1914}
1915
1916#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
1917static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1918{
1919 if (!(rx->skb = netdev_alloc_skb_ip_align(nic->netdev, RFD_BUF_LEN)))
1920 return -ENOMEM;
1921
1922 /* Init, and map the RFD. */
1923 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1924 rx->dma_addr = dma_map_single(&nic->pdev->dev, rx->skb->data,
1925 RFD_BUF_LEN, DMA_BIDIRECTIONAL);
1926
1927 if (dma_mapping_error(&nic->pdev->dev, rx->dma_addr)) {
1928 dev_kfree_skb_any(rx->skb);
1929 rx->skb = NULL;
1930 rx->dma_addr = 0;
1931 return -ENOMEM;
1932 }
1933
1934 /* Link the RFD to end of RFA by linking previous RFD to
1935 * this one. We are safe to touch the previous RFD because
1936 * it is protected by the before last buffer's el bit being set */
1937 if (rx->prev->skb) {
1938 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1939 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1940 dma_sync_single_for_device(&nic->pdev->dev,
1941 rx->prev->dma_addr,
1942 sizeof(struct rfd),
1943 DMA_BIDIRECTIONAL);
1944 }
1945
1946 return 0;
1947}
1948
1949static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1950 unsigned int *work_done, unsigned int work_to_do)
1951{
1952 struct net_device *dev = nic->netdev;
1953 struct sk_buff *skb = rx->skb;
1954 struct rfd *rfd = (struct rfd *)skb->data;
1955 u16 rfd_status, actual_size;
1956 u16 fcs_pad = 0;
1957
1958 if (unlikely(work_done && *work_done >= work_to_do))
1959 return -EAGAIN;
1960
1961 /* Need to sync before taking a peek at cb_complete bit */
1962 dma_sync_single_for_cpu(&nic->pdev->dev, rx->dma_addr,
1963 sizeof(struct rfd), DMA_BIDIRECTIONAL);
1964 rfd_status = le16_to_cpu(rfd->status);
1965
1966 netif_printk(nic, rx_status, KERN_DEBUG, nic->netdev,
1967 "status=0x%04X\n", rfd_status);
1968 dma_rmb(); /* read size after status bit */
1969
1970 /* If data isn't ready, nothing to indicate */
1971 if (unlikely(!(rfd_status & cb_complete))) {
1972 /* If the next buffer has the el bit, but we think the receiver
1973 * is still running, check to see if it really stopped while
1974 * we had interrupts off.
1975 * This allows for a fast restart without re-enabling
1976 * interrupts */
1977 if ((le16_to_cpu(rfd->command) & cb_el) &&
1978 (RU_RUNNING == nic->ru_running))
1979
1980 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1981 nic->ru_running = RU_SUSPENDED;
1982 dma_sync_single_for_device(&nic->pdev->dev, rx->dma_addr,
1983 sizeof(struct rfd),
1984 DMA_FROM_DEVICE);
1985 return -ENODATA;
1986 }
1987
1988 /* Get actual data size */
1989 if (unlikely(dev->features & NETIF_F_RXFCS))
1990 fcs_pad = 4;
1991 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1992 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1993 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1994
1995 /* Get data */
1996 dma_unmap_single(&nic->pdev->dev, rx->dma_addr, RFD_BUF_LEN,
1997 DMA_BIDIRECTIONAL);
1998
1999 /* If this buffer has the el bit, but we think the receiver
2000 * is still running, check to see if it really stopped while
2001 * we had interrupts off.
2002 * This allows for a fast restart without re-enabling interrupts.
2003 * This can happen when the RU sees the size change but also sees
2004 * the el bit set. */
2005 if ((le16_to_cpu(rfd->command) & cb_el) &&
2006 (RU_RUNNING == nic->ru_running)) {
2007
2008 if (ioread8(&nic->csr->scb.status) & rus_no_res)
2009 nic->ru_running = RU_SUSPENDED;
2010 }
2011
2012 /* Pull off the RFD and put the actual data (minus eth hdr) */
2013 skb_reserve(skb, sizeof(struct rfd));
2014 skb_put(skb, actual_size);
2015 skb->protocol = eth_type_trans(skb, nic->netdev);
2016
2017 /* If we are receiving all frames, then don't bother
2018 * checking for errors.
2019 */
2020 if (unlikely(dev->features & NETIF_F_RXALL)) {
2021 if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad)
2022 /* Received oversized frame, but keep it. */
2023 nic->rx_over_length_errors++;
2024 goto process_skb;
2025 }
2026
2027 if (unlikely(!(rfd_status & cb_ok))) {
2028 /* Don't indicate if hardware indicates errors */
2029 dev_kfree_skb_any(skb);
2030 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad) {
2031 /* Don't indicate oversized frames */
2032 nic->rx_over_length_errors++;
2033 dev_kfree_skb_any(skb);
2034 } else {
2035process_skb:
2036 dev->stats.rx_packets++;
2037 dev->stats.rx_bytes += (actual_size - fcs_pad);
2038 netif_receive_skb(skb);
2039 if (work_done)
2040 (*work_done)++;
2041 }
2042
2043 rx->skb = NULL;
2044
2045 return 0;
2046}
2047
2048static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
2049 unsigned int work_to_do)
2050{
2051 struct rx *rx;
2052 int restart_required = 0, err = 0;
2053 struct rx *old_before_last_rx, *new_before_last_rx;
2054 struct rfd *old_before_last_rfd, *new_before_last_rfd;
2055
2056 /* Indicate newly arrived packets */
2057 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
2058 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
2059 /* Hit quota or no more to clean */
2060 if (-EAGAIN == err || -ENODATA == err)
2061 break;
2062 }
2063
2064
2065 /* On EAGAIN, hit quota so have more work to do, restart once
2066 * cleanup is complete.
2067 * Else, are we already rnr? then pay attention!!! this ensures that
2068 * the state machine progression never allows a start with a
2069 * partially cleaned list, avoiding a race between hardware
2070 * and rx_to_clean when in NAPI mode */
2071 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
2072 restart_required = 1;
2073
2074 old_before_last_rx = nic->rx_to_use->prev->prev;
2075 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
2076
2077 /* Alloc new skbs to refill list */
2078 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
2079 if (unlikely(e100_rx_alloc_skb(nic, rx)))
2080 break; /* Better luck next time (see watchdog) */
2081 }
2082
2083 new_before_last_rx = nic->rx_to_use->prev->prev;
2084 if (new_before_last_rx != old_before_last_rx) {
2085 /* Set the el-bit on the buffer that is before the last buffer.
2086 * This lets us update the next pointer on the last buffer
2087 * without worrying about hardware touching it.
2088 * We set the size to 0 to prevent hardware from touching this
2089 * buffer.
2090 * When the hardware hits the before last buffer with el-bit
2091 * and size of 0, it will RNR interrupt, the RUS will go into
2092 * the No Resources state. It will not complete nor write to
2093 * this buffer. */
2094 new_before_last_rfd =
2095 (struct rfd *)new_before_last_rx->skb->data;
2096 new_before_last_rfd->size = 0;
2097 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2098 dma_sync_single_for_device(&nic->pdev->dev,
2099 new_before_last_rx->dma_addr,
2100 sizeof(struct rfd),
2101 DMA_BIDIRECTIONAL);
2102
2103 /* Now that we have a new stopping point, we can clear the old
2104 * stopping point. We must sync twice to get the proper
2105 * ordering on the hardware side of things. */
2106 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2107 dma_sync_single_for_device(&nic->pdev->dev,
2108 old_before_last_rx->dma_addr,
2109 sizeof(struct rfd),
2110 DMA_BIDIRECTIONAL);
2111 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN
2112 + ETH_FCS_LEN);
2113 dma_sync_single_for_device(&nic->pdev->dev,
2114 old_before_last_rx->dma_addr,
2115 sizeof(struct rfd),
2116 DMA_BIDIRECTIONAL);
2117 }
2118
2119 if (restart_required) {
2120 // ack the rnr?
2121 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
2122 e100_start_receiver(nic, nic->rx_to_clean);
2123 if (work_done)
2124 (*work_done)++;
2125 }
2126}
2127
2128static void e100_rx_clean_list(struct nic *nic)
2129{
2130 struct rx *rx;
2131 unsigned int i, count = nic->params.rfds.count;
2132
2133 nic->ru_running = RU_UNINITIALIZED;
2134
2135 if (nic->rxs) {
2136 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2137 if (rx->skb) {
2138 dma_unmap_single(&nic->pdev->dev,
2139 rx->dma_addr, RFD_BUF_LEN,
2140 DMA_BIDIRECTIONAL);
2141 dev_kfree_skb(rx->skb);
2142 }
2143 }
2144 kfree(nic->rxs);
2145 nic->rxs = NULL;
2146 }
2147
2148 nic->rx_to_use = nic->rx_to_clean = NULL;
2149}
2150
2151static int e100_rx_alloc_list(struct nic *nic)
2152{
2153 struct rx *rx;
2154 unsigned int i, count = nic->params.rfds.count;
2155 struct rfd *before_last;
2156
2157 nic->rx_to_use = nic->rx_to_clean = NULL;
2158 nic->ru_running = RU_UNINITIALIZED;
2159
2160 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_KERNEL)))
2161 return -ENOMEM;
2162
2163 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2164 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2165 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
2166 if (e100_rx_alloc_skb(nic, rx)) {
2167 e100_rx_clean_list(nic);
2168 return -ENOMEM;
2169 }
2170 }
2171 /* Set the el-bit on the buffer that is before the last buffer.
2172 * This lets us update the next pointer on the last buffer without
2173 * worrying about hardware touching it.
2174 * We set the size to 0 to prevent hardware from touching this buffer.
2175 * When the hardware hits the before last buffer with el-bit and size
2176 * of 0, it will RNR interrupt, the RU will go into the No Resources
2177 * state. It will not complete nor write to this buffer. */
2178 rx = nic->rxs->prev->prev;
2179 before_last = (struct rfd *)rx->skb->data;
2180 before_last->command |= cpu_to_le16(cb_el);
2181 before_last->size = 0;
2182 dma_sync_single_for_device(&nic->pdev->dev, rx->dma_addr,
2183 sizeof(struct rfd), DMA_BIDIRECTIONAL);
2184
2185 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
2186 nic->ru_running = RU_SUSPENDED;
2187
2188 return 0;
2189}
2190
2191static irqreturn_t e100_intr(int irq, void *dev_id)
2192{
2193 struct net_device *netdev = dev_id;
2194 struct nic *nic = netdev_priv(netdev);
2195 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
2196
2197 netif_printk(nic, intr, KERN_DEBUG, nic->netdev,
2198 "stat_ack = 0x%02X\n", stat_ack);
2199
2200 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
2201 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2202 return IRQ_NONE;
2203
2204 /* Ack interrupt(s) */
2205 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
2206
2207 /* We hit Receive No Resource (RNR); restart RU after cleaning */
2208 if (stat_ack & stat_ack_rnr)
2209 nic->ru_running = RU_SUSPENDED;
2210
2211 if (likely(napi_schedule_prep(&nic->napi))) {
2212 e100_disable_irq(nic);
2213 __napi_schedule(&nic->napi);
2214 }
2215
2216 return IRQ_HANDLED;
2217}
2218
2219static int e100_poll(struct napi_struct *napi, int budget)
2220{
2221 struct nic *nic = container_of(napi, struct nic, napi);
2222 unsigned int work_done = 0;
2223
2224 e100_rx_clean(nic, &work_done, budget);
2225 e100_tx_clean(nic);
2226
2227 /* If budget fully consumed, continue polling */
2228 if (work_done == budget)
2229 return budget;
2230
2231 /* only re-enable interrupt if stack agrees polling is really done */
2232 if (likely(napi_complete_done(napi, work_done)))
2233 e100_enable_irq(nic);
2234
2235 return work_done;
2236}
2237
2238#ifdef CONFIG_NET_POLL_CONTROLLER
2239static void e100_netpoll(struct net_device *netdev)
2240{
2241 struct nic *nic = netdev_priv(netdev);
2242
2243 e100_disable_irq(nic);
2244 e100_intr(nic->pdev->irq, netdev);
2245 e100_tx_clean(nic);
2246 e100_enable_irq(nic);
2247}
2248#endif
2249
2250static int e100_set_mac_address(struct net_device *netdev, void *p)
2251{
2252 struct nic *nic = netdev_priv(netdev);
2253 struct sockaddr *addr = p;
2254
2255 if (!is_valid_ether_addr(addr->sa_data))
2256 return -EADDRNOTAVAIL;
2257
2258 eth_hw_addr_set(netdev, addr->sa_data);
2259 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2260
2261 return 0;
2262}
2263
2264static int e100_asf(struct nic *nic)
2265{
2266 /* ASF can be enabled from eeprom */
2267 return (nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2268 (le16_to_cpu(nic->eeprom[eeprom_config_asf]) & eeprom_asf) &&
2269 !(le16_to_cpu(nic->eeprom[eeprom_config_asf]) & eeprom_gcl) &&
2270 ((le16_to_cpu(nic->eeprom[eeprom_smbus_addr]) & 0xFF) != 0xFE);
2271}
2272
2273static int e100_up(struct nic *nic)
2274{
2275 int err;
2276
2277 if ((err = e100_rx_alloc_list(nic)))
2278 return err;
2279 if ((err = e100_alloc_cbs(nic)))
2280 goto err_rx_clean_list;
2281 if ((err = e100_hw_init(nic)))
2282 goto err_clean_cbs;
2283 e100_set_multicast_list(nic->netdev);
2284 e100_start_receiver(nic, NULL);
2285 mod_timer(&nic->watchdog, jiffies);
2286 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2287 nic->netdev->name, nic->netdev)))
2288 goto err_no_irq;
2289 netif_wake_queue(nic->netdev);
2290 napi_enable(&nic->napi);
2291 /* enable ints _after_ enabling poll, preventing a race between
2292 * disable ints+schedule */
2293 e100_enable_irq(nic);
2294 return 0;
2295
2296err_no_irq:
2297 del_timer_sync(&nic->watchdog);
2298err_clean_cbs:
2299 e100_clean_cbs(nic);
2300err_rx_clean_list:
2301 e100_rx_clean_list(nic);
2302 return err;
2303}
2304
2305static void e100_down(struct nic *nic)
2306{
2307 /* wait here for poll to complete */
2308 napi_disable(&nic->napi);
2309 netif_stop_queue(nic->netdev);
2310 e100_hw_reset(nic);
2311 free_irq(nic->pdev->irq, nic->netdev);
2312 del_timer_sync(&nic->watchdog);
2313 netif_carrier_off(nic->netdev);
2314 e100_clean_cbs(nic);
2315 e100_rx_clean_list(nic);
2316}
2317
2318static void e100_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2319{
2320 struct nic *nic = netdev_priv(netdev);
2321
2322 /* Reset outside of interrupt context, to avoid request_irq
2323 * in interrupt context */
2324 schedule_work(&nic->tx_timeout_task);
2325}
2326
2327static void e100_tx_timeout_task(struct work_struct *work)
2328{
2329 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2330 struct net_device *netdev = nic->netdev;
2331
2332 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
2333 "scb.status=0x%02X\n", ioread8(&nic->csr->scb.status));
2334
2335 rtnl_lock();
2336 if (netif_running(netdev)) {
2337 e100_down(netdev_priv(netdev));
2338 e100_up(netdev_priv(netdev));
2339 }
2340 rtnl_unlock();
2341}
2342
2343static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2344{
2345 int err;
2346 struct sk_buff *skb;
2347
2348 /* Use driver resources to perform internal MAC or PHY
2349 * loopback test. A single packet is prepared and transmitted
2350 * in loopback mode, and the test passes if the received
2351 * packet compares byte-for-byte to the transmitted packet. */
2352
2353 if ((err = e100_rx_alloc_list(nic)))
2354 return err;
2355 if ((err = e100_alloc_cbs(nic)))
2356 goto err_clean_rx;
2357
2358 /* ICH PHY loopback is broken so do MAC loopback instead */
2359 if (nic->flags & ich && loopback_mode == lb_phy)
2360 loopback_mode = lb_mac;
2361
2362 nic->loopback = loopback_mode;
2363 if ((err = e100_hw_init(nic)))
2364 goto err_loopback_none;
2365
2366 if (loopback_mode == lb_phy)
2367 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2368 BMCR_LOOPBACK);
2369
2370 e100_start_receiver(nic, NULL);
2371
2372 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2373 err = -ENOMEM;
2374 goto err_loopback_none;
2375 }
2376 skb_put(skb, ETH_DATA_LEN);
2377 memset(skb->data, 0xFF, ETH_DATA_LEN);
2378 e100_xmit_frame(skb, nic->netdev);
2379
2380 msleep(10);
2381
2382 dma_sync_single_for_cpu(&nic->pdev->dev, nic->rx_to_clean->dma_addr,
2383 RFD_BUF_LEN, DMA_BIDIRECTIONAL);
2384
2385 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2386 skb->data, ETH_DATA_LEN))
2387 err = -EAGAIN;
2388
2389err_loopback_none:
2390 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2391 nic->loopback = lb_none;
2392 e100_clean_cbs(nic);
2393 e100_hw_reset(nic);
2394err_clean_rx:
2395 e100_rx_clean_list(nic);
2396 return err;
2397}
2398
2399#define MII_LED_CONTROL 0x1B
2400#define E100_82552_LED_OVERRIDE 0x19
2401#define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2402#define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
2403
2404static int e100_get_link_ksettings(struct net_device *netdev,
2405 struct ethtool_link_ksettings *cmd)
2406{
2407 struct nic *nic = netdev_priv(netdev);
2408
2409 mii_ethtool_get_link_ksettings(&nic->mii, cmd);
2410
2411 return 0;
2412}
2413
2414static int e100_set_link_ksettings(struct net_device *netdev,
2415 const struct ethtool_link_ksettings *cmd)
2416{
2417 struct nic *nic = netdev_priv(netdev);
2418 int err;
2419
2420 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2421 err = mii_ethtool_set_link_ksettings(&nic->mii, cmd);
2422 e100_exec_cb(nic, NULL, e100_configure);
2423
2424 return err;
2425}
2426
2427static void e100_get_drvinfo(struct net_device *netdev,
2428 struct ethtool_drvinfo *info)
2429{
2430 struct nic *nic = netdev_priv(netdev);
2431 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
2432 strscpy(info->bus_info, pci_name(nic->pdev),
2433 sizeof(info->bus_info));
2434}
2435
2436#define E100_PHY_REGS 0x1D
2437static int e100_get_regs_len(struct net_device *netdev)
2438{
2439 struct nic *nic = netdev_priv(netdev);
2440
2441 /* We know the number of registers, and the size of the dump buffer.
2442 * Calculate the total size in bytes.
2443 */
2444 return (1 + E100_PHY_REGS) * sizeof(u32) + sizeof(nic->mem->dump_buf);
2445}
2446
2447static void e100_get_regs(struct net_device *netdev,
2448 struct ethtool_regs *regs, void *p)
2449{
2450 struct nic *nic = netdev_priv(netdev);
2451 u32 *buff = p;
2452 int i;
2453
2454 regs->version = (1 << 24) | nic->pdev->revision;
2455 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2456 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2457 ioread16(&nic->csr->scb.status);
2458 for (i = 0; i < E100_PHY_REGS; i++)
2459 /* Note that we read the registers in reverse order. This
2460 * ordering is the ABI apparently used by ethtool and other
2461 * applications.
2462 */
2463 buff[1 + i] = mdio_read(netdev, nic->mii.phy_id,
2464 E100_PHY_REGS - 1 - i);
2465 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2466 e100_exec_cb(nic, NULL, e100_dump);
2467 msleep(10);
2468 memcpy(&buff[1 + E100_PHY_REGS], nic->mem->dump_buf,
2469 sizeof(nic->mem->dump_buf));
2470}
2471
2472static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2473{
2474 struct nic *nic = netdev_priv(netdev);
2475 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2476 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2477}
2478
2479static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2480{
2481 struct nic *nic = netdev_priv(netdev);
2482
2483 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2484 !device_can_wakeup(&nic->pdev->dev))
2485 return -EOPNOTSUPP;
2486
2487 if (wol->wolopts)
2488 nic->flags |= wol_magic;
2489 else
2490 nic->flags &= ~wol_magic;
2491
2492 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2493
2494 e100_exec_cb(nic, NULL, e100_configure);
2495
2496 return 0;
2497}
2498
2499static u32 e100_get_msglevel(struct net_device *netdev)
2500{
2501 struct nic *nic = netdev_priv(netdev);
2502 return nic->msg_enable;
2503}
2504
2505static void e100_set_msglevel(struct net_device *netdev, u32 value)
2506{
2507 struct nic *nic = netdev_priv(netdev);
2508 nic->msg_enable = value;
2509}
2510
2511static int e100_nway_reset(struct net_device *netdev)
2512{
2513 struct nic *nic = netdev_priv(netdev);
2514 return mii_nway_restart(&nic->mii);
2515}
2516
2517static u32 e100_get_link(struct net_device *netdev)
2518{
2519 struct nic *nic = netdev_priv(netdev);
2520 return mii_link_ok(&nic->mii);
2521}
2522
2523static int e100_get_eeprom_len(struct net_device *netdev)
2524{
2525 struct nic *nic = netdev_priv(netdev);
2526 return nic->eeprom_wc << 1;
2527}
2528
2529#define E100_EEPROM_MAGIC 0x1234
2530static int e100_get_eeprom(struct net_device *netdev,
2531 struct ethtool_eeprom *eeprom, u8 *bytes)
2532{
2533 struct nic *nic = netdev_priv(netdev);
2534
2535 eeprom->magic = E100_EEPROM_MAGIC;
2536 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2537
2538 return 0;
2539}
2540
2541static int e100_set_eeprom(struct net_device *netdev,
2542 struct ethtool_eeprom *eeprom, u8 *bytes)
2543{
2544 struct nic *nic = netdev_priv(netdev);
2545
2546 if (eeprom->magic != E100_EEPROM_MAGIC)
2547 return -EINVAL;
2548
2549 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2550
2551 return e100_eeprom_save(nic, eeprom->offset >> 1,
2552 (eeprom->len >> 1) + 1);
2553}
2554
2555static void e100_get_ringparam(struct net_device *netdev,
2556 struct ethtool_ringparam *ring,
2557 struct kernel_ethtool_ringparam *kernel_ring,
2558 struct netlink_ext_ack *extack)
2559{
2560 struct nic *nic = netdev_priv(netdev);
2561 struct param_range *rfds = &nic->params.rfds;
2562 struct param_range *cbs = &nic->params.cbs;
2563
2564 ring->rx_max_pending = rfds->max;
2565 ring->tx_max_pending = cbs->max;
2566 ring->rx_pending = rfds->count;
2567 ring->tx_pending = cbs->count;
2568}
2569
2570static int e100_set_ringparam(struct net_device *netdev,
2571 struct ethtool_ringparam *ring,
2572 struct kernel_ethtool_ringparam *kernel_ring,
2573 struct netlink_ext_ack *extack)
2574{
2575 struct nic *nic = netdev_priv(netdev);
2576 struct param_range *rfds = &nic->params.rfds;
2577 struct param_range *cbs = &nic->params.cbs;
2578
2579 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2580 return -EINVAL;
2581
2582 if (netif_running(netdev))
2583 e100_down(nic);
2584 rfds->count = max(ring->rx_pending, rfds->min);
2585 rfds->count = min(rfds->count, rfds->max);
2586 cbs->count = max(ring->tx_pending, cbs->min);
2587 cbs->count = min(cbs->count, cbs->max);
2588 netif_info(nic, drv, nic->netdev, "Ring Param settings: rx: %d, tx %d\n",
2589 rfds->count, cbs->count);
2590 if (netif_running(netdev))
2591 e100_up(nic);
2592
2593 return 0;
2594}
2595
2596static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2597 "Link test (on/offline)",
2598 "Eeprom test (on/offline)",
2599 "Self test (offline)",
2600 "Mac loopback (offline)",
2601 "Phy loopback (offline)",
2602};
2603#define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2604
2605static void e100_diag_test(struct net_device *netdev,
2606 struct ethtool_test *test, u64 *data)
2607{
2608 struct ethtool_cmd cmd;
2609 struct nic *nic = netdev_priv(netdev);
2610 int i;
2611
2612 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2613 data[0] = !mii_link_ok(&nic->mii);
2614 data[1] = e100_eeprom_load(nic);
2615 if (test->flags & ETH_TEST_FL_OFFLINE) {
2616
2617 /* save speed, duplex & autoneg settings */
2618 mii_ethtool_gset(&nic->mii, &cmd);
2619
2620 if (netif_running(netdev))
2621 e100_down(nic);
2622 data[2] = e100_self_test(nic);
2623 data[3] = e100_loopback_test(nic, lb_mac);
2624 data[4] = e100_loopback_test(nic, lb_phy);
2625
2626 /* restore speed, duplex & autoneg settings */
2627 mii_ethtool_sset(&nic->mii, &cmd);
2628
2629 if (netif_running(netdev))
2630 e100_up(nic);
2631 }
2632 for (i = 0; i < E100_TEST_LEN; i++)
2633 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2634
2635 msleep_interruptible(4 * 1000);
2636}
2637
2638static int e100_set_phys_id(struct net_device *netdev,
2639 enum ethtool_phys_id_state state)
2640{
2641 struct nic *nic = netdev_priv(netdev);
2642 enum led_state {
2643 led_on = 0x01,
2644 led_off = 0x04,
2645 led_on_559 = 0x05,
2646 led_on_557 = 0x07,
2647 };
2648 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2649 MII_LED_CONTROL;
2650 u16 leds = 0;
2651
2652 switch (state) {
2653 case ETHTOOL_ID_ACTIVE:
2654 return 2;
2655
2656 case ETHTOOL_ID_ON:
2657 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_ON :
2658 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
2659 break;
2660
2661 case ETHTOOL_ID_OFF:
2662 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_OFF : led_off;
2663 break;
2664
2665 case ETHTOOL_ID_INACTIVE:
2666 break;
2667 }
2668
2669 mdio_write(netdev, nic->mii.phy_id, led_reg, leds);
2670 return 0;
2671}
2672
2673static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2674 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2675 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2676 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2677 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2678 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2679 "tx_heartbeat_errors", "tx_window_errors",
2680 /* device-specific stats */
2681 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2682 "tx_flow_control_pause", "rx_flow_control_pause",
2683 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2684 "rx_short_frame_errors", "rx_over_length_errors",
2685};
2686#define E100_NET_STATS_LEN 21
2687#define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2688
2689static int e100_get_sset_count(struct net_device *netdev, int sset)
2690{
2691 switch (sset) {
2692 case ETH_SS_TEST:
2693 return E100_TEST_LEN;
2694 case ETH_SS_STATS:
2695 return E100_STATS_LEN;
2696 default:
2697 return -EOPNOTSUPP;
2698 }
2699}
2700
2701static void e100_get_ethtool_stats(struct net_device *netdev,
2702 struct ethtool_stats *stats, u64 *data)
2703{
2704 struct nic *nic = netdev_priv(netdev);
2705 int i;
2706
2707 for (i = 0; i < E100_NET_STATS_LEN; i++)
2708 data[i] = ((unsigned long *)&netdev->stats)[i];
2709
2710 data[i++] = nic->tx_deferred;
2711 data[i++] = nic->tx_single_collisions;
2712 data[i++] = nic->tx_multiple_collisions;
2713 data[i++] = nic->tx_fc_pause;
2714 data[i++] = nic->rx_fc_pause;
2715 data[i++] = nic->rx_fc_unsupported;
2716 data[i++] = nic->tx_tco_frames;
2717 data[i++] = nic->rx_tco_frames;
2718 data[i++] = nic->rx_short_frame_errors;
2719 data[i++] = nic->rx_over_length_errors;
2720}
2721
2722static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2723{
2724 switch (stringset) {
2725 case ETH_SS_TEST:
2726 memcpy(data, e100_gstrings_test, sizeof(e100_gstrings_test));
2727 break;
2728 case ETH_SS_STATS:
2729 memcpy(data, e100_gstrings_stats, sizeof(e100_gstrings_stats));
2730 break;
2731 }
2732}
2733
2734static const struct ethtool_ops e100_ethtool_ops = {
2735 .get_drvinfo = e100_get_drvinfo,
2736 .get_regs_len = e100_get_regs_len,
2737 .get_regs = e100_get_regs,
2738 .get_wol = e100_get_wol,
2739 .set_wol = e100_set_wol,
2740 .get_msglevel = e100_get_msglevel,
2741 .set_msglevel = e100_set_msglevel,
2742 .nway_reset = e100_nway_reset,
2743 .get_link = e100_get_link,
2744 .get_eeprom_len = e100_get_eeprom_len,
2745 .get_eeprom = e100_get_eeprom,
2746 .set_eeprom = e100_set_eeprom,
2747 .get_ringparam = e100_get_ringparam,
2748 .set_ringparam = e100_set_ringparam,
2749 .self_test = e100_diag_test,
2750 .get_strings = e100_get_strings,
2751 .set_phys_id = e100_set_phys_id,
2752 .get_ethtool_stats = e100_get_ethtool_stats,
2753 .get_sset_count = e100_get_sset_count,
2754 .get_ts_info = ethtool_op_get_ts_info,
2755 .get_link_ksettings = e100_get_link_ksettings,
2756 .set_link_ksettings = e100_set_link_ksettings,
2757};
2758
2759static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2760{
2761 struct nic *nic = netdev_priv(netdev);
2762
2763 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2764}
2765
2766static int e100_alloc(struct nic *nic)
2767{
2768 nic->mem = dma_alloc_coherent(&nic->pdev->dev, sizeof(struct mem),
2769 &nic->dma_addr, GFP_KERNEL);
2770 return nic->mem ? 0 : -ENOMEM;
2771}
2772
2773static void e100_free(struct nic *nic)
2774{
2775 if (nic->mem) {
2776 dma_free_coherent(&nic->pdev->dev, sizeof(struct mem),
2777 nic->mem, nic->dma_addr);
2778 nic->mem = NULL;
2779 }
2780}
2781
2782static int e100_open(struct net_device *netdev)
2783{
2784 struct nic *nic = netdev_priv(netdev);
2785 int err = 0;
2786
2787 netif_carrier_off(netdev);
2788 if ((err = e100_up(nic)))
2789 netif_err(nic, ifup, nic->netdev, "Cannot open interface, aborting\n");
2790 return err;
2791}
2792
2793static int e100_close(struct net_device *netdev)
2794{
2795 e100_down(netdev_priv(netdev));
2796 return 0;
2797}
2798
2799static int e100_set_features(struct net_device *netdev,
2800 netdev_features_t features)
2801{
2802 struct nic *nic = netdev_priv(netdev);
2803 netdev_features_t changed = features ^ netdev->features;
2804
2805 if (!(changed & (NETIF_F_RXFCS | NETIF_F_RXALL)))
2806 return 0;
2807
2808 netdev->features = features;
2809 e100_exec_cb(nic, NULL, e100_configure);
2810 return 1;
2811}
2812
2813static const struct net_device_ops e100_netdev_ops = {
2814 .ndo_open = e100_open,
2815 .ndo_stop = e100_close,
2816 .ndo_start_xmit = e100_xmit_frame,
2817 .ndo_validate_addr = eth_validate_addr,
2818 .ndo_set_rx_mode = e100_set_multicast_list,
2819 .ndo_set_mac_address = e100_set_mac_address,
2820 .ndo_eth_ioctl = e100_do_ioctl,
2821 .ndo_tx_timeout = e100_tx_timeout,
2822#ifdef CONFIG_NET_POLL_CONTROLLER
2823 .ndo_poll_controller = e100_netpoll,
2824#endif
2825 .ndo_set_features = e100_set_features,
2826};
2827
2828static int e100_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2829{
2830 struct net_device *netdev;
2831 struct nic *nic;
2832 int err;
2833
2834 if (!(netdev = alloc_etherdev(sizeof(struct nic))))
2835 return -ENOMEM;
2836
2837 netdev->hw_features |= NETIF_F_RXFCS;
2838 netdev->priv_flags |= IFF_SUPP_NOFCS;
2839 netdev->hw_features |= NETIF_F_RXALL;
2840
2841 netdev->netdev_ops = &e100_netdev_ops;
2842 netdev->ethtool_ops = &e100_ethtool_ops;
2843 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2844 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
2845
2846 nic = netdev_priv(netdev);
2847 netif_napi_add_weight(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2848 nic->netdev = netdev;
2849 nic->pdev = pdev;
2850 nic->msg_enable = (1 << debug) - 1;
2851 nic->mdio_ctrl = mdio_ctrl_hw;
2852 pci_set_drvdata(pdev, netdev);
2853
2854 if ((err = pci_enable_device(pdev))) {
2855 netif_err(nic, probe, nic->netdev, "Cannot enable PCI device, aborting\n");
2856 goto err_out_free_dev;
2857 }
2858
2859 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2860 netif_err(nic, probe, nic->netdev, "Cannot find proper PCI device base address, aborting\n");
2861 err = -ENODEV;
2862 goto err_out_disable_pdev;
2863 }
2864
2865 if ((err = pci_request_regions(pdev, DRV_NAME))) {
2866 netif_err(nic, probe, nic->netdev, "Cannot obtain PCI resources, aborting\n");
2867 goto err_out_disable_pdev;
2868 }
2869
2870 if ((err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))) {
2871 netif_err(nic, probe, nic->netdev, "No usable DMA configuration, aborting\n");
2872 goto err_out_free_res;
2873 }
2874
2875 SET_NETDEV_DEV(netdev, &pdev->dev);
2876
2877 if (use_io)
2878 netif_info(nic, probe, nic->netdev, "using i/o access mode\n");
2879
2880 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2881 if (!nic->csr) {
2882 netif_err(nic, probe, nic->netdev, "Cannot map device registers, aborting\n");
2883 err = -ENOMEM;
2884 goto err_out_free_res;
2885 }
2886
2887 if (ent->driver_data)
2888 nic->flags |= ich;
2889 else
2890 nic->flags &= ~ich;
2891
2892 e100_get_defaults(nic);
2893
2894 /* D100 MAC doesn't allow rx of vlan packets with normal MTU */
2895 if (nic->mac < mac_82558_D101_A4)
2896 netdev->features |= NETIF_F_VLAN_CHALLENGED;
2897
2898 /* locks must be initialized before calling hw_reset */
2899 spin_lock_init(&nic->cb_lock);
2900 spin_lock_init(&nic->cmd_lock);
2901 spin_lock_init(&nic->mdio_lock);
2902
2903 /* Reset the device before pci_set_master() in case device is in some
2904 * funky state and has an interrupt pending - hint: we don't have the
2905 * interrupt handler registered yet. */
2906 e100_hw_reset(nic);
2907
2908 pci_set_master(pdev);
2909
2910 timer_setup(&nic->watchdog, e100_watchdog, 0);
2911
2912 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2913
2914 if ((err = e100_alloc(nic))) {
2915 netif_err(nic, probe, nic->netdev, "Cannot alloc driver memory, aborting\n");
2916 goto err_out_iounmap;
2917 }
2918
2919 if ((err = e100_eeprom_load(nic)))
2920 goto err_out_free;
2921
2922 e100_phy_init(nic);
2923
2924 eth_hw_addr_set(netdev, (u8 *)nic->eeprom);
2925 if (!is_valid_ether_addr(netdev->dev_addr)) {
2926 if (!eeprom_bad_csum_allow) {
2927 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, aborting\n");
2928 err = -EAGAIN;
2929 goto err_out_free;
2930 } else {
2931 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, you MUST configure one.\n");
2932 }
2933 }
2934
2935 /* Wol magic packet can be enabled from eeprom */
2936 if ((nic->mac >= mac_82558_D101_A4) &&
2937 (le16_to_cpu(nic->eeprom[eeprom_id]) & eeprom_id_wol)) {
2938 nic->flags |= wol_magic;
2939 device_set_wakeup_enable(&pdev->dev, true);
2940 }
2941
2942 /* ack any pending wake events, disable PME */
2943 pci_pme_active(pdev, false);
2944
2945 strcpy(netdev->name, "eth%d");
2946 if ((err = register_netdev(netdev))) {
2947 netif_err(nic, probe, nic->netdev, "Cannot register net device, aborting\n");
2948 goto err_out_free;
2949 }
2950 nic->cbs_pool = dma_pool_create(netdev->name,
2951 &nic->pdev->dev,
2952 nic->params.cbs.max * sizeof(struct cb),
2953 sizeof(u32),
2954 0);
2955 if (!nic->cbs_pool) {
2956 netif_err(nic, probe, nic->netdev, "Cannot create DMA pool, aborting\n");
2957 err = -ENOMEM;
2958 goto err_out_pool;
2959 }
2960 netif_info(nic, probe, nic->netdev,
2961 "addr 0x%llx, irq %d, MAC addr %pM\n",
2962 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2963 pdev->irq, netdev->dev_addr);
2964
2965 return 0;
2966
2967err_out_pool:
2968 unregister_netdev(netdev);
2969err_out_free:
2970 e100_free(nic);
2971err_out_iounmap:
2972 pci_iounmap(pdev, nic->csr);
2973err_out_free_res:
2974 pci_release_regions(pdev);
2975err_out_disable_pdev:
2976 pci_disable_device(pdev);
2977err_out_free_dev:
2978 free_netdev(netdev);
2979 return err;
2980}
2981
2982static void e100_remove(struct pci_dev *pdev)
2983{
2984 struct net_device *netdev = pci_get_drvdata(pdev);
2985
2986 if (netdev) {
2987 struct nic *nic = netdev_priv(netdev);
2988 unregister_netdev(netdev);
2989 e100_free(nic);
2990 pci_iounmap(pdev, nic->csr);
2991 dma_pool_destroy(nic->cbs_pool);
2992 free_netdev(netdev);
2993 pci_release_regions(pdev);
2994 pci_disable_device(pdev);
2995 }
2996}
2997
2998#define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2999#define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
3000#define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
3001static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
3002{
3003 struct net_device *netdev = pci_get_drvdata(pdev);
3004 struct nic *nic = netdev_priv(netdev);
3005
3006 netif_device_detach(netdev);
3007
3008 if (netif_running(netdev))
3009 e100_down(nic);
3010
3011 if ((nic->flags & wol_magic) | e100_asf(nic)) {
3012 /* enable reverse auto-negotiation */
3013 if (nic->phy == phy_82552_v) {
3014 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
3015 E100_82552_SMARTSPEED);
3016
3017 mdio_write(netdev, nic->mii.phy_id,
3018 E100_82552_SMARTSPEED, smartspeed |
3019 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
3020 }
3021 *enable_wake = true;
3022 } else {
3023 *enable_wake = false;
3024 }
3025
3026 pci_disable_device(pdev);
3027}
3028
3029static int __e100_power_off(struct pci_dev *pdev, bool wake)
3030{
3031 if (wake)
3032 return pci_prepare_to_sleep(pdev);
3033
3034 pci_wake_from_d3(pdev, false);
3035 pci_set_power_state(pdev, PCI_D3hot);
3036
3037 return 0;
3038}
3039
3040static int __maybe_unused e100_suspend(struct device *dev_d)
3041{
3042 bool wake;
3043
3044 __e100_shutdown(to_pci_dev(dev_d), &wake);
3045
3046 return 0;
3047}
3048
3049static int __maybe_unused e100_resume(struct device *dev_d)
3050{
3051 struct net_device *netdev = dev_get_drvdata(dev_d);
3052 struct nic *nic = netdev_priv(netdev);
3053 int err;
3054
3055 err = pci_enable_device(to_pci_dev(dev_d));
3056 if (err) {
3057 netdev_err(netdev, "Resume cannot enable PCI device, aborting\n");
3058 return err;
3059 }
3060 pci_set_master(to_pci_dev(dev_d));
3061
3062 /* disable reverse auto-negotiation */
3063 if (nic->phy == phy_82552_v) {
3064 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
3065 E100_82552_SMARTSPEED);
3066
3067 mdio_write(netdev, nic->mii.phy_id,
3068 E100_82552_SMARTSPEED,
3069 smartspeed & ~(E100_82552_REV_ANEG));
3070 }
3071
3072 if (netif_running(netdev))
3073 e100_up(nic);
3074
3075 netif_device_attach(netdev);
3076
3077 return 0;
3078}
3079
3080static void e100_shutdown(struct pci_dev *pdev)
3081{
3082 bool wake;
3083 __e100_shutdown(pdev, &wake);
3084 if (system_state == SYSTEM_POWER_OFF)
3085 __e100_power_off(pdev, wake);
3086}
3087
3088/* ------------------ PCI Error Recovery infrastructure -------------- */
3089/**
3090 * e100_io_error_detected - called when PCI error is detected.
3091 * @pdev: Pointer to PCI device
3092 * @state: The current pci connection state
3093 */
3094static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
3095{
3096 struct net_device *netdev = pci_get_drvdata(pdev);
3097 struct nic *nic = netdev_priv(netdev);
3098
3099 netif_device_detach(netdev);
3100
3101 if (state == pci_channel_io_perm_failure)
3102 return PCI_ERS_RESULT_DISCONNECT;
3103
3104 if (netif_running(netdev))
3105 e100_down(nic);
3106 pci_disable_device(pdev);
3107
3108 /* Request a slot reset. */
3109 return PCI_ERS_RESULT_NEED_RESET;
3110}
3111
3112/**
3113 * e100_io_slot_reset - called after the pci bus has been reset.
3114 * @pdev: Pointer to PCI device
3115 *
3116 * Restart the card from scratch.
3117 */
3118static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
3119{
3120 struct net_device *netdev = pci_get_drvdata(pdev);
3121 struct nic *nic = netdev_priv(netdev);
3122
3123 if (pci_enable_device(pdev)) {
3124 pr_err("Cannot re-enable PCI device after reset\n");
3125 return PCI_ERS_RESULT_DISCONNECT;
3126 }
3127 pci_set_master(pdev);
3128
3129 /* Only one device per card can do a reset */
3130 if (0 != PCI_FUNC(pdev->devfn))
3131 return PCI_ERS_RESULT_RECOVERED;
3132 e100_hw_reset(nic);
3133 e100_phy_init(nic);
3134
3135 return PCI_ERS_RESULT_RECOVERED;
3136}
3137
3138/**
3139 * e100_io_resume - resume normal operations
3140 * @pdev: Pointer to PCI device
3141 *
3142 * Resume normal operations after an error recovery
3143 * sequence has been completed.
3144 */
3145static void e100_io_resume(struct pci_dev *pdev)
3146{
3147 struct net_device *netdev = pci_get_drvdata(pdev);
3148 struct nic *nic = netdev_priv(netdev);
3149
3150 /* ack any pending wake events, disable PME */
3151 pci_enable_wake(pdev, PCI_D0, 0);
3152
3153 netif_device_attach(netdev);
3154 if (netif_running(netdev)) {
3155 e100_open(netdev);
3156 mod_timer(&nic->watchdog, jiffies);
3157 }
3158}
3159
3160static const struct pci_error_handlers e100_err_handler = {
3161 .error_detected = e100_io_error_detected,
3162 .slot_reset = e100_io_slot_reset,
3163 .resume = e100_io_resume,
3164};
3165
3166static SIMPLE_DEV_PM_OPS(e100_pm_ops, e100_suspend, e100_resume);
3167
3168static struct pci_driver e100_driver = {
3169 .name = DRV_NAME,
3170 .id_table = e100_id_table,
3171 .probe = e100_probe,
3172 .remove = e100_remove,
3173
3174 /* Power Management hooks */
3175 .driver.pm = &e100_pm_ops,
3176
3177 .shutdown = e100_shutdown,
3178 .err_handler = &e100_err_handler,
3179};
3180
3181static int __init e100_init_module(void)
3182{
3183 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
3184 pr_info("%s\n", DRV_DESCRIPTION);
3185 pr_info("%s\n", DRV_COPYRIGHT);
3186 }
3187 return pci_register_driver(&e100_driver);
3188}
3189
3190static void __exit e100_cleanup_module(void)
3191{
3192 pci_unregister_driver(&e100_driver);
3193}
3194
3195module_init(e100_init_module);
3196module_exit(e100_cleanup_module);
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2006 Intel Corporation. */
3
4/*
5 * e100.c: Intel(R) PRO/100 ethernet driver
6 *
7 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
8 * original e100 driver, but better described as a munging of
9 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
10 *
11 * References:
12 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
13 * Open Source Software Developers Manual,
14 * http://sourceforge.net/projects/e1000
15 *
16 *
17 * Theory of Operation
18 *
19 * I. General
20 *
21 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
22 * controller family, which includes the 82557, 82558, 82559, 82550,
23 * 82551, and 82562 devices. 82558 and greater controllers
24 * integrate the Intel 82555 PHY. The controllers are used in
25 * server and client network interface cards, as well as in
26 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
27 * configurations. 8255x supports a 32-bit linear addressing
28 * mode and operates at 33Mhz PCI clock rate.
29 *
30 * II. Driver Operation
31 *
32 * Memory-mapped mode is used exclusively to access the device's
33 * shared-memory structure, the Control/Status Registers (CSR). All
34 * setup, configuration, and control of the device, including queuing
35 * of Tx, Rx, and configuration commands is through the CSR.
36 * cmd_lock serializes accesses to the CSR command register. cb_lock
37 * protects the shared Command Block List (CBL).
38 *
39 * 8255x is highly MII-compliant and all access to the PHY go
40 * through the Management Data Interface (MDI). Consequently, the
41 * driver leverages the mii.c library shared with other MII-compliant
42 * devices.
43 *
44 * Big- and Little-Endian byte order as well as 32- and 64-bit
45 * archs are supported. Weak-ordered memory and non-cache-coherent
46 * archs are supported.
47 *
48 * III. Transmit
49 *
50 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
51 * together in a fixed-size ring (CBL) thus forming the flexible mode
52 * memory structure. A TCB marked with the suspend-bit indicates
53 * the end of the ring. The last TCB processed suspends the
54 * controller, and the controller can be restarted by issue a CU
55 * resume command to continue from the suspend point, or a CU start
56 * command to start at a given position in the ring.
57 *
58 * Non-Tx commands (config, multicast setup, etc) are linked
59 * into the CBL ring along with Tx commands. The common structure
60 * used for both Tx and non-Tx commands is the Command Block (CB).
61 *
62 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
63 * is the next CB to check for completion; cb_to_send is the first
64 * CB to start on in case of a previous failure to resume. CB clean
65 * up happens in interrupt context in response to a CU interrupt.
66 * cbs_avail keeps track of number of free CB resources available.
67 *
68 * Hardware padding of short packets to minimum packet size is
69 * enabled. 82557 pads with 7Eh, while the later controllers pad
70 * with 00h.
71 *
72 * IV. Receive
73 *
74 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
75 * Descriptors (RFD) + data buffer, thus forming the simplified mode
76 * memory structure. Rx skbs are allocated to contain both the RFD
77 * and the data buffer, but the RFD is pulled off before the skb is
78 * indicated. The data buffer is aligned such that encapsulated
79 * protocol headers are u32-aligned. Since the RFD is part of the
80 * mapped shared memory, and completion status is contained within
81 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
82 * view from software and hardware.
83 *
84 * In order to keep updates to the RFD link field from colliding with
85 * hardware writes to mark packets complete, we use the feature that
86 * hardware will not write to a size 0 descriptor and mark the previous
87 * packet as end-of-list (EL). After updating the link, we remove EL
88 * and only then restore the size such that hardware may use the
89 * previous-to-end RFD.
90 *
91 * Under typical operation, the receive unit (RU) is start once,
92 * and the controller happily fills RFDs as frames arrive. If
93 * replacement RFDs cannot be allocated, or the RU goes non-active,
94 * the RU must be restarted. Frame arrival generates an interrupt,
95 * and Rx indication and re-allocation happen in the same context,
96 * therefore no locking is required. A software-generated interrupt
97 * is generated from the watchdog to recover from a failed allocation
98 * scenario where all Rx resources have been indicated and none re-
99 * placed.
100 *
101 * V. Miscellaneous
102 *
103 * VLAN offloading of tagging, stripping and filtering is not
104 * supported, but driver will accommodate the extra 4-byte VLAN tag
105 * for processing by upper layers. Tx/Rx Checksum offloading is not
106 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
107 * not supported (hardware limitation).
108 *
109 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
110 *
111 * Thanks to JC (jchapman@katalix.com) for helping with
112 * testing/troubleshooting the development driver.
113 *
114 * TODO:
115 * o several entry points race with dev->close
116 * o check for tx-no-resources/stop Q races with tx clean/wake Q
117 *
118 * FIXES:
119 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
120 * - Stratus87247: protect MDI control register manipulations
121 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
122 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
123 */
124
125#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
126
127#include <linux/hardirq.h>
128#include <linux/interrupt.h>
129#include <linux/module.h>
130#include <linux/moduleparam.h>
131#include <linux/kernel.h>
132#include <linux/types.h>
133#include <linux/sched.h>
134#include <linux/slab.h>
135#include <linux/delay.h>
136#include <linux/init.h>
137#include <linux/pci.h>
138#include <linux/dma-mapping.h>
139#include <linux/dmapool.h>
140#include <linux/netdevice.h>
141#include <linux/etherdevice.h>
142#include <linux/mii.h>
143#include <linux/if_vlan.h>
144#include <linux/skbuff.h>
145#include <linux/ethtool.h>
146#include <linux/string.h>
147#include <linux/firmware.h>
148#include <linux/rtnetlink.h>
149#include <asm/unaligned.h>
150
151
152#define DRV_NAME "e100"
153#define DRV_EXT "-NAPI"
154#define DRV_VERSION "3.5.24-k2"DRV_EXT
155#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
156#define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
157
158#define E100_WATCHDOG_PERIOD (2 * HZ)
159#define E100_NAPI_WEIGHT 16
160
161#define FIRMWARE_D101M "e100/d101m_ucode.bin"
162#define FIRMWARE_D101S "e100/d101s_ucode.bin"
163#define FIRMWARE_D102E "e100/d102e_ucode.bin"
164
165MODULE_DESCRIPTION(DRV_DESCRIPTION);
166MODULE_AUTHOR(DRV_COPYRIGHT);
167MODULE_LICENSE("GPL v2");
168MODULE_VERSION(DRV_VERSION);
169MODULE_FIRMWARE(FIRMWARE_D101M);
170MODULE_FIRMWARE(FIRMWARE_D101S);
171MODULE_FIRMWARE(FIRMWARE_D102E);
172
173static int debug = 3;
174static int eeprom_bad_csum_allow = 0;
175static int use_io = 0;
176module_param(debug, int, 0);
177module_param(eeprom_bad_csum_allow, int, 0);
178module_param(use_io, int, 0);
179MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
180MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
181MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
182
183#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
184 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
185 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
186static const struct pci_device_id e100_id_table[] = {
187 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
188 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
189 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
190 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
191 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
192 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
193 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
194 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
196 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
197 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
198 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
199 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
200 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
204 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
205 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
206 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
207 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
208 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
209 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
213 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
214 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
215 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
216 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
217 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
218 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
219 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
220 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
221 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
222 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
223 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
224 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
225 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
226 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
227 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
228 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
229 { 0, }
230};
231MODULE_DEVICE_TABLE(pci, e100_id_table);
232
233enum mac {
234 mac_82557_D100_A = 0,
235 mac_82557_D100_B = 1,
236 mac_82557_D100_C = 2,
237 mac_82558_D101_A4 = 4,
238 mac_82558_D101_B0 = 5,
239 mac_82559_D101M = 8,
240 mac_82559_D101S = 9,
241 mac_82550_D102 = 12,
242 mac_82550_D102_C = 13,
243 mac_82551_E = 14,
244 mac_82551_F = 15,
245 mac_82551_10 = 16,
246 mac_unknown = 0xFF,
247};
248
249enum phy {
250 phy_100a = 0x000003E0,
251 phy_100c = 0x035002A8,
252 phy_82555_tx = 0x015002A8,
253 phy_nsc_tx = 0x5C002000,
254 phy_82562_et = 0x033002A8,
255 phy_82562_em = 0x032002A8,
256 phy_82562_ek = 0x031002A8,
257 phy_82562_eh = 0x017002A8,
258 phy_82552_v = 0xd061004d,
259 phy_unknown = 0xFFFFFFFF,
260};
261
262/* CSR (Control/Status Registers) */
263struct csr {
264 struct {
265 u8 status;
266 u8 stat_ack;
267 u8 cmd_lo;
268 u8 cmd_hi;
269 u32 gen_ptr;
270 } scb;
271 u32 port;
272 u16 flash_ctrl;
273 u8 eeprom_ctrl_lo;
274 u8 eeprom_ctrl_hi;
275 u32 mdi_ctrl;
276 u32 rx_dma_count;
277};
278
279enum scb_status {
280 rus_no_res = 0x08,
281 rus_ready = 0x10,
282 rus_mask = 0x3C,
283};
284
285enum ru_state {
286 RU_SUSPENDED = 0,
287 RU_RUNNING = 1,
288 RU_UNINITIALIZED = -1,
289};
290
291enum scb_stat_ack {
292 stat_ack_not_ours = 0x00,
293 stat_ack_sw_gen = 0x04,
294 stat_ack_rnr = 0x10,
295 stat_ack_cu_idle = 0x20,
296 stat_ack_frame_rx = 0x40,
297 stat_ack_cu_cmd_done = 0x80,
298 stat_ack_not_present = 0xFF,
299 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
300 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
301};
302
303enum scb_cmd_hi {
304 irq_mask_none = 0x00,
305 irq_mask_all = 0x01,
306 irq_sw_gen = 0x02,
307};
308
309enum scb_cmd_lo {
310 cuc_nop = 0x00,
311 ruc_start = 0x01,
312 ruc_load_base = 0x06,
313 cuc_start = 0x10,
314 cuc_resume = 0x20,
315 cuc_dump_addr = 0x40,
316 cuc_dump_stats = 0x50,
317 cuc_load_base = 0x60,
318 cuc_dump_reset = 0x70,
319};
320
321enum cuc_dump {
322 cuc_dump_complete = 0x0000A005,
323 cuc_dump_reset_complete = 0x0000A007,
324};
325
326enum port {
327 software_reset = 0x0000,
328 selftest = 0x0001,
329 selective_reset = 0x0002,
330};
331
332enum eeprom_ctrl_lo {
333 eesk = 0x01,
334 eecs = 0x02,
335 eedi = 0x04,
336 eedo = 0x08,
337};
338
339enum mdi_ctrl {
340 mdi_write = 0x04000000,
341 mdi_read = 0x08000000,
342 mdi_ready = 0x10000000,
343};
344
345enum eeprom_op {
346 op_write = 0x05,
347 op_read = 0x06,
348 op_ewds = 0x10,
349 op_ewen = 0x13,
350};
351
352enum eeprom_offsets {
353 eeprom_cnfg_mdix = 0x03,
354 eeprom_phy_iface = 0x06,
355 eeprom_id = 0x0A,
356 eeprom_config_asf = 0x0D,
357 eeprom_smbus_addr = 0x90,
358};
359
360enum eeprom_cnfg_mdix {
361 eeprom_mdix_enabled = 0x0080,
362};
363
364enum eeprom_phy_iface {
365 NoSuchPhy = 0,
366 I82553AB,
367 I82553C,
368 I82503,
369 DP83840,
370 S80C240,
371 S80C24,
372 I82555,
373 DP83840A = 10,
374};
375
376enum eeprom_id {
377 eeprom_id_wol = 0x0020,
378};
379
380enum eeprom_config_asf {
381 eeprom_asf = 0x8000,
382 eeprom_gcl = 0x4000,
383};
384
385enum cb_status {
386 cb_complete = 0x8000,
387 cb_ok = 0x2000,
388};
389
390/**
391 * cb_command - Command Block flags
392 * @cb_tx_nc: 0: controller does CRC (normal), 1: CRC from skb memory
393 */
394enum cb_command {
395 cb_nop = 0x0000,
396 cb_iaaddr = 0x0001,
397 cb_config = 0x0002,
398 cb_multi = 0x0003,
399 cb_tx = 0x0004,
400 cb_ucode = 0x0005,
401 cb_dump = 0x0006,
402 cb_tx_sf = 0x0008,
403 cb_tx_nc = 0x0010,
404 cb_cid = 0x1f00,
405 cb_i = 0x2000,
406 cb_s = 0x4000,
407 cb_el = 0x8000,
408};
409
410struct rfd {
411 __le16 status;
412 __le16 command;
413 __le32 link;
414 __le32 rbd;
415 __le16 actual_size;
416 __le16 size;
417};
418
419struct rx {
420 struct rx *next, *prev;
421 struct sk_buff *skb;
422 dma_addr_t dma_addr;
423};
424
425#if defined(__BIG_ENDIAN_BITFIELD)
426#define X(a,b) b,a
427#else
428#define X(a,b) a,b
429#endif
430struct config {
431/*0*/ u8 X(byte_count:6, pad0:2);
432/*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
433/*2*/ u8 adaptive_ifs;
434/*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
435 term_write_cache_line:1), pad3:4);
436/*4*/ u8 X(rx_dma_max_count:7, pad4:1);
437/*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
438/*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
439 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
440 rx_save_overruns : 1), rx_save_bad_frames : 1);
441/*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
442 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
443 tx_dynamic_tbd:1);
444/*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
445/*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
446 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
447/*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
448 loopback:2);
449/*11*/ u8 X(linear_priority:3, pad11:5);
450/*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
451/*13*/ u8 ip_addr_lo;
452/*14*/ u8 ip_addr_hi;
453/*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
454 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
455 pad15_2:1), crs_or_cdt:1);
456/*16*/ u8 fc_delay_lo;
457/*17*/ u8 fc_delay_hi;
458/*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
459 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
460/*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
461 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
462 full_duplex_force:1), full_duplex_pin:1);
463/*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
464/*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
465/*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
466 u8 pad_d102[9];
467};
468
469#define E100_MAX_MULTICAST_ADDRS 64
470struct multi {
471 __le16 count;
472 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
473};
474
475/* Important: keep total struct u32-aligned */
476#define UCODE_SIZE 134
477struct cb {
478 __le16 status;
479 __le16 command;
480 __le32 link;
481 union {
482 u8 iaaddr[ETH_ALEN];
483 __le32 ucode[UCODE_SIZE];
484 struct config config;
485 struct multi multi;
486 struct {
487 u32 tbd_array;
488 u16 tcb_byte_count;
489 u8 threshold;
490 u8 tbd_count;
491 struct {
492 __le32 buf_addr;
493 __le16 size;
494 u16 eol;
495 } tbd;
496 } tcb;
497 __le32 dump_buffer_addr;
498 } u;
499 struct cb *next, *prev;
500 dma_addr_t dma_addr;
501 struct sk_buff *skb;
502};
503
504enum loopback {
505 lb_none = 0, lb_mac = 1, lb_phy = 3,
506};
507
508struct stats {
509 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
510 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
511 tx_multiple_collisions, tx_total_collisions;
512 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
513 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
514 rx_short_frame_errors;
515 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
516 __le16 xmt_tco_frames, rcv_tco_frames;
517 __le32 complete;
518};
519
520struct mem {
521 struct {
522 u32 signature;
523 u32 result;
524 } selftest;
525 struct stats stats;
526 u8 dump_buf[596];
527};
528
529struct param_range {
530 u32 min;
531 u32 max;
532 u32 count;
533};
534
535struct params {
536 struct param_range rfds;
537 struct param_range cbs;
538};
539
540struct nic {
541 /* Begin: frequently used values: keep adjacent for cache effect */
542 u32 msg_enable ____cacheline_aligned;
543 struct net_device *netdev;
544 struct pci_dev *pdev;
545 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
546
547 struct rx *rxs ____cacheline_aligned;
548 struct rx *rx_to_use;
549 struct rx *rx_to_clean;
550 struct rfd blank_rfd;
551 enum ru_state ru_running;
552
553 spinlock_t cb_lock ____cacheline_aligned;
554 spinlock_t cmd_lock;
555 struct csr __iomem *csr;
556 enum scb_cmd_lo cuc_cmd;
557 unsigned int cbs_avail;
558 struct napi_struct napi;
559 struct cb *cbs;
560 struct cb *cb_to_use;
561 struct cb *cb_to_send;
562 struct cb *cb_to_clean;
563 __le16 tx_command;
564 /* End: frequently used values: keep adjacent for cache effect */
565
566 enum {
567 ich = (1 << 0),
568 promiscuous = (1 << 1),
569 multicast_all = (1 << 2),
570 wol_magic = (1 << 3),
571 ich_10h_workaround = (1 << 4),
572 } flags ____cacheline_aligned;
573
574 enum mac mac;
575 enum phy phy;
576 struct params params;
577 struct timer_list watchdog;
578 struct mii_if_info mii;
579 struct work_struct tx_timeout_task;
580 enum loopback loopback;
581
582 struct mem *mem;
583 dma_addr_t dma_addr;
584
585 struct dma_pool *cbs_pool;
586 dma_addr_t cbs_dma_addr;
587 u8 adaptive_ifs;
588 u8 tx_threshold;
589 u32 tx_frames;
590 u32 tx_collisions;
591 u32 tx_deferred;
592 u32 tx_single_collisions;
593 u32 tx_multiple_collisions;
594 u32 tx_fc_pause;
595 u32 tx_tco_frames;
596
597 u32 rx_fc_pause;
598 u32 rx_fc_unsupported;
599 u32 rx_tco_frames;
600 u32 rx_short_frame_errors;
601 u32 rx_over_length_errors;
602
603 u16 eeprom_wc;
604 __le16 eeprom[256];
605 spinlock_t mdio_lock;
606 const struct firmware *fw;
607};
608
609static inline void e100_write_flush(struct nic *nic)
610{
611 /* Flush previous PCI writes through intermediate bridges
612 * by doing a benign read */
613 (void)ioread8(&nic->csr->scb.status);
614}
615
616static void e100_enable_irq(struct nic *nic)
617{
618 unsigned long flags;
619
620 spin_lock_irqsave(&nic->cmd_lock, flags);
621 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
622 e100_write_flush(nic);
623 spin_unlock_irqrestore(&nic->cmd_lock, flags);
624}
625
626static void e100_disable_irq(struct nic *nic)
627{
628 unsigned long flags;
629
630 spin_lock_irqsave(&nic->cmd_lock, flags);
631 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
632 e100_write_flush(nic);
633 spin_unlock_irqrestore(&nic->cmd_lock, flags);
634}
635
636static void e100_hw_reset(struct nic *nic)
637{
638 /* Put CU and RU into idle with a selective reset to get
639 * device off of PCI bus */
640 iowrite32(selective_reset, &nic->csr->port);
641 e100_write_flush(nic); udelay(20);
642
643 /* Now fully reset device */
644 iowrite32(software_reset, &nic->csr->port);
645 e100_write_flush(nic); udelay(20);
646
647 /* Mask off our interrupt line - it's unmasked after reset */
648 e100_disable_irq(nic);
649}
650
651static int e100_self_test(struct nic *nic)
652{
653 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
654
655 /* Passing the self-test is a pretty good indication
656 * that the device can DMA to/from host memory */
657
658 nic->mem->selftest.signature = 0;
659 nic->mem->selftest.result = 0xFFFFFFFF;
660
661 iowrite32(selftest | dma_addr, &nic->csr->port);
662 e100_write_flush(nic);
663 /* Wait 10 msec for self-test to complete */
664 msleep(10);
665
666 /* Interrupts are enabled after self-test */
667 e100_disable_irq(nic);
668
669 /* Check results of self-test */
670 if (nic->mem->selftest.result != 0) {
671 netif_err(nic, hw, nic->netdev,
672 "Self-test failed: result=0x%08X\n",
673 nic->mem->selftest.result);
674 return -ETIMEDOUT;
675 }
676 if (nic->mem->selftest.signature == 0) {
677 netif_err(nic, hw, nic->netdev, "Self-test failed: timed out\n");
678 return -ETIMEDOUT;
679 }
680
681 return 0;
682}
683
684static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
685{
686 u32 cmd_addr_data[3];
687 u8 ctrl;
688 int i, j;
689
690 /* Three cmds: write/erase enable, write data, write/erase disable */
691 cmd_addr_data[0] = op_ewen << (addr_len - 2);
692 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
693 le16_to_cpu(data);
694 cmd_addr_data[2] = op_ewds << (addr_len - 2);
695
696 /* Bit-bang cmds to write word to eeprom */
697 for (j = 0; j < 3; j++) {
698
699 /* Chip select */
700 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
701 e100_write_flush(nic); udelay(4);
702
703 for (i = 31; i >= 0; i--) {
704 ctrl = (cmd_addr_data[j] & (1 << i)) ?
705 eecs | eedi : eecs;
706 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
707 e100_write_flush(nic); udelay(4);
708
709 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
710 e100_write_flush(nic); udelay(4);
711 }
712 /* Wait 10 msec for cmd to complete */
713 msleep(10);
714
715 /* Chip deselect */
716 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
717 e100_write_flush(nic); udelay(4);
718 }
719};
720
721/* General technique stolen from the eepro100 driver - very clever */
722static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
723{
724 u32 cmd_addr_data;
725 u16 data = 0;
726 u8 ctrl;
727 int i;
728
729 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
730
731 /* Chip select */
732 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
733 e100_write_flush(nic); udelay(4);
734
735 /* Bit-bang to read word from eeprom */
736 for (i = 31; i >= 0; i--) {
737 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
738 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
739 e100_write_flush(nic); udelay(4);
740
741 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
742 e100_write_flush(nic); udelay(4);
743
744 /* Eeprom drives a dummy zero to EEDO after receiving
745 * complete address. Use this to adjust addr_len. */
746 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
747 if (!(ctrl & eedo) && i > 16) {
748 *addr_len -= (i - 16);
749 i = 17;
750 }
751
752 data = (data << 1) | (ctrl & eedo ? 1 : 0);
753 }
754
755 /* Chip deselect */
756 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
757 e100_write_flush(nic); udelay(4);
758
759 return cpu_to_le16(data);
760};
761
762/* Load entire EEPROM image into driver cache and validate checksum */
763static int e100_eeprom_load(struct nic *nic)
764{
765 u16 addr, addr_len = 8, checksum = 0;
766
767 /* Try reading with an 8-bit addr len to discover actual addr len */
768 e100_eeprom_read(nic, &addr_len, 0);
769 nic->eeprom_wc = 1 << addr_len;
770
771 for (addr = 0; addr < nic->eeprom_wc; addr++) {
772 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
773 if (addr < nic->eeprom_wc - 1)
774 checksum += le16_to_cpu(nic->eeprom[addr]);
775 }
776
777 /* The checksum, stored in the last word, is calculated such that
778 * the sum of words should be 0xBABA */
779 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
780 netif_err(nic, probe, nic->netdev, "EEPROM corrupted\n");
781 if (!eeprom_bad_csum_allow)
782 return -EAGAIN;
783 }
784
785 return 0;
786}
787
788/* Save (portion of) driver EEPROM cache to device and update checksum */
789static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
790{
791 u16 addr, addr_len = 8, checksum = 0;
792
793 /* Try reading with an 8-bit addr len to discover actual addr len */
794 e100_eeprom_read(nic, &addr_len, 0);
795 nic->eeprom_wc = 1 << addr_len;
796
797 if (start + count >= nic->eeprom_wc)
798 return -EINVAL;
799
800 for (addr = start; addr < start + count; addr++)
801 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
802
803 /* The checksum, stored in the last word, is calculated such that
804 * the sum of words should be 0xBABA */
805 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
806 checksum += le16_to_cpu(nic->eeprom[addr]);
807 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
808 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
809 nic->eeprom[nic->eeprom_wc - 1]);
810
811 return 0;
812}
813
814#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
815#define E100_WAIT_SCB_FAST 20 /* delay like the old code */
816static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
817{
818 unsigned long flags;
819 unsigned int i;
820 int err = 0;
821
822 spin_lock_irqsave(&nic->cmd_lock, flags);
823
824 /* Previous command is accepted when SCB clears */
825 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
826 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
827 break;
828 cpu_relax();
829 if (unlikely(i > E100_WAIT_SCB_FAST))
830 udelay(5);
831 }
832 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
833 err = -EAGAIN;
834 goto err_unlock;
835 }
836
837 if (unlikely(cmd != cuc_resume))
838 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
839 iowrite8(cmd, &nic->csr->scb.cmd_lo);
840
841err_unlock:
842 spin_unlock_irqrestore(&nic->cmd_lock, flags);
843
844 return err;
845}
846
847static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
848 int (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
849{
850 struct cb *cb;
851 unsigned long flags;
852 int err;
853
854 spin_lock_irqsave(&nic->cb_lock, flags);
855
856 if (unlikely(!nic->cbs_avail)) {
857 err = -ENOMEM;
858 goto err_unlock;
859 }
860
861 cb = nic->cb_to_use;
862 nic->cb_to_use = cb->next;
863 nic->cbs_avail--;
864 cb->skb = skb;
865
866 err = cb_prepare(nic, cb, skb);
867 if (err)
868 goto err_unlock;
869
870 if (unlikely(!nic->cbs_avail))
871 err = -ENOSPC;
872
873
874 /* Order is important otherwise we'll be in a race with h/w:
875 * set S-bit in current first, then clear S-bit in previous. */
876 cb->command |= cpu_to_le16(cb_s);
877 dma_wmb();
878 cb->prev->command &= cpu_to_le16(~cb_s);
879
880 while (nic->cb_to_send != nic->cb_to_use) {
881 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
882 nic->cb_to_send->dma_addr))) {
883 /* Ok, here's where things get sticky. It's
884 * possible that we can't schedule the command
885 * because the controller is too busy, so
886 * let's just queue the command and try again
887 * when another command is scheduled. */
888 if (err == -ENOSPC) {
889 //request a reset
890 schedule_work(&nic->tx_timeout_task);
891 }
892 break;
893 } else {
894 nic->cuc_cmd = cuc_resume;
895 nic->cb_to_send = nic->cb_to_send->next;
896 }
897 }
898
899err_unlock:
900 spin_unlock_irqrestore(&nic->cb_lock, flags);
901
902 return err;
903}
904
905static int mdio_read(struct net_device *netdev, int addr, int reg)
906{
907 struct nic *nic = netdev_priv(netdev);
908 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
909}
910
911static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
912{
913 struct nic *nic = netdev_priv(netdev);
914
915 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
916}
917
918/* the standard mdio_ctrl() function for usual MII-compliant hardware */
919static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
920{
921 u32 data_out = 0;
922 unsigned int i;
923 unsigned long flags;
924
925
926 /*
927 * Stratus87247: we shouldn't be writing the MDI control
928 * register until the Ready bit shows True. Also, since
929 * manipulation of the MDI control registers is a multi-step
930 * procedure it should be done under lock.
931 */
932 spin_lock_irqsave(&nic->mdio_lock, flags);
933 for (i = 100; i; --i) {
934 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
935 break;
936 udelay(20);
937 }
938 if (unlikely(!i)) {
939 netdev_err(nic->netdev, "e100.mdio_ctrl won't go Ready\n");
940 spin_unlock_irqrestore(&nic->mdio_lock, flags);
941 return 0; /* No way to indicate timeout error */
942 }
943 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
944
945 for (i = 0; i < 100; i++) {
946 udelay(20);
947 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
948 break;
949 }
950 spin_unlock_irqrestore(&nic->mdio_lock, flags);
951 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
952 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
953 dir == mdi_read ? "READ" : "WRITE",
954 addr, reg, data, data_out);
955 return (u16)data_out;
956}
957
958/* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
959static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
960 u32 addr,
961 u32 dir,
962 u32 reg,
963 u16 data)
964{
965 if ((reg == MII_BMCR) && (dir == mdi_write)) {
966 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
967 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
968 MII_ADVERTISE);
969
970 /*
971 * Workaround Si issue where sometimes the part will not
972 * autoneg to 100Mbps even when advertised.
973 */
974 if (advert & ADVERTISE_100FULL)
975 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
976 else if (advert & ADVERTISE_100HALF)
977 data |= BMCR_SPEED100;
978 }
979 }
980 return mdio_ctrl_hw(nic, addr, dir, reg, data);
981}
982
983/* Fully software-emulated mdio_ctrl() function for cards without
984 * MII-compliant PHYs.
985 * For now, this is mainly geared towards 80c24 support; in case of further
986 * requirements for other types (i82503, ...?) either extend this mechanism
987 * or split it, whichever is cleaner.
988 */
989static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
990 u32 addr,
991 u32 dir,
992 u32 reg,
993 u16 data)
994{
995 /* might need to allocate a netdev_priv'ed register array eventually
996 * to be able to record state changes, but for now
997 * some fully hardcoded register handling ought to be ok I guess. */
998
999 if (dir == mdi_read) {
1000 switch (reg) {
1001 case MII_BMCR:
1002 /* Auto-negotiation, right? */
1003 return BMCR_ANENABLE |
1004 BMCR_FULLDPLX;
1005 case MII_BMSR:
1006 return BMSR_LSTATUS /* for mii_link_ok() */ |
1007 BMSR_ANEGCAPABLE |
1008 BMSR_10FULL;
1009 case MII_ADVERTISE:
1010 /* 80c24 is a "combo card" PHY, right? */
1011 return ADVERTISE_10HALF |
1012 ADVERTISE_10FULL;
1013 default:
1014 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1015 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1016 dir == mdi_read ? "READ" : "WRITE",
1017 addr, reg, data);
1018 return 0xFFFF;
1019 }
1020 } else {
1021 switch (reg) {
1022 default:
1023 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1024 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1025 dir == mdi_read ? "READ" : "WRITE",
1026 addr, reg, data);
1027 return 0xFFFF;
1028 }
1029 }
1030}
1031static inline int e100_phy_supports_mii(struct nic *nic)
1032{
1033 /* for now, just check it by comparing whether we
1034 are using MII software emulation.
1035 */
1036 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1037}
1038
1039static void e100_get_defaults(struct nic *nic)
1040{
1041 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1042 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1043
1044 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
1045 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
1046 if (nic->mac == mac_unknown)
1047 nic->mac = mac_82557_D100_A;
1048
1049 nic->params.rfds = rfds;
1050 nic->params.cbs = cbs;
1051
1052 /* Quadwords to DMA into FIFO before starting frame transmit */
1053 nic->tx_threshold = 0xE0;
1054
1055 /* no interrupt for every tx completion, delay = 256us if not 557 */
1056 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1057 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1058
1059 /* Template for a freshly allocated RFD */
1060 nic->blank_rfd.command = 0;
1061 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1062 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN);
1063
1064 /* MII setup */
1065 nic->mii.phy_id_mask = 0x1F;
1066 nic->mii.reg_num_mask = 0x1F;
1067 nic->mii.dev = nic->netdev;
1068 nic->mii.mdio_read = mdio_read;
1069 nic->mii.mdio_write = mdio_write;
1070}
1071
1072static int e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1073{
1074 struct config *config = &cb->u.config;
1075 u8 *c = (u8 *)config;
1076 struct net_device *netdev = nic->netdev;
1077
1078 cb->command = cpu_to_le16(cb_config);
1079
1080 memset(config, 0, sizeof(struct config));
1081
1082 config->byte_count = 0x16; /* bytes in this struct */
1083 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1084 config->direct_rx_dma = 0x1; /* reserved */
1085 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1086 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1087 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1088 config->tx_underrun_retry = 0x3; /* # of underrun retries */
1089 if (e100_phy_supports_mii(nic))
1090 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1091 config->pad10 = 0x6;
1092 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1093 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1094 config->ifs = 0x6; /* x16 = inter frame spacing */
1095 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1096 config->pad15_1 = 0x1;
1097 config->pad15_2 = 0x1;
1098 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1099 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1100 config->tx_padding = 0x1; /* 1=pad short frames */
1101 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1102 config->pad18 = 0x1;
1103 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1104 config->pad20_1 = 0x1F;
1105 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1106 config->pad21_1 = 0x5;
1107
1108 config->adaptive_ifs = nic->adaptive_ifs;
1109 config->loopback = nic->loopback;
1110
1111 if (nic->mii.force_media && nic->mii.full_duplex)
1112 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1113
1114 if (nic->flags & promiscuous || nic->loopback) {
1115 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1116 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1117 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1118 }
1119
1120 if (unlikely(netdev->features & NETIF_F_RXFCS))
1121 config->rx_crc_transfer = 0x1; /* 1=save, 0=discard */
1122
1123 if (nic->flags & multicast_all)
1124 config->multicast_all = 0x1; /* 1=accept, 0=no */
1125
1126 /* disable WoL when up */
1127 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1128 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1129
1130 if (nic->mac >= mac_82558_D101_A4) {
1131 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1132 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1133 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1134 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1135 if (nic->mac >= mac_82559_D101M) {
1136 config->tno_intr = 0x1; /* TCO stats enable */
1137 /* Enable TCO in extended config */
1138 if (nic->mac >= mac_82551_10) {
1139 config->byte_count = 0x20; /* extended bytes */
1140 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1141 }
1142 } else {
1143 config->standard_stat_counter = 0x0;
1144 }
1145 }
1146
1147 if (netdev->features & NETIF_F_RXALL) {
1148 config->rx_save_overruns = 0x1; /* 1=save, 0=discard */
1149 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1150 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1151 }
1152
1153 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[00-07]=%8ph\n",
1154 c + 0);
1155 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[08-15]=%8ph\n",
1156 c + 8);
1157 netif_printk(nic, hw, KERN_DEBUG, nic->netdev, "[16-23]=%8ph\n",
1158 c + 16);
1159 return 0;
1160}
1161
1162/*************************************************************************
1163* CPUSaver parameters
1164*
1165* All CPUSaver parameters are 16-bit literals that are part of a
1166* "move immediate value" instruction. By changing the value of
1167* the literal in the instruction before the code is loaded, the
1168* driver can change the algorithm.
1169*
1170* INTDELAY - This loads the dead-man timer with its initial value.
1171* When this timer expires the interrupt is asserted, and the
1172* timer is reset each time a new packet is received. (see
1173* BUNDLEMAX below to set the limit on number of chained packets)
1174* The current default is 0x600 or 1536. Experiments show that
1175* the value should probably stay within the 0x200 - 0x1000.
1176*
1177* BUNDLEMAX -
1178* This sets the maximum number of frames that will be bundled. In
1179* some situations, such as the TCP windowing algorithm, it may be
1180* better to limit the growth of the bundle size than let it go as
1181* high as it can, because that could cause too much added latency.
1182* The default is six, because this is the number of packets in the
1183* default TCP window size. A value of 1 would make CPUSaver indicate
1184* an interrupt for every frame received. If you do not want to put
1185* a limit on the bundle size, set this value to xFFFF.
1186*
1187* BUNDLESMALL -
1188* This contains a bit-mask describing the minimum size frame that
1189* will be bundled. The default masks the lower 7 bits, which means
1190* that any frame less than 128 bytes in length will not be bundled,
1191* but will instead immediately generate an interrupt. This does
1192* not affect the current bundle in any way. Any frame that is 128
1193* bytes or large will be bundled normally. This feature is meant
1194* to provide immediate indication of ACK frames in a TCP environment.
1195* Customers were seeing poor performance when a machine with CPUSaver
1196* enabled was sending but not receiving. The delay introduced when
1197* the ACKs were received was enough to reduce total throughput, because
1198* the sender would sit idle until the ACK was finally seen.
1199*
1200* The current default is 0xFF80, which masks out the lower 7 bits.
1201* This means that any frame which is x7F (127) bytes or smaller
1202* will cause an immediate interrupt. Because this value must be a
1203* bit mask, there are only a few valid values that can be used. To
1204* turn this feature off, the driver can write the value xFFFF to the
1205* lower word of this instruction (in the same way that the other
1206* parameters are used). Likewise, a value of 0xF800 (2047) would
1207* cause an interrupt to be generated for every frame, because all
1208* standard Ethernet frames are <= 2047 bytes in length.
1209*************************************************************************/
1210
1211/* if you wish to disable the ucode functionality, while maintaining the
1212 * workarounds it provides, set the following defines to:
1213 * BUNDLESMALL 0
1214 * BUNDLEMAX 1
1215 * INTDELAY 1
1216 */
1217#define BUNDLESMALL 1
1218#define BUNDLEMAX (u16)6
1219#define INTDELAY (u16)1536 /* 0x600 */
1220
1221/* Initialize firmware */
1222static const struct firmware *e100_request_firmware(struct nic *nic)
1223{
1224 const char *fw_name;
1225 const struct firmware *fw = nic->fw;
1226 u8 timer, bundle, min_size;
1227 int err = 0;
1228 bool required = false;
1229
1230 /* do not load u-code for ICH devices */
1231 if (nic->flags & ich)
1232 return NULL;
1233
1234 /* Search for ucode match against h/w revision
1235 *
1236 * Based on comments in the source code for the FreeBSD fxp
1237 * driver, the FIRMWARE_D102E ucode includes both CPUSaver and
1238 *
1239 * "fixes for bugs in the B-step hardware (specifically, bugs
1240 * with Inline Receive)."
1241 *
1242 * So we must fail if it cannot be loaded.
1243 *
1244 * The other microcode files are only required for the optional
1245 * CPUSaver feature. Nice to have, but no reason to fail.
1246 */
1247 if (nic->mac == mac_82559_D101M) {
1248 fw_name = FIRMWARE_D101M;
1249 } else if (nic->mac == mac_82559_D101S) {
1250 fw_name = FIRMWARE_D101S;
1251 } else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10) {
1252 fw_name = FIRMWARE_D102E;
1253 required = true;
1254 } else { /* No ucode on other devices */
1255 return NULL;
1256 }
1257
1258 /* If the firmware has not previously been loaded, request a pointer
1259 * to it. If it was previously loaded, we are reinitializing the
1260 * adapter, possibly in a resume from hibernate, in which case
1261 * request_firmware() cannot be used.
1262 */
1263 if (!fw)
1264 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1265
1266 if (err) {
1267 if (required) {
1268 netif_err(nic, probe, nic->netdev,
1269 "Failed to load firmware \"%s\": %d\n",
1270 fw_name, err);
1271 return ERR_PTR(err);
1272 } else {
1273 netif_info(nic, probe, nic->netdev,
1274 "CPUSaver disabled. Needs \"%s\": %d\n",
1275 fw_name, err);
1276 return NULL;
1277 }
1278 }
1279
1280 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1281 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1282 if (fw->size != UCODE_SIZE * 4 + 3) {
1283 netif_err(nic, probe, nic->netdev,
1284 "Firmware \"%s\" has wrong size %zu\n",
1285 fw_name, fw->size);
1286 release_firmware(fw);
1287 return ERR_PTR(-EINVAL);
1288 }
1289
1290 /* Read timer, bundle and min_size from end of firmware blob */
1291 timer = fw->data[UCODE_SIZE * 4];
1292 bundle = fw->data[UCODE_SIZE * 4 + 1];
1293 min_size = fw->data[UCODE_SIZE * 4 + 2];
1294
1295 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1296 min_size >= UCODE_SIZE) {
1297 netif_err(nic, probe, nic->netdev,
1298 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1299 fw_name, timer, bundle, min_size);
1300 release_firmware(fw);
1301 return ERR_PTR(-EINVAL);
1302 }
1303
1304 /* OK, firmware is validated and ready to use. Save a pointer
1305 * to it in the nic */
1306 nic->fw = fw;
1307 return fw;
1308}
1309
1310static int e100_setup_ucode(struct nic *nic, struct cb *cb,
1311 struct sk_buff *skb)
1312{
1313 const struct firmware *fw = (void *)skb;
1314 u8 timer, bundle, min_size;
1315
1316 /* It's not a real skb; we just abused the fact that e100_exec_cb
1317 will pass it through to here... */
1318 cb->skb = NULL;
1319
1320 /* firmware is stored as little endian already */
1321 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1322
1323 /* Read timer, bundle and min_size from end of firmware blob */
1324 timer = fw->data[UCODE_SIZE * 4];
1325 bundle = fw->data[UCODE_SIZE * 4 + 1];
1326 min_size = fw->data[UCODE_SIZE * 4 + 2];
1327
1328 /* Insert user-tunable settings in cb->u.ucode */
1329 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1330 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1331 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1332 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1333 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1334 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1335
1336 cb->command = cpu_to_le16(cb_ucode | cb_el);
1337 return 0;
1338}
1339
1340static inline int e100_load_ucode_wait(struct nic *nic)
1341{
1342 const struct firmware *fw;
1343 int err = 0, counter = 50;
1344 struct cb *cb = nic->cb_to_clean;
1345
1346 fw = e100_request_firmware(nic);
1347 /* If it's NULL, then no ucode is required */
1348 if (IS_ERR_OR_NULL(fw))
1349 return PTR_ERR_OR_ZERO(fw);
1350
1351 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
1352 netif_err(nic, probe, nic->netdev,
1353 "ucode cmd failed with error %d\n", err);
1354
1355 /* must restart cuc */
1356 nic->cuc_cmd = cuc_start;
1357
1358 /* wait for completion */
1359 e100_write_flush(nic);
1360 udelay(10);
1361
1362 /* wait for possibly (ouch) 500ms */
1363 while (!(cb->status & cpu_to_le16(cb_complete))) {
1364 msleep(10);
1365 if (!--counter) break;
1366 }
1367
1368 /* ack any interrupts, something could have been set */
1369 iowrite8(~0, &nic->csr->scb.stat_ack);
1370
1371 /* if the command failed, or is not OK, notify and return */
1372 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1373 netif_err(nic, probe, nic->netdev, "ucode load failed\n");
1374 err = -EPERM;
1375 }
1376
1377 return err;
1378}
1379
1380static int e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1381 struct sk_buff *skb)
1382{
1383 cb->command = cpu_to_le16(cb_iaaddr);
1384 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1385 return 0;
1386}
1387
1388static int e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1389{
1390 cb->command = cpu_to_le16(cb_dump);
1391 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1392 offsetof(struct mem, dump_buf));
1393 return 0;
1394}
1395
1396static int e100_phy_check_without_mii(struct nic *nic)
1397{
1398 u8 phy_type;
1399 int without_mii;
1400
1401 phy_type = (nic->eeprom[eeprom_phy_iface] >> 8) & 0x0f;
1402
1403 switch (phy_type) {
1404 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1405 case I82503: /* Non-MII PHY; UNTESTED! */
1406 case S80C24: /* Non-MII PHY; tested and working */
1407 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1408 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1409 * doesn't have a programming interface of any sort. The
1410 * media is sensed automatically based on how the link partner
1411 * is configured. This is, in essence, manual configuration.
1412 */
1413 netif_info(nic, probe, nic->netdev,
1414 "found MII-less i82503 or 80c24 or other PHY\n");
1415
1416 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1417 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1418
1419 /* these might be needed for certain MII-less cards...
1420 * nic->flags |= ich;
1421 * nic->flags |= ich_10h_workaround; */
1422
1423 without_mii = 1;
1424 break;
1425 default:
1426 without_mii = 0;
1427 break;
1428 }
1429 return without_mii;
1430}
1431
1432#define NCONFIG_AUTO_SWITCH 0x0080
1433#define MII_NSC_CONG MII_RESV1
1434#define NSC_CONG_ENABLE 0x0100
1435#define NSC_CONG_TXREADY 0x0400
1436#define ADVERTISE_FC_SUPPORTED 0x0400
1437static int e100_phy_init(struct nic *nic)
1438{
1439 struct net_device *netdev = nic->netdev;
1440 u32 addr;
1441 u16 bmcr, stat, id_lo, id_hi, cong;
1442
1443 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1444 for (addr = 0; addr < 32; addr++) {
1445 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1446 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1447 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1448 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1449 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1450 break;
1451 }
1452 if (addr == 32) {
1453 /* uhoh, no PHY detected: check whether we seem to be some
1454 * weird, rare variant which is *known* to not have any MII.
1455 * But do this AFTER MII checking only, since this does
1456 * lookup of EEPROM values which may easily be unreliable. */
1457 if (e100_phy_check_without_mii(nic))
1458 return 0; /* simply return and hope for the best */
1459 else {
1460 /* for unknown cases log a fatal error */
1461 netif_err(nic, hw, nic->netdev,
1462 "Failed to locate any known PHY, aborting\n");
1463 return -EAGAIN;
1464 }
1465 } else
1466 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1467 "phy_addr = %d\n", nic->mii.phy_id);
1468
1469 /* Get phy ID */
1470 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1471 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1472 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1473 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1474 "phy ID = 0x%08X\n", nic->phy);
1475
1476 /* Select the phy and isolate the rest */
1477 for (addr = 0; addr < 32; addr++) {
1478 if (addr != nic->mii.phy_id) {
1479 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1480 } else if (nic->phy != phy_82552_v) {
1481 bmcr = mdio_read(netdev, addr, MII_BMCR);
1482 mdio_write(netdev, addr, MII_BMCR,
1483 bmcr & ~BMCR_ISOLATE);
1484 }
1485 }
1486 /*
1487 * Workaround for 82552:
1488 * Clear the ISOLATE bit on selected phy_id last (mirrored on all
1489 * other phy_id's) using bmcr value from addr discovery loop above.
1490 */
1491 if (nic->phy == phy_82552_v)
1492 mdio_write(netdev, nic->mii.phy_id, MII_BMCR,
1493 bmcr & ~BMCR_ISOLATE);
1494
1495 /* Handle National tx phys */
1496#define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1497 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1498 /* Disable congestion control */
1499 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1500 cong |= NSC_CONG_TXREADY;
1501 cong &= ~NSC_CONG_ENABLE;
1502 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1503 }
1504
1505 if (nic->phy == phy_82552_v) {
1506 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1507
1508 /* assign special tweaked mdio_ctrl() function */
1509 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1510
1511 /* Workaround Si not advertising flow-control during autoneg */
1512 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1513 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1514
1515 /* Reset for the above changes to take effect */
1516 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1517 bmcr |= BMCR_RESET;
1518 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1519 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1520 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1521 (nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1522 /* enable/disable MDI/MDI-X auto-switching. */
1523 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1524 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1525 }
1526
1527 return 0;
1528}
1529
1530static int e100_hw_init(struct nic *nic)
1531{
1532 int err = 0;
1533
1534 e100_hw_reset(nic);
1535
1536 netif_err(nic, hw, nic->netdev, "e100_hw_init\n");
1537 if (!in_interrupt() && (err = e100_self_test(nic)))
1538 return err;
1539
1540 if ((err = e100_phy_init(nic)))
1541 return err;
1542 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1543 return err;
1544 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1545 return err;
1546 if ((err = e100_load_ucode_wait(nic)))
1547 return err;
1548 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1549 return err;
1550 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1551 return err;
1552 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1553 nic->dma_addr + offsetof(struct mem, stats))))
1554 return err;
1555 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1556 return err;
1557
1558 e100_disable_irq(nic);
1559
1560 return 0;
1561}
1562
1563static int e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1564{
1565 struct net_device *netdev = nic->netdev;
1566 struct netdev_hw_addr *ha;
1567 u16 i, count = min(netdev_mc_count(netdev), E100_MAX_MULTICAST_ADDRS);
1568
1569 cb->command = cpu_to_le16(cb_multi);
1570 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1571 i = 0;
1572 netdev_for_each_mc_addr(ha, netdev) {
1573 if (i == count)
1574 break;
1575 memcpy(&cb->u.multi.addr[i++ * ETH_ALEN], &ha->addr,
1576 ETH_ALEN);
1577 }
1578 return 0;
1579}
1580
1581static void e100_set_multicast_list(struct net_device *netdev)
1582{
1583 struct nic *nic = netdev_priv(netdev);
1584
1585 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1586 "mc_count=%d, flags=0x%04X\n",
1587 netdev_mc_count(netdev), netdev->flags);
1588
1589 if (netdev->flags & IFF_PROMISC)
1590 nic->flags |= promiscuous;
1591 else
1592 nic->flags &= ~promiscuous;
1593
1594 if (netdev->flags & IFF_ALLMULTI ||
1595 netdev_mc_count(netdev) > E100_MAX_MULTICAST_ADDRS)
1596 nic->flags |= multicast_all;
1597 else
1598 nic->flags &= ~multicast_all;
1599
1600 e100_exec_cb(nic, NULL, e100_configure);
1601 e100_exec_cb(nic, NULL, e100_multi);
1602}
1603
1604static void e100_update_stats(struct nic *nic)
1605{
1606 struct net_device *dev = nic->netdev;
1607 struct net_device_stats *ns = &dev->stats;
1608 struct stats *s = &nic->mem->stats;
1609 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1610 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1611 &s->complete;
1612
1613 /* Device's stats reporting may take several microseconds to
1614 * complete, so we're always waiting for results of the
1615 * previous command. */
1616
1617 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1618 *complete = 0;
1619 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1620 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1621 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1622 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1623 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1624 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1625 ns->collisions += nic->tx_collisions;
1626 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1627 le32_to_cpu(s->tx_lost_crs);
1628 nic->rx_short_frame_errors +=
1629 le32_to_cpu(s->rx_short_frame_errors);
1630 ns->rx_length_errors = nic->rx_short_frame_errors +
1631 nic->rx_over_length_errors;
1632 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1633 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1634 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1635 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1636 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1637 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1638 le32_to_cpu(s->rx_alignment_errors) +
1639 le32_to_cpu(s->rx_short_frame_errors) +
1640 le32_to_cpu(s->rx_cdt_errors);
1641 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1642 nic->tx_single_collisions +=
1643 le32_to_cpu(s->tx_single_collisions);
1644 nic->tx_multiple_collisions +=
1645 le32_to_cpu(s->tx_multiple_collisions);
1646 if (nic->mac >= mac_82558_D101_A4) {
1647 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1648 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1649 nic->rx_fc_unsupported +=
1650 le32_to_cpu(s->fc_rcv_unsupported);
1651 if (nic->mac >= mac_82559_D101M) {
1652 nic->tx_tco_frames +=
1653 le16_to_cpu(s->xmt_tco_frames);
1654 nic->rx_tco_frames +=
1655 le16_to_cpu(s->rcv_tco_frames);
1656 }
1657 }
1658 }
1659
1660
1661 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1662 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1663 "exec cuc_dump_reset failed\n");
1664}
1665
1666static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1667{
1668 /* Adjust inter-frame-spacing (IFS) between two transmits if
1669 * we're getting collisions on a half-duplex connection. */
1670
1671 if (duplex == DUPLEX_HALF) {
1672 u32 prev = nic->adaptive_ifs;
1673 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1674
1675 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1676 (nic->tx_frames > min_frames)) {
1677 if (nic->adaptive_ifs < 60)
1678 nic->adaptive_ifs += 5;
1679 } else if (nic->tx_frames < min_frames) {
1680 if (nic->adaptive_ifs >= 5)
1681 nic->adaptive_ifs -= 5;
1682 }
1683 if (nic->adaptive_ifs != prev)
1684 e100_exec_cb(nic, NULL, e100_configure);
1685 }
1686}
1687
1688static void e100_watchdog(struct timer_list *t)
1689{
1690 struct nic *nic = from_timer(nic, t, watchdog);
1691 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1692 u32 speed;
1693
1694 netif_printk(nic, timer, KERN_DEBUG, nic->netdev,
1695 "right now = %ld\n", jiffies);
1696
1697 /* mii library handles link maintenance tasks */
1698
1699 mii_ethtool_gset(&nic->mii, &cmd);
1700 speed = ethtool_cmd_speed(&cmd);
1701
1702 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1703 netdev_info(nic->netdev, "NIC Link is Up %u Mbps %s Duplex\n",
1704 speed == SPEED_100 ? 100 : 10,
1705 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1706 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1707 netdev_info(nic->netdev, "NIC Link is Down\n");
1708 }
1709
1710 mii_check_link(&nic->mii);
1711
1712 /* Software generated interrupt to recover from (rare) Rx
1713 * allocation failure.
1714 * Unfortunately have to use a spinlock to not re-enable interrupts
1715 * accidentally, due to hardware that shares a register between the
1716 * interrupt mask bit and the SW Interrupt generation bit */
1717 spin_lock_irq(&nic->cmd_lock);
1718 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1719 e100_write_flush(nic);
1720 spin_unlock_irq(&nic->cmd_lock);
1721
1722 e100_update_stats(nic);
1723 e100_adjust_adaptive_ifs(nic, speed, cmd.duplex);
1724
1725 if (nic->mac <= mac_82557_D100_C)
1726 /* Issue a multicast command to workaround a 557 lock up */
1727 e100_set_multicast_list(nic->netdev);
1728
1729 if (nic->flags & ich && speed == SPEED_10 && cmd.duplex == DUPLEX_HALF)
1730 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1731 nic->flags |= ich_10h_workaround;
1732 else
1733 nic->flags &= ~ich_10h_workaround;
1734
1735 mod_timer(&nic->watchdog,
1736 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1737}
1738
1739static int e100_xmit_prepare(struct nic *nic, struct cb *cb,
1740 struct sk_buff *skb)
1741{
1742 dma_addr_t dma_addr;
1743 cb->command = nic->tx_command;
1744
1745 dma_addr = pci_map_single(nic->pdev,
1746 skb->data, skb->len, PCI_DMA_TODEVICE);
1747 /* If we can't map the skb, have the upper layer try later */
1748 if (pci_dma_mapping_error(nic->pdev, dma_addr)) {
1749 dev_kfree_skb_any(skb);
1750 skb = NULL;
1751 return -ENOMEM;
1752 }
1753
1754 /*
1755 * Use the last 4 bytes of the SKB payload packet as the CRC, used for
1756 * testing, ie sending frames with bad CRC.
1757 */
1758 if (unlikely(skb->no_fcs))
1759 cb->command |= cpu_to_le16(cb_tx_nc);
1760 else
1761 cb->command &= ~cpu_to_le16(cb_tx_nc);
1762
1763 /* interrupt every 16 packets regardless of delay */
1764 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
1765 cb->command |= cpu_to_le16(cb_i);
1766 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1767 cb->u.tcb.tcb_byte_count = 0;
1768 cb->u.tcb.threshold = nic->tx_threshold;
1769 cb->u.tcb.tbd_count = 1;
1770 cb->u.tcb.tbd.buf_addr = cpu_to_le32(dma_addr);
1771 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1772 skb_tx_timestamp(skb);
1773 return 0;
1774}
1775
1776static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1777 struct net_device *netdev)
1778{
1779 struct nic *nic = netdev_priv(netdev);
1780 int err;
1781
1782 if (nic->flags & ich_10h_workaround) {
1783 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1784 Issue a NOP command followed by a 1us delay before
1785 issuing the Tx command. */
1786 if (e100_exec_cmd(nic, cuc_nop, 0))
1787 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1788 "exec cuc_nop failed\n");
1789 udelay(1);
1790 }
1791
1792 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1793
1794 switch (err) {
1795 case -ENOSPC:
1796 /* We queued the skb, but now we're out of space. */
1797 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1798 "No space for CB\n");
1799 netif_stop_queue(netdev);
1800 break;
1801 case -ENOMEM:
1802 /* This is a hard error - log it. */
1803 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1804 "Out of Tx resources, returning skb\n");
1805 netif_stop_queue(netdev);
1806 return NETDEV_TX_BUSY;
1807 }
1808
1809 return NETDEV_TX_OK;
1810}
1811
1812static int e100_tx_clean(struct nic *nic)
1813{
1814 struct net_device *dev = nic->netdev;
1815 struct cb *cb;
1816 int tx_cleaned = 0;
1817
1818 spin_lock(&nic->cb_lock);
1819
1820 /* Clean CBs marked complete */
1821 for (cb = nic->cb_to_clean;
1822 cb->status & cpu_to_le16(cb_complete);
1823 cb = nic->cb_to_clean = cb->next) {
1824 dma_rmb(); /* read skb after status */
1825 netif_printk(nic, tx_done, KERN_DEBUG, nic->netdev,
1826 "cb[%d]->status = 0x%04X\n",
1827 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1828 cb->status);
1829
1830 if (likely(cb->skb != NULL)) {
1831 dev->stats.tx_packets++;
1832 dev->stats.tx_bytes += cb->skb->len;
1833
1834 pci_unmap_single(nic->pdev,
1835 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1836 le16_to_cpu(cb->u.tcb.tbd.size),
1837 PCI_DMA_TODEVICE);
1838 dev_kfree_skb_any(cb->skb);
1839 cb->skb = NULL;
1840 tx_cleaned = 1;
1841 }
1842 cb->status = 0;
1843 nic->cbs_avail++;
1844 }
1845
1846 spin_unlock(&nic->cb_lock);
1847
1848 /* Recover from running out of Tx resources in xmit_frame */
1849 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1850 netif_wake_queue(nic->netdev);
1851
1852 return tx_cleaned;
1853}
1854
1855static void e100_clean_cbs(struct nic *nic)
1856{
1857 if (nic->cbs) {
1858 while (nic->cbs_avail != nic->params.cbs.count) {
1859 struct cb *cb = nic->cb_to_clean;
1860 if (cb->skb) {
1861 pci_unmap_single(nic->pdev,
1862 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1863 le16_to_cpu(cb->u.tcb.tbd.size),
1864 PCI_DMA_TODEVICE);
1865 dev_kfree_skb(cb->skb);
1866 }
1867 nic->cb_to_clean = nic->cb_to_clean->next;
1868 nic->cbs_avail++;
1869 }
1870 dma_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
1871 nic->cbs = NULL;
1872 nic->cbs_avail = 0;
1873 }
1874 nic->cuc_cmd = cuc_start;
1875 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1876 nic->cbs;
1877}
1878
1879static int e100_alloc_cbs(struct nic *nic)
1880{
1881 struct cb *cb;
1882 unsigned int i, count = nic->params.cbs.count;
1883
1884 nic->cuc_cmd = cuc_start;
1885 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1886 nic->cbs_avail = 0;
1887
1888 nic->cbs = dma_pool_zalloc(nic->cbs_pool, GFP_KERNEL,
1889 &nic->cbs_dma_addr);
1890 if (!nic->cbs)
1891 return -ENOMEM;
1892
1893 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1894 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1895 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1896
1897 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1898 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1899 ((i+1) % count) * sizeof(struct cb));
1900 }
1901
1902 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1903 nic->cbs_avail = count;
1904
1905 return 0;
1906}
1907
1908static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1909{
1910 if (!nic->rxs) return;
1911 if (RU_SUSPENDED != nic->ru_running) return;
1912
1913 /* handle init time starts */
1914 if (!rx) rx = nic->rxs;
1915
1916 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1917 if (rx->skb) {
1918 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1919 nic->ru_running = RU_RUNNING;
1920 }
1921}
1922
1923#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
1924static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1925{
1926 if (!(rx->skb = netdev_alloc_skb_ip_align(nic->netdev, RFD_BUF_LEN)))
1927 return -ENOMEM;
1928
1929 /* Init, and map the RFD. */
1930 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1931 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1932 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1933
1934 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1935 dev_kfree_skb_any(rx->skb);
1936 rx->skb = NULL;
1937 rx->dma_addr = 0;
1938 return -ENOMEM;
1939 }
1940
1941 /* Link the RFD to end of RFA by linking previous RFD to
1942 * this one. We are safe to touch the previous RFD because
1943 * it is protected by the before last buffer's el bit being set */
1944 if (rx->prev->skb) {
1945 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1946 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1947 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1948 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1949 }
1950
1951 return 0;
1952}
1953
1954static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1955 unsigned int *work_done, unsigned int work_to_do)
1956{
1957 struct net_device *dev = nic->netdev;
1958 struct sk_buff *skb = rx->skb;
1959 struct rfd *rfd = (struct rfd *)skb->data;
1960 u16 rfd_status, actual_size;
1961 u16 fcs_pad = 0;
1962
1963 if (unlikely(work_done && *work_done >= work_to_do))
1964 return -EAGAIN;
1965
1966 /* Need to sync before taking a peek at cb_complete bit */
1967 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1968 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1969 rfd_status = le16_to_cpu(rfd->status);
1970
1971 netif_printk(nic, rx_status, KERN_DEBUG, nic->netdev,
1972 "status=0x%04X\n", rfd_status);
1973 dma_rmb(); /* read size after status bit */
1974
1975 /* If data isn't ready, nothing to indicate */
1976 if (unlikely(!(rfd_status & cb_complete))) {
1977 /* If the next buffer has the el bit, but we think the receiver
1978 * is still running, check to see if it really stopped while
1979 * we had interrupts off.
1980 * This allows for a fast restart without re-enabling
1981 * interrupts */
1982 if ((le16_to_cpu(rfd->command) & cb_el) &&
1983 (RU_RUNNING == nic->ru_running))
1984
1985 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1986 nic->ru_running = RU_SUSPENDED;
1987 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1988 sizeof(struct rfd),
1989 PCI_DMA_FROMDEVICE);
1990 return -ENODATA;
1991 }
1992
1993 /* Get actual data size */
1994 if (unlikely(dev->features & NETIF_F_RXFCS))
1995 fcs_pad = 4;
1996 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1997 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1998 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1999
2000 /* Get data */
2001 pci_unmap_single(nic->pdev, rx->dma_addr,
2002 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2003
2004 /* If this buffer has the el bit, but we think the receiver
2005 * is still running, check to see if it really stopped while
2006 * we had interrupts off.
2007 * This allows for a fast restart without re-enabling interrupts.
2008 * This can happen when the RU sees the size change but also sees
2009 * the el bit set. */
2010 if ((le16_to_cpu(rfd->command) & cb_el) &&
2011 (RU_RUNNING == nic->ru_running)) {
2012
2013 if (ioread8(&nic->csr->scb.status) & rus_no_res)
2014 nic->ru_running = RU_SUSPENDED;
2015 }
2016
2017 /* Pull off the RFD and put the actual data (minus eth hdr) */
2018 skb_reserve(skb, sizeof(struct rfd));
2019 skb_put(skb, actual_size);
2020 skb->protocol = eth_type_trans(skb, nic->netdev);
2021
2022 /* If we are receiving all frames, then don't bother
2023 * checking for errors.
2024 */
2025 if (unlikely(dev->features & NETIF_F_RXALL)) {
2026 if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad)
2027 /* Received oversized frame, but keep it. */
2028 nic->rx_over_length_errors++;
2029 goto process_skb;
2030 }
2031
2032 if (unlikely(!(rfd_status & cb_ok))) {
2033 /* Don't indicate if hardware indicates errors */
2034 dev_kfree_skb_any(skb);
2035 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN + fcs_pad) {
2036 /* Don't indicate oversized frames */
2037 nic->rx_over_length_errors++;
2038 dev_kfree_skb_any(skb);
2039 } else {
2040process_skb:
2041 dev->stats.rx_packets++;
2042 dev->stats.rx_bytes += (actual_size - fcs_pad);
2043 netif_receive_skb(skb);
2044 if (work_done)
2045 (*work_done)++;
2046 }
2047
2048 rx->skb = NULL;
2049
2050 return 0;
2051}
2052
2053static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
2054 unsigned int work_to_do)
2055{
2056 struct rx *rx;
2057 int restart_required = 0, err = 0;
2058 struct rx *old_before_last_rx, *new_before_last_rx;
2059 struct rfd *old_before_last_rfd, *new_before_last_rfd;
2060
2061 /* Indicate newly arrived packets */
2062 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
2063 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
2064 /* Hit quota or no more to clean */
2065 if (-EAGAIN == err || -ENODATA == err)
2066 break;
2067 }
2068
2069
2070 /* On EAGAIN, hit quota so have more work to do, restart once
2071 * cleanup is complete.
2072 * Else, are we already rnr? then pay attention!!! this ensures that
2073 * the state machine progression never allows a start with a
2074 * partially cleaned list, avoiding a race between hardware
2075 * and rx_to_clean when in NAPI mode */
2076 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
2077 restart_required = 1;
2078
2079 old_before_last_rx = nic->rx_to_use->prev->prev;
2080 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
2081
2082 /* Alloc new skbs to refill list */
2083 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
2084 if (unlikely(e100_rx_alloc_skb(nic, rx)))
2085 break; /* Better luck next time (see watchdog) */
2086 }
2087
2088 new_before_last_rx = nic->rx_to_use->prev->prev;
2089 if (new_before_last_rx != old_before_last_rx) {
2090 /* Set the el-bit on the buffer that is before the last buffer.
2091 * This lets us update the next pointer on the last buffer
2092 * without worrying about hardware touching it.
2093 * We set the size to 0 to prevent hardware from touching this
2094 * buffer.
2095 * When the hardware hits the before last buffer with el-bit
2096 * and size of 0, it will RNR interrupt, the RUS will go into
2097 * the No Resources state. It will not complete nor write to
2098 * this buffer. */
2099 new_before_last_rfd =
2100 (struct rfd *)new_before_last_rx->skb->data;
2101 new_before_last_rfd->size = 0;
2102 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2103 pci_dma_sync_single_for_device(nic->pdev,
2104 new_before_last_rx->dma_addr, sizeof(struct rfd),
2105 PCI_DMA_BIDIRECTIONAL);
2106
2107 /* Now that we have a new stopping point, we can clear the old
2108 * stopping point. We must sync twice to get the proper
2109 * ordering on the hardware side of things. */
2110 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2111 pci_dma_sync_single_for_device(nic->pdev,
2112 old_before_last_rx->dma_addr, sizeof(struct rfd),
2113 PCI_DMA_BIDIRECTIONAL);
2114 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN
2115 + ETH_FCS_LEN);
2116 pci_dma_sync_single_for_device(nic->pdev,
2117 old_before_last_rx->dma_addr, sizeof(struct rfd),
2118 PCI_DMA_BIDIRECTIONAL);
2119 }
2120
2121 if (restart_required) {
2122 // ack the rnr?
2123 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
2124 e100_start_receiver(nic, nic->rx_to_clean);
2125 if (work_done)
2126 (*work_done)++;
2127 }
2128}
2129
2130static void e100_rx_clean_list(struct nic *nic)
2131{
2132 struct rx *rx;
2133 unsigned int i, count = nic->params.rfds.count;
2134
2135 nic->ru_running = RU_UNINITIALIZED;
2136
2137 if (nic->rxs) {
2138 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2139 if (rx->skb) {
2140 pci_unmap_single(nic->pdev, rx->dma_addr,
2141 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2142 dev_kfree_skb(rx->skb);
2143 }
2144 }
2145 kfree(nic->rxs);
2146 nic->rxs = NULL;
2147 }
2148
2149 nic->rx_to_use = nic->rx_to_clean = NULL;
2150}
2151
2152static int e100_rx_alloc_list(struct nic *nic)
2153{
2154 struct rx *rx;
2155 unsigned int i, count = nic->params.rfds.count;
2156 struct rfd *before_last;
2157
2158 nic->rx_to_use = nic->rx_to_clean = NULL;
2159 nic->ru_running = RU_UNINITIALIZED;
2160
2161 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
2162 return -ENOMEM;
2163
2164 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2165 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2166 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
2167 if (e100_rx_alloc_skb(nic, rx)) {
2168 e100_rx_clean_list(nic);
2169 return -ENOMEM;
2170 }
2171 }
2172 /* Set the el-bit on the buffer that is before the last buffer.
2173 * This lets us update the next pointer on the last buffer without
2174 * worrying about hardware touching it.
2175 * We set the size to 0 to prevent hardware from touching this buffer.
2176 * When the hardware hits the before last buffer with el-bit and size
2177 * of 0, it will RNR interrupt, the RU will go into the No Resources
2178 * state. It will not complete nor write to this buffer. */
2179 rx = nic->rxs->prev->prev;
2180 before_last = (struct rfd *)rx->skb->data;
2181 before_last->command |= cpu_to_le16(cb_el);
2182 before_last->size = 0;
2183 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
2184 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
2185
2186 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
2187 nic->ru_running = RU_SUSPENDED;
2188
2189 return 0;
2190}
2191
2192static irqreturn_t e100_intr(int irq, void *dev_id)
2193{
2194 struct net_device *netdev = dev_id;
2195 struct nic *nic = netdev_priv(netdev);
2196 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
2197
2198 netif_printk(nic, intr, KERN_DEBUG, nic->netdev,
2199 "stat_ack = 0x%02X\n", stat_ack);
2200
2201 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
2202 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2203 return IRQ_NONE;
2204
2205 /* Ack interrupt(s) */
2206 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
2207
2208 /* We hit Receive No Resource (RNR); restart RU after cleaning */
2209 if (stat_ack & stat_ack_rnr)
2210 nic->ru_running = RU_SUSPENDED;
2211
2212 if (likely(napi_schedule_prep(&nic->napi))) {
2213 e100_disable_irq(nic);
2214 __napi_schedule(&nic->napi);
2215 }
2216
2217 return IRQ_HANDLED;
2218}
2219
2220static int e100_poll(struct napi_struct *napi, int budget)
2221{
2222 struct nic *nic = container_of(napi, struct nic, napi);
2223 unsigned int work_done = 0;
2224
2225 e100_rx_clean(nic, &work_done, budget);
2226 e100_tx_clean(nic);
2227
2228 /* If budget fully consumed, continue polling */
2229 if (work_done == budget)
2230 return budget;
2231
2232 /* only re-enable interrupt if stack agrees polling is really done */
2233 if (likely(napi_complete_done(napi, work_done)))
2234 e100_enable_irq(nic);
2235
2236 return work_done;
2237}
2238
2239#ifdef CONFIG_NET_POLL_CONTROLLER
2240static void e100_netpoll(struct net_device *netdev)
2241{
2242 struct nic *nic = netdev_priv(netdev);
2243
2244 e100_disable_irq(nic);
2245 e100_intr(nic->pdev->irq, netdev);
2246 e100_tx_clean(nic);
2247 e100_enable_irq(nic);
2248}
2249#endif
2250
2251static int e100_set_mac_address(struct net_device *netdev, void *p)
2252{
2253 struct nic *nic = netdev_priv(netdev);
2254 struct sockaddr *addr = p;
2255
2256 if (!is_valid_ether_addr(addr->sa_data))
2257 return -EADDRNOTAVAIL;
2258
2259 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2260 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2261
2262 return 0;
2263}
2264
2265static int e100_asf(struct nic *nic)
2266{
2267 /* ASF can be enabled from eeprom */
2268 return (nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2269 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2270 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2271 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE);
2272}
2273
2274static int e100_up(struct nic *nic)
2275{
2276 int err;
2277
2278 if ((err = e100_rx_alloc_list(nic)))
2279 return err;
2280 if ((err = e100_alloc_cbs(nic)))
2281 goto err_rx_clean_list;
2282 if ((err = e100_hw_init(nic)))
2283 goto err_clean_cbs;
2284 e100_set_multicast_list(nic->netdev);
2285 e100_start_receiver(nic, NULL);
2286 mod_timer(&nic->watchdog, jiffies);
2287 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2288 nic->netdev->name, nic->netdev)))
2289 goto err_no_irq;
2290 netif_wake_queue(nic->netdev);
2291 napi_enable(&nic->napi);
2292 /* enable ints _after_ enabling poll, preventing a race between
2293 * disable ints+schedule */
2294 e100_enable_irq(nic);
2295 return 0;
2296
2297err_no_irq:
2298 del_timer_sync(&nic->watchdog);
2299err_clean_cbs:
2300 e100_clean_cbs(nic);
2301err_rx_clean_list:
2302 e100_rx_clean_list(nic);
2303 return err;
2304}
2305
2306static void e100_down(struct nic *nic)
2307{
2308 /* wait here for poll to complete */
2309 napi_disable(&nic->napi);
2310 netif_stop_queue(nic->netdev);
2311 e100_hw_reset(nic);
2312 free_irq(nic->pdev->irq, nic->netdev);
2313 del_timer_sync(&nic->watchdog);
2314 netif_carrier_off(nic->netdev);
2315 e100_clean_cbs(nic);
2316 e100_rx_clean_list(nic);
2317}
2318
2319static void e100_tx_timeout(struct net_device *netdev)
2320{
2321 struct nic *nic = netdev_priv(netdev);
2322
2323 /* Reset outside of interrupt context, to avoid request_irq
2324 * in interrupt context */
2325 schedule_work(&nic->tx_timeout_task);
2326}
2327
2328static void e100_tx_timeout_task(struct work_struct *work)
2329{
2330 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2331 struct net_device *netdev = nic->netdev;
2332
2333 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
2334 "scb.status=0x%02X\n", ioread8(&nic->csr->scb.status));
2335
2336 rtnl_lock();
2337 if (netif_running(netdev)) {
2338 e100_down(netdev_priv(netdev));
2339 e100_up(netdev_priv(netdev));
2340 }
2341 rtnl_unlock();
2342}
2343
2344static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2345{
2346 int err;
2347 struct sk_buff *skb;
2348
2349 /* Use driver resources to perform internal MAC or PHY
2350 * loopback test. A single packet is prepared and transmitted
2351 * in loopback mode, and the test passes if the received
2352 * packet compares byte-for-byte to the transmitted packet. */
2353
2354 if ((err = e100_rx_alloc_list(nic)))
2355 return err;
2356 if ((err = e100_alloc_cbs(nic)))
2357 goto err_clean_rx;
2358
2359 /* ICH PHY loopback is broken so do MAC loopback instead */
2360 if (nic->flags & ich && loopback_mode == lb_phy)
2361 loopback_mode = lb_mac;
2362
2363 nic->loopback = loopback_mode;
2364 if ((err = e100_hw_init(nic)))
2365 goto err_loopback_none;
2366
2367 if (loopback_mode == lb_phy)
2368 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2369 BMCR_LOOPBACK);
2370
2371 e100_start_receiver(nic, NULL);
2372
2373 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2374 err = -ENOMEM;
2375 goto err_loopback_none;
2376 }
2377 skb_put(skb, ETH_DATA_LEN);
2378 memset(skb->data, 0xFF, ETH_DATA_LEN);
2379 e100_xmit_frame(skb, nic->netdev);
2380
2381 msleep(10);
2382
2383 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2384 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2385
2386 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2387 skb->data, ETH_DATA_LEN))
2388 err = -EAGAIN;
2389
2390err_loopback_none:
2391 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2392 nic->loopback = lb_none;
2393 e100_clean_cbs(nic);
2394 e100_hw_reset(nic);
2395err_clean_rx:
2396 e100_rx_clean_list(nic);
2397 return err;
2398}
2399
2400#define MII_LED_CONTROL 0x1B
2401#define E100_82552_LED_OVERRIDE 0x19
2402#define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2403#define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
2404
2405static int e100_get_link_ksettings(struct net_device *netdev,
2406 struct ethtool_link_ksettings *cmd)
2407{
2408 struct nic *nic = netdev_priv(netdev);
2409
2410 mii_ethtool_get_link_ksettings(&nic->mii, cmd);
2411
2412 return 0;
2413}
2414
2415static int e100_set_link_ksettings(struct net_device *netdev,
2416 const struct ethtool_link_ksettings *cmd)
2417{
2418 struct nic *nic = netdev_priv(netdev);
2419 int err;
2420
2421 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2422 err = mii_ethtool_set_link_ksettings(&nic->mii, cmd);
2423 e100_exec_cb(nic, NULL, e100_configure);
2424
2425 return err;
2426}
2427
2428static void e100_get_drvinfo(struct net_device *netdev,
2429 struct ethtool_drvinfo *info)
2430{
2431 struct nic *nic = netdev_priv(netdev);
2432 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2433 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2434 strlcpy(info->bus_info, pci_name(nic->pdev),
2435 sizeof(info->bus_info));
2436}
2437
2438#define E100_PHY_REGS 0x1C
2439static int e100_get_regs_len(struct net_device *netdev)
2440{
2441 struct nic *nic = netdev_priv(netdev);
2442 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
2443}
2444
2445static void e100_get_regs(struct net_device *netdev,
2446 struct ethtool_regs *regs, void *p)
2447{
2448 struct nic *nic = netdev_priv(netdev);
2449 u32 *buff = p;
2450 int i;
2451
2452 regs->version = (1 << 24) | nic->pdev->revision;
2453 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2454 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2455 ioread16(&nic->csr->scb.status);
2456 for (i = E100_PHY_REGS; i >= 0; i--)
2457 buff[1 + E100_PHY_REGS - i] =
2458 mdio_read(netdev, nic->mii.phy_id, i);
2459 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2460 e100_exec_cb(nic, NULL, e100_dump);
2461 msleep(10);
2462 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2463 sizeof(nic->mem->dump_buf));
2464}
2465
2466static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2467{
2468 struct nic *nic = netdev_priv(netdev);
2469 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2470 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2471}
2472
2473static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2474{
2475 struct nic *nic = netdev_priv(netdev);
2476
2477 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2478 !device_can_wakeup(&nic->pdev->dev))
2479 return -EOPNOTSUPP;
2480
2481 if (wol->wolopts)
2482 nic->flags |= wol_magic;
2483 else
2484 nic->flags &= ~wol_magic;
2485
2486 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2487
2488 e100_exec_cb(nic, NULL, e100_configure);
2489
2490 return 0;
2491}
2492
2493static u32 e100_get_msglevel(struct net_device *netdev)
2494{
2495 struct nic *nic = netdev_priv(netdev);
2496 return nic->msg_enable;
2497}
2498
2499static void e100_set_msglevel(struct net_device *netdev, u32 value)
2500{
2501 struct nic *nic = netdev_priv(netdev);
2502 nic->msg_enable = value;
2503}
2504
2505static int e100_nway_reset(struct net_device *netdev)
2506{
2507 struct nic *nic = netdev_priv(netdev);
2508 return mii_nway_restart(&nic->mii);
2509}
2510
2511static u32 e100_get_link(struct net_device *netdev)
2512{
2513 struct nic *nic = netdev_priv(netdev);
2514 return mii_link_ok(&nic->mii);
2515}
2516
2517static int e100_get_eeprom_len(struct net_device *netdev)
2518{
2519 struct nic *nic = netdev_priv(netdev);
2520 return nic->eeprom_wc << 1;
2521}
2522
2523#define E100_EEPROM_MAGIC 0x1234
2524static int e100_get_eeprom(struct net_device *netdev,
2525 struct ethtool_eeprom *eeprom, u8 *bytes)
2526{
2527 struct nic *nic = netdev_priv(netdev);
2528
2529 eeprom->magic = E100_EEPROM_MAGIC;
2530 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2531
2532 return 0;
2533}
2534
2535static int e100_set_eeprom(struct net_device *netdev,
2536 struct ethtool_eeprom *eeprom, u8 *bytes)
2537{
2538 struct nic *nic = netdev_priv(netdev);
2539
2540 if (eeprom->magic != E100_EEPROM_MAGIC)
2541 return -EINVAL;
2542
2543 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2544
2545 return e100_eeprom_save(nic, eeprom->offset >> 1,
2546 (eeprom->len >> 1) + 1);
2547}
2548
2549static void e100_get_ringparam(struct net_device *netdev,
2550 struct ethtool_ringparam *ring)
2551{
2552 struct nic *nic = netdev_priv(netdev);
2553 struct param_range *rfds = &nic->params.rfds;
2554 struct param_range *cbs = &nic->params.cbs;
2555
2556 ring->rx_max_pending = rfds->max;
2557 ring->tx_max_pending = cbs->max;
2558 ring->rx_pending = rfds->count;
2559 ring->tx_pending = cbs->count;
2560}
2561
2562static int e100_set_ringparam(struct net_device *netdev,
2563 struct ethtool_ringparam *ring)
2564{
2565 struct nic *nic = netdev_priv(netdev);
2566 struct param_range *rfds = &nic->params.rfds;
2567 struct param_range *cbs = &nic->params.cbs;
2568
2569 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2570 return -EINVAL;
2571
2572 if (netif_running(netdev))
2573 e100_down(nic);
2574 rfds->count = max(ring->rx_pending, rfds->min);
2575 rfds->count = min(rfds->count, rfds->max);
2576 cbs->count = max(ring->tx_pending, cbs->min);
2577 cbs->count = min(cbs->count, cbs->max);
2578 netif_info(nic, drv, nic->netdev, "Ring Param settings: rx: %d, tx %d\n",
2579 rfds->count, cbs->count);
2580 if (netif_running(netdev))
2581 e100_up(nic);
2582
2583 return 0;
2584}
2585
2586static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2587 "Link test (on/offline)",
2588 "Eeprom test (on/offline)",
2589 "Self test (offline)",
2590 "Mac loopback (offline)",
2591 "Phy loopback (offline)",
2592};
2593#define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2594
2595static void e100_diag_test(struct net_device *netdev,
2596 struct ethtool_test *test, u64 *data)
2597{
2598 struct ethtool_cmd cmd;
2599 struct nic *nic = netdev_priv(netdev);
2600 int i, err;
2601
2602 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2603 data[0] = !mii_link_ok(&nic->mii);
2604 data[1] = e100_eeprom_load(nic);
2605 if (test->flags & ETH_TEST_FL_OFFLINE) {
2606
2607 /* save speed, duplex & autoneg settings */
2608 err = mii_ethtool_gset(&nic->mii, &cmd);
2609
2610 if (netif_running(netdev))
2611 e100_down(nic);
2612 data[2] = e100_self_test(nic);
2613 data[3] = e100_loopback_test(nic, lb_mac);
2614 data[4] = e100_loopback_test(nic, lb_phy);
2615
2616 /* restore speed, duplex & autoneg settings */
2617 err = mii_ethtool_sset(&nic->mii, &cmd);
2618
2619 if (netif_running(netdev))
2620 e100_up(nic);
2621 }
2622 for (i = 0; i < E100_TEST_LEN; i++)
2623 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2624
2625 msleep_interruptible(4 * 1000);
2626}
2627
2628static int e100_set_phys_id(struct net_device *netdev,
2629 enum ethtool_phys_id_state state)
2630{
2631 struct nic *nic = netdev_priv(netdev);
2632 enum led_state {
2633 led_on = 0x01,
2634 led_off = 0x04,
2635 led_on_559 = 0x05,
2636 led_on_557 = 0x07,
2637 };
2638 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2639 MII_LED_CONTROL;
2640 u16 leds = 0;
2641
2642 switch (state) {
2643 case ETHTOOL_ID_ACTIVE:
2644 return 2;
2645
2646 case ETHTOOL_ID_ON:
2647 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_ON :
2648 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
2649 break;
2650
2651 case ETHTOOL_ID_OFF:
2652 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_OFF : led_off;
2653 break;
2654
2655 case ETHTOOL_ID_INACTIVE:
2656 break;
2657 }
2658
2659 mdio_write(netdev, nic->mii.phy_id, led_reg, leds);
2660 return 0;
2661}
2662
2663static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2664 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2665 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2666 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2667 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2668 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2669 "tx_heartbeat_errors", "tx_window_errors",
2670 /* device-specific stats */
2671 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2672 "tx_flow_control_pause", "rx_flow_control_pause",
2673 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2674 "rx_short_frame_errors", "rx_over_length_errors",
2675};
2676#define E100_NET_STATS_LEN 21
2677#define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2678
2679static int e100_get_sset_count(struct net_device *netdev, int sset)
2680{
2681 switch (sset) {
2682 case ETH_SS_TEST:
2683 return E100_TEST_LEN;
2684 case ETH_SS_STATS:
2685 return E100_STATS_LEN;
2686 default:
2687 return -EOPNOTSUPP;
2688 }
2689}
2690
2691static void e100_get_ethtool_stats(struct net_device *netdev,
2692 struct ethtool_stats *stats, u64 *data)
2693{
2694 struct nic *nic = netdev_priv(netdev);
2695 int i;
2696
2697 for (i = 0; i < E100_NET_STATS_LEN; i++)
2698 data[i] = ((unsigned long *)&netdev->stats)[i];
2699
2700 data[i++] = nic->tx_deferred;
2701 data[i++] = nic->tx_single_collisions;
2702 data[i++] = nic->tx_multiple_collisions;
2703 data[i++] = nic->tx_fc_pause;
2704 data[i++] = nic->rx_fc_pause;
2705 data[i++] = nic->rx_fc_unsupported;
2706 data[i++] = nic->tx_tco_frames;
2707 data[i++] = nic->rx_tco_frames;
2708 data[i++] = nic->rx_short_frame_errors;
2709 data[i++] = nic->rx_over_length_errors;
2710}
2711
2712static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2713{
2714 switch (stringset) {
2715 case ETH_SS_TEST:
2716 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2717 break;
2718 case ETH_SS_STATS:
2719 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2720 break;
2721 }
2722}
2723
2724static const struct ethtool_ops e100_ethtool_ops = {
2725 .get_drvinfo = e100_get_drvinfo,
2726 .get_regs_len = e100_get_regs_len,
2727 .get_regs = e100_get_regs,
2728 .get_wol = e100_get_wol,
2729 .set_wol = e100_set_wol,
2730 .get_msglevel = e100_get_msglevel,
2731 .set_msglevel = e100_set_msglevel,
2732 .nway_reset = e100_nway_reset,
2733 .get_link = e100_get_link,
2734 .get_eeprom_len = e100_get_eeprom_len,
2735 .get_eeprom = e100_get_eeprom,
2736 .set_eeprom = e100_set_eeprom,
2737 .get_ringparam = e100_get_ringparam,
2738 .set_ringparam = e100_set_ringparam,
2739 .self_test = e100_diag_test,
2740 .get_strings = e100_get_strings,
2741 .set_phys_id = e100_set_phys_id,
2742 .get_ethtool_stats = e100_get_ethtool_stats,
2743 .get_sset_count = e100_get_sset_count,
2744 .get_ts_info = ethtool_op_get_ts_info,
2745 .get_link_ksettings = e100_get_link_ksettings,
2746 .set_link_ksettings = e100_set_link_ksettings,
2747};
2748
2749static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2750{
2751 struct nic *nic = netdev_priv(netdev);
2752
2753 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2754}
2755
2756static int e100_alloc(struct nic *nic)
2757{
2758 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2759 &nic->dma_addr);
2760 return nic->mem ? 0 : -ENOMEM;
2761}
2762
2763static void e100_free(struct nic *nic)
2764{
2765 if (nic->mem) {
2766 pci_free_consistent(nic->pdev, sizeof(struct mem),
2767 nic->mem, nic->dma_addr);
2768 nic->mem = NULL;
2769 }
2770}
2771
2772static int e100_open(struct net_device *netdev)
2773{
2774 struct nic *nic = netdev_priv(netdev);
2775 int err = 0;
2776
2777 netif_carrier_off(netdev);
2778 if ((err = e100_up(nic)))
2779 netif_err(nic, ifup, nic->netdev, "Cannot open interface, aborting\n");
2780 return err;
2781}
2782
2783static int e100_close(struct net_device *netdev)
2784{
2785 e100_down(netdev_priv(netdev));
2786 return 0;
2787}
2788
2789static int e100_set_features(struct net_device *netdev,
2790 netdev_features_t features)
2791{
2792 struct nic *nic = netdev_priv(netdev);
2793 netdev_features_t changed = features ^ netdev->features;
2794
2795 if (!(changed & (NETIF_F_RXFCS | NETIF_F_RXALL)))
2796 return 0;
2797
2798 netdev->features = features;
2799 e100_exec_cb(nic, NULL, e100_configure);
2800 return 1;
2801}
2802
2803static const struct net_device_ops e100_netdev_ops = {
2804 .ndo_open = e100_open,
2805 .ndo_stop = e100_close,
2806 .ndo_start_xmit = e100_xmit_frame,
2807 .ndo_validate_addr = eth_validate_addr,
2808 .ndo_set_rx_mode = e100_set_multicast_list,
2809 .ndo_set_mac_address = e100_set_mac_address,
2810 .ndo_do_ioctl = e100_do_ioctl,
2811 .ndo_tx_timeout = e100_tx_timeout,
2812#ifdef CONFIG_NET_POLL_CONTROLLER
2813 .ndo_poll_controller = e100_netpoll,
2814#endif
2815 .ndo_set_features = e100_set_features,
2816};
2817
2818static int e100_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2819{
2820 struct net_device *netdev;
2821 struct nic *nic;
2822 int err;
2823
2824 if (!(netdev = alloc_etherdev(sizeof(struct nic))))
2825 return -ENOMEM;
2826
2827 netdev->hw_features |= NETIF_F_RXFCS;
2828 netdev->priv_flags |= IFF_SUPP_NOFCS;
2829 netdev->hw_features |= NETIF_F_RXALL;
2830
2831 netdev->netdev_ops = &e100_netdev_ops;
2832 netdev->ethtool_ops = &e100_ethtool_ops;
2833 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2834 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2835
2836 nic = netdev_priv(netdev);
2837 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2838 nic->netdev = netdev;
2839 nic->pdev = pdev;
2840 nic->msg_enable = (1 << debug) - 1;
2841 nic->mdio_ctrl = mdio_ctrl_hw;
2842 pci_set_drvdata(pdev, netdev);
2843
2844 if ((err = pci_enable_device(pdev))) {
2845 netif_err(nic, probe, nic->netdev, "Cannot enable PCI device, aborting\n");
2846 goto err_out_free_dev;
2847 }
2848
2849 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2850 netif_err(nic, probe, nic->netdev, "Cannot find proper PCI device base address, aborting\n");
2851 err = -ENODEV;
2852 goto err_out_disable_pdev;
2853 }
2854
2855 if ((err = pci_request_regions(pdev, DRV_NAME))) {
2856 netif_err(nic, probe, nic->netdev, "Cannot obtain PCI resources, aborting\n");
2857 goto err_out_disable_pdev;
2858 }
2859
2860 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
2861 netif_err(nic, probe, nic->netdev, "No usable DMA configuration, aborting\n");
2862 goto err_out_free_res;
2863 }
2864
2865 SET_NETDEV_DEV(netdev, &pdev->dev);
2866
2867 if (use_io)
2868 netif_info(nic, probe, nic->netdev, "using i/o access mode\n");
2869
2870 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2871 if (!nic->csr) {
2872 netif_err(nic, probe, nic->netdev, "Cannot map device registers, aborting\n");
2873 err = -ENOMEM;
2874 goto err_out_free_res;
2875 }
2876
2877 if (ent->driver_data)
2878 nic->flags |= ich;
2879 else
2880 nic->flags &= ~ich;
2881
2882 e100_get_defaults(nic);
2883
2884 /* D100 MAC doesn't allow rx of vlan packets with normal MTU */
2885 if (nic->mac < mac_82558_D101_A4)
2886 netdev->features |= NETIF_F_VLAN_CHALLENGED;
2887
2888 /* locks must be initialized before calling hw_reset */
2889 spin_lock_init(&nic->cb_lock);
2890 spin_lock_init(&nic->cmd_lock);
2891 spin_lock_init(&nic->mdio_lock);
2892
2893 /* Reset the device before pci_set_master() in case device is in some
2894 * funky state and has an interrupt pending - hint: we don't have the
2895 * interrupt handler registered yet. */
2896 e100_hw_reset(nic);
2897
2898 pci_set_master(pdev);
2899
2900 timer_setup(&nic->watchdog, e100_watchdog, 0);
2901
2902 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2903
2904 if ((err = e100_alloc(nic))) {
2905 netif_err(nic, probe, nic->netdev, "Cannot alloc driver memory, aborting\n");
2906 goto err_out_iounmap;
2907 }
2908
2909 if ((err = e100_eeprom_load(nic)))
2910 goto err_out_free;
2911
2912 e100_phy_init(nic);
2913
2914 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2915 if (!is_valid_ether_addr(netdev->dev_addr)) {
2916 if (!eeprom_bad_csum_allow) {
2917 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, aborting\n");
2918 err = -EAGAIN;
2919 goto err_out_free;
2920 } else {
2921 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, you MUST configure one.\n");
2922 }
2923 }
2924
2925 /* Wol magic packet can be enabled from eeprom */
2926 if ((nic->mac >= mac_82558_D101_A4) &&
2927 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
2928 nic->flags |= wol_magic;
2929 device_set_wakeup_enable(&pdev->dev, true);
2930 }
2931
2932 /* ack any pending wake events, disable PME */
2933 pci_pme_active(pdev, false);
2934
2935 strcpy(netdev->name, "eth%d");
2936 if ((err = register_netdev(netdev))) {
2937 netif_err(nic, probe, nic->netdev, "Cannot register net device, aborting\n");
2938 goto err_out_free;
2939 }
2940 nic->cbs_pool = dma_pool_create(netdev->name,
2941 &nic->pdev->dev,
2942 nic->params.cbs.max * sizeof(struct cb),
2943 sizeof(u32),
2944 0);
2945 if (!nic->cbs_pool) {
2946 netif_err(nic, probe, nic->netdev, "Cannot create DMA pool, aborting\n");
2947 err = -ENOMEM;
2948 goto err_out_pool;
2949 }
2950 netif_info(nic, probe, nic->netdev,
2951 "addr 0x%llx, irq %d, MAC addr %pM\n",
2952 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2953 pdev->irq, netdev->dev_addr);
2954
2955 return 0;
2956
2957err_out_pool:
2958 unregister_netdev(netdev);
2959err_out_free:
2960 e100_free(nic);
2961err_out_iounmap:
2962 pci_iounmap(pdev, nic->csr);
2963err_out_free_res:
2964 pci_release_regions(pdev);
2965err_out_disable_pdev:
2966 pci_disable_device(pdev);
2967err_out_free_dev:
2968 free_netdev(netdev);
2969 return err;
2970}
2971
2972static void e100_remove(struct pci_dev *pdev)
2973{
2974 struct net_device *netdev = pci_get_drvdata(pdev);
2975
2976 if (netdev) {
2977 struct nic *nic = netdev_priv(netdev);
2978 unregister_netdev(netdev);
2979 e100_free(nic);
2980 pci_iounmap(pdev, nic->csr);
2981 dma_pool_destroy(nic->cbs_pool);
2982 free_netdev(netdev);
2983 pci_release_regions(pdev);
2984 pci_disable_device(pdev);
2985 }
2986}
2987
2988#define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2989#define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
2990#define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
2991static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
2992{
2993 struct net_device *netdev = pci_get_drvdata(pdev);
2994 struct nic *nic = netdev_priv(netdev);
2995
2996 if (netif_running(netdev))
2997 e100_down(nic);
2998 netif_device_detach(netdev);
2999
3000 pci_save_state(pdev);
3001
3002 if ((nic->flags & wol_magic) | e100_asf(nic)) {
3003 /* enable reverse auto-negotiation */
3004 if (nic->phy == phy_82552_v) {
3005 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
3006 E100_82552_SMARTSPEED);
3007
3008 mdio_write(netdev, nic->mii.phy_id,
3009 E100_82552_SMARTSPEED, smartspeed |
3010 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
3011 }
3012 *enable_wake = true;
3013 } else {
3014 *enable_wake = false;
3015 }
3016
3017 pci_clear_master(pdev);
3018}
3019
3020static int __e100_power_off(struct pci_dev *pdev, bool wake)
3021{
3022 if (wake)
3023 return pci_prepare_to_sleep(pdev);
3024
3025 pci_wake_from_d3(pdev, false);
3026 pci_set_power_state(pdev, PCI_D3hot);
3027
3028 return 0;
3029}
3030
3031#ifdef CONFIG_PM
3032static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
3033{
3034 bool wake;
3035 __e100_shutdown(pdev, &wake);
3036 return __e100_power_off(pdev, wake);
3037}
3038
3039static int e100_resume(struct pci_dev *pdev)
3040{
3041 struct net_device *netdev = pci_get_drvdata(pdev);
3042 struct nic *nic = netdev_priv(netdev);
3043
3044 pci_set_power_state(pdev, PCI_D0);
3045 pci_restore_state(pdev);
3046 /* ack any pending wake events, disable PME */
3047 pci_enable_wake(pdev, PCI_D0, 0);
3048
3049 /* disable reverse auto-negotiation */
3050 if (nic->phy == phy_82552_v) {
3051 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
3052 E100_82552_SMARTSPEED);
3053
3054 mdio_write(netdev, nic->mii.phy_id,
3055 E100_82552_SMARTSPEED,
3056 smartspeed & ~(E100_82552_REV_ANEG));
3057 }
3058
3059 netif_device_attach(netdev);
3060 if (netif_running(netdev))
3061 e100_up(nic);
3062
3063 return 0;
3064}
3065#endif /* CONFIG_PM */
3066
3067static void e100_shutdown(struct pci_dev *pdev)
3068{
3069 bool wake;
3070 __e100_shutdown(pdev, &wake);
3071 if (system_state == SYSTEM_POWER_OFF)
3072 __e100_power_off(pdev, wake);
3073}
3074
3075/* ------------------ PCI Error Recovery infrastructure -------------- */
3076/**
3077 * e100_io_error_detected - called when PCI error is detected.
3078 * @pdev: Pointer to PCI device
3079 * @state: The current pci connection state
3080 */
3081static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
3082{
3083 struct net_device *netdev = pci_get_drvdata(pdev);
3084 struct nic *nic = netdev_priv(netdev);
3085
3086 netif_device_detach(netdev);
3087
3088 if (state == pci_channel_io_perm_failure)
3089 return PCI_ERS_RESULT_DISCONNECT;
3090
3091 if (netif_running(netdev))
3092 e100_down(nic);
3093 pci_disable_device(pdev);
3094
3095 /* Request a slot reset. */
3096 return PCI_ERS_RESULT_NEED_RESET;
3097}
3098
3099/**
3100 * e100_io_slot_reset - called after the pci bus has been reset.
3101 * @pdev: Pointer to PCI device
3102 *
3103 * Restart the card from scratch.
3104 */
3105static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
3106{
3107 struct net_device *netdev = pci_get_drvdata(pdev);
3108 struct nic *nic = netdev_priv(netdev);
3109
3110 if (pci_enable_device(pdev)) {
3111 pr_err("Cannot re-enable PCI device after reset\n");
3112 return PCI_ERS_RESULT_DISCONNECT;
3113 }
3114 pci_set_master(pdev);
3115
3116 /* Only one device per card can do a reset */
3117 if (0 != PCI_FUNC(pdev->devfn))
3118 return PCI_ERS_RESULT_RECOVERED;
3119 e100_hw_reset(nic);
3120 e100_phy_init(nic);
3121
3122 return PCI_ERS_RESULT_RECOVERED;
3123}
3124
3125/**
3126 * e100_io_resume - resume normal operations
3127 * @pdev: Pointer to PCI device
3128 *
3129 * Resume normal operations after an error recovery
3130 * sequence has been completed.
3131 */
3132static void e100_io_resume(struct pci_dev *pdev)
3133{
3134 struct net_device *netdev = pci_get_drvdata(pdev);
3135 struct nic *nic = netdev_priv(netdev);
3136
3137 /* ack any pending wake events, disable PME */
3138 pci_enable_wake(pdev, PCI_D0, 0);
3139
3140 netif_device_attach(netdev);
3141 if (netif_running(netdev)) {
3142 e100_open(netdev);
3143 mod_timer(&nic->watchdog, jiffies);
3144 }
3145}
3146
3147static const struct pci_error_handlers e100_err_handler = {
3148 .error_detected = e100_io_error_detected,
3149 .slot_reset = e100_io_slot_reset,
3150 .resume = e100_io_resume,
3151};
3152
3153static struct pci_driver e100_driver = {
3154 .name = DRV_NAME,
3155 .id_table = e100_id_table,
3156 .probe = e100_probe,
3157 .remove = e100_remove,
3158#ifdef CONFIG_PM
3159 /* Power Management hooks */
3160 .suspend = e100_suspend,
3161 .resume = e100_resume,
3162#endif
3163 .shutdown = e100_shutdown,
3164 .err_handler = &e100_err_handler,
3165};
3166
3167static int __init e100_init_module(void)
3168{
3169 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
3170 pr_info("%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
3171 pr_info("%s\n", DRV_COPYRIGHT);
3172 }
3173 return pci_register_driver(&e100_driver);
3174}
3175
3176static void __exit e100_cleanup_module(void)
3177{
3178 pci_unregister_driver(&e100_driver);
3179}
3180
3181module_init(e100_init_module);
3182module_exit(e100_cleanup_module);