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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#define SWSMU_CODE_LAYER_L2
25
26#include <linux/firmware.h>
27#include <linux/pci.h>
28#include <linux/i2c.h>
29#include "amdgpu.h"
30#include "amdgpu_dpm.h"
31#include "amdgpu_smu.h"
32#include "atomfirmware.h"
33#include "amdgpu_atomfirmware.h"
34#include "amdgpu_atombios.h"
35#include "smu_v11_0.h"
36#include "smu11_driver_if_sienna_cichlid.h"
37#include "soc15_common.h"
38#include "atom.h"
39#include "sienna_cichlid_ppt.h"
40#include "smu_v11_0_7_pptable.h"
41#include "smu_v11_0_7_ppsmc.h"
42#include "nbio/nbio_2_3_offset.h"
43#include "nbio/nbio_2_3_sh_mask.h"
44#include "thm/thm_11_0_2_offset.h"
45#include "thm/thm_11_0_2_sh_mask.h"
46#include "mp/mp_11_0_offset.h"
47#include "mp/mp_11_0_sh_mask.h"
48
49#include "asic_reg/mp/mp_11_0_sh_mask.h"
50#include "amdgpu_ras.h"
51#include "smu_cmn.h"
52
53/*
54 * DO NOT use these for err/warn/info/debug messages.
55 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
56 * They are more MGPU friendly.
57 */
58#undef pr_err
59#undef pr_warn
60#undef pr_info
61#undef pr_debug
62
63#define FEATURE_MASK(feature) (1ULL << feature)
64#define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
73
74#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
76#define GET_PPTABLE_MEMBER(field, member) \
77 do { \
78 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == \
79 IP_VERSION(11, 0, 13)) \
80 (*member) = (smu->smu_table.driver_pptable + \
81 offsetof(PPTable_beige_goby_t, field)); \
82 else \
83 (*member) = (smu->smu_table.driver_pptable + \
84 offsetof(PPTable_t, field)); \
85 } while (0)
86
87/* STB FIFO depth is in 64bit units */
88#define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
89
90/*
91 * SMU support ECCTABLE since version 58.70.0,
92 * use this to check whether ECCTABLE feature is supported.
93 */
94#define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
95
96static int get_table_size(struct smu_context *smu)
97{
98 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
99 return sizeof(PPTable_beige_goby_t);
100 else
101 return sizeof(PPTable_t);
102}
103
104static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
105 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
106 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
107 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
108 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
109 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
110 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
111 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
112 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
113 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
114 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
115 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
116 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
117 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
118 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
119 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
120 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
121 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
122 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
123 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
124 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
125 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
126 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
127 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
128 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
129 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
130 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
131 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
132 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
133 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
134 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
135 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
136 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
137 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
138 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
139 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
140 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
141 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
142 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
143 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
144 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
145 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
146 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
147 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
148 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
149 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
150 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
151 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
152 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
153 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
154 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
155 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
156 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
157 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
158 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
159 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
160 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
161 MSG_MAP(DriverMode2Reset, PPSMC_MSG_DriverMode2Reset, 0),
162};
163
164static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
165 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
166 CLK_MAP(SCLK, PPCLK_GFXCLK),
167 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
168 CLK_MAP(FCLK, PPCLK_FCLK),
169 CLK_MAP(UCLK, PPCLK_UCLK),
170 CLK_MAP(MCLK, PPCLK_UCLK),
171 CLK_MAP(DCLK, PPCLK_DCLK_0),
172 CLK_MAP(DCLK1, PPCLK_DCLK_1),
173 CLK_MAP(VCLK, PPCLK_VCLK_0),
174 CLK_MAP(VCLK1, PPCLK_VCLK_1),
175 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
176 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
177 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
178 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
179};
180
181static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
182 FEA_MAP(DPM_PREFETCHER),
183 FEA_MAP(DPM_GFXCLK),
184 FEA_MAP(DPM_GFX_GPO),
185 FEA_MAP(DPM_UCLK),
186 FEA_MAP(DPM_FCLK),
187 FEA_MAP(DPM_SOCCLK),
188 FEA_MAP(DPM_MP0CLK),
189 FEA_MAP(DPM_LINK),
190 FEA_MAP(DPM_DCEFCLK),
191 FEA_MAP(DPM_XGMI),
192 FEA_MAP(MEM_VDDCI_SCALING),
193 FEA_MAP(MEM_MVDD_SCALING),
194 FEA_MAP(DS_GFXCLK),
195 FEA_MAP(DS_SOCCLK),
196 FEA_MAP(DS_FCLK),
197 FEA_MAP(DS_LCLK),
198 FEA_MAP(DS_DCEFCLK),
199 FEA_MAP(DS_UCLK),
200 FEA_MAP(GFX_ULV),
201 FEA_MAP(FW_DSTATE),
202 FEA_MAP(GFXOFF),
203 FEA_MAP(BACO),
204 FEA_MAP(MM_DPM_PG),
205 FEA_MAP(RSMU_SMN_CG),
206 FEA_MAP(PPT),
207 FEA_MAP(TDC),
208 FEA_MAP(APCC_PLUS),
209 FEA_MAP(GTHR),
210 FEA_MAP(ACDC),
211 FEA_MAP(VR0HOT),
212 FEA_MAP(VR1HOT),
213 FEA_MAP(FW_CTF),
214 FEA_MAP(FAN_CONTROL),
215 FEA_MAP(THERMAL),
216 FEA_MAP(GFX_DCS),
217 FEA_MAP(RM),
218 FEA_MAP(LED_DISPLAY),
219 FEA_MAP(GFX_SS),
220 FEA_MAP(OUT_OF_BAND_MONITOR),
221 FEA_MAP(TEMP_DEPENDENT_VMIN),
222 FEA_MAP(MMHUB_PG),
223 FEA_MAP(ATHUB_PG),
224 FEA_MAP(APCC_DFLL),
225};
226
227static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
228 TAB_MAP(PPTABLE),
229 TAB_MAP(WATERMARKS),
230 TAB_MAP(AVFS_PSM_DEBUG),
231 TAB_MAP(AVFS_FUSE_OVERRIDE),
232 TAB_MAP(PMSTATUSLOG),
233 TAB_MAP(SMU_METRICS),
234 TAB_MAP(DRIVER_SMU_CONFIG),
235 TAB_MAP(ACTIVITY_MONITOR_COEFF),
236 TAB_MAP(OVERDRIVE),
237 TAB_MAP(I2C_COMMANDS),
238 TAB_MAP(PACE),
239 TAB_MAP(ECCINFO),
240};
241
242static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
243 PWR_MAP(AC),
244 PWR_MAP(DC),
245};
246
247static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
248 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
249 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
250 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
251 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
252 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
253 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
254 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
255};
256
257static const uint8_t sienna_cichlid_throttler_map[] = {
258 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
259 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
260 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
261 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
262 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
263 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
264 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
265 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
266 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
267 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
268 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
269 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
270 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
271 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
272 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
273 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
274 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
275 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
276};
277
278static int
279sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
280 uint32_t *feature_mask, uint32_t num)
281{
282 struct amdgpu_device *adev = smu->adev;
283
284 if (num > 2)
285 return -EINVAL;
286
287 memset(feature_mask, 0, sizeof(uint32_t) * num);
288
289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
290 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
291 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
292 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
293 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
294 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
295 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
296 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
297 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
298 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
299 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
300 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
301 | FEATURE_MASK(FEATURE_PPT_BIT)
302 | FEATURE_MASK(FEATURE_TDC_BIT)
303 | FEATURE_MASK(FEATURE_BACO_BIT)
304 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
305 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
306 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
307 | FEATURE_MASK(FEATURE_THERMAL_BIT)
308 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
309
310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
312 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
313 }
314
315 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
316 (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) &&
317 !(adev->flags & AMD_IS_APU))
318 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
319
320 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
321 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
322 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
323 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
324
325 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
327
328 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
330
331 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
333
334 if (adev->pm.pp_feature & PP_ULV_MASK)
335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
336
337 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
339
340 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
342
343 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
344 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
345
346 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
347 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
348
349 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
350 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
352
353 if (smu->dc_controlled_by_gpio)
354 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
355
356 if (amdgpu_device_should_use_aspm(adev))
357 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
358
359 return 0;
360}
361
362static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
363{
364 struct smu_table_context *table_context = &smu->smu_table;
365 struct smu_11_0_7_powerplay_table *powerplay_table =
366 table_context->power_play_table;
367 struct smu_baco_context *smu_baco = &smu->smu_baco;
368 struct amdgpu_device *adev = smu->adev;
369 uint32_t val;
370
371 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
372 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
373 smu_baco->platform_support =
374 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
375 false;
376
377 /*
378 * Disable BACO entry/exit completely on below SKUs to
379 * avoid hardware intermittent failures.
380 */
381 if (((adev->pdev->device == 0x73A1) &&
382 (adev->pdev->revision == 0x00)) ||
383 ((adev->pdev->device == 0x73BF) &&
384 (adev->pdev->revision == 0xCF)) ||
385 ((adev->pdev->device == 0x7422) &&
386 (adev->pdev->revision == 0x00)) ||
387 ((adev->pdev->device == 0x73A3) &&
388 (adev->pdev->revision == 0x00)) ||
389 ((adev->pdev->device == 0x73E3) &&
390 (adev->pdev->revision == 0x00)))
391 smu_baco->platform_support = false;
392
393 }
394}
395
396static void sienna_cichlid_check_fan_support(struct smu_context *smu)
397{
398 struct smu_table_context *table_context = &smu->smu_table;
399 PPTable_t *pptable = table_context->driver_pptable;
400 uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
401
402 /* Fan control is not possible if PPTable has it disabled */
403 smu->adev->pm.no_fan =
404 !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
405 if (smu->adev->pm.no_fan)
406 dev_info_once(smu->adev->dev,
407 "PMFW based fan control disabled");
408}
409
410static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
411{
412 struct smu_table_context *table_context = &smu->smu_table;
413 struct smu_11_0_7_powerplay_table *powerplay_table =
414 table_context->power_play_table;
415
416 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
417 smu->dc_controlled_by_gpio = true;
418
419 sienna_cichlid_check_bxco_support(smu);
420 sienna_cichlid_check_fan_support(smu);
421
422 table_context->thermal_controller_type =
423 powerplay_table->thermal_controller_type;
424
425 /*
426 * Instead of having its own buffer space and get overdrive_table copied,
427 * smu->od_settings just points to the actual overdrive_table
428 */
429 smu->od_settings = &powerplay_table->overdrive_table;
430
431 return 0;
432}
433
434static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
435{
436 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
437 int index, ret;
438 PPTable_beige_goby_t *ppt_beige_goby;
439 PPTable_t *ppt;
440
441 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
442 ppt_beige_goby = smu->smu_table.driver_pptable;
443 else
444 ppt = smu->smu_table.driver_pptable;
445
446 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
447 smc_dpm_info);
448
449 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
450 (uint8_t **)&smc_dpm_table);
451 if (ret)
452 return ret;
453
454 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
455 smu_memcpy_trailing(ppt_beige_goby, I2cControllers, BoardReserved,
456 smc_dpm_table, I2cControllers);
457 else
458 smu_memcpy_trailing(ppt, I2cControllers, BoardReserved,
459 smc_dpm_table, I2cControllers);
460
461 return 0;
462}
463
464static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
465{
466 struct smu_table_context *table_context = &smu->smu_table;
467 struct smu_11_0_7_powerplay_table *powerplay_table =
468 table_context->power_play_table;
469 int table_size;
470
471 table_size = get_table_size(smu);
472 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
473 table_size);
474
475 return 0;
476}
477
478static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
479{
480 struct amdgpu_device *adev = smu->adev;
481 uint32_t *board_reserved;
482 uint16_t *freq_table_gfx;
483 uint32_t i;
484
485 /* Fix some OEM SKU specific stability issues */
486 GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
487 if ((adev->pdev->device == 0x73DF) &&
488 (adev->pdev->revision == 0XC3) &&
489 (adev->pdev->subsystem_device == 0x16C2) &&
490 (adev->pdev->subsystem_vendor == 0x1043))
491 board_reserved[0] = 1387;
492
493 GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
494 if ((adev->pdev->device == 0x73DF) &&
495 (adev->pdev->revision == 0XC3) &&
496 ((adev->pdev->subsystem_device == 0x16C2) ||
497 (adev->pdev->subsystem_device == 0x133C)) &&
498 (adev->pdev->subsystem_vendor == 0x1043)) {
499 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
500 if (freq_table_gfx[i] > 2500)
501 freq_table_gfx[i] = 2500;
502 }
503 }
504
505 return 0;
506}
507
508static int sienna_cichlid_setup_pptable(struct smu_context *smu)
509{
510 int ret = 0;
511
512 ret = smu_v11_0_setup_pptable(smu);
513 if (ret)
514 return ret;
515
516 ret = sienna_cichlid_store_powerplay_table(smu);
517 if (ret)
518 return ret;
519
520 ret = sienna_cichlid_append_powerplay_table(smu);
521 if (ret)
522 return ret;
523
524 ret = sienna_cichlid_check_powerplay_table(smu);
525 if (ret)
526 return ret;
527
528 return sienna_cichlid_patch_pptable_quirk(smu);
529}
530
531static int sienna_cichlid_tables_init(struct smu_context *smu)
532{
533 struct smu_table_context *smu_table = &smu->smu_table;
534 struct smu_table *tables = smu_table->tables;
535 int table_size;
536
537 table_size = get_table_size(smu);
538 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
539 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
540 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
541 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
542 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
543 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
544 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
545 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
546 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
547 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
548 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
549 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
550 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
551 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
552 AMDGPU_GEM_DOMAIN_VRAM);
553 SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
554 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
555 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
556 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
557
558 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
559 if (!smu_table->metrics_table)
560 goto err0_out;
561 smu_table->metrics_time = 0;
562
563 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
564 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
565 if (!smu_table->gpu_metrics_table)
566 goto err1_out;
567
568 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
569 if (!smu_table->watermarks_table)
570 goto err2_out;
571
572 smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
573 if (!smu_table->ecc_table)
574 goto err3_out;
575
576 smu_table->driver_smu_config_table =
577 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
578 if (!smu_table->driver_smu_config_table)
579 goto err4_out;
580
581 return 0;
582
583err4_out:
584 kfree(smu_table->ecc_table);
585err3_out:
586 kfree(smu_table->watermarks_table);
587err2_out:
588 kfree(smu_table->gpu_metrics_table);
589err1_out:
590 kfree(smu_table->metrics_table);
591err0_out:
592 return -ENOMEM;
593}
594
595static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu,
596 bool use_metrics_v3,
597 bool use_metrics_v2)
598{
599 struct smu_table_context *smu_table= &smu->smu_table;
600 SmuMetricsExternal_t *metrics_ext =
601 (SmuMetricsExternal_t *)(smu_table->metrics_table);
602 uint32_t throttler_status = 0;
603 int i;
604
605 if (use_metrics_v3) {
606 for (i = 0; i < THROTTLER_COUNT; i++)
607 throttler_status |=
608 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
609 } else if (use_metrics_v2) {
610 for (i = 0; i < THROTTLER_COUNT; i++)
611 throttler_status |=
612 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
613 } else {
614 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
615 }
616
617 return throttler_status;
618}
619
620static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
621 enum SMU_11_0_7_ODFEATURE_CAP cap)
622{
623 return od_table->cap[cap];
624}
625
626static int sienna_cichlid_get_power_limit(struct smu_context *smu,
627 uint32_t *current_power_limit,
628 uint32_t *default_power_limit,
629 uint32_t *max_power_limit,
630 uint32_t *min_power_limit)
631{
632 struct smu_11_0_7_powerplay_table *powerplay_table =
633 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
634 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
635 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
636 uint16_t *table_member;
637
638 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
639
640 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
641 power_limit =
642 table_member[PPT_THROTTLER_PPT0];
643 }
644
645 if (current_power_limit)
646 *current_power_limit = power_limit;
647 if (default_power_limit)
648 *default_power_limit = power_limit;
649
650 if (powerplay_table) {
651 if (smu->od_enabled &&
652 sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_POWER_LIMIT)) {
653 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
654 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
655 } else if ((sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_POWER_LIMIT))) {
656 od_percent_upper = 0;
657 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
658 }
659 }
660
661 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
662 od_percent_upper, od_percent_lower, power_limit);
663
664 if (max_power_limit) {
665 *max_power_limit = power_limit * (100 + od_percent_upper);
666 *max_power_limit /= 100;
667 }
668
669 if (min_power_limit) {
670 *min_power_limit = power_limit * (100 - od_percent_lower);
671 *min_power_limit /= 100;
672 }
673 return 0;
674}
675
676static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
677 uint32_t *apu_percent,
678 uint32_t *dgpu_percent)
679{
680 struct smu_table_context *smu_table = &smu->smu_table;
681 SmuMetrics_V4_t *metrics_v4 =
682 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
683 uint16_t powerRatio = 0;
684 uint16_t apu_power_limit = 0;
685 uint16_t dgpu_power_limit = 0;
686 uint32_t apu_boost = 0;
687 uint32_t dgpu_boost = 0;
688 uint32_t cur_power_limit;
689
690 if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
691 sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL, NULL);
692 apu_power_limit = metrics_v4->ApuSTAPMLimit;
693 dgpu_power_limit = cur_power_limit;
694 powerRatio = (((apu_power_limit +
695 dgpu_power_limit) * 100) /
696 metrics_v4->ApuSTAPMSmartShiftLimit);
697 if (powerRatio > 100) {
698 apu_power_limit = (apu_power_limit * 100) /
699 powerRatio;
700 dgpu_power_limit = (dgpu_power_limit * 100) /
701 powerRatio;
702 }
703 if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
704 apu_power_limit != 0) {
705 apu_boost = ((metrics_v4->AverageApuSocketPower -
706 apu_power_limit) * 100) /
707 apu_power_limit;
708 if (apu_boost > 100)
709 apu_boost = 100;
710 }
711
712 if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
713 dgpu_power_limit != 0) {
714 dgpu_boost = ((metrics_v4->AverageSocketPower -
715 dgpu_power_limit) * 100) /
716 dgpu_power_limit;
717 if (dgpu_boost > 100)
718 dgpu_boost = 100;
719 }
720
721 if (dgpu_boost >= apu_boost)
722 apu_boost = 0;
723 else
724 dgpu_boost = 0;
725 }
726 *apu_percent = apu_boost;
727 *dgpu_percent = dgpu_boost;
728}
729
730static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
731 MetricsMember_t member,
732 uint32_t *value)
733{
734 struct smu_table_context *smu_table= &smu->smu_table;
735 SmuMetrics_t *metrics =
736 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
737 SmuMetrics_V2_t *metrics_v2 =
738 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
739 SmuMetrics_V3_t *metrics_v3 =
740 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
741 bool use_metrics_v2 = false;
742 bool use_metrics_v3 = false;
743 uint16_t average_gfx_activity;
744 int ret = 0;
745 uint32_t apu_percent = 0;
746 uint32_t dgpu_percent = 0;
747
748 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
749 case IP_VERSION(11, 0, 7):
750 if (smu->smc_fw_version >= 0x3A4900)
751 use_metrics_v3 = true;
752 else if (smu->smc_fw_version >= 0x3A4300)
753 use_metrics_v2 = true;
754 break;
755 case IP_VERSION(11, 0, 11):
756 if (smu->smc_fw_version >= 0x412D00)
757 use_metrics_v2 = true;
758 break;
759 case IP_VERSION(11, 0, 12):
760 if (smu->smc_fw_version >= 0x3B2300)
761 use_metrics_v2 = true;
762 break;
763 case IP_VERSION(11, 0, 13):
764 if (smu->smc_fw_version >= 0x491100)
765 use_metrics_v2 = true;
766 break;
767 default:
768 break;
769 }
770
771 ret = smu_cmn_get_metrics_table(smu,
772 NULL,
773 false);
774 if (ret)
775 return ret;
776
777 switch (member) {
778 case METRICS_CURR_GFXCLK:
779 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
780 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
781 metrics->CurrClock[PPCLK_GFXCLK];
782 break;
783 case METRICS_CURR_SOCCLK:
784 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
785 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
786 metrics->CurrClock[PPCLK_SOCCLK];
787 break;
788 case METRICS_CURR_UCLK:
789 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
790 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
791 metrics->CurrClock[PPCLK_UCLK];
792 break;
793 case METRICS_CURR_VCLK:
794 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
795 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
796 metrics->CurrClock[PPCLK_VCLK_0];
797 break;
798 case METRICS_CURR_VCLK1:
799 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
800 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
801 metrics->CurrClock[PPCLK_VCLK_1];
802 break;
803 case METRICS_CURR_DCLK:
804 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
805 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
806 metrics->CurrClock[PPCLK_DCLK_0];
807 break;
808 case METRICS_CURR_DCLK1:
809 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
810 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
811 metrics->CurrClock[PPCLK_DCLK_1];
812 break;
813 case METRICS_CURR_DCEFCLK:
814 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
815 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
816 metrics->CurrClock[PPCLK_DCEFCLK];
817 break;
818 case METRICS_CURR_FCLK:
819 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
820 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
821 metrics->CurrClock[PPCLK_FCLK];
822 break;
823 case METRICS_AVERAGE_GFXCLK:
824 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
825 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
826 metrics->AverageGfxActivity;
827 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
828 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
829 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
830 metrics->AverageGfxclkFrequencyPostDs;
831 else
832 *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
833 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
834 metrics->AverageGfxclkFrequencyPreDs;
835 break;
836 case METRICS_AVERAGE_FCLK:
837 *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
838 use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
839 metrics->AverageFclkFrequencyPostDs;
840 break;
841 case METRICS_AVERAGE_UCLK:
842 *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
843 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
844 metrics->AverageUclkFrequencyPostDs;
845 break;
846 case METRICS_AVERAGE_GFXACTIVITY:
847 *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
848 use_metrics_v2 ? metrics_v2->AverageGfxActivity :
849 metrics->AverageGfxActivity;
850 break;
851 case METRICS_AVERAGE_MEMACTIVITY:
852 *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
853 use_metrics_v2 ? metrics_v2->AverageUclkActivity :
854 metrics->AverageUclkActivity;
855 break;
856 case METRICS_AVERAGE_SOCKETPOWER:
857 *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
858 use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
859 metrics->AverageSocketPower << 8;
860 break;
861 case METRICS_TEMPERATURE_EDGE:
862 *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
863 use_metrics_v2 ? metrics_v2->TemperatureEdge :
864 metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
865 break;
866 case METRICS_TEMPERATURE_HOTSPOT:
867 *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
868 use_metrics_v2 ? metrics_v2->TemperatureHotspot :
869 metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
870 break;
871 case METRICS_TEMPERATURE_MEM:
872 *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
873 use_metrics_v2 ? metrics_v2->TemperatureMem :
874 metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
875 break;
876 case METRICS_TEMPERATURE_VRGFX:
877 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
878 use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
879 metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
880 break;
881 case METRICS_TEMPERATURE_VRSOC:
882 *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
883 use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
884 metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
885 break;
886 case METRICS_THROTTLER_STATUS:
887 *value = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
888 break;
889 case METRICS_CURR_FANSPEED:
890 *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
891 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
892 break;
893 case METRICS_UNIQUE_ID_UPPER32:
894 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
895 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
896 break;
897 case METRICS_UNIQUE_ID_LOWER32:
898 /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
899 *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
900 break;
901 case METRICS_SS_APU_SHARE:
902 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
903 *value = apu_percent;
904 break;
905 case METRICS_SS_DGPU_SHARE:
906 sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
907 *value = dgpu_percent;
908 break;
909
910 default:
911 *value = UINT_MAX;
912 break;
913 }
914
915 return ret;
916
917}
918
919static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
920{
921 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
922
923 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
924 GFP_KERNEL);
925 if (!smu_dpm->dpm_context)
926 return -ENOMEM;
927
928 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
929
930 return 0;
931}
932
933static void sienna_cichlid_stb_init(struct smu_context *smu);
934
935static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
936{
937 struct amdgpu_device *adev = smu->adev;
938 int ret = 0;
939
940 ret = sienna_cichlid_tables_init(smu);
941 if (ret)
942 return ret;
943
944 ret = sienna_cichlid_allocate_dpm_context(smu);
945 if (ret)
946 return ret;
947
948 if (!amdgpu_sriov_vf(adev))
949 sienna_cichlid_stb_init(smu);
950
951 return smu_v11_0_init_smc_tables(smu);
952}
953
954static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
955{
956 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
957 struct smu_11_0_dpm_table *dpm_table;
958 struct amdgpu_device *adev = smu->adev;
959 int i, ret = 0;
960 DpmDescriptor_t *table_member;
961
962 /* socclk dpm table setup */
963 dpm_table = &dpm_context->dpm_tables.soc_table;
964 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
965 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
966 ret = smu_v11_0_set_single_dpm_table(smu,
967 SMU_SOCCLK,
968 dpm_table);
969 if (ret)
970 return ret;
971 dpm_table->is_fine_grained =
972 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
973 } else {
974 dpm_table->count = 1;
975 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
976 dpm_table->dpm_levels[0].enabled = true;
977 dpm_table->min = dpm_table->dpm_levels[0].value;
978 dpm_table->max = dpm_table->dpm_levels[0].value;
979 }
980
981 /* gfxclk dpm table setup */
982 dpm_table = &dpm_context->dpm_tables.gfx_table;
983 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
984 ret = smu_v11_0_set_single_dpm_table(smu,
985 SMU_GFXCLK,
986 dpm_table);
987 if (ret)
988 return ret;
989 dpm_table->is_fine_grained =
990 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
991 } else {
992 dpm_table->count = 1;
993 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
994 dpm_table->dpm_levels[0].enabled = true;
995 dpm_table->min = dpm_table->dpm_levels[0].value;
996 dpm_table->max = dpm_table->dpm_levels[0].value;
997 }
998
999 /* uclk dpm table setup */
1000 dpm_table = &dpm_context->dpm_tables.uclk_table;
1001 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1002 ret = smu_v11_0_set_single_dpm_table(smu,
1003 SMU_UCLK,
1004 dpm_table);
1005 if (ret)
1006 return ret;
1007 dpm_table->is_fine_grained =
1008 !table_member[PPCLK_UCLK].SnapToDiscrete;
1009 } else {
1010 dpm_table->count = 1;
1011 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1012 dpm_table->dpm_levels[0].enabled = true;
1013 dpm_table->min = dpm_table->dpm_levels[0].value;
1014 dpm_table->max = dpm_table->dpm_levels[0].value;
1015 }
1016
1017 /* fclk dpm table setup */
1018 dpm_table = &dpm_context->dpm_tables.fclk_table;
1019 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
1020 ret = smu_v11_0_set_single_dpm_table(smu,
1021 SMU_FCLK,
1022 dpm_table);
1023 if (ret)
1024 return ret;
1025 dpm_table->is_fine_grained =
1026 !table_member[PPCLK_FCLK].SnapToDiscrete;
1027 } else {
1028 dpm_table->count = 1;
1029 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
1030 dpm_table->dpm_levels[0].enabled = true;
1031 dpm_table->min = dpm_table->dpm_levels[0].value;
1032 dpm_table->max = dpm_table->dpm_levels[0].value;
1033 }
1034
1035 /* vclk0/1 dpm table setup */
1036 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1037 if (adev->vcn.harvest_config & (1 << i))
1038 continue;
1039
1040 dpm_table = &dpm_context->dpm_tables.vclk_table;
1041 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1042 ret = smu_v11_0_set_single_dpm_table(smu,
1043 i ? SMU_VCLK1 : SMU_VCLK,
1044 dpm_table);
1045 if (ret)
1046 return ret;
1047 dpm_table->is_fine_grained =
1048 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
1049 } else {
1050 dpm_table->count = 1;
1051 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1052 dpm_table->dpm_levels[0].enabled = true;
1053 dpm_table->min = dpm_table->dpm_levels[0].value;
1054 dpm_table->max = dpm_table->dpm_levels[0].value;
1055 }
1056 }
1057
1058 /* dclk0/1 dpm table setup */
1059 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1060 if (adev->vcn.harvest_config & (1 << i))
1061 continue;
1062 dpm_table = &dpm_context->dpm_tables.dclk_table;
1063 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1064 ret = smu_v11_0_set_single_dpm_table(smu,
1065 i ? SMU_DCLK1 : SMU_DCLK,
1066 dpm_table);
1067 if (ret)
1068 return ret;
1069 dpm_table->is_fine_grained =
1070 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
1071 } else {
1072 dpm_table->count = 1;
1073 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1074 dpm_table->dpm_levels[0].enabled = true;
1075 dpm_table->min = dpm_table->dpm_levels[0].value;
1076 dpm_table->max = dpm_table->dpm_levels[0].value;
1077 }
1078 }
1079
1080 /* dcefclk dpm table setup */
1081 dpm_table = &dpm_context->dpm_tables.dcef_table;
1082 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1083 ret = smu_v11_0_set_single_dpm_table(smu,
1084 SMU_DCEFCLK,
1085 dpm_table);
1086 if (ret)
1087 return ret;
1088 dpm_table->is_fine_grained =
1089 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
1090 } else {
1091 dpm_table->count = 1;
1092 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1093 dpm_table->dpm_levels[0].enabled = true;
1094 dpm_table->min = dpm_table->dpm_levels[0].value;
1095 dpm_table->max = dpm_table->dpm_levels[0].value;
1096 }
1097
1098 /* pixelclk dpm table setup */
1099 dpm_table = &dpm_context->dpm_tables.pixel_table;
1100 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1101 ret = smu_v11_0_set_single_dpm_table(smu,
1102 SMU_PIXCLK,
1103 dpm_table);
1104 if (ret)
1105 return ret;
1106 dpm_table->is_fine_grained =
1107 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
1108 } else {
1109 dpm_table->count = 1;
1110 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1111 dpm_table->dpm_levels[0].enabled = true;
1112 dpm_table->min = dpm_table->dpm_levels[0].value;
1113 dpm_table->max = dpm_table->dpm_levels[0].value;
1114 }
1115
1116 /* displayclk dpm table setup */
1117 dpm_table = &dpm_context->dpm_tables.display_table;
1118 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1119 ret = smu_v11_0_set_single_dpm_table(smu,
1120 SMU_DISPCLK,
1121 dpm_table);
1122 if (ret)
1123 return ret;
1124 dpm_table->is_fine_grained =
1125 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
1126 } else {
1127 dpm_table->count = 1;
1128 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1129 dpm_table->dpm_levels[0].enabled = true;
1130 dpm_table->min = dpm_table->dpm_levels[0].value;
1131 dpm_table->max = dpm_table->dpm_levels[0].value;
1132 }
1133
1134 /* phyclk dpm table setup */
1135 dpm_table = &dpm_context->dpm_tables.phy_table;
1136 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1137 ret = smu_v11_0_set_single_dpm_table(smu,
1138 SMU_PHYCLK,
1139 dpm_table);
1140 if (ret)
1141 return ret;
1142 dpm_table->is_fine_grained =
1143 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
1144 } else {
1145 dpm_table->count = 1;
1146 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1147 dpm_table->dpm_levels[0].enabled = true;
1148 dpm_table->min = dpm_table->dpm_levels[0].value;
1149 dpm_table->max = dpm_table->dpm_levels[0].value;
1150 }
1151
1152 return 0;
1153}
1154
1155static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1156{
1157 struct amdgpu_device *adev = smu->adev;
1158 int i, ret = 0;
1159
1160 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1161 if (adev->vcn.harvest_config & (1 << i))
1162 continue;
1163 /* vcn dpm on is a prerequisite for vcn power gate messages */
1164 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1165 ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1166 SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1167 0x10000 * i, NULL);
1168 if (ret)
1169 return ret;
1170 }
1171 }
1172
1173 return ret;
1174}
1175
1176static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1177{
1178 int ret = 0;
1179
1180 if (enable) {
1181 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1182 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
1183 if (ret)
1184 return ret;
1185 }
1186 } else {
1187 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1188 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
1189 if (ret)
1190 return ret;
1191 }
1192 }
1193
1194 return ret;
1195}
1196
1197static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1198 enum smu_clk_type clk_type,
1199 uint32_t *value)
1200{
1201 MetricsMember_t member_type;
1202 int clk_id = 0;
1203
1204 clk_id = smu_cmn_to_asic_specific_index(smu,
1205 CMN2ASIC_MAPPING_CLK,
1206 clk_type);
1207 if (clk_id < 0)
1208 return clk_id;
1209
1210 switch (clk_id) {
1211 case PPCLK_GFXCLK:
1212 member_type = METRICS_CURR_GFXCLK;
1213 break;
1214 case PPCLK_UCLK:
1215 member_type = METRICS_CURR_UCLK;
1216 break;
1217 case PPCLK_SOCCLK:
1218 member_type = METRICS_CURR_SOCCLK;
1219 break;
1220 case PPCLK_FCLK:
1221 member_type = METRICS_CURR_FCLK;
1222 break;
1223 case PPCLK_VCLK_0:
1224 member_type = METRICS_CURR_VCLK;
1225 break;
1226 case PPCLK_VCLK_1:
1227 member_type = METRICS_CURR_VCLK1;
1228 break;
1229 case PPCLK_DCLK_0:
1230 member_type = METRICS_CURR_DCLK;
1231 break;
1232 case PPCLK_DCLK_1:
1233 member_type = METRICS_CURR_DCLK1;
1234 break;
1235 case PPCLK_DCEFCLK:
1236 member_type = METRICS_CURR_DCEFCLK;
1237 break;
1238 default:
1239 return -EINVAL;
1240 }
1241
1242 return sienna_cichlid_get_smu_metrics_data(smu,
1243 member_type,
1244 value);
1245
1246}
1247
1248static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1249{
1250 DpmDescriptor_t *dpm_desc = NULL;
1251 DpmDescriptor_t *table_member;
1252 uint32_t clk_index = 0;
1253
1254 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1255 clk_index = smu_cmn_to_asic_specific_index(smu,
1256 CMN2ASIC_MAPPING_CLK,
1257 clk_type);
1258 dpm_desc = &table_member[clk_index];
1259
1260 /* 0 - Fine grained DPM, 1 - Discrete DPM */
1261 return dpm_desc->SnapToDiscrete == 0;
1262}
1263
1264static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1265 enum SMU_11_0_7_ODSETTING_ID setting,
1266 uint32_t *min, uint32_t *max)
1267{
1268 if (min)
1269 *min = od_table->min[setting];
1270 if (max)
1271 *max = od_table->max[setting];
1272}
1273
1274static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1275 enum smu_clk_type clk_type, char *buf)
1276{
1277 struct amdgpu_device *adev = smu->adev;
1278 struct smu_table_context *table_context = &smu->smu_table;
1279 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1280 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1281 uint16_t *table_member;
1282
1283 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1284 OverDriveTable_t *od_table =
1285 (OverDriveTable_t *)table_context->overdrive_table;
1286 int i, size = 0, ret = 0;
1287 uint32_t cur_value = 0, value = 0, count = 0;
1288 uint32_t freq_values[3] = {0};
1289 uint32_t mark_index = 0;
1290 uint32_t gen_speed, lane_width;
1291 uint32_t min_value, max_value;
1292
1293 smu_cmn_get_sysfs_buf(&buf, &size);
1294
1295 switch (clk_type) {
1296 case SMU_GFXCLK:
1297 case SMU_SCLK:
1298 case SMU_SOCCLK:
1299 case SMU_MCLK:
1300 case SMU_UCLK:
1301 case SMU_FCLK:
1302 case SMU_VCLK:
1303 case SMU_VCLK1:
1304 case SMU_DCLK:
1305 case SMU_DCLK1:
1306 case SMU_DCEFCLK:
1307 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1308 if (ret)
1309 goto print_clk_out;
1310
1311 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1312 if (ret)
1313 goto print_clk_out;
1314
1315 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1316 for (i = 0; i < count; i++) {
1317 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1318 if (ret)
1319 goto print_clk_out;
1320
1321 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1322 cur_value == value ? "*" : "");
1323 }
1324 } else {
1325 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1326 if (ret)
1327 goto print_clk_out;
1328 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1329 if (ret)
1330 goto print_clk_out;
1331
1332 freq_values[1] = cur_value;
1333 mark_index = cur_value == freq_values[0] ? 0 :
1334 cur_value == freq_values[2] ? 2 : 1;
1335
1336 count = 3;
1337 if (mark_index != 1) {
1338 count = 2;
1339 freq_values[1] = freq_values[2];
1340 }
1341
1342 for (i = 0; i < count; i++) {
1343 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1344 cur_value == freq_values[i] ? "*" : "");
1345 }
1346
1347 }
1348 break;
1349 case SMU_PCIE:
1350 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1351 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1352 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1353 for (i = 0; i < NUM_LINK_LEVELS; i++)
1354 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1355 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1356 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1357 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1358 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1359 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1360 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1361 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1362 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1363 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1364 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1365 table_member[i],
1366 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1367 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1368 "*" : "");
1369 break;
1370 case SMU_OD_SCLK:
1371 if (!smu->od_enabled || !od_table || !od_settings)
1372 break;
1373
1374 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1375 break;
1376
1377 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1378 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1379 break;
1380
1381 case SMU_OD_MCLK:
1382 if (!smu->od_enabled || !od_table || !od_settings)
1383 break;
1384
1385 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1386 break;
1387
1388 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1389 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1390 break;
1391
1392 case SMU_OD_VDDGFX_OFFSET:
1393 if (!smu->od_enabled || !od_table || !od_settings)
1394 break;
1395
1396 /*
1397 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1398 * and onwards SMU firmwares.
1399 */
1400 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1401 IP_VERSION(11, 0, 7)) &&
1402 (smu->smc_fw_version < 0x003a2900))
1403 break;
1404
1405 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1406 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1407 break;
1408
1409 case SMU_OD_RANGE:
1410 if (!smu->od_enabled || !od_table || !od_settings)
1411 break;
1412
1413 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1414
1415 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1416 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1417 &min_value, NULL);
1418 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1419 NULL, &max_value);
1420 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1421 min_value, max_value);
1422 }
1423
1424 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1425 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1426 &min_value, NULL);
1427 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1428 NULL, &max_value);
1429 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1430 min_value, max_value);
1431 }
1432 break;
1433
1434 default:
1435 break;
1436 }
1437
1438print_clk_out:
1439 return size;
1440}
1441
1442static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1443 enum smu_clk_type clk_type, uint32_t mask)
1444{
1445 int ret = 0;
1446 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1447
1448 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1449 soft_max_level = mask ? (fls(mask) - 1) : 0;
1450
1451 switch (clk_type) {
1452 case SMU_GFXCLK:
1453 case SMU_SCLK:
1454 case SMU_SOCCLK:
1455 case SMU_MCLK:
1456 case SMU_UCLK:
1457 case SMU_FCLK:
1458 /* There is only 2 levels for fine grained DPM */
1459 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1460 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1461 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1462 }
1463
1464 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1465 if (ret)
1466 goto forec_level_out;
1467
1468 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1469 if (ret)
1470 goto forec_level_out;
1471
1472 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1473 if (ret)
1474 goto forec_level_out;
1475 break;
1476 case SMU_DCEFCLK:
1477 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1478 break;
1479 default:
1480 break;
1481 }
1482
1483forec_level_out:
1484 return 0;
1485}
1486
1487static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1488{
1489 struct smu_11_0_dpm_context *dpm_context =
1490 smu->smu_dpm.dpm_context;
1491 struct smu_11_0_dpm_table *gfx_table =
1492 &dpm_context->dpm_tables.gfx_table;
1493 struct smu_11_0_dpm_table *mem_table =
1494 &dpm_context->dpm_tables.uclk_table;
1495 struct smu_11_0_dpm_table *soc_table =
1496 &dpm_context->dpm_tables.soc_table;
1497 struct smu_umd_pstate_table *pstate_table =
1498 &smu->pstate_table;
1499 struct amdgpu_device *adev = smu->adev;
1500
1501 pstate_table->gfxclk_pstate.min = gfx_table->min;
1502 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1503
1504 pstate_table->uclk_pstate.min = mem_table->min;
1505 pstate_table->uclk_pstate.peak = mem_table->max;
1506
1507 pstate_table->socclk_pstate.min = soc_table->min;
1508 pstate_table->socclk_pstate.peak = soc_table->max;
1509
1510 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1511 case IP_VERSION(11, 0, 7):
1512 case IP_VERSION(11, 0, 11):
1513 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1514 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1515 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1516 break;
1517 case IP_VERSION(11, 0, 12):
1518 pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1519 pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1520 pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1521 break;
1522 case IP_VERSION(11, 0, 13):
1523 pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1524 pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1525 pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1526 break;
1527 default:
1528 break;
1529 }
1530
1531 return 0;
1532}
1533
1534static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1535{
1536 int ret = 0;
1537 uint32_t max_freq = 0;
1538
1539 /* Sienna_Cichlid do not support to change display num currently */
1540 return 0;
1541#if 0
1542 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1543 if (ret)
1544 return ret;
1545#endif
1546
1547 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1548 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1549 if (ret)
1550 return ret;
1551 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1552 if (ret)
1553 return ret;
1554 }
1555
1556 return ret;
1557}
1558
1559static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1560{
1561 int ret = 0;
1562
1563 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1564 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1565 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1566#if 0
1567 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1568 smu->display_config->num_display,
1569 NULL);
1570#endif
1571 if (ret)
1572 return ret;
1573 }
1574
1575 return ret;
1576}
1577
1578static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1579{
1580 int ret = 0;
1581 uint64_t feature_enabled;
1582
1583 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1584 if (ret)
1585 return false;
1586
1587 return !!(feature_enabled & SMC_DPM_FEATURE);
1588}
1589
1590static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1591 uint32_t *speed)
1592{
1593 if (!speed)
1594 return -EINVAL;
1595
1596 /*
1597 * For Sienna_Cichlid and later, the fan speed(rpm) reported
1598 * by pmfw is always trustable(even when the fan control feature
1599 * disabled or 0 RPM kicked in).
1600 */
1601 return sienna_cichlid_get_smu_metrics_data(smu,
1602 METRICS_CURR_FANSPEED,
1603 speed);
1604}
1605
1606static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1607{
1608 uint16_t *table_member;
1609
1610 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1611 smu->fan_max_rpm = *table_member;
1612
1613 return 0;
1614}
1615
1616static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1617{
1618 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1619 DpmActivityMonitorCoeffInt_t *activity_monitor =
1620 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1621 uint32_t i, size = 0;
1622 int16_t workload_type = 0;
1623 static const char *title[] = {
1624 "PROFILE_INDEX(NAME)",
1625 "CLOCK_TYPE(NAME)",
1626 "FPS",
1627 "MinFreqType",
1628 "MinActiveFreqType",
1629 "MinActiveFreq",
1630 "BoosterFreqType",
1631 "BoosterFreq",
1632 "PD_Data_limit_c",
1633 "PD_Data_error_coeff",
1634 "PD_Data_error_rate_coeff"};
1635 int result = 0;
1636
1637 if (!buf)
1638 return -EINVAL;
1639
1640 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1641 title[0], title[1], title[2], title[3], title[4], title[5],
1642 title[6], title[7], title[8], title[9], title[10]);
1643
1644 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1645 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1646 workload_type = smu_cmn_to_asic_specific_index(smu,
1647 CMN2ASIC_MAPPING_WORKLOAD,
1648 i);
1649 if (workload_type < 0)
1650 return -EINVAL;
1651
1652 result = smu_cmn_update_table(smu,
1653 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1654 (void *)(&activity_monitor_external), false);
1655 if (result) {
1656 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1657 return result;
1658 }
1659
1660 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1661 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1662
1663 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1664 " ",
1665 0,
1666 "GFXCLK",
1667 activity_monitor->Gfx_FPS,
1668 activity_monitor->Gfx_MinFreqStep,
1669 activity_monitor->Gfx_MinActiveFreqType,
1670 activity_monitor->Gfx_MinActiveFreq,
1671 activity_monitor->Gfx_BoosterFreqType,
1672 activity_monitor->Gfx_BoosterFreq,
1673 activity_monitor->Gfx_PD_Data_limit_c,
1674 activity_monitor->Gfx_PD_Data_error_coeff,
1675 activity_monitor->Gfx_PD_Data_error_rate_coeff);
1676
1677 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1678 " ",
1679 1,
1680 "SOCCLK",
1681 activity_monitor->Fclk_FPS,
1682 activity_monitor->Fclk_MinFreqStep,
1683 activity_monitor->Fclk_MinActiveFreqType,
1684 activity_monitor->Fclk_MinActiveFreq,
1685 activity_monitor->Fclk_BoosterFreqType,
1686 activity_monitor->Fclk_BoosterFreq,
1687 activity_monitor->Fclk_PD_Data_limit_c,
1688 activity_monitor->Fclk_PD_Data_error_coeff,
1689 activity_monitor->Fclk_PD_Data_error_rate_coeff);
1690
1691 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1692 " ",
1693 2,
1694 "MEMLK",
1695 activity_monitor->Mem_FPS,
1696 activity_monitor->Mem_MinFreqStep,
1697 activity_monitor->Mem_MinActiveFreqType,
1698 activity_monitor->Mem_MinActiveFreq,
1699 activity_monitor->Mem_BoosterFreqType,
1700 activity_monitor->Mem_BoosterFreq,
1701 activity_monitor->Mem_PD_Data_limit_c,
1702 activity_monitor->Mem_PD_Data_error_coeff,
1703 activity_monitor->Mem_PD_Data_error_rate_coeff);
1704 }
1705
1706 return size;
1707}
1708
1709static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1710{
1711
1712 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1713 DpmActivityMonitorCoeffInt_t *activity_monitor =
1714 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1715 int workload_type, ret = 0;
1716
1717 smu->power_profile_mode = input[size];
1718
1719 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1720 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1721 return -EINVAL;
1722 }
1723
1724 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1725
1726 ret = smu_cmn_update_table(smu,
1727 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1728 (void *)(&activity_monitor_external), false);
1729 if (ret) {
1730 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1731 return ret;
1732 }
1733
1734 switch (input[0]) {
1735 case 0: /* Gfxclk */
1736 activity_monitor->Gfx_FPS = input[1];
1737 activity_monitor->Gfx_MinFreqStep = input[2];
1738 activity_monitor->Gfx_MinActiveFreqType = input[3];
1739 activity_monitor->Gfx_MinActiveFreq = input[4];
1740 activity_monitor->Gfx_BoosterFreqType = input[5];
1741 activity_monitor->Gfx_BoosterFreq = input[6];
1742 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1743 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1744 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1745 break;
1746 case 1: /* Socclk */
1747 activity_monitor->Fclk_FPS = input[1];
1748 activity_monitor->Fclk_MinFreqStep = input[2];
1749 activity_monitor->Fclk_MinActiveFreqType = input[3];
1750 activity_monitor->Fclk_MinActiveFreq = input[4];
1751 activity_monitor->Fclk_BoosterFreqType = input[5];
1752 activity_monitor->Fclk_BoosterFreq = input[6];
1753 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1754 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1755 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1756 break;
1757 case 2: /* Memlk */
1758 activity_monitor->Mem_FPS = input[1];
1759 activity_monitor->Mem_MinFreqStep = input[2];
1760 activity_monitor->Mem_MinActiveFreqType = input[3];
1761 activity_monitor->Mem_MinActiveFreq = input[4];
1762 activity_monitor->Mem_BoosterFreqType = input[5];
1763 activity_monitor->Mem_BoosterFreq = input[6];
1764 activity_monitor->Mem_PD_Data_limit_c = input[7];
1765 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1766 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1767 break;
1768 }
1769
1770 ret = smu_cmn_update_table(smu,
1771 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1772 (void *)(&activity_monitor_external), true);
1773 if (ret) {
1774 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1775 return ret;
1776 }
1777 }
1778
1779 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1780 workload_type = smu_cmn_to_asic_specific_index(smu,
1781 CMN2ASIC_MAPPING_WORKLOAD,
1782 smu->power_profile_mode);
1783 if (workload_type < 0)
1784 return -EINVAL;
1785 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1786 1 << workload_type, NULL);
1787
1788 return ret;
1789}
1790
1791static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1792{
1793 struct smu_clocks min_clocks = {0};
1794 struct pp_display_clock_request clock_req;
1795 int ret = 0;
1796
1797 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1798 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1799 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1800
1801 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1802 clock_req.clock_type = amd_pp_dcef_clock;
1803 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1804
1805 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1806 if (!ret) {
1807 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1808 ret = smu_cmn_send_smc_msg_with_param(smu,
1809 SMU_MSG_SetMinDeepSleepDcefclk,
1810 min_clocks.dcef_clock_in_sr/100,
1811 NULL);
1812 if (ret) {
1813 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1814 return ret;
1815 }
1816 }
1817 } else {
1818 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1819 }
1820 }
1821
1822 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1823 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1824 if (ret) {
1825 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1826 return ret;
1827 }
1828 }
1829
1830 return 0;
1831}
1832
1833static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1834 struct pp_smu_wm_range_sets *clock_ranges)
1835{
1836 Watermarks_t *table = smu->smu_table.watermarks_table;
1837 int ret = 0;
1838 int i;
1839
1840 if (clock_ranges) {
1841 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1842 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1843 return -EINVAL;
1844
1845 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1846 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1847 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1848 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1849 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1850 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1851 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1852 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1853 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1854
1855 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1856 clock_ranges->reader_wm_sets[i].wm_inst;
1857 }
1858
1859 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1860 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1861 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1862 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1863 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1864 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1865 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1866 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1867 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1868
1869 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1870 clock_ranges->writer_wm_sets[i].wm_inst;
1871 }
1872
1873 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1874 }
1875
1876 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1877 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1878 ret = smu_cmn_write_watermarks_table(smu);
1879 if (ret) {
1880 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1881 return ret;
1882 }
1883 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1884 }
1885
1886 return 0;
1887}
1888
1889static int sienna_cichlid_read_sensor(struct smu_context *smu,
1890 enum amd_pp_sensors sensor,
1891 void *data, uint32_t *size)
1892{
1893 int ret = 0;
1894 uint16_t *temp;
1895 struct amdgpu_device *adev = smu->adev;
1896
1897 if(!data || !size)
1898 return -EINVAL;
1899
1900 switch (sensor) {
1901 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1902 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1903 *(uint16_t *)data = *temp;
1904 *size = 4;
1905 break;
1906 case AMDGPU_PP_SENSOR_MEM_LOAD:
1907 ret = sienna_cichlid_get_smu_metrics_data(smu,
1908 METRICS_AVERAGE_MEMACTIVITY,
1909 (uint32_t *)data);
1910 *size = 4;
1911 break;
1912 case AMDGPU_PP_SENSOR_GPU_LOAD:
1913 ret = sienna_cichlid_get_smu_metrics_data(smu,
1914 METRICS_AVERAGE_GFXACTIVITY,
1915 (uint32_t *)data);
1916 *size = 4;
1917 break;
1918 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1919 ret = sienna_cichlid_get_smu_metrics_data(smu,
1920 METRICS_AVERAGE_SOCKETPOWER,
1921 (uint32_t *)data);
1922 *size = 4;
1923 break;
1924 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1925 ret = sienna_cichlid_get_smu_metrics_data(smu,
1926 METRICS_TEMPERATURE_HOTSPOT,
1927 (uint32_t *)data);
1928 *size = 4;
1929 break;
1930 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1931 ret = sienna_cichlid_get_smu_metrics_data(smu,
1932 METRICS_TEMPERATURE_EDGE,
1933 (uint32_t *)data);
1934 *size = 4;
1935 break;
1936 case AMDGPU_PP_SENSOR_MEM_TEMP:
1937 ret = sienna_cichlid_get_smu_metrics_data(smu,
1938 METRICS_TEMPERATURE_MEM,
1939 (uint32_t *)data);
1940 *size = 4;
1941 break;
1942 case AMDGPU_PP_SENSOR_GFX_MCLK:
1943 ret = sienna_cichlid_get_smu_metrics_data(smu,
1944 METRICS_CURR_UCLK,
1945 (uint32_t *)data);
1946 *(uint32_t *)data *= 100;
1947 *size = 4;
1948 break;
1949 case AMDGPU_PP_SENSOR_GFX_SCLK:
1950 ret = sienna_cichlid_get_smu_metrics_data(smu,
1951 METRICS_AVERAGE_GFXCLK,
1952 (uint32_t *)data);
1953 *(uint32_t *)data *= 100;
1954 *size = 4;
1955 break;
1956 case AMDGPU_PP_SENSOR_VDDGFX:
1957 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1958 *size = 4;
1959 break;
1960 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1961 if (amdgpu_ip_version(adev, MP1_HWIP, 0) !=
1962 IP_VERSION(11, 0, 7)) {
1963 ret = sienna_cichlid_get_smu_metrics_data(smu,
1964 METRICS_SS_APU_SHARE, (uint32_t *)data);
1965 *size = 4;
1966 } else {
1967 ret = -EOPNOTSUPP;
1968 }
1969 break;
1970 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1971 if (amdgpu_ip_version(adev, MP1_HWIP, 0) !=
1972 IP_VERSION(11, 0, 7)) {
1973 ret = sienna_cichlid_get_smu_metrics_data(smu,
1974 METRICS_SS_DGPU_SHARE, (uint32_t *)data);
1975 *size = 4;
1976 } else {
1977 ret = -EOPNOTSUPP;
1978 }
1979 break;
1980 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1981 default:
1982 ret = -EOPNOTSUPP;
1983 break;
1984 }
1985
1986 return ret;
1987}
1988
1989static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1990{
1991 struct amdgpu_device *adev = smu->adev;
1992 uint32_t upper32 = 0, lower32 = 0;
1993
1994 /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
1995 if (smu->smc_fw_version < 0x3A5300 ||
1996 amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7))
1997 return;
1998
1999 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
2000 goto out;
2001 if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
2002 goto out;
2003
2004out:
2005
2006 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
2007}
2008
2009static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2010{
2011 uint32_t num_discrete_levels = 0;
2012 uint16_t *dpm_levels = NULL;
2013 uint16_t i = 0;
2014 struct smu_table_context *table_context = &smu->smu_table;
2015 DpmDescriptor_t *table_member1;
2016 uint16_t *table_member2;
2017
2018 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2019 return -EINVAL;
2020
2021 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
2022 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
2023 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
2024 dpm_levels = table_member2;
2025
2026 if (num_discrete_levels == 0 || dpm_levels == NULL)
2027 return -EINVAL;
2028
2029 *num_states = num_discrete_levels;
2030 for (i = 0; i < num_discrete_levels; i++) {
2031 /* convert to khz */
2032 *clocks_in_khz = (*dpm_levels) * 1000;
2033 clocks_in_khz++;
2034 dpm_levels++;
2035 }
2036
2037 return 0;
2038}
2039
2040static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
2041 struct smu_temperature_range *range)
2042{
2043 struct smu_table_context *table_context = &smu->smu_table;
2044 struct smu_11_0_7_powerplay_table *powerplay_table =
2045 table_context->power_play_table;
2046 uint16_t *table_member;
2047 uint16_t temp_edge, temp_hotspot, temp_mem;
2048
2049 if (!range)
2050 return -EINVAL;
2051
2052 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2053
2054 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2055 temp_edge = table_member[TEMP_EDGE];
2056 temp_hotspot = table_member[TEMP_HOTSPOT];
2057 temp_mem = table_member[TEMP_MEM];
2058
2059 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2060 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2061 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2062 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2063 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2064 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2065 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2066 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
2067 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2068
2069 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2070
2071 return 0;
2072}
2073
2074static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2075 bool disable_memory_clock_switch)
2076{
2077 int ret = 0;
2078 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2079 (struct smu_11_0_max_sustainable_clocks *)
2080 smu->smu_table.max_sustainable_clocks;
2081 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2082 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2083
2084 if(smu->disable_uclk_switch == disable_memory_clock_switch)
2085 return 0;
2086
2087 if(disable_memory_clock_switch)
2088 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2089 else
2090 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2091
2092 if(!ret)
2093 smu->disable_uclk_switch = disable_memory_clock_switch;
2094
2095 return ret;
2096}
2097
2098static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2099 uint8_t pcie_gen_cap,
2100 uint8_t pcie_width_cap)
2101{
2102 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2103 struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
2104 uint8_t *table_member1, *table_member2;
2105 uint8_t min_gen_speed, max_gen_speed;
2106 uint8_t min_lane_width, max_lane_width;
2107 uint32_t smu_pcie_arg;
2108 int ret, i;
2109
2110 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2111 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2112
2113 min_gen_speed = max_t(uint8_t, 0, table_member1[0]);
2114 max_gen_speed = min(pcie_gen_cap, table_member1[1]);
2115 min_gen_speed = min_gen_speed > max_gen_speed ?
2116 max_gen_speed : min_gen_speed;
2117 min_lane_width = max_t(uint8_t, 1, table_member2[0]);
2118 max_lane_width = min(pcie_width_cap, table_member2[1]);
2119 min_lane_width = min_lane_width > max_lane_width ?
2120 max_lane_width : min_lane_width;
2121
2122 if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
2123 pcie_table->pcie_gen[0] = max_gen_speed;
2124 pcie_table->pcie_lane[0] = max_lane_width;
2125 } else {
2126 pcie_table->pcie_gen[0] = min_gen_speed;
2127 pcie_table->pcie_lane[0] = min_lane_width;
2128 }
2129 pcie_table->pcie_gen[1] = max_gen_speed;
2130 pcie_table->pcie_lane[1] = max_lane_width;
2131
2132 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2133 smu_pcie_arg = (i << 16 |
2134 pcie_table->pcie_gen[i] << 8 |
2135 pcie_table->pcie_lane[i]);
2136
2137 ret = smu_cmn_send_smc_msg_with_param(smu,
2138 SMU_MSG_OverridePcieParameters,
2139 smu_pcie_arg,
2140 NULL);
2141 if (ret)
2142 return ret;
2143 }
2144
2145 return 0;
2146}
2147
2148static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
2149 enum smu_clk_type clk_type,
2150 uint32_t *min, uint32_t *max)
2151{
2152 return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
2153}
2154
2155static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2156 OverDriveTable_t *od_table)
2157{
2158 struct amdgpu_device *adev = smu->adev;
2159
2160 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2161 od_table->GfxclkFmax);
2162 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2163 od_table->UclkFmax);
2164
2165 if (!((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) &&
2166 (smu->smc_fw_version < 0x003a2900)))
2167 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
2168}
2169
2170static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2171{
2172 OverDriveTable_t *od_table =
2173 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2174 OverDriveTable_t *boot_od_table =
2175 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2176 OverDriveTable_t *user_od_table =
2177 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2178 OverDriveTable_t user_od_table_bak;
2179 int ret = 0;
2180
2181 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2182 0, (void *)boot_od_table, false);
2183 if (ret) {
2184 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2185 return ret;
2186 }
2187
2188 sienna_cichlid_dump_od_table(smu, boot_od_table);
2189
2190 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2191
2192 /*
2193 * For S3/S4/Runpm resume, we need to setup those overdrive tables again,
2194 * but we have to preserve user defined values in "user_od_table".
2195 */
2196 if (!smu->adev->in_suspend) {
2197 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2198 smu->user_dpm_profile.user_od = false;
2199 } else if (smu->user_dpm_profile.user_od) {
2200 memcpy(&user_od_table_bak, user_od_table, sizeof(OverDriveTable_t));
2201 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2202 user_od_table->GfxclkFmin = user_od_table_bak.GfxclkFmin;
2203 user_od_table->GfxclkFmax = user_od_table_bak.GfxclkFmax;
2204 user_od_table->UclkFmin = user_od_table_bak.UclkFmin;
2205 user_od_table->UclkFmax = user_od_table_bak.UclkFmax;
2206 user_od_table->VddGfxOffset = user_od_table_bak.VddGfxOffset;
2207 }
2208
2209 return 0;
2210}
2211
2212static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2213 struct smu_11_0_7_overdrive_table *od_table,
2214 enum SMU_11_0_7_ODSETTING_ID setting,
2215 uint32_t value)
2216{
2217 if (value < od_table->min[setting]) {
2218 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2219 setting, value, od_table->min[setting]);
2220 return -EINVAL;
2221 }
2222 if (value > od_table->max[setting]) {
2223 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2224 setting, value, od_table->max[setting]);
2225 return -EINVAL;
2226 }
2227
2228 return 0;
2229}
2230
2231static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2232 enum PP_OD_DPM_TABLE_COMMAND type,
2233 long input[], uint32_t size)
2234{
2235 struct smu_table_context *table_context = &smu->smu_table;
2236 OverDriveTable_t *od_table =
2237 (OverDriveTable_t *)table_context->overdrive_table;
2238 struct smu_11_0_7_overdrive_table *od_settings =
2239 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2240 struct amdgpu_device *adev = smu->adev;
2241 enum SMU_11_0_7_ODSETTING_ID freq_setting;
2242 uint16_t *freq_ptr;
2243 int i, ret = 0;
2244
2245 if (!smu->od_enabled) {
2246 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2247 return -EINVAL;
2248 }
2249
2250 if (!smu->od_settings) {
2251 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2252 return -ENOENT;
2253 }
2254
2255 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2256 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2257 return -EINVAL;
2258 }
2259
2260 switch (type) {
2261 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2262 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2263 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2264 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2265 return -ENOTSUPP;
2266 }
2267
2268 for (i = 0; i < size; i += 2) {
2269 if (i + 2 > size) {
2270 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2271 return -EINVAL;
2272 }
2273
2274 switch (input[i]) {
2275 case 0:
2276 if (input[i + 1] > od_table->GfxclkFmax) {
2277 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2278 input[i + 1], od_table->GfxclkFmax);
2279 return -EINVAL;
2280 }
2281
2282 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2283 freq_ptr = &od_table->GfxclkFmin;
2284 break;
2285
2286 case 1:
2287 if (input[i + 1] < od_table->GfxclkFmin) {
2288 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2289 input[i + 1], od_table->GfxclkFmin);
2290 return -EINVAL;
2291 }
2292
2293 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2294 freq_ptr = &od_table->GfxclkFmax;
2295 break;
2296
2297 default:
2298 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2299 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2300 return -EINVAL;
2301 }
2302
2303 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2304 freq_setting, input[i + 1]);
2305 if (ret)
2306 return ret;
2307
2308 *freq_ptr = (uint16_t)input[i + 1];
2309 }
2310 break;
2311
2312 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2313 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2314 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2315 return -ENOTSUPP;
2316 }
2317
2318 for (i = 0; i < size; i += 2) {
2319 if (i + 2 > size) {
2320 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2321 return -EINVAL;
2322 }
2323
2324 switch (input[i]) {
2325 case 0:
2326 if (input[i + 1] > od_table->UclkFmax) {
2327 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2328 input[i + 1], od_table->UclkFmax);
2329 return -EINVAL;
2330 }
2331
2332 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2333 freq_ptr = &od_table->UclkFmin;
2334 break;
2335
2336 case 1:
2337 if (input[i + 1] < od_table->UclkFmin) {
2338 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2339 input[i + 1], od_table->UclkFmin);
2340 return -EINVAL;
2341 }
2342
2343 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2344 freq_ptr = &od_table->UclkFmax;
2345 break;
2346
2347 default:
2348 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2349 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2350 return -EINVAL;
2351 }
2352
2353 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2354 freq_setting, input[i + 1]);
2355 if (ret)
2356 return ret;
2357
2358 *freq_ptr = (uint16_t)input[i + 1];
2359 }
2360 break;
2361
2362 case PP_OD_RESTORE_DEFAULT_TABLE:
2363 memcpy(table_context->overdrive_table,
2364 table_context->boot_overdrive_table,
2365 sizeof(OverDriveTable_t));
2366 fallthrough;
2367
2368 case PP_OD_COMMIT_DPM_TABLE:
2369 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2370 sienna_cichlid_dump_od_table(smu, od_table);
2371 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2372 if (ret) {
2373 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2374 return ret;
2375 }
2376 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2377 smu->user_dpm_profile.user_od = true;
2378
2379 if (!memcmp(table_context->user_overdrive_table,
2380 table_context->boot_overdrive_table,
2381 sizeof(OverDriveTable_t)))
2382 smu->user_dpm_profile.user_od = false;
2383 }
2384 break;
2385
2386 case PP_OD_EDIT_VDDGFX_OFFSET:
2387 if (size != 1) {
2388 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2389 return -EINVAL;
2390 }
2391
2392 /*
2393 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2394 * and onwards SMU firmwares.
2395 */
2396 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2397 IP_VERSION(11, 0, 7)) &&
2398 (smu->smc_fw_version < 0x003a2900)) {
2399 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2400 "only by 58.41.0 and onwards SMU firmwares!\n");
2401 return -EOPNOTSUPP;
2402 }
2403
2404 od_table->VddGfxOffset = (int16_t)input[0];
2405
2406 sienna_cichlid_dump_od_table(smu, od_table);
2407 break;
2408
2409 default:
2410 return -ENOSYS;
2411 }
2412
2413 return ret;
2414}
2415
2416static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu)
2417{
2418 struct smu_table_context *table_context = &smu->smu_table;
2419 OverDriveTable_t *od_table = table_context->overdrive_table;
2420 OverDriveTable_t *user_od_table = table_context->user_overdrive_table;
2421 int res;
2422
2423 res = smu_v11_0_restore_user_od_settings(smu);
2424 if (res == 0)
2425 memcpy(od_table, user_od_table, sizeof(OverDriveTable_t));
2426
2427 return res;
2428}
2429
2430static int sienna_cichlid_run_btc(struct smu_context *smu)
2431{
2432 int res;
2433
2434 res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2435 if (res)
2436 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2437
2438 return res;
2439}
2440
2441static int sienna_cichlid_baco_enter(struct smu_context *smu)
2442{
2443 struct amdgpu_device *adev = smu->adev;
2444
2445 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2446 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2447 else
2448 return smu_v11_0_baco_enter(smu);
2449}
2450
2451static int sienna_cichlid_baco_exit(struct smu_context *smu)
2452{
2453 struct amdgpu_device *adev = smu->adev;
2454
2455 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2456 /* Wait for PMFW handling for the Dstate change */
2457 msleep(10);
2458 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2459 } else {
2460 return smu_v11_0_baco_exit(smu);
2461 }
2462}
2463
2464static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2465{
2466 struct amdgpu_device *adev = smu->adev;
2467 uint32_t val;
2468 uint32_t smu_version;
2469 int ret;
2470
2471 /**
2472 * SRIOV env will not support SMU mode1 reset
2473 * PM FW support mode1 reset from 58.26
2474 */
2475 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2476 if (ret)
2477 return false;
2478
2479 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2480 return false;
2481
2482 /**
2483 * mode1 reset relies on PSP, so we should check if
2484 * PSP is alive.
2485 */
2486 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2487 return val != 0x0;
2488}
2489
2490static void beige_goby_dump_pptable(struct smu_context *smu)
2491{
2492 struct smu_table_context *table_context = &smu->smu_table;
2493 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2494 int i;
2495
2496 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2497
2498 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2499 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2500 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2501
2502 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2503 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2504 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2505 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2506 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2507 }
2508
2509 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2510 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2511 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2512 }
2513
2514 for (i = 0; i < TEMP_COUNT; i++) {
2515 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2516 }
2517
2518 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2519 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2520 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2521 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2522 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2523
2524 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2525 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2526 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2527 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2528 }
2529 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2530
2531 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2532
2533 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2534 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2535 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2536 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2537
2538 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2539
2540 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2541
2542 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2543 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2544 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2545 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2546
2547 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2548 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2549
2550 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2551 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2552 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2553 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2554 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2555 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2556 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2557 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2558
2559 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2560 " .VoltageMode = 0x%02x\n"
2561 " .SnapToDiscrete = 0x%02x\n"
2562 " .NumDiscreteLevels = 0x%02x\n"
2563 " .padding = 0x%02x\n"
2564 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2565 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2566 " .SsFmin = 0x%04x\n"
2567 " .Padding_16 = 0x%04x\n",
2568 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2569 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2570 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2571 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2572 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2573 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2574 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2575 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2576 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2577 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2578 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2579
2580 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2581 " .VoltageMode = 0x%02x\n"
2582 " .SnapToDiscrete = 0x%02x\n"
2583 " .NumDiscreteLevels = 0x%02x\n"
2584 " .padding = 0x%02x\n"
2585 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2586 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2587 " .SsFmin = 0x%04x\n"
2588 " .Padding_16 = 0x%04x\n",
2589 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2590 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2591 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2592 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2593 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2594 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2595 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2596 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2597 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2598 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2599 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2600
2601 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2602 " .VoltageMode = 0x%02x\n"
2603 " .SnapToDiscrete = 0x%02x\n"
2604 " .NumDiscreteLevels = 0x%02x\n"
2605 " .padding = 0x%02x\n"
2606 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2607 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2608 " .SsFmin = 0x%04x\n"
2609 " .Padding_16 = 0x%04x\n",
2610 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2611 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2612 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2613 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2614 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2615 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2616 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2617 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2618 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2619 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2620 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2621
2622 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2623 " .VoltageMode = 0x%02x\n"
2624 " .SnapToDiscrete = 0x%02x\n"
2625 " .NumDiscreteLevels = 0x%02x\n"
2626 " .padding = 0x%02x\n"
2627 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2628 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2629 " .SsFmin = 0x%04x\n"
2630 " .Padding_16 = 0x%04x\n",
2631 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2632 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2633 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2634 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2635 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2636 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2637 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2638 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2639 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2640 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2641 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2642
2643 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2644 " .VoltageMode = 0x%02x\n"
2645 " .SnapToDiscrete = 0x%02x\n"
2646 " .NumDiscreteLevels = 0x%02x\n"
2647 " .padding = 0x%02x\n"
2648 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2649 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2650 " .SsFmin = 0x%04x\n"
2651 " .Padding_16 = 0x%04x\n",
2652 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2653 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2654 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2655 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2656 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2657 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2658 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2659 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2660 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2661 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2662 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2663
2664 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2665 " .VoltageMode = 0x%02x\n"
2666 " .SnapToDiscrete = 0x%02x\n"
2667 " .NumDiscreteLevels = 0x%02x\n"
2668 " .padding = 0x%02x\n"
2669 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2670 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2671 " .SsFmin = 0x%04x\n"
2672 " .Padding_16 = 0x%04x\n",
2673 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2674 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2675 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2676 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2677 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2678 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2679 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2680 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2681 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2682 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2683 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2684
2685 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2686 " .VoltageMode = 0x%02x\n"
2687 " .SnapToDiscrete = 0x%02x\n"
2688 " .NumDiscreteLevels = 0x%02x\n"
2689 " .padding = 0x%02x\n"
2690 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2691 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2692 " .SsFmin = 0x%04x\n"
2693 " .Padding_16 = 0x%04x\n",
2694 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2695 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2696 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2697 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2698 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2699 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2700 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2701 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2702 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2703 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2704 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2705
2706 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2707 " .VoltageMode = 0x%02x\n"
2708 " .SnapToDiscrete = 0x%02x\n"
2709 " .NumDiscreteLevels = 0x%02x\n"
2710 " .padding = 0x%02x\n"
2711 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2712 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2713 " .SsFmin = 0x%04x\n"
2714 " .Padding_16 = 0x%04x\n",
2715 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2716 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2717 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2718 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2719 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2720 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2721 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2722 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2723 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2724 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2725 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2726
2727 dev_info(smu->adev->dev, "FreqTableGfx\n");
2728 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2729 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2730
2731 dev_info(smu->adev->dev, "FreqTableVclk\n");
2732 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2733 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2734
2735 dev_info(smu->adev->dev, "FreqTableDclk\n");
2736 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2737 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2738
2739 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2740 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2741 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2742
2743 dev_info(smu->adev->dev, "FreqTableUclk\n");
2744 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2745 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2746
2747 dev_info(smu->adev->dev, "FreqTableFclk\n");
2748 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2749 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2750
2751 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2752 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2753 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2754 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2755 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2756 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2757 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2758 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2759 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2760
2761 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2762 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2763 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2764
2765 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2766 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2767
2768 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2769 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2770 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2771
2772 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2773 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2774 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2775
2776 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2777 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2778 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2779
2780 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2781 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2782 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2783
2784 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2785 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2786 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2787 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2788 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2789
2790 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2791
2792 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2793 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2794 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2795 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2796 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2797 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2798 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2799 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2800 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2801 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2802 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2803
2804 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2805 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2806 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2807 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2808 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2809 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2810
2811 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2812 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2813 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2814 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2815 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2816
2817 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2818 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2819 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2820
2821 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2822 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2823 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2824 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2825
2826 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2827 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2828 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2829
2830 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2831 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2832 pptable->UclkDpmSrcFreqRange.Fmin);
2833 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2834 pptable->UclkDpmSrcFreqRange.Fmax);
2835 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2836 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2837 pptable->UclkDpmTargFreqRange.Fmin);
2838 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2839 pptable->UclkDpmTargFreqRange.Fmax);
2840 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2841 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2842
2843 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2844 for (i = 0; i < NUM_LINK_LEVELS; i++)
2845 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2846
2847 dev_info(smu->adev->dev, "PcieLaneCount\n");
2848 for (i = 0; i < NUM_LINK_LEVELS; i++)
2849 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2850
2851 dev_info(smu->adev->dev, "LclkFreq\n");
2852 for (i = 0; i < NUM_LINK_LEVELS; i++)
2853 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2854
2855 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2856 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2857
2858 dev_info(smu->adev->dev, "FanGain\n");
2859 for (i = 0; i < TEMP_COUNT; i++)
2860 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2861
2862 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2863 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2864 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2865 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2866 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2867 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2868 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2869 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2870 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2871 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2872 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2873 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2874
2875 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2876 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2877 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2878 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2879
2880 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2881 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2882 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2883 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2884
2885 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2886 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2887 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2888 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2889 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2890 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2891 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2892 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2893 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2894 pptable->dBtcGbGfxPll.a,
2895 pptable->dBtcGbGfxPll.b,
2896 pptable->dBtcGbGfxPll.c);
2897 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2898 pptable->dBtcGbGfxDfll.a,
2899 pptable->dBtcGbGfxDfll.b,
2900 pptable->dBtcGbGfxDfll.c);
2901 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2902 pptable->dBtcGbSoc.a,
2903 pptable->dBtcGbSoc.b,
2904 pptable->dBtcGbSoc.c);
2905 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2906 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2907 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2908 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2909 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2910 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2911
2912 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2913 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2914 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2915 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2916 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2917 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2918 }
2919
2920 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2921 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2922 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2923 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2924 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2925 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2926 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2927 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2928
2929 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2930 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2931
2932 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2933 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2934 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2935 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2936
2937 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2938 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2939 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2940 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2941
2942 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2943 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2944
2945 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2946 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2947 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2948 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2949 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2950
2951 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2952 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2953 pptable->ReservedEquation0.a,
2954 pptable->ReservedEquation0.b,
2955 pptable->ReservedEquation0.c);
2956 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2957 pptable->ReservedEquation1.a,
2958 pptable->ReservedEquation1.b,
2959 pptable->ReservedEquation1.c);
2960 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2961 pptable->ReservedEquation2.a,
2962 pptable->ReservedEquation2.b,
2963 pptable->ReservedEquation2.c);
2964 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2965 pptable->ReservedEquation3.a,
2966 pptable->ReservedEquation3.b,
2967 pptable->ReservedEquation3.c);
2968
2969 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2970 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2971 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2972 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2973 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2974 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2975 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2976 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2977
2978 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2979 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2980 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2981 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2982 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2983 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2984
2985 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2986 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2987 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2988 pptable->I2cControllers[i].Enabled);
2989 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2990 pptable->I2cControllers[i].Speed);
2991 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2992 pptable->I2cControllers[i].SlaveAddress);
2993 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2994 pptable->I2cControllers[i].ControllerPort);
2995 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2996 pptable->I2cControllers[i].ControllerName);
2997 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2998 pptable->I2cControllers[i].ThermalThrotter);
2999 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
3000 pptable->I2cControllers[i].I2cProtocol);
3001 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
3002 pptable->I2cControllers[i].PaddingConfig);
3003 }
3004
3005 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3006 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3007 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3008 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3009
3010 dev_info(smu->adev->dev, "Board Parameters:\n");
3011 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3012 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3013 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3014 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3015 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3016 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3017 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3018 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3019
3020 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3021 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3022 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3023
3024 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3025 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3026 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3027
3028 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3029 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3030 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3031
3032 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3033 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3034 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3035
3036 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3037
3038 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3039 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3040 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3041 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3042 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3043 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3044 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3045 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3046 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3047 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3048 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3049 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3050 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3051 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3052 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3053 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3054
3055 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3056 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3057 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3058
3059 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3060 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3061 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3062
3063 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3064 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3065
3066 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3067 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3068 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3069
3070 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3071 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3072 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3073 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3074 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3075
3076 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3077 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3078
3079 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3080 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3081 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3082 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3083 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3084 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3085 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3086 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3087 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3088 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3089 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3090 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3091
3092 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3093 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3094 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3095 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3096
3097 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3098 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3099 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3100 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3101 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3102 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3103 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3104 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3105 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3106 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3107 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3108
3109 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3110 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3111 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3112 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3113 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3114 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3115 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3116 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3117}
3118
3119static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3120{
3121 struct smu_table_context *table_context = &smu->smu_table;
3122 PPTable_t *pptable = table_context->driver_pptable;
3123 int i;
3124
3125 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
3126 IP_VERSION(11, 0, 13)) {
3127 beige_goby_dump_pptable(smu);
3128 return;
3129 }
3130
3131 dev_info(smu->adev->dev, "Dumped PPTable:\n");
3132
3133 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3134 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3135 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
3136
3137 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
3138 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3139 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3140 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3141 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
3142 }
3143
3144 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
3145 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3146 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
3147 }
3148
3149 for (i = 0; i < TEMP_COUNT; i++) {
3150 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
3151 }
3152
3153 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3154 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3155 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3156 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3157 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
3158
3159 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
3160 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
3161 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3162 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
3163 }
3164 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3165
3166 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3167
3168 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3169 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3170 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3171 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3172
3173 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3174 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3175
3176 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3177 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3178 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3179 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3180
3181 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3182 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3183 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3184 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3185
3186 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3187 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3188
3189 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3190 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3191 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3192 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3193 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3194 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3195 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3196 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3197
3198 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
3199 " .VoltageMode = 0x%02x\n"
3200 " .SnapToDiscrete = 0x%02x\n"
3201 " .NumDiscreteLevels = 0x%02x\n"
3202 " .padding = 0x%02x\n"
3203 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3204 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3205 " .SsFmin = 0x%04x\n"
3206 " .Padding_16 = 0x%04x\n",
3207 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3208 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3209 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3210 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3211 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3212 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3213 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3214 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3215 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3216 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3217 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3218
3219 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
3220 " .VoltageMode = 0x%02x\n"
3221 " .SnapToDiscrete = 0x%02x\n"
3222 " .NumDiscreteLevels = 0x%02x\n"
3223 " .padding = 0x%02x\n"
3224 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3225 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3226 " .SsFmin = 0x%04x\n"
3227 " .Padding_16 = 0x%04x\n",
3228 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3229 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3230 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3231 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3232 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3233 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3234 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3235 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3236 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3237 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3238 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3239
3240 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
3241 " .VoltageMode = 0x%02x\n"
3242 " .SnapToDiscrete = 0x%02x\n"
3243 " .NumDiscreteLevels = 0x%02x\n"
3244 " .padding = 0x%02x\n"
3245 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3246 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3247 " .SsFmin = 0x%04x\n"
3248 " .Padding_16 = 0x%04x\n",
3249 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3250 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3251 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3252 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3253 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3254 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3255 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3256 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3257 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3258 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3259 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3260
3261 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3262 " .VoltageMode = 0x%02x\n"
3263 " .SnapToDiscrete = 0x%02x\n"
3264 " .NumDiscreteLevels = 0x%02x\n"
3265 " .padding = 0x%02x\n"
3266 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3267 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3268 " .SsFmin = 0x%04x\n"
3269 " .Padding_16 = 0x%04x\n",
3270 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3271 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3272 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3273 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3274 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3275 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3276 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3277 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3278 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3279 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3280 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3281
3282 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3283 " .VoltageMode = 0x%02x\n"
3284 " .SnapToDiscrete = 0x%02x\n"
3285 " .NumDiscreteLevels = 0x%02x\n"
3286 " .padding = 0x%02x\n"
3287 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3288 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3289 " .SsFmin = 0x%04x\n"
3290 " .Padding_16 = 0x%04x\n",
3291 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3292 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3293 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3294 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3295 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3296 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3297 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3298 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3299 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3300 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3301 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3302
3303 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3304 " .VoltageMode = 0x%02x\n"
3305 " .SnapToDiscrete = 0x%02x\n"
3306 " .NumDiscreteLevels = 0x%02x\n"
3307 " .padding = 0x%02x\n"
3308 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3309 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3310 " .SsFmin = 0x%04x\n"
3311 " .Padding_16 = 0x%04x\n",
3312 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3313 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3314 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3315 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3316 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3317 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3318 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3319 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3320 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3321 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3322 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3323
3324 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3325 " .VoltageMode = 0x%02x\n"
3326 " .SnapToDiscrete = 0x%02x\n"
3327 " .NumDiscreteLevels = 0x%02x\n"
3328 " .padding = 0x%02x\n"
3329 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3330 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3331 " .SsFmin = 0x%04x\n"
3332 " .Padding_16 = 0x%04x\n",
3333 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3334 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3335 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3336 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3337 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3338 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3339 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3340 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3341 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3342 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3343 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3344
3345 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3346 " .VoltageMode = 0x%02x\n"
3347 " .SnapToDiscrete = 0x%02x\n"
3348 " .NumDiscreteLevels = 0x%02x\n"
3349 " .padding = 0x%02x\n"
3350 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3351 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3352 " .SsFmin = 0x%04x\n"
3353 " .Padding_16 = 0x%04x\n",
3354 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3355 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3356 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3357 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3358 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3359 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3360 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3361 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3362 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3363 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3364 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3365
3366 dev_info(smu->adev->dev, "FreqTableGfx\n");
3367 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3368 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3369
3370 dev_info(smu->adev->dev, "FreqTableVclk\n");
3371 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3372 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3373
3374 dev_info(smu->adev->dev, "FreqTableDclk\n");
3375 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3376 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3377
3378 dev_info(smu->adev->dev, "FreqTableSocclk\n");
3379 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3380 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3381
3382 dev_info(smu->adev->dev, "FreqTableUclk\n");
3383 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3384 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3385
3386 dev_info(smu->adev->dev, "FreqTableFclk\n");
3387 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3388 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3389
3390 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3391 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3392 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3393 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3394 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3395 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3396 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3397 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3398 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3399
3400 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3401 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3402 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3403
3404 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3405 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3406
3407 dev_info(smu->adev->dev, "Mp0clkFreq\n");
3408 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3409 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3410
3411 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3412 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3413 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3414
3415 dev_info(smu->adev->dev, "MemVddciVoltage\n");
3416 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3417 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3418
3419 dev_info(smu->adev->dev, "MemMvddVoltage\n");
3420 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3421 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3422
3423 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3424 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3425 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3426 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3427 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3428
3429 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3430
3431 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3432 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3433 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3434 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3435 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3436 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3437 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3438 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3439 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3440 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3441 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3442
3443 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3444 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3445 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3446 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3447 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3448 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3449
3450 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3451 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3452 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3453 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3454 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3455
3456 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3457 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3458 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3459
3460 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3461 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3462 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3463 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3464
3465 dev_info(smu->adev->dev, "UclkDpmPstates\n");
3466 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3467 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3468
3469 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3470 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3471 pptable->UclkDpmSrcFreqRange.Fmin);
3472 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3473 pptable->UclkDpmSrcFreqRange.Fmax);
3474 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3475 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3476 pptable->UclkDpmTargFreqRange.Fmin);
3477 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3478 pptable->UclkDpmTargFreqRange.Fmax);
3479 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3480 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3481
3482 dev_info(smu->adev->dev, "PcieGenSpeed\n");
3483 for (i = 0; i < NUM_LINK_LEVELS; i++)
3484 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3485
3486 dev_info(smu->adev->dev, "PcieLaneCount\n");
3487 for (i = 0; i < NUM_LINK_LEVELS; i++)
3488 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3489
3490 dev_info(smu->adev->dev, "LclkFreq\n");
3491 for (i = 0; i < NUM_LINK_LEVELS; i++)
3492 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3493
3494 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3495 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3496
3497 dev_info(smu->adev->dev, "FanGain\n");
3498 for (i = 0; i < TEMP_COUNT; i++)
3499 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3500
3501 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3502 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3503 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3504 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3505 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3506 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3507 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3508 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3509 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3510 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3511 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3512 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3513
3514 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3515 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3516 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3517 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3518
3519 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3520 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3521 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3522 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3523
3524 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3525 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3526 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3527 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3528 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3529 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3530 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3531 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3532 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3533 pptable->dBtcGbGfxPll.a,
3534 pptable->dBtcGbGfxPll.b,
3535 pptable->dBtcGbGfxPll.c);
3536 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3537 pptable->dBtcGbGfxDfll.a,
3538 pptable->dBtcGbGfxDfll.b,
3539 pptable->dBtcGbGfxDfll.c);
3540 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3541 pptable->dBtcGbSoc.a,
3542 pptable->dBtcGbSoc.b,
3543 pptable->dBtcGbSoc.c);
3544 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3545 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3546 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3547 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3548 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3549 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3550
3551 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3552 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3553 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
3554 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3555 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
3556 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3557 }
3558
3559 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3560 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3561 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3562 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3563 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3564 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3565 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3566 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3567
3568 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3569 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3570
3571 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3572 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3573 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3574 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3575
3576 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3577 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3578 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3579 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3580
3581 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3582 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3583
3584 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3585 for (i = 0; i < NUM_XGMI_LEVELS; i++)
3586 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3587 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3588 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3589
3590 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3591 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3592 pptable->ReservedEquation0.a,
3593 pptable->ReservedEquation0.b,
3594 pptable->ReservedEquation0.c);
3595 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3596 pptable->ReservedEquation1.a,
3597 pptable->ReservedEquation1.b,
3598 pptable->ReservedEquation1.c);
3599 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3600 pptable->ReservedEquation2.a,
3601 pptable->ReservedEquation2.b,
3602 pptable->ReservedEquation2.c);
3603 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3604 pptable->ReservedEquation3.a,
3605 pptable->ReservedEquation3.b,
3606 pptable->ReservedEquation3.c);
3607
3608 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3609 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3610 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3611 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3612 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3613 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3614 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3615 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3616
3617 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3618 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3619 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3620 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3621 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3622 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3623
3624 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3625 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3626 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
3627 pptable->I2cControllers[i].Enabled);
3628 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
3629 pptable->I2cControllers[i].Speed);
3630 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
3631 pptable->I2cControllers[i].SlaveAddress);
3632 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
3633 pptable->I2cControllers[i].ControllerPort);
3634 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
3635 pptable->I2cControllers[i].ControllerName);
3636 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
3637 pptable->I2cControllers[i].ThermalThrotter);
3638 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
3639 pptable->I2cControllers[i].I2cProtocol);
3640 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
3641 pptable->I2cControllers[i].PaddingConfig);
3642 }
3643
3644 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3645 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3646 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3647 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3648
3649 dev_info(smu->adev->dev, "Board Parameters:\n");
3650 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3651 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3652 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3653 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3654 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3655 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3656 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3657 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3658
3659 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3660 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3661 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3662
3663 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3664 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3665 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3666
3667 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3668 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3669 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3670
3671 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3672 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3673 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3674
3675 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3676
3677 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3678 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3679 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3680 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3681 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3682 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3683 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3684 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3685 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3686 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3687 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3688 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3689 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3690 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3691 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3692 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3693
3694 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3695 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3696 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3697
3698 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3699 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3700 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3701
3702 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3703 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3704
3705 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3706 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3707 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3708
3709 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3710 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3711 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3712 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3713 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3714
3715 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3716 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3717
3718 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3719 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3720 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3721 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3722 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3723 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3724 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3725 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3726 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3727 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3728 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3729 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3730
3731 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3732 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3733 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3734 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3735
3736 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3737 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3738 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3739 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3740 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3741 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3742 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3743 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3744 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3745 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3746 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3747
3748 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3749 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3750 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3751 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3752 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3753 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3754 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3755 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3756}
3757
3758static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3759 struct i2c_msg *msg, int num_msgs)
3760{
3761 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3762 struct amdgpu_device *adev = smu_i2c->adev;
3763 struct smu_context *smu = adev->powerplay.pp_handle;
3764 struct smu_table_context *smu_table = &smu->smu_table;
3765 struct smu_table *table = &smu_table->driver_table;
3766 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3767 int i, j, r, c;
3768 u16 dir;
3769
3770 if (!adev->pm.dpm_enabled)
3771 return -EBUSY;
3772
3773 req = kzalloc(sizeof(*req), GFP_KERNEL);
3774 if (!req)
3775 return -ENOMEM;
3776
3777 req->I2CcontrollerPort = smu_i2c->port;
3778 req->I2CSpeed = I2C_SPEED_FAST_400K;
3779 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3780 dir = msg[0].flags & I2C_M_RD;
3781
3782 for (c = i = 0; i < num_msgs; i++) {
3783 for (j = 0; j < msg[i].len; j++, c++) {
3784 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3785
3786 if (!(msg[i].flags & I2C_M_RD)) {
3787 /* write */
3788 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3789 cmd->ReadWriteData = msg[i].buf[j];
3790 }
3791
3792 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3793 /* The direction changes.
3794 */
3795 dir = msg[i].flags & I2C_M_RD;
3796 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3797 }
3798
3799 req->NumCmds++;
3800
3801 /*
3802 * Insert STOP if we are at the last byte of either last
3803 * message for the transaction or the client explicitly
3804 * requires a STOP at this particular message.
3805 */
3806 if ((j == msg[i].len - 1) &&
3807 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3808 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3809 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3810 }
3811 }
3812 }
3813 mutex_lock(&adev->pm.mutex);
3814 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3815 if (r)
3816 goto fail;
3817
3818 for (c = i = 0; i < num_msgs; i++) {
3819 if (!(msg[i].flags & I2C_M_RD)) {
3820 c += msg[i].len;
3821 continue;
3822 }
3823 for (j = 0; j < msg[i].len; j++, c++) {
3824 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3825
3826 msg[i].buf[j] = cmd->ReadWriteData;
3827 }
3828 }
3829 r = num_msgs;
3830fail:
3831 mutex_unlock(&adev->pm.mutex);
3832 kfree(req);
3833 return r;
3834}
3835
3836static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3837{
3838 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3839}
3840
3841
3842static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3843 .master_xfer = sienna_cichlid_i2c_xfer,
3844 .functionality = sienna_cichlid_i2c_func,
3845};
3846
3847static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3848 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3849 .max_read_len = MAX_SW_I2C_COMMANDS,
3850 .max_write_len = MAX_SW_I2C_COMMANDS,
3851 .max_comb_1st_msg_len = 2,
3852 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3853};
3854
3855static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
3856{
3857 struct amdgpu_device *adev = smu->adev;
3858 int res, i;
3859
3860 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3861 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3862 struct i2c_adapter *control = &smu_i2c->adapter;
3863
3864 smu_i2c->adev = adev;
3865 smu_i2c->port = i;
3866 mutex_init(&smu_i2c->mutex);
3867 control->owner = THIS_MODULE;
3868 control->class = I2C_CLASS_HWMON;
3869 control->dev.parent = &adev->pdev->dev;
3870 control->algo = &sienna_cichlid_i2c_algo;
3871 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3872 control->quirks = &sienna_cichlid_i2c_control_quirks;
3873 i2c_set_adapdata(control, smu_i2c);
3874
3875 res = i2c_add_adapter(control);
3876 if (res) {
3877 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3878 goto Out_err;
3879 }
3880 }
3881 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3882 /* XXX ideally this would be something in a vbios data table */
3883 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3884 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3885
3886 return 0;
3887Out_err:
3888 for ( ; i >= 0; i--) {
3889 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3890 struct i2c_adapter *control = &smu_i2c->adapter;
3891
3892 i2c_del_adapter(control);
3893 }
3894 return res;
3895}
3896
3897static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
3898{
3899 struct amdgpu_device *adev = smu->adev;
3900 int i;
3901
3902 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3903 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3904 struct i2c_adapter *control = &smu_i2c->adapter;
3905
3906 i2c_del_adapter(control);
3907 }
3908 adev->pm.ras_eeprom_i2c_bus = NULL;
3909 adev->pm.fru_eeprom_i2c_bus = NULL;
3910}
3911
3912static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3913 void **table)
3914{
3915 struct smu_table_context *smu_table = &smu->smu_table;
3916 struct gpu_metrics_v1_3 *gpu_metrics =
3917 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3918 SmuMetricsExternal_t metrics_external;
3919 SmuMetrics_t *metrics =
3920 &(metrics_external.SmuMetrics);
3921 SmuMetrics_V2_t *metrics_v2 =
3922 &(metrics_external.SmuMetrics_V2);
3923 SmuMetrics_V3_t *metrics_v3 =
3924 &(metrics_external.SmuMetrics_V3);
3925 struct amdgpu_device *adev = smu->adev;
3926 bool use_metrics_v2 = false;
3927 bool use_metrics_v3 = false;
3928 uint16_t average_gfx_activity;
3929 int ret = 0;
3930
3931 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
3932 case IP_VERSION(11, 0, 7):
3933 if (smu->smc_fw_version >= 0x3A4900)
3934 use_metrics_v3 = true;
3935 else if (smu->smc_fw_version >= 0x3A4300)
3936 use_metrics_v2 = true;
3937 break;
3938 case IP_VERSION(11, 0, 11):
3939 if (smu->smc_fw_version >= 0x412D00)
3940 use_metrics_v2 = true;
3941 break;
3942 case IP_VERSION(11, 0, 12):
3943 if (smu->smc_fw_version >= 0x3B2300)
3944 use_metrics_v2 = true;
3945 break;
3946 case IP_VERSION(11, 0, 13):
3947 if (smu->smc_fw_version >= 0x491100)
3948 use_metrics_v2 = true;
3949 break;
3950 default:
3951 break;
3952 }
3953
3954 ret = smu_cmn_get_metrics_table(smu,
3955 &metrics_external,
3956 true);
3957 if (ret)
3958 return ret;
3959
3960 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3961
3962 gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
3963 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3964 gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
3965 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3966 gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
3967 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3968 gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
3969 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3970 gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
3971 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3972 gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
3973 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3974
3975 gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3976 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3977 gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
3978 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3979 gpu_metrics->average_mm_activity = use_metrics_v3 ?
3980 (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
3981 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3982
3983 gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
3984 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3985 gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
3986 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3987
3988 if (metrics->CurrGfxVoltageOffset)
3989 gpu_metrics->voltage_gfx =
3990 (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3991 if (metrics->CurrMemVidOffset)
3992 gpu_metrics->voltage_mem =
3993 (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3994 if (metrics->CurrSocVoltageOffset)
3995 gpu_metrics->voltage_soc =
3996 (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3997
3998 average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3999 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
4000 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
4001 gpu_metrics->average_gfxclk_frequency =
4002 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
4003 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
4004 metrics->AverageGfxclkFrequencyPostDs;
4005 else
4006 gpu_metrics->average_gfxclk_frequency =
4007 use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
4008 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
4009 metrics->AverageGfxclkFrequencyPreDs;
4010
4011 gpu_metrics->average_uclk_frequency =
4012 use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
4013 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
4014 metrics->AverageUclkFrequencyPostDs;
4015 gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
4016 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
4017 gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
4018 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
4019 gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
4020 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
4021 gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
4022 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
4023
4024 gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
4025 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
4026 gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
4027 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
4028 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
4029 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
4030 gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
4031 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
4032 gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
4033 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
4034 gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
4035 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
4036 gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
4037 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
4038
4039 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
4040 gpu_metrics->indep_throttle_status =
4041 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
4042 sienna_cichlid_throttler_map);
4043
4044 gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
4045 use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
4046
4047 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)) &&
4048 smu->smc_fw_version > 0x003A1E00) ||
4049 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11)) &&
4050 smu->smc_fw_version > 0x00410400)) {
4051 gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
4052 use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
4053 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
4054 use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
4055 } else {
4056 gpu_metrics->pcie_link_width =
4057 smu_v11_0_get_current_pcie_link_width(smu);
4058 gpu_metrics->pcie_link_speed =
4059 smu_v11_0_get_current_pcie_link_speed(smu);
4060 }
4061
4062 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
4063
4064 *table = (void *)gpu_metrics;
4065
4066 return sizeof(struct gpu_metrics_v1_3);
4067}
4068
4069static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
4070{
4071 int ret = 0;
4072
4073 if (smu->smc_fw_version < SUPPORT_ECCTABLE_SMU_VERSION)
4074 ret = -EOPNOTSUPP;
4075
4076 return ret;
4077}
4078
4079static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4080 void *table)
4081{
4082 struct smu_table_context *smu_table = &smu->smu_table;
4083 EccInfoTable_t *ecc_table = NULL;
4084 struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4085 int i, ret = 0;
4086 struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4087
4088 ret = sienna_cichlid_check_ecc_table_support(smu);
4089 if (ret)
4090 return ret;
4091
4092 ret = smu_cmn_update_table(smu,
4093 SMU_TABLE_ECCINFO,
4094 0,
4095 smu_table->ecc_table,
4096 false);
4097 if (ret) {
4098 dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4099 return ret;
4100 }
4101
4102 ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4103
4104 for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4105 ecc_info_per_channel = &(eccinfo->ecc[i]);
4106 ecc_info_per_channel->ce_count_lo_chip =
4107 ecc_table->EccInfo[i].ce_count_lo_chip;
4108 ecc_info_per_channel->ce_count_hi_chip =
4109 ecc_table->EccInfo[i].ce_count_hi_chip;
4110 ecc_info_per_channel->mca_umc_status =
4111 ecc_table->EccInfo[i].mca_umc_status;
4112 ecc_info_per_channel->mca_umc_addr =
4113 ecc_table->EccInfo[i].mca_umc_addr;
4114 }
4115
4116 return ret;
4117}
4118static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4119{
4120 uint16_t *mgpu_fan_boost_limit_rpm;
4121
4122 GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
4123 /*
4124 * Skip the MGpuFanBoost setting for those ASICs
4125 * which do not support it
4126 */
4127 if (*mgpu_fan_boost_limit_rpm == 0)
4128 return 0;
4129
4130 return smu_cmn_send_smc_msg_with_param(smu,
4131 SMU_MSG_SetMGpuFanBoostLimitRpm,
4132 0,
4133 NULL);
4134}
4135
4136static int sienna_cichlid_gpo_control(struct smu_context *smu,
4137 bool enablement)
4138{
4139 int ret = 0;
4140
4141
4142 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
4143
4144 if (enablement) {
4145 if (smu->smc_fw_version < 0x003a2500) {
4146 ret = smu_cmn_send_smc_msg_with_param(smu,
4147 SMU_MSG_SetGpoFeaturePMask,
4148 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4149 NULL);
4150 } else {
4151 ret = smu_cmn_send_smc_msg_with_param(smu,
4152 SMU_MSG_DisallowGpo,
4153 0,
4154 NULL);
4155 }
4156 } else {
4157 if (smu->smc_fw_version < 0x003a2500) {
4158 ret = smu_cmn_send_smc_msg_with_param(smu,
4159 SMU_MSG_SetGpoFeaturePMask,
4160 0,
4161 NULL);
4162 } else {
4163 ret = smu_cmn_send_smc_msg_with_param(smu,
4164 SMU_MSG_DisallowGpo,
4165 1,
4166 NULL);
4167 }
4168 }
4169 }
4170
4171 return ret;
4172}
4173
4174static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4175{
4176 /*
4177 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4178 * onwards PMFWs.
4179 */
4180 if (smu->smc_fw_version < 0x003A2D00)
4181 return 0;
4182
4183 return smu_cmn_send_smc_msg_with_param(smu,
4184 SMU_MSG_Enable2ndUSB20Port,
4185 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4186 1 : 0,
4187 NULL);
4188}
4189
4190static int sienna_cichlid_system_features_control(struct smu_context *smu,
4191 bool en)
4192{
4193 int ret = 0;
4194
4195 if (en) {
4196 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4197 if (ret)
4198 return ret;
4199 }
4200
4201 return smu_v11_0_system_features_control(smu, en);
4202}
4203
4204static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4205 enum pp_mp1_state mp1_state)
4206{
4207 int ret;
4208
4209 switch (mp1_state) {
4210 case PP_MP1_STATE_UNLOAD:
4211 ret = smu_cmn_set_mp1_state(smu, mp1_state);
4212 break;
4213 default:
4214 /* Ignore others */
4215 ret = 0;
4216 }
4217
4218 return ret;
4219}
4220
4221static void sienna_cichlid_stb_init(struct smu_context *smu)
4222{
4223 struct amdgpu_device *adev = smu->adev;
4224 uint32_t reg;
4225
4226 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4227 smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4228
4229 /* STB is disabled */
4230 if (!smu->stb_context.enabled)
4231 return;
4232
4233 spin_lock_init(&smu->stb_context.lock);
4234
4235 /* STB buffer size in bytes as function of FIFO depth */
4236 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4237 smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4238 smu->stb_context.stb_buf_size *= SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4239
4240 dev_info(smu->adev->dev, "STB initialized to %d entries",
4241 smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4242
4243}
4244
4245static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4246 struct config_table_setting *table)
4247{
4248 struct amdgpu_device *adev = smu->adev;
4249
4250 if (!table)
4251 return -EINVAL;
4252
4253 table->gfxclk_average_tau = 10;
4254 table->socclk_average_tau = 10;
4255 table->fclk_average_tau = 10;
4256 table->uclk_average_tau = 10;
4257 table->gfx_activity_average_tau = 10;
4258 table->mem_activity_average_tau = 10;
4259 table->socket_power_average_tau = 100;
4260 if (amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(11, 0, 7))
4261 table->apu_socket_power_average_tau = 100;
4262
4263 return 0;
4264}
4265
4266static int sienna_cichlid_set_config_table(struct smu_context *smu,
4267 struct config_table_setting *table)
4268{
4269 DriverSmuConfigExternal_t driver_smu_config_table;
4270
4271 if (!table)
4272 return -EINVAL;
4273
4274 memset(&driver_smu_config_table,
4275 0,
4276 sizeof(driver_smu_config_table));
4277 driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4278 table->gfxclk_average_tau;
4279 driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4280 table->fclk_average_tau;
4281 driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4282 table->uclk_average_tau;
4283 driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4284 table->gfx_activity_average_tau;
4285 driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4286 table->mem_activity_average_tau;
4287 driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4288 table->socket_power_average_tau;
4289
4290 return smu_cmn_update_table(smu,
4291 SMU_TABLE_DRIVER_SMU_CONFIG,
4292 0,
4293 (void *)&driver_smu_config_table,
4294 true);
4295}
4296
4297static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4298 void *buf,
4299 uint32_t size)
4300{
4301 uint32_t *p = buf;
4302 struct amdgpu_device *adev = smu->adev;
4303
4304 /* No need to disable interrupts for now as we don't lock it yet from ISR */
4305 spin_lock(&smu->stb_context.lock);
4306
4307 /*
4308 * Read the STB FIFO in units of 32bit since this is the accessor window
4309 * (register width) we have.
4310 */
4311 buf = ((char *) buf) + size;
4312 while ((void *)p < buf)
4313 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4314
4315 spin_unlock(&smu->stb_context.lock);
4316
4317 return 0;
4318}
4319
4320static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu)
4321{
4322 return true;
4323}
4324
4325static int sienna_cichlid_mode2_reset(struct smu_context *smu)
4326{
4327 int ret = 0, index;
4328 struct amdgpu_device *adev = smu->adev;
4329 int timeout = 100;
4330
4331 index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
4332 SMU_MSG_DriverMode2Reset);
4333
4334 mutex_lock(&smu->message_lock);
4335
4336 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index,
4337 SMU_RESET_MODE_2);
4338
4339 ret = smu_cmn_wait_for_response(smu);
4340 while (ret != 0 && timeout) {
4341 ret = smu_cmn_wait_for_response(smu);
4342 /* Wait a bit more time for getting ACK */
4343 if (ret != 0) {
4344 --timeout;
4345 usleep_range(500, 1000);
4346 continue;
4347 } else {
4348 break;
4349 }
4350 }
4351
4352 if (!timeout) {
4353 dev_err(adev->dev,
4354 "failed to send mode2 message \tparam: 0x%08x response %#x\n",
4355 SMU_RESET_MODE_2, ret);
4356 goto out;
4357 }
4358
4359 dev_info(smu->adev->dev, "restore config space...\n");
4360 /* Restore the config space saved during init */
4361 amdgpu_device_load_pci_state(adev->pdev);
4362out:
4363 mutex_unlock(&smu->message_lock);
4364
4365 return ret;
4366}
4367
4368static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
4369 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4370 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
4371 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
4372 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
4373 .i2c_init = sienna_cichlid_i2c_control_init,
4374 .i2c_fini = sienna_cichlid_i2c_control_fini,
4375 .print_clk_levels = sienna_cichlid_print_clk_levels,
4376 .force_clk_levels = sienna_cichlid_force_clk_levels,
4377 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
4378 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4379 .display_config_changed = sienna_cichlid_display_config_changed,
4380 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
4381 .is_dpm_running = sienna_cichlid_is_dpm_running,
4382 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
4383 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
4384 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4385 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
4386 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4387 .read_sensor = sienna_cichlid_read_sensor,
4388 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
4389 .set_performance_level = smu_v11_0_set_performance_level,
4390 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4391 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4392 .get_power_limit = sienna_cichlid_get_power_limit,
4393 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
4394 .dump_pptable = sienna_cichlid_dump_pptable,
4395 .init_microcode = smu_v11_0_init_microcode,
4396 .load_microcode = smu_v11_0_load_microcode,
4397 .fini_microcode = smu_v11_0_fini_microcode,
4398 .init_smc_tables = sienna_cichlid_init_smc_tables,
4399 .fini_smc_tables = smu_v11_0_fini_smc_tables,
4400 .init_power = smu_v11_0_init_power,
4401 .fini_power = smu_v11_0_fini_power,
4402 .check_fw_status = smu_v11_0_check_fw_status,
4403 .setup_pptable = sienna_cichlid_setup_pptable,
4404 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
4405 .check_fw_version = smu_v11_0_check_fw_version,
4406 .write_pptable = smu_cmn_write_pptable,
4407 .set_driver_table_location = smu_v11_0_set_driver_table_location,
4408 .set_tool_table_location = smu_v11_0_set_tool_table_location,
4409 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
4410 .system_features_control = sienna_cichlid_system_features_control,
4411 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4412 .send_smc_msg = smu_cmn_send_smc_msg,
4413 .init_display_count = NULL,
4414 .set_allowed_mask = smu_v11_0_set_allowed_mask,
4415 .get_enabled_mask = smu_cmn_get_enabled_mask,
4416 .feature_is_enabled = smu_cmn_feature_is_enabled,
4417 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
4418 .notify_display_change = NULL,
4419 .set_power_limit = smu_v11_0_set_power_limit,
4420 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4421 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4422 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
4423 .set_min_dcef_deep_sleep = NULL,
4424 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4425 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4426 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
4427 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
4428 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
4429 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4430 .gfx_off_control = smu_v11_0_gfx_off_control,
4431 .register_irq_handler = smu_v11_0_register_irq_handler,
4432 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4433 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
4434 .baco_is_support = smu_v11_0_baco_is_support,
4435 .baco_enter = sienna_cichlid_baco_enter,
4436 .baco_exit = sienna_cichlid_baco_exit,
4437 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4438 .mode1_reset = smu_v11_0_mode1_reset,
4439 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
4440 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
4441 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
4442 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
4443 .restore_user_od_settings = sienna_cichlid_restore_user_od_settings,
4444 .run_btc = sienna_cichlid_run_btc,
4445 .set_power_source = smu_v11_0_set_power_source,
4446 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4447 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
4448 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
4449 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
4450 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
4451 .deep_sleep_control = smu_v11_0_deep_sleep_control,
4452 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
4453 .interrupt_work = smu_v11_0_interrupt_work,
4454 .gpo_control = sienna_cichlid_gpo_control,
4455 .set_mp1_state = sienna_cichlid_set_mp1_state,
4456 .stb_collect_info = sienna_cichlid_stb_get_data_direct,
4457 .get_ecc_info = sienna_cichlid_get_ecc_info,
4458 .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4459 .set_config_table = sienna_cichlid_set_config_table,
4460 .get_unique_id = sienna_cichlid_get_unique_id,
4461 .mode2_reset_is_support = sienna_cichlid_is_mode2_reset_supported,
4462 .mode2_reset = sienna_cichlid_mode2_reset,
4463};
4464
4465void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4466{
4467 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
4468 smu->message_map = sienna_cichlid_message_map;
4469 smu->clock_map = sienna_cichlid_clk_map;
4470 smu->feature_map = sienna_cichlid_feature_mask_map;
4471 smu->table_map = sienna_cichlid_table_map;
4472 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4473 smu->workload_map = sienna_cichlid_workload_map;
4474 smu_v11_0_set_smu_mailbox_registers(smu);
4475}