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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_HW_SHARED_H__
27#define __DAL_HW_SHARED_H__
28
29#include "os_types.h"
30#include "fixed31_32.h"
31#include "dc_hw_types.h"
32
33/******************************************************************************
34 * Data types shared between different Virtual HW blocks
35 ******************************************************************************/
36
37#define MAX_AUDIOS 7
38
39/**
40 * @MAX_PIPES:
41 *
42 * Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number
43 * to be used inside loops and for determining array sizes.
44 */
45#define MAX_PIPES 6
46#define MAX_PHANTOM_PIPES (MAX_PIPES / 2)
47#define MAX_DIG_LINK_ENCODERS 7
48#define MAX_DWB_PIPES 1
49#define MAX_HPO_DP2_ENCODERS 4
50#define MAX_HPO_DP2_LINK_ENCODERS 2
51
52struct gamma_curve {
53 uint32_t offset;
54 uint32_t segments_num;
55};
56
57struct curve_points {
58 struct fixed31_32 x;
59 struct fixed31_32 y;
60 struct fixed31_32 offset;
61 struct fixed31_32 slope;
62
63 uint32_t custom_float_x;
64 uint32_t custom_float_y;
65 uint32_t custom_float_offset;
66 uint32_t custom_float_slope;
67};
68
69struct curve_points3 {
70 struct curve_points red;
71 struct curve_points green;
72 struct curve_points blue;
73};
74
75struct pwl_result_data {
76 struct fixed31_32 red;
77 struct fixed31_32 green;
78 struct fixed31_32 blue;
79
80 struct fixed31_32 delta_red;
81 struct fixed31_32 delta_green;
82 struct fixed31_32 delta_blue;
83
84 uint32_t red_reg;
85 uint32_t green_reg;
86 uint32_t blue_reg;
87
88 uint32_t delta_red_reg;
89 uint32_t delta_green_reg;
90 uint32_t delta_blue_reg;
91};
92
93struct dc_rgb {
94 uint32_t red;
95 uint32_t green;
96 uint32_t blue;
97};
98
99struct tetrahedral_17x17x17 {
100 struct dc_rgb lut0[1229];
101 struct dc_rgb lut1[1228];
102 struct dc_rgb lut2[1228];
103 struct dc_rgb lut3[1228];
104};
105struct tetrahedral_9x9x9 {
106 struct dc_rgb lut0[183];
107 struct dc_rgb lut1[182];
108 struct dc_rgb lut2[182];
109 struct dc_rgb lut3[182];
110};
111
112struct tetrahedral_params {
113 union {
114 struct tetrahedral_17x17x17 tetrahedral_17;
115 struct tetrahedral_9x9x9 tetrahedral_9;
116 };
117 bool use_tetrahedral_9;
118 bool use_12bits;
119
120};
121
122/* arr_curve_points - regamma regions/segments specification
123 * arr_points - beginning and end point specified separately (only one on DCE)
124 * corner_points - beginning and end point for all 3 colors (DCN)
125 * rgb_resulted - final curve
126 */
127struct pwl_params {
128 struct gamma_curve arr_curve_points[34];
129 union {
130 struct curve_points arr_points[2];
131 struct curve_points3 corner_points[2];
132 };
133 struct pwl_result_data rgb_resulted[256 + 3];
134 uint32_t hw_points_num;
135};
136
137/* move to dpp
138 * while we are moving functionality out of opp to dpp to align
139 * HW programming to HW IP, we define these struct in hw_shared
140 * so we can still compile while refactoring
141 */
142
143enum lb_pixel_depth {
144 /* do not change the values because it is used as bit vector */
145 LB_PIXEL_DEPTH_18BPP = 1,
146 LB_PIXEL_DEPTH_24BPP = 2,
147 LB_PIXEL_DEPTH_30BPP = 4,
148 LB_PIXEL_DEPTH_36BPP = 8
149};
150
151enum graphics_csc_adjust_type {
152 GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
153 GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
154 GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */
155};
156
157enum ipp_degamma_mode {
158 IPP_DEGAMMA_MODE_BYPASS,
159 IPP_DEGAMMA_MODE_HW_sRGB,
160 IPP_DEGAMMA_MODE_HW_xvYCC,
161 IPP_DEGAMMA_MODE_USER_PWL
162};
163
164enum gamcor_mode {
165 GAMCOR_MODE_BYPASS,
166 GAMCOR_MODE_RESERVED_1,
167 GAMCOR_MODE_USER_PWL,
168 GAMCOR_MODE_RESERVED_3
169};
170
171enum ipp_output_format {
172 IPP_OUTPUT_FORMAT_12_BIT_FIX,
173 IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
174 IPP_OUTPUT_FORMAT_FLOAT
175};
176
177enum expansion_mode {
178 EXPANSION_MODE_DYNAMIC,
179 EXPANSION_MODE_ZERO
180};
181
182struct default_adjustment {
183 enum lb_pixel_depth lb_color_depth;
184 enum dc_color_space out_color_space;
185 enum dc_color_space in_color_space;
186 enum dc_color_depth color_depth;
187 enum pixel_format surface_pixel_format;
188 enum graphics_csc_adjust_type csc_adjust_type;
189 bool force_hw_default;
190};
191
192
193struct out_csc_color_matrix {
194 enum dc_color_space color_space;
195 uint16_t regval[12];
196};
197
198enum gamut_remap_select {
199 GAMUT_REMAP_BYPASS = 0,
200 GAMUT_REMAP_COEFF,
201 GAMUT_REMAP_COMA_COEFF,
202 GAMUT_REMAP_COMB_COEFF
203};
204
205enum opp_regamma {
206 OPP_REGAMMA_BYPASS = 0,
207 OPP_REGAMMA_SRGB,
208 OPP_REGAMMA_XVYCC,
209 OPP_REGAMMA_USER
210};
211
212enum optc_dsc_mode {
213 OPTC_DSC_DISABLED = 0,
214 OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */
215 OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */
216};
217
218struct dc_bias_and_scale {
219 uint16_t scale_red;
220 uint16_t bias_red;
221 uint16_t scale_green;
222 uint16_t bias_green;
223 uint16_t scale_blue;
224 uint16_t bias_blue;
225};
226
227enum test_pattern_dyn_range {
228 TEST_PATTERN_DYN_RANGE_VESA = 0,
229 TEST_PATTERN_DYN_RANGE_CEA
230};
231
232enum test_pattern_mode {
233 TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
234 TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
235 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
236 TEST_PATTERN_MODE_VERTICALBARS,
237 TEST_PATTERN_MODE_HORIZONTALBARS,
238 TEST_PATTERN_MODE_SINGLERAMP_RGB,
239 TEST_PATTERN_MODE_DUALRAMP_RGB,
240 TEST_PATTERN_MODE_XR_BIAS_RGB
241};
242
243enum test_pattern_color_format {
244 TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
245 TEST_PATTERN_COLOR_FORMAT_BPC_8,
246 TEST_PATTERN_COLOR_FORMAT_BPC_10,
247 TEST_PATTERN_COLOR_FORMAT_BPC_12
248};
249
250enum controller_dp_test_pattern {
251 CONTROLLER_DP_TEST_PATTERN_D102 = 0,
252 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
253 CONTROLLER_DP_TEST_PATTERN_PRBS7,
254 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
255 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
256 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
257 CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
258 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
259 CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
260 CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
261 CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
262 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA,
263 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR
264};
265
266enum controller_dp_color_space {
267 CONTROLLER_DP_COLOR_SPACE_RGB,
268 CONTROLLER_DP_COLOR_SPACE_YCBCR601,
269 CONTROLLER_DP_COLOR_SPACE_YCBCR709,
270 CONTROLLER_DP_COLOR_SPACE_UDEFINED
271};
272
273enum dc_lut_mode {
274 LUT_BYPASS,
275 LUT_RAM_A,
276 LUT_RAM_B
277};
278
279/**
280 * speakersToChannels
281 *
282 * @brief
283 * translate speakers to channels
284 *
285 * FL - Front Left
286 * FR - Front Right
287 * RL - Rear Left
288 * RR - Rear Right
289 * RC - Rear Center
290 * FC - Front Center
291 * FLC - Front Left Center
292 * FRC - Front Right Center
293 * RLC - Rear Left Center
294 * RRC - Rear Right Center
295 * LFE - Low Freq Effect
296 *
297 * FC
298 * FLC FRC
299 * FL FR
300 *
301 * LFE
302 * ()
303 *
304 *
305 * RL RR
306 * RLC RRC
307 * RC
308 *
309 * ch 8 7 6 5 4 3 2 1
310 * 0b00000011 - - - - - - FR FL
311 * 0b00000111 - - - - - LFE FR FL
312 * 0b00001011 - - - - FC - FR FL
313 * 0b00001111 - - - - FC LFE FR FL
314 * 0b00010011 - - - RC - - FR FL
315 * 0b00010111 - - - RC - LFE FR FL
316 * 0b00011011 - - - RC FC - FR FL
317 * 0b00011111 - - - RC FC LFE FR FL
318 * 0b00110011 - - RR RL - - FR FL
319 * 0b00110111 - - RR RL - LFE FR FL
320 * 0b00111011 - - RR RL FC - FR FL
321 * 0b00111111 - - RR RL FC LFE FR FL
322 * 0b01110011 - RC RR RL - - FR FL
323 * 0b01110111 - RC RR RL - LFE FR FL
324 * 0b01111011 - RC RR RL FC - FR FL
325 * 0b01111111 - RC RR RL FC LFE FR FL
326 * 0b11110011 RRC RLC RR RL - - FR FL
327 * 0b11110111 RRC RLC RR RL - LFE FR FL
328 * 0b11111011 RRC RLC RR RL FC - FR FL
329 * 0b11111111 RRC RLC RR RL FC LFE FR FL
330 * 0b11000011 FRC FLC - - - - FR FL
331 * 0b11000111 FRC FLC - - - LFE FR FL
332 * 0b11001011 FRC FLC - - FC - FR FL
333 * 0b11001111 FRC FLC - - FC LFE FR FL
334 * 0b11010011 FRC FLC - RC - - FR FL
335 * 0b11010111 FRC FLC - RC - LFE FR FL
336 * 0b11011011 FRC FLC - RC FC - FR FL
337 * 0b11011111 FRC FLC - RC FC LFE FR FL
338 * 0b11110011 FRC FLC RR RL - - FR FL
339 * 0b11110111 FRC FLC RR RL - LFE FR FL
340 * 0b11111011 FRC FLC RR RL FC - FR FL
341 * 0b11111111 FRC FLC RR RL FC LFE FR FL
342 *
343 * @param
344 * speakers - speaker information as it comes from CEA audio block
345 */
346/* translate speakers to channels */
347
348union audio_cea_channels {
349 uint8_t all;
350 struct audio_cea_channels_bits {
351 uint32_t FL:1;
352 uint32_t FR:1;
353 uint32_t LFE:1;
354 uint32_t FC:1;
355 uint32_t RL_RC:1;
356 uint32_t RR:1;
357 uint32_t RC_RLC_FLC:1;
358 uint32_t RRC_FRC:1;
359 } channels;
360};
361
362#endif /* __DAL_HW_SHARED_H__ */
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_HW_SHARED_H__
27#define __DAL_HW_SHARED_H__
28
29#include "os_types.h"
30#include "fixed31_32.h"
31#include "dc_hw_types.h"
32
33/******************************************************************************
34 * Data types shared between different Virtual HW blocks
35 ******************************************************************************/
36
37#define MAX_AUDIOS 7
38#define MAX_PIPES 6
39#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
40#define MAX_DWB_PIPES 1
41#endif
42
43struct gamma_curve {
44 uint32_t offset;
45 uint32_t segments_num;
46};
47
48struct curve_points {
49 struct fixed31_32 x;
50 struct fixed31_32 y;
51 struct fixed31_32 offset;
52 struct fixed31_32 slope;
53
54 uint32_t custom_float_x;
55 uint32_t custom_float_y;
56 uint32_t custom_float_offset;
57 uint32_t custom_float_slope;
58};
59
60struct curve_points3 {
61 struct curve_points red;
62 struct curve_points green;
63 struct curve_points blue;
64};
65
66struct pwl_result_data {
67 struct fixed31_32 red;
68 struct fixed31_32 green;
69 struct fixed31_32 blue;
70
71 struct fixed31_32 delta_red;
72 struct fixed31_32 delta_green;
73 struct fixed31_32 delta_blue;
74
75 uint32_t red_reg;
76 uint32_t green_reg;
77 uint32_t blue_reg;
78
79 uint32_t delta_red_reg;
80 uint32_t delta_green_reg;
81 uint32_t delta_blue_reg;
82};
83
84#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
85struct dc_rgb {
86 uint32_t red;
87 uint32_t green;
88 uint32_t blue;
89};
90
91struct tetrahedral_17x17x17 {
92 struct dc_rgb lut0[1229];
93 struct dc_rgb lut1[1228];
94 struct dc_rgb lut2[1228];
95 struct dc_rgb lut3[1228];
96};
97struct tetrahedral_9x9x9 {
98 struct dc_rgb lut0[183];
99 struct dc_rgb lut1[182];
100 struct dc_rgb lut2[182];
101 struct dc_rgb lut3[182];
102};
103
104struct tetrahedral_params {
105 union {
106 struct tetrahedral_17x17x17 tetrahedral_17;
107 struct tetrahedral_9x9x9 tetrahedral_9;
108 };
109 bool use_tetrahedral_9;
110 bool use_12bits;
111
112};
113#endif
114
115/* arr_curve_points - regamma regions/segments specification
116 * arr_points - beginning and end point specified separately (only one on DCE)
117 * corner_points - beginning and end point for all 3 colors (DCN)
118 * rgb_resulted - final curve
119 */
120struct pwl_params {
121 struct gamma_curve arr_curve_points[34];
122 union {
123 struct curve_points arr_points[2];
124 struct curve_points3 corner_points[2];
125 };
126 struct pwl_result_data rgb_resulted[256 + 3];
127 uint32_t hw_points_num;
128};
129
130/* move to dpp
131 * while we are moving functionality out of opp to dpp to align
132 * HW programming to HW IP, we define these struct in hw_shared
133 * so we can still compile while refactoring
134 */
135
136enum lb_pixel_depth {
137 /* do not change the values because it is used as bit vector */
138 LB_PIXEL_DEPTH_18BPP = 1,
139 LB_PIXEL_DEPTH_24BPP = 2,
140 LB_PIXEL_DEPTH_30BPP = 4,
141 LB_PIXEL_DEPTH_36BPP = 8
142};
143
144enum graphics_csc_adjust_type {
145 GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0,
146 GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */
147 GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */
148};
149
150enum ipp_degamma_mode {
151 IPP_DEGAMMA_MODE_BYPASS,
152 IPP_DEGAMMA_MODE_HW_sRGB,
153 IPP_DEGAMMA_MODE_HW_xvYCC,
154 IPP_DEGAMMA_MODE_USER_PWL
155};
156
157enum ipp_output_format {
158 IPP_OUTPUT_FORMAT_12_BIT_FIX,
159 IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
160 IPP_OUTPUT_FORMAT_FLOAT
161};
162
163enum expansion_mode {
164 EXPANSION_MODE_DYNAMIC,
165 EXPANSION_MODE_ZERO
166};
167
168struct default_adjustment {
169 enum lb_pixel_depth lb_color_depth;
170 enum dc_color_space out_color_space;
171 enum dc_color_space in_color_space;
172 enum dc_color_depth color_depth;
173 enum pixel_format surface_pixel_format;
174 enum graphics_csc_adjust_type csc_adjust_type;
175 bool force_hw_default;
176};
177
178
179struct out_csc_color_matrix {
180 enum dc_color_space color_space;
181 uint16_t regval[12];
182};
183
184enum gamut_remap_select {
185 GAMUT_REMAP_BYPASS = 0,
186 GAMUT_REMAP_COEFF,
187 GAMUT_REMAP_COMA_COEFF,
188 GAMUT_REMAP_COMB_COEFF
189};
190
191enum opp_regamma {
192 OPP_REGAMMA_BYPASS = 0,
193 OPP_REGAMMA_SRGB,
194 OPP_REGAMMA_XVYCC,
195 OPP_REGAMMA_USER
196};
197
198#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
199enum optc_dsc_mode {
200 OPTC_DSC_DISABLED = 0,
201 OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */
202 OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */
203};
204#endif
205
206struct dc_bias_and_scale {
207 uint16_t scale_red;
208 uint16_t bias_red;
209 uint16_t scale_green;
210 uint16_t bias_green;
211 uint16_t scale_blue;
212 uint16_t bias_blue;
213};
214
215enum test_pattern_dyn_range {
216 TEST_PATTERN_DYN_RANGE_VESA = 0,
217 TEST_PATTERN_DYN_RANGE_CEA
218};
219
220enum test_pattern_mode {
221 TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
222 TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
223 TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
224 TEST_PATTERN_MODE_VERTICALBARS,
225 TEST_PATTERN_MODE_HORIZONTALBARS,
226 TEST_PATTERN_MODE_SINGLERAMP_RGB,
227#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
228 TEST_PATTERN_MODE_DUALRAMP_RGB,
229 TEST_PATTERN_MODE_XR_BIAS_RGB
230#else
231 TEST_PATTERN_MODE_DUALRAMP_RGB
232#endif
233};
234
235enum test_pattern_color_format {
236 TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
237 TEST_PATTERN_COLOR_FORMAT_BPC_8,
238 TEST_PATTERN_COLOR_FORMAT_BPC_10,
239 TEST_PATTERN_COLOR_FORMAT_BPC_12
240};
241
242enum controller_dp_test_pattern {
243 CONTROLLER_DP_TEST_PATTERN_D102 = 0,
244 CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
245 CONTROLLER_DP_TEST_PATTERN_PRBS7,
246 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
247 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
248 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
249 CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
250 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
251 CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
252 CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
253 CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
254 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA,
255 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR
256};
257
258enum dc_lut_mode {
259 LUT_BYPASS,
260 LUT_RAM_A,
261 LUT_RAM_B
262};
263#endif /* __DAL_HW_SHARED_H__ */