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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "df_v3_6.h"
25
26#include "df/df_3_6_default.h"
27#include "df/df_3_6_offset.h"
28#include "df/df_3_6_sh_mask.h"
29
30#define DF_3_6_SMN_REG_INST_DIST 0x8
31#define DF_3_6_INST_CNT 8
32
33/* Defined in global_features.h as FTI_PERFMON_VISIBLE */
34#define DF_V3_6_MAX_COUNTERS 4
35
36/* get flags from df perfmon config */
37#define DF_V3_6_GET_EVENT(x) (x & 0xFFUL)
38#define DF_V3_6_GET_INSTANCE(x) ((x >> 8) & 0xFFUL)
39#define DF_V3_6_GET_UNITMASK(x) ((x >> 16) & 0xFFUL)
40#define DF_V3_6_PERFMON_OVERFLOW 0xFFFFFFFFFFFFULL
41
42static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,
43 16, 32, 0, 0, 0, 2, 4, 8};
44
45static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
46 uint32_t ficaa_val)
47{
48 unsigned long flags, address, data;
49 uint32_t ficadl_val, ficadh_val;
50
51 address = adev->nbio.funcs->get_pcie_index_offset(adev);
52 data = adev->nbio.funcs->get_pcie_data_offset(adev);
53
54 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
55 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
56 WREG32(data, ficaa_val);
57
58 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
59 ficadl_val = RREG32(data);
60
61 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
62 ficadh_val = RREG32(data);
63
64 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
65
66 return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val);
67}
68
69static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
70 uint32_t ficadl_val, uint32_t ficadh_val)
71{
72 unsigned long flags, address, data;
73
74 address = adev->nbio.funcs->get_pcie_index_offset(adev);
75 data = adev->nbio.funcs->get_pcie_data_offset(adev);
76
77 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
78 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
79 WREG32(data, ficaa_val);
80
81 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
82 WREG32(data, ficadl_val);
83
84 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
85 WREG32(data, ficadh_val);
86
87 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
88}
89
90/*
91 * df_v3_6_perfmon_rreg - read perfmon lo and hi
92 *
93 * required to be atomic. no mmio method provided so subsequent reads for lo
94 * and hi require to preserve df finite state machine
95 */
96static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
97 uint32_t lo_addr, uint32_t *lo_val,
98 uint32_t hi_addr, uint32_t *hi_val)
99{
100 unsigned long flags, address, data;
101
102 address = adev->nbio.funcs->get_pcie_index_offset(adev);
103 data = adev->nbio.funcs->get_pcie_data_offset(adev);
104
105 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
106 WREG32(address, lo_addr);
107 *lo_val = RREG32(data);
108 WREG32(address, hi_addr);
109 *hi_val = RREG32(data);
110 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
111}
112
113/*
114 * df_v3_6_perfmon_wreg - write to perfmon lo and hi
115 *
116 * required to be atomic. no mmio method provided so subsequent reads after
117 * data writes cannot occur to preserve data fabrics finite state machine.
118 */
119static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
120 uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val)
121{
122 unsigned long flags, address, data;
123
124 address = adev->nbio.funcs->get_pcie_index_offset(adev);
125 data = adev->nbio.funcs->get_pcie_data_offset(adev);
126
127 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
128 WREG32(address, lo_addr);
129 WREG32(data, lo_val);
130 WREG32(address, hi_addr);
131 WREG32(data, hi_val);
132 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
133}
134
135/* same as perfmon_wreg but return status on write value check */
136static int df_v3_6_perfmon_arm_with_status(struct amdgpu_device *adev,
137 uint32_t lo_addr, uint32_t lo_val,
138 uint32_t hi_addr, uint32_t hi_val)
139{
140 unsigned long flags, address, data;
141 uint32_t lo_val_rb, hi_val_rb;
142
143 address = adev->nbio.funcs->get_pcie_index_offset(adev);
144 data = adev->nbio.funcs->get_pcie_data_offset(adev);
145
146 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
147 WREG32(address, lo_addr);
148 WREG32(data, lo_val);
149 WREG32(address, hi_addr);
150 WREG32(data, hi_val);
151
152 WREG32(address, lo_addr);
153 lo_val_rb = RREG32(data);
154 WREG32(address, hi_addr);
155 hi_val_rb = RREG32(data);
156 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
157
158 if (!(lo_val == lo_val_rb && hi_val == hi_val_rb))
159 return -EBUSY;
160
161 return 0;
162}
163
164
165/*
166 * retry arming counters every 100 usecs within 1 millisecond interval.
167 * if retry fails after time out, return error.
168 */
169#define ARM_RETRY_USEC_TIMEOUT 1000
170#define ARM_RETRY_USEC_INTERVAL 100
171static int df_v3_6_perfmon_arm_with_retry(struct amdgpu_device *adev,
172 uint32_t lo_addr, uint32_t lo_val,
173 uint32_t hi_addr, uint32_t hi_val)
174{
175 int countdown = ARM_RETRY_USEC_TIMEOUT;
176
177 while (countdown) {
178
179 if (!df_v3_6_perfmon_arm_with_status(adev, lo_addr, lo_val,
180 hi_addr, hi_val))
181 break;
182
183 countdown -= ARM_RETRY_USEC_INTERVAL;
184 udelay(ARM_RETRY_USEC_INTERVAL);
185 }
186
187 return countdown > 0 ? 0 : -ETIME;
188}
189
190/* get the number of df counters available */
191static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev,
192 struct device_attribute *attr,
193 char *buf)
194{
195 struct amdgpu_device *adev;
196 struct drm_device *ddev;
197 int i, count;
198
199 ddev = dev_get_drvdata(dev);
200 adev = drm_to_adev(ddev);
201 count = 0;
202
203 for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
204 if (adev->df_perfmon_config_assign_mask[i] == 0)
205 count++;
206 }
207
208 return sysfs_emit(buf, "%i\n", count);
209}
210
211/* device attr for available perfmon counters */
212static DEVICE_ATTR(df_cntr_avail, S_IRUGO, df_v3_6_get_df_cntr_avail, NULL);
213
214static void df_v3_6_query_hashes(struct amdgpu_device *adev)
215{
216 u32 tmp;
217
218 adev->df.hash_status.hash_64k = false;
219 adev->df.hash_status.hash_2m = false;
220 adev->df.hash_status.hash_1g = false;
221
222 /* encoding for hash-enabled on Arcturus and Aldebaran */
223 if ((adev->asic_type == CHIP_ARCTURUS &&
224 adev->df.funcs->get_fb_channel_number(adev) == 0xe) ||
225 (adev->asic_type == CHIP_ALDEBARAN &&
226 adev->df.funcs->get_fb_channel_number(adev) == 0x1e)) {
227 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DfGlobalCtrl);
228 adev->df.hash_status.hash_64k = REG_GET_FIELD(tmp,
229 DF_CS_UMC_AON0_DfGlobalCtrl,
230 GlbHashIntlvCtl64K);
231 adev->df.hash_status.hash_2m = REG_GET_FIELD(tmp,
232 DF_CS_UMC_AON0_DfGlobalCtrl,
233 GlbHashIntlvCtl2M);
234 adev->df.hash_status.hash_1g = REG_GET_FIELD(tmp,
235 DF_CS_UMC_AON0_DfGlobalCtrl,
236 GlbHashIntlvCtl1G);
237 }
238}
239
240/* init perfmons */
241static void df_v3_6_sw_init(struct amdgpu_device *adev)
242{
243 int i, ret;
244
245 ret = device_create_file(adev->dev, &dev_attr_df_cntr_avail);
246 if (ret)
247 DRM_ERROR("failed to create file for available df counters\n");
248
249 for (i = 0; i < AMDGPU_MAX_DF_PERFMONS; i++)
250 adev->df_perfmon_config_assign_mask[i] = 0;
251
252 df_v3_6_query_hashes(adev);
253}
254
255static void df_v3_6_sw_fini(struct amdgpu_device *adev)
256{
257
258 device_remove_file(adev->dev, &dev_attr_df_cntr_avail);
259
260}
261
262static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev,
263 bool enable)
264{
265 u32 tmp;
266
267 if (enable) {
268 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
269 tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
270 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
271 } else
272 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
273 mmFabricConfigAccessControl_DEFAULT);
274}
275
276static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev)
277{
278 u32 tmp;
279
280 if (adev->asic_type == CHIP_ALDEBARAN) {
281 tmp = RREG32_SOC15(DF, 0, mmDF_GCM_AON0_DramMegaBaseAddress0);
282 tmp &=
283 ALDEBARAN_DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
284 } else {
285 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
286 tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
287 }
288 tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
289
290 return tmp;
291}
292
293static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev)
294{
295 int fb_channel_number;
296
297 fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);
298 if (fb_channel_number >= ARRAY_SIZE(df_v3_6_channel_number))
299 fb_channel_number = 0;
300
301 return df_v3_6_channel_number[fb_channel_number];
302}
303
304static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
305 bool enable)
306{
307 u32 tmp;
308
309 if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) {
310 /* Put DF on broadcast mode */
311 adev->df.funcs->enable_broadcast_mode(adev, true);
312
313 if (enable) {
314 tmp = RREG32_SOC15(DF, 0,
315 mmDF_PIE_AON0_DfGlobalClkGater);
316 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
317 tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
318 WREG32_SOC15(DF, 0,
319 mmDF_PIE_AON0_DfGlobalClkGater, tmp);
320 } else {
321 tmp = RREG32_SOC15(DF, 0,
322 mmDF_PIE_AON0_DfGlobalClkGater);
323 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
324 tmp |= DF_V3_6_MGCG_DISABLE;
325 WREG32_SOC15(DF, 0,
326 mmDF_PIE_AON0_DfGlobalClkGater, tmp);
327 }
328
329 /* Exit broadcast mode */
330 adev->df.funcs->enable_broadcast_mode(adev, false);
331 }
332}
333
334static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
335 u64 *flags)
336{
337 u32 tmp;
338
339 /* AMD_CG_SUPPORT_DF_MGCG */
340 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
341 if (tmp & DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY)
342 *flags |= AMD_CG_SUPPORT_DF_MGCG;
343}
344
345/* get assigned df perfmon ctr as int */
346static bool df_v3_6_pmc_has_counter(struct amdgpu_device *adev,
347 uint64_t config,
348 int counter_idx)
349{
350
351 return ((config & 0x0FFFFFFUL) ==
352 adev->df_perfmon_config_assign_mask[counter_idx]);
353
354}
355
356/* get address based on counter assignment */
357static void df_v3_6_pmc_get_addr(struct amdgpu_device *adev,
358 uint64_t config,
359 int counter_idx,
360 int is_ctrl,
361 uint32_t *lo_base_addr,
362 uint32_t *hi_base_addr)
363{
364 if (!df_v3_6_pmc_has_counter(adev, config, counter_idx))
365 return;
366
367 switch (counter_idx) {
368
369 case 0:
370 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo4 : smnPerfMonCtrLo4;
371 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi4 : smnPerfMonCtrHi4;
372 break;
373 case 1:
374 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo5 : smnPerfMonCtrLo5;
375 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi5 : smnPerfMonCtrHi5;
376 break;
377 case 2:
378 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo6 : smnPerfMonCtrLo6;
379 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi6 : smnPerfMonCtrHi6;
380 break;
381 case 3:
382 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo7 : smnPerfMonCtrLo7;
383 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi7 : smnPerfMonCtrHi7;
384 break;
385
386 }
387
388}
389
390/* get read counter address */
391static void df_v3_6_pmc_get_read_settings(struct amdgpu_device *adev,
392 uint64_t config,
393 int counter_idx,
394 uint32_t *lo_base_addr,
395 uint32_t *hi_base_addr)
396{
397 df_v3_6_pmc_get_addr(adev, config, counter_idx, 0, lo_base_addr,
398 hi_base_addr);
399}
400
401/* get control counter settings i.e. address and values to set */
402static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
403 uint64_t config,
404 int counter_idx,
405 uint32_t *lo_base_addr,
406 uint32_t *hi_base_addr,
407 uint32_t *lo_val,
408 uint32_t *hi_val,
409 bool is_enable)
410{
411
412 uint32_t eventsel, instance, unitmask;
413 uint32_t instance_10, instance_5432, instance_76;
414
415 df_v3_6_pmc_get_addr(adev, config, counter_idx, 1, lo_base_addr,
416 hi_base_addr);
417
418 if ((*lo_base_addr == 0) || (*hi_base_addr == 0)) {
419 DRM_ERROR("[DF PMC] addressing not retrieved! Lo: %x, Hi: %x",
420 *lo_base_addr, *hi_base_addr);
421 return -ENXIO;
422 }
423
424 eventsel = DF_V3_6_GET_EVENT(config) & 0x3f;
425 unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf;
426 instance = DF_V3_6_GET_INSTANCE(config);
427
428 instance_10 = instance & 0x3;
429 instance_5432 = (instance >> 2) & 0xf;
430 instance_76 = (instance >> 6) & 0x3;
431
432 *lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel;
433 *lo_val = is_enable ? *lo_val | (1 << 22) : *lo_val & ~(1 << 22);
434 *hi_val = (instance_76 << 29) | instance_5432;
435
436 DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
437 config, *lo_base_addr, *hi_base_addr, *lo_val, *hi_val);
438
439 return 0;
440}
441
442/* add df performance counters for read */
443static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev,
444 uint64_t config)
445{
446 int i;
447
448 for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
449 if (adev->df_perfmon_config_assign_mask[i] == 0U) {
450 adev->df_perfmon_config_assign_mask[i] =
451 config & 0x0FFFFFFUL;
452 return i;
453 }
454 }
455
456 return -ENOSPC;
457}
458
459#define DEFERRED_ARM_MASK (1 << 31)
460static int df_v3_6_pmc_set_deferred(struct amdgpu_device *adev,
461 uint64_t config, int counter_idx,
462 bool is_deferred)
463{
464
465 if (!df_v3_6_pmc_has_counter(adev, config, counter_idx))
466 return -EINVAL;
467
468 if (is_deferred)
469 adev->df_perfmon_config_assign_mask[counter_idx] |=
470 DEFERRED_ARM_MASK;
471 else
472 adev->df_perfmon_config_assign_mask[counter_idx] &=
473 ~DEFERRED_ARM_MASK;
474
475 return 0;
476}
477
478static bool df_v3_6_pmc_is_deferred(struct amdgpu_device *adev,
479 uint64_t config,
480 int counter_idx)
481{
482 return (df_v3_6_pmc_has_counter(adev, config, counter_idx) &&
483 (adev->df_perfmon_config_assign_mask[counter_idx]
484 & DEFERRED_ARM_MASK));
485
486}
487
488/* release performance counter */
489static void df_v3_6_pmc_release_cntr(struct amdgpu_device *adev,
490 uint64_t config,
491 int counter_idx)
492{
493 if (df_v3_6_pmc_has_counter(adev, config, counter_idx))
494 adev->df_perfmon_config_assign_mask[counter_idx] = 0ULL;
495}
496
497
498static void df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev,
499 uint64_t config,
500 int counter_idx)
501{
502 uint32_t lo_base_addr = 0, hi_base_addr = 0;
503
504 df_v3_6_pmc_get_read_settings(adev, config, counter_idx, &lo_base_addr,
505 &hi_base_addr);
506
507 if ((lo_base_addr == 0) || (hi_base_addr == 0))
508 return;
509
510 df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0);
511}
512
513/* return available counter if is_add == 1 otherwise return error status. */
514static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
515 int counter_idx, int is_add)
516{
517 uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
518 int err = 0, ret = 0;
519
520 switch (adev->asic_type) {
521 case CHIP_VEGA20:
522 case CHIP_ARCTURUS:
523 if (is_add)
524 return df_v3_6_pmc_add_cntr(adev, config);
525
526 ret = df_v3_6_pmc_get_ctrl_settings(adev,
527 config,
528 counter_idx,
529 &lo_base_addr,
530 &hi_base_addr,
531 &lo_val,
532 &hi_val,
533 true);
534
535 if (ret)
536 return ret;
537
538 err = df_v3_6_perfmon_arm_with_retry(adev,
539 lo_base_addr,
540 lo_val,
541 hi_base_addr,
542 hi_val);
543
544 if (err)
545 ret = df_v3_6_pmc_set_deferred(adev, config,
546 counter_idx, true);
547
548 break;
549 default:
550 break;
551 }
552
553 return ret;
554}
555
556static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
557 int counter_idx, int is_remove)
558{
559 uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
560 int ret = 0;
561
562 switch (adev->asic_type) {
563 case CHIP_VEGA20:
564 case CHIP_ARCTURUS:
565 ret = df_v3_6_pmc_get_ctrl_settings(adev,
566 config,
567 counter_idx,
568 &lo_base_addr,
569 &hi_base_addr,
570 &lo_val,
571 &hi_val,
572 false);
573
574 if (ret)
575 return ret;
576
577 df_v3_6_perfmon_wreg(adev, lo_base_addr, lo_val,
578 hi_base_addr, hi_val);
579
580 if (is_remove) {
581 df_v3_6_reset_perfmon_cntr(adev, config, counter_idx);
582 df_v3_6_pmc_release_cntr(adev, config, counter_idx);
583 }
584
585 break;
586 default:
587 break;
588 }
589
590 return ret;
591}
592
593static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
594 uint64_t config,
595 int counter_idx,
596 uint64_t *count)
597{
598 uint32_t lo_base_addr = 0, hi_base_addr = 0, lo_val = 0, hi_val = 0;
599 *count = 0;
600
601 switch (adev->asic_type) {
602 case CHIP_VEGA20:
603 case CHIP_ARCTURUS:
604 df_v3_6_pmc_get_read_settings(adev, config, counter_idx,
605 &lo_base_addr, &hi_base_addr);
606
607 if ((lo_base_addr == 0) || (hi_base_addr == 0))
608 return;
609
610 /* rearm the counter or throw away count value on failure */
611 if (df_v3_6_pmc_is_deferred(adev, config, counter_idx)) {
612 int rearm_err = df_v3_6_perfmon_arm_with_status(adev,
613 lo_base_addr, lo_val,
614 hi_base_addr, hi_val);
615
616 if (rearm_err)
617 return;
618
619 df_v3_6_pmc_set_deferred(adev, config, counter_idx,
620 false);
621 }
622
623 df_v3_6_perfmon_rreg(adev, lo_base_addr, &lo_val,
624 hi_base_addr, &hi_val);
625
626 *count = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL);
627
628 if (*count >= DF_V3_6_PERFMON_OVERFLOW)
629 *count = 0;
630
631 DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
632 config, lo_base_addr, hi_base_addr, lo_val, hi_val);
633
634 break;
635 default:
636 break;
637 }
638}
639
640static bool df_v3_6_query_ras_poison_mode(struct amdgpu_device *adev)
641{
642 uint32_t hw_assert_msklo, hw_assert_mskhi;
643 uint32_t v0, v1, v28, v31;
644
645 hw_assert_msklo = RREG32_SOC15(DF, 0,
646 mmDF_CS_UMC_AON0_HardwareAssertMaskLow);
647 hw_assert_mskhi = RREG32_SOC15(DF, 0,
648 mmDF_NCS_PG0_HardwareAssertMaskHigh);
649
650 v0 = REG_GET_FIELD(hw_assert_msklo,
651 DF_CS_UMC_AON0_HardwareAssertMaskLow, HWAssertMsk0);
652 v1 = REG_GET_FIELD(hw_assert_msklo,
653 DF_CS_UMC_AON0_HardwareAssertMaskLow, HWAssertMsk1);
654 v28 = REG_GET_FIELD(hw_assert_mskhi,
655 DF_NCS_PG0_HardwareAssertMaskHigh, HWAssertMsk28);
656 v31 = REG_GET_FIELD(hw_assert_mskhi,
657 DF_NCS_PG0_HardwareAssertMaskHigh, HWAssertMsk31);
658
659 if (v0 && v1 && v28 && v31)
660 return true;
661 else if (!v0 && !v1 && !v28 && !v31)
662 return false;
663 else {
664 dev_warn(adev->dev, "DF poison setting is inconsistent(%d:%d:%d:%d)!\n",
665 v0, v1, v28, v31);
666 return false;
667 }
668}
669
670const struct amdgpu_df_funcs df_v3_6_funcs = {
671 .sw_init = df_v3_6_sw_init,
672 .sw_fini = df_v3_6_sw_fini,
673 .enable_broadcast_mode = df_v3_6_enable_broadcast_mode,
674 .get_fb_channel_number = df_v3_6_get_fb_channel_number,
675 .get_hbm_channel_number = df_v3_6_get_hbm_channel_number,
676 .update_medium_grain_clock_gating =
677 df_v3_6_update_medium_grain_clock_gating,
678 .get_clockgating_state = df_v3_6_get_clockgating_state,
679 .pmc_start = df_v3_6_pmc_start,
680 .pmc_stop = df_v3_6_pmc_stop,
681 .pmc_get_count = df_v3_6_pmc_get_count,
682 .get_fica = df_v3_6_get_fica,
683 .set_fica = df_v3_6_set_fica,
684 .query_ras_poison_mode = df_v3_6_query_ras_poison_mode,
685};
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "df_v3_6.h"
25
26#include "df/df_3_6_default.h"
27#include "df/df_3_6_offset.h"
28#include "df/df_3_6_sh_mask.h"
29
30static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,
31 16, 32, 0, 0, 0, 2, 4, 8};
32
33/* init df format attrs */
34AMDGPU_PMU_ATTR(event, "config:0-7");
35AMDGPU_PMU_ATTR(instance, "config:8-15");
36AMDGPU_PMU_ATTR(umask, "config:16-23");
37
38/* df format attributes */
39static struct attribute *df_v3_6_format_attrs[] = {
40 &pmu_attr_event.attr,
41 &pmu_attr_instance.attr,
42 &pmu_attr_umask.attr,
43 NULL
44};
45
46/* df format attribute group */
47static struct attribute_group df_v3_6_format_attr_group = {
48 .name = "format",
49 .attrs = df_v3_6_format_attrs,
50};
51
52/* df event attrs */
53AMDGPU_PMU_ATTR(cake0_pcsout_txdata,
54 "event=0x7,instance=0x46,umask=0x2");
55AMDGPU_PMU_ATTR(cake1_pcsout_txdata,
56 "event=0x7,instance=0x47,umask=0x2");
57AMDGPU_PMU_ATTR(cake0_pcsout_txmeta,
58 "event=0x7,instance=0x46,umask=0x4");
59AMDGPU_PMU_ATTR(cake1_pcsout_txmeta,
60 "event=0x7,instance=0x47,umask=0x4");
61AMDGPU_PMU_ATTR(cake0_ftiinstat_reqalloc,
62 "event=0xb,instance=0x46,umask=0x4");
63AMDGPU_PMU_ATTR(cake1_ftiinstat_reqalloc,
64 "event=0xb,instance=0x47,umask=0x4");
65AMDGPU_PMU_ATTR(cake0_ftiinstat_rspalloc,
66 "event=0xb,instance=0x46,umask=0x8");
67AMDGPU_PMU_ATTR(cake1_ftiinstat_rspalloc,
68 "event=0xb,instance=0x47,umask=0x8");
69
70/* df event attributes */
71static struct attribute *df_v3_6_event_attrs[] = {
72 &pmu_attr_cake0_pcsout_txdata.attr,
73 &pmu_attr_cake1_pcsout_txdata.attr,
74 &pmu_attr_cake0_pcsout_txmeta.attr,
75 &pmu_attr_cake1_pcsout_txmeta.attr,
76 &pmu_attr_cake0_ftiinstat_reqalloc.attr,
77 &pmu_attr_cake1_ftiinstat_reqalloc.attr,
78 &pmu_attr_cake0_ftiinstat_rspalloc.attr,
79 &pmu_attr_cake1_ftiinstat_rspalloc.attr,
80 NULL
81};
82
83/* df event attribute group */
84static struct attribute_group df_v3_6_event_attr_group = {
85 .name = "events",
86 .attrs = df_v3_6_event_attrs
87};
88
89/* df event attr groups */
90const struct attribute_group *df_v3_6_attr_groups[] = {
91 &df_v3_6_format_attr_group,
92 &df_v3_6_event_attr_group,
93 NULL
94};
95
96static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
97 uint32_t ficaa_val)
98{
99 unsigned long flags, address, data;
100 uint32_t ficadl_val, ficadh_val;
101
102 address = adev->nbio_funcs->get_pcie_index_offset(adev);
103 data = adev->nbio_funcs->get_pcie_data_offset(adev);
104
105 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
106 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
107 WREG32(data, ficaa_val);
108
109 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
110 ficadl_val = RREG32(data);
111
112 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
113 ficadh_val = RREG32(data);
114
115 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
116
117 return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val);
118}
119
120static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
121 uint32_t ficadl_val, uint32_t ficadh_val)
122{
123 unsigned long flags, address, data;
124
125 address = adev->nbio_funcs->get_pcie_index_offset(adev);
126 data = adev->nbio_funcs->get_pcie_data_offset(adev);
127
128 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
129 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
130 WREG32(data, ficaa_val);
131
132 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
133 WREG32(data, ficadl_val);
134
135 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
136 WREG32(data, ficadh_val);
137
138 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
139}
140
141/*
142 * df_v3_6_perfmon_rreg - read perfmon lo and hi
143 *
144 * required to be atomic. no mmio method provided so subsequent reads for lo
145 * and hi require to preserve df finite state machine
146 */
147static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
148 uint32_t lo_addr, uint32_t *lo_val,
149 uint32_t hi_addr, uint32_t *hi_val)
150{
151 unsigned long flags, address, data;
152
153 address = adev->nbio_funcs->get_pcie_index_offset(adev);
154 data = adev->nbio_funcs->get_pcie_data_offset(adev);
155
156 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
157 WREG32(address, lo_addr);
158 *lo_val = RREG32(data);
159 WREG32(address, hi_addr);
160 *hi_val = RREG32(data);
161 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
162}
163
164/*
165 * df_v3_6_perfmon_wreg - write to perfmon lo and hi
166 *
167 * required to be atomic. no mmio method provided so subsequent reads after
168 * data writes cannot occur to preserve data fabrics finite state machine.
169 */
170static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
171 uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val)
172{
173 unsigned long flags, address, data;
174
175 address = adev->nbio_funcs->get_pcie_index_offset(adev);
176 data = adev->nbio_funcs->get_pcie_data_offset(adev);
177
178 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
179 WREG32(address, lo_addr);
180 WREG32(data, lo_val);
181 WREG32(address, hi_addr);
182 WREG32(data, hi_val);
183 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
184}
185
186/* get the number of df counters available */
187static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev,
188 struct device_attribute *attr,
189 char *buf)
190{
191 struct amdgpu_device *adev;
192 struct drm_device *ddev;
193 int i, count;
194
195 ddev = dev_get_drvdata(dev);
196 adev = ddev->dev_private;
197 count = 0;
198
199 for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
200 if (adev->df_perfmon_config_assign_mask[i] == 0)
201 count++;
202 }
203
204 return snprintf(buf, PAGE_SIZE, "%i\n", count);
205}
206
207/* device attr for available perfmon counters */
208static DEVICE_ATTR(df_cntr_avail, S_IRUGO, df_v3_6_get_df_cntr_avail, NULL);
209
210/* init perfmons */
211static void df_v3_6_sw_init(struct amdgpu_device *adev)
212{
213 int i, ret;
214
215 ret = device_create_file(adev->dev, &dev_attr_df_cntr_avail);
216 if (ret)
217 DRM_ERROR("failed to create file for available df counters\n");
218
219 for (i = 0; i < AMDGPU_MAX_DF_PERFMONS; i++)
220 adev->df_perfmon_config_assign_mask[i] = 0;
221}
222
223static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev,
224 bool enable)
225{
226 u32 tmp;
227
228 if (enable) {
229 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
230 tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
231 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
232 } else
233 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
234 mmFabricConfigAccessControl_DEFAULT);
235}
236
237static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev)
238{
239 u32 tmp;
240
241 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
242 tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
243 tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
244
245 return tmp;
246}
247
248static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev)
249{
250 int fb_channel_number;
251
252 fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
253 if (fb_channel_number >= ARRAY_SIZE(df_v3_6_channel_number))
254 fb_channel_number = 0;
255
256 return df_v3_6_channel_number[fb_channel_number];
257}
258
259static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
260 bool enable)
261{
262 u32 tmp;
263
264 /* Put DF on broadcast mode */
265 adev->df_funcs->enable_broadcast_mode(adev, true);
266
267 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
268 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
269 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
270 tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
271 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
272 } else {
273 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
274 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
275 tmp |= DF_V3_6_MGCG_DISABLE;
276 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
277 }
278
279 /* Exit broadcast mode */
280 adev->df_funcs->enable_broadcast_mode(adev, false);
281}
282
283static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
284 u32 *flags)
285{
286 u32 tmp;
287
288 /* AMD_CG_SUPPORT_DF_MGCG */
289 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
290 if (tmp & DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY)
291 *flags |= AMD_CG_SUPPORT_DF_MGCG;
292}
293
294/* get assigned df perfmon ctr as int */
295static int df_v3_6_pmc_config_2_cntr(struct amdgpu_device *adev,
296 uint64_t config)
297{
298 int i;
299
300 for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
301 if ((config & 0x0FFFFFFUL) ==
302 adev->df_perfmon_config_assign_mask[i])
303 return i;
304 }
305
306 return -EINVAL;
307}
308
309/* get address based on counter assignment */
310static void df_v3_6_pmc_get_addr(struct amdgpu_device *adev,
311 uint64_t config,
312 int is_ctrl,
313 uint32_t *lo_base_addr,
314 uint32_t *hi_base_addr)
315{
316 int target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
317
318 if (target_cntr < 0)
319 return;
320
321 switch (target_cntr) {
322
323 case 0:
324 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo0 : smnPerfMonCtrLo0;
325 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi0 : smnPerfMonCtrHi0;
326 break;
327 case 1:
328 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo1 : smnPerfMonCtrLo1;
329 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi1 : smnPerfMonCtrHi1;
330 break;
331 case 2:
332 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo2 : smnPerfMonCtrLo2;
333 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi2 : smnPerfMonCtrHi2;
334 break;
335 case 3:
336 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo3 : smnPerfMonCtrLo3;
337 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi3 : smnPerfMonCtrHi3;
338 break;
339
340 }
341
342}
343
344/* get read counter address */
345static void df_v3_6_pmc_get_read_settings(struct amdgpu_device *adev,
346 uint64_t config,
347 uint32_t *lo_base_addr,
348 uint32_t *hi_base_addr)
349{
350 df_v3_6_pmc_get_addr(adev, config, 0, lo_base_addr, hi_base_addr);
351}
352
353/* get control counter settings i.e. address and values to set */
354static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev,
355 uint64_t config,
356 uint32_t *lo_base_addr,
357 uint32_t *hi_base_addr,
358 uint32_t *lo_val,
359 uint32_t *hi_val)
360{
361
362 uint32_t eventsel, instance, unitmask;
363 uint32_t instance_10, instance_5432, instance_76;
364
365 df_v3_6_pmc_get_addr(adev, config, 1, lo_base_addr, hi_base_addr);
366
367 if ((*lo_base_addr == 0) || (*hi_base_addr == 0)) {
368 DRM_ERROR("[DF PMC] addressing not retrieved! Lo: %x, Hi: %x",
369 *lo_base_addr, *hi_base_addr);
370 return -ENXIO;
371 }
372
373 eventsel = DF_V3_6_GET_EVENT(config) & 0x3f;
374 unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf;
375 instance = DF_V3_6_GET_INSTANCE(config);
376
377 instance_10 = instance & 0x3;
378 instance_5432 = (instance >> 2) & 0xf;
379 instance_76 = (instance >> 6) & 0x3;
380
381 *lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel | (1 << 22);
382 *hi_val = (instance_76 << 29) | instance_5432;
383
384 DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
385 config, *lo_base_addr, *hi_base_addr, *lo_val, *hi_val);
386
387 return 0;
388}
389
390/* add df performance counters for read */
391static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev,
392 uint64_t config)
393{
394 int i, target_cntr;
395
396 target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
397
398 if (target_cntr >= 0)
399 return 0;
400
401 for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) {
402 if (adev->df_perfmon_config_assign_mask[i] == 0U) {
403 adev->df_perfmon_config_assign_mask[i] =
404 config & 0x0FFFFFFUL;
405 return 0;
406 }
407 }
408
409 return -ENOSPC;
410}
411
412/* release performance counter */
413static void df_v3_6_pmc_release_cntr(struct amdgpu_device *adev,
414 uint64_t config)
415{
416 int target_cntr = df_v3_6_pmc_config_2_cntr(adev, config);
417
418 if (target_cntr >= 0)
419 adev->df_perfmon_config_assign_mask[target_cntr] = 0ULL;
420}
421
422
423static void df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev,
424 uint64_t config)
425{
426 uint32_t lo_base_addr, hi_base_addr;
427
428 df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr,
429 &hi_base_addr);
430
431 if ((lo_base_addr == 0) || (hi_base_addr == 0))
432 return;
433
434 df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0);
435}
436
437static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config,
438 int is_enable)
439{
440 uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
441 int ret = 0;
442
443 switch (adev->asic_type) {
444 case CHIP_VEGA20:
445
446 df_v3_6_reset_perfmon_cntr(adev, config);
447
448 if (is_enable) {
449 ret = df_v3_6_pmc_add_cntr(adev, config);
450 } else {
451 ret = df_v3_6_pmc_get_ctrl_settings(adev,
452 config,
453 &lo_base_addr,
454 &hi_base_addr,
455 &lo_val,
456 &hi_val);
457
458 if (ret)
459 return ret;
460
461 df_v3_6_perfmon_wreg(adev, lo_base_addr, lo_val,
462 hi_base_addr, hi_val);
463 }
464
465 break;
466 default:
467 break;
468 }
469
470 return ret;
471}
472
473static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config,
474 int is_disable)
475{
476 uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
477 int ret = 0;
478
479 switch (adev->asic_type) {
480 case CHIP_VEGA20:
481 ret = df_v3_6_pmc_get_ctrl_settings(adev,
482 config,
483 &lo_base_addr,
484 &hi_base_addr,
485 &lo_val,
486 &hi_val);
487
488 if (ret)
489 return ret;
490
491 df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0);
492
493 if (is_disable)
494 df_v3_6_pmc_release_cntr(adev, config);
495
496 break;
497 default:
498 break;
499 }
500
501 return ret;
502}
503
504static void df_v3_6_pmc_get_count(struct amdgpu_device *adev,
505 uint64_t config,
506 uint64_t *count)
507{
508 uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val;
509 *count = 0;
510
511 switch (adev->asic_type) {
512 case CHIP_VEGA20:
513
514 df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr,
515 &hi_base_addr);
516
517 if ((lo_base_addr == 0) || (hi_base_addr == 0))
518 return;
519
520 df_v3_6_perfmon_rreg(adev, lo_base_addr, &lo_val,
521 hi_base_addr, &hi_val);
522
523 *count = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL);
524
525 if (*count >= DF_V3_6_PERFMON_OVERFLOW)
526 *count = 0;
527
528 DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x",
529 config, lo_base_addr, hi_base_addr, lo_val, hi_val);
530
531 break;
532
533 default:
534 break;
535 }
536}
537
538const struct amdgpu_df_funcs df_v3_6_funcs = {
539 .sw_init = df_v3_6_sw_init,
540 .enable_broadcast_mode = df_v3_6_enable_broadcast_mode,
541 .get_fb_channel_number = df_v3_6_get_fb_channel_number,
542 .get_hbm_channel_number = df_v3_6_get_hbm_channel_number,
543 .update_medium_grain_clock_gating =
544 df_v3_6_update_medium_grain_clock_gating,
545 .get_clockgating_state = df_v3_6_get_clockgating_state,
546 .pmc_start = df_v3_6_pmc_start,
547 .pmc_stop = df_v3_6_pmc_stop,
548 .pmc_get_count = df_v3_6_pmc_get_count,
549 .get_fica = df_v3_6_get_fica,
550 .set_fica = df_v3_6_set_fica
551};