1// SPDX-License-Identifier: GPL-2.0 OR MIT
  2/*
  3 * Copyright 2009 VMware, Inc.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining a
  6 * copy of this software and associated documentation files (the "Software"),
  7 * to deal in the Software without restriction, including without limitation
  8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9 * and/or sell copies of the Software, and to permit persons to whom the
 10 * Software is furnished to do so, subject to the following conditions:
 11 *
 12 * The above copyright notice and this permission notice shall be included in
 13 * all copies or substantial portions of the Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 21 * OTHER DEALINGS IN THE SOFTWARE.
 22 *
 23 * Authors: Michel Dänzer
 24 */
 25
 26#include <drm/amdgpu_drm.h>
 27#include "amdgpu.h"
 28#include "amdgpu_uvd.h"
 29#include "amdgpu_vce.h"
 30
 31/* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
 32static void amdgpu_do_test_moves(struct amdgpu_device *adev)
 33{
 34	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 35	struct amdgpu_bo *vram_obj = NULL;
 36	struct amdgpu_bo **gtt_obj = NULL;
 37	struct amdgpu_bo_param bp;
 38	uint64_t gart_addr, vram_addr;
 39	unsigned n, size;
 40	int i, r;
 41
 42	size = 1024 * 1024;
 43
 44	/* Number of tests =
 45	 * (Total GTT - IB pool - writeback page - ring buffers) / test size
 46	 */
 47	n = adev->gmc.gart_size - AMDGPU_IB_POOL_SIZE*64*1024;
 48	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
 49		if (adev->rings[i])
 50			n -= adev->rings[i]->ring_size;
 51	if (adev->wb.wb_obj)
 52		n -= AMDGPU_GPU_PAGE_SIZE;
 53	if (adev->irq.ih.ring_obj)
 54		n -= adev->irq.ih.ring_size;
 55	n /= size;
 56
 57	gtt_obj = kcalloc(n, sizeof(*gtt_obj), GFP_KERNEL);
 58	if (!gtt_obj) {
 59		DRM_ERROR("Failed to allocate %d pointers\n", n);
 60		r = 1;
 61		goto out_cleanup;
 62	}
 63	memset(&bp, 0, sizeof(bp));
 64	bp.size = size;
 65	bp.byte_align = PAGE_SIZE;
 66	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
 67	bp.flags = 0;
 68	bp.type = ttm_bo_type_kernel;
 69	bp.resv = NULL;
 70
 71	r = amdgpu_bo_create(adev, &bp, &vram_obj);
 72	if (r) {
 73		DRM_ERROR("Failed to create VRAM object\n");
 74		goto out_cleanup;
 75	}
 76	r = amdgpu_bo_reserve(vram_obj, false);
 77	if (unlikely(r != 0))
 78		goto out_unref;
 79	r = amdgpu_bo_pin(vram_obj, AMDGPU_GEM_DOMAIN_VRAM);
 80	if (r) {
 81		DRM_ERROR("Failed to pin VRAM object\n");
 82		goto out_unres;
 83	}
 84	vram_addr = amdgpu_bo_gpu_offset(vram_obj);
 85	for (i = 0; i < n; i++) {
 86		void *gtt_map, *vram_map;
 87		void **gart_start, **gart_end;
 88		void **vram_start, **vram_end;
 89		struct dma_fence *fence = NULL;
 90
 91		bp.domain = AMDGPU_GEM_DOMAIN_GTT;
 92		r = amdgpu_bo_create(adev, &bp, gtt_obj + i);
 93		if (r) {
 94			DRM_ERROR("Failed to create GTT object %d\n", i);
 95			goto out_lclean;
 96		}
 97
 98		r = amdgpu_bo_reserve(gtt_obj[i], false);
 99		if (unlikely(r != 0))
100			goto out_lclean_unref;
101		r = amdgpu_bo_pin(gtt_obj[i], AMDGPU_GEM_DOMAIN_GTT);
102		if (r) {
103			DRM_ERROR("Failed to pin GTT object %d\n", i);
104			goto out_lclean_unres;
105		}
106		r = amdgpu_ttm_alloc_gart(&gtt_obj[i]->tbo);
107		if (r) {
108			DRM_ERROR("%p bind failed\n", gtt_obj[i]);
109			goto out_lclean_unpin;
110		}
111		gart_addr = amdgpu_bo_gpu_offset(gtt_obj[i]);
112
113		r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
114		if (r) {
115			DRM_ERROR("Failed to map GTT object %d\n", i);
116			goto out_lclean_unpin;
117		}
118
119		for (gart_start = gtt_map, gart_end = gtt_map + size;
120		     gart_start < gart_end;
121		     gart_start++)
122			*gart_start = gart_start;
123
124		amdgpu_bo_kunmap(gtt_obj[i]);
125
126		r = amdgpu_copy_buffer(ring, gart_addr, vram_addr,
127				       size, NULL, &fence, false, false);
128
129		if (r) {
130			DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
131			goto out_lclean_unpin;
132		}
133
134		r = dma_fence_wait(fence, false);
135		if (r) {
136			DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
137			goto out_lclean_unpin;
138		}
139
140		dma_fence_put(fence);
141
142		r = amdgpu_bo_kmap(vram_obj, &vram_map);
143		if (r) {
144			DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
145			goto out_lclean_unpin;
146		}
147
148		for (gart_start = gtt_map, gart_end = gtt_map + size,
149		     vram_start = vram_map, vram_end = vram_map + size;
150		     vram_start < vram_end;
151		     gart_start++, vram_start++) {
152			if (*vram_start != gart_start) {
153				DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
154					  "expected 0x%p (GTT/VRAM offset "
155					  "0x%16llx/0x%16llx)\n",
156					  i, *vram_start, gart_start,
157					  (unsigned long long)
158					  (gart_addr - adev->gmc.gart_start +
159					   (void*)gart_start - gtt_map),
160					  (unsigned long long)
161					  (vram_addr - adev->gmc.vram_start +
162					   (void*)gart_start - gtt_map));
163				amdgpu_bo_kunmap(vram_obj);
164				goto out_lclean_unpin;
165			}
166			*vram_start = vram_start;
167		}
168
169		amdgpu_bo_kunmap(vram_obj);
170
171		r = amdgpu_copy_buffer(ring, vram_addr, gart_addr,
172				       size, NULL, &fence, false, false);
173
174		if (r) {
175			DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
176			goto out_lclean_unpin;
177		}
178
179		r = dma_fence_wait(fence, false);
180		if (r) {
181			DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
182			goto out_lclean_unpin;
183		}
184
185		dma_fence_put(fence);
186
187		r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
188		if (r) {
189			DRM_ERROR("Failed to map GTT object after copy %d\n", i);
190			goto out_lclean_unpin;
191		}
192
193		for (gart_start = gtt_map, gart_end = gtt_map + size,
194		     vram_start = vram_map, vram_end = vram_map + size;
195		     gart_start < gart_end;
196		     gart_start++, vram_start++) {
197			if (*gart_start != vram_start) {
198				DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
199					  "expected 0x%p (VRAM/GTT offset "
200					  "0x%16llx/0x%16llx)\n",
201					  i, *gart_start, vram_start,
202					  (unsigned long long)
203					  (vram_addr - adev->gmc.vram_start +
204					   (void*)vram_start - vram_map),
205					  (unsigned long long)
206					  (gart_addr - adev->gmc.gart_start +
207					   (void*)vram_start - vram_map));
208				amdgpu_bo_kunmap(gtt_obj[i]);
209				goto out_lclean_unpin;
210			}
211		}
212
213		amdgpu_bo_kunmap(gtt_obj[i]);
214
215		DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
216			 gart_addr - adev->gmc.gart_start);
217		continue;
218
219out_lclean_unpin:
220		amdgpu_bo_unpin(gtt_obj[i]);
221out_lclean_unres:
222		amdgpu_bo_unreserve(gtt_obj[i]);
223out_lclean_unref:
224		amdgpu_bo_unref(&gtt_obj[i]);
225out_lclean:
226		for (--i; i >= 0; --i) {
227			amdgpu_bo_unpin(gtt_obj[i]);
228			amdgpu_bo_unreserve(gtt_obj[i]);
229			amdgpu_bo_unref(&gtt_obj[i]);
230		}
231		if (fence)
232			dma_fence_put(fence);
233		break;
234	}
235
236	amdgpu_bo_unpin(vram_obj);
237out_unres:
238	amdgpu_bo_unreserve(vram_obj);
239out_unref:
240	amdgpu_bo_unref(&vram_obj);
241out_cleanup:
242	kfree(gtt_obj);
243	if (r) {
244		pr_warn("Error while testing BO move\n");
245	}
246}
247
248void amdgpu_test_moves(struct amdgpu_device *adev)
249{
250	if (adev->mman.buffer_funcs)
251		amdgpu_do_test_moves(adev);
252}