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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25#ifndef __AMDGPU_PSP_H__
26#define __AMDGPU_PSP_H__
27
28#include "amdgpu.h"
29#include "psp_gfx_if.h"
30#include "ta_xgmi_if.h"
31#include "ta_ras_if.h"
32#include "ta_rap_if.h"
33#include "ta_secureDisplay_if.h"
34
35#define PSP_FENCE_BUFFER_SIZE 0x1000
36#define PSP_CMD_BUFFER_SIZE 0x1000
37#define PSP_1_MEG 0x100000
38#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
39#define PSP_TMR_ALIGNMENT 0x100000
40#define PSP_FW_NAME_LEN 0x24
41
42extern const struct attribute_group amdgpu_flash_attr_group;
43
44enum psp_shared_mem_size {
45 PSP_ASD_SHARED_MEM_SIZE = 0x0,
46 PSP_XGMI_SHARED_MEM_SIZE = 0x4000,
47 PSP_RAS_SHARED_MEM_SIZE = 0x4000,
48 PSP_HDCP_SHARED_MEM_SIZE = 0x4000,
49 PSP_DTM_SHARED_MEM_SIZE = 0x4000,
50 PSP_RAP_SHARED_MEM_SIZE = 0x4000,
51 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000,
52};
53
54enum ta_type_id {
55 TA_TYPE_XGMI = 1,
56 TA_TYPE_RAS,
57 TA_TYPE_HDCP,
58 TA_TYPE_DTM,
59 TA_TYPE_RAP,
60 TA_TYPE_SECUREDISPLAY,
61
62 TA_TYPE_MAX_INDEX,
63};
64
65struct psp_context;
66struct psp_xgmi_node_info;
67struct psp_xgmi_topology_info;
68struct psp_bin_desc;
69
70enum psp_bootloader_cmd {
71 PSP_BL__LOAD_SYSDRV = 0x10000,
72 PSP_BL__LOAD_SOSDRV = 0x20000,
73 PSP_BL__LOAD_KEY_DATABASE = 0x80000,
74 PSP_BL__LOAD_SOCDRV = 0xB0000,
75 PSP_BL__LOAD_DBGDRV = 0xC0000,
76 PSP_BL__LOAD_INTFDRV = 0xD0000,
77 PSP_BL__LOAD_RASDRV = 0xE0000,
78 PSP_BL__DRAM_LONG_TRAIN = 0x100000,
79 PSP_BL__DRAM_SHORT_TRAIN = 0x200000,
80 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000,
81};
82
83enum psp_ring_type {
84 PSP_RING_TYPE__INVALID = 0,
85 /*
86 * These values map to the way the PSP kernel identifies the
87 * rings.
88 */
89 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
90 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
91};
92
93struct psp_ring {
94 enum psp_ring_type ring_type;
95 struct psp_gfx_rb_frame *ring_mem;
96 uint64_t ring_mem_mc_addr;
97 void *ring_mem_handle;
98 uint32_t ring_size;
99 uint32_t ring_wptr;
100};
101
102/* More registers may will be supported */
103enum psp_reg_prog_id {
104 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */
105 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */
106 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */
107 PSP_REG_LAST
108};
109
110struct psp_funcs {
111 int (*init_microcode)(struct psp_context *psp);
112 int (*wait_for_bootloader)(struct psp_context *psp);
113 int (*bootloader_load_kdb)(struct psp_context *psp);
114 int (*bootloader_load_spl)(struct psp_context *psp);
115 int (*bootloader_load_sysdrv)(struct psp_context *psp);
116 int (*bootloader_load_soc_drv)(struct psp_context *psp);
117 int (*bootloader_load_intf_drv)(struct psp_context *psp);
118 int (*bootloader_load_dbg_drv)(struct psp_context *psp);
119 int (*bootloader_load_ras_drv)(struct psp_context *psp);
120 int (*bootloader_load_sos)(struct psp_context *psp);
121 int (*ring_create)(struct psp_context *psp,
122 enum psp_ring_type ring_type);
123 int (*ring_stop)(struct psp_context *psp,
124 enum psp_ring_type ring_type);
125 int (*ring_destroy)(struct psp_context *psp,
126 enum psp_ring_type ring_type);
127 bool (*smu_reload_quirk)(struct psp_context *psp);
128 int (*mode1_reset)(struct psp_context *psp);
129 int (*mem_training)(struct psp_context *psp, uint32_t ops);
130 uint32_t (*ring_get_wptr)(struct psp_context *psp);
131 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
132 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
133 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
134 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
135 int (*vbflash_stat)(struct psp_context *psp);
136 int (*fatal_error_recovery_quirk)(struct psp_context *psp);
137 bool (*get_ras_capability)(struct psp_context *psp);
138};
139
140struct ta_funcs {
141 int (*fn_ta_initialize)(struct psp_context *psp);
142 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id);
143 int (*fn_ta_terminate)(struct psp_context *psp);
144};
145
146#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
147struct psp_xgmi_node_info {
148 uint64_t node_id;
149 uint8_t num_hops;
150 uint8_t is_sharing_enabled;
151 enum ta_xgmi_assigned_sdma_engine sdma_engine;
152 uint8_t num_links;
153 struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM];
154};
155
156struct psp_xgmi_topology_info {
157 uint32_t num_nodes;
158 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
159};
160
161struct psp_bin_desc {
162 uint32_t fw_version;
163 uint32_t feature_version;
164 uint32_t size_bytes;
165 uint8_t *start_addr;
166};
167
168struct ta_mem_context {
169 struct amdgpu_bo *shared_bo;
170 uint64_t shared_mc_addr;
171 void *shared_buf;
172 enum psp_shared_mem_size shared_mem_size;
173};
174
175struct ta_context {
176 bool initialized;
177 uint32_t session_id;
178 uint32_t resp_status;
179 struct ta_mem_context mem_context;
180 struct psp_bin_desc bin_desc;
181 enum psp_gfx_cmd_id ta_load_type;
182 enum ta_type_id ta_type;
183};
184
185struct ta_cp_context {
186 struct ta_context context;
187 struct mutex mutex;
188};
189
190struct psp_xgmi_context {
191 struct ta_context context;
192 struct psp_xgmi_topology_info top_info;
193 bool supports_extended_data;
194 uint8_t xgmi_ta_caps;
195};
196
197struct psp_ras_context {
198 struct ta_context context;
199 struct amdgpu_ras *ras;
200};
201
202#define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942
203#define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000
204#define GDDR6_MEM_TRAINING_OFFSET 0x8000
205/*Define the VRAM size that will be encroached by BIST training.*/
206#define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000
207
208enum psp_memory_training_init_flag {
209 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0,
210 PSP_MEM_TRAIN_SUPPORT = 0x1,
211 PSP_MEM_TRAIN_INIT_FAILED = 0x2,
212 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4,
213 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8,
214};
215
216enum psp_memory_training_ops {
217 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1,
218 PSP_MEM_TRAIN_SAVE = 0x2,
219 PSP_MEM_TRAIN_RESTORE = 0x4,
220 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8,
221 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG,
222 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG,
223};
224
225struct psp_memory_training_context {
226 /*training data size*/
227 u64 train_data_size;
228 /*
229 * sys_cache
230 * cpu virtual address
231 * system memory buffer that used to store the training data.
232 */
233 void *sys_cache;
234
235 /*vram offset of the p2c training data*/
236 u64 p2c_train_data_offset;
237
238 /*vram offset of the c2p training data*/
239 u64 c2p_train_data_offset;
240 struct amdgpu_bo *c2p_bo;
241
242 enum psp_memory_training_init_flag init;
243 u32 training_cnt;
244 bool enable_mem_training;
245};
246
247/** PSP runtime DB **/
248#define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000
249#define PSP_RUNTIME_DB_OFFSET 0x100000
250#define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5
251#define PSP_RUNTIME_DB_VER_1 0x0100
252#define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40
253
254enum psp_runtime_entry_type {
255 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0,
256 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1,
257 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */
258 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */
259 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */
260 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */
261 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */
262};
263
264/* PSP runtime DB header */
265struct psp_runtime_data_header {
266 /* determine the existence of runtime db */
267 uint16_t cookie;
268 /* version of runtime db */
269 uint16_t version;
270};
271
272/* PSP runtime DB entry */
273struct psp_runtime_entry {
274 /* type of runtime db entry */
275 uint32_t entry_type;
276 /* offset of entry in bytes */
277 uint16_t offset;
278 /* size of entry in bytes */
279 uint16_t size;
280};
281
282/* PSP runtime DB directory */
283struct psp_runtime_data_directory {
284 /* number of valid entries */
285 uint16_t entry_count;
286 /* db entries*/
287 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT];
288};
289
290/* PSP runtime DB boot config feature bitmask */
291enum psp_runtime_boot_cfg_feature {
292 BOOT_CFG_FEATURE_GECC = 0x1,
293 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2,
294};
295
296/* PSP run time DB SCPM authentication defines */
297enum psp_runtime_scpm_authentication {
298 SCPM_DISABLE = 0x0,
299 SCPM_ENABLE = 0x1,
300 SCPM_ENABLE_WITH_SCPM_ERR = 0x2,
301};
302
303/* PSP runtime DB boot config entry */
304struct psp_runtime_boot_cfg_entry {
305 uint32_t boot_cfg_bitmask;
306 uint32_t reserved;
307};
308
309/* PSP runtime DB SCPM entry */
310struct psp_runtime_scpm_entry {
311 enum psp_runtime_scpm_authentication scpm_status;
312};
313
314struct psp_context {
315 struct amdgpu_device *adev;
316 struct psp_ring km_ring;
317 struct psp_gfx_cmd_resp *cmd;
318
319 const struct psp_funcs *funcs;
320 const struct ta_funcs *ta_funcs;
321
322 /* firmware buffer */
323 struct amdgpu_bo *fw_pri_bo;
324 uint64_t fw_pri_mc_addr;
325 void *fw_pri_buf;
326
327 /* sos firmware */
328 const struct firmware *sos_fw;
329 struct psp_bin_desc sys;
330 struct psp_bin_desc sos;
331 struct psp_bin_desc toc;
332 struct psp_bin_desc kdb;
333 struct psp_bin_desc spl;
334 struct psp_bin_desc rl;
335 struct psp_bin_desc soc_drv;
336 struct psp_bin_desc intf_drv;
337 struct psp_bin_desc dbg_drv;
338 struct psp_bin_desc ras_drv;
339
340 /* tmr buffer */
341 struct amdgpu_bo *tmr_bo;
342 uint64_t tmr_mc_addr;
343
344 /* asd firmware */
345 const struct firmware *asd_fw;
346
347 /* toc firmware */
348 const struct firmware *toc_fw;
349
350 /* cap firmware */
351 const struct firmware *cap_fw;
352
353 /* fence buffer */
354 struct amdgpu_bo *fence_buf_bo;
355 uint64_t fence_buf_mc_addr;
356 void *fence_buf;
357
358 /* cmd buffer */
359 struct amdgpu_bo *cmd_buf_bo;
360 uint64_t cmd_buf_mc_addr;
361 struct psp_gfx_cmd_resp *cmd_buf_mem;
362
363 /* fence value associated with cmd buffer */
364 atomic_t fence_value;
365 /* flag to mark whether gfx fw autoload is supported or not */
366 bool autoload_supported;
367 /* flag to mark whether psp use runtime TMR or boottime TMR */
368 bool boot_time_tmr;
369 /* flag to mark whether df cstate management centralized to PMFW */
370 bool pmfw_centralized_cstate_management;
371
372 /* xgmi ta firmware and buffer */
373 const struct firmware *ta_fw;
374 uint32_t ta_fw_version;
375
376 uint32_t cap_fw_version;
377 uint32_t cap_feature_version;
378 uint32_t cap_ucode_size;
379
380 struct ta_context asd_context;
381 struct psp_xgmi_context xgmi_context;
382 struct psp_ras_context ras_context;
383 struct ta_cp_context hdcp_context;
384 struct ta_cp_context dtm_context;
385 struct ta_cp_context rap_context;
386 struct ta_cp_context securedisplay_context;
387 struct mutex mutex;
388 struct psp_memory_training_context mem_train_ctx;
389
390 uint32_t boot_cfg_bitmask;
391
392 /* firmware upgrades supported */
393 bool sup_pd_fw_up;
394 bool sup_ifwi_up;
395
396 char *vbflash_tmp_buf;
397 size_t vbflash_image_size;
398 bool vbflash_done;
399};
400
401struct amdgpu_psp_funcs {
402 bool (*check_fw_loading_status)(struct amdgpu_device *adev,
403 enum AMDGPU_UCODE_ID);
404};
405
406
407#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
408#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
409#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
410#define psp_init_microcode(psp) \
411 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
412#define psp_bootloader_load_kdb(psp) \
413 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
414#define psp_bootloader_load_spl(psp) \
415 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
416#define psp_bootloader_load_sysdrv(psp) \
417 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
418#define psp_bootloader_load_soc_drv(psp) \
419 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
420#define psp_bootloader_load_intf_drv(psp) \
421 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0)
422#define psp_bootloader_load_dbg_drv(psp) \
423 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0)
424#define psp_bootloader_load_ras_drv(psp) \
425 ((psp)->funcs->bootloader_load_ras_drv ? \
426 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0)
427#define psp_bootloader_load_sos(psp) \
428 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
429#define psp_smu_reload_quirk(psp) \
430 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
431#define psp_mode1_reset(psp) \
432 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
433#define psp_mem_training(psp, ops) \
434 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)
435
436#define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp))
437#define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value))
438
439#define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \
440 ((psp)->funcs->load_usbc_pd_fw ? \
441 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL)
442
443#define psp_read_usbc_pd_fw(psp, fw_ver) \
444 ((psp)->funcs->read_usbc_pd_fw ? \
445 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
446
447#define psp_update_spirom(psp, fw_pri_mc_addr) \
448 ((psp)->funcs->update_spirom ? \
449 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
450
451#define psp_vbflash_status(psp) \
452 ((psp)->funcs->vbflash_stat ? \
453 (psp)->funcs->vbflash_stat((psp)) : -EINVAL)
454
455#define psp_fatal_error_recovery_quirk(psp) \
456 ((psp)->funcs->fatal_error_recovery_quirk ? \
457 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0)
458
459extern const struct amd_ip_funcs psp_ip_funcs;
460
461extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
462extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
463extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
464extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block;
465extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
466extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
467extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
468extern const struct amdgpu_ip_block_version psp_v14_0_ip_block;
469
470extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
471 uint32_t field_val, uint32_t mask, bool check_changed);
472extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
473 uint32_t field_val, uint32_t mask, uint32_t msec_timeout);
474
475int psp_execute_ip_fw_load(struct psp_context *psp,
476 struct amdgpu_firmware_info *ucode);
477
478int psp_gpu_reset(struct amdgpu_device *adev);
479
480int psp_ta_init_shared_buf(struct psp_context *psp,
481 struct ta_mem_context *mem_ctx);
482void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx);
483int psp_ta_unload(struct psp_context *psp, struct ta_context *context);
484int psp_ta_load(struct psp_context *psp, struct ta_context *context);
485int psp_ta_invoke(struct psp_context *psp,
486 uint32_t ta_cmd_id,
487 struct ta_context *context);
488
489int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta);
490int psp_xgmi_terminate(struct psp_context *psp);
491int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
492int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
493int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
494int psp_xgmi_get_topology_info(struct psp_context *psp,
495 int number_devices,
496 struct psp_xgmi_topology_info *topology,
497 bool get_extended_data);
498int psp_xgmi_set_topology_info(struct psp_context *psp,
499 int number_devices,
500 struct psp_xgmi_topology_info *topology);
501int psp_ras_initialize(struct psp_context *psp);
502int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
503int psp_ras_enable_features(struct psp_context *psp,
504 union ta_ras_cmd_input *info, bool enable);
505int psp_ras_trigger_error(struct psp_context *psp,
506 struct ta_ras_trigger_error_input *info, uint32_t instance_mask);
507int psp_ras_terminate(struct psp_context *psp);
508int psp_ras_query_address(struct psp_context *psp,
509 struct ta_ras_query_address_input *addr_in,
510 struct ta_ras_query_address_output *addr_out);
511
512int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
513int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
514int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status);
515int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
516
517int psp_rlc_autoload_start(struct psp_context *psp);
518
519int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
520 uint32_t value);
521int psp_ring_cmd_submit(struct psp_context *psp,
522 uint64_t cmd_buf_mc_addr,
523 uint64_t fence_mc_addr,
524 int index);
525int psp_init_asd_microcode(struct psp_context *psp,
526 const char *chip_name);
527int psp_init_toc_microcode(struct psp_context *psp,
528 const char *chip_name);
529int psp_init_sos_microcode(struct psp_context *psp,
530 const char *chip_name);
531int psp_init_ta_microcode(struct psp_context *psp,
532 const char *chip_name);
533int psp_init_cap_microcode(struct psp_context *psp,
534 const char *chip_name);
535int psp_get_fw_attestation_records_addr(struct psp_context *psp,
536 uint64_t *output_ptr);
537
538int psp_load_fw_list(struct psp_context *psp,
539 struct amdgpu_firmware_info **ucode_list, int ucode_count);
540void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
541
542int psp_spatial_partition(struct psp_context *psp, int mode);
543
544int is_psp_fw_valid(struct psp_bin_desc bin);
545
546int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev);
547bool amdgpu_psp_get_ras_capability(struct psp_context *psp);
548#endif
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25#ifndef __AMDGPU_PSP_H__
26#define __AMDGPU_PSP_H__
27
28#include "amdgpu.h"
29#include "psp_gfx_if.h"
30#include "ta_xgmi_if.h"
31#include "ta_ras_if.h"
32
33#define PSP_FENCE_BUFFER_SIZE 0x1000
34#define PSP_CMD_BUFFER_SIZE 0x1000
35#define PSP_ASD_SHARED_MEM_SIZE 0x4000
36#define PSP_XGMI_SHARED_MEM_SIZE 0x4000
37#define PSP_RAS_SHARED_MEM_SIZE 0x4000
38#define PSP_1_MEG 0x100000
39#define PSP_TMR_SIZE 0x400000
40
41struct psp_context;
42struct psp_xgmi_node_info;
43struct psp_xgmi_topology_info;
44
45enum psp_bootloader_cmd {
46 PSP_BL__LOAD_SYSDRV = 0x10000,
47 PSP_BL__LOAD_SOSDRV = 0x20000,
48 PSP_BL__LOAD_KEY_DATABASE = 0x80000,
49};
50
51enum psp_ring_type
52{
53 PSP_RING_TYPE__INVALID = 0,
54 /*
55 * These values map to the way the PSP kernel identifies the
56 * rings.
57 */
58 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
59 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
60};
61
62struct psp_ring
63{
64 enum psp_ring_type ring_type;
65 struct psp_gfx_rb_frame *ring_mem;
66 uint64_t ring_mem_mc_addr;
67 void *ring_mem_handle;
68 uint32_t ring_size;
69};
70
71/* More registers may will be supported */
72enum psp_reg_prog_id {
73 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */
74 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */
75 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */
76 PSP_REG_LAST
77};
78
79struct psp_funcs
80{
81 int (*init_microcode)(struct psp_context *psp);
82 int (*bootloader_load_kdb)(struct psp_context *psp);
83 int (*bootloader_load_sysdrv)(struct psp_context *psp);
84 int (*bootloader_load_sos)(struct psp_context *psp);
85 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
86 int (*ring_create)(struct psp_context *psp,
87 enum psp_ring_type ring_type);
88 int (*ring_stop)(struct psp_context *psp,
89 enum psp_ring_type ring_type);
90 int (*ring_destroy)(struct psp_context *psp,
91 enum psp_ring_type ring_type);
92 int (*cmd_submit)(struct psp_context *psp,
93 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
94 int index);
95 bool (*compare_sram_data)(struct psp_context *psp,
96 struct amdgpu_firmware_info *ucode,
97 enum AMDGPU_UCODE_ID ucode_type);
98 bool (*smu_reload_quirk)(struct psp_context *psp);
99 int (*mode1_reset)(struct psp_context *psp);
100 int (*xgmi_get_node_id)(struct psp_context *psp, uint64_t *node_id);
101 int (*xgmi_get_hive_id)(struct psp_context *psp, uint64_t *hive_id);
102 int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices,
103 struct psp_xgmi_topology_info *topology);
104 int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices,
105 struct psp_xgmi_topology_info *topology);
106 bool (*support_vmr_ring)(struct psp_context *psp);
107 int (*ras_trigger_error)(struct psp_context *psp,
108 struct ta_ras_trigger_error_input *info);
109 int (*ras_cure_posion)(struct psp_context *psp, uint64_t *mode_ptr);
110 int (*rlc_autoload_start)(struct psp_context *psp);
111};
112
113#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
114struct psp_xgmi_node_info {
115 uint64_t node_id;
116 uint8_t num_hops;
117 uint8_t is_sharing_enabled;
118 enum ta_xgmi_assigned_sdma_engine sdma_engine;
119};
120
121struct psp_xgmi_topology_info {
122 uint32_t num_nodes;
123 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
124};
125
126struct psp_xgmi_context {
127 uint8_t initialized;
128 uint32_t session_id;
129 struct amdgpu_bo *xgmi_shared_bo;
130 uint64_t xgmi_shared_mc_addr;
131 void *xgmi_shared_buf;
132 struct psp_xgmi_topology_info top_info;
133};
134
135struct psp_ras_context {
136 /*ras fw*/
137 bool ras_initialized;
138 uint32_t session_id;
139 struct amdgpu_bo *ras_shared_bo;
140 uint64_t ras_shared_mc_addr;
141 void *ras_shared_buf;
142 struct amdgpu_ras *ras;
143};
144
145struct psp_context
146{
147 struct amdgpu_device *adev;
148 struct psp_ring km_ring;
149 struct psp_gfx_cmd_resp *cmd;
150
151 const struct psp_funcs *funcs;
152
153 /* firmware buffer */
154 struct amdgpu_bo *fw_pri_bo;
155 uint64_t fw_pri_mc_addr;
156 void *fw_pri_buf;
157
158 /* sos firmware */
159 const struct firmware *sos_fw;
160 uint32_t sos_fw_version;
161 uint32_t sos_feature_version;
162 uint32_t sys_bin_size;
163 uint32_t sos_bin_size;
164 uint32_t toc_bin_size;
165 uint32_t kdb_bin_size;
166 uint8_t *sys_start_addr;
167 uint8_t *sos_start_addr;
168 uint8_t *toc_start_addr;
169 uint8_t *kdb_start_addr;
170
171 /* tmr buffer */
172 struct amdgpu_bo *tmr_bo;
173 uint64_t tmr_mc_addr;
174
175 /* asd firmware and buffer */
176 const struct firmware *asd_fw;
177 uint32_t asd_fw_version;
178 uint32_t asd_feature_version;
179 uint32_t asd_ucode_size;
180 uint8_t *asd_start_addr;
181 struct amdgpu_bo *asd_shared_bo;
182 uint64_t asd_shared_mc_addr;
183 void *asd_shared_buf;
184
185 /* fence buffer */
186 struct amdgpu_bo *fence_buf_bo;
187 uint64_t fence_buf_mc_addr;
188 void *fence_buf;
189
190 /* cmd buffer */
191 struct amdgpu_bo *cmd_buf_bo;
192 uint64_t cmd_buf_mc_addr;
193 struct psp_gfx_cmd_resp *cmd_buf_mem;
194
195 /* fence value associated with cmd buffer */
196 atomic_t fence_value;
197 /* flag to mark whether gfx fw autoload is supported or not */
198 bool autoload_supported;
199
200 /* xgmi ta firmware and buffer */
201 const struct firmware *ta_fw;
202 uint32_t ta_fw_version;
203 uint32_t ta_xgmi_ucode_version;
204 uint32_t ta_xgmi_ucode_size;
205 uint8_t *ta_xgmi_start_addr;
206 uint32_t ta_ras_ucode_version;
207 uint32_t ta_ras_ucode_size;
208 uint8_t *ta_ras_start_addr;
209 struct psp_xgmi_context xgmi_context;
210 struct psp_ras_context ras;
211 struct mutex mutex;
212};
213
214struct amdgpu_psp_funcs {
215 bool (*check_fw_loading_status)(struct amdgpu_device *adev,
216 enum AMDGPU_UCODE_ID);
217};
218
219
220#define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
221#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
222#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
223#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
224#define psp_cmd_submit(psp, cmd_mc, fence_mc, index) \
225 (psp)->funcs->cmd_submit((psp), (cmd_mc), (fence_mc), (index))
226#define psp_compare_sram_data(psp, ucode, type) \
227 (psp)->funcs->compare_sram_data((psp), (ucode), (type))
228#define psp_init_microcode(psp) \
229 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
230#define psp_bootloader_load_kdb(psp) \
231 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
232#define psp_bootloader_load_sysdrv(psp) \
233 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
234#define psp_bootloader_load_sos(psp) \
235 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
236#define psp_smu_reload_quirk(psp) \
237 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
238#define psp_support_vmr_ring(psp) \
239 ((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false)
240#define psp_mode1_reset(psp) \
241 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
242#define psp_xgmi_get_node_id(psp, node_id) \
243 ((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL)
244#define psp_xgmi_get_hive_id(psp, hive_id) \
245 ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp), (hive_id)) : -EINVAL)
246#define psp_xgmi_get_topology_info(psp, num_device, topology) \
247 ((psp)->funcs->xgmi_get_topology_info ? \
248 (psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL)
249#define psp_xgmi_set_topology_info(psp, num_device, topology) \
250 ((psp)->funcs->xgmi_set_topology_info ? \
251 (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL)
252#define psp_rlc_autoload(psp) \
253 ((psp)->funcs->rlc_autoload_start ? (psp)->funcs->rlc_autoload_start((psp)) : 0)
254
255#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
256
257#define psp_ras_trigger_error(psp, info) \
258 ((psp)->funcs->ras_trigger_error ? \
259 (psp)->funcs->ras_trigger_error((psp), (info)) : -EINVAL)
260#define psp_ras_cure_posion(psp, addr) \
261 ((psp)->funcs->ras_cure_posion ? \
262 (psp)->funcs->ras_cure_posion(psp, (addr)) : -EINVAL)
263
264extern const struct amd_ip_funcs psp_ip_funcs;
265
266extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
267extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
268 uint32_t field_val, uint32_t mask, bool check_changed);
269
270extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
271extern const struct amdgpu_ip_block_version psp_v12_0_ip_block;
272
273int psp_gpu_reset(struct amdgpu_device *adev);
274int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
275 uint64_t cmd_gpu_addr, int cmd_size);
276
277int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
278
279int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
280int psp_ras_enable_features(struct psp_context *psp,
281 union ta_ras_cmd_input *info, bool enable);
282
283int psp_rlc_autoload_start(struct psp_context *psp);
284
285extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
286int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
287 uint32_t value);
288#endif