1/*
  2 * Copyright 2015 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DC_HW_SEQUENCER_PRIVATE_H__
 27#define __DC_HW_SEQUENCER_PRIVATE_H__
 28
 29#include "dc_types.h"
 30
 31enum pipe_gating_control {
 32	PIPE_GATING_CONTROL_DISABLE = 0,
 33	PIPE_GATING_CONTROL_ENABLE,
 34	PIPE_GATING_CONTROL_INIT
 35};
 36
 37struct dce_hwseq_wa {
 38	bool blnd_crtc_trigger;
 39	bool DEGVIDCN10_253;
 40	bool false_optc_underflow;
 41	bool DEGVIDCN10_254;
 42	bool DEGVIDCN21;
 43	bool disallow_self_refresh_during_multi_plane_transition;
 44	bool early_riommu_invalidation;
 45};
 46
 47struct hwseq_wa_state {
 48	bool DEGVIDCN10_253_applied;
 49	bool disallow_self_refresh_during_multi_plane_transition_applied;
 50	unsigned int disallow_self_refresh_during_multi_plane_transition_applied_on_frame;
 51};
 52
 53struct pipe_ctx;
 54struct dc_state;
 55struct dc_stream_status;
 56struct dc_writeback_info;
 57struct dchub_init_data;
 58struct dc_static_screen_params;
 59struct resource_pool;
 60struct resource_context;
 61struct stream_resource;
 62struct dc_phy_addr_space_config;
 63struct dc_virtual_addr_space_config;
 64struct hubp;
 65struct dpp;
 66struct dce_hwseq;
 67struct timing_generator;
 68struct tg_color;
 69struct output_pixel_processor;
 70
 71struct hwseq_private_funcs {
 72
 73	void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 74	void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 75	void (*init_pipes)(struct dc *dc, struct dc_state *context);
 76	void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
 77	void (*update_plane_addr)(const struct dc *dc,
 78			struct pipe_ctx *pipe_ctx);
 79	void (*plane_atomic_disconnect)(struct dc *dc,
 80			struct pipe_ctx *pipe_ctx);
 81	void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 82	bool (*set_input_transfer_func)(struct dc *dc,
 83				struct pipe_ctx *pipe_ctx,
 84				const struct dc_plane_state *plane_state);
 85	bool (*set_output_transfer_func)(struct dc *dc,
 86				struct pipe_ctx *pipe_ctx,
 87				const struct dc_stream_state *stream);
 88	void (*power_down)(struct dc *dc);
 89	void (*enable_display_pipe_clock_gating)(struct dc_context *ctx,
 90					bool clock_gating);
 91	bool (*enable_display_power_gating)(struct dc *dc,
 92					uint8_t controller_id,
 93					struct dc_bios *dcb,
 94					enum pipe_gating_control power_gating);
 95	void (*blank_pixel_data)(struct dc *dc,
 96			struct pipe_ctx *pipe_ctx,
 97			bool blank);
 98	enum dc_status (*enable_stream_timing)(
 99			struct pipe_ctx *pipe_ctx,
100			struct dc_state *context,
101			struct dc *dc);
102	void (*edp_backlight_control)(struct dc_link *link,
103			bool enable);
104	void (*setup_vupdate_interrupt)(struct dc *dc,
105			struct pipe_ctx *pipe_ctx);
106	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
107	void (*init_blank)(struct dc *dc, struct timing_generator *tg);
108	void (*disable_vga)(struct dce_hwseq *hws);
109	void (*bios_golden_init)(struct dc *dc);
110	void (*plane_atomic_power_down)(struct dc *dc,
111			struct dpp *dpp,
112			struct hubp *hubp);
113	void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);
114	void (*enable_power_gating_plane)(struct dce_hwseq *hws,
115		bool enable);
116	void (*dpp_pg_control)(struct dce_hwseq *hws,
117			unsigned int dpp_inst,
118			bool power_on);
119	void (*hubp_pg_control)(struct dce_hwseq *hws,
120			unsigned int hubp_inst,
121			bool power_on);
122	void (*dsc_pg_control)(struct dce_hwseq *hws,
123			unsigned int dsc_inst,
124			bool power_on);
125	void (*update_odm)(struct dc *dc, struct dc_state *context,
126			struct pipe_ctx *pipe_ctx);
127	void (*program_all_writeback_pipes_in_tree)(struct dc *dc,
128			const struct dc_stream_state *stream,
129			struct dc_state *context);
130	bool (*s0i3_golden_init_wa)(struct dc *dc);
131	void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
132	void (*verify_allow_pstate_change_high)(struct dc *dc);
133	void (*program_pipe)(struct dc *dc,
134			struct pipe_ctx *pipe_ctx,
135			struct dc_state *context);
136	bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);
137	void (*dccg_init)(struct dce_hwseq *hws);
138	bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,
139			const struct dc_plane_state *plane_state);
140	bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
141			const struct dc_plane_state *plane_state);
142	void (*PLAT_58856_wa)(struct dc_state *context,
143			struct pipe_ctx *pipe_ctx);
144};
145
146struct dce_hwseq {
147	struct dc_context *ctx;
148	const struct dce_hwseq_registers *regs;
149	const struct dce_hwseq_shift *shifts;
150	const struct dce_hwseq_mask *masks;
151	struct dce_hwseq_wa wa;
152	struct hwseq_wa_state wa_state;
153	struct hwseq_private_funcs funcs;
154
155};
156
157#endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */