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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R-Mobile TPU PWM driver
4 *
5 * Copyright (C) 2012 Renesas Solutions Corp.
6 */
7
8#include <linux/clk.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/init.h>
12#include <linux/ioport.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/pwm.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
20
21#define TPU_CHANNEL_MAX 4
22
23#define TPU_TSTR 0x00 /* Timer start register (shared) */
24
25#define TPU_TCRn 0x00 /* Timer control register */
26#define TPU_TCR_CCLR_NONE (0 << 5)
27#define TPU_TCR_CCLR_TGRA (1 << 5)
28#define TPU_TCR_CCLR_TGRB (2 << 5)
29#define TPU_TCR_CCLR_TGRC (5 << 5)
30#define TPU_TCR_CCLR_TGRD (6 << 5)
31#define TPU_TCR_CKEG_RISING (0 << 3)
32#define TPU_TCR_CKEG_FALLING (1 << 3)
33#define TPU_TCR_CKEG_BOTH (2 << 3)
34#define TPU_TMDRn 0x04 /* Timer mode register */
35#define TPU_TMDR_BFWT (1 << 6)
36#define TPU_TMDR_BFB (1 << 5)
37#define TPU_TMDR_BFA (1 << 4)
38#define TPU_TMDR_MD_NORMAL (0 << 0)
39#define TPU_TMDR_MD_PWM (2 << 0)
40#define TPU_TIORn 0x08 /* Timer I/O control register */
41#define TPU_TIOR_IOA_0 (0 << 0)
42#define TPU_TIOR_IOA_0_CLR (1 << 0)
43#define TPU_TIOR_IOA_0_SET (2 << 0)
44#define TPU_TIOR_IOA_0_TOGGLE (3 << 0)
45#define TPU_TIOR_IOA_1 (4 << 0)
46#define TPU_TIOR_IOA_1_CLR (5 << 0)
47#define TPU_TIOR_IOA_1_SET (6 << 0)
48#define TPU_TIOR_IOA_1_TOGGLE (7 << 0)
49#define TPU_TIERn 0x0c /* Timer interrupt enable register */
50#define TPU_TSRn 0x10 /* Timer status register */
51#define TPU_TCNTn 0x14 /* Timer counter */
52#define TPU_TGRAn 0x18 /* Timer general register A */
53#define TPU_TGRBn 0x1c /* Timer general register B */
54#define TPU_TGRCn 0x20 /* Timer general register C */
55#define TPU_TGRDn 0x24 /* Timer general register D */
56
57#define TPU_CHANNEL_OFFSET 0x10
58#define TPU_CHANNEL_SIZE 0x40
59
60enum tpu_pin_state {
61 TPU_PIN_INACTIVE, /* Pin is driven inactive */
62 TPU_PIN_PWM, /* Pin is driven by PWM */
63 TPU_PIN_ACTIVE, /* Pin is driven active */
64};
65
66struct tpu_device;
67
68struct tpu_pwm_device {
69 bool timer_on; /* Whether the timer is running */
70
71 struct tpu_device *tpu;
72 unsigned int channel; /* Channel number in the TPU */
73
74 enum pwm_polarity polarity;
75 unsigned int prescaler;
76 u16 period;
77 u16 duty;
78};
79
80struct tpu_device {
81 struct platform_device *pdev;
82 spinlock_t lock;
83
84 void __iomem *base;
85 struct clk *clk;
86 struct tpu_pwm_device tpd[TPU_CHANNEL_MAX];
87};
88
89static inline struct tpu_device *to_tpu_device(struct pwm_chip *chip)
90{
91 return pwmchip_get_drvdata(chip);
92}
93
94static void tpu_pwm_write(struct tpu_pwm_device *tpd, int reg_nr, u16 value)
95{
96 void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET
97 + tpd->channel * TPU_CHANNEL_SIZE;
98
99 iowrite16(value, base + reg_nr);
100}
101
102static void tpu_pwm_set_pin(struct tpu_pwm_device *tpd,
103 enum tpu_pin_state state)
104{
105 static const char * const states[] = { "inactive", "PWM", "active" };
106
107 dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n",
108 tpd->channel, states[state]);
109
110 switch (state) {
111 case TPU_PIN_INACTIVE:
112 tpu_pwm_write(tpd, TPU_TIORn,
113 tpd->polarity == PWM_POLARITY_INVERSED ?
114 TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0);
115 break;
116 case TPU_PIN_PWM:
117 tpu_pwm_write(tpd, TPU_TIORn,
118 tpd->polarity == PWM_POLARITY_INVERSED ?
119 TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR);
120 break;
121 case TPU_PIN_ACTIVE:
122 tpu_pwm_write(tpd, TPU_TIORn,
123 tpd->polarity == PWM_POLARITY_INVERSED ?
124 TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1);
125 break;
126 }
127}
128
129static void tpu_pwm_start_stop(struct tpu_pwm_device *tpd, int start)
130{
131 unsigned long flags;
132 u16 value;
133
134 spin_lock_irqsave(&tpd->tpu->lock, flags);
135 value = ioread16(tpd->tpu->base + TPU_TSTR);
136
137 if (start)
138 value |= 1 << tpd->channel;
139 else
140 value &= ~(1 << tpd->channel);
141
142 iowrite16(value, tpd->tpu->base + TPU_TSTR);
143 spin_unlock_irqrestore(&tpd->tpu->lock, flags);
144}
145
146static int tpu_pwm_timer_start(struct tpu_pwm_device *tpd)
147{
148 int ret;
149
150 if (!tpd->timer_on) {
151 /* Wake up device and enable clock. */
152 pm_runtime_get_sync(&tpd->tpu->pdev->dev);
153 ret = clk_prepare_enable(tpd->tpu->clk);
154 if (ret) {
155 dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n");
156 return ret;
157 }
158 tpd->timer_on = true;
159 }
160
161 /*
162 * Make sure the channel is stopped, as we need to reconfigure it
163 * completely. First drive the pin to the inactive state to avoid
164 * glitches.
165 */
166 tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
167 tpu_pwm_start_stop(tpd, false);
168
169 /*
170 * - Clear TCNT on TGRB match
171 * - Count on rising edge
172 * - Set prescaler
173 * - Output 0 until TGRA, output 1 until TGRB (active low polarity)
174 * - Output 1 until TGRA, output 0 until TGRB (active high polarity
175 * - PWM mode
176 */
177 tpu_pwm_write(tpd, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING |
178 tpd->prescaler);
179 tpu_pwm_write(tpd, TPU_TMDRn, TPU_TMDR_MD_PWM);
180 tpu_pwm_set_pin(tpd, TPU_PIN_PWM);
181 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
182 tpu_pwm_write(tpd, TPU_TGRBn, tpd->period);
183
184 dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
185 tpd->channel, tpd->duty, tpd->period);
186
187 /* Start the channel. */
188 tpu_pwm_start_stop(tpd, true);
189
190 return 0;
191}
192
193static void tpu_pwm_timer_stop(struct tpu_pwm_device *tpd)
194{
195 if (!tpd->timer_on)
196 return;
197
198 /* Disable channel. */
199 tpu_pwm_start_stop(tpd, false);
200
201 /* Stop clock and mark device as idle. */
202 clk_disable_unprepare(tpd->tpu->clk);
203 pm_runtime_put(&tpd->tpu->pdev->dev);
204
205 tpd->timer_on = false;
206}
207
208/* -----------------------------------------------------------------------------
209 * PWM API
210 */
211
212static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
213{
214 struct tpu_device *tpu = to_tpu_device(chip);
215 struct tpu_pwm_device *tpd;
216
217 if (pwm->hwpwm >= TPU_CHANNEL_MAX)
218 return -EINVAL;
219
220 tpd = &tpu->tpd[pwm->hwpwm];
221
222 tpd->tpu = tpu;
223 tpd->channel = pwm->hwpwm;
224 tpd->polarity = PWM_POLARITY_NORMAL;
225 tpd->prescaler = 0;
226 tpd->period = 0;
227 tpd->duty = 0;
228
229 tpd->timer_on = false;
230
231 return 0;
232}
233
234static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
235{
236 struct tpu_device *tpu = to_tpu_device(chip);
237 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
238
239 tpu_pwm_timer_stop(tpd);
240}
241
242static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
243 u64 duty_ns, u64 period_ns, bool enabled)
244{
245 struct tpu_device *tpu = to_tpu_device(chip);
246 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
247 unsigned int prescaler;
248 bool duty_only = false;
249 u32 clk_rate;
250 u64 period;
251 u32 duty;
252 int ret;
253
254 clk_rate = clk_get_rate(tpu->clk);
255 if (unlikely(clk_rate > NSEC_PER_SEC)) {
256 /*
257 * This won't happen in the nearer future, so this is only a
258 * safeguard to prevent the following calculation from
259 * overflowing. With this clk_rate * period_ns / NSEC_PER_SEC is
260 * not greater than period_ns and so fits into an u64.
261 */
262 return -EINVAL;
263 }
264
265 period = mul_u64_u64_div_u64(clk_rate, period_ns, NSEC_PER_SEC);
266
267 /*
268 * Find the minimal prescaler in [0..3] such that
269 *
270 * period >> (2 * prescaler) < 0x10000
271 *
272 * This could be calculated using something like:
273 *
274 * prescaler = max(ilog2(period) / 2, 7) - 7;
275 *
276 * but given there are only four allowed results and that ilog2 isn't
277 * cheap on all platforms using a switch statement is more effective.
278 */
279 switch (period) {
280 case 1 ... 0xffff:
281 prescaler = 0;
282 break;
283
284 case 0x10000 ... 0x3ffff:
285 prescaler = 1;
286 break;
287
288 case 0x40000 ... 0xfffff:
289 prescaler = 2;
290 break;
291
292 case 0x100000 ... 0x3fffff:
293 prescaler = 3;
294 break;
295
296 default:
297 return -EINVAL;
298 }
299
300 period >>= 2 * prescaler;
301
302 if (duty_ns)
303 duty = mul_u64_u64_div_u64(clk_rate, duty_ns,
304 (u64)NSEC_PER_SEC << (2 * prescaler));
305 else
306 duty = 0;
307
308 dev_dbg(&tpu->pdev->dev,
309 "rate %u, prescaler %u, period %u, duty %u\n",
310 clk_rate, 1 << (2 * prescaler), (u32)period, duty);
311
312 if (tpd->prescaler == prescaler && tpd->period == period)
313 duty_only = true;
314
315 tpd->prescaler = prescaler;
316 tpd->period = period;
317 tpd->duty = duty;
318
319 /* If the channel is disabled we're done. */
320 if (!enabled)
321 return 0;
322
323 if (duty_only && tpd->timer_on) {
324 /*
325 * If only the duty cycle changed and the timer is already
326 * running, there's no need to reconfigure it completely, Just
327 * modify the duty cycle.
328 */
329 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
330 dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel,
331 tpd->duty);
332 } else {
333 /* Otherwise perform a full reconfiguration. */
334 ret = tpu_pwm_timer_start(tpd);
335 if (ret < 0)
336 return ret;
337 }
338
339 if (duty == 0 || duty == period) {
340 /*
341 * To avoid running the timer when not strictly required, handle
342 * 0% and 100% duty cycles as fixed levels and stop the timer.
343 */
344 tpu_pwm_set_pin(tpd, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
345 tpu_pwm_timer_stop(tpd);
346 }
347
348 return 0;
349}
350
351static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
352 enum pwm_polarity polarity)
353{
354 struct tpu_device *tpu = to_tpu_device(chip);
355 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
356
357 tpd->polarity = polarity;
358
359 return 0;
360}
361
362static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
363{
364 struct tpu_device *tpu = to_tpu_device(chip);
365 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
366 int ret;
367
368 ret = tpu_pwm_timer_start(tpd);
369 if (ret < 0)
370 return ret;
371
372 /*
373 * To avoid running the timer when not strictly required, handle 0% and
374 * 100% duty cycles as fixed levels and stop the timer.
375 */
376 if (tpd->duty == 0 || tpd->duty == tpd->period) {
377 tpu_pwm_set_pin(tpd, tpd->duty ?
378 TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
379 tpu_pwm_timer_stop(tpd);
380 }
381
382 return 0;
383}
384
385static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
386{
387 struct tpu_device *tpu = to_tpu_device(chip);
388 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm];
389
390 /* The timer must be running to modify the pin output configuration. */
391 tpu_pwm_timer_start(tpd);
392 tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
393 tpu_pwm_timer_stop(tpd);
394}
395
396static int tpu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
397 const struct pwm_state *state)
398{
399 int err;
400 bool enabled = pwm->state.enabled;
401
402 if (state->polarity != pwm->state.polarity) {
403 if (enabled) {
404 tpu_pwm_disable(chip, pwm);
405 enabled = false;
406 }
407
408 err = tpu_pwm_set_polarity(chip, pwm, state->polarity);
409 if (err)
410 return err;
411 }
412
413 if (!state->enabled) {
414 if (enabled)
415 tpu_pwm_disable(chip, pwm);
416
417 return 0;
418 }
419
420 err = tpu_pwm_config(chip, pwm,
421 state->duty_cycle, state->period, enabled);
422 if (err)
423 return err;
424
425 if (!enabled)
426 err = tpu_pwm_enable(chip, pwm);
427
428 return err;
429}
430
431static const struct pwm_ops tpu_pwm_ops = {
432 .request = tpu_pwm_request,
433 .free = tpu_pwm_free,
434 .apply = tpu_pwm_apply,
435};
436
437/* -----------------------------------------------------------------------------
438 * Probe and remove
439 */
440
441static int tpu_probe(struct platform_device *pdev)
442{
443 struct pwm_chip *chip;
444 struct tpu_device *tpu;
445 int ret;
446
447 chip = devm_pwmchip_alloc(&pdev->dev, TPU_CHANNEL_MAX, sizeof(*tpu));
448 if (IS_ERR(chip))
449 return PTR_ERR(chip);
450 tpu = to_tpu_device(chip);
451
452 spin_lock_init(&tpu->lock);
453 tpu->pdev = pdev;
454
455 /* Map memory, get clock and pin control. */
456 tpu->base = devm_platform_ioremap_resource(pdev, 0);
457 if (IS_ERR(tpu->base))
458 return PTR_ERR(tpu->base);
459
460 tpu->clk = devm_clk_get(&pdev->dev, NULL);
461 if (IS_ERR(tpu->clk))
462 return dev_err_probe(&pdev->dev, PTR_ERR(tpu->clk), "Failed to get clock\n");
463
464 /* Initialize and register the device. */
465 platform_set_drvdata(pdev, tpu);
466
467 chip->ops = &tpu_pwm_ops;
468
469 ret = devm_pm_runtime_enable(&pdev->dev);
470 if (ret < 0)
471 return dev_err_probe(&pdev->dev, ret, "Failed to enable runtime PM\n");
472
473 ret = devm_pwmchip_add(&pdev->dev, chip);
474 if (ret < 0)
475 return dev_err_probe(&pdev->dev, ret, "Failed to register PWM chip\n");
476
477 return 0;
478}
479
480#ifdef CONFIG_OF
481static const struct of_device_id tpu_of_table[] = {
482 { .compatible = "renesas,tpu-r8a73a4", },
483 { .compatible = "renesas,tpu-r8a7740", },
484 { .compatible = "renesas,tpu-r8a7790", },
485 { .compatible = "renesas,tpu", },
486 { },
487};
488
489MODULE_DEVICE_TABLE(of, tpu_of_table);
490#endif
491
492static struct platform_driver tpu_driver = {
493 .probe = tpu_probe,
494 .driver = {
495 .name = "renesas-tpu-pwm",
496 .of_match_table = of_match_ptr(tpu_of_table),
497 }
498};
499
500module_platform_driver(tpu_driver);
501
502MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
503MODULE_DESCRIPTION("Renesas TPU PWM Driver");
504MODULE_LICENSE("GPL v2");
505MODULE_ALIAS("platform:renesas-tpu-pwm");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R-Mobile TPU PWM driver
4 *
5 * Copyright (C) 2012 Renesas Solutions Corp.
6 */
7
8#include <linux/clk.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/init.h>
12#include <linux/ioport.h>
13#include <linux/module.h>
14#include <linux/mutex.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/pwm.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21
22#define TPU_CHANNEL_MAX 4
23
24#define TPU_TSTR 0x00 /* Timer start register (shared) */
25
26#define TPU_TCRn 0x00 /* Timer control register */
27#define TPU_TCR_CCLR_NONE (0 << 5)
28#define TPU_TCR_CCLR_TGRA (1 << 5)
29#define TPU_TCR_CCLR_TGRB (2 << 5)
30#define TPU_TCR_CCLR_TGRC (5 << 5)
31#define TPU_TCR_CCLR_TGRD (6 << 5)
32#define TPU_TCR_CKEG_RISING (0 << 3)
33#define TPU_TCR_CKEG_FALLING (1 << 3)
34#define TPU_TCR_CKEG_BOTH (2 << 3)
35#define TPU_TMDRn 0x04 /* Timer mode register */
36#define TPU_TMDR_BFWT (1 << 6)
37#define TPU_TMDR_BFB (1 << 5)
38#define TPU_TMDR_BFA (1 << 4)
39#define TPU_TMDR_MD_NORMAL (0 << 0)
40#define TPU_TMDR_MD_PWM (2 << 0)
41#define TPU_TIORn 0x08 /* Timer I/O control register */
42#define TPU_TIOR_IOA_0 (0 << 0)
43#define TPU_TIOR_IOA_0_CLR (1 << 0)
44#define TPU_TIOR_IOA_0_SET (2 << 0)
45#define TPU_TIOR_IOA_0_TOGGLE (3 << 0)
46#define TPU_TIOR_IOA_1 (4 << 0)
47#define TPU_TIOR_IOA_1_CLR (5 << 0)
48#define TPU_TIOR_IOA_1_SET (6 << 0)
49#define TPU_TIOR_IOA_1_TOGGLE (7 << 0)
50#define TPU_TIERn 0x0c /* Timer interrupt enable register */
51#define TPU_TSRn 0x10 /* Timer status register */
52#define TPU_TCNTn 0x14 /* Timer counter */
53#define TPU_TGRAn 0x18 /* Timer general register A */
54#define TPU_TGRBn 0x1c /* Timer general register B */
55#define TPU_TGRCn 0x20 /* Timer general register C */
56#define TPU_TGRDn 0x24 /* Timer general register D */
57
58#define TPU_CHANNEL_OFFSET 0x10
59#define TPU_CHANNEL_SIZE 0x40
60
61enum tpu_pin_state {
62 TPU_PIN_INACTIVE, /* Pin is driven inactive */
63 TPU_PIN_PWM, /* Pin is driven by PWM */
64 TPU_PIN_ACTIVE, /* Pin is driven active */
65};
66
67struct tpu_device;
68
69struct tpu_pwm_device {
70 bool timer_on; /* Whether the timer is running */
71
72 struct tpu_device *tpu;
73 unsigned int channel; /* Channel number in the TPU */
74
75 enum pwm_polarity polarity;
76 unsigned int prescaler;
77 u16 period;
78 u16 duty;
79};
80
81struct tpu_device {
82 struct platform_device *pdev;
83 struct pwm_chip chip;
84 spinlock_t lock;
85
86 void __iomem *base;
87 struct clk *clk;
88};
89
90#define to_tpu_device(c) container_of(c, struct tpu_device, chip)
91
92static void tpu_pwm_write(struct tpu_pwm_device *pwm, int reg_nr, u16 value)
93{
94 void __iomem *base = pwm->tpu->base + TPU_CHANNEL_OFFSET
95 + pwm->channel * TPU_CHANNEL_SIZE;
96
97 iowrite16(value, base + reg_nr);
98}
99
100static void tpu_pwm_set_pin(struct tpu_pwm_device *pwm,
101 enum tpu_pin_state state)
102{
103 static const char * const states[] = { "inactive", "PWM", "active" };
104
105 dev_dbg(&pwm->tpu->pdev->dev, "%u: configuring pin as %s\n",
106 pwm->channel, states[state]);
107
108 switch (state) {
109 case TPU_PIN_INACTIVE:
110 tpu_pwm_write(pwm, TPU_TIORn,
111 pwm->polarity == PWM_POLARITY_INVERSED ?
112 TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0);
113 break;
114 case TPU_PIN_PWM:
115 tpu_pwm_write(pwm, TPU_TIORn,
116 pwm->polarity == PWM_POLARITY_INVERSED ?
117 TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR);
118 break;
119 case TPU_PIN_ACTIVE:
120 tpu_pwm_write(pwm, TPU_TIORn,
121 pwm->polarity == PWM_POLARITY_INVERSED ?
122 TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1);
123 break;
124 }
125}
126
127static void tpu_pwm_start_stop(struct tpu_pwm_device *pwm, int start)
128{
129 unsigned long flags;
130 u16 value;
131
132 spin_lock_irqsave(&pwm->tpu->lock, flags);
133 value = ioread16(pwm->tpu->base + TPU_TSTR);
134
135 if (start)
136 value |= 1 << pwm->channel;
137 else
138 value &= ~(1 << pwm->channel);
139
140 iowrite16(value, pwm->tpu->base + TPU_TSTR);
141 spin_unlock_irqrestore(&pwm->tpu->lock, flags);
142}
143
144static int tpu_pwm_timer_start(struct tpu_pwm_device *pwm)
145{
146 int ret;
147
148 if (!pwm->timer_on) {
149 /* Wake up device and enable clock. */
150 pm_runtime_get_sync(&pwm->tpu->pdev->dev);
151 ret = clk_prepare_enable(pwm->tpu->clk);
152 if (ret) {
153 dev_err(&pwm->tpu->pdev->dev, "cannot enable clock\n");
154 return ret;
155 }
156 pwm->timer_on = true;
157 }
158
159 /*
160 * Make sure the channel is stopped, as we need to reconfigure it
161 * completely. First drive the pin to the inactive state to avoid
162 * glitches.
163 */
164 tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE);
165 tpu_pwm_start_stop(pwm, false);
166
167 /*
168 * - Clear TCNT on TGRB match
169 * - Count on rising edge
170 * - Set prescaler
171 * - Output 0 until TGRA, output 1 until TGRB (active low polarity)
172 * - Output 1 until TGRA, output 0 until TGRB (active high polarity
173 * - PWM mode
174 */
175 tpu_pwm_write(pwm, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING |
176 pwm->prescaler);
177 tpu_pwm_write(pwm, TPU_TMDRn, TPU_TMDR_MD_PWM);
178 tpu_pwm_set_pin(pwm, TPU_PIN_PWM);
179 tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty);
180 tpu_pwm_write(pwm, TPU_TGRBn, pwm->period);
181
182 dev_dbg(&pwm->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
183 pwm->channel, pwm->duty, pwm->period);
184
185 /* Start the channel. */
186 tpu_pwm_start_stop(pwm, true);
187
188 return 0;
189}
190
191static void tpu_pwm_timer_stop(struct tpu_pwm_device *pwm)
192{
193 if (!pwm->timer_on)
194 return;
195
196 /* Disable channel. */
197 tpu_pwm_start_stop(pwm, false);
198
199 /* Stop clock and mark device as idle. */
200 clk_disable_unprepare(pwm->tpu->clk);
201 pm_runtime_put(&pwm->tpu->pdev->dev);
202
203 pwm->timer_on = false;
204}
205
206/* -----------------------------------------------------------------------------
207 * PWM API
208 */
209
210static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *_pwm)
211{
212 struct tpu_device *tpu = to_tpu_device(chip);
213 struct tpu_pwm_device *pwm;
214
215 if (_pwm->hwpwm >= TPU_CHANNEL_MAX)
216 return -EINVAL;
217
218 pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
219 if (pwm == NULL)
220 return -ENOMEM;
221
222 pwm->tpu = tpu;
223 pwm->channel = _pwm->hwpwm;
224 pwm->polarity = PWM_POLARITY_NORMAL;
225 pwm->prescaler = 0;
226 pwm->period = 0;
227 pwm->duty = 0;
228
229 pwm->timer_on = false;
230
231 pwm_set_chip_data(_pwm, pwm);
232
233 return 0;
234}
235
236static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *_pwm)
237{
238 struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
239
240 tpu_pwm_timer_stop(pwm);
241 kfree(pwm);
242}
243
244static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *_pwm,
245 int duty_ns, int period_ns)
246{
247 static const unsigned int prescalers[] = { 1, 4, 16, 64 };
248 struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
249 struct tpu_device *tpu = to_tpu_device(chip);
250 unsigned int prescaler;
251 bool duty_only = false;
252 u32 clk_rate;
253 u32 period;
254 u32 duty;
255 int ret;
256
257 /*
258 * Pick a prescaler to avoid overflowing the counter.
259 * TODO: Pick the highest acceptable prescaler.
260 */
261 clk_rate = clk_get_rate(tpu->clk);
262
263 for (prescaler = 0; prescaler < ARRAY_SIZE(prescalers); ++prescaler) {
264 period = clk_rate / prescalers[prescaler]
265 / (NSEC_PER_SEC / period_ns);
266 if (period <= 0xffff)
267 break;
268 }
269
270 if (prescaler == ARRAY_SIZE(prescalers) || period == 0) {
271 dev_err(&tpu->pdev->dev, "clock rate mismatch\n");
272 return -ENOTSUPP;
273 }
274
275 if (duty_ns) {
276 duty = clk_rate / prescalers[prescaler]
277 / (NSEC_PER_SEC / duty_ns);
278 if (duty > period)
279 return -EINVAL;
280 } else {
281 duty = 0;
282 }
283
284 dev_dbg(&tpu->pdev->dev,
285 "rate %u, prescaler %u, period %u, duty %u\n",
286 clk_rate, prescalers[prescaler], period, duty);
287
288 if (pwm->prescaler == prescaler && pwm->period == period)
289 duty_only = true;
290
291 pwm->prescaler = prescaler;
292 pwm->period = period;
293 pwm->duty = duty;
294
295 /* If the channel is disabled we're done. */
296 if (!pwm_is_enabled(_pwm))
297 return 0;
298
299 if (duty_only && pwm->timer_on) {
300 /*
301 * If only the duty cycle changed and the timer is already
302 * running, there's no need to reconfigure it completely, Just
303 * modify the duty cycle.
304 */
305 tpu_pwm_write(pwm, TPU_TGRAn, pwm->duty);
306 dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", pwm->channel,
307 pwm->duty);
308 } else {
309 /* Otherwise perform a full reconfiguration. */
310 ret = tpu_pwm_timer_start(pwm);
311 if (ret < 0)
312 return ret;
313 }
314
315 if (duty == 0 || duty == period) {
316 /*
317 * To avoid running the timer when not strictly required, handle
318 * 0% and 100% duty cycles as fixed levels and stop the timer.
319 */
320 tpu_pwm_set_pin(pwm, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
321 tpu_pwm_timer_stop(pwm);
322 }
323
324 return 0;
325}
326
327static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *_pwm,
328 enum pwm_polarity polarity)
329{
330 struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
331
332 pwm->polarity = polarity;
333
334 return 0;
335}
336
337static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *_pwm)
338{
339 struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
340 int ret;
341
342 ret = tpu_pwm_timer_start(pwm);
343 if (ret < 0)
344 return ret;
345
346 /*
347 * To avoid running the timer when not strictly required, handle 0% and
348 * 100% duty cycles as fixed levels and stop the timer.
349 */
350 if (pwm->duty == 0 || pwm->duty == pwm->period) {
351 tpu_pwm_set_pin(pwm, pwm->duty ?
352 TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
353 tpu_pwm_timer_stop(pwm);
354 }
355
356 return 0;
357}
358
359static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *_pwm)
360{
361 struct tpu_pwm_device *pwm = pwm_get_chip_data(_pwm);
362
363 /* The timer must be running to modify the pin output configuration. */
364 tpu_pwm_timer_start(pwm);
365 tpu_pwm_set_pin(pwm, TPU_PIN_INACTIVE);
366 tpu_pwm_timer_stop(pwm);
367}
368
369static const struct pwm_ops tpu_pwm_ops = {
370 .request = tpu_pwm_request,
371 .free = tpu_pwm_free,
372 .config = tpu_pwm_config,
373 .set_polarity = tpu_pwm_set_polarity,
374 .enable = tpu_pwm_enable,
375 .disable = tpu_pwm_disable,
376 .owner = THIS_MODULE,
377};
378
379/* -----------------------------------------------------------------------------
380 * Probe and remove
381 */
382
383static int tpu_probe(struct platform_device *pdev)
384{
385 struct tpu_device *tpu;
386 int ret;
387
388 tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL);
389 if (tpu == NULL)
390 return -ENOMEM;
391
392 spin_lock_init(&tpu->lock);
393 tpu->pdev = pdev;
394
395 /* Map memory, get clock and pin control. */
396 tpu->base = devm_platform_ioremap_resource(pdev, 0);
397 if (IS_ERR(tpu->base))
398 return PTR_ERR(tpu->base);
399
400 tpu->clk = devm_clk_get(&pdev->dev, NULL);
401 if (IS_ERR(tpu->clk)) {
402 dev_err(&pdev->dev, "cannot get clock\n");
403 return PTR_ERR(tpu->clk);
404 }
405
406 /* Initialize and register the device. */
407 platform_set_drvdata(pdev, tpu);
408
409 tpu->chip.dev = &pdev->dev;
410 tpu->chip.ops = &tpu_pwm_ops;
411 tpu->chip.npwm = TPU_CHANNEL_MAX;
412
413 pm_runtime_enable(&pdev->dev);
414
415 ret = pwmchip_add(&tpu->chip);
416 if (ret < 0) {
417 dev_err(&pdev->dev, "failed to register PWM chip\n");
418 pm_runtime_disable(&pdev->dev);
419 return ret;
420 }
421
422 return 0;
423}
424
425static int tpu_remove(struct platform_device *pdev)
426{
427 struct tpu_device *tpu = platform_get_drvdata(pdev);
428 int ret;
429
430 ret = pwmchip_remove(&tpu->chip);
431
432 pm_runtime_disable(&pdev->dev);
433
434 return ret;
435}
436
437#ifdef CONFIG_OF
438static const struct of_device_id tpu_of_table[] = {
439 { .compatible = "renesas,tpu-r8a73a4", },
440 { .compatible = "renesas,tpu-r8a7740", },
441 { .compatible = "renesas,tpu-r8a7790", },
442 { .compatible = "renesas,tpu", },
443 { },
444};
445
446MODULE_DEVICE_TABLE(of, tpu_of_table);
447#endif
448
449static struct platform_driver tpu_driver = {
450 .probe = tpu_probe,
451 .remove = tpu_remove,
452 .driver = {
453 .name = "renesas-tpu-pwm",
454 .of_match_table = of_match_ptr(tpu_of_table),
455 }
456};
457
458module_platform_driver(tpu_driver);
459
460MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
461MODULE_DESCRIPTION("Renesas TPU PWM Driver");
462MODULE_LICENSE("GPL v2");
463MODULE_ALIAS("platform:renesas-tpu-pwm");