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1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * Copyright 2019 Raptor Engineering, LLC
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27#include "dm_services.h"
28#include "dc.h"
29#include "dcn_calcs.h"
30#include "dcn_calc_auto.h"
31#include "dal_asic_id.h"
32#include "resource.h"
33#include "dcn10/dcn10_resource.h"
34#include "dcn10/dcn10_hubbub.h"
35#include "dml/dml1_display_rq_dlg_calc.h"
36
37#include "dcn_calc_math.h"
38
39#define DC_LOGGER \
40 dc->ctx->logger
41
42#define WM_SET_COUNT 4
43#define WM_A 0
44#define WM_B 1
45#define WM_C 2
46#define WM_D 3
47
48/*
49 * NOTE:
50 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
51 *
52 * It doesn't adhere to Linux kernel style and sometimes will do things in odd
53 * ways. Unless there is something clearly wrong with it the code should
54 * remain as-is as it provides us with a guarantee from HW that it is correct.
55 */
56
57/* Defaults from spreadsheet rev#247.
58 * RV2 delta: dram_clock_change_latency, max_num_dpp
59 */
60const struct dcn_soc_bounding_box dcn10_soc_defaults = {
61 /* latencies */
62 .sr_exit_time = 17, /*us*/
63 .sr_enter_plus_exit_time = 19, /*us*/
64 .urgent_latency = 4, /*us*/
65 .dram_clock_change_latency = 17, /*us*/
66 .write_back_latency = 12, /*us*/
67 .percent_of_ideal_drambw_received_after_urg_latency = 80, /*%*/
68
69 /* below default clocks derived from STA target base on
70 * slow-slow corner + 10% margin with voltages aligned to FCLK.
71 *
72 * Use these value if fused value doesn't make sense as earlier
73 * part don't have correct value fused */
74 /* default DCF CLK DPM on RV*/
75 .dcfclkv_max0p9 = 655, /* MHz, = 3600/5.5 */
76 .dcfclkv_nom0p8 = 626, /* MHz, = 3600/5.75 */
77 .dcfclkv_mid0p72 = 600, /* MHz, = 3600/6, bypass */
78 .dcfclkv_min0p65 = 300, /* MHz, = 3600/12, bypass */
79
80 /* default DISP CLK voltage state on RV */
81 .max_dispclk_vmax0p9 = 1108, /* MHz, = 3600/3.25 */
82 .max_dispclk_vnom0p8 = 1029, /* MHz, = 3600/3.5 */
83 .max_dispclk_vmid0p72 = 960, /* MHz, = 3600/3.75 */
84 .max_dispclk_vmin0p65 = 626, /* MHz, = 3600/5.75 */
85
86 /* default DPP CLK voltage state on RV */
87 .max_dppclk_vmax0p9 = 720, /* MHz, = 3600/5 */
88 .max_dppclk_vnom0p8 = 686, /* MHz, = 3600/5.25 */
89 .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75 */
90 .max_dppclk_vmin0p65 = 400, /* MHz, = 3600/9 */
91
92 /* default PHY CLK voltage state on RV */
93 .phyclkv_max0p9 = 900, /*MHz*/
94 .phyclkv_nom0p8 = 847, /*MHz*/
95 .phyclkv_mid0p72 = 800, /*MHz*/
96 .phyclkv_min0p65 = 600, /*MHz*/
97
98 /* BW depend on FCLK, MCLK, # of channels */
99 /* dual channel BW */
100 .fabric_and_dram_bandwidth_vmax0p9 = 38.4f, /*GB/s*/
101 .fabric_and_dram_bandwidth_vnom0p8 = 34.133f, /*GB/s*/
102 .fabric_and_dram_bandwidth_vmid0p72 = 29.866f, /*GB/s*/
103 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f, /*GB/s*/
104 /* single channel BW
105 .fabric_and_dram_bandwidth_vmax0p9 = 19.2f,
106 .fabric_and_dram_bandwidth_vnom0p8 = 17.066f,
107 .fabric_and_dram_bandwidth_vmid0p72 = 14.933f,
108 .fabric_and_dram_bandwidth_vmin0p65 = 12.8f,
109 */
110
111 .number_of_channels = 2,
112
113 .socclk = 208, /*MHz*/
114 .downspreading = 0.5f, /*%*/
115 .round_trip_ping_latency_cycles = 128, /*DCFCLK Cycles*/
116 .urgent_out_of_order_return_per_channel = 256, /*bytes*/
117 .vmm_page_size = 4096, /*bytes*/
118 .return_bus_width = 64, /*bytes*/
119 .max_request_size = 256, /*bytes*/
120
121 /* Depends on user class (client vs embedded, workstation, etc) */
122 .percent_disp_bw_limit = 0.3f /*%*/
123};
124
125const struct dcn_ip_params dcn10_ip_defaults = {
126 .rob_buffer_size_in_kbyte = 64,
127 .det_buffer_size_in_kbyte = 164,
128 .dpp_output_buffer_pixels = 2560,
129 .opp_output_buffer_lines = 1,
130 .pixel_chunk_size_in_kbyte = 8,
131 .pte_enable = dcn_bw_yes,
132 .pte_chunk_size = 2, /*kbytes*/
133 .meta_chunk_size = 2, /*kbytes*/
134 .writeback_chunk_size = 2, /*kbytes*/
135 .odm_capability = dcn_bw_no,
136 .dsc_capability = dcn_bw_no,
137 .line_buffer_size = 589824, /*bit*/
138 .max_line_buffer_lines = 12,
139 .is_line_buffer_bpp_fixed = dcn_bw_no,
140 .line_buffer_fixed_bpp = dcn_bw_na,
141 .writeback_luma_buffer_size = 12, /*kbytes*/
142 .writeback_chroma_buffer_size = 8, /*kbytes*/
143 .max_num_dpp = 4,
144 .max_num_writeback = 2,
145 .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
146 .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
147 .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
148 .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
149 .max_hscl_ratio = 4,
150 .max_vscl_ratio = 4,
151 .max_hscl_taps = 8,
152 .max_vscl_taps = 8,
153 .pte_buffer_size_in_requests = 42,
154 .dispclk_ramping_margin = 1, /*%*/
155 .under_scan_factor = 1.11f,
156 .max_inter_dcn_tile_repeaters = 8,
157 .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = dcn_bw_no,
158 .bug_forcing_luma_and_chroma_request_to_same_size_fixed = dcn_bw_no,
159 .dcfclk_cstate_latency = 10 /*TODO clone of something else? sr_enter_plus_exit_time?*/
160};
161
162static enum dcn_bw_defs tl_sw_mode_to_bw_defs(enum swizzle_mode_values sw_mode)
163{
164 switch (sw_mode) {
165 case DC_SW_LINEAR:
166 return dcn_bw_sw_linear;
167 case DC_SW_4KB_S:
168 return dcn_bw_sw_4_kb_s;
169 case DC_SW_4KB_D:
170 return dcn_bw_sw_4_kb_d;
171 case DC_SW_64KB_S:
172 return dcn_bw_sw_64_kb_s;
173 case DC_SW_64KB_D:
174 return dcn_bw_sw_64_kb_d;
175 case DC_SW_VAR_S:
176 return dcn_bw_sw_var_s;
177 case DC_SW_VAR_D:
178 return dcn_bw_sw_var_d;
179 case DC_SW_64KB_S_T:
180 return dcn_bw_sw_64_kb_s_t;
181 case DC_SW_64KB_D_T:
182 return dcn_bw_sw_64_kb_d_t;
183 case DC_SW_4KB_S_X:
184 return dcn_bw_sw_4_kb_s_x;
185 case DC_SW_4KB_D_X:
186 return dcn_bw_sw_4_kb_d_x;
187 case DC_SW_64KB_S_X:
188 return dcn_bw_sw_64_kb_s_x;
189 case DC_SW_64KB_D_X:
190 return dcn_bw_sw_64_kb_d_x;
191 case DC_SW_VAR_S_X:
192 return dcn_bw_sw_var_s_x;
193 case DC_SW_VAR_D_X:
194 return dcn_bw_sw_var_d_x;
195 case DC_SW_256B_S:
196 case DC_SW_256_D:
197 case DC_SW_256_R:
198 case DC_SW_4KB_R:
199 case DC_SW_64KB_R:
200 case DC_SW_VAR_R:
201 case DC_SW_4KB_R_X:
202 case DC_SW_64KB_R_X:
203 case DC_SW_VAR_R_X:
204 default:
205 BREAK_TO_DEBUGGER(); /*not in formula*/
206 return dcn_bw_sw_4_kb_s;
207 }
208}
209
210static int tl_lb_bpp_to_int(enum lb_pixel_depth depth)
211{
212 switch (depth) {
213 case LB_PIXEL_DEPTH_18BPP:
214 return 18;
215 case LB_PIXEL_DEPTH_24BPP:
216 return 24;
217 case LB_PIXEL_DEPTH_30BPP:
218 return 30;
219 case LB_PIXEL_DEPTH_36BPP:
220 return 36;
221 default:
222 return 30;
223 }
224}
225
226static enum dcn_bw_defs tl_pixel_format_to_bw_defs(enum surface_pixel_format format)
227{
228 switch (format) {
229 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
230 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
231 return dcn_bw_rgb_sub_16;
232 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
233 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
234 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
235 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
236 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
237 return dcn_bw_rgb_sub_32;
238 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
239 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
240 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
241 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
242 return dcn_bw_rgb_sub_64;
243 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
244 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
245 return dcn_bw_yuv420_sub_8;
246 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
247 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
248 return dcn_bw_yuv420_sub_10;
249 default:
250 return dcn_bw_rgb_sub_32;
251 }
252}
253
254enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode)
255{
256 switch (sw_mode) {
257 /* for 4/8/16 high tiles */
258 case DC_SW_LINEAR:
259 return dm_4k_tile;
260 case DC_SW_4KB_S:
261 case DC_SW_4KB_S_X:
262 return dm_4k_tile;
263 case DC_SW_64KB_S:
264 case DC_SW_64KB_S_X:
265 case DC_SW_64KB_S_T:
266 return dm_64k_tile;
267 case DC_SW_VAR_S:
268 case DC_SW_VAR_S_X:
269 return dm_256k_tile;
270
271 /* For 64bpp 2 high tiles */
272 case DC_SW_4KB_D:
273 case DC_SW_4KB_D_X:
274 return dm_4k_tile;
275 case DC_SW_64KB_D:
276 case DC_SW_64KB_D_X:
277 case DC_SW_64KB_D_T:
278 return dm_64k_tile;
279 case DC_SW_VAR_D:
280 case DC_SW_VAR_D_X:
281 return dm_256k_tile;
282
283 case DC_SW_4KB_R:
284 case DC_SW_4KB_R_X:
285 return dm_4k_tile;
286 case DC_SW_64KB_R:
287 case DC_SW_64KB_R_X:
288 return dm_64k_tile;
289 case DC_SW_VAR_R:
290 case DC_SW_VAR_R_X:
291 return dm_256k_tile;
292
293 /* Unsupported swizzle modes for dcn */
294 case DC_SW_256B_S:
295 default:
296 ASSERT(0); /* Not supported */
297 return 0;
298 }
299}
300
301static void pipe_ctx_to_e2e_pipe_params (
302 const struct pipe_ctx *pipe,
303 struct _vcs_dpi_display_pipe_params_st *input)
304{
305 input->src.is_hsplit = false;
306
307 /* stereo can never be split */
308 if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
309 pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
310 /* reset the split group if it was already considered split. */
311 input->src.hsplit_grp = pipe->pipe_idx;
312 } else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) {
313 input->src.is_hsplit = true;
314 } else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) {
315 input->src.is_hsplit = true;
316 }
317
318 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {
319 /*
320 * this method requires us to always re-calculate watermark when dcc change
321 * between flip.
322 */
323 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0;
324 } else {
325 /*
326 * allow us to disable dcc on the fly without re-calculating WM
327 *
328 * extra overhead for DCC is quite small. for 1080p WM without
329 * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
330 */
331 unsigned int bpe;
332
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
334 dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0;
335 }
336 input->src.dcc_rate = 1;
337 input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch;
338 input->src.source_scan = dm_horz;
339 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle;
340
341 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width;
342 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height;
343 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width;
344 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width;
345 input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */
346 input->src.cur0_bpp = 32;
347
348 input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle);
349
350 switch (pipe->plane_state->rotation) {
351 case ROTATION_ANGLE_0:
352 case ROTATION_ANGLE_180:
353 input->src.source_scan = dm_horz;
354 break;
355 case ROTATION_ANGLE_90:
356 case ROTATION_ANGLE_270:
357 input->src.source_scan = dm_vert;
358 break;
359 default:
360 ASSERT(0); /* Not supported */
361 break;
362 }
363
364 /* TODO: Fix pixel format mappings */
365 switch (pipe->plane_state->format) {
366 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
367 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
368 input->src.source_format = dm_420_8;
369 input->src.viewport_width_c = input->src.viewport_width / 2;
370 input->src.viewport_height_c = input->src.viewport_height / 2;
371 break;
372 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
373 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
374 input->src.source_format = dm_420_10;
375 input->src.viewport_width_c = input->src.viewport_width / 2;
376 input->src.viewport_height_c = input->src.viewport_height / 2;
377 break;
378 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
379 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
380 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
381 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
382 input->src.source_format = dm_444_64;
383 input->src.viewport_width_c = input->src.viewport_width;
384 input->src.viewport_height_c = input->src.viewport_height;
385 break;
386 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
387 input->src.source_format = dm_rgbe_alpha;
388 input->src.viewport_width_c = input->src.viewport_width;
389 input->src.viewport_height_c = input->src.viewport_height;
390 break;
391 default:
392 input->src.source_format = dm_444_32;
393 input->src.viewport_width_c = input->src.viewport_width;
394 input->src.viewport_height_c = input->src.viewport_height;
395 break;
396 }
397
398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps;
399 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
400 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
401 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0;
402 if (input->scale_ratio_depth.vinit < 1.0)
403 input->scale_ratio_depth.vinit = 1;
404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
405 input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;
406 input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c;
407 input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;
408 input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;
409 input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;
410 if (input->scale_ratio_depth.vinit_c < 1.0)
411 input->scale_ratio_depth.vinit_c = 1;
412 switch (pipe->plane_res.scl_data.lb_params.depth) {
413 case LB_PIXEL_DEPTH_30BPP:
414 input->scale_ratio_depth.lb_depth = 30; break;
415 case LB_PIXEL_DEPTH_36BPP:
416 input->scale_ratio_depth.lb_depth = 36; break;
417 default:
418 input->scale_ratio_depth.lb_depth = 24; break;
419 }
420
421
422 input->dest.vactive = pipe->stream->timing.v_addressable + pipe->stream->timing.v_border_top
423 + pipe->stream->timing.v_border_bottom;
424
425 input->dest.recout_width = pipe->plane_res.scl_data.recout.width;
426 input->dest.recout_height = pipe->plane_res.scl_data.recout.height;
427
428 input->dest.full_recout_width = pipe->plane_res.scl_data.recout.width;
429 input->dest.full_recout_height = pipe->plane_res.scl_data.recout.height;
430
431 input->dest.htotal = pipe->stream->timing.h_total;
432 input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch;
433 input->dest.hblank_end = input->dest.hblank_start
434 - pipe->stream->timing.h_addressable
435 - pipe->stream->timing.h_border_left
436 - pipe->stream->timing.h_border_right;
437
438 input->dest.vtotal = pipe->stream->timing.v_total;
439 input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch;
440 input->dest.vblank_end = input->dest.vblank_start
441 - pipe->stream->timing.v_addressable
442 - pipe->stream->timing.v_border_bottom
443 - pipe->stream->timing.v_border_top;
444 input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_100hz/10000.0;
445 input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
446 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
447 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
448 input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
449
450}
451
452static void dcn_bw_calc_rq_dlg_ttu(
453 const struct dc *dc,
454 const struct dcn_bw_internal_vars *v,
455 struct pipe_ctx *pipe,
456 int in_idx)
457{
458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml);
459 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &pipe->dlg_regs;
460 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &pipe->ttu_regs;
461 struct _vcs_dpi_display_rq_regs_st *rq_regs = &pipe->rq_regs;
462 struct _vcs_dpi_display_rq_params_st rq_param = {0};
463 struct _vcs_dpi_display_dlg_sys_params_st dlg_sys_param = {0};
464 struct _vcs_dpi_display_e2e_pipe_params_st input = { { { 0 } } };
465 float total_active_bw = 0;
466 float total_prefetch_bw = 0;
467 int total_flip_bytes = 0;
468 int i;
469
470 memset(dlg_regs, 0, sizeof(*dlg_regs));
471 memset(ttu_regs, 0, sizeof(*ttu_regs));
472 memset(rq_regs, 0, sizeof(*rq_regs));
473
474 for (i = 0; i < number_of_planes; i++) {
475 total_active_bw += v->read_bandwidth[i];
476 total_prefetch_bw += v->prefetch_bandwidth[i];
477 total_flip_bytes += v->total_immediate_flip_bytes[i];
478 }
479 dlg_sys_param.total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw);
480 if (dlg_sys_param.total_flip_bw < 0.0)
481 dlg_sys_param.total_flip_bw = 0;
482
483 dlg_sys_param.t_mclk_wm_us = v->dram_clock_change_watermark;
484 dlg_sys_param.t_sr_wm_us = v->stutter_enter_plus_exit_watermark;
485 dlg_sys_param.t_urg_wm_us = v->urgent_watermark;
486 dlg_sys_param.t_extra_us = v->urgent_extra_latency;
487 dlg_sys_param.deepsleep_dcfclk_mhz = v->dcf_clk_deep_sleep;
488 dlg_sys_param.total_flip_bytes = total_flip_bytes;
489
490 pipe_ctx_to_e2e_pipe_params(pipe, &input.pipe);
491 input.clks_cfg.dcfclk_mhz = v->dcfclk;
492 input.clks_cfg.dispclk_mhz = v->dispclk;
493 input.clks_cfg.dppclk_mhz = v->dppclk;
494 input.clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
495 input.clks_cfg.socclk_mhz = v->socclk;
496 input.clks_cfg.voltage = v->voltage_level;
497// dc->dml.logger = pool->base.logger;
498 input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? dm_420 : dm_444;
499 input.dout.output_type = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi : dm_dp;
500 //input[in_idx].dout.output_standard;
501
502 /*todo: soc->sr_enter_plus_exit_time??*/
503 dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / v->dcf_clk_deep_sleep;
504
505 dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
506 dml1_extract_rq_regs(dml, rq_regs, rq_param);
507 dml1_rq_dlg_get_dlg_params(
508 dml,
509 dlg_regs,
510 ttu_regs,
511 rq_param.dlg,
512 dlg_sys_param,
513 input,
514 true,
515 true,
516 v->pte_enable == dcn_bw_yes,
517 pipe->plane_state->flip_immediate);
518}
519
520static void split_stream_across_pipes(
521 struct resource_context *res_ctx,
522 const struct resource_pool *pool,
523 struct pipe_ctx *primary_pipe,
524 struct pipe_ctx *secondary_pipe)
525{
526 int pipe_idx = secondary_pipe->pipe_idx;
527
528 if (!primary_pipe->plane_state)
529 return;
530
531 *secondary_pipe = *primary_pipe;
532
533 secondary_pipe->pipe_idx = pipe_idx;
534 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
535 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
536 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
537 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
538 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
539 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
540 if (primary_pipe->bottom_pipe) {
541 ASSERT(primary_pipe->bottom_pipe != secondary_pipe);
542 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
543 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
544 }
545 primary_pipe->bottom_pipe = secondary_pipe;
546 secondary_pipe->top_pipe = primary_pipe;
547
548 resource_build_scaling_params(primary_pipe);
549 resource_build_scaling_params(secondary_pipe);
550}
551
552#if 0
553static void calc_wm_sets_and_perf_params(
554 struct dc_state *context,
555 struct dcn_bw_internal_vars *v)
556{
557 /* Calculate set A last to keep internal var state consistent for required config */
558 if (v->voltage_level < 2) {
559 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vnom0p8;
560 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vnom0p8;
561 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vnom0p8;
562 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
563
564 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
565 v->stutter_exit_watermark * 1000;
566 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
567 v->stutter_enter_plus_exit_watermark * 1000;
568 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
569 v->dram_clock_change_watermark * 1000;
570 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
571 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
572
573 v->dcfclk_per_state[1] = v->dcfclkv_nom0p8;
574 v->dcfclk_per_state[0] = v->dcfclkv_nom0p8;
575 v->dcfclk = v->dcfclkv_nom0p8;
576 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
577
578 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
579 v->stutter_exit_watermark * 1000;
580 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
581 v->stutter_enter_plus_exit_watermark * 1000;
582 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
583 v->dram_clock_change_watermark * 1000;
584 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
585 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
586 }
587
588 if (v->voltage_level < 3) {
589 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vmax0p9;
590 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmax0p9;
591 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmax0p9;
592 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_vmax0p9;
593 v->dcfclk_per_state[2] = v->dcfclkv_max0p9;
594 v->dcfclk_per_state[1] = v->dcfclkv_max0p9;
595 v->dcfclk_per_state[0] = v->dcfclkv_max0p9;
596 v->dcfclk = v->dcfclkv_max0p9;
597 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
598
599 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns =
600 v->stutter_exit_watermark * 1000;
601 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns =
602 v->stutter_enter_plus_exit_watermark * 1000;
603 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns =
604 v->dram_clock_change_watermark * 1000;
605 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
606 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = v->urgent_watermark * 1000;
607 }
608
609 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
610 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
611 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
612 v->fabric_and_dram_bandwidth = v->fabric_and_dram_bandwidth_per_state[v->voltage_level];
613 v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
614 v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
615 v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
616 v->dcfclk = v->dcfclk_per_state[v->voltage_level];
617 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
618
619 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
620 v->stutter_exit_watermark * 1000;
621 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
622 v->stutter_enter_plus_exit_watermark * 1000;
623 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
624 v->dram_clock_change_watermark * 1000;
625 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
626 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
627 if (v->voltage_level >= 2) {
628 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
629 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
630 }
631 if (v->voltage_level >= 3)
632 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
633}
634#endif
635
636static bool dcn_bw_apply_registry_override(struct dc *dc)
637{
638 bool updated = false;
639
640 DC_FP_START();
641 if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
642 && dc->debug.sr_exit_time_ns) {
643 updated = true;
644 dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;
645 }
646
647 if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)
648 != dc->debug.sr_enter_plus_exit_time_ns
649 && dc->debug.sr_enter_plus_exit_time_ns) {
650 updated = true;
651 dc->dcn_soc->sr_enter_plus_exit_time =
652 dc->debug.sr_enter_plus_exit_time_ns / 1000.0;
653 }
654
655 if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns
656 && dc->debug.urgent_latency_ns) {
657 updated = true;
658 dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;
659 }
660
661 if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)
662 != dc->debug.percent_of_ideal_drambw
663 && dc->debug.percent_of_ideal_drambw) {
664 updated = true;
665 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =
666 dc->debug.percent_of_ideal_drambw;
667 }
668
669 if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)
670 != dc->debug.dram_clock_change_latency_ns
671 && dc->debug.dram_clock_change_latency_ns) {
672 updated = true;
673 dc->dcn_soc->dram_clock_change_latency =
674 dc->debug.dram_clock_change_latency_ns / 1000.0;
675 }
676 DC_FP_END();
677
678 return updated;
679}
680
681static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
682{
683 /*
684 * disable optional pipe split by lower dispclk bounding box
685 * at DPM0
686 */
687 v->max_dispclk[0] = v->max_dppclk_vmin0p65;
688}
689
690static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
691 unsigned int pixel_rate_100hz)
692{
693 float pixel_rate_mhz = pixel_rate_100hz / 10000;
694
695 /*
696 * force enabling pipe split by lower dpp clock for DPM0 to just
697 * below the specify pixel_rate, so bw calc would split pipe.
698 */
699 if (pixel_rate_mhz < v->max_dppclk[0])
700 v->max_dppclk[0] = pixel_rate_mhz;
701}
702
703static void hack_bounding_box(struct dcn_bw_internal_vars *v,
704 struct dc_debug_options *dbg,
705 struct dc_state *context)
706{
707 int i;
708
709 for (i = 0; i < MAX_PIPES; i++) {
710 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
711
712 /**
713 * Workaround for avoiding pipe-split in cases where we'd split
714 * planes that are too small, resulting in splits that aren't
715 * valid for the scaler.
716 */
717 if (pipe->plane_state &&
718 (pipe->plane_state->dst_rect.width <= 16 ||
719 pipe->plane_state->dst_rect.height <= 16 ||
720 pipe->plane_state->src_rect.width <= 16 ||
721 pipe->plane_state->src_rect.height <= 16)) {
722 hack_disable_optional_pipe_split(v);
723 return;
724 }
725 }
726
727 if (dbg->pipe_split_policy == MPC_SPLIT_AVOID)
728 hack_disable_optional_pipe_split(v);
729
730 if (dbg->pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP &&
731 context->stream_count >= 2)
732 hack_disable_optional_pipe_split(v);
733
734 if (context->stream_count == 1 &&
735 dbg->force_single_disp_pipe_split)
736 hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_100hz);
737}
738
739unsigned int get_highest_allowed_voltage_level(uint32_t chip_family, uint32_t hw_internal_rev, uint32_t pci_revision_id)
740{
741 /* for low power RV2 variants, the highest voltage level we want is 0 */
742 if ((chip_family == FAMILY_RV) &&
743 ASICREV_IS_RAVEN2(hw_internal_rev))
744 switch (pci_revision_id) {
745 case PRID_DALI_DE:
746 case PRID_DALI_DF:
747 case PRID_DALI_E3:
748 case PRID_DALI_E4:
749 case PRID_POLLOCK_94:
750 case PRID_POLLOCK_95:
751 case PRID_POLLOCK_E9:
752 case PRID_POLLOCK_EA:
753 case PRID_POLLOCK_EB:
754 return 0;
755 default:
756 break;
757 }
758
759 /* we are ok with all levels */
760 return 4;
761}
762
763bool dcn_validate_bandwidth(
764 struct dc *dc,
765 struct dc_state *context,
766 bool fast_validate)
767{
768 /*
769 * we want a breakdown of the various stages of validation, which the
770 * perf_trace macro doesn't support
771 */
772 BW_VAL_TRACE_SETUP();
773
774 const struct resource_pool *pool = dc->res_pool;
775 struct dcn_bw_internal_vars *v = &context->dcn_bw_vars;
776 int i, input_idx, k;
777 int vesa_sync_start, asic_blank_end, asic_blank_start;
778 bool bw_limit_pass;
779 float bw_limit;
780
781 PERFORMANCE_TRACE_START();
782
783 BW_VAL_TRACE_COUNT();
784
785 if (dcn_bw_apply_registry_override(dc))
786 dcn_bw_sync_calcs_and_dml(dc);
787
788 memset(v, 0, sizeof(*v));
789 DC_FP_START();
790
791 v->sr_exit_time = dc->dcn_soc->sr_exit_time;
792 v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
793 v->urgent_latency = dc->dcn_soc->urgent_latency;
794 v->write_back_latency = dc->dcn_soc->write_back_latency;
795 v->percent_of_ideal_drambw_received_after_urg_latency =
796 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
797
798 v->dcfclkv_min0p65 = dc->dcn_soc->dcfclkv_min0p65;
799 v->dcfclkv_mid0p72 = dc->dcn_soc->dcfclkv_mid0p72;
800 v->dcfclkv_nom0p8 = dc->dcn_soc->dcfclkv_nom0p8;
801 v->dcfclkv_max0p9 = dc->dcn_soc->dcfclkv_max0p9;
802
803 v->max_dispclk_vmin0p65 = dc->dcn_soc->max_dispclk_vmin0p65;
804 v->max_dispclk_vmid0p72 = dc->dcn_soc->max_dispclk_vmid0p72;
805 v->max_dispclk_vnom0p8 = dc->dcn_soc->max_dispclk_vnom0p8;
806 v->max_dispclk_vmax0p9 = dc->dcn_soc->max_dispclk_vmax0p9;
807
808 v->max_dppclk_vmin0p65 = dc->dcn_soc->max_dppclk_vmin0p65;
809 v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72;
810 v->max_dppclk_vnom0p8 = dc->dcn_soc->max_dppclk_vnom0p8;
811 v->max_dppclk_vmax0p9 = dc->dcn_soc->max_dppclk_vmax0p9;
812
813 v->socclk = dc->dcn_soc->socclk;
814
815 v->fabric_and_dram_bandwidth_vmin0p65 = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65;
816 v->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72;
817 v->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8;
818 v->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9;
819
820 v->phyclkv_min0p65 = dc->dcn_soc->phyclkv_min0p65;
821 v->phyclkv_mid0p72 = dc->dcn_soc->phyclkv_mid0p72;
822 v->phyclkv_nom0p8 = dc->dcn_soc->phyclkv_nom0p8;
823 v->phyclkv_max0p9 = dc->dcn_soc->phyclkv_max0p9;
824
825 v->downspreading = dc->dcn_soc->downspreading;
826 v->round_trip_ping_latency_cycles = dc->dcn_soc->round_trip_ping_latency_cycles;
827 v->urgent_out_of_order_return_per_channel = dc->dcn_soc->urgent_out_of_order_return_per_channel;
828 v->number_of_channels = dc->dcn_soc->number_of_channels;
829 v->vmm_page_size = dc->dcn_soc->vmm_page_size;
830 v->dram_clock_change_latency = dc->dcn_soc->dram_clock_change_latency;
831 v->return_bus_width = dc->dcn_soc->return_bus_width;
832
833 v->rob_buffer_size_in_kbyte = dc->dcn_ip->rob_buffer_size_in_kbyte;
834 v->det_buffer_size_in_kbyte = dc->dcn_ip->det_buffer_size_in_kbyte;
835 v->dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
836 v->opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
837 v->pixel_chunk_size_in_kbyte = dc->dcn_ip->pixel_chunk_size_in_kbyte;
838 v->pte_enable = dc->dcn_ip->pte_enable;
839 v->pte_chunk_size = dc->dcn_ip->pte_chunk_size;
840 v->meta_chunk_size = dc->dcn_ip->meta_chunk_size;
841 v->writeback_chunk_size = dc->dcn_ip->writeback_chunk_size;
842 v->odm_capability = dc->dcn_ip->odm_capability;
843 v->dsc_capability = dc->dcn_ip->dsc_capability;
844 v->line_buffer_size = dc->dcn_ip->line_buffer_size;
845 v->is_line_buffer_bpp_fixed = dc->dcn_ip->is_line_buffer_bpp_fixed;
846 v->line_buffer_fixed_bpp = dc->dcn_ip->line_buffer_fixed_bpp;
847 v->max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
848 v->writeback_luma_buffer_size = dc->dcn_ip->writeback_luma_buffer_size;
849 v->writeback_chroma_buffer_size = dc->dcn_ip->writeback_chroma_buffer_size;
850 v->max_num_dpp = dc->dcn_ip->max_num_dpp;
851 v->max_num_writeback = dc->dcn_ip->max_num_writeback;
852 v->max_dchub_topscl_throughput = dc->dcn_ip->max_dchub_topscl_throughput;
853 v->max_pscl_tolb_throughput = dc->dcn_ip->max_pscl_tolb_throughput;
854 v->max_lb_tovscl_throughput = dc->dcn_ip->max_lb_tovscl_throughput;
855 v->max_vscl_tohscl_throughput = dc->dcn_ip->max_vscl_tohscl_throughput;
856 v->max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
857 v->max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
858 v->max_hscl_taps = dc->dcn_ip->max_hscl_taps;
859 v->max_vscl_taps = dc->dcn_ip->max_vscl_taps;
860 v->under_scan_factor = dc->dcn_ip->under_scan_factor;
861 v->pte_buffer_size_in_requests = dc->dcn_ip->pte_buffer_size_in_requests;
862 v->dispclk_ramping_margin = dc->dcn_ip->dispclk_ramping_margin;
863 v->max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
864 v->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
865 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
866 v->bug_forcing_luma_and_chroma_request_to_same_size_fixed =
867 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed;
868
869 v->voltage[5] = dcn_bw_no_support;
870 v->voltage[4] = dcn_bw_v_max0p9;
871 v->voltage[3] = dcn_bw_v_max0p9;
872 v->voltage[2] = dcn_bw_v_nom0p8;
873 v->voltage[1] = dcn_bw_v_mid0p72;
874 v->voltage[0] = dcn_bw_v_min0p65;
875 v->fabric_and_dram_bandwidth_per_state[5] = v->fabric_and_dram_bandwidth_vmax0p9;
876 v->fabric_and_dram_bandwidth_per_state[4] = v->fabric_and_dram_bandwidth_vmax0p9;
877 v->fabric_and_dram_bandwidth_per_state[3] = v->fabric_and_dram_bandwidth_vmax0p9;
878 v->fabric_and_dram_bandwidth_per_state[2] = v->fabric_and_dram_bandwidth_vnom0p8;
879 v->fabric_and_dram_bandwidth_per_state[1] = v->fabric_and_dram_bandwidth_vmid0p72;
880 v->fabric_and_dram_bandwidth_per_state[0] = v->fabric_and_dram_bandwidth_vmin0p65;
881 v->dcfclk_per_state[5] = v->dcfclkv_max0p9;
882 v->dcfclk_per_state[4] = v->dcfclkv_max0p9;
883 v->dcfclk_per_state[3] = v->dcfclkv_max0p9;
884 v->dcfclk_per_state[2] = v->dcfclkv_nom0p8;
885 v->dcfclk_per_state[1] = v->dcfclkv_mid0p72;
886 v->dcfclk_per_state[0] = v->dcfclkv_min0p65;
887 v->max_dispclk[5] = v->max_dispclk_vmax0p9;
888 v->max_dispclk[4] = v->max_dispclk_vmax0p9;
889 v->max_dispclk[3] = v->max_dispclk_vmax0p9;
890 v->max_dispclk[2] = v->max_dispclk_vnom0p8;
891 v->max_dispclk[1] = v->max_dispclk_vmid0p72;
892 v->max_dispclk[0] = v->max_dispclk_vmin0p65;
893 v->max_dppclk[5] = v->max_dppclk_vmax0p9;
894 v->max_dppclk[4] = v->max_dppclk_vmax0p9;
895 v->max_dppclk[3] = v->max_dppclk_vmax0p9;
896 v->max_dppclk[2] = v->max_dppclk_vnom0p8;
897 v->max_dppclk[1] = v->max_dppclk_vmid0p72;
898 v->max_dppclk[0] = v->max_dppclk_vmin0p65;
899 v->phyclk_per_state[5] = v->phyclkv_max0p9;
900 v->phyclk_per_state[4] = v->phyclkv_max0p9;
901 v->phyclk_per_state[3] = v->phyclkv_max0p9;
902 v->phyclk_per_state[2] = v->phyclkv_nom0p8;
903 v->phyclk_per_state[1] = v->phyclkv_mid0p72;
904 v->phyclk_per_state[0] = v->phyclkv_min0p65;
905 v->synchronized_vblank = dcn_bw_no;
906 v->ta_pscalculation = dcn_bw_override;
907 v->allow_different_hratio_vratio = dcn_bw_yes;
908
909 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
910 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
911
912 if (!pipe->stream)
913 continue;
914 /* skip all but first of split pipes */
915 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
916 continue;
917
918 v->underscan_output[input_idx] = false; /* taken care of in recout already*/
919 v->interlace_output[input_idx] = false;
920
921 v->htotal[input_idx] = pipe->stream->timing.h_total;
922 v->vtotal[input_idx] = pipe->stream->timing.v_total;
923 v->vactive[input_idx] = pipe->stream->timing.v_addressable +
924 pipe->stream->timing.v_border_top + pipe->stream->timing.v_border_bottom;
925 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
926 - v->vactive[input_idx]
927 - pipe->stream->timing.v_front_porch;
928 v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_100hz/10000.0;
929 if (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
930 v->pixel_clock[input_idx] *= 2;
931 if (!pipe->plane_state) {
932 v->dcc_enable[input_idx] = dcn_bw_yes;
933 v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
934 v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
935 v->lb_bit_per_pixel[input_idx] = 30;
936 v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
937 v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
938 /*
939 * for cases where we have no plane, we want to validate up to 1080p
940 * source size because here we are only interested in if the output
941 * timing is supported or not. if we cannot support native resolution
942 * of the high res display, we still want to support lower res up scale
943 * to native
944 */
945 if (v->viewport_width[input_idx] > 1920)
946 v->viewport_width[input_idx] = 1920;
947 if (v->viewport_height[input_idx] > 1080)
948 v->viewport_height[input_idx] = 1080;
949 v->scaler_rec_out_width[input_idx] = v->viewport_width[input_idx];
950 v->scaler_recout_height[input_idx] = v->viewport_height[input_idx];
951 v->override_hta_ps[input_idx] = 1;
952 v->override_vta_ps[input_idx] = 1;
953 v->override_hta_pschroma[input_idx] = 1;
954 v->override_vta_pschroma[input_idx] = 1;
955 v->source_scan[input_idx] = dcn_bw_hor;
956
957 } else {
958 v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height;
959 v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;
960 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;
961 v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;
962 if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) {
963 if (pipe->plane_state->rotation % 2 == 0) {
964 int viewport_end = pipe->plane_res.scl_data.viewport.width
965 + pipe->plane_res.scl_data.viewport.x;
966 int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width
967 + pipe->bottom_pipe->plane_res.scl_data.viewport.x;
968
969 if (viewport_end > viewport_b_end)
970 v->viewport_width[input_idx] = viewport_end
971 - pipe->bottom_pipe->plane_res.scl_data.viewport.x;
972 else
973 v->viewport_width[input_idx] = viewport_b_end
974 - pipe->plane_res.scl_data.viewport.x;
975 } else {
976 int viewport_end = pipe->plane_res.scl_data.viewport.height
977 + pipe->plane_res.scl_data.viewport.y;
978 int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height
979 + pipe->bottom_pipe->plane_res.scl_data.viewport.y;
980
981 if (viewport_end > viewport_b_end)
982 v->viewport_height[input_idx] = viewport_end
983 - pipe->bottom_pipe->plane_res.scl_data.viewport.y;
984 else
985 v->viewport_height[input_idx] = viewport_b_end
986 - pipe->plane_res.scl_data.viewport.y;
987 }
988 v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width
989 + pipe->bottom_pipe->plane_res.scl_data.recout.width;
990 }
991
992 if (pipe->plane_state->rotation % 2 == 0) {
993 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
994 || v->scaler_rec_out_width[input_idx] == v->viewport_width[input_idx]);
995 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
996 || v->scaler_recout_height[input_idx] == v->viewport_height[input_idx]);
997 } else {
998 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
999 || v->scaler_recout_height[input_idx] == v->viewport_width[input_idx]);
1000 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
1001 || v->scaler_rec_out_width[input_idx] == v->viewport_height[input_idx]);
1002 }
1003
1004 if (dc->debug.optimized_watermark) {
1005 /*
1006 * this method requires us to always re-calculate watermark when dcc change
1007 * between flip.
1008 */
1009 v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
1010 } else {
1011 /*
1012 * allow us to disable dcc on the fly without re-calculating WM
1013 *
1014 * extra overhead for DCC is quite small. for 1080p WM without
1015 * DCC is only 0.417us lower (urgent goes from 6.979us to 6.562us)
1016 */
1017 unsigned int bpe;
1018
1019 v->dcc_enable[input_idx] = dc->res_pool->hubbub->funcs->dcc_support_pixel_format(
1020 pipe->plane_state->format, &bpe) ? dcn_bw_yes : dcn_bw_no;
1021 }
1022
1023 v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs(
1024 pipe->plane_state->format);
1025 v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs(
1026 pipe->plane_state->tiling_info.gfx9.swizzle);
1027 v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);
1028 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
1029 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
1030 v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
1031 v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
1032 /*
1033 * Spreadsheet doesn't handle taps_c is one properly,
1034 * need to force Chroma to always be scaled to pass
1035 * bandwidth validation.
1036 */
1037 if (v->override_hta_pschroma[input_idx] == 1)
1038 v->override_hta_pschroma[input_idx] = 2;
1039 if (v->override_vta_pschroma[input_idx] == 1)
1040 v->override_vta_pschroma[input_idx] = 2;
1041 v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
1042 }
1043 if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
1044 v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp;
1045 v->dcc_rate[input_idx] = 1; /*TODO: Worst case? does this change?*/
1046 v->output_format[input_idx] = pipe->stream->timing.pixel_encoding ==
1047 PIXEL_ENCODING_YCBCR420 ? dcn_bw_420 : dcn_bw_444;
1048 v->output[input_idx] = pipe->stream->signal ==
1049 SIGNAL_TYPE_HDMI_TYPE_A ? dcn_bw_hdmi : dcn_bw_dp;
1050 v->output_deep_color[input_idx] = dcn_bw_encoder_8bpc;
1051 if (v->output[input_idx] == dcn_bw_hdmi) {
1052 switch (pipe->stream->timing.display_color_depth) {
1053 case COLOR_DEPTH_101010:
1054 v->output_deep_color[input_idx] = dcn_bw_encoder_10bpc;
1055 break;
1056 case COLOR_DEPTH_121212:
1057 v->output_deep_color[input_idx] = dcn_bw_encoder_12bpc;
1058 break;
1059 case COLOR_DEPTH_161616:
1060 v->output_deep_color[input_idx] = dcn_bw_encoder_16bpc;
1061 break;
1062 default:
1063 break;
1064 }
1065 }
1066
1067 input_idx++;
1068 }
1069 v->number_of_active_planes = input_idx;
1070
1071 scaler_settings_calculation(v);
1072
1073 hack_bounding_box(v, &dc->debug, context);
1074
1075 mode_support_and_system_configuration(v);
1076
1077 /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */
1078 if (v->voltage_level != 0
1079 && context->stream_count == 1
1080 && dc->debug.force_single_disp_pipe_split) {
1081 v->max_dppclk[0] = v->max_dppclk_vmin0p65;
1082 mode_support_and_system_configuration(v);
1083 }
1084
1085 if (v->voltage_level == 0 &&
1086 (dc->debug.sr_exit_time_dpm0_ns
1087 || dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {
1088
1089 if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)
1090 v->sr_enter_plus_exit_time =
1091 dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
1092 if (dc->debug.sr_exit_time_dpm0_ns)
1093 v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
1094 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
1095 context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time;
1096 mode_support_and_system_configuration(v);
1097 }
1098
1099 display_pipe_configuration(v);
1100
1101 for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1102 if (v->source_scan[k] == dcn_bw_hor)
1103 v->swath_width_y[k] = v->viewport_width[k] / v->dpp_per_plane[k];
1104 else
1105 v->swath_width_y[k] = v->viewport_height[k] / v->dpp_per_plane[k];
1106 }
1107 for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1108 if (v->source_pixel_format[k] == dcn_bw_rgb_sub_64) {
1109 v->byte_per_pixel_dety[k] = 8.0;
1110 v->byte_per_pixel_detc[k] = 0.0;
1111 } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_32) {
1112 v->byte_per_pixel_dety[k] = 4.0;
1113 v->byte_per_pixel_detc[k] = 0.0;
1114 } else if (v->source_pixel_format[k] == dcn_bw_rgb_sub_16) {
1115 v->byte_per_pixel_dety[k] = 2.0;
1116 v->byte_per_pixel_detc[k] = 0.0;
1117 } else if (v->source_pixel_format[k] == dcn_bw_yuv420_sub_8) {
1118 v->byte_per_pixel_dety[k] = 1.0;
1119 v->byte_per_pixel_detc[k] = 2.0;
1120 } else {
1121 v->byte_per_pixel_dety[k] = 4.0f / 3.0f;
1122 v->byte_per_pixel_detc[k] = 8.0f / 3.0f;
1123 }
1124 }
1125
1126 v->total_data_read_bandwidth = 0.0;
1127 for (k = 0; k <= v->number_of_active_planes - 1; k++) {
1128 v->read_bandwidth_plane_luma[k] = v->swath_width_y[k] * v->dpp_per_plane[k] *
1129 dcn_bw_ceil2(v->byte_per_pixel_dety[k], 1.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k];
1130 v->read_bandwidth_plane_chroma[k] = v->swath_width_y[k] / 2.0 * v->dpp_per_plane[k] *
1131 dcn_bw_ceil2(v->byte_per_pixel_detc[k], 2.0) / (v->htotal[k] / v->pixel_clock[k]) * v->v_ratio[k] / 2.0;
1132 v->total_data_read_bandwidth = v->total_data_read_bandwidth +
1133 v->read_bandwidth_plane_luma[k] + v->read_bandwidth_plane_chroma[k];
1134 }
1135
1136 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1137
1138 if (v->voltage_level != number_of_states_plus_one && !fast_validate) {
1139 float bw_consumed = v->total_bandwidth_consumed_gbyte_per_second;
1140
1141 if (bw_consumed < v->fabric_and_dram_bandwidth_vmin0p65)
1142 bw_consumed = v->fabric_and_dram_bandwidth_vmin0p65;
1143 else if (bw_consumed < v->fabric_and_dram_bandwidth_vmid0p72)
1144 bw_consumed = v->fabric_and_dram_bandwidth_vmid0p72;
1145 else if (bw_consumed < v->fabric_and_dram_bandwidth_vnom0p8)
1146 bw_consumed = v->fabric_and_dram_bandwidth_vnom0p8;
1147 else
1148 bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
1149
1150 if (bw_consumed < v->fabric_and_dram_bandwidth)
1151 if (dc->debug.voltage_align_fclk)
1152 bw_consumed = v->fabric_and_dram_bandwidth;
1153
1154 display_pipe_configuration(v);
1155 /*calc_wm_sets_and_perf_params(context, v);*/
1156 /* Only 1 set is used by dcn since no noticeable
1157 * performance improvement was measured and due to hw bug DEGVIDCN10-254
1158 */
1159 dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation(v);
1160
1161 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns =
1162 v->stutter_exit_watermark * 1000;
1163 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns =
1164 v->stutter_enter_plus_exit_watermark * 1000;
1165 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns =
1166 v->dram_clock_change_watermark * 1000;
1167 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
1168 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = v->urgent_watermark * 1000;
1169 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
1170 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
1171 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1172
1173 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 /
1174 (ddr4_dram_factor_single_Channel * v->number_of_channels));
1175 if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65)
1176 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32);
1177
1178 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
1179 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000);
1180
1181 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000);
1182 if (dc->debug.max_disp_clk == true)
1183 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
1184
1185 if (context->bw_ctx.bw.dcn.clk.dispclk_khz <
1186 dc->debug.min_disp_clk_khz) {
1187 context->bw_ctx.bw.dcn.clk.dispclk_khz =
1188 dc->debug.min_disp_clk_khz;
1189 }
1190
1191 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /
1192 v->dispclk_dppclk_ratio;
1193 context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level];
1194 switch (v->voltage_level) {
1195 case 0:
1196 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1197 (int)(dc->dcn_soc->max_dppclk_vmin0p65 * 1000);
1198 break;
1199 case 1:
1200 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1201 (int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000);
1202 break;
1203 case 2:
1204 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1205 (int)(dc->dcn_soc->max_dppclk_vnom0p8 * 1000);
1206 break;
1207 default:
1208 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1209 (int)(dc->dcn_soc->max_dppclk_vmax0p9 * 1000);
1210 break;
1211 }
1212
1213 BW_VAL_TRACE_END_WATERMARKS();
1214
1215 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
1216 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1217
1218 /* skip inactive pipe */
1219 if (!pipe->stream)
1220 continue;
1221 /* skip all but first of split pipes */
1222 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1223 continue;
1224
1225 pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1226 pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1227 pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1228 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1229
1230 pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1231 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1232 vesa_sync_start = pipe->stream->timing.v_addressable +
1233 pipe->stream->timing.v_border_bottom +
1234 pipe->stream->timing.v_front_porch;
1235
1236 asic_blank_end = (pipe->stream->timing.v_total -
1237 vesa_sync_start -
1238 pipe->stream->timing.v_border_top)
1239 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1240
1241 asic_blank_start = asic_blank_end +
1242 (pipe->stream->timing.v_border_top +
1243 pipe->stream->timing.v_addressable +
1244 pipe->stream->timing.v_border_bottom)
1245 * (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
1246
1247 pipe->pipe_dlg_param.vblank_start = asic_blank_start;
1248 pipe->pipe_dlg_param.vblank_end = asic_blank_end;
1249
1250 if (pipe->plane_state) {
1251 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1252
1253 pipe->plane_state->update_flags.bits.full_update = 1;
1254
1255 if (v->dpp_per_plane[input_idx] == 2 ||
1256 ((pipe->stream->view_format ==
1257 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
1258 pipe->stream->view_format ==
1259 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
1260 (pipe->stream->timing.timing_3d_format ==
1261 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
1262 pipe->stream->timing.timing_3d_format ==
1263 TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
1264 if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1265 /* update previously split pipe */
1266 hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1267 hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1268 hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1269 hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1270
1271 hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1272 hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
1273 hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
1274 hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
1275 } else {
1276 /* pipe not split previously needs split */
1277 hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool, pipe);
1278 ASSERT(hsplit_pipe);
1279 split_stream_across_pipes(&context->res_ctx, pool, pipe, hsplit_pipe);
1280 }
1281
1282 dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx);
1283 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1284 /* merge previously split pipe */
1285 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1286 if (hsplit_pipe->bottom_pipe)
1287 hsplit_pipe->bottom_pipe->top_pipe = pipe;
1288 hsplit_pipe->plane_state = NULL;
1289 hsplit_pipe->stream = NULL;
1290 hsplit_pipe->top_pipe = NULL;
1291 hsplit_pipe->bottom_pipe = NULL;
1292 /* Clear plane_res and stream_res */
1293 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
1294 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
1295 resource_build_scaling_params(pipe);
1296 }
1297 /* for now important to do this after pipe split for building e2e params */
1298 dcn_bw_calc_rq_dlg_ttu(dc, v, pipe, input_idx);
1299 }
1300
1301 input_idx++;
1302 }
1303 } else if (v->voltage_level == number_of_states_plus_one) {
1304 BW_VAL_TRACE_SKIP(fail);
1305 } else if (fast_validate) {
1306 BW_VAL_TRACE_SKIP(fast);
1307 }
1308
1309 if (v->voltage_level == 0) {
1310 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us =
1311 dc->dcn_soc->sr_enter_plus_exit_time;
1312 context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1313 }
1314
1315 /*
1316 * BW limit is set to prevent display from impacting other system functions
1317 */
1318
1319 bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
1320 bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
1321
1322 DC_FP_END();
1323
1324 PERFORMANCE_TRACE_END();
1325 BW_VAL_TRACE_FINISH();
1326
1327 if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(
1328 dc->ctx->asic_id.chip_family,
1329 dc->ctx->asic_id.hw_internal_rev,
1330 dc->ctx->asic_id.pci_revision_id))
1331 return true;
1332 else
1333 return false;
1334}
1335
1336static unsigned int dcn_find_normalized_clock_vdd_Level(
1337 const struct dc *dc,
1338 enum dm_pp_clock_type clocks_type,
1339 int clocks_in_khz)
1340{
1341 int vdd_level = dcn_bw_v_min0p65;
1342
1343 if (clocks_in_khz == 0)/*todo some clock not in the considerations*/
1344 return vdd_level;
1345
1346 switch (clocks_type) {
1347 case DM_PP_CLOCK_TYPE_DISPLAY_CLK:
1348 if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmax0p9*1000) {
1349 vdd_level = dcn_bw_v_max0p91;
1350 BREAK_TO_DEBUGGER();
1351 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vnom0p8*1000) {
1352 vdd_level = dcn_bw_v_max0p9;
1353 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmid0p72*1000) {
1354 vdd_level = dcn_bw_v_nom0p8;
1355 } else if (clocks_in_khz > dc->dcn_soc->max_dispclk_vmin0p65*1000) {
1356 vdd_level = dcn_bw_v_mid0p72;
1357 } else
1358 vdd_level = dcn_bw_v_min0p65;
1359 break;
1360 case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK:
1361 if (clocks_in_khz > dc->dcn_soc->phyclkv_max0p9*1000) {
1362 vdd_level = dcn_bw_v_max0p91;
1363 BREAK_TO_DEBUGGER();
1364 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_nom0p8*1000) {
1365 vdd_level = dcn_bw_v_max0p9;
1366 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_mid0p72*1000) {
1367 vdd_level = dcn_bw_v_nom0p8;
1368 } else if (clocks_in_khz > dc->dcn_soc->phyclkv_min0p65*1000) {
1369 vdd_level = dcn_bw_v_mid0p72;
1370 } else
1371 vdd_level = dcn_bw_v_min0p65;
1372 break;
1373
1374 case DM_PP_CLOCK_TYPE_DPPCLK:
1375 if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmax0p9*1000) {
1376 vdd_level = dcn_bw_v_max0p91;
1377 BREAK_TO_DEBUGGER();
1378 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vnom0p8*1000) {
1379 vdd_level = dcn_bw_v_max0p9;
1380 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) {
1381 vdd_level = dcn_bw_v_nom0p8;
1382 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmin0p65*1000) {
1383 vdd_level = dcn_bw_v_mid0p72;
1384 } else
1385 vdd_level = dcn_bw_v_min0p65;
1386 break;
1387
1388 case DM_PP_CLOCK_TYPE_MEMORY_CLK:
1389 {
1390 unsigned factor = (ddr4_dram_factor_single_Channel * dc->dcn_soc->number_of_channels);
1391
1392 if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9*1000000/factor) {
1393 vdd_level = dcn_bw_v_max0p91;
1394 BREAK_TO_DEBUGGER();
1395 } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8*1000000/factor) {
1396 vdd_level = dcn_bw_v_max0p9;
1397 } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72*1000000/factor) {
1398 vdd_level = dcn_bw_v_nom0p8;
1399 } else if (clocks_in_khz > dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65*1000000/factor) {
1400 vdd_level = dcn_bw_v_mid0p72;
1401 } else
1402 vdd_level = dcn_bw_v_min0p65;
1403 }
1404 break;
1405
1406 case DM_PP_CLOCK_TYPE_DCFCLK:
1407 if (clocks_in_khz > dc->dcn_soc->dcfclkv_max0p9*1000) {
1408 vdd_level = dcn_bw_v_max0p91;
1409 BREAK_TO_DEBUGGER();
1410 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_nom0p8*1000) {
1411 vdd_level = dcn_bw_v_max0p9;
1412 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_mid0p72*1000) {
1413 vdd_level = dcn_bw_v_nom0p8;
1414 } else if (clocks_in_khz > dc->dcn_soc->dcfclkv_min0p65*1000) {
1415 vdd_level = dcn_bw_v_mid0p72;
1416 } else
1417 vdd_level = dcn_bw_v_min0p65;
1418 break;
1419
1420 default:
1421 break;
1422 }
1423 return vdd_level;
1424}
1425
1426unsigned int dcn_find_dcfclk_suits_all(
1427 const struct dc *dc,
1428 struct dc_clocks *clocks)
1429{
1430 unsigned vdd_level, vdd_level_temp;
1431 unsigned dcf_clk;
1432
1433 /*find a common supported voltage level*/
1434 vdd_level = dcn_find_normalized_clock_vdd_Level(
1435 dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz);
1436 vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1437 dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz);
1438
1439 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1440 vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1441 dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
1442 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1443
1444 vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1445 dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz);
1446 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1447 vdd_level_temp = dcn_find_normalized_clock_vdd_Level(
1448 dc, DM_PP_CLOCK_TYPE_DCFCLK, clocks->dcfclk_khz);
1449
1450 /*find that level conresponding dcfclk*/
1451 vdd_level = dcn_bw_max(vdd_level, vdd_level_temp);
1452 if (vdd_level == dcn_bw_v_max0p91) {
1453 BREAK_TO_DEBUGGER();
1454 dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
1455 } else if (vdd_level == dcn_bw_v_max0p9)
1456 dcf_clk = dc->dcn_soc->dcfclkv_max0p9*1000;
1457 else if (vdd_level == dcn_bw_v_nom0p8)
1458 dcf_clk = dc->dcn_soc->dcfclkv_nom0p8*1000;
1459 else if (vdd_level == dcn_bw_v_mid0p72)
1460 dcf_clk = dc->dcn_soc->dcfclkv_mid0p72*1000;
1461 else
1462 dcf_clk = dc->dcn_soc->dcfclkv_min0p65*1000;
1463
1464 DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk);
1465 return dcf_clk;
1466}
1467
1468static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks)
1469{
1470 int i;
1471
1472 if (clks->num_levels == 0)
1473 return false;
1474
1475 for (i = 0; i < clks->num_levels; i++)
1476 /* Ensure that the result is sane */
1477 if (clks->data[i].clocks_in_khz == 0)
1478 return false;
1479
1480 return true;
1481}
1482
1483void dcn_bw_update_from_pplib(struct dc *dc)
1484{
1485 struct dc_context *ctx = dc->ctx;
1486 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0};
1487 bool res;
1488 unsigned vmin0p65_idx, vmid0p72_idx, vnom0p8_idx, vmax0p9_idx;
1489
1490 /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */
1491 res = dm_pp_get_clock_levels_by_type_with_voltage(
1492 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
1493
1494 DC_FP_START();
1495
1496 if (res)
1497 res = verify_clock_values(&fclks);
1498
1499 if (res) {
1500 ASSERT(fclks.num_levels);
1501
1502 vmin0p65_idx = 0;
1503 vmid0p72_idx = fclks.num_levels -
1504 (fclks.num_levels > 2 ? 3 : (fclks.num_levels > 1 ? 2 : 1));
1505 vnom0p8_idx = fclks.num_levels - (fclks.num_levels > 1 ? 2 : 1);
1506 vmax0p9_idx = fclks.num_levels - 1;
1507
1508 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 =
1509 32 * (fclks.data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0;
1510 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 =
1511 dc->dcn_soc->number_of_channels *
1512 (fclks.data[vmid0p72_idx].clocks_in_khz / 1000.0)
1513 * ddr4_dram_factor_single_Channel / 1000.0;
1514 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 =
1515 dc->dcn_soc->number_of_channels *
1516 (fclks.data[vnom0p8_idx].clocks_in_khz / 1000.0)
1517 * ddr4_dram_factor_single_Channel / 1000.0;
1518 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 =
1519 dc->dcn_soc->number_of_channels *
1520 (fclks.data[vmax0p9_idx].clocks_in_khz / 1000.0)
1521 * ddr4_dram_factor_single_Channel / 1000.0;
1522 } else
1523 BREAK_TO_DEBUGGER();
1524
1525 DC_FP_END();
1526
1527 res = dm_pp_get_clock_levels_by_type_with_voltage(
1528 ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
1529
1530 DC_FP_START();
1531
1532 if (res)
1533 res = verify_clock_values(&dcfclks);
1534
1535 if (res && dcfclks.num_levels >= 3) {
1536 dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0;
1537 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0;
1538 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0;
1539 dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0;
1540 } else
1541 BREAK_TO_DEBUGGER();
1542
1543 DC_FP_END();
1544}
1545
1546void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
1547{
1548 struct pp_smu_funcs_rv *pp = NULL;
1549 struct pp_smu_wm_range_sets ranges = {0};
1550 int min_fclk_khz, min_dcfclk_khz, socclk_khz;
1551 const int overdrive = 5000000; /* 5 GHz to cover Overdrive */
1552
1553 if (dc->res_pool->pp_smu)
1554 pp = &dc->res_pool->pp_smu->rv_funcs;
1555 if (!pp || !pp->set_wm_ranges)
1556 return;
1557
1558 DC_FP_START();
1559 min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
1560 min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
1561 socclk_khz = dc->dcn_soc->socclk * 1000;
1562 DC_FP_END();
1563
1564 /* Now notify PPLib/SMU about which Watermarks sets they should select
1565 * depending on DPM state they are in. And update BW MGR GFX Engine and
1566 * Memory clock member variables for Watermarks calculations for each
1567 * Watermark Set. Only one watermark set for dcn1 due to hw bug DEGVIDCN10-254.
1568 */
1569 /* SOCCLK does not affect anytihng but writeback for DCN so for now we dont
1570 * care what the value is, hence min to overdrive level
1571 */
1572 ranges.num_reader_wm_sets = WM_SET_COUNT;
1573 ranges.num_writer_wm_sets = WM_SET_COUNT;
1574 ranges.reader_wm_sets[0].wm_inst = WM_A;
1575 ranges.reader_wm_sets[0].min_drain_clk_mhz = min_dcfclk_khz / 1000;
1576 ranges.reader_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1577 ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000;
1578 ranges.reader_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1579 ranges.writer_wm_sets[0].wm_inst = WM_A;
1580 ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000;
1581 ranges.writer_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
1582 ranges.writer_wm_sets[0].min_drain_clk_mhz = min_fclk_khz / 1000;
1583 ranges.writer_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
1584
1585 if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) {
1586 ranges.reader_wm_sets[0].wm_inst = WM_A;
1587 ranges.reader_wm_sets[0].min_drain_clk_mhz = 300;
1588 ranges.reader_wm_sets[0].max_drain_clk_mhz = 5000;
1589 ranges.reader_wm_sets[0].min_fill_clk_mhz = 800;
1590 ranges.reader_wm_sets[0].max_fill_clk_mhz = 5000;
1591 ranges.writer_wm_sets[0].wm_inst = WM_A;
1592 ranges.writer_wm_sets[0].min_fill_clk_mhz = 200;
1593 ranges.writer_wm_sets[0].max_fill_clk_mhz = 5000;
1594 ranges.writer_wm_sets[0].min_drain_clk_mhz = 800;
1595 ranges.writer_wm_sets[0].max_drain_clk_mhz = 5000;
1596 }
1597
1598 ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0];
1599 ranges.reader_wm_sets[1].wm_inst = WM_B;
1600
1601 ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0];
1602 ranges.reader_wm_sets[2].wm_inst = WM_C;
1603
1604 ranges.reader_wm_sets[3] = ranges.writer_wm_sets[0];
1605 ranges.reader_wm_sets[3].wm_inst = WM_D;
1606
1607 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1608 pp->set_wm_ranges(&pp->pp_smu, &ranges);
1609}
1610
1611void dcn_bw_sync_calcs_and_dml(struct dc *dc)
1612{
1613 DC_FP_START();
1614 DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
1615 "sr_enter_plus_exit_time: %f ns\n"
1616 "urgent_latency: %f ns\n"
1617 "write_back_latency: %f ns\n"
1618 "percent_of_ideal_drambw_received_after_urg_latency: %f %%\n"
1619 "max_request_size: %d bytes\n"
1620 "dcfclkv_max0p9: %f kHz\n"
1621 "dcfclkv_nom0p8: %f kHz\n"
1622 "dcfclkv_mid0p72: %f kHz\n"
1623 "dcfclkv_min0p65: %f kHz\n"
1624 "max_dispclk_vmax0p9: %f kHz\n"
1625 "max_dispclk_vnom0p8: %f kHz\n"
1626 "max_dispclk_vmid0p72: %f kHz\n"
1627 "max_dispclk_vmin0p65: %f kHz\n"
1628 "max_dppclk_vmax0p9: %f kHz\n"
1629 "max_dppclk_vnom0p8: %f kHz\n"
1630 "max_dppclk_vmid0p72: %f kHz\n"
1631 "max_dppclk_vmin0p65: %f kHz\n"
1632 "socclk: %f kHz\n"
1633 "fabric_and_dram_bandwidth_vmax0p9: %f MB/s\n"
1634 "fabric_and_dram_bandwidth_vnom0p8: %f MB/s\n"
1635 "fabric_and_dram_bandwidth_vmid0p72: %f MB/s\n"
1636 "fabric_and_dram_bandwidth_vmin0p65: %f MB/s\n"
1637 "phyclkv_max0p9: %f kHz\n"
1638 "phyclkv_nom0p8: %f kHz\n"
1639 "phyclkv_mid0p72: %f kHz\n"
1640 "phyclkv_min0p65: %f kHz\n"
1641 "downspreading: %f %%\n"
1642 "round_trip_ping_latency_cycles: %d DCFCLK Cycles\n"
1643 "urgent_out_of_order_return_per_channel: %d Bytes\n"
1644 "number_of_channels: %d\n"
1645 "vmm_page_size: %d Bytes\n"
1646 "dram_clock_change_latency: %f ns\n"
1647 "return_bus_width: %d Bytes\n",
1648 dc->dcn_soc->sr_exit_time * 1000,
1649 dc->dcn_soc->sr_enter_plus_exit_time * 1000,
1650 dc->dcn_soc->urgent_latency * 1000,
1651 dc->dcn_soc->write_back_latency * 1000,
1652 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency,
1653 dc->dcn_soc->max_request_size,
1654 dc->dcn_soc->dcfclkv_max0p9 * 1000,
1655 dc->dcn_soc->dcfclkv_nom0p8 * 1000,
1656 dc->dcn_soc->dcfclkv_mid0p72 * 1000,
1657 dc->dcn_soc->dcfclkv_min0p65 * 1000,
1658 dc->dcn_soc->max_dispclk_vmax0p9 * 1000,
1659 dc->dcn_soc->max_dispclk_vnom0p8 * 1000,
1660 dc->dcn_soc->max_dispclk_vmid0p72 * 1000,
1661 dc->dcn_soc->max_dispclk_vmin0p65 * 1000,
1662 dc->dcn_soc->max_dppclk_vmax0p9 * 1000,
1663 dc->dcn_soc->max_dppclk_vnom0p8 * 1000,
1664 dc->dcn_soc->max_dppclk_vmid0p72 * 1000,
1665 dc->dcn_soc->max_dppclk_vmin0p65 * 1000,
1666 dc->dcn_soc->socclk * 1000,
1667 dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 * 1000,
1668 dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 * 1000,
1669 dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 * 1000,
1670 dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000,
1671 dc->dcn_soc->phyclkv_max0p9 * 1000,
1672 dc->dcn_soc->phyclkv_nom0p8 * 1000,
1673 dc->dcn_soc->phyclkv_mid0p72 * 1000,
1674 dc->dcn_soc->phyclkv_min0p65 * 1000,
1675 dc->dcn_soc->downspreading * 100,
1676 dc->dcn_soc->round_trip_ping_latency_cycles,
1677 dc->dcn_soc->urgent_out_of_order_return_per_channel,
1678 dc->dcn_soc->number_of_channels,
1679 dc->dcn_soc->vmm_page_size,
1680 dc->dcn_soc->dram_clock_change_latency * 1000,
1681 dc->dcn_soc->return_bus_width);
1682 DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %f\n"
1683 "det_buffer_size_in_kbyte: %f\n"
1684 "dpp_output_buffer_pixels: %f\n"
1685 "opp_output_buffer_lines: %f\n"
1686 "pixel_chunk_size_in_kbyte: %f\n"
1687 "pte_enable: %d\n"
1688 "pte_chunk_size: %d kbytes\n"
1689 "meta_chunk_size: %d kbytes\n"
1690 "writeback_chunk_size: %d kbytes\n"
1691 "odm_capability: %d\n"
1692 "dsc_capability: %d\n"
1693 "line_buffer_size: %d bits\n"
1694 "max_line_buffer_lines: %d\n"
1695 "is_line_buffer_bpp_fixed: %d\n"
1696 "line_buffer_fixed_bpp: %d\n"
1697 "writeback_luma_buffer_size: %d kbytes\n"
1698 "writeback_chroma_buffer_size: %d kbytes\n"
1699 "max_num_dpp: %d\n"
1700 "max_num_writeback: %d\n"
1701 "max_dchub_topscl_throughput: %d pixels/dppclk\n"
1702 "max_pscl_tolb_throughput: %d pixels/dppclk\n"
1703 "max_lb_tovscl_throughput: %d pixels/dppclk\n"
1704 "max_vscl_tohscl_throughput: %d pixels/dppclk\n"
1705 "max_hscl_ratio: %f\n"
1706 "max_vscl_ratio: %f\n"
1707 "max_hscl_taps: %d\n"
1708 "max_vscl_taps: %d\n"
1709 "pte_buffer_size_in_requests: %d\n"
1710 "dispclk_ramping_margin: %f %%\n"
1711 "under_scan_factor: %f %%\n"
1712 "max_inter_dcn_tile_repeaters: %d\n"
1713 "can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one: %d\n"
1714 "bug_forcing_luma_and_chroma_request_to_same_size_fixed: %d\n"
1715 "dcfclk_cstate_latency: %d\n",
1716 dc->dcn_ip->rob_buffer_size_in_kbyte,
1717 dc->dcn_ip->det_buffer_size_in_kbyte,
1718 dc->dcn_ip->dpp_output_buffer_pixels,
1719 dc->dcn_ip->opp_output_buffer_lines,
1720 dc->dcn_ip->pixel_chunk_size_in_kbyte,
1721 dc->dcn_ip->pte_enable,
1722 dc->dcn_ip->pte_chunk_size,
1723 dc->dcn_ip->meta_chunk_size,
1724 dc->dcn_ip->writeback_chunk_size,
1725 dc->dcn_ip->odm_capability,
1726 dc->dcn_ip->dsc_capability,
1727 dc->dcn_ip->line_buffer_size,
1728 dc->dcn_ip->max_line_buffer_lines,
1729 dc->dcn_ip->is_line_buffer_bpp_fixed,
1730 dc->dcn_ip->line_buffer_fixed_bpp,
1731 dc->dcn_ip->writeback_luma_buffer_size,
1732 dc->dcn_ip->writeback_chroma_buffer_size,
1733 dc->dcn_ip->max_num_dpp,
1734 dc->dcn_ip->max_num_writeback,
1735 dc->dcn_ip->max_dchub_topscl_throughput,
1736 dc->dcn_ip->max_pscl_tolb_throughput,
1737 dc->dcn_ip->max_lb_tovscl_throughput,
1738 dc->dcn_ip->max_vscl_tohscl_throughput,
1739 dc->dcn_ip->max_hscl_ratio,
1740 dc->dcn_ip->max_vscl_ratio,
1741 dc->dcn_ip->max_hscl_taps,
1742 dc->dcn_ip->max_vscl_taps,
1743 dc->dcn_ip->pte_buffer_size_in_requests,
1744 dc->dcn_ip->dispclk_ramping_margin,
1745 dc->dcn_ip->under_scan_factor * 100,
1746 dc->dcn_ip->max_inter_dcn_tile_repeaters,
1747 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one,
1748 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed,
1749 dc->dcn_ip->dcfclk_cstate_latency);
1750
1751 dc->dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time;
1752 dc->dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time;
1753 dc->dml.soc.urgent_latency_us = dc->dcn_soc->urgent_latency;
1754 dc->dml.soc.writeback_latency_us = dc->dcn_soc->write_back_latency;
1755 dc->dml.soc.ideal_dram_bw_after_urgent_percent =
1756 dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency;
1757 dc->dml.soc.max_request_size_bytes = dc->dcn_soc->max_request_size;
1758 dc->dml.soc.downspread_percent = dc->dcn_soc->downspreading;
1759 dc->dml.soc.round_trip_ping_latency_dcfclk_cycles =
1760 dc->dcn_soc->round_trip_ping_latency_cycles;
1761 dc->dml.soc.urgent_out_of_order_return_per_channel_bytes =
1762 dc->dcn_soc->urgent_out_of_order_return_per_channel;
1763 dc->dml.soc.num_chans = dc->dcn_soc->number_of_channels;
1764 dc->dml.soc.vmm_page_size_bytes = dc->dcn_soc->vmm_page_size;
1765 dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency;
1766 dc->dml.soc.return_bus_width_bytes = dc->dcn_soc->return_bus_width;
1767
1768 dc->dml.ip.rob_buffer_size_kbytes = dc->dcn_ip->rob_buffer_size_in_kbyte;
1769 dc->dml.ip.det_buffer_size_kbytes = dc->dcn_ip->det_buffer_size_in_kbyte;
1770 dc->dml.ip.dpp_output_buffer_pixels = dc->dcn_ip->dpp_output_buffer_pixels;
1771 dc->dml.ip.opp_output_buffer_lines = dc->dcn_ip->opp_output_buffer_lines;
1772 dc->dml.ip.pixel_chunk_size_kbytes = dc->dcn_ip->pixel_chunk_size_in_kbyte;
1773 dc->dml.ip.pte_enable = dc->dcn_ip->pte_enable == dcn_bw_yes;
1774 dc->dml.ip.pte_chunk_size_kbytes = dc->dcn_ip->pte_chunk_size;
1775 dc->dml.ip.meta_chunk_size_kbytes = dc->dcn_ip->meta_chunk_size;
1776 dc->dml.ip.writeback_chunk_size_kbytes = dc->dcn_ip->writeback_chunk_size;
1777 dc->dml.ip.line_buffer_size_bits = dc->dcn_ip->line_buffer_size;
1778 dc->dml.ip.max_line_buffer_lines = dc->dcn_ip->max_line_buffer_lines;
1779 dc->dml.ip.IsLineBufferBppFixed = dc->dcn_ip->is_line_buffer_bpp_fixed == dcn_bw_yes;
1780 dc->dml.ip.LineBufferFixedBpp = dc->dcn_ip->line_buffer_fixed_bpp;
1781 dc->dml.ip.writeback_luma_buffer_size_kbytes = dc->dcn_ip->writeback_luma_buffer_size;
1782 dc->dml.ip.writeback_chroma_buffer_size_kbytes = dc->dcn_ip->writeback_chroma_buffer_size;
1783 dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp;
1784 dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback;
1785 dc->dml.ip.max_dchub_pscl_bw_pix_per_clk = dc->dcn_ip->max_dchub_topscl_throughput;
1786 dc->dml.ip.max_pscl_lb_bw_pix_per_clk = dc->dcn_ip->max_pscl_tolb_throughput;
1787 dc->dml.ip.max_lb_vscl_bw_pix_per_clk = dc->dcn_ip->max_lb_tovscl_throughput;
1788 dc->dml.ip.max_vscl_hscl_bw_pix_per_clk = dc->dcn_ip->max_vscl_tohscl_throughput;
1789 dc->dml.ip.max_hscl_ratio = dc->dcn_ip->max_hscl_ratio;
1790 dc->dml.ip.max_vscl_ratio = dc->dcn_ip->max_vscl_ratio;
1791 dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps;
1792 dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps;
1793 /*pte_buffer_size_in_requests missing in dml*/
1794 dc->dml.ip.dispclk_ramp_margin_percent = dc->dcn_ip->dispclk_ramping_margin;
1795 dc->dml.ip.underscan_factor = dc->dcn_ip->under_scan_factor;
1796 dc->dml.ip.max_inter_dcn_tile_repeaters = dc->dcn_ip->max_inter_dcn_tile_repeaters;
1797 dc->dml.ip.can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one =
1798 dc->dcn_ip->can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one == dcn_bw_yes;
1799 dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
1800 dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
1801 dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
1802 DC_FP_END();
1803}