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1/*
2 * Copyright © 2007 David Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * David Airlie
25 */
26
27#include <linux/module.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/vga_switcheroo.h>
31
32#include <drm/amdgpu_drm.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_fb_helper.h>
36#include <drm/drm_fourcc.h>
37
38#include "amdgpu.h"
39#include "cikd.h"
40#include "amdgpu_gem.h"
41
42#include "amdgpu_display.h"
43
44/* object hierarchy -
45 this contains a helper + a amdgpu fb
46 the helper contains a pointer to amdgpu framebuffer baseclass.
47*/
48
49static int
50amdgpufb_open(struct fb_info *info, int user)
51{
52 struct drm_fb_helper *fb_helper = info->par;
53 int ret = pm_runtime_get_sync(fb_helper->dev->dev);
54 if (ret < 0 && ret != -EACCES) {
55 pm_runtime_mark_last_busy(fb_helper->dev->dev);
56 pm_runtime_put_autosuspend(fb_helper->dev->dev);
57 return ret;
58 }
59 return 0;
60}
61
62static int
63amdgpufb_release(struct fb_info *info, int user)
64{
65 struct drm_fb_helper *fb_helper = info->par;
66
67 pm_runtime_mark_last_busy(fb_helper->dev->dev);
68 pm_runtime_put_autosuspend(fb_helper->dev->dev);
69 return 0;
70}
71
72static const struct fb_ops amdgpufb_ops = {
73 .owner = THIS_MODULE,
74 DRM_FB_HELPER_DEFAULT_OPS,
75 .fb_open = amdgpufb_open,
76 .fb_release = amdgpufb_release,
77 .fb_fillrect = drm_fb_helper_cfb_fillrect,
78 .fb_copyarea = drm_fb_helper_cfb_copyarea,
79 .fb_imageblit = drm_fb_helper_cfb_imageblit,
80};
81
82
83int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
84{
85 int aligned = width;
86 int pitch_mask = 0;
87
88 switch (cpp) {
89 case 1:
90 pitch_mask = 255;
91 break;
92 case 2:
93 pitch_mask = 127;
94 break;
95 case 3:
96 case 4:
97 pitch_mask = 63;
98 break;
99 }
100
101 aligned += pitch_mask;
102 aligned &= ~pitch_mask;
103 return aligned * cpp;
104}
105
106static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
107{
108 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
109 int ret;
110
111 ret = amdgpu_bo_reserve(abo, true);
112 if (likely(ret == 0)) {
113 amdgpu_bo_kunmap(abo);
114 amdgpu_bo_unpin(abo);
115 amdgpu_bo_unreserve(abo);
116 }
117 drm_gem_object_put(gobj);
118}
119
120static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
121 struct drm_mode_fb_cmd2 *mode_cmd,
122 struct drm_gem_object **gobj_p)
123{
124 const struct drm_format_info *info;
125 struct amdgpu_device *adev = rfbdev->adev;
126 struct drm_gem_object *gobj = NULL;
127 struct amdgpu_bo *abo = NULL;
128 bool fb_tiled = false; /* useful for testing */
129 u32 tiling_flags = 0, domain;
130 int ret;
131 int aligned_size, size;
132 int height = mode_cmd->height;
133 u32 cpp;
134 u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
135 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
136 AMDGPU_GEM_CREATE_VRAM_CLEARED;
137
138 info = drm_get_format_info(adev_to_drm(adev), mode_cmd);
139 cpp = info->cpp[0];
140
141 /* need to align pitch with crtc limits */
142 mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
143 fb_tiled);
144 domain = amdgpu_display_supported_domains(adev, flags);
145 height = ALIGN(mode_cmd->height, 8);
146 size = mode_cmd->pitches[0] * height;
147 aligned_size = ALIGN(size, PAGE_SIZE);
148 ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags,
149 ttm_bo_type_device, NULL, &gobj);
150 if (ret) {
151 pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
152 return -ENOMEM;
153 }
154 abo = gem_to_amdgpu_bo(gobj);
155
156 if (fb_tiled)
157 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
158
159 ret = amdgpu_bo_reserve(abo, false);
160 if (unlikely(ret != 0))
161 goto out_unref;
162
163 if (tiling_flags) {
164 ret = amdgpu_bo_set_tiling_flags(abo,
165 tiling_flags);
166 if (ret)
167 dev_err(adev->dev, "FB failed to set tiling flags\n");
168 }
169
170 ret = amdgpu_bo_pin(abo, domain);
171 if (ret) {
172 amdgpu_bo_unreserve(abo);
173 goto out_unref;
174 }
175
176 ret = amdgpu_ttm_alloc_gart(&abo->tbo);
177 if (ret) {
178 amdgpu_bo_unreserve(abo);
179 dev_err(adev->dev, "%p bind failed\n", abo);
180 goto out_unref;
181 }
182
183 ret = amdgpu_bo_kmap(abo, NULL);
184 amdgpu_bo_unreserve(abo);
185 if (ret) {
186 goto out_unref;
187 }
188
189 *gobj_p = gobj;
190 return 0;
191out_unref:
192 amdgpufb_destroy_pinned_object(gobj);
193 *gobj_p = NULL;
194 return ret;
195}
196
197static int amdgpufb_create(struct drm_fb_helper *helper,
198 struct drm_fb_helper_surface_size *sizes)
199{
200 struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
201 struct amdgpu_device *adev = rfbdev->adev;
202 struct fb_info *info;
203 struct drm_framebuffer *fb = NULL;
204 struct drm_mode_fb_cmd2 mode_cmd;
205 struct drm_gem_object *gobj = NULL;
206 struct amdgpu_bo *abo = NULL;
207 int ret;
208
209 memset(&mode_cmd, 0, sizeof(mode_cmd));
210 mode_cmd.width = sizes->surface_width;
211 mode_cmd.height = sizes->surface_height;
212
213 if (sizes->surface_bpp == 24)
214 sizes->surface_bpp = 32;
215
216 mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
217 sizes->surface_depth);
218
219 ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
220 if (ret) {
221 DRM_ERROR("failed to create fbcon object %d\n", ret);
222 return ret;
223 }
224
225 abo = gem_to_amdgpu_bo(gobj);
226
227 /* okay we have an object now allocate the framebuffer */
228 info = drm_fb_helper_alloc_fbi(helper);
229 if (IS_ERR(info)) {
230 ret = PTR_ERR(info);
231 goto out;
232 }
233
234 ret = amdgpu_display_gem_fb_init(adev_to_drm(adev), &rfbdev->rfb,
235 &mode_cmd, gobj);
236 if (ret) {
237 DRM_ERROR("failed to initialize framebuffer %d\n", ret);
238 goto out;
239 }
240
241 fb = &rfbdev->rfb.base;
242
243 /* setup helper */
244 rfbdev->helper.fb = fb;
245
246 info->fbops = &amdgpufb_ops;
247
248 info->fix.smem_start = amdgpu_gmc_vram_cpu_pa(adev, abo);
249 info->fix.smem_len = amdgpu_bo_size(abo);
250 info->screen_base = amdgpu_bo_kptr(abo);
251 info->screen_size = amdgpu_bo_size(abo);
252
253 drm_fb_helper_fill_info(info, &rfbdev->helper, sizes);
254
255 /* setup aperture base/size for vesafb takeover */
256 info->apertures->ranges[0].base = adev_to_drm(adev)->mode_config.fb_base;
257 info->apertures->ranges[0].size = adev->gmc.aper_size;
258
259 /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
260
261 if (info->screen_base == NULL) {
262 ret = -ENOSPC;
263 goto out;
264 }
265
266 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
267 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base);
268 DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
269 DRM_INFO("fb depth is %d\n", fb->format->depth);
270 DRM_INFO(" pitch is %d\n", fb->pitches[0]);
271
272 vga_switcheroo_client_fb_set(adev->pdev, info);
273 return 0;
274
275out:
276 if (abo) {
277
278 }
279 if (fb && ret) {
280 drm_gem_object_put(gobj);
281 drm_framebuffer_unregister_private(fb);
282 drm_framebuffer_cleanup(fb);
283 kfree(fb);
284 }
285 return ret;
286}
287
288static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
289{
290 struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
291 int i;
292
293 drm_fb_helper_unregister_fbi(&rfbdev->helper);
294
295 if (rfb->base.obj[0]) {
296 for (i = 0; i < rfb->base.format->num_planes; i++)
297 drm_gem_object_put(rfb->base.obj[0]);
298 amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
299 rfb->base.obj[0] = NULL;
300 drm_framebuffer_unregister_private(&rfb->base);
301 drm_framebuffer_cleanup(&rfb->base);
302 }
303 drm_fb_helper_fini(&rfbdev->helper);
304
305 return 0;
306}
307
308static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
309 .fb_probe = amdgpufb_create,
310};
311
312int amdgpu_fbdev_init(struct amdgpu_device *adev)
313{
314 struct amdgpu_fbdev *rfbdev;
315 int bpp_sel = 32;
316 int ret;
317
318 /* don't init fbdev on hw without DCE */
319 if (!adev->mode_info.mode_config_initialized)
320 return 0;
321
322 /* don't init fbdev if there are no connectors */
323 if (list_empty(&adev_to_drm(adev)->mode_config.connector_list))
324 return 0;
325
326 /* select 8 bpp console on low vram cards */
327 if (adev->gmc.real_vram_size <= (32*1024*1024))
328 bpp_sel = 8;
329
330 rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
331 if (!rfbdev)
332 return -ENOMEM;
333
334 rfbdev->adev = adev;
335 adev->mode_info.rfbdev = rfbdev;
336
337 drm_fb_helper_prepare(adev_to_drm(adev), &rfbdev->helper,
338 &amdgpu_fb_helper_funcs);
339
340 ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper);
341 if (ret) {
342 kfree(rfbdev);
343 return ret;
344 }
345
346 /* disable all the possible outputs/crtcs before entering KMS mode */
347 if (!amdgpu_device_has_dc_support(adev))
348 drm_helper_disable_unused_functions(adev_to_drm(adev));
349
350 drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
351 return 0;
352}
353
354void amdgpu_fbdev_fini(struct amdgpu_device *adev)
355{
356 if (!adev->mode_info.rfbdev)
357 return;
358
359 amdgpu_fbdev_destroy(adev_to_drm(adev), adev->mode_info.rfbdev);
360 kfree(adev->mode_info.rfbdev);
361 adev->mode_info.rfbdev = NULL;
362}
363
364void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
365{
366 if (adev->mode_info.rfbdev)
367 drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper,
368 state);
369}
370
371int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
372{
373 struct amdgpu_bo *robj;
374 int size = 0;
375
376 if (!adev->mode_info.rfbdev)
377 return 0;
378
379 robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]);
380 size += amdgpu_bo_size(robj);
381 return size;
382}
383
384bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
385{
386 if (!adev->mode_info.rfbdev)
387 return false;
388 if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]))
389 return true;
390 return false;
391}