1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2/* Copyright (c) 2018-2019 SiFive, Inc */
  3
  4#include "fu540-c000.dtsi"
  5#include <dt-bindings/gpio/gpio.h>
  6#include <dt-bindings/leds/common.h>
  7#include <dt-bindings/pwm/pwm.h>
  8
  9/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
 10#define RTCCLK_FREQ		1000000
 11
 12/ {
 
 
 13	model = "SiFive HiFive Unleashed A00";
 14	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
 15		     "sifive,fu540";
 16
 17	chosen {
 18		stdout-path = "serial0";
 19	};
 20
 21	cpus {
 22		timebase-frequency = <RTCCLK_FREQ>;
 23	};
 24
 25	memory@80000000 {
 26		device_type = "memory";
 27		reg = <0x0 0x80000000 0x2 0x00000000>;
 28	};
 29
 
 
 
 30	hfclk: hfclk {
 31		#clock-cells = <0>;
 32		compatible = "fixed-clock";
 33		clock-frequency = <33333333>;
 34		clock-output-names = "hfclk";
 35	};
 36
 37	rtcclk: rtcclk {
 38		#clock-cells = <0>;
 39		compatible = "fixed-clock";
 40		clock-frequency = <RTCCLK_FREQ>;
 41		clock-output-names = "rtcclk";
 42	};
 43	gpio-restart {
 44		compatible = "gpio-restart";
 45		gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 46	};
 47
 48	led-controller {
 49		compatible = "pwm-leds";
 50
 51		led-d1 {
 52			pwms = <&pwm0 0 7812500 PWM_POLARITY_INVERTED>;
 53			active-low;
 54			color = <LED_COLOR_ID_GREEN>;
 55			max-brightness = <255>;
 56			label = "d1";
 57		};
 58
 59		led-d2 {
 60			pwms = <&pwm0 1 7812500 PWM_POLARITY_INVERTED>;
 61			active-low;
 62			color = <LED_COLOR_ID_GREEN>;
 63			max-brightness = <255>;
 64			label = "d2";
 65		};
 66
 67		led-d3 {
 68			pwms = <&pwm0 2 7812500 PWM_POLARITY_INVERTED>;
 69			active-low;
 70			color = <LED_COLOR_ID_GREEN>;
 71			max-brightness = <255>;
 72			label = "d3";
 73		};
 74
 75		led-d4 {
 76			pwms = <&pwm0 3 7812500 PWM_POLARITY_INVERTED>;
 77			active-low;
 78			color = <LED_COLOR_ID_GREEN>;
 79			max-brightness = <255>;
 80			label = "d4";
 81		};
 82	};
 83};
 84
 85&uart0 {
 86	status = "okay";
 87};
 88
 89&uart1 {
 90	status = "okay";
 91};
 92
 93&i2c0 {
 94	status = "okay";
 95};
 96
 97&qspi0 {
 98	status = "okay";
 99	flash@0 {
100		compatible = "jedec,spi-nor";
101		reg = <0>;
102		spi-max-frequency = <50000000>;
103		m25p,fast-read;
104		spi-tx-bus-width = <4>;
105		spi-rx-bus-width = <4>;
106	};
107};
108
109&qspi2 {
110	status = "okay";
111	mmc@0 {
112		compatible = "mmc-spi-slot";
113		reg = <0>;
114		spi-max-frequency = <20000000>;
115		voltage-ranges = <3300 3300>;
116		disable-wp;
117		gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
118	};
119};
120
121&eth0 {
122	status = "okay";
123	phy-mode = "gmii";
124	phy-handle = <&phy0>;
125	phy0: ethernet-phy@0 {
126		compatible = "ethernet-phy-id0007.0771";
127		reg = <0>;
128	};
129};
130
131&pwm0 {
132	status = "okay";
133};
134
135&pwm1 {
136	status = "okay";
137};
138
139&gpio {
140	status = "okay";
141};

  1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2/* Copyright (c) 2018-2019 SiFive, Inc */
  3
  4#include "fu540-c000.dtsi"
  5#include <dt-bindings/gpio/gpio.h>
 
 
  6
  7/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
  8#define RTCCLK_FREQ		1000000
  9
 10/ {
 11	#address-cells = <2>;
 12	#size-cells = <2>;
 13	model = "SiFive HiFive Unleashed A00";
 14	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
 
 15
 16	chosen {
 17		stdout-path = "serial0";
 18	};
 19
 20	cpus {
 21		timebase-frequency = <RTCCLK_FREQ>;
 22	};
 23
 24	memory@80000000 {
 25		device_type = "memory";
 26		reg = <0x0 0x80000000 0x2 0x00000000>;
 27	};
 28
 29	soc {
 30	};
 31
 32	hfclk: hfclk {
 33		#clock-cells = <0>;
 34		compatible = "fixed-clock";
 35		clock-frequency = <33333333>;
 36		clock-output-names = "hfclk";
 37	};
 38
 39	rtcclk: rtcclk {
 40		#clock-cells = <0>;
 41		compatible = "fixed-clock";
 42		clock-frequency = <RTCCLK_FREQ>;
 43		clock-output-names = "rtcclk";
 44	};
 45	gpio-restart {
 46		compatible = "gpio-restart";
 47		gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
 48	};
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 49};
 50
 51&uart0 {
 52	status = "okay";
 53};
 54
 55&uart1 {
 56	status = "okay";
 57};
 58
 59&i2c0 {
 60	status = "okay";
 61};
 62
 63&qspi0 {
 64	status = "okay";
 65	flash@0 {
 66		compatible = "issi,is25wp256", "jedec,spi-nor";
 67		reg = <0>;
 68		spi-max-frequency = <50000000>;
 69		m25p,fast-read;
 70		spi-tx-bus-width = <4>;
 71		spi-rx-bus-width = <4>;
 72	};
 73};
 74
 75&qspi2 {
 76	status = "okay";
 77	mmc@0 {
 78		compatible = "mmc-spi-slot";
 79		reg = <0>;
 80		spi-max-frequency = <20000000>;
 81		voltage-ranges = <3300 3300>;
 82		disable-wp;
 
 83	};
 84};
 85
 86&eth0 {
 87	status = "okay";
 88	phy-mode = "gmii";
 89	phy-handle = <&phy0>;
 90	phy0: ethernet-phy@0 {
 91		compatible = "ethernet-phy-id0007.0771";
 92		reg = <0>;
 93	};
 94};
 95
 96&pwm0 {
 97	status = "okay";
 98};
 99
100&pwm1 {
101	status = "okay";
102};
103
104&gpio {
105	status = "okay";
106};