Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2011 John Crispin <john@phrozen.org>
5 */
6
7#include <linux/init.h>
8#include <linux/platform_device.h>
9#include <linux/io.h>
10#include <linux/dma-mapping.h>
11#include <linux/export.h>
12#include <linux/spinlock.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/of.h>
17
18#include <lantiq_soc.h>
19#include <xway_dma.h>
20
21#define LTQ_DMA_ID 0x08
22#define LTQ_DMA_CTRL 0x10
23#define LTQ_DMA_CPOLL 0x14
24#define LTQ_DMA_CS 0x18
25#define LTQ_DMA_CCTRL 0x1C
26#define LTQ_DMA_CDBA 0x20
27#define LTQ_DMA_CDLEN 0x24
28#define LTQ_DMA_CIS 0x28
29#define LTQ_DMA_CIE 0x2C
30#define LTQ_DMA_PS 0x40
31#define LTQ_DMA_PCTRL 0x44
32#define LTQ_DMA_IRNEN 0xf4
33
34#define DMA_ID_CHNR GENMASK(26, 20) /* channel number */
35#define DMA_DESCPT BIT(3) /* descriptor complete irq */
36#define DMA_TX BIT(8) /* TX channel direction */
37#define DMA_CHAN_ON BIT(0) /* channel on / off bit */
38#define DMA_PDEN BIT(6) /* enable packet drop */
39#define DMA_CHAN_RST BIT(1) /* channel on / off bit */
40#define DMA_RESET BIT(0) /* channel on / off bit */
41#define DMA_IRQ_ACK 0x7e /* IRQ status register */
42#define DMA_POLL BIT(31) /* turn on channel polling */
43#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
44#define DMA_PCTRL_2W_BURST 0x1 /* 2 word burst length */
45#define DMA_PCTRL_4W_BURST 0x2 /* 4 word burst length */
46#define DMA_PCTRL_8W_BURST 0x3 /* 8 word burst length */
47#define DMA_TX_BURST_SHIFT 4 /* tx burst shift */
48#define DMA_RX_BURST_SHIFT 2 /* rx burst shift */
49#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
50#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
51
52#define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x))
53#define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y))
54#define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
55 ltq_dma_membase + (z))
56
57static void __iomem *ltq_dma_membase;
58static DEFINE_SPINLOCK(ltq_dma_lock);
59
60void
61ltq_dma_enable_irq(struct ltq_dma_channel *ch)
62{
63 unsigned long flags;
64
65 spin_lock_irqsave(<q_dma_lock, flags);
66 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
67 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
68 spin_unlock_irqrestore(<q_dma_lock, flags);
69}
70EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
71
72void
73ltq_dma_disable_irq(struct ltq_dma_channel *ch)
74{
75 unsigned long flags;
76
77 spin_lock_irqsave(<q_dma_lock, flags);
78 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
79 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
80 spin_unlock_irqrestore(<q_dma_lock, flags);
81}
82EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
83
84void
85ltq_dma_ack_irq(struct ltq_dma_channel *ch)
86{
87 unsigned long flags;
88
89 spin_lock_irqsave(<q_dma_lock, flags);
90 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
91 ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
92 spin_unlock_irqrestore(<q_dma_lock, flags);
93}
94EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
95
96void
97ltq_dma_open(struct ltq_dma_channel *ch)
98{
99 unsigned long flag;
100
101 spin_lock_irqsave(<q_dma_lock, flag);
102 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
103 ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
104 spin_unlock_irqrestore(<q_dma_lock, flag);
105}
106EXPORT_SYMBOL_GPL(ltq_dma_open);
107
108void
109ltq_dma_close(struct ltq_dma_channel *ch)
110{
111 unsigned long flag;
112
113 spin_lock_irqsave(<q_dma_lock, flag);
114 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
115 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
116 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
117 spin_unlock_irqrestore(<q_dma_lock, flag);
118}
119EXPORT_SYMBOL_GPL(ltq_dma_close);
120
121static void
122ltq_dma_alloc(struct ltq_dma_channel *ch)
123{
124 unsigned long flags;
125
126 ch->desc = 0;
127 ch->desc_base = dma_alloc_coherent(ch->dev,
128 LTQ_DESC_NUM * LTQ_DESC_SIZE,
129 &ch->phys, GFP_ATOMIC);
130
131 spin_lock_irqsave(<q_dma_lock, flags);
132 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
133 ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
134 ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
135 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
136 wmb();
137 ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
138 while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
139 ;
140 spin_unlock_irqrestore(<q_dma_lock, flags);
141}
142
143void
144ltq_dma_alloc_tx(struct ltq_dma_channel *ch)
145{
146 unsigned long flags;
147
148 ltq_dma_alloc(ch);
149
150 spin_lock_irqsave(<q_dma_lock, flags);
151 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
152 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
153 ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
154 spin_unlock_irqrestore(<q_dma_lock, flags);
155}
156EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
157
158void
159ltq_dma_alloc_rx(struct ltq_dma_channel *ch)
160{
161 unsigned long flags;
162
163 ltq_dma_alloc(ch);
164
165 spin_lock_irqsave(<q_dma_lock, flags);
166 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
167 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
168 ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
169 spin_unlock_irqrestore(<q_dma_lock, flags);
170}
171EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);
172
173void
174ltq_dma_free(struct ltq_dma_channel *ch)
175{
176 if (!ch->desc_base)
177 return;
178 ltq_dma_close(ch);
179 dma_free_coherent(ch->dev, LTQ_DESC_NUM * LTQ_DESC_SIZE,
180 ch->desc_base, ch->phys);
181}
182EXPORT_SYMBOL_GPL(ltq_dma_free);
183
184void
185ltq_dma_init_port(int p, int tx_burst, int rx_burst)
186{
187 ltq_dma_w32(p, LTQ_DMA_PS);
188 switch (p) {
189 case DMA_PORT_ETOP:
190 /*
191 * Tell the DMA engine to swap the endianness of data frames and
192 * drop packets if the channel arbitration fails.
193 */
194 ltq_dma_w32_mask(0, (DMA_ETOP_ENDIANNESS | DMA_PDEN),
195 LTQ_DMA_PCTRL);
196 break;
197
198 default:
199 break;
200 }
201
202 switch (rx_burst) {
203 case 8:
204 ltq_dma_w32_mask(0x0c, (DMA_PCTRL_8W_BURST << DMA_RX_BURST_SHIFT),
205 LTQ_DMA_PCTRL);
206 break;
207 case 4:
208 ltq_dma_w32_mask(0x0c, (DMA_PCTRL_4W_BURST << DMA_RX_BURST_SHIFT),
209 LTQ_DMA_PCTRL);
210 break;
211 case 2:
212 ltq_dma_w32_mask(0x0c, (DMA_PCTRL_2W_BURST << DMA_RX_BURST_SHIFT),
213 LTQ_DMA_PCTRL);
214 break;
215 default:
216 break;
217 }
218
219 switch (tx_burst) {
220 case 8:
221 ltq_dma_w32_mask(0x30, (DMA_PCTRL_8W_BURST << DMA_TX_BURST_SHIFT),
222 LTQ_DMA_PCTRL);
223 break;
224 case 4:
225 ltq_dma_w32_mask(0x30, (DMA_PCTRL_4W_BURST << DMA_TX_BURST_SHIFT),
226 LTQ_DMA_PCTRL);
227 break;
228 case 2:
229 ltq_dma_w32_mask(0x30, (DMA_PCTRL_2W_BURST << DMA_TX_BURST_SHIFT),
230 LTQ_DMA_PCTRL);
231 break;
232 default:
233 break;
234 }
235}
236EXPORT_SYMBOL_GPL(ltq_dma_init_port);
237
238static int
239ltq_dma_init(struct platform_device *pdev)
240{
241 struct clk *clk;
242 unsigned int id, nchannels;
243 int i;
244
245 ltq_dma_membase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
246 if (IS_ERR(ltq_dma_membase))
247 panic("Failed to remap dma resource");
248
249 /* power up and reset the dma engine */
250 clk = clk_get(&pdev->dev, NULL);
251 if (IS_ERR(clk))
252 panic("Failed to get dma clock");
253
254 clk_enable(clk);
255 ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
256
257 usleep_range(1, 10);
258
259 /* disable all interrupts */
260 ltq_dma_w32(0, LTQ_DMA_IRNEN);
261
262 /* reset/configure each channel */
263 id = ltq_dma_r32(LTQ_DMA_ID);
264 nchannels = ((id & DMA_ID_CHNR) >> 20);
265 for (i = 0; i < nchannels; i++) {
266 ltq_dma_w32(i, LTQ_DMA_CS);
267 ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
268 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
269 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
270 }
271
272 dev_info(&pdev->dev,
273 "Init done - hw rev: %X, ports: %d, channels: %d\n",
274 id & 0x1f, (id >> 16) & 0xf, nchannels);
275
276 return 0;
277}
278
279static const struct of_device_id dma_match[] = {
280 { .compatible = "lantiq,dma-xway" },
281 {},
282};
283
284static struct platform_driver dma_driver = {
285 .probe = ltq_dma_init,
286 .driver = {
287 .name = "dma-xway",
288 .of_match_table = dma_match,
289 },
290};
291
292int __init
293dma_init(void)
294{
295 return platform_driver_register(&dma_driver);
296}
297
298postcore_initcall(dma_init);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2011 John Crispin <john@phrozen.org>
5 */
6
7#include <linux/init.h>
8#include <linux/platform_device.h>
9#include <linux/io.h>
10#include <linux/dma-mapping.h>
11#include <linux/export.h>
12#include <linux/spinlock.h>
13#include <linux/clk.h>
14#include <linux/err.h>
15#include <linux/of.h>
16
17#include <lantiq_soc.h>
18#include <xway_dma.h>
19
20#define LTQ_DMA_ID 0x08
21#define LTQ_DMA_CTRL 0x10
22#define LTQ_DMA_CPOLL 0x14
23#define LTQ_DMA_CS 0x18
24#define LTQ_DMA_CCTRL 0x1C
25#define LTQ_DMA_CDBA 0x20
26#define LTQ_DMA_CDLEN 0x24
27#define LTQ_DMA_CIS 0x28
28#define LTQ_DMA_CIE 0x2C
29#define LTQ_DMA_PS 0x40
30#define LTQ_DMA_PCTRL 0x44
31#define LTQ_DMA_IRNEN 0xf4
32
33#define DMA_DESCPT BIT(3) /* descriptor complete irq */
34#define DMA_TX BIT(8) /* TX channel direction */
35#define DMA_CHAN_ON BIT(0) /* channel on / off bit */
36#define DMA_PDEN BIT(6) /* enable packet drop */
37#define DMA_CHAN_RST BIT(1) /* channel on / off bit */
38#define DMA_RESET BIT(0) /* channel on / off bit */
39#define DMA_IRQ_ACK 0x7e /* IRQ status register */
40#define DMA_POLL BIT(31) /* turn on channel polling */
41#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
42#define DMA_2W_BURST BIT(1) /* 2 word burst length */
43#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */
44#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */
45#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
46
47#define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x))
48#define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y))
49#define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
50 ltq_dma_membase + (z))
51
52static void __iomem *ltq_dma_membase;
53static DEFINE_SPINLOCK(ltq_dma_lock);
54
55void
56ltq_dma_enable_irq(struct ltq_dma_channel *ch)
57{
58 unsigned long flags;
59
60 spin_lock_irqsave(<q_dma_lock, flags);
61 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
62 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
63 spin_unlock_irqrestore(<q_dma_lock, flags);
64}
65EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
66
67void
68ltq_dma_disable_irq(struct ltq_dma_channel *ch)
69{
70 unsigned long flags;
71
72 spin_lock_irqsave(<q_dma_lock, flags);
73 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
74 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
75 spin_unlock_irqrestore(<q_dma_lock, flags);
76}
77EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
78
79void
80ltq_dma_ack_irq(struct ltq_dma_channel *ch)
81{
82 unsigned long flags;
83
84 spin_lock_irqsave(<q_dma_lock, flags);
85 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
86 ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
87 spin_unlock_irqrestore(<q_dma_lock, flags);
88}
89EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
90
91void
92ltq_dma_open(struct ltq_dma_channel *ch)
93{
94 unsigned long flag;
95
96 spin_lock_irqsave(<q_dma_lock, flag);
97 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
98 ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
99 spin_unlock_irqrestore(<q_dma_lock, flag);
100}
101EXPORT_SYMBOL_GPL(ltq_dma_open);
102
103void
104ltq_dma_close(struct ltq_dma_channel *ch)
105{
106 unsigned long flag;
107
108 spin_lock_irqsave(<q_dma_lock, flag);
109 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
110 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
111 ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
112 spin_unlock_irqrestore(<q_dma_lock, flag);
113}
114EXPORT_SYMBOL_GPL(ltq_dma_close);
115
116static void
117ltq_dma_alloc(struct ltq_dma_channel *ch)
118{
119 unsigned long flags;
120
121 ch->desc = 0;
122 ch->desc_base = dma_alloc_coherent(ch->dev,
123 LTQ_DESC_NUM * LTQ_DESC_SIZE,
124 &ch->phys, GFP_ATOMIC);
125
126 spin_lock_irqsave(<q_dma_lock, flags);
127 ltq_dma_w32(ch->nr, LTQ_DMA_CS);
128 ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
129 ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
130 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
131 wmb();
132 ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
133 while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
134 ;
135 spin_unlock_irqrestore(<q_dma_lock, flags);
136}
137
138void
139ltq_dma_alloc_tx(struct ltq_dma_channel *ch)
140{
141 unsigned long flags;
142
143 ltq_dma_alloc(ch);
144
145 spin_lock_irqsave(<q_dma_lock, flags);
146 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
147 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
148 ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
149 spin_unlock_irqrestore(<q_dma_lock, flags);
150}
151EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
152
153void
154ltq_dma_alloc_rx(struct ltq_dma_channel *ch)
155{
156 unsigned long flags;
157
158 ltq_dma_alloc(ch);
159
160 spin_lock_irqsave(<q_dma_lock, flags);
161 ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
162 ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
163 ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
164 spin_unlock_irqrestore(<q_dma_lock, flags);
165}
166EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);
167
168void
169ltq_dma_free(struct ltq_dma_channel *ch)
170{
171 if (!ch->desc_base)
172 return;
173 ltq_dma_close(ch);
174 dma_free_coherent(ch->dev, LTQ_DESC_NUM * LTQ_DESC_SIZE,
175 ch->desc_base, ch->phys);
176}
177EXPORT_SYMBOL_GPL(ltq_dma_free);
178
179void
180ltq_dma_init_port(int p)
181{
182 ltq_dma_w32(p, LTQ_DMA_PS);
183 switch (p) {
184 case DMA_PORT_ETOP:
185 /*
186 * Tell the DMA engine to swap the endianness of data frames and
187 * drop packets if the channel arbitration fails.
188 */
189 ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN,
190 LTQ_DMA_PCTRL);
191 break;
192
193 case DMA_PORT_DEU:
194 ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
195 LTQ_DMA_PCTRL);
196 break;
197
198 default:
199 break;
200 }
201}
202EXPORT_SYMBOL_GPL(ltq_dma_init_port);
203
204static int
205ltq_dma_init(struct platform_device *pdev)
206{
207 struct clk *clk;
208 struct resource *res;
209 unsigned id;
210 int i;
211
212 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
213 ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res);
214 if (IS_ERR(ltq_dma_membase))
215 panic("Failed to remap dma resource");
216
217 /* power up and reset the dma engine */
218 clk = clk_get(&pdev->dev, NULL);
219 if (IS_ERR(clk))
220 panic("Failed to get dma clock");
221
222 clk_enable(clk);
223 ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
224
225 /* disable all interrupts */
226 ltq_dma_w32(0, LTQ_DMA_IRNEN);
227
228 /* reset/configure each channel */
229 for (i = 0; i < DMA_MAX_CHANNEL; i++) {
230 ltq_dma_w32(i, LTQ_DMA_CS);
231 ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
232 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
233 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
234 }
235
236 id = ltq_dma_r32(LTQ_DMA_ID);
237 dev_info(&pdev->dev,
238 "Init done - hw rev: %X, ports: %d, channels: %d\n",
239 id & 0x1f, (id >> 16) & 0xf, id >> 20);
240
241 return 0;
242}
243
244static const struct of_device_id dma_match[] = {
245 { .compatible = "lantiq,dma-xway" },
246 {},
247};
248
249static struct platform_driver dma_driver = {
250 .probe = ltq_dma_init,
251 .driver = {
252 .name = "dma-xway",
253 .of_match_table = dma_match,
254 },
255};
256
257int __init
258dma_init(void)
259{
260 return platform_driver_register(&dma_driver);
261}
262
263postcore_initcall(dma_init);