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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
5 * Copyright (C) 2006 Atmark Techno, Inc.
6 */
7
8#ifndef _ASM_MICROBLAZE_PGTABLE_H
9#define _ASM_MICROBLAZE_PGTABLE_H
10
11#include <asm/setup.h>
12
13#ifndef __ASSEMBLY__
14extern int mem_init_done;
15#endif
16
17#include <asm-generic/pgtable-nopmd.h>
18
19#ifdef __KERNEL__
20#ifndef __ASSEMBLY__
21
22#include <linux/sched.h>
23#include <linux/threads.h>
24#include <asm/processor.h> /* For TASK_SIZE */
25#include <asm/mmu.h>
26#include <asm/page.h>
27
28extern unsigned long va_to_phys(unsigned long address);
29extern pte_t *va_to_pte(unsigned long address);
30
31/*
32 * The following only work if pte_present() is true.
33 * Undefined behaviour if not..
34 */
35
36/* Start and end of the vmalloc area. */
37/* Make sure to map the vmalloc area above the pinned kernel memory area
38 of 32Mb. */
39#define VMALLOC_START (CONFIG_KERNEL_START + CONFIG_LOWMEM_SIZE)
40#define VMALLOC_END ioremap_bot
41
42#endif /* __ASSEMBLY__ */
43
44/*
45 * Macro to mark a page protection value as "uncacheable".
46 */
47
48#define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \
49 _PAGE_WRITETHRU)
50
51#define pgprot_noncached(prot) \
52 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
53 _PAGE_NO_CACHE | _PAGE_GUARDED))
54
55#define pgprot_noncached_wc(prot) \
56 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
57 _PAGE_NO_CACHE))
58
59/*
60 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash
61 * table containing PTEs, together with a set of 16 segment registers, to
62 * define the virtual to physical address mapping.
63 *
64 * We use the hash table as an extended TLB, i.e. a cache of currently
65 * active mappings. We maintain a two-level page table tree, much
66 * like that used by the i386, for the sake of the Linux memory
67 * management code. Low-level assembler code in hashtable.S
68 * (procedure hash_page) is responsible for extracting ptes from the
69 * tree and putting them into the hash table when necessary, and
70 * updating the accessed and modified bits in the page table tree.
71 */
72
73/*
74 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
75 * instruction and data sides share a unified, 64-entry, semi-associative
76 * TLB which is maintained totally under software control. In addition, the
77 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
78 * TLB which serves as a first level to the shared TLB. These two TLBs are
79 * known as the UTLB and ITLB, respectively (see "mmu.h" for definitions).
80 */
81
82/*
83 * The normal case is that PTEs are 32-bits and we have a 1-page
84 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
85 *
86 */
87
88/* PGDIR_SHIFT determines what a top-level page table entry can map */
89#define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
90#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
91#define PGDIR_MASK (~(PGDIR_SIZE-1))
92
93/*
94 * entries per page directory level: our page-table tree is two-level, so
95 * we don't really have any PMD directory.
96 */
97#define PTRS_PER_PTE (1 << PTE_SHIFT)
98#define PTRS_PER_PMD 1
99#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
100
101#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
102#define FIRST_USER_PGD_NR 0
103
104#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
105#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
106
107#define pte_ERROR(e) \
108 printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \
109 __FILE__, __LINE__, pte_val(e))
110#define pgd_ERROR(e) \
111 printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
112 __FILE__, __LINE__, pgd_val(e))
113
114/*
115 * Bits in a linux-style PTE. These match the bits in the
116 * (hardware-defined) PTE as closely as possible.
117 */
118
119/* There are several potential gotchas here. The hardware TLBLO
120 * field looks like this:
121 *
122 * 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
123 * RPN..................... 0 0 EX WR ZSEL....... W I M G
124 *
125 * Where possible we make the Linux PTE bits match up with this
126 *
127 * - bits 20 and 21 must be cleared, because we use 4k pages (4xx can
128 * support down to 1k pages), this is done in the TLBMiss exception
129 * handler.
130 * - We use only zones 0 (for kernel pages) and 1 (for user pages)
131 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
132 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
133 * zone.
134 * - PRESENT *must* be in the bottom two bits because swap PTEs use the top
135 * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we
136 * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler
137 * before the TLB entry is loaded.
138 * - All other bits of the PTE are loaded into TLBLO without
139 * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
140 * software PTE bits. We actually use bits 21, 24, 25, and
141 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
142 * PRESENT.
143 */
144
145/* Definitions for MicroBlaze. */
146#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
147#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
148#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
149#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
150#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
151#define _PAGE_RW 0x040 /* software: Writes permitted */
152#define _PAGE_DIRTY 0x080 /* software: dirty page */
153#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
154#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
155#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
156#define _PMD_PRESENT PAGE_MASK
157
158/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
159#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY
160
161/*
162 * Some bits are unused...
163 */
164#ifndef _PAGE_HASHPTE
165#define _PAGE_HASHPTE 0
166#endif
167#ifndef _PTE_NONE_MASK
168#define _PTE_NONE_MASK 0
169#endif
170#ifndef _PAGE_SHARED
171#define _PAGE_SHARED 0
172#endif
173#ifndef _PAGE_EXEC
174#define _PAGE_EXEC 0
175#endif
176
177#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
178
179/*
180 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
181 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
182 * to have it in the Linux PTE, and in fact the bit could be reused for
183 * another purpose. -- paulus.
184 */
185#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
186#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
187
188#define _PAGE_KERNEL \
189 (_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC)
190
191#define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
192
193#define PAGE_NONE __pgprot(_PAGE_BASE)
194#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
195#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
196#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
197#define PAGE_SHARED_X \
198 __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
199#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
200#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
201
202#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
203#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_SHARED)
204#define PAGE_KERNEL_CI __pgprot(_PAGE_IO)
205
206/*
207 * We consider execute permission the same as read.
208 * Also, write permissions imply read permissions.
209 */
210
211#ifndef __ASSEMBLY__
212/*
213 * ZERO_PAGE is a global shared page that is always zero: used
214 * for zero-mapped memory areas etc..
215 */
216extern unsigned long empty_zero_page[1024];
217#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
218
219#endif /* __ASSEMBLY__ */
220
221#define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
222#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
223#define pte_clear(mm, addr, ptep) \
224 do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
225
226#define pmd_none(pmd) (!pmd_val(pmd))
227#define pmd_bad(pmd) ((pmd_val(pmd) & _PMD_PRESENT) == 0)
228#define pmd_present(pmd) ((pmd_val(pmd) & _PMD_PRESENT) != 0)
229#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
230
231#define pte_page(x) (mem_map + (unsigned long) \
232 ((pte_val(x) - memory_start) >> PAGE_SHIFT))
233#define PFN_PTE_SHIFT PAGE_SHIFT
234
235#define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
236
237#define pfn_pte(pfn, prot) \
238 __pte(((pte_basic_t)(pfn) << PFN_PTE_SHIFT) | pgprot_val(prot))
239
240#ifndef __ASSEMBLY__
241/*
242 * The following only work if pte_present() is true.
243 * Undefined behaviour if not..
244 */
245static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
246static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
247static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
248static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
249static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
250
251static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
252static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
253
254static inline pte_t pte_rdprotect(pte_t pte) \
255 { pte_val(pte) &= ~_PAGE_USER; return pte; }
256static inline pte_t pte_wrprotect(pte_t pte) \
257 { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
258static inline pte_t pte_exprotect(pte_t pte) \
259 { pte_val(pte) &= ~_PAGE_EXEC; return pte; }
260static inline pte_t pte_mkclean(pte_t pte) \
261 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
262static inline pte_t pte_mkold(pte_t pte) \
263 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
264
265static inline pte_t pte_mkread(pte_t pte) \
266 { pte_val(pte) |= _PAGE_USER; return pte; }
267static inline pte_t pte_mkexec(pte_t pte) \
268 { pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
269static inline pte_t pte_mkwrite_novma(pte_t pte) \
270 { pte_val(pte) |= _PAGE_RW; return pte; }
271static inline pte_t pte_mkdirty(pte_t pte) \
272 { pte_val(pte) |= _PAGE_DIRTY; return pte; }
273static inline pte_t pte_mkyoung(pte_t pte) \
274 { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
275
276/*
277 * Conversion functions: convert a page and protection to a page entry,
278 * and a page entry and page directory to the page they refer to.
279 */
280
281static inline pte_t mk_pte_phys(phys_addr_t physpage, pgprot_t pgprot)
282{
283 pte_t pte;
284 pte_val(pte) = physpage | pgprot_val(pgprot);
285 return pte;
286}
287
288#define mk_pte(page, pgprot) \
289({ \
290 pte_t pte; \
291 pte_val(pte) = (((page - mem_map) << PAGE_SHIFT) + memory_start) | \
292 pgprot_val(pgprot); \
293 pte; \
294})
295
296static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
297{
298 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
299 return pte;
300}
301
302/*
303 * Atomic PTE updates.
304 *
305 * pte_update clears and sets bit atomically, and returns
306 * the old pte value.
307 * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant
308 * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits.
309 */
310static inline unsigned long pte_update(pte_t *p, unsigned long clr,
311 unsigned long set)
312{
313 unsigned long flags, old, tmp;
314
315 raw_local_irq_save(flags);
316
317 __asm__ __volatile__( "lw %0, %2, r0 \n"
318 "andn %1, %0, %3 \n"
319 "or %1, %1, %4 \n"
320 "sw %1, %2, r0 \n"
321 : "=&r" (old), "=&r" (tmp)
322 : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set)
323 : "cc");
324
325 raw_local_irq_restore(flags);
326
327 return old;
328}
329
330/*
331 * set_pte stores a linux PTE into the linux page table.
332 */
333static inline void set_pte(pte_t *ptep, pte_t pte)
334{
335 *ptep = pte;
336}
337
338#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
339struct vm_area_struct;
340static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
341 unsigned long address, pte_t *ptep)
342{
343 return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0;
344}
345
346static inline int ptep_test_and_clear_dirty(struct mm_struct *mm,
347 unsigned long addr, pte_t *ptep)
348{
349 return (pte_update(ptep, \
350 (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
351}
352
353#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
354static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
355 unsigned long addr, pte_t *ptep)
356{
357 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
358}
359
360/*static inline void ptep_set_wrprotect(struct mm_struct *mm,
361 unsigned long addr, pte_t *ptep)
362{
363 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
364}*/
365
366static inline void ptep_mkdirty(struct mm_struct *mm,
367 unsigned long addr, pte_t *ptep)
368{
369 pte_update(ptep, 0, _PAGE_DIRTY);
370}
371
372/*#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)*/
373
374/* Convert pmd entry to page */
375/* our pmd entry is an effective address of pte table*/
376/* returns effective address of the pmd entry*/
377static inline unsigned long pmd_page_vaddr(pmd_t pmd)
378{
379 return ((unsigned long) (pmd_val(pmd) & PAGE_MASK));
380}
381
382/* returns pfn of the pmd entry*/
383#define pmd_pfn(pmd) (__pa(pmd_val(pmd)) >> PAGE_SHIFT)
384
385/* returns struct *page of the pmd entry*/
386#define pmd_page(pmd) (pfn_to_page(__pa(pmd_val(pmd)) >> PAGE_SHIFT))
387
388/* Find an entry in the third-level page table.. */
389
390extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
391
392/*
393 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
394 * are !pte_none() && !pte_present().
395 *
396 * 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
397 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
398 * <------------------ offset -------------------> E < type -> 0 0
399 *
400 * E is the exclusive marker that is not stored in swap entries.
401 */
402#define __swp_type(entry) ((entry).val & 0x1f)
403#define __swp_offset(entry) ((entry).val >> 6)
404#define __swp_entry(type, offset) \
405 ((swp_entry_t) { ((type) & 0x1f) | ((offset) << 6) })
406#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 })
407#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 })
408
409static inline int pte_swp_exclusive(pte_t pte)
410{
411 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
412}
413
414static inline pte_t pte_swp_mkexclusive(pte_t pte)
415{
416 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
417 return pte;
418}
419
420static inline pte_t pte_swp_clear_exclusive(pte_t pte)
421{
422 pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
423 return pte;
424}
425
426extern unsigned long iopa(unsigned long addr);
427
428/* Values for nocacheflag and cmode */
429/* These are not used by the APUS kernel_map, but prevents
430 * compilation errors.
431 */
432#define IOMAP_FULL_CACHING 0
433#define IOMAP_NOCACHE_SER 1
434#define IOMAP_NOCACHE_NONSER 2
435#define IOMAP_NO_COPYBACK 3
436
437void do_page_fault(struct pt_regs *regs, unsigned long address,
438 unsigned long error_code);
439
440void mapin_ram(void);
441int map_page(unsigned long va, phys_addr_t pa, int flags);
442
443extern int mem_init_done;
444
445asmlinkage void __init mmu_init(void);
446
447#endif /* __ASSEMBLY__ */
448#endif /* __KERNEL__ */
449
450#ifndef __ASSEMBLY__
451extern unsigned long ioremap_bot, ioremap_base;
452
453void setup_memory(void);
454#endif /* __ASSEMBLY__ */
455
456#endif /* _ASM_MICROBLAZE_PGTABLE_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
5 * Copyright (C) 2006 Atmark Techno, Inc.
6 */
7
8#ifndef _ASM_MICROBLAZE_PGTABLE_H
9#define _ASM_MICROBLAZE_PGTABLE_H
10
11#include <asm/setup.h>
12
13#ifndef __ASSEMBLY__
14extern int mem_init_done;
15#endif
16
17#include <asm-generic/pgtable-nopmd.h>
18
19#ifdef __KERNEL__
20#ifndef __ASSEMBLY__
21
22#include <linux/sched.h>
23#include <linux/threads.h>
24#include <asm/processor.h> /* For TASK_SIZE */
25#include <asm/mmu.h>
26#include <asm/page.h>
27
28extern unsigned long va_to_phys(unsigned long address);
29extern pte_t *va_to_pte(unsigned long address);
30
31/*
32 * The following only work if pte_present() is true.
33 * Undefined behaviour if not..
34 */
35
36/* Start and end of the vmalloc area. */
37/* Make sure to map the vmalloc area above the pinned kernel memory area
38 of 32Mb. */
39#define VMALLOC_START (CONFIG_KERNEL_START + CONFIG_LOWMEM_SIZE)
40#define VMALLOC_END ioremap_bot
41
42#endif /* __ASSEMBLY__ */
43
44/*
45 * Macro to mark a page protection value as "uncacheable".
46 */
47
48#define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \
49 _PAGE_WRITETHRU)
50
51#define pgprot_noncached(prot) \
52 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
53 _PAGE_NO_CACHE | _PAGE_GUARDED))
54
55#define pgprot_noncached_wc(prot) \
56 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
57 _PAGE_NO_CACHE))
58
59/*
60 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash
61 * table containing PTEs, together with a set of 16 segment registers, to
62 * define the virtual to physical address mapping.
63 *
64 * We use the hash table as an extended TLB, i.e. a cache of currently
65 * active mappings. We maintain a two-level page table tree, much
66 * like that used by the i386, for the sake of the Linux memory
67 * management code. Low-level assembler code in hashtable.S
68 * (procedure hash_page) is responsible for extracting ptes from the
69 * tree and putting them into the hash table when necessary, and
70 * updating the accessed and modified bits in the page table tree.
71 */
72
73/*
74 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
75 * instruction and data sides share a unified, 64-entry, semi-associative
76 * TLB which is maintained totally under software control. In addition, the
77 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
78 * TLB which serves as a first level to the shared TLB. These two TLBs are
79 * known as the UTLB and ITLB, respectively (see "mmu.h" for definitions).
80 */
81
82/*
83 * The normal case is that PTEs are 32-bits and we have a 1-page
84 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
85 *
86 */
87
88/* PGDIR_SHIFT determines what a top-level page table entry can map */
89#define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
90#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
91#define PGDIR_MASK (~(PGDIR_SIZE-1))
92
93/*
94 * entries per page directory level: our page-table tree is two-level, so
95 * we don't really have any PMD directory.
96 */
97#define PTRS_PER_PTE (1 << PTE_SHIFT)
98#define PTRS_PER_PMD 1
99#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
100
101#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
102#define FIRST_USER_PGD_NR 0
103
104#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
105#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
106
107#define pte_ERROR(e) \
108 printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \
109 __FILE__, __LINE__, pte_val(e))
110#define pgd_ERROR(e) \
111 printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
112 __FILE__, __LINE__, pgd_val(e))
113
114/*
115 * Bits in a linux-style PTE. These match the bits in the
116 * (hardware-defined) PTE as closely as possible.
117 */
118
119/* There are several potential gotchas here. The hardware TLBLO
120 * field looks like this:
121 *
122 * 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
123 * RPN..................... 0 0 EX WR ZSEL....... W I M G
124 *
125 * Where possible we make the Linux PTE bits match up with this
126 *
127 * - bits 20 and 21 must be cleared, because we use 4k pages (4xx can
128 * support down to 1k pages), this is done in the TLBMiss exception
129 * handler.
130 * - We use only zones 0 (for kernel pages) and 1 (for user pages)
131 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
132 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
133 * zone.
134 * - PRESENT *must* be in the bottom two bits because swap cache
135 * entries use the top 30 bits. Because 4xx doesn't support SMP
136 * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
137 * is cleared in the TLB miss handler before the TLB entry is loaded.
138 * - All other bits of the PTE are loaded into TLBLO without
139 * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
140 * software PTE bits. We actually use bits 21, 24, 25, and
141 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
142 * PRESENT.
143 */
144
145/* Definitions for MicroBlaze. */
146#define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
147#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
148#define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
149#define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
150#define _PAGE_USER 0x010 /* matches one of the zone permission bits */
151#define _PAGE_RW 0x040 /* software: Writes permitted */
152#define _PAGE_DIRTY 0x080 /* software: dirty page */
153#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
154#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
155#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
156#define _PMD_PRESENT PAGE_MASK
157
158/*
159 * Some bits are unused...
160 */
161#ifndef _PAGE_HASHPTE
162#define _PAGE_HASHPTE 0
163#endif
164#ifndef _PTE_NONE_MASK
165#define _PTE_NONE_MASK 0
166#endif
167#ifndef _PAGE_SHARED
168#define _PAGE_SHARED 0
169#endif
170#ifndef _PAGE_EXEC
171#define _PAGE_EXEC 0
172#endif
173
174#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
175
176/*
177 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
178 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
179 * to have it in the Linux PTE, and in fact the bit could be reused for
180 * another purpose. -- paulus.
181 */
182#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
183#define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
184
185#define _PAGE_KERNEL \
186 (_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC)
187
188#define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
189
190#define PAGE_NONE __pgprot(_PAGE_BASE)
191#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
192#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
193#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
194#define PAGE_SHARED_X \
195 __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
196#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
197#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
198
199#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
200#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_SHARED)
201#define PAGE_KERNEL_CI __pgprot(_PAGE_IO)
202
203/*
204 * We consider execute permission the same as read.
205 * Also, write permissions imply read permissions.
206 */
207#define __P000 PAGE_NONE
208#define __P001 PAGE_READONLY_X
209#define __P010 PAGE_COPY
210#define __P011 PAGE_COPY_X
211#define __P100 PAGE_READONLY
212#define __P101 PAGE_READONLY_X
213#define __P110 PAGE_COPY
214#define __P111 PAGE_COPY_X
215
216#define __S000 PAGE_NONE
217#define __S001 PAGE_READONLY_X
218#define __S010 PAGE_SHARED
219#define __S011 PAGE_SHARED_X
220#define __S100 PAGE_READONLY
221#define __S101 PAGE_READONLY_X
222#define __S110 PAGE_SHARED
223#define __S111 PAGE_SHARED_X
224
225#ifndef __ASSEMBLY__
226/*
227 * ZERO_PAGE is a global shared page that is always zero: used
228 * for zero-mapped memory areas etc..
229 */
230extern unsigned long empty_zero_page[1024];
231#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
232
233#endif /* __ASSEMBLY__ */
234
235#define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
236#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
237#define pte_clear(mm, addr, ptep) \
238 do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
239
240#define pmd_none(pmd) (!pmd_val(pmd))
241#define pmd_bad(pmd) ((pmd_val(pmd) & _PMD_PRESENT) == 0)
242#define pmd_present(pmd) ((pmd_val(pmd) & _PMD_PRESENT) != 0)
243#define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
244
245#define pte_page(x) (mem_map + (unsigned long) \
246 ((pte_val(x) - memory_start) >> PAGE_SHIFT))
247#define PFN_SHIFT_OFFSET (PAGE_SHIFT)
248
249#define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET)
250
251#define pfn_pte(pfn, prot) \
252 __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) | pgprot_val(prot))
253
254#ifndef __ASSEMBLY__
255/*
256 * The following only work if pte_present() is true.
257 * Undefined behaviour if not..
258 */
259static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
260static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
261static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
262static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
263static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
264
265static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
266static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
267
268static inline pte_t pte_rdprotect(pte_t pte) \
269 { pte_val(pte) &= ~_PAGE_USER; return pte; }
270static inline pte_t pte_wrprotect(pte_t pte) \
271 { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
272static inline pte_t pte_exprotect(pte_t pte) \
273 { pte_val(pte) &= ~_PAGE_EXEC; return pte; }
274static inline pte_t pte_mkclean(pte_t pte) \
275 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
276static inline pte_t pte_mkold(pte_t pte) \
277 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
278
279static inline pte_t pte_mkread(pte_t pte) \
280 { pte_val(pte) |= _PAGE_USER; return pte; }
281static inline pte_t pte_mkexec(pte_t pte) \
282 { pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
283static inline pte_t pte_mkwrite(pte_t pte) \
284 { pte_val(pte) |= _PAGE_RW; return pte; }
285static inline pte_t pte_mkdirty(pte_t pte) \
286 { pte_val(pte) |= _PAGE_DIRTY; return pte; }
287static inline pte_t pte_mkyoung(pte_t pte) \
288 { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
289
290/*
291 * Conversion functions: convert a page and protection to a page entry,
292 * and a page entry and page directory to the page they refer to.
293 */
294
295static inline pte_t mk_pte_phys(phys_addr_t physpage, pgprot_t pgprot)
296{
297 pte_t pte;
298 pte_val(pte) = physpage | pgprot_val(pgprot);
299 return pte;
300}
301
302#define mk_pte(page, pgprot) \
303({ \
304 pte_t pte; \
305 pte_val(pte) = (((page - mem_map) << PAGE_SHIFT) + memory_start) | \
306 pgprot_val(pgprot); \
307 pte; \
308})
309
310static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
311{
312 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
313 return pte;
314}
315
316/*
317 * Atomic PTE updates.
318 *
319 * pte_update clears and sets bit atomically, and returns
320 * the old pte value.
321 * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant
322 * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits.
323 */
324static inline unsigned long pte_update(pte_t *p, unsigned long clr,
325 unsigned long set)
326{
327 unsigned long flags, old, tmp;
328
329 raw_local_irq_save(flags);
330
331 __asm__ __volatile__( "lw %0, %2, r0 \n"
332 "andn %1, %0, %3 \n"
333 "or %1, %1, %4 \n"
334 "sw %1, %2, r0 \n"
335 : "=&r" (old), "=&r" (tmp)
336 : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set)
337 : "cc");
338
339 raw_local_irq_restore(flags);
340
341 return old;
342}
343
344/*
345 * set_pte stores a linux PTE into the linux page table.
346 */
347static inline void set_pte(struct mm_struct *mm, unsigned long addr,
348 pte_t *ptep, pte_t pte)
349{
350 *ptep = pte;
351}
352
353static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
354 pte_t *ptep, pte_t pte)
355{
356 *ptep = pte;
357}
358
359#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
360static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
361 unsigned long address, pte_t *ptep)
362{
363 return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0;
364}
365
366static inline int ptep_test_and_clear_dirty(struct mm_struct *mm,
367 unsigned long addr, pte_t *ptep)
368{
369 return (pte_update(ptep, \
370 (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
371}
372
373#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
374static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
375 unsigned long addr, pte_t *ptep)
376{
377 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
378}
379
380/*static inline void ptep_set_wrprotect(struct mm_struct *mm,
381 unsigned long addr, pte_t *ptep)
382{
383 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
384}*/
385
386static inline void ptep_mkdirty(struct mm_struct *mm,
387 unsigned long addr, pte_t *ptep)
388{
389 pte_update(ptep, 0, _PAGE_DIRTY);
390}
391
392/*#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)*/
393
394/* Convert pmd entry to page */
395/* our pmd entry is an effective address of pte table*/
396/* returns effective address of the pmd entry*/
397static inline unsigned long pmd_page_vaddr(pmd_t pmd)
398{
399 return ((unsigned long) (pmd_val(pmd) & PAGE_MASK));
400}
401
402/* returns struct *page of the pmd entry*/
403#define pmd_page(pmd) (pfn_to_page(__pa(pmd_val(pmd)) >> PAGE_SHIFT))
404
405/* Find an entry in the third-level page table.. */
406
407extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
408
409/*
410 * Encode and decode a swap entry.
411 * Note that the bits we use in a PTE for representing a swap entry
412 * must not include the _PAGE_PRESENT bit, or the _PAGE_HASHPTE bit
413 * (if used). -- paulus
414 */
415#define __swp_type(entry) ((entry).val & 0x3f)
416#define __swp_offset(entry) ((entry).val >> 6)
417#define __swp_entry(type, offset) \
418 ((swp_entry_t) { (type) | ((offset) << 6) })
419#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 })
420#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 })
421
422extern unsigned long iopa(unsigned long addr);
423
424/* Values for nocacheflag and cmode */
425/* These are not used by the APUS kernel_map, but prevents
426 * compilation errors.
427 */
428#define IOMAP_FULL_CACHING 0
429#define IOMAP_NOCACHE_SER 1
430#define IOMAP_NOCACHE_NONSER 2
431#define IOMAP_NO_COPYBACK 3
432
433/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
434#define kern_addr_valid(addr) (1)
435
436void do_page_fault(struct pt_regs *regs, unsigned long address,
437 unsigned long error_code);
438
439void mapin_ram(void);
440int map_page(unsigned long va, phys_addr_t pa, int flags);
441
442extern int mem_init_done;
443
444asmlinkage void __init mmu_init(void);
445
446void __init *early_get_page(void);
447
448#endif /* __ASSEMBLY__ */
449#endif /* __KERNEL__ */
450
451#ifndef __ASSEMBLY__
452extern unsigned long ioremap_bot, ioremap_base;
453
454void setup_memory(void);
455#endif /* __ASSEMBLY__ */
456
457#endif /* _ASM_MICROBLAZE_PGTABLE_H */