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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 */
5
6#include <linux/kernel.h>
7#include <linux/string_helpers.h>
8
9#include "i915_reg.h"
10#include "intel_atomic.h"
11#include "intel_crtc.h"
12#include "intel_cx0_phy.h"
13#include "intel_de.h"
14#include "intel_display.h"
15#include "intel_display_types.h"
16#include "intel_dpio_phy.h"
17#include "intel_dpll.h"
18#include "intel_lvds.h"
19#include "intel_lvds_regs.h"
20#include "intel_panel.h"
21#include "intel_pps.h"
22#include "intel_snps_phy.h"
23#include "vlv_sideband.h"
24
25struct intel_dpll_funcs {
26 int (*crtc_compute_clock)(struct intel_atomic_state *state,
27 struct intel_crtc *crtc);
28 int (*crtc_get_shared_dpll)(struct intel_atomic_state *state,
29 struct intel_crtc *crtc);
30};
31
32struct intel_limit {
33 struct {
34 int min, max;
35 } dot, vco, n, m, m1, m2, p, p1;
36
37 struct {
38 int dot_limit;
39 int p2_slow, p2_fast;
40 } p2;
41};
42static const struct intel_limit intel_limits_i8xx_dac = {
43 .dot = { .min = 25000, .max = 350000 },
44 .vco = { .min = 908000, .max = 1512000 },
45 .n = { .min = 2, .max = 16 },
46 .m = { .min = 96, .max = 140 },
47 .m1 = { .min = 18, .max = 26 },
48 .m2 = { .min = 6, .max = 16 },
49 .p = { .min = 4, .max = 128 },
50 .p1 = { .min = 2, .max = 33 },
51 .p2 = { .dot_limit = 165000,
52 .p2_slow = 4, .p2_fast = 2 },
53};
54
55static const struct intel_limit intel_limits_i8xx_dvo = {
56 .dot = { .min = 25000, .max = 350000 },
57 .vco = { .min = 908000, .max = 1512000 },
58 .n = { .min = 2, .max = 16 },
59 .m = { .min = 96, .max = 140 },
60 .m1 = { .min = 18, .max = 26 },
61 .m2 = { .min = 6, .max = 16 },
62 .p = { .min = 4, .max = 128 },
63 .p1 = { .min = 2, .max = 33 },
64 .p2 = { .dot_limit = 165000,
65 .p2_slow = 4, .p2_fast = 4 },
66};
67
68static const struct intel_limit intel_limits_i8xx_lvds = {
69 .dot = { .min = 25000, .max = 350000 },
70 .vco = { .min = 908000, .max = 1512000 },
71 .n = { .min = 2, .max = 16 },
72 .m = { .min = 96, .max = 140 },
73 .m1 = { .min = 18, .max = 26 },
74 .m2 = { .min = 6, .max = 16 },
75 .p = { .min = 4, .max = 128 },
76 .p1 = { .min = 1, .max = 6 },
77 .p2 = { .dot_limit = 165000,
78 .p2_slow = 14, .p2_fast = 7 },
79};
80
81static const struct intel_limit intel_limits_i9xx_sdvo = {
82 .dot = { .min = 20000, .max = 400000 },
83 .vco = { .min = 1400000, .max = 2800000 },
84 .n = { .min = 1, .max = 6 },
85 .m = { .min = 70, .max = 120 },
86 .m1 = { .min = 8, .max = 18 },
87 .m2 = { .min = 3, .max = 7 },
88 .p = { .min = 5, .max = 80 },
89 .p1 = { .min = 1, .max = 8 },
90 .p2 = { .dot_limit = 200000,
91 .p2_slow = 10, .p2_fast = 5 },
92};
93
94static const struct intel_limit intel_limits_i9xx_lvds = {
95 .dot = { .min = 20000, .max = 400000 },
96 .vco = { .min = 1400000, .max = 2800000 },
97 .n = { .min = 1, .max = 6 },
98 .m = { .min = 70, .max = 120 },
99 .m1 = { .min = 8, .max = 18 },
100 .m2 = { .min = 3, .max = 7 },
101 .p = { .min = 7, .max = 98 },
102 .p1 = { .min = 1, .max = 8 },
103 .p2 = { .dot_limit = 112000,
104 .p2_slow = 14, .p2_fast = 7 },
105};
106
107
108static const struct intel_limit intel_limits_g4x_sdvo = {
109 .dot = { .min = 25000, .max = 270000 },
110 .vco = { .min = 1750000, .max = 3500000},
111 .n = { .min = 1, .max = 4 },
112 .m = { .min = 104, .max = 138 },
113 .m1 = { .min = 17, .max = 23 },
114 .m2 = { .min = 5, .max = 11 },
115 .p = { .min = 10, .max = 30 },
116 .p1 = { .min = 1, .max = 3},
117 .p2 = { .dot_limit = 270000,
118 .p2_slow = 10,
119 .p2_fast = 10
120 },
121};
122
123static const struct intel_limit intel_limits_g4x_hdmi = {
124 .dot = { .min = 22000, .max = 400000 },
125 .vco = { .min = 1750000, .max = 3500000},
126 .n = { .min = 1, .max = 4 },
127 .m = { .min = 104, .max = 138 },
128 .m1 = { .min = 16, .max = 23 },
129 .m2 = { .min = 5, .max = 11 },
130 .p = { .min = 5, .max = 80 },
131 .p1 = { .min = 1, .max = 8},
132 .p2 = { .dot_limit = 165000,
133 .p2_slow = 10, .p2_fast = 5 },
134};
135
136static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
137 .dot = { .min = 20000, .max = 115000 },
138 .vco = { .min = 1750000, .max = 3500000 },
139 .n = { .min = 1, .max = 3 },
140 .m = { .min = 104, .max = 138 },
141 .m1 = { .min = 17, .max = 23 },
142 .m2 = { .min = 5, .max = 11 },
143 .p = { .min = 28, .max = 112 },
144 .p1 = { .min = 2, .max = 8 },
145 .p2 = { .dot_limit = 0,
146 .p2_slow = 14, .p2_fast = 14
147 },
148};
149
150static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
151 .dot = { .min = 80000, .max = 224000 },
152 .vco = { .min = 1750000, .max = 3500000 },
153 .n = { .min = 1, .max = 3 },
154 .m = { .min = 104, .max = 138 },
155 .m1 = { .min = 17, .max = 23 },
156 .m2 = { .min = 5, .max = 11 },
157 .p = { .min = 14, .max = 42 },
158 .p1 = { .min = 2, .max = 6 },
159 .p2 = { .dot_limit = 0,
160 .p2_slow = 7, .p2_fast = 7
161 },
162};
163
164static const struct intel_limit pnv_limits_sdvo = {
165 .dot = { .min = 20000, .max = 400000},
166 .vco = { .min = 1700000, .max = 3500000 },
167 /* Pineview's Ncounter is a ring counter */
168 .n = { .min = 3, .max = 6 },
169 .m = { .min = 2, .max = 256 },
170 /* Pineview only has one combined m divider, which we treat as m2. */
171 .m1 = { .min = 0, .max = 0 },
172 .m2 = { .min = 0, .max = 254 },
173 .p = { .min = 5, .max = 80 },
174 .p1 = { .min = 1, .max = 8 },
175 .p2 = { .dot_limit = 200000,
176 .p2_slow = 10, .p2_fast = 5 },
177};
178
179static const struct intel_limit pnv_limits_lvds = {
180 .dot = { .min = 20000, .max = 400000 },
181 .vco = { .min = 1700000, .max = 3500000 },
182 .n = { .min = 3, .max = 6 },
183 .m = { .min = 2, .max = 256 },
184 .m1 = { .min = 0, .max = 0 },
185 .m2 = { .min = 0, .max = 254 },
186 .p = { .min = 7, .max = 112 },
187 .p1 = { .min = 1, .max = 8 },
188 .p2 = { .dot_limit = 112000,
189 .p2_slow = 14, .p2_fast = 14 },
190};
191
192/* Ironlake / Sandybridge
193 *
194 * We calculate clock using (register_value + 2) for N/M1/M2, so here
195 * the range value for them is (actual_value - 2).
196 */
197static const struct intel_limit ilk_limits_dac = {
198 .dot = { .min = 25000, .max = 350000 },
199 .vco = { .min = 1760000, .max = 3510000 },
200 .n = { .min = 1, .max = 5 },
201 .m = { .min = 79, .max = 127 },
202 .m1 = { .min = 12, .max = 22 },
203 .m2 = { .min = 5, .max = 9 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 225000,
207 .p2_slow = 10, .p2_fast = 5 },
208};
209
210static const struct intel_limit ilk_limits_single_lvds = {
211 .dot = { .min = 25000, .max = 350000 },
212 .vco = { .min = 1760000, .max = 3510000 },
213 .n = { .min = 1, .max = 3 },
214 .m = { .min = 79, .max = 118 },
215 .m1 = { .min = 12, .max = 22 },
216 .m2 = { .min = 5, .max = 9 },
217 .p = { .min = 28, .max = 112 },
218 .p1 = { .min = 2, .max = 8 },
219 .p2 = { .dot_limit = 225000,
220 .p2_slow = 14, .p2_fast = 14 },
221};
222
223static const struct intel_limit ilk_limits_dual_lvds = {
224 .dot = { .min = 25000, .max = 350000 },
225 .vco = { .min = 1760000, .max = 3510000 },
226 .n = { .min = 1, .max = 3 },
227 .m = { .min = 79, .max = 127 },
228 .m1 = { .min = 12, .max = 22 },
229 .m2 = { .min = 5, .max = 9 },
230 .p = { .min = 14, .max = 56 },
231 .p1 = { .min = 2, .max = 8 },
232 .p2 = { .dot_limit = 225000,
233 .p2_slow = 7, .p2_fast = 7 },
234};
235
236/* LVDS 100mhz refclk limits. */
237static const struct intel_limit ilk_limits_single_lvds_100m = {
238 .dot = { .min = 25000, .max = 350000 },
239 .vco = { .min = 1760000, .max = 3510000 },
240 .n = { .min = 1, .max = 2 },
241 .m = { .min = 79, .max = 126 },
242 .m1 = { .min = 12, .max = 22 },
243 .m2 = { .min = 5, .max = 9 },
244 .p = { .min = 28, .max = 112 },
245 .p1 = { .min = 2, .max = 8 },
246 .p2 = { .dot_limit = 225000,
247 .p2_slow = 14, .p2_fast = 14 },
248};
249
250static const struct intel_limit ilk_limits_dual_lvds_100m = {
251 .dot = { .min = 25000, .max = 350000 },
252 .vco = { .min = 1760000, .max = 3510000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 79, .max = 126 },
255 .m1 = { .min = 12, .max = 22 },
256 .m2 = { .min = 5, .max = 9 },
257 .p = { .min = 14, .max = 42 },
258 .p1 = { .min = 2, .max = 6 },
259 .p2 = { .dot_limit = 225000,
260 .p2_slow = 7, .p2_fast = 7 },
261};
262
263static const struct intel_limit intel_limits_vlv = {
264 /*
265 * These are based on the data rate limits (measured in fast clocks)
266 * since those are the strictest limits we have. The fast
267 * clock and actual rate limits are more relaxed, so checking
268 * them would make no difference.
269 */
270 .dot = { .min = 25000, .max = 270000 },
271 .vco = { .min = 4000000, .max = 6000000 },
272 .n = { .min = 1, .max = 7 },
273 .m1 = { .min = 2, .max = 3 },
274 .m2 = { .min = 11, .max = 156 },
275 .p1 = { .min = 2, .max = 3 },
276 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
277};
278
279static const struct intel_limit intel_limits_chv = {
280 /*
281 * These are based on the data rate limits (measured in fast clocks)
282 * since those are the strictest limits we have. The fast
283 * clock and actual rate limits are more relaxed, so checking
284 * them would make no difference.
285 */
286 .dot = { .min = 25000, .max = 540000 },
287 .vco = { .min = 4800000, .max = 6480000 },
288 .n = { .min = 1, .max = 1 },
289 .m1 = { .min = 2, .max = 2 },
290 .m2 = { .min = 24 << 22, .max = 175 << 22 },
291 .p1 = { .min = 2, .max = 4 },
292 .p2 = { .p2_slow = 1, .p2_fast = 14 },
293};
294
295static const struct intel_limit intel_limits_bxt = {
296 .dot = { .min = 25000, .max = 594000 },
297 .vco = { .min = 4800000, .max = 6700000 },
298 .n = { .min = 1, .max = 1 },
299 .m1 = { .min = 2, .max = 2 },
300 /* FIXME: find real m2 limits */
301 .m2 = { .min = 2 << 22, .max = 255 << 22 },
302 .p1 = { .min = 2, .max = 4 },
303 .p2 = { .p2_slow = 1, .p2_fast = 20 },
304};
305
306/*
307 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
308 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
309 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
310 * The helpers' return value is the rate of the clock that is fed to the
311 * display engine's pipe which can be the above fast dot clock rate or a
312 * divided-down version of it.
313 */
314/* m1 is reserved as 0 in Pineview, n is a ring counter */
315static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
316{
317 clock->m = clock->m2 + 2;
318 clock->p = clock->p1 * clock->p2;
319
320 clock->vco = clock->n == 0 ? 0 :
321 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
322 clock->dot = clock->p == 0 ? 0 :
323 DIV_ROUND_CLOSEST(clock->vco, clock->p);
324
325 return clock->dot;
326}
327
328static u32 i9xx_dpll_compute_m(const struct dpll *dpll)
329{
330 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
331}
332
333int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
334{
335 clock->m = i9xx_dpll_compute_m(clock);
336 clock->p = clock->p1 * clock->p2;
337
338 clock->vco = clock->n + 2 == 0 ? 0 :
339 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
340 clock->dot = clock->p == 0 ? 0 :
341 DIV_ROUND_CLOSEST(clock->vco, clock->p);
342
343 return clock->dot;
344}
345
346static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
347{
348 clock->m = clock->m1 * clock->m2;
349 clock->p = clock->p1 * clock->p2 * 5;
350
351 clock->vco = clock->n == 0 ? 0 :
352 DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
353 clock->dot = clock->p == 0 ? 0 :
354 DIV_ROUND_CLOSEST(clock->vco, clock->p);
355
356 return clock->dot;
357}
358
359int chv_calc_dpll_params(int refclk, struct dpll *clock)
360{
361 clock->m = clock->m1 * clock->m2;
362 clock->p = clock->p1 * clock->p2 * 5;
363
364 clock->vco = clock->n == 0 ? 0 :
365 DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), clock->n << 22);
366 clock->dot = clock->p == 0 ? 0 :
367 DIV_ROUND_CLOSEST(clock->vco, clock->p);
368
369 return clock->dot;
370}
371
372static int i9xx_pll_refclk(struct drm_device *dev,
373 const struct intel_crtc_state *pipe_config)
374{
375 struct drm_i915_private *dev_priv = to_i915(dev);
376 u32 dpll = pipe_config->dpll_hw_state.dpll;
377
378 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
379 return dev_priv->display.vbt.lvds_ssc_freq;
380 else if (HAS_PCH_SPLIT(dev_priv))
381 return 120000;
382 else if (DISPLAY_VER(dev_priv) != 2)
383 return 96000;
384 else
385 return 48000;
386}
387
388/* Returns the clock of the currently programmed mode of the given pipe. */
389void i9xx_crtc_clock_get(struct intel_crtc *crtc,
390 struct intel_crtc_state *pipe_config)
391{
392 struct drm_device *dev = crtc->base.dev;
393 struct drm_i915_private *dev_priv = to_i915(dev);
394 u32 dpll = pipe_config->dpll_hw_state.dpll;
395 u32 fp;
396 struct dpll clock;
397 int port_clock;
398 int refclk = i9xx_pll_refclk(dev, pipe_config);
399
400 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
401 fp = pipe_config->dpll_hw_state.fp0;
402 else
403 fp = pipe_config->dpll_hw_state.fp1;
404
405 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
406 if (IS_PINEVIEW(dev_priv)) {
407 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
408 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
409 } else {
410 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
411 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
412 }
413
414 if (DISPLAY_VER(dev_priv) != 2) {
415 if (IS_PINEVIEW(dev_priv))
416 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
417 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
418 else
419 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
420 DPLL_FPA01_P1_POST_DIV_SHIFT);
421
422 switch (dpll & DPLL_MODE_MASK) {
423 case DPLLB_MODE_DAC_SERIAL:
424 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
425 5 : 10;
426 break;
427 case DPLLB_MODE_LVDS:
428 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
429 7 : 14;
430 break;
431 default:
432 drm_dbg_kms(&dev_priv->drm,
433 "Unknown DPLL mode %08x in programmed "
434 "mode\n", (int)(dpll & DPLL_MODE_MASK));
435 return;
436 }
437
438 if (IS_PINEVIEW(dev_priv))
439 port_clock = pnv_calc_dpll_params(refclk, &clock);
440 else
441 port_clock = i9xx_calc_dpll_params(refclk, &clock);
442 } else {
443 enum pipe lvds_pipe;
444
445 if (IS_I85X(dev_priv) &&
446 intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
447 lvds_pipe == crtc->pipe) {
448 u32 lvds = intel_de_read(dev_priv, LVDS);
449
450 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
451 DPLL_FPA01_P1_POST_DIV_SHIFT);
452
453 if (lvds & LVDS_CLKB_POWER_UP)
454 clock.p2 = 7;
455 else
456 clock.p2 = 14;
457 } else {
458 if (dpll & PLL_P1_DIVIDE_BY_TWO)
459 clock.p1 = 2;
460 else {
461 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
462 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
463 }
464 if (dpll & PLL_P2_DIVIDE_BY_4)
465 clock.p2 = 4;
466 else
467 clock.p2 = 2;
468 }
469
470 port_clock = i9xx_calc_dpll_params(refclk, &clock);
471 }
472
473 /*
474 * This value includes pixel_multiplier. We will use
475 * port_clock to compute adjusted_mode.crtc_clock in the
476 * encoder's get_config() function.
477 */
478 pipe_config->port_clock = port_clock;
479}
480
481void vlv_crtc_clock_get(struct intel_crtc *crtc,
482 struct intel_crtc_state *pipe_config)
483{
484 struct drm_device *dev = crtc->base.dev;
485 struct drm_i915_private *dev_priv = to_i915(dev);
486 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
487 struct dpll clock;
488 u32 mdiv;
489 int refclk = 100000;
490
491 /* In case of DSI, DPLL will not be used */
492 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
493 return;
494
495 vlv_dpio_get(dev_priv);
496 mdiv = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
497 vlv_dpio_put(dev_priv);
498
499 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
500 clock.m2 = mdiv & DPIO_M2DIV_MASK;
501 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
502 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
503 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
504
505 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
506}
507
508void chv_crtc_clock_get(struct intel_crtc *crtc,
509 struct intel_crtc_state *pipe_config)
510{
511 struct drm_device *dev = crtc->base.dev;
512 struct drm_i915_private *dev_priv = to_i915(dev);
513 enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe);
514 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
515 struct dpll clock;
516 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
517 int refclk = 100000;
518
519 /* In case of DSI, DPLL will not be used */
520 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
521 return;
522
523 vlv_dpio_get(dev_priv);
524 cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(port));
525 pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(port));
526 pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(port));
527 pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(port));
528 pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
529 vlv_dpio_put(dev_priv);
530
531 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
532 clock.m2 = (pll_dw0 & 0xff) << 22;
533 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
534 clock.m2 |= pll_dw2 & 0x3fffff;
535 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
536 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
537 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
538
539 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
540}
541
542/*
543 * Returns whether the given set of divisors are valid for a given refclk with
544 * the given connectors.
545 */
546static bool intel_pll_is_valid(struct drm_i915_private *dev_priv,
547 const struct intel_limit *limit,
548 const struct dpll *clock)
549{
550 if (clock->n < limit->n.min || limit->n.max < clock->n)
551 return false;
552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
553 return false;
554 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
555 return false;
556 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
557 return false;
558
559 if (!IS_PINEVIEW(dev_priv) && !IS_LP(dev_priv))
560 if (clock->m1 <= clock->m2)
561 return false;
562
563 if (!IS_LP(dev_priv)) {
564 if (clock->p < limit->p.min || limit->p.max < clock->p)
565 return false;
566 if (clock->m < limit->m.min || limit->m.max < clock->m)
567 return false;
568 }
569
570 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
571 return false;
572 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
573 * connector, etc., rather than just a single range.
574 */
575 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
576 return false;
577
578 return true;
579}
580
581static int
582i9xx_select_p2_div(const struct intel_limit *limit,
583 const struct intel_crtc_state *crtc_state,
584 int target)
585{
586 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
587
588 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
589 /*
590 * For LVDS just rely on its current settings for dual-channel.
591 * We haven't figured out how to reliably set up different
592 * single/dual channel state, if we even can.
593 */
594 if (intel_is_dual_link_lvds(dev_priv))
595 return limit->p2.p2_fast;
596 else
597 return limit->p2.p2_slow;
598 } else {
599 if (target < limit->p2.dot_limit)
600 return limit->p2.p2_slow;
601 else
602 return limit->p2.p2_fast;
603 }
604}
605
606/*
607 * Returns a set of divisors for the desired target clock with the given
608 * refclk, or FALSE.
609 *
610 * Target and reference clocks are specified in kHz.
611 *
612 * If match_clock is provided, then best_clock P divider must match the P
613 * divider from @match_clock used for LVDS downclocking.
614 */
615static bool
616i9xx_find_best_dpll(const struct intel_limit *limit,
617 struct intel_crtc_state *crtc_state,
618 int target, int refclk,
619 const struct dpll *match_clock,
620 struct dpll *best_clock)
621{
622 struct drm_device *dev = crtc_state->uapi.crtc->dev;
623 struct dpll clock;
624 int err = target;
625
626 memset(best_clock, 0, sizeof(*best_clock));
627
628 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
640 int this_err;
641
642 i9xx_calc_dpll_params(refclk, &clock);
643 if (!intel_pll_is_valid(to_i915(dev),
644 limit,
645 &clock))
646 continue;
647 if (match_clock &&
648 clock.p != match_clock->p)
649 continue;
650
651 this_err = abs(clock.dot - target);
652 if (this_err < err) {
653 *best_clock = clock;
654 err = this_err;
655 }
656 }
657 }
658 }
659 }
660
661 return (err != target);
662}
663
664/*
665 * Returns a set of divisors for the desired target clock with the given
666 * refclk, or FALSE.
667 *
668 * Target and reference clocks are specified in kHz.
669 *
670 * If match_clock is provided, then best_clock P divider must match the P
671 * divider from @match_clock used for LVDS downclocking.
672 */
673static bool
674pnv_find_best_dpll(const struct intel_limit *limit,
675 struct intel_crtc_state *crtc_state,
676 int target, int refclk,
677 const struct dpll *match_clock,
678 struct dpll *best_clock)
679{
680 struct drm_device *dev = crtc_state->uapi.crtc->dev;
681 struct dpll clock;
682 int err = target;
683
684 memset(best_clock, 0, sizeof(*best_clock));
685
686 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
687
688 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
689 clock.m1++) {
690 for (clock.m2 = limit->m2.min;
691 clock.m2 <= limit->m2.max; clock.m2++) {
692 for (clock.n = limit->n.min;
693 clock.n <= limit->n.max; clock.n++) {
694 for (clock.p1 = limit->p1.min;
695 clock.p1 <= limit->p1.max; clock.p1++) {
696 int this_err;
697
698 pnv_calc_dpll_params(refclk, &clock);
699 if (!intel_pll_is_valid(to_i915(dev),
700 limit,
701 &clock))
702 continue;
703 if (match_clock &&
704 clock.p != match_clock->p)
705 continue;
706
707 this_err = abs(clock.dot - target);
708 if (this_err < err) {
709 *best_clock = clock;
710 err = this_err;
711 }
712 }
713 }
714 }
715 }
716
717 return (err != target);
718}
719
720/*
721 * Returns a set of divisors for the desired target clock with the given
722 * refclk, or FALSE.
723 *
724 * Target and reference clocks are specified in kHz.
725 *
726 * If match_clock is provided, then best_clock P divider must match the P
727 * divider from @match_clock used for LVDS downclocking.
728 */
729static bool
730g4x_find_best_dpll(const struct intel_limit *limit,
731 struct intel_crtc_state *crtc_state,
732 int target, int refclk,
733 const struct dpll *match_clock,
734 struct dpll *best_clock)
735{
736 struct drm_device *dev = crtc_state->uapi.crtc->dev;
737 struct dpll clock;
738 int max_n;
739 bool found = false;
740 /* approximately equals target * 0.00585 */
741 int err_most = (target >> 8) + (target >> 9);
742
743 memset(best_clock, 0, sizeof(*best_clock));
744
745 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_calc_dpll_params(refclk, &clock);
760 if (!intel_pll_is_valid(to_i915(dev),
761 limit,
762 &clock))
763 continue;
764
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
776 return found;
777}
778
779/*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const struct dpll *calculated_clock,
785 const struct dpll *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788{
789 /*
790 * For CHV ignore the error and consider only the P value.
791 * Prefer a bigger P value based on HW requirements.
792 */
793 if (IS_CHERRYVIEW(to_i915(dev))) {
794 *error_ppm = 0;
795
796 return calculated_clock->p > best_clock->p;
797 }
798
799 if (drm_WARN_ON_ONCE(dev, !target_freq))
800 return false;
801
802 *error_ppm = div_u64(1000000ULL *
803 abs(target_freq - calculated_clock->dot),
804 target_freq);
805 /*
806 * Prefer a better P value over a better (smaller) error if the error
807 * is small. Ensure this preference for future configurations too by
808 * setting the error to 0.
809 */
810 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
811 *error_ppm = 0;
812
813 return true;
814 }
815
816 return *error_ppm + 10 < best_error_ppm;
817}
818
819/*
820 * Returns a set of divisors for the desired target clock with the given
821 * refclk, or FALSE.
822 */
823static bool
824vlv_find_best_dpll(const struct intel_limit *limit,
825 struct intel_crtc_state *crtc_state,
826 int target, int refclk,
827 const struct dpll *match_clock,
828 struct dpll *best_clock)
829{
830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
831 struct drm_device *dev = crtc->base.dev;
832 struct dpll clock;
833 unsigned int bestppm = 1000000;
834 /* min update 19.2 MHz */
835 int max_n = min(limit->n.max, refclk / 19200);
836 bool found = false;
837
838 memset(best_clock, 0, sizeof(*best_clock));
839
840 /* based on hardware requirement, prefer smaller n to precision */
841 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
842 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
843 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
844 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
845 clock.p = clock.p1 * clock.p2 * 5;
846 /* based on hardware requirement, prefer bigger m1,m2 values */
847 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
848 unsigned int ppm;
849
850 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
851 refclk * clock.m1);
852
853 vlv_calc_dpll_params(refclk, &clock);
854
855 if (!intel_pll_is_valid(to_i915(dev),
856 limit,
857 &clock))
858 continue;
859
860 if (!vlv_PLL_is_optimal(dev, target,
861 &clock,
862 best_clock,
863 bestppm, &ppm))
864 continue;
865
866 *best_clock = clock;
867 bestppm = ppm;
868 found = true;
869 }
870 }
871 }
872 }
873
874 return found;
875}
876
877/*
878 * Returns a set of divisors for the desired target clock with the given
879 * refclk, or FALSE.
880 */
881static bool
882chv_find_best_dpll(const struct intel_limit *limit,
883 struct intel_crtc_state *crtc_state,
884 int target, int refclk,
885 const struct dpll *match_clock,
886 struct dpll *best_clock)
887{
888 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
889 struct drm_device *dev = crtc->base.dev;
890 unsigned int best_error_ppm;
891 struct dpll clock;
892 u64 m2;
893 int found = false;
894
895 memset(best_clock, 0, sizeof(*best_clock));
896 best_error_ppm = 1000000;
897
898 /*
899 * Based on hardware doc, the n always set to 1, and m1 always
900 * set to 2. If requires to support 200Mhz refclk, we need to
901 * revisit this because n may not 1 anymore.
902 */
903 clock.n = 1;
904 clock.m1 = 2;
905
906 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
907 for (clock.p2 = limit->p2.p2_fast;
908 clock.p2 >= limit->p2.p2_slow;
909 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
910 unsigned int error_ppm;
911
912 clock.p = clock.p1 * clock.p2 * 5;
913
914 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,
915 refclk * clock.m1);
916
917 if (m2 > INT_MAX/clock.m1)
918 continue;
919
920 clock.m2 = m2;
921
922 chv_calc_dpll_params(refclk, &clock);
923
924 if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
925 continue;
926
927 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
928 best_error_ppm, &error_ppm))
929 continue;
930
931 *best_clock = clock;
932 best_error_ppm = error_ppm;
933 found = true;
934 }
935 }
936
937 return found;
938}
939
940bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
941 struct dpll *best_clock)
942{
943 const struct intel_limit *limit = &intel_limits_bxt;
944 int refclk = 100000;
945
946 return chv_find_best_dpll(limit, crtc_state,
947 crtc_state->port_clock, refclk,
948 NULL, best_clock);
949}
950
951u32 i9xx_dpll_compute_fp(const struct dpll *dpll)
952{
953 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
954}
955
956static u32 pnv_dpll_compute_fp(const struct dpll *dpll)
957{
958 return (1 << dpll->n) << 16 | dpll->m2;
959}
960
961static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state,
962 const struct dpll *clock,
963 const struct dpll *reduced_clock)
964{
965 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
966 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
967 u32 fp, fp2;
968
969 if (IS_PINEVIEW(dev_priv)) {
970 fp = pnv_dpll_compute_fp(clock);
971 fp2 = pnv_dpll_compute_fp(reduced_clock);
972 } else {
973 fp = i9xx_dpll_compute_fp(clock);
974 fp2 = i9xx_dpll_compute_fp(reduced_clock);
975 }
976
977 crtc_state->dpll_hw_state.fp0 = fp;
978 crtc_state->dpll_hw_state.fp1 = fp2;
979}
980
981static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state,
982 const struct dpll *clock,
983 const struct dpll *reduced_clock)
984{
985 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
986 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
987 u32 dpll;
988
989 i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
990
991 dpll = DPLL_VGA_MODE_DIS;
992
993 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
994 dpll |= DPLLB_MODE_LVDS;
995 else
996 dpll |= DPLLB_MODE_DAC_SERIAL;
997
998 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
999 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
1000 dpll |= (crtc_state->pixel_multiplier - 1)
1001 << SDVO_MULTIPLIER_SHIFT_HIRES;
1002 }
1003
1004 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
1005 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1006 dpll |= DPLL_SDVO_HIGH_SPEED;
1007
1008 if (intel_crtc_has_dp_encoder(crtc_state))
1009 dpll |= DPLL_SDVO_HIGH_SPEED;
1010
1011 /* compute bitmask from p1 value */
1012 if (IS_G4X(dev_priv)) {
1013 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1014 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1015 } else if (IS_PINEVIEW(dev_priv)) {
1016 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
1017 WARN_ON(reduced_clock->p1 != clock->p1);
1018 } else {
1019 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1020 WARN_ON(reduced_clock->p1 != clock->p1);
1021 }
1022
1023 switch (clock->p2) {
1024 case 5:
1025 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1026 break;
1027 case 7:
1028 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1029 break;
1030 case 10:
1031 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1032 break;
1033 case 14:
1034 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1035 break;
1036 }
1037 WARN_ON(reduced_clock->p2 != clock->p2);
1038
1039 if (DISPLAY_VER(dev_priv) >= 4)
1040 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
1041
1042 if (crtc_state->sdvo_tv_clock)
1043 dpll |= PLL_REF_INPUT_TVCLKINBC;
1044 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1045 intel_panel_use_ssc(dev_priv))
1046 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1047 else
1048 dpll |= PLL_REF_INPUT_DREFCLK;
1049
1050 dpll |= DPLL_VCO_ENABLE;
1051 crtc_state->dpll_hw_state.dpll = dpll;
1052
1053 if (DISPLAY_VER(dev_priv) >= 4) {
1054 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
1055 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1056 crtc_state->dpll_hw_state.dpll_md = dpll_md;
1057 }
1058}
1059
1060static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state,
1061 const struct dpll *clock,
1062 const struct dpll *reduced_clock)
1063{
1064 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1065 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1066 u32 dpll;
1067
1068 i9xx_update_pll_dividers(crtc_state, clock, reduced_clock);
1069
1070 dpll = DPLL_VGA_MODE_DIS;
1071
1072 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1073 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1074 } else {
1075 if (clock->p1 == 2)
1076 dpll |= PLL_P1_DIVIDE_BY_TWO;
1077 else
1078 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1079 if (clock->p2 == 4)
1080 dpll |= PLL_P2_DIVIDE_BY_4;
1081 }
1082 WARN_ON(reduced_clock->p1 != clock->p1);
1083 WARN_ON(reduced_clock->p2 != clock->p2);
1084
1085 /*
1086 * Bspec:
1087 * "[Almador Errata}: For the correct operation of the muxed DVO pins
1088 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
1089 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
1090 * Enable) must be set to “1” in both the DPLL A Control Register
1091 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
1092 *
1093 * For simplicity We simply keep both bits always enabled in
1094 * both DPLLS. The spec says we should disable the DVO 2X clock
1095 * when not needed, but this seems to work fine in practice.
1096 */
1097 if (IS_I830(dev_priv) ||
1098 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
1099 dpll |= DPLL_DVO_2X_MODE;
1100
1101 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1102 intel_panel_use_ssc(dev_priv))
1103 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1104 else
1105 dpll |= PLL_REF_INPUT_DREFCLK;
1106
1107 dpll |= DPLL_VCO_ENABLE;
1108 crtc_state->dpll_hw_state.dpll = dpll;
1109}
1110
1111static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
1112 struct intel_crtc *crtc)
1113{
1114 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1115 struct intel_crtc_state *crtc_state =
1116 intel_atomic_get_new_crtc_state(state, crtc);
1117 struct intel_encoder *encoder =
1118 intel_get_crtc_new_encoder(state, crtc_state);
1119 int ret;
1120
1121 if (DISPLAY_VER(dev_priv) < 11 &&
1122 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1123 return 0;
1124
1125 ret = intel_compute_shared_dplls(state, crtc, encoder);
1126 if (ret)
1127 return ret;
1128
1129 /* FIXME this is a mess */
1130 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1131 return 0;
1132
1133 /* CRT dotclock is determined via other means */
1134 if (!crtc_state->has_pch_encoder)
1135 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1136
1137 return 0;
1138}
1139
1140static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state,
1141 struct intel_crtc *crtc)
1142{
1143 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1144 struct intel_crtc_state *crtc_state =
1145 intel_atomic_get_new_crtc_state(state, crtc);
1146 struct intel_encoder *encoder =
1147 intel_get_crtc_new_encoder(state, crtc_state);
1148
1149 if (DISPLAY_VER(dev_priv) < 11 &&
1150 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1151 return 0;
1152
1153 return intel_reserve_shared_dplls(state, crtc, encoder);
1154}
1155
1156static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
1157 struct intel_crtc *crtc)
1158{
1159 struct intel_crtc_state *crtc_state =
1160 intel_atomic_get_new_crtc_state(state, crtc);
1161 struct intel_encoder *encoder =
1162 intel_get_crtc_new_encoder(state, crtc_state);
1163 int ret;
1164
1165 ret = intel_mpllb_calc_state(crtc_state, encoder);
1166 if (ret)
1167 return ret;
1168
1169 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1170
1171 return 0;
1172}
1173
1174static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
1175 struct intel_crtc *crtc)
1176{
1177 struct intel_crtc_state *crtc_state =
1178 intel_atomic_get_new_crtc_state(state, crtc);
1179 struct intel_encoder *encoder =
1180 intel_get_crtc_new_encoder(state, crtc_state);
1181 int ret;
1182
1183 ret = intel_cx0pll_calc_state(crtc_state, encoder);
1184 if (ret)
1185 return ret;
1186
1187 /* TODO: Do the readback via intel_compute_shared_dplls() */
1188 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->cx0pll_state);
1189
1190 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1191
1192 return 0;
1193}
1194
1195static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
1196{
1197 return dpll->m < factor * dpll->n;
1198}
1199
1200static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state,
1201 const struct dpll *clock,
1202 const struct dpll *reduced_clock)
1203{
1204 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1205 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1206 u32 fp, fp2;
1207 int factor;
1208
1209 /* Enable autotuning of the PLL clock (if permissible) */
1210 factor = 21;
1211 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1212 if ((intel_panel_use_ssc(dev_priv) &&
1213 dev_priv->display.vbt.lvds_ssc_freq == 100000) ||
1214 (HAS_PCH_IBX(dev_priv) &&
1215 intel_is_dual_link_lvds(dev_priv)))
1216 factor = 25;
1217 } else if (crtc_state->sdvo_tv_clock) {
1218 factor = 20;
1219 }
1220
1221 fp = i9xx_dpll_compute_fp(clock);
1222 if (ilk_needs_fb_cb_tune(clock, factor))
1223 fp |= FP_CB_TUNE;
1224
1225 fp2 = i9xx_dpll_compute_fp(reduced_clock);
1226 if (ilk_needs_fb_cb_tune(reduced_clock, factor))
1227 fp2 |= FP_CB_TUNE;
1228
1229 crtc_state->dpll_hw_state.fp0 = fp;
1230 crtc_state->dpll_hw_state.fp1 = fp2;
1231}
1232
1233static void ilk_compute_dpll(struct intel_crtc_state *crtc_state,
1234 const struct dpll *clock,
1235 const struct dpll *reduced_clock)
1236{
1237 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1238 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1239 u32 dpll;
1240
1241 ilk_update_pll_dividers(crtc_state, clock, reduced_clock);
1242
1243 dpll = 0;
1244
1245 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
1246 dpll |= DPLLB_MODE_LVDS;
1247 else
1248 dpll |= DPLLB_MODE_DAC_SERIAL;
1249
1250 dpll |= (crtc_state->pixel_multiplier - 1)
1251 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
1252
1253 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
1254 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1255 dpll |= DPLL_SDVO_HIGH_SPEED;
1256
1257 if (intel_crtc_has_dp_encoder(crtc_state))
1258 dpll |= DPLL_SDVO_HIGH_SPEED;
1259
1260 /*
1261 * The high speed IO clock is only really required for
1262 * SDVO/HDMI/DP, but we also enable it for CRT to make it
1263 * possible to share the DPLL between CRT and HDMI. Enabling
1264 * the clock needlessly does no real harm, except use up a
1265 * bit of power potentially.
1266 *
1267 * We'll limit this to IVB with 3 pipes, since it has only two
1268 * DPLLs and so DPLL sharing is the only way to get three pipes
1269 * driving PCH ports at the same time. On SNB we could do this,
1270 * and potentially avoid enabling the second DPLL, but it's not
1271 * clear if it''s a win or loss power wise. No point in doing
1272 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
1273 */
1274 if (INTEL_NUM_PIPES(dev_priv) == 3 &&
1275 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1276 dpll |= DPLL_SDVO_HIGH_SPEED;
1277
1278 /* compute bitmask from p1 value */
1279 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1280 /* also FPA1 */
1281 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1282
1283 switch (clock->p2) {
1284 case 5:
1285 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
1286 break;
1287 case 7:
1288 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
1289 break;
1290 case 10:
1291 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
1292 break;
1293 case 14:
1294 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1295 break;
1296 }
1297 WARN_ON(reduced_clock->p2 != clock->p2);
1298
1299 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
1300 intel_panel_use_ssc(dev_priv))
1301 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
1302 else
1303 dpll |= PLL_REF_INPUT_DREFCLK;
1304
1305 dpll |= DPLL_VCO_ENABLE;
1306
1307 crtc_state->dpll_hw_state.dpll = dpll;
1308}
1309
1310static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
1311 struct intel_crtc *crtc)
1312{
1313 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1314 struct intel_crtc_state *crtc_state =
1315 intel_atomic_get_new_crtc_state(state, crtc);
1316 const struct intel_limit *limit;
1317 int refclk = 120000;
1318 int ret;
1319
1320 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
1321 if (!crtc_state->has_pch_encoder)
1322 return 0;
1323
1324 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1325 if (intel_panel_use_ssc(dev_priv)) {
1326 drm_dbg_kms(&dev_priv->drm,
1327 "using SSC reference clock of %d kHz\n",
1328 dev_priv->display.vbt.lvds_ssc_freq);
1329 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1330 }
1331
1332 if (intel_is_dual_link_lvds(dev_priv)) {
1333 if (refclk == 100000)
1334 limit = &ilk_limits_dual_lvds_100m;
1335 else
1336 limit = &ilk_limits_dual_lvds;
1337 } else {
1338 if (refclk == 100000)
1339 limit = &ilk_limits_single_lvds_100m;
1340 else
1341 limit = &ilk_limits_single_lvds;
1342 }
1343 } else {
1344 limit = &ilk_limits_dac;
1345 }
1346
1347 if (!crtc_state->clock_set &&
1348 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1349 refclk, NULL, &crtc_state->dpll))
1350 return -EINVAL;
1351
1352 i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1353
1354 ilk_compute_dpll(crtc_state, &crtc_state->dpll,
1355 &crtc_state->dpll);
1356
1357 ret = intel_compute_shared_dplls(state, crtc, NULL);
1358 if (ret)
1359 return ret;
1360
1361 crtc_state->port_clock = crtc_state->dpll.dot;
1362 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1363
1364 return ret;
1365}
1366
1367static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
1368 struct intel_crtc *crtc)
1369{
1370 struct intel_crtc_state *crtc_state =
1371 intel_atomic_get_new_crtc_state(state, crtc);
1372
1373 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
1374 if (!crtc_state->has_pch_encoder)
1375 return 0;
1376
1377 return intel_reserve_shared_dplls(state, crtc, NULL);
1378}
1379
1380void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
1381{
1382 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1383
1384 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
1385 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1386 if (crtc->pipe != PIPE_A)
1387 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1388
1389 /* DPLL not used with DSI, but still need the rest set up */
1390 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1391 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
1392 DPLL_EXT_BUFFER_ENABLE_VLV;
1393
1394 crtc_state->dpll_hw_state.dpll_md =
1395 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1396}
1397
1398void chv_compute_dpll(struct intel_crtc_state *crtc_state)
1399{
1400 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1401
1402 crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
1403 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1404 if (crtc->pipe != PIPE_A)
1405 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1406
1407 /* DPLL not used with DSI, but still need the rest set up */
1408 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1409 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
1410
1411 crtc_state->dpll_hw_state.dpll_md =
1412 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1413}
1414
1415static int chv_crtc_compute_clock(struct intel_atomic_state *state,
1416 struct intel_crtc *crtc)
1417{
1418 struct intel_crtc_state *crtc_state =
1419 intel_atomic_get_new_crtc_state(state, crtc);
1420 const struct intel_limit *limit = &intel_limits_chv;
1421 int refclk = 100000;
1422
1423 if (!crtc_state->clock_set &&
1424 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1425 refclk, NULL, &crtc_state->dpll))
1426 return -EINVAL;
1427
1428 chv_calc_dpll_params(refclk, &crtc_state->dpll);
1429
1430 chv_compute_dpll(crtc_state);
1431
1432 /* FIXME this is a mess */
1433 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1434 return 0;
1435
1436 crtc_state->port_clock = crtc_state->dpll.dot;
1437 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1438
1439 return 0;
1440}
1441
1442static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
1443 struct intel_crtc *crtc)
1444{
1445 struct intel_crtc_state *crtc_state =
1446 intel_atomic_get_new_crtc_state(state, crtc);
1447 const struct intel_limit *limit = &intel_limits_vlv;
1448 int refclk = 100000;
1449
1450 if (!crtc_state->clock_set &&
1451 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1452 refclk, NULL, &crtc_state->dpll))
1453 return -EINVAL;
1454
1455 vlv_calc_dpll_params(refclk, &crtc_state->dpll);
1456
1457 vlv_compute_dpll(crtc_state);
1458
1459 /* FIXME this is a mess */
1460 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
1461 return 0;
1462
1463 crtc_state->port_clock = crtc_state->dpll.dot;
1464 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1465
1466 return 0;
1467}
1468
1469static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
1470 struct intel_crtc *crtc)
1471{
1472 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1473 struct intel_crtc_state *crtc_state =
1474 intel_atomic_get_new_crtc_state(state, crtc);
1475 const struct intel_limit *limit;
1476 int refclk = 96000;
1477
1478 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1479 if (intel_panel_use_ssc(dev_priv)) {
1480 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1481 drm_dbg_kms(&dev_priv->drm,
1482 "using SSC reference clock of %d kHz\n",
1483 refclk);
1484 }
1485
1486 if (intel_is_dual_link_lvds(dev_priv))
1487 limit = &intel_limits_g4x_dual_channel_lvds;
1488 else
1489 limit = &intel_limits_g4x_single_channel_lvds;
1490 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
1491 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1492 limit = &intel_limits_g4x_hdmi;
1493 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
1494 limit = &intel_limits_g4x_sdvo;
1495 } else {
1496 /* The option is for other outputs */
1497 limit = &intel_limits_i9xx_sdvo;
1498 }
1499
1500 if (!crtc_state->clock_set &&
1501 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1502 refclk, NULL, &crtc_state->dpll))
1503 return -EINVAL;
1504
1505 i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1506
1507 i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1508 &crtc_state->dpll);
1509
1510 crtc_state->port_clock = crtc_state->dpll.dot;
1511 /* FIXME this is a mess */
1512 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT))
1513 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1514
1515 return 0;
1516}
1517
1518static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
1519 struct intel_crtc *crtc)
1520{
1521 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1522 struct intel_crtc_state *crtc_state =
1523 intel_atomic_get_new_crtc_state(state, crtc);
1524 const struct intel_limit *limit;
1525 int refclk = 96000;
1526
1527 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1528 if (intel_panel_use_ssc(dev_priv)) {
1529 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1530 drm_dbg_kms(&dev_priv->drm,
1531 "using SSC reference clock of %d kHz\n",
1532 refclk);
1533 }
1534
1535 limit = &pnv_limits_lvds;
1536 } else {
1537 limit = &pnv_limits_sdvo;
1538 }
1539
1540 if (!crtc_state->clock_set &&
1541 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1542 refclk, NULL, &crtc_state->dpll))
1543 return -EINVAL;
1544
1545 pnv_calc_dpll_params(refclk, &crtc_state->dpll);
1546
1547 i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1548 &crtc_state->dpll);
1549
1550 crtc_state->port_clock = crtc_state->dpll.dot;
1551 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1552
1553 return 0;
1554}
1555
1556static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
1557 struct intel_crtc *crtc)
1558{
1559 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1560 struct intel_crtc_state *crtc_state =
1561 intel_atomic_get_new_crtc_state(state, crtc);
1562 const struct intel_limit *limit;
1563 int refclk = 96000;
1564
1565 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1566 if (intel_panel_use_ssc(dev_priv)) {
1567 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1568 drm_dbg_kms(&dev_priv->drm,
1569 "using SSC reference clock of %d kHz\n",
1570 refclk);
1571 }
1572
1573 limit = &intel_limits_i9xx_lvds;
1574 } else {
1575 limit = &intel_limits_i9xx_sdvo;
1576 }
1577
1578 if (!crtc_state->clock_set &&
1579 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1580 refclk, NULL, &crtc_state->dpll))
1581 return -EINVAL;
1582
1583 i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1584
1585 i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
1586 &crtc_state->dpll);
1587
1588 crtc_state->port_clock = crtc_state->dpll.dot;
1589 /* FIXME this is a mess */
1590 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT))
1591 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1592
1593 return 0;
1594}
1595
1596static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
1597 struct intel_crtc *crtc)
1598{
1599 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1600 struct intel_crtc_state *crtc_state =
1601 intel_atomic_get_new_crtc_state(state, crtc);
1602 const struct intel_limit *limit;
1603 int refclk = 48000;
1604
1605 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1606 if (intel_panel_use_ssc(dev_priv)) {
1607 refclk = dev_priv->display.vbt.lvds_ssc_freq;
1608 drm_dbg_kms(&dev_priv->drm,
1609 "using SSC reference clock of %d kHz\n",
1610 refclk);
1611 }
1612
1613 limit = &intel_limits_i8xx_lvds;
1614 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
1615 limit = &intel_limits_i8xx_dvo;
1616 } else {
1617 limit = &intel_limits_i8xx_dac;
1618 }
1619
1620 if (!crtc_state->clock_set &&
1621 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
1622 refclk, NULL, &crtc_state->dpll))
1623 return -EINVAL;
1624
1625 i9xx_calc_dpll_params(refclk, &crtc_state->dpll);
1626
1627 i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
1628 &crtc_state->dpll);
1629
1630 crtc_state->port_clock = crtc_state->dpll.dot;
1631 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
1632
1633 return 0;
1634}
1635
1636static const struct intel_dpll_funcs mtl_dpll_funcs = {
1637 .crtc_compute_clock = mtl_crtc_compute_clock,
1638};
1639
1640static const struct intel_dpll_funcs dg2_dpll_funcs = {
1641 .crtc_compute_clock = dg2_crtc_compute_clock,
1642};
1643
1644static const struct intel_dpll_funcs hsw_dpll_funcs = {
1645 .crtc_compute_clock = hsw_crtc_compute_clock,
1646 .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll,
1647};
1648
1649static const struct intel_dpll_funcs ilk_dpll_funcs = {
1650 .crtc_compute_clock = ilk_crtc_compute_clock,
1651 .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll,
1652};
1653
1654static const struct intel_dpll_funcs chv_dpll_funcs = {
1655 .crtc_compute_clock = chv_crtc_compute_clock,
1656};
1657
1658static const struct intel_dpll_funcs vlv_dpll_funcs = {
1659 .crtc_compute_clock = vlv_crtc_compute_clock,
1660};
1661
1662static const struct intel_dpll_funcs g4x_dpll_funcs = {
1663 .crtc_compute_clock = g4x_crtc_compute_clock,
1664};
1665
1666static const struct intel_dpll_funcs pnv_dpll_funcs = {
1667 .crtc_compute_clock = pnv_crtc_compute_clock,
1668};
1669
1670static const struct intel_dpll_funcs i9xx_dpll_funcs = {
1671 .crtc_compute_clock = i9xx_crtc_compute_clock,
1672};
1673
1674static const struct intel_dpll_funcs i8xx_dpll_funcs = {
1675 .crtc_compute_clock = i8xx_crtc_compute_clock,
1676};
1677
1678int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
1679 struct intel_crtc *crtc)
1680{
1681 struct drm_i915_private *i915 = to_i915(state->base.dev);
1682 struct intel_crtc_state *crtc_state =
1683 intel_atomic_get_new_crtc_state(state, crtc);
1684 int ret;
1685
1686 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
1687
1688 memset(&crtc_state->dpll_hw_state, 0,
1689 sizeof(crtc_state->dpll_hw_state));
1690
1691 if (!crtc_state->hw.enable)
1692 return 0;
1693
1694 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc);
1695 if (ret) {
1696 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
1697 crtc->base.base.id, crtc->base.name);
1698 return ret;
1699 }
1700
1701 return 0;
1702}
1703
1704int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
1705 struct intel_crtc *crtc)
1706{
1707 struct drm_i915_private *i915 = to_i915(state->base.dev);
1708 struct intel_crtc_state *crtc_state =
1709 intel_atomic_get_new_crtc_state(state, crtc);
1710 int ret;
1711
1712 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
1713 drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);
1714
1715 if (!crtc_state->hw.enable || crtc_state->shared_dpll)
1716 return 0;
1717
1718 if (!i915->display.funcs.dpll->crtc_get_shared_dpll)
1719 return 0;
1720
1721 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc);
1722 if (ret) {
1723 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
1724 crtc->base.base.id, crtc->base.name);
1725 return ret;
1726 }
1727
1728 return 0;
1729}
1730
1731void
1732intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
1733{
1734 if (DISPLAY_VER(dev_priv) >= 14)
1735 dev_priv->display.funcs.dpll = &mtl_dpll_funcs;
1736 else if (IS_DG2(dev_priv))
1737 dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
1738 else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
1739 dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
1740 else if (HAS_PCH_SPLIT(dev_priv))
1741 dev_priv->display.funcs.dpll = &ilk_dpll_funcs;
1742 else if (IS_CHERRYVIEW(dev_priv))
1743 dev_priv->display.funcs.dpll = &chv_dpll_funcs;
1744 else if (IS_VALLEYVIEW(dev_priv))
1745 dev_priv->display.funcs.dpll = &vlv_dpll_funcs;
1746 else if (IS_G4X(dev_priv))
1747 dev_priv->display.funcs.dpll = &g4x_dpll_funcs;
1748 else if (IS_PINEVIEW(dev_priv))
1749 dev_priv->display.funcs.dpll = &pnv_dpll_funcs;
1750 else if (DISPLAY_VER(dev_priv) != 2)
1751 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs;
1752 else
1753 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs;
1754}
1755
1756static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
1757{
1758 if (IS_I830(dev_priv))
1759 return false;
1760
1761 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
1762}
1763
1764void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
1765{
1766 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1767 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1768 u32 dpll = crtc_state->dpll_hw_state.dpll;
1769 enum pipe pipe = crtc->pipe;
1770 int i;
1771
1772 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1773
1774 /* PLL is protected by panel, make sure we can write it */
1775 if (i9xx_has_pps(dev_priv))
1776 assert_pps_unlocked(dev_priv, pipe);
1777
1778 intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0);
1779 intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1);
1780
1781 /*
1782 * Apparently we need to have VGA mode enabled prior to changing
1783 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1784 * dividers, even though the register value does change.
1785 */
1786 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
1787 intel_de_write(dev_priv, DPLL(pipe), dpll);
1788
1789 /* Wait for the clocks to stabilize. */
1790 intel_de_posting_read(dev_priv, DPLL(pipe));
1791 udelay(150);
1792
1793 if (DISPLAY_VER(dev_priv) >= 4) {
1794 intel_de_write(dev_priv, DPLL_MD(pipe),
1795 crtc_state->dpll_hw_state.dpll_md);
1796 } else {
1797 /* The pixel multiplier can only be updated once the
1798 * DPLL is enabled and the clocks are stable.
1799 *
1800 * So write it again.
1801 */
1802 intel_de_write(dev_priv, DPLL(pipe), dpll);
1803 }
1804
1805 /* We do this three times for luck */
1806 for (i = 0; i < 3; i++) {
1807 intel_de_write(dev_priv, DPLL(pipe), dpll);
1808 intel_de_posting_read(dev_priv, DPLL(pipe));
1809 udelay(150); /* wait for warmup */
1810 }
1811}
1812
1813static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
1814 enum dpio_phy phy)
1815{
1816 u32 reg_val;
1817
1818 /*
1819 * PLLB opamp always calibrates to max value of 0x3f, force enable it
1820 * and set it to a reasonable value instead.
1821 */
1822 reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
1823 reg_val &= 0xffffff00;
1824 reg_val |= 0x00000030;
1825 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
1826
1827 reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13);
1828 reg_val &= 0x00ffffff;
1829 reg_val |= 0x8c000000;
1830 vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val);
1831
1832 reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
1833 reg_val &= 0xffffff00;
1834 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
1835
1836 reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13);
1837 reg_val &= 0x00ffffff;
1838 reg_val |= 0xb0000000;
1839 vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val);
1840}
1841
1842static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
1843{
1844 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1845 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1846 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
1847 enum pipe pipe = crtc->pipe;
1848 u32 mdiv;
1849 u32 bestn, bestm1, bestm2, bestp1, bestp2;
1850 u32 coreclk, reg_val;
1851
1852 vlv_dpio_get(dev_priv);
1853
1854 bestn = crtc_state->dpll.n;
1855 bestm1 = crtc_state->dpll.m1;
1856 bestm2 = crtc_state->dpll.m2;
1857 bestp1 = crtc_state->dpll.p1;
1858 bestp2 = crtc_state->dpll.p2;
1859
1860 /* See eDP HDMI DPIO driver vbios notes doc */
1861
1862 /* PLL B needs special handling */
1863 if (pipe == PIPE_B)
1864 vlv_pllb_recal_opamp(dev_priv, phy);
1865
1866 /* Set up Tx target for periodic Rcomp update */
1867 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9_BCAST, 0x0100000f);
1868
1869 /* Disable target IRef on PLL */
1870 reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe));
1871 reg_val &= 0x00ffffff;
1872 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW8(pipe), reg_val);
1873
1874 /* Disable fast lock */
1875 vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
1876
1877 /* Set idtafcrecal before PLL is enabled */
1878 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
1879 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
1880 mdiv |= ((bestn << DPIO_N_SHIFT));
1881 mdiv |= (1 << DPIO_K_SHIFT);
1882
1883 /*
1884 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
1885 * but we don't support that).
1886 * Note: don't use the DAC post divider as it seems unstable.
1887 */
1888 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
1889 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), mdiv);
1890
1891 mdiv |= DPIO_ENABLE_CALIBRATION;
1892 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), mdiv);
1893
1894 /* Set HBR and RBR LPF coefficients */
1895 if (crtc_state->port_clock == 162000 ||
1896 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||
1897 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1898 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe),
1899 0x009f0003);
1900 else
1901 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe),
1902 0x00d0000f);
1903
1904 if (intel_crtc_has_dp_encoder(crtc_state)) {
1905 /* Use SSC source */
1906 if (pipe == PIPE_A)
1907 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe),
1908 0x0df40000);
1909 else
1910 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe),
1911 0x0df70000);
1912 } else { /* HDMI or VGA */
1913 /* Use bend source */
1914 if (pipe == PIPE_A)
1915 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe),
1916 0x0df70000);
1917 else
1918 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe),
1919 0x0df40000);
1920 }
1921
1922 coreclk = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW7(pipe));
1923 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
1924 if (intel_crtc_has_dp_encoder(crtc_state))
1925 coreclk |= 0x01000000;
1926 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(pipe), coreclk);
1927
1928 vlv_dpio_write(dev_priv, phy, VLV_PLL_DW11(pipe), 0x87871000);
1929
1930 vlv_dpio_put(dev_priv);
1931}
1932
1933static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state)
1934{
1935 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1936 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1937 enum pipe pipe = crtc->pipe;
1938
1939 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);
1940 intel_de_posting_read(dev_priv, DPLL(pipe));
1941 udelay(150);
1942
1943 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
1944 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe);
1945}
1946
1947void vlv_enable_pll(const struct intel_crtc_state *crtc_state)
1948{
1949 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1950 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951 enum pipe pipe = crtc->pipe;
1952
1953 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1954
1955 /* PLL is protected by panel, make sure we can write it */
1956 assert_pps_unlocked(dev_priv, pipe);
1957
1958 /* Enable Refclk */
1959 intel_de_write(dev_priv, DPLL(pipe),
1960 crtc_state->dpll_hw_state.dpll &
1961 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
1962
1963 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) {
1964 vlv_prepare_pll(crtc_state);
1965 _vlv_enable_pll(crtc_state);
1966 }
1967
1968 intel_de_write(dev_priv, DPLL_MD(pipe),
1969 crtc_state->dpll_hw_state.dpll_md);
1970 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
1971}
1972
1973static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
1974{
1975 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1976 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1977 enum pipe pipe = crtc->pipe;
1978 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1979 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
1980 u32 loopfilter, tribuf_calcntr;
1981 u32 bestm2, bestp1, bestp2, bestm2_frac;
1982 u32 dpio_val;
1983 int vco;
1984
1985 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff;
1986 bestm2 = crtc_state->dpll.m2 >> 22;
1987 bestp1 = crtc_state->dpll.p1;
1988 bestp2 = crtc_state->dpll.p2;
1989 vco = crtc_state->dpll.vco;
1990 dpio_val = 0;
1991 loopfilter = 0;
1992
1993 vlv_dpio_get(dev_priv);
1994
1995 /* p1 and p2 divider */
1996 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port),
1997 5 << DPIO_CHV_S1_DIV_SHIFT |
1998 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
1999 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
2000 1 << DPIO_CHV_K_DIV_SHIFT);
2001
2002 /* Feedback post-divider - m2 */
2003 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port), bestm2);
2004
2005 /* Feedback refclk divider - n and m1 */
2006 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port),
2007 DPIO_CHV_M1_DIV_BY_2 |
2008 1 << DPIO_CHV_N_DIV_SHIFT);
2009
2010 /* M2 fraction division */
2011 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port), bestm2_frac);
2012
2013 /* M2 fraction division enable */
2014 dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
2015 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
2016 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
2017 if (bestm2_frac)
2018 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
2019 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), dpio_val);
2020
2021 /* Program digital lock detect threshold */
2022 dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(port));
2023 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
2024 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
2025 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
2026 if (!bestm2_frac)
2027 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
2028 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), dpio_val);
2029
2030 /* Loop filter */
2031 if (vco == 5400000) {
2032 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
2033 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
2034 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
2035 tribuf_calcntr = 0x9;
2036 } else if (vco <= 6200000) {
2037 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
2038 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
2039 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
2040 tribuf_calcntr = 0x9;
2041 } else if (vco <= 6480000) {
2042 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
2043 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
2044 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
2045 tribuf_calcntr = 0x8;
2046 } else {
2047 /* Not supported. Apply the same limits as in the max case */
2048 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
2049 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
2050 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
2051 tribuf_calcntr = 0;
2052 }
2053 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(port), loopfilter);
2054
2055 dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(port));
2056 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
2057 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
2058 vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(port), dpio_val);
2059
2060 /* AFC Recal */
2061 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port),
2062 vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)) |
2063 DPIO_AFC_RECAL);
2064
2065 vlv_dpio_put(dev_priv);
2066}
2067
2068static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
2069{
2070 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2071 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2072 enum pipe pipe = crtc->pipe;
2073 enum dpio_channel port = vlv_pipe_to_channel(pipe);
2074 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
2075 u32 tmp;
2076
2077 vlv_dpio_get(dev_priv);
2078
2079 /* Enable back the 10bit clock to display controller */
2080 tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port));
2081 tmp |= DPIO_DCLKP_EN;
2082 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), tmp);
2083
2084 vlv_dpio_put(dev_priv);
2085
2086 /*
2087 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
2088 */
2089 udelay(1);
2090
2091 /* Enable PLL */
2092 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll);
2093
2094 /* Check PLL is locked */
2095 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
2096 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe);
2097}
2098
2099void chv_enable_pll(const struct intel_crtc_state *crtc_state)
2100{
2101 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2102 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2103 enum pipe pipe = crtc->pipe;
2104
2105 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
2106
2107 /* PLL is protected by panel, make sure we can write it */
2108 assert_pps_unlocked(dev_priv, pipe);
2109
2110 /* Enable Refclk and SSC */
2111 intel_de_write(dev_priv, DPLL(pipe),
2112 crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
2113
2114 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) {
2115 chv_prepare_pll(crtc_state);
2116 _chv_enable_pll(crtc_state);
2117 }
2118
2119 if (pipe != PIPE_A) {
2120 /*
2121 * WaPixelRepeatModeFixForC0:chv
2122 *
2123 * DPLLCMD is AWOL. Use chicken bits to propagate
2124 * the value from DPLLBMD to either pipe B or C.
2125 */
2126 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe));
2127 intel_de_write(dev_priv, DPLL_MD(PIPE_B),
2128 crtc_state->dpll_hw_state.dpll_md);
2129 intel_de_write(dev_priv, CBR4_VLV, 0);
2130 dev_priv->display.state.chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md;
2131
2132 /*
2133 * DPLLB VGA mode also seems to cause problems.
2134 * We should always have it disabled.
2135 */
2136 drm_WARN_ON(&dev_priv->drm,
2137 (intel_de_read(dev_priv, DPLL(PIPE_B)) &
2138 DPLL_VGA_MODE_DIS) == 0);
2139 } else {
2140 intel_de_write(dev_priv, DPLL_MD(pipe),
2141 crtc_state->dpll_hw_state.dpll_md);
2142 intel_de_posting_read(dev_priv, DPLL_MD(pipe));
2143 }
2144}
2145
2146/**
2147 * vlv_force_pll_on - forcibly enable just the PLL
2148 * @dev_priv: i915 private structure
2149 * @pipe: pipe PLL to enable
2150 * @dpll: PLL configuration
2151 *
2152 * Enable the PLL for @pipe using the supplied @dpll config. To be used
2153 * in cases where we need the PLL enabled even when @pipe is not going to
2154 * be enabled.
2155 */
2156int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
2157 const struct dpll *dpll)
2158{
2159 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
2160 struct intel_crtc_state *crtc_state;
2161
2162 crtc_state = intel_crtc_state_alloc(crtc);
2163 if (!crtc_state)
2164 return -ENOMEM;
2165
2166 crtc_state->cpu_transcoder = (enum transcoder)pipe;
2167 crtc_state->pixel_multiplier = 1;
2168 crtc_state->dpll = *dpll;
2169 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP);
2170
2171 if (IS_CHERRYVIEW(dev_priv)) {
2172 chv_compute_dpll(crtc_state);
2173 chv_enable_pll(crtc_state);
2174 } else {
2175 vlv_compute_dpll(crtc_state);
2176 vlv_enable_pll(crtc_state);
2177 }
2178
2179 intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);
2180
2181 return 0;
2182}
2183
2184void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
2185{
2186 u32 val;
2187
2188 /* Make sure the pipe isn't still relying on us */
2189 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe);
2190
2191 val = DPLL_INTEGRATED_REF_CLK_VLV |
2192 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
2193 if (pipe != PIPE_A)
2194 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
2195
2196 intel_de_write(dev_priv, DPLL(pipe), val);
2197 intel_de_posting_read(dev_priv, DPLL(pipe));
2198}
2199
2200void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
2201{
2202 enum dpio_channel port = vlv_pipe_to_channel(pipe);
2203 enum dpio_phy phy = vlv_pipe_to_phy(pipe);
2204 u32 val;
2205
2206 /* Make sure the pipe isn't still relying on us */
2207 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe);
2208
2209 val = DPLL_SSC_REF_CLK_CHV |
2210 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
2211 if (pipe != PIPE_A)
2212 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
2213
2214 intel_de_write(dev_priv, DPLL(pipe), val);
2215 intel_de_posting_read(dev_priv, DPLL(pipe));
2216
2217 vlv_dpio_get(dev_priv);
2218
2219 /* Disable 10bit clock to display controller */
2220 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port));
2221 val &= ~DPIO_DCLKP_EN;
2222 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), val);
2223
2224 vlv_dpio_put(dev_priv);
2225}
2226
2227void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
2228{
2229 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2230 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2231 enum pipe pipe = crtc->pipe;
2232
2233 /* Don't disable pipe or pipe PLLs if needed */
2234 if (IS_I830(dev_priv))
2235 return;
2236
2237 /* Make sure the pipe isn't still relying on us */
2238 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
2239
2240 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
2241 intel_de_posting_read(dev_priv, DPLL(pipe));
2242}
2243
2244
2245/**
2246 * vlv_force_pll_off - forcibly disable just the PLL
2247 * @dev_priv: i915 private structure
2248 * @pipe: pipe PLL to disable
2249 *
2250 * Disable the PLL for @pipe. To be used in cases where we need
2251 * the PLL enabled even when @pipe is not going to be enabled.
2252 */
2253void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
2254{
2255 if (IS_CHERRYVIEW(dev_priv))
2256 chv_disable_pll(dev_priv, pipe);
2257 else
2258 vlv_disable_pll(dev_priv, pipe);
2259}
2260
2261/* Only for pre-ILK configs */
2262static void assert_pll(struct drm_i915_private *dev_priv,
2263 enum pipe pipe, bool state)
2264{
2265 bool cur_state;
2266
2267 cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
2268 I915_STATE_WARN(dev_priv, cur_state != state,
2269 "PLL state assertion failure (expected %s, current %s)\n",
2270 str_on_off(state), str_on_off(cur_state));
2271}
2272
2273void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
2274{
2275 assert_pll(i915, pipe, true);
2276}
2277
2278void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe)
2279{
2280 assert_pll(i915, pipe, false);
2281}