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1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#if !defined (_soc21_ENUM_HEADER)
24#define _soc21_ENUM_HEADER
25
26#ifndef _DRIVER_BUILD
27#ifndef GL_ZERO
28#define GL__ZERO BLEND_ZERO
29#define GL__ONE BLEND_ONE
30#define GL__SRC_COLOR BLEND_SRC_COLOR
31#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR
32#define GL__DST_COLOR BLEND_DST_COLOR
33#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR
34#define GL__SRC_ALPHA BLEND_SRC_ALPHA
35#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA
36#define GL__DST_ALPHA BLEND_DST_ALPHA
37#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA
38#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE
39#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR
40#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR
41#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA
42#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA
43#endif
44#endif
45
46/*******************************************************
47 * Chip Enums
48 *******************************************************/
49
50/*
51 * DSM_DATA_SEL enum
52 */
53
54typedef enum DSM_DATA_SEL {
55DSM_DATA_SEL_DISABLE = 0x00000000,
56DSM_DATA_SEL_0 = 0x00000001,
57DSM_DATA_SEL_1 = 0x00000002,
58DSM_DATA_SEL_BOTH = 0x00000003,
59} DSM_DATA_SEL;
60
61/*
62 * DSM_ENABLE_ERROR_INJECT enum
63 */
64
65typedef enum DSM_ENABLE_ERROR_INJECT {
66DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
67DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
68DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002,
69DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003,
70} DSM_ENABLE_ERROR_INJECT;
71
72/*
73 * DSM_SELECT_INJECT_DELAY enum
74 */
75
76typedef enum DSM_SELECT_INJECT_DELAY {
77DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
78DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
79} DSM_SELECT_INJECT_DELAY;
80
81/*
82 * DSM_SINGLE_WRITE enum
83 */
84
85typedef enum DSM_SINGLE_WRITE {
86DSM_SINGLE_WRITE_DIS = 0x00000000,
87DSM_SINGLE_WRITE_EN = 0x00000001,
88} DSM_SINGLE_WRITE;
89
90/*
91 * ENUM_NUM_SIMD_PER_CU enum
92 */
93
94typedef enum ENUM_NUM_SIMD_PER_CU {
95NUM_SIMD_PER_CU = 0x00000004,
96} ENUM_NUM_SIMD_PER_CU;
97
98/*
99 * GATCL1RequestType enum
100 */
101
102typedef enum GATCL1RequestType {
103GATCL1_TYPE_NORMAL = 0x00000000,
104GATCL1_TYPE_SHOOTDOWN = 0x00000001,
105GATCL1_TYPE_BYPASS = 0x00000002,
106} GATCL1RequestType;
107
108/*
109 * GL0V_CACHE_POLICIES enum
110 */
111
112typedef enum GL0V_CACHE_POLICIES {
113GL0V_CACHE_POLICY_MISS_LRU = 0x00000000,
114GL0V_CACHE_POLICY_MISS_EVICT = 0x00000001,
115GL0V_CACHE_POLICY_HIT_LRU = 0x00000002,
116GL0V_CACHE_POLICY_HIT_EVICT = 0x00000003,
117} GL0V_CACHE_POLICIES;
118
119/*
120 * GL1_CACHE_POLICIES enum
121 */
122
123typedef enum GL1_CACHE_POLICIES {
124GL1_CACHE_POLICY_MISS_LRU = 0x00000000,
125GL1_CACHE_POLICY_MISS_EVICT = 0x00000001,
126GL1_CACHE_POLICY_HIT_LRU = 0x00000002,
127GL1_CACHE_POLICY_HIT_EVICT = 0x00000003,
128} GL1_CACHE_POLICIES;
129
130/*
131 * GL1_CACHE_STORE_POLICIES enum
132 */
133
134typedef enum GL1_CACHE_STORE_POLICIES {
135GL1_CACHE_STORE_POLICY_BYPASS = 0x00000000,
136} GL1_CACHE_STORE_POLICIES;
137
138/*
139 * GL2_CACHE_POLICIES enum
140 */
141
142typedef enum GL2_CACHE_POLICIES {
143GL2_CACHE_POLICY_LRU = 0x00000000,
144GL2_CACHE_POLICY_STREAM = 0x00000001,
145GL2_CACHE_POLICY_NOA = 0x00000002,
146GL2_CACHE_POLICY_BYPASS = 0x00000003,
147} GL2_CACHE_POLICIES;
148
149/*
150 * Hdp_SurfaceEndian enum
151 */
152
153typedef enum Hdp_SurfaceEndian {
154HDP_ENDIAN_NONE = 0x00000000,
155HDP_ENDIAN_8IN16 = 0x00000001,
156HDP_ENDIAN_8IN32 = 0x00000002,
157HDP_ENDIAN_8IN64 = 0x00000003,
158} Hdp_SurfaceEndian;
159
160/*
161 * MTYPE enum
162 */
163
164typedef enum MTYPE {
165MTYPE_C_RW_US = 0x00000000,
166MTYPE_RESERVED_1 = 0x00000001,
167MTYPE_C_RO_S = 0x00000002,
168MTYPE_UC = 0x00000003,
169MTYPE_C_RW_S = 0x00000004,
170MTYPE_RESERVED_5 = 0x00000005,
171MTYPE_C_RO_US = 0x00000006,
172MTYPE_RESERVED_7 = 0x00000007,
173} MTYPE;
174
175/*
176 * PERFMON_COUNTER_MODE enum
177 */
178
179typedef enum PERFMON_COUNTER_MODE {
180PERFMON_COUNTER_MODE_ACCUM = 0x00000000,
181PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001,
182PERFMON_COUNTER_MODE_MAX = 0x00000002,
183PERFMON_COUNTER_MODE_DIRTY = 0x00000003,
184PERFMON_COUNTER_MODE_SAMPLE = 0x00000004,
185PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
186PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
187PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007,
188PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008,
189PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009,
190PERFMON_COUNTER_MODE_RESERVED = 0x0000000f,
191} PERFMON_COUNTER_MODE;
192
193/*
194 * PERFMON_SPM_MODE enum
195 */
196
197typedef enum PERFMON_SPM_MODE {
198PERFMON_SPM_MODE_OFF = 0x00000000,
199PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001,
200PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002,
201PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003,
202PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004,
203PERFMON_SPM_MODE_RESERVED_5 = 0x00000005,
204PERFMON_SPM_MODE_RESERVED_6 = 0x00000006,
205PERFMON_SPM_MODE_RESERVED_7 = 0x00000007,
206PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008,
207PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009,
208PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a,
209} PERFMON_SPM_MODE;
210
211/*
212 * RMI_CID enum
213 */
214
215typedef enum RMI_CID {
216RMI_CID_CC = 0x00000000,
217RMI_CID_FC = 0x00000001,
218RMI_CID_CM = 0x00000002,
219RMI_CID_DC = 0x00000003,
220RMI_CID_Z = 0x00000004,
221RMI_CID_S = 0x00000005,
222RMI_CID_TILE = 0x00000006,
223RMI_CID_ZPCPSD = 0x00000007,
224} RMI_CID;
225
226/*
227 * ReadPolicy enum
228 */
229
230typedef enum ReadPolicy {
231CACHE_LRU_RD = 0x00000000,
232CACHE_STREAM_RD = 0x00000001,
233CACHE_NOA = 0x00000002,
234RESERVED_RDPOLICY = 0x00000003,
235} ReadPolicy;
236
237/*
238 * SDMA_PERFMON_SEL enum
239 */
240
241typedef enum SDMA_PERFMON_SEL {
242SDMA_PERFMON_SEL_CYCLE = 0x00000000,
243SDMA_PERFMON_SEL_IDLE = 0x00000001,
244SDMA_PERFMON_SEL_REG_IDLE = 0x00000002,
245SDMA_PERFMON_SEL_RB_EMPTY = 0x00000003,
246SDMA_PERFMON_SEL_RB_FULL = 0x00000004,
247SDMA_PERFMON_SEL_RB_WPTR_WRAP = 0x00000005,
248SDMA_PERFMON_SEL_RB_RPTR_WRAP = 0x00000006,
249SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 0x00000007,
250SDMA_PERFMON_SEL_RB_RPTR_WB = 0x00000008,
251SDMA_PERFMON_SEL_RB_CMD_IDLE = 0x00000009,
252SDMA_PERFMON_SEL_RB_CMD_FULL = 0x0000000a,
253SDMA_PERFMON_SEL_IB_CMD_IDLE = 0x0000000b,
254SDMA_PERFMON_SEL_IB_CMD_FULL = 0x0000000c,
255SDMA_PERFMON_SEL_EX_IDLE = 0x0000000d,
256SDMA_PERFMON_SEL_SRBM_REG_SEND = 0x0000000e,
257SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
258SDMA_PERFMON_SEL_WR_BA_RTR = 0x00000010,
259SDMA_PERFMON_SEL_MC_WR_IDLE = 0x00000011,
260SDMA_PERFMON_SEL_MC_WR_COUNT = 0x00000012,
261SDMA_PERFMON_SEL_RD_BA_RTR = 0x00000013,
262SDMA_PERFMON_SEL_MC_RD_IDLE = 0x00000014,
263SDMA_PERFMON_SEL_MC_RD_COUNT = 0x00000015,
264SDMA_PERFMON_SEL_MC_RD_RET_STALL = 0x00000016,
265SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 0x00000017,
266SDMA_PERFMON_SEL_SEM_IDLE = 0x0000001a,
267SDMA_PERFMON_SEL_SEM_REQ_STALL = 0x0000001b,
268SDMA_PERFMON_SEL_SEM_REQ_COUNT = 0x0000001c,
269SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 0x0000001d,
270SDMA_PERFMON_SEL_SEM_RESP_FAIL = 0x0000001e,
271SDMA_PERFMON_SEL_SEM_RESP_PASS = 0x0000001f,
272SDMA_PERFMON_SEL_INT_IDLE = 0x00000020,
273SDMA_PERFMON_SEL_INT_REQ_STALL = 0x00000021,
274SDMA_PERFMON_SEL_INT_REQ_COUNT = 0x00000022,
275SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 0x00000023,
276SDMA_PERFMON_SEL_INT_RESP_RETRY = 0x00000024,
277SDMA_PERFMON_SEL_NUM_PACKET = 0x00000025,
278SDMA_PERFMON_SEL_CE_WREQ_IDLE = 0x00000027,
279SDMA_PERFMON_SEL_CE_WR_IDLE = 0x00000028,
280SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 0x00000029,
281SDMA_PERFMON_SEL_CE_RREQ_IDLE = 0x0000002a,
282SDMA_PERFMON_SEL_CE_OUT_IDLE = 0x0000002b,
283SDMA_PERFMON_SEL_CE_IN_IDLE = 0x0000002c,
284SDMA_PERFMON_SEL_CE_DST_IDLE = 0x0000002d,
285SDMA_PERFMON_SEL_CE_AFIFO_FULL = 0x00000030,
286SDMA_PERFMON_SEL_CE_INFO_FULL = 0x00000033,
287SDMA_PERFMON_SEL_CE_INFO1_FULL = 0x00000034,
288SDMA_PERFMON_SEL_CE_RD_STALL = 0x00000035,
289SDMA_PERFMON_SEL_CE_WR_STALL = 0x00000036,
290SDMA_PERFMON_SEL_GFX_SELECT = 0x00000037,
291SDMA_PERFMON_SEL_RLC0_SELECT = 0x00000038,
292SDMA_PERFMON_SEL_RLC1_SELECT = 0x00000039,
293SDMA_PERFMON_SEL_PAGE_SELECT = 0x0000003a,
294SDMA_PERFMON_SEL_CTX_CHANGE = 0x0000003b,
295SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 0x0000003c,
296SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 0x0000003d,
297SDMA_PERFMON_SEL_DOORBELL = 0x0000003e,
298SDMA_PERFMON_SEL_F32_L1_WR_VLD = 0x0000003f,
299SDMA_PERFMON_SEL_CE_L1_WR_VLD = 0x00000040,
300SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 0x00000041,
301SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 0x00000042,
302SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 0x00000043,
303SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 0x00000044,
304SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045,
305SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046,
306SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 0x00000047,
307SDMA_PERFMON_SEL_UTCL2_RET_ACK = 0x00000048,
308SDMA_PERFMON_SEL_UTCL2_FREE = 0x00000049,
309SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 0x0000004a,
310SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 0x0000004b,
311SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 0x0000004c,
312SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 0x0000004d,
313SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 0x0000004e,
314SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 0x0000004f,
315SDMA_PERFMON_SEL_GPUVM_INV_LOW = 0x00000050,
316SDMA_PERFMON_SEL_L1_WRL2_IDLE = 0x00000051,
317SDMA_PERFMON_SEL_L1_RDL2_IDLE = 0x00000052,
318SDMA_PERFMON_SEL_L1_WRMC_IDLE = 0x00000053,
319SDMA_PERFMON_SEL_L1_RDMC_IDLE = 0x00000054,
320SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 0x00000055,
321SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 0x00000056,
322SDMA_PERFMON_SEL_META_L2_REQ_SEND = 0x00000057,
323SDMA_PERFMON_SEL_L2_META_RET_VLD = 0x00000058,
324SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 0x00000059,
325SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a,
326SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b,
327SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c,
328SDMA_PERFMON_SEL_META_REQ_SEND = 0x0000005d,
329SDMA_PERFMON_SEL_META_RTN_VLD = 0x0000005e,
330SDMA_PERFMON_SEL_TLBI_SEND = 0x0000005f,
331SDMA_PERFMON_SEL_TLBI_RTN = 0x00000060,
332SDMA_PERFMON_SEL_GCR_SEND = 0x00000061,
333SDMA_PERFMON_SEL_GCR_RTN = 0x00000062,
334SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 0x00000063,
335SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 0x00000064,
336} SDMA_PERFMON_SEL;
337
338/*
339 * SDMA_PERF_SEL enum
340 */
341
342typedef enum SDMA_PERF_SEL {
343SDMA_PERF_SEL_CYCLE = 0x00000000,
344SDMA_PERF_SEL_IDLE = 0x00000001,
345SDMA_PERF_SEL_REG_IDLE = 0x00000002,
346SDMA_PERF_SEL_RB_EMPTY = 0x00000003,
347SDMA_PERF_SEL_RB_FULL = 0x00000004,
348SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005,
349SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006,
350SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007,
351SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008,
352SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009,
353SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a,
354SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b,
355SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c,
356SDMA_PERF_SEL_EX_IDLE = 0x0000000d,
357SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e,
358SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
359SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010,
360SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011,
361SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012,
362SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013,
363SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014,
364SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015,
365SDMA_PERF_SEL_SEM_IDLE = 0x00000018,
366SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019,
367SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a,
368SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b,
369SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c,
370SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d,
371SDMA_PERF_SEL_INT_IDLE = 0x0000001e,
372SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f,
373SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020,
374SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021,
375SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022,
376SDMA_PERF_SEL_NUM_PACKET = 0x00000023,
377SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025,
378SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026,
379SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027,
380SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028,
381SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029,
382SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a,
383SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b,
384SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e,
385SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031,
386SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032,
387SDMA_PERF_SEL_CE_RD_STALL = 0x00000033,
388SDMA_PERF_SEL_CE_WR_STALL = 0x00000034,
389SDMA_PERF_SEL_GFX_SELECT = 0x00000035,
390SDMA_PERF_SEL_RLC0_SELECT = 0x00000036,
391SDMA_PERF_SEL_RLC1_SELECT = 0x00000037,
392SDMA_PERF_SEL_PAGE_SELECT = 0x00000038,
393SDMA_PERF_SEL_CTX_CHANGE = 0x00000039,
394SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a,
395SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b,
396SDMA_PERF_SEL_DOORBELL = 0x0000003c,
397SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d,
398SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e,
399SDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f,
400SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040,
401SDMA_PERF_SEL_CPF_SDMA_INVREQ = 0x00000041,
402SDMA_PERF_SEL_SDMA_CPF_INVACK = 0x00000042,
403SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 0x00000043,
404SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 0x00000044,
405SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045,
406SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046,
407SDMA_PERF_SEL_UTCL2_RET_XNACK = 0x00000047,
408SDMA_PERF_SEL_UTCL2_RET_ACK = 0x00000048,
409SDMA_PERF_SEL_UTCL2_FREE = 0x00000049,
410SDMA_PERF_SEL_SDMA_UTCL2_SEND = 0x0000004a,
411SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004b,
412SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004c,
413SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004d,
414SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004e,
415SDMA_PERF_SEL_GPUVM_INV_HIGH = 0x0000004f,
416SDMA_PERF_SEL_GPUVM_INV_LOW = 0x00000050,
417SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000051,
418SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000052,
419SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000053,
420SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000054,
421SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000055,
422SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000056,
423SDMA_PERF_SEL_META_L2_REQ_SEND = 0x00000057,
424SDMA_PERF_SEL_L2_META_RET_VLD = 0x00000058,
425SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 0x00000059,
426SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a,
427SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b,
428SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c,
429SDMA_PERF_SEL_META_REQ_SEND = 0x0000005d,
430SDMA_PERF_SEL_META_RTN_VLD = 0x0000005e,
431SDMA_PERF_SEL_TLBI_SEND = 0x0000005f,
432SDMA_PERF_SEL_TLBI_RTN = 0x00000060,
433SDMA_PERF_SEL_GCR_SEND = 0x00000061,
434SDMA_PERF_SEL_GCR_RTN = 0x00000062,
435SDMA_PERF_SEL_CGCG_FENCE = 0x00000063,
436SDMA_PERF_SEL_CE_CH_WR_REQ = 0x00000064,
437SDMA_PERF_SEL_CE_CH_WR_RET = 0x00000065,
438SDMA_PERF_SEL_F32_CH_WR_REQ = 0x00000066,
439SDMA_PERF_SEL_F32_CH_WR_RET = 0x00000067,
440SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ = 0x00000068,
441SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET = 0x00000069,
442SDMA_PERF_SEL_RB_CH_RD_REQ = 0x0000006a,
443SDMA_PERF_SEL_RB_CH_RD_RET = 0x0000006b,
444SDMA_PERF_SEL_IB_CH_RD_REQ = 0x0000006c,
445SDMA_PERF_SEL_IB_CH_RD_RET = 0x0000006d,
446SDMA_PERF_SEL_WPTR_CH_RD_REQ = 0x0000006e,
447SDMA_PERF_SEL_WPTR_CH_RD_RET = 0x0000006f,
448SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 0x00000070,
449SDMA_PERF_SEL_UTCL1_UTCL2_RET = 0x00000071,
450SDMA_PERF_SEL_CMD_OP_MATCH = 0x00000072,
451SDMA_PERF_SEL_CMD_OP_START = 0x00000073,
452SDMA_PERF_SEL_CMD_OP_END = 0x00000074,
453SDMA_PERF_SEL_CE_BUSY = 0x00000075,
454SDMA_PERF_SEL_CE_BUSY_START = 0x00000076,
455SDMA_PERF_SEL_CE_BUSY_END = 0x00000077,
456SDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 0x00000078,
457SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 0x00000079,
458SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 0x0000007a,
459SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 0x0000007b,
460SDMA_PERF_SEL_CH_CE_WRRET_VALID = 0x0000007c,
461SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 0x0000007d,
462SDMA_PERF_SEL_CH_CE_RDRET_VALID = 0x0000007e,
463} SDMA_PERF_SEL;
464
465/*
466 * TCC_CACHE_POLICIES enum
467 */
468
469typedef enum TCC_CACHE_POLICIES {
470TCC_CACHE_POLICY_LRU = 0x00000000,
471TCC_CACHE_POLICY_STREAM = 0x00000001,
472} TCC_CACHE_POLICIES;
473
474/*
475 * TCC_MTYPE enum
476 */
477
478typedef enum TCC_MTYPE {
479MTYPE_NC = 0x00000000,
480MTYPE_WC = 0x00000001,
481MTYPE_CC = 0x00000002,
482} TCC_MTYPE;
483
484/*
485 * UTCL0FaultType enum
486 */
487
488typedef enum UTCL0FaultType {
489UTCL0_XNACK_SUCCESS = 0x00000000,
490UTCL0_XNACK_RETRY = 0x00000001,
491UTCL0_XNACK_PRT = 0x00000002,
492UTCL0_XNACK_NO_RETRY = 0x00000003,
493} UTCL0FaultType;
494
495/*
496 * UTCL0RequestType enum
497 */
498
499typedef enum UTCL0RequestType {
500UTCL0_TYPE_NORMAL = 0x00000000,
501UTCL0_TYPE_SHOOTDOWN = 0x00000001,
502UTCL0_TYPE_BYPASS = 0x00000002,
503} UTCL0RequestType;
504
505/*
506 * UTCL1FaultType enum
507 */
508
509typedef enum UTCL1FaultType {
510UTCL1_XNACK_SUCCESS = 0x00000000,
511UTCL1_XNACK_RETRY = 0x00000001,
512UTCL1_XNACK_PRT = 0x00000002,
513UTCL1_XNACK_NO_RETRY = 0x00000003,
514} UTCL1FaultType;
515
516/*
517 * UTCL1RequestType enum
518 */
519
520typedef enum UTCL1RequestType {
521UTCL1_TYPE_NORMAL = 0x00000000,
522UTCL1_TYPE_SHOOTDOWN = 0x00000001,
523UTCL1_TYPE_BYPASS = 0x00000002,
524} UTCL1RequestType;
525
526/*
527 * VMEMCMD_RETURN_ORDER enum
528 */
529
530typedef enum VMEMCMD_RETURN_ORDER {
531VMEMCMD_RETURN_OUT_OF_ORDER = 0x00000000,
532VMEMCMD_RETURN_IN_ORDER = 0x00000001,
533VMEMCMD_RETURN_IN_ORDER_READ = 0x00000002,
534} VMEMCMD_RETURN_ORDER;
535
536/*
537 * WritePolicy enum
538 */
539
540typedef enum WritePolicy {
541CACHE_LRU_WR = 0x00000000,
542CACHE_STREAM = 0x00000001,
543CACHE_NOA_WR = 0x00000002,
544CACHE_BYPASS = 0x00000003,
545} WritePolicy;
546
547/*******************************************************
548 * CNVC_CFG Enums
549 *******************************************************/
550
551/*
552 * CNVC_BYPASS enum
553 */
554
555typedef enum CNVC_BYPASS {
556CNVC_BYPASS_DISABLE = 0x00000000,
557CNVC_BYPASS_EN = 0x00000001,
558} CNVC_BYPASS;
559
560/*
561 * CNVC_COEF_FORMAT_ENUM enum
562 */
563
564typedef enum CNVC_COEF_FORMAT_ENUM {
565CNVC_FIX_S2_13 = 0x00000000,
566CNVC_FIX_S3_12 = 0x00000001,
567} CNVC_COEF_FORMAT_ENUM;
568
569/*
570 * CNVC_ENABLE enum
571 */
572
573typedef enum CNVC_ENABLE {
574CNVC_DIS = 0x00000000,
575CNVC_EN = 0x00000001,
576} CNVC_ENABLE;
577
578/*
579 * CNVC_PENDING enum
580 */
581
582typedef enum CNVC_PENDING {
583CNVC_NOT_PENDING = 0x00000000,
584CNVC_YES_PENDING = 0x00000001,
585} CNVC_PENDING;
586
587/*
588 * COLOR_KEYER_MODE enum
589 */
590
591typedef enum COLOR_KEYER_MODE {
592FORCE_00 = 0x00000000,
593FORCE_FF = 0x00000001,
594RANGE_00 = 0x00000002,
595RANGE_FF = 0x00000003,
596} COLOR_KEYER_MODE;
597
598/*
599 * DENORM_TRUNCATE enum
600 */
601
602typedef enum DENORM_TRUNCATE {
603CNVC_ROUND = 0x00000000,
604CNVC_TRUNCATE = 0x00000001,
605} DENORM_TRUNCATE;
606
607/*
608 * FORMAT_CROSSBAR enum
609 */
610
611typedef enum FORMAT_CROSSBAR {
612FORMAT_CROSSBAR_R = 0x00000000,
613FORMAT_CROSSBAR_G = 0x00000001,
614FORMAT_CROSSBAR_B = 0x00000002,
615} FORMAT_CROSSBAR;
616
617/*
618 * PIX_EXPAND_MODE enum
619 */
620
621typedef enum PIX_EXPAND_MODE {
622PIX_DYNAMIC_EXPANSION = 0x00000000,
623PIX_ZERO_EXPANSION = 0x00000001,
624} PIX_EXPAND_MODE;
625
626/*
627 * PRE_CSC_MODE_ENUM enum
628 */
629
630typedef enum PRE_CSC_MODE_ENUM {
631PRE_CSC_BYPASS = 0x00000000,
632PRE_CSC_SET_A = 0x00000001,
633PRE_CSC_SET_B = 0x00000002,
634} PRE_CSC_MODE_ENUM;
635
636/*
637 * PRE_DEGAM_MODE enum
638 */
639
640typedef enum PRE_DEGAM_MODE {
641PRE_DEGAM_BYPASS = 0x00000000,
642PRE_DEGAM_ENABLE = 0x00000001,
643} PRE_DEGAM_MODE;
644
645/*
646 * PRE_DEGAM_SELECT enum
647 */
648
649typedef enum PRE_DEGAM_SELECT {
650PRE_DEGAM_SRGB = 0x00000000,
651PRE_DEGAM_GAMMA_22 = 0x00000001,
652PRE_DEGAM_GAMMA_24 = 0x00000002,
653PRE_DEGAM_GAMMA_26 = 0x00000003,
654PRE_DEGAM_BT2020 = 0x00000004,
655PRE_DEGAM_BT2100PQ = 0x00000005,
656PRE_DEGAM_BT2100HLG = 0x00000006,
657} PRE_DEGAM_SELECT;
658
659/*
660 * SURFACE_PIXEL_FORMAT enum
661 */
662
663typedef enum SURFACE_PIXEL_FORMAT {
664ARGB1555 = 0x00000001,
665RGBA5551 = 0x00000002,
666RGB565 = 0x00000003,
667BGR565 = 0x00000004,
668ARGB4444 = 0x00000005,
669RGBA4444 = 0x00000006,
670ARGB8888 = 0x00000008,
671RGBA8888 = 0x00000009,
672ARGB2101010 = 0x0000000a,
673RGBA1010102 = 0x0000000b,
674AYCrCb8888 = 0x0000000c,
675YCrCbA8888 = 0x0000000d,
676ACrYCb8888 = 0x0000000e,
677CrYCbA8888 = 0x0000000f,
678ARGB16161616_10MSB = 0x00000010,
679RGBA16161616_10MSB = 0x00000011,
680ARGB16161616_10LSB = 0x00000012,
681RGBA16161616_10LSB = 0x00000013,
682ARGB16161616_12MSB = 0x00000014,
683RGBA16161616_12MSB = 0x00000015,
684ARGB16161616_12LSB = 0x00000016,
685RGBA16161616_12LSB = 0x00000017,
686ARGB16161616_FLOAT = 0x00000018,
687RGBA16161616_FLOAT = 0x00000019,
688ARGB16161616_UNORM = 0x0000001a,
689RGBA16161616_UNORM = 0x0000001b,
690ARGB16161616_SNORM = 0x0000001c,
691RGBA16161616_SNORM = 0x0000001d,
692AYCrCb16161616_10MSB = 0x00000020,
693AYCrCb16161616_10LSB = 0x00000021,
694YCrCbA16161616_10MSB = 0x00000022,
695YCrCbA16161616_10LSB = 0x00000023,
696ACrYCb16161616_10MSB = 0x00000024,
697ACrYCb16161616_10LSB = 0x00000025,
698CrYCbA16161616_10MSB = 0x00000026,
699CrYCbA16161616_10LSB = 0x00000027,
700AYCrCb16161616_12MSB = 0x00000028,
701AYCrCb16161616_12LSB = 0x00000029,
702YCrCbA16161616_12MSB = 0x0000002a,
703YCrCbA16161616_12LSB = 0x0000002b,
704ACrYCb16161616_12MSB = 0x0000002c,
705ACrYCb16161616_12LSB = 0x0000002d,
706CrYCbA16161616_12MSB = 0x0000002e,
707CrYCbA16161616_12LSB = 0x0000002f,
708Y8_CrCb88_420_PLANAR = 0x00000040,
709Y8_CbCr88_420_PLANAR = 0x00000041,
710Y10_CrCb1010_420_PLANAR = 0x00000042,
711Y10_CbCr1010_420_PLANAR = 0x00000043,
712Y12_CrCb1212_420_PLANAR = 0x00000044,
713Y12_CbCr1212_420_PLANAR = 0x00000045,
714YCrYCb8888_422_PACKED = 0x00000048,
715YCbYCr8888_422_PACKED = 0x00000049,
716CrYCbY8888_422_PACKED = 0x0000004a,
717CbYCrY8888_422_PACKED = 0x0000004b,
718YCrYCb10101010_422_PACKED = 0x0000004c,
719YCbYCr10101010_422_PACKED = 0x0000004d,
720CrYCbY10101010_422_PACKED = 0x0000004e,
721CbYCrY10101010_422_PACKED = 0x0000004f,
722YCrYCb12121212_422_PACKED = 0x00000050,
723YCbYCr12121212_422_PACKED = 0x00000051,
724CrYCbY12121212_422_PACKED = 0x00000052,
725CbYCrY12121212_422_PACKED = 0x00000053,
726RGB111110_FIX = 0x00000070,
727BGR101111_FIX = 0x00000071,
728ACrYCb2101010 = 0x00000072,
729CrYCbA1010102 = 0x00000073,
730RGBE = 0x00000074,
731RGB111110_FLOAT = 0x00000076,
732BGR101111_FLOAT = 0x00000077,
733MONO_8 = 0x00000078,
734MONO_10MSB = 0x00000079,
735MONO_10LSB = 0x0000007a,
736MONO_12MSB = 0x0000007b,
737MONO_12LSB = 0x0000007c,
738MONO_16 = 0x0000007d,
739} SURFACE_PIXEL_FORMAT;
740
741/*
742 * XNORM enum
743 */
744
745typedef enum XNORM {
746XNORM_A = 0x00000000,
747XNORM_B = 0x00000001,
748} XNORM;
749
750/*******************************************************
751 * CNVC_CUR Enums
752 *******************************************************/
753
754/*
755 * CUR_ENABLE enum
756 */
757
758typedef enum CUR_ENABLE {
759CUR_DIS = 0x00000000,
760CUR_EN = 0x00000001,
761} CUR_ENABLE;
762
763/*
764 * CUR_EXPAND_MODE enum
765 */
766
767typedef enum CUR_EXPAND_MODE {
768CUR_DYNAMIC_EXPANSION = 0x00000000,
769CUR_ZERO_EXPANSION = 0x00000001,
770} CUR_EXPAND_MODE;
771
772/*
773 * CUR_INV_CLAMP enum
774 */
775
776typedef enum CUR_INV_CLAMP {
777CUR_CLAMP_DIS = 0x00000000,
778CUR_CLAMP_EN = 0x00000001,
779} CUR_INV_CLAMP;
780
781/*
782 * CUR_MODE enum
783 */
784
785typedef enum CUR_MODE {
786MONO_2BIT = 0x00000000,
787COLOR_24BIT_1BIT_AND = 0x00000001,
788COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002,
789COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003,
790COLOR_64BIT_FP_PREMULT = 0x00000004,
791COLOR_64BIT_FP_UNPREMULT = 0x00000005,
792} CUR_MODE;
793
794/*
795 * CUR_PENDING enum
796 */
797
798typedef enum CUR_PENDING {
799CUR_NOT_PENDING = 0x00000000,
800CUR_YES_PENDING = 0x00000001,
801} CUR_PENDING;
802
803/*
804 * CUR_ROM_EN enum
805 */
806
807typedef enum CUR_ROM_EN {
808CUR_FP_NO_ROM = 0x00000000,
809CUR_FP_USE_ROM = 0x00000001,
810} CUR_ROM_EN;
811
812/*******************************************************
813 * DSCL Enums
814 *******************************************************/
815
816/*
817 * COEF_RAM_SELECT_RD enum
818 */
819
820typedef enum COEF_RAM_SELECT_RD {
821COEF_RAM_SELECT_BACK = 0x00000000,
822COEF_RAM_SELECT_CURRENT = 0x00000001,
823} COEF_RAM_SELECT_RD;
824
825/*
826 * DSCL_MODE_SEL enum
827 */
828
829typedef enum DSCL_MODE_SEL {
830DSCL_MODE_SCALING_444_BYPASS = 0x00000000,
831DSCL_MODE_SCALING_444_RGB_ENABLE = 0x00000001,
832DSCL_MODE_SCALING_444_YCBCR_ENABLE = 0x00000002,
833DSCL_MODE_SCALING_YCBCR_ENABLE = 0x00000003,
834DSCL_MODE_LUMA_SCALING_BYPASS = 0x00000004,
835DSCL_MODE_CHROMA_SCALING_BYPASS = 0x00000005,
836DSCL_MODE_DSCL_BYPASS = 0x00000006,
837} DSCL_MODE_SEL;
838
839/*
840 * LB_ALPHA_EN enum
841 */
842
843typedef enum LB_ALPHA_EN {
844LB_ALPHA_DISABLE = 0x00000000,
845LB_ALPHA_ENABLE = 0x00000001,
846} LB_ALPHA_EN;
847
848/*
849 * LB_INTERLEAVE_EN enum
850 */
851
852typedef enum LB_INTERLEAVE_EN {
853LB_INTERLEAVE_DISABLE = 0x00000000,
854LB_INTERLEAVE_ENABLE = 0x00000001,
855} LB_INTERLEAVE_EN;
856
857/*
858 * LB_MEMORY_CONFIG enum
859 */
860
861typedef enum LB_MEMORY_CONFIG {
862LB_MEMORY_CONFIG_0 = 0x00000000,
863LB_MEMORY_CONFIG_1 = 0x00000001,
864LB_MEMORY_CONFIG_2 = 0x00000002,
865LB_MEMORY_CONFIG_3 = 0x00000003,
866} LB_MEMORY_CONFIG;
867
868/*
869 * OBUF_BYPASS_SEL enum
870 */
871
872typedef enum OBUF_BYPASS_SEL {
873OBUF_BYPASS_DIS = 0x00000000,
874OBUF_BYPASS_EN = 0x00000001,
875} OBUF_BYPASS_SEL;
876
877/*
878 * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum
879 */
880
881typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL {
882OBUF_FULL_RECOUT = 0x00000000,
883OBUF_HALF_RECOUT = 0x00000001,
884} OBUF_IS_HALF_RECOUT_WIDTH_SEL;
885
886/*
887 * OBUF_USE_FULL_BUFFER_SEL enum
888 */
889
890typedef enum OBUF_USE_FULL_BUFFER_SEL {
891OBUF_RECOUT = 0x00000000,
892OBUF_FULL = 0x00000001,
893} OBUF_USE_FULL_BUFFER_SEL;
894
895/*
896 * SCL_2TAP_HARDCODE enum
897 */
898
899typedef enum SCL_2TAP_HARDCODE {
900SCL_COEF_2TAP_HARDCODE_OFF = 0x00000000,
901SCL_COEF_2TAP_HARDCODE_ON = 0x00000001,
902} SCL_2TAP_HARDCODE;
903
904/*
905 * SCL_ALPHA_COEF enum
906 */
907
908typedef enum SCL_ALPHA_COEF {
909SCL_ALPHA_COEF_FIRST = 0x00000000,
910SCL_ALPHA_COEF_SECOND = 0x00000001,
911} SCL_ALPHA_COEF;
912
913/*
914 * SCL_AUTOCAL_MODE enum
915 */
916
917typedef enum SCL_AUTOCAL_MODE {
918AUTOCAL_MODE_OFF = 0x00000000,
919AUTOCAL_MODE_AUTOSCALE = 0x00000001,
920AUTOCAL_MODE_AUTOCENTER = 0x00000002,
921AUTOCAL_MODE_AUTOREPLICATE = 0x00000003,
922} SCL_AUTOCAL_MODE;
923
924/*
925 * SCL_BOUNDARY enum
926 */
927
928typedef enum SCL_BOUNDARY {
929SCL_BOUNDARY_EDGE = 0x00000000,
930SCL_BOUNDARY_BLACK = 0x00000001,
931} SCL_BOUNDARY;
932
933/*
934 * SCL_CHROMA_COEF enum
935 */
936
937typedef enum SCL_CHROMA_COEF {
938SCL_CHROMA_COEF_FIRST = 0x00000000,
939SCL_CHROMA_COEF_SECOND = 0x00000001,
940} SCL_CHROMA_COEF;
941
942/*
943 * SCL_COEF_FILTER_TYPE_SEL enum
944 */
945
946typedef enum SCL_COEF_FILTER_TYPE_SEL {
947SCL_COEF_LUMA_VERT_FILTER = 0x00000000,
948SCL_COEF_LUMA_HORZ_FILTER = 0x00000001,
949SCL_COEF_CHROMA_VERT_FILTER = 0x00000002,
950SCL_COEF_CHROMA_HORZ_FILTER = 0x00000003,
951} SCL_COEF_FILTER_TYPE_SEL;
952
953/*
954 * SCL_COEF_RAM_SEL enum
955 */
956
957typedef enum SCL_COEF_RAM_SEL {
958SCL_COEF_RAM_SEL_0 = 0x00000000,
959SCL_COEF_RAM_SEL_1 = 0x00000001,
960} SCL_COEF_RAM_SEL;
961
962/*
963 * SCL_SHARP_EN enum
964 */
965
966typedef enum SCL_SHARP_EN {
967SCL_SHARP_DISABLE = 0x00000000,
968SCL_SHARP_ENABLE = 0x00000001,
969} SCL_SHARP_EN;
970
971/*******************************************************
972 * CM Enums
973 *******************************************************/
974
975/*
976 * CMC_3DLUT_30BIT_ENUM enum
977 */
978
979typedef enum CMC_3DLUT_30BIT_ENUM {
980CMC_3DLUT_36BIT = 0x00000000,
981CMC_3DLUT_30BIT = 0x00000001,
982} CMC_3DLUT_30BIT_ENUM;
983
984/*
985 * CMC_3DLUT_RAM_SEL enum
986 */
987
988typedef enum CMC_3DLUT_RAM_SEL {
989CMC_RAM0_ACCESS = 0x00000000,
990CMC_RAM1_ACCESS = 0x00000001,
991CMC_RAM2_ACCESS = 0x00000002,
992CMC_RAM3_ACCESS = 0x00000003,
993} CMC_3DLUT_RAM_SEL;
994
995/*
996 * CMC_3DLUT_SIZE_ENUM enum
997 */
998
999typedef enum CMC_3DLUT_SIZE_ENUM {
1000CMC_3DLUT_17CUBE = 0x00000000,
1001CMC_3DLUT_9CUBE = 0x00000001,
1002} CMC_3DLUT_SIZE_ENUM;
1003
1004/*
1005 * CMC_LUT_2_CONFIG_ENUM enum
1006 */
1007
1008typedef enum CMC_LUT_2_CONFIG_ENUM {
1009CMC_LUT_2CFG_NO_MEMORY = 0x00000000,
1010CMC_LUT_2CFG_MEMORY_A = 0x00000001,
1011CMC_LUT_2CFG_MEMORY_B = 0x00000002,
1012} CMC_LUT_2_CONFIG_ENUM;
1013
1014/*
1015 * CMC_LUT_2_MODE_ENUM enum
1016 */
1017
1018typedef enum CMC_LUT_2_MODE_ENUM {
1019CMC_LUT_2_MODE_BYPASS = 0x00000000,
1020CMC_LUT_2_MODE_RAMA_LUT = 0x00000001,
1021CMC_LUT_2_MODE_RAMB_LUT = 0x00000002,
1022} CMC_LUT_2_MODE_ENUM;
1023
1024/*
1025 * CMC_LUT_NUM_SEG enum
1026 */
1027
1028typedef enum CMC_LUT_NUM_SEG {
1029CMC_SEGMENTS_1 = 0x00000000,
1030CMC_SEGMENTS_2 = 0x00000001,
1031CMC_SEGMENTS_4 = 0x00000002,
1032CMC_SEGMENTS_8 = 0x00000003,
1033CMC_SEGMENTS_16 = 0x00000004,
1034CMC_SEGMENTS_32 = 0x00000005,
1035CMC_SEGMENTS_64 = 0x00000006,
1036CMC_SEGMENTS_128 = 0x00000007,
1037} CMC_LUT_NUM_SEG;
1038
1039/*
1040 * CMC_LUT_RAM_SEL enum
1041 */
1042
1043typedef enum CMC_LUT_RAM_SEL {
1044CMC_RAMA_ACCESS = 0x00000000,
1045CMC_RAMB_ACCESS = 0x00000001,
1046} CMC_LUT_RAM_SEL;
1047
1048/*
1049 * CM_BYPASS enum
1050 */
1051
1052typedef enum CM_BYPASS {
1053NON_BYPASS = 0x00000000,
1054BYPASS_EN = 0x00000001,
1055} CM_BYPASS;
1056
1057/*
1058 * CM_COEF_FORMAT_ENUM enum
1059 */
1060
1061typedef enum CM_COEF_FORMAT_ENUM {
1062FIX_S2_13 = 0x00000000,
1063FIX_S3_12 = 0x00000001,
1064} CM_COEF_FORMAT_ENUM;
1065
1066/*
1067 * CM_DATA_SIGNED enum
1068 */
1069
1070typedef enum CM_DATA_SIGNED {
1071UNSIGNED = 0x00000000,
1072SIGNED = 0x00000001,
1073} CM_DATA_SIGNED;
1074
1075/*
1076 * CM_EN enum
1077 */
1078
1079typedef enum CM_EN {
1080CM_DISABLE = 0x00000000,
1081CM_ENABLE = 0x00000001,
1082} CM_EN;
1083
1084/*
1085 * CM_GAMMA_LUT_MODE_ENUM enum
1086 */
1087
1088typedef enum CM_GAMMA_LUT_MODE_ENUM {
1089BYPASS = 0x00000000,
1090RESERVED_1 = 0x00000001,
1091RAM_LUT = 0x00000002,
1092RESERVED_3 = 0x00000003,
1093} CM_GAMMA_LUT_MODE_ENUM;
1094
1095/*
1096 * CM_GAMMA_LUT_PWL_DISABLE_ENUM enum
1097 */
1098
1099typedef enum CM_GAMMA_LUT_PWL_DISABLE_ENUM {
1100ENABLE_PWL = 0x00000000,
1101DISABLE_PWL = 0x00000001,
1102} CM_GAMMA_LUT_PWL_DISABLE_ENUM;
1103
1104/*
1105 * CM_GAMMA_LUT_SEL_ENUM enum
1106 */
1107
1108typedef enum CM_GAMMA_LUT_SEL_ENUM {
1109RAMA = 0x00000000,
1110RAMB = 0x00000001,
1111} CM_GAMMA_LUT_SEL_ENUM;
1112
1113/*
1114 * CM_GAMUT_REMAP_MODE_ENUM enum
1115 */
1116
1117typedef enum CM_GAMUT_REMAP_MODE_ENUM {
1118BYPASS_GAMUT = 0x00000000,
1119GAMUT_COEF = 0x00000001,
1120GAMUT_COEF_B = 0x00000002,
1121} CM_GAMUT_REMAP_MODE_ENUM;
1122
1123/*
1124 * CM_LUT_2_CONFIG_ENUM enum
1125 */
1126
1127typedef enum CM_LUT_2_CONFIG_ENUM {
1128LUT_2CFG_NO_MEMORY = 0x00000000,
1129LUT_2CFG_MEMORY_A = 0x00000001,
1130LUT_2CFG_MEMORY_B = 0x00000002,
1131} CM_LUT_2_CONFIG_ENUM;
1132
1133/*
1134 * CM_LUT_2_MODE_ENUM enum
1135 */
1136
1137typedef enum CM_LUT_2_MODE_ENUM {
1138LUT_2_MODE_BYPASS = 0x00000000,
1139LUT_2_MODE_RAMA_LUT = 0x00000001,
1140LUT_2_MODE_RAMB_LUT = 0x00000002,
1141} CM_LUT_2_MODE_ENUM;
1142
1143/*
1144 * CM_LUT_4_CONFIG_ENUM enum
1145 */
1146
1147typedef enum CM_LUT_4_CONFIG_ENUM {
1148LUT_4CFG_NO_MEMORY = 0x00000000,
1149LUT_4CFG_ROM_A = 0x00000001,
1150LUT_4CFG_ROM_B = 0x00000002,
1151LUT_4CFG_MEMORY_A = 0x00000003,
1152LUT_4CFG_MEMORY_B = 0x00000004,
1153} CM_LUT_4_CONFIG_ENUM;
1154
1155/*
1156 * CM_LUT_4_MODE_ENUM enum
1157 */
1158
1159typedef enum CM_LUT_4_MODE_ENUM {
1160LUT_4_MODE_BYPASS = 0x00000000,
1161LUT_4_MODE_ROMA_LUT = 0x00000001,
1162LUT_4_MODE_ROMB_LUT = 0x00000002,
1163LUT_4_MODE_RAMA_LUT = 0x00000003,
1164LUT_4_MODE_RAMB_LUT = 0x00000004,
1165} CM_LUT_4_MODE_ENUM;
1166
1167/*
1168 * CM_LUT_CONFIG_MODE enum
1169 */
1170
1171typedef enum CM_LUT_CONFIG_MODE {
1172DIFFERENT_RGB = 0x00000000,
1173ALL_USE_R = 0x00000001,
1174} CM_LUT_CONFIG_MODE;
1175
1176/*
1177 * CM_LUT_NUM_SEG enum
1178 */
1179
1180typedef enum CM_LUT_NUM_SEG {
1181SEGMENTS_1 = 0x00000000,
1182SEGMENTS_2 = 0x00000001,
1183SEGMENTS_4 = 0x00000002,
1184SEGMENTS_8 = 0x00000003,
1185SEGMENTS_16 = 0x00000004,
1186SEGMENTS_32 = 0x00000005,
1187SEGMENTS_64 = 0x00000006,
1188SEGMENTS_128 = 0x00000007,
1189} CM_LUT_NUM_SEG;
1190
1191/*
1192 * CM_LUT_RAM_SEL enum
1193 */
1194
1195typedef enum CM_LUT_RAM_SEL {
1196RAMA_ACCESS = 0x00000000,
1197RAMB_ACCESS = 0x00000001,
1198} CM_LUT_RAM_SEL;
1199
1200/*
1201 * CM_LUT_READ_COLOR_SEL enum
1202 */
1203
1204typedef enum CM_LUT_READ_COLOR_SEL {
1205BLUE_LUT = 0x00000000,
1206GREEN_LUT = 0x00000001,
1207RED_LUT = 0x00000002,
1208} CM_LUT_READ_COLOR_SEL;
1209
1210/*
1211 * CM_LUT_READ_DBG enum
1212 */
1213
1214typedef enum CM_LUT_READ_DBG {
1215DISABLE_DEBUG = 0x00000000,
1216ENABLE_DEBUG = 0x00000001,
1217} CM_LUT_READ_DBG;
1218
1219/*
1220 * CM_PENDING enum
1221 */
1222
1223typedef enum CM_PENDING {
1224CM_NOT_PENDING = 0x00000000,
1225CM_YES_PENDING = 0x00000001,
1226} CM_PENDING;
1227
1228/*
1229 * CM_POST_CSC_MODE_ENUM enum
1230 */
1231
1232typedef enum CM_POST_CSC_MODE_ENUM {
1233BYPASS_POST_CSC = 0x00000000,
1234COEF_POST_CSC = 0x00000001,
1235COEF_POST_CSC_B = 0x00000002,
1236} CM_POST_CSC_MODE_ENUM;
1237
1238/*
1239 * CM_WRITE_BASE_ONLY enum
1240 */
1241
1242typedef enum CM_WRITE_BASE_ONLY {
1243WRITE_BOTH = 0x00000000,
1244WRITE_BASE_ONLY = 0x00000001,
1245} CM_WRITE_BASE_ONLY;
1246
1247/*******************************************************
1248 * DPP_TOP Enums
1249 *******************************************************/
1250
1251/*
1252 * CRC_CUR_SEL enum
1253 */
1254
1255typedef enum CRC_CUR_SEL {
1256CRC_CUR_0 = 0x00000000,
1257CRC_CUR_1 = 0x00000001,
1258} CRC_CUR_SEL;
1259
1260/*
1261 * CRC_INTERLACE_SEL enum
1262 */
1263
1264typedef enum CRC_INTERLACE_SEL {
1265CRC_INTERLACE_0 = 0x00000000,
1266CRC_INTERLACE_1 = 0x00000001,
1267CRC_INTERLACE_2 = 0x00000002,
1268CRC_INTERLACE_3 = 0x00000003,
1269} CRC_INTERLACE_SEL;
1270
1271/*
1272 * CRC_IN_CUR_SEL enum
1273 */
1274
1275typedef enum CRC_IN_CUR_SEL {
1276CRC_IN_CUR_0 = 0x00000000,
1277CRC_IN_CUR_1 = 0x00000001,
1278CRC_IN_CUR_2 = 0x00000002,
1279CRC_IN_CUR_3 = 0x00000003,
1280} CRC_IN_CUR_SEL;
1281
1282/*
1283 * CRC_IN_PIX_SEL enum
1284 */
1285
1286typedef enum CRC_IN_PIX_SEL {
1287CRC_IN_PIX_0 = 0x00000000,
1288CRC_IN_PIX_1 = 0x00000001,
1289CRC_IN_PIX_2 = 0x00000002,
1290CRC_IN_PIX_3 = 0x00000003,
1291CRC_IN_PIX_4 = 0x00000004,
1292CRC_IN_PIX_5 = 0x00000005,
1293CRC_IN_PIX_6 = 0x00000006,
1294CRC_IN_PIX_7 = 0x00000007,
1295} CRC_IN_PIX_SEL;
1296
1297/*
1298 * CRC_SRC_SEL enum
1299 */
1300
1301typedef enum CRC_SRC_SEL {
1302CRC_SRC_0 = 0x00000000,
1303CRC_SRC_1 = 0x00000001,
1304CRC_SRC_2 = 0x00000002,
1305CRC_SRC_3 = 0x00000003,
1306} CRC_SRC_SEL;
1307
1308/*
1309 * CRC_STEREO_SEL enum
1310 */
1311
1312typedef enum CRC_STEREO_SEL {
1313CRC_STEREO_0 = 0x00000000,
1314CRC_STEREO_1 = 0x00000001,
1315CRC_STEREO_2 = 0x00000002,
1316CRC_STEREO_3 = 0x00000003,
1317} CRC_STEREO_SEL;
1318
1319/*
1320 * TEST_CLK_SEL enum
1321 */
1322
1323typedef enum TEST_CLK_SEL {
1324TEST_CLK_SEL_0 = 0x00000000,
1325TEST_CLK_SEL_1 = 0x00000001,
1326TEST_CLK_SEL_2 = 0x00000002,
1327TEST_CLK_SEL_3 = 0x00000003,
1328TEST_CLK_SEL_4 = 0x00000004,
1329TEST_CLK_SEL_5 = 0x00000005,
1330TEST_CLK_SEL_6 = 0x00000006,
1331TEST_CLK_SEL_7 = 0x00000007,
1332} TEST_CLK_SEL;
1333
1334/*******************************************************
1335 * DC_PERFMON Enums
1336 *******************************************************/
1337
1338/*
1339 * PERFCOUNTER_ACTIVE enum
1340 */
1341
1342typedef enum PERFCOUNTER_ACTIVE {
1343PERFCOUNTER_IS_IDLE = 0x00000000,
1344PERFCOUNTER_IS_ACTIVE = 0x00000001,
1345} PERFCOUNTER_ACTIVE;
1346
1347/*
1348 * PERFCOUNTER_CNT0_STATE enum
1349 */
1350
1351typedef enum PERFCOUNTER_CNT0_STATE {
1352PERFCOUNTER_CNT0_STATE_RESET = 0x00000000,
1353PERFCOUNTER_CNT0_STATE_START = 0x00000001,
1354PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002,
1355PERFCOUNTER_CNT0_STATE_HW = 0x00000003,
1356} PERFCOUNTER_CNT0_STATE;
1357
1358/*
1359 * PERFCOUNTER_CNT1_STATE enum
1360 */
1361
1362typedef enum PERFCOUNTER_CNT1_STATE {
1363PERFCOUNTER_CNT1_STATE_RESET = 0x00000000,
1364PERFCOUNTER_CNT1_STATE_START = 0x00000001,
1365PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002,
1366PERFCOUNTER_CNT1_STATE_HW = 0x00000003,
1367} PERFCOUNTER_CNT1_STATE;
1368
1369/*
1370 * PERFCOUNTER_CNT2_STATE enum
1371 */
1372
1373typedef enum PERFCOUNTER_CNT2_STATE {
1374PERFCOUNTER_CNT2_STATE_RESET = 0x00000000,
1375PERFCOUNTER_CNT2_STATE_START = 0x00000001,
1376PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002,
1377PERFCOUNTER_CNT2_STATE_HW = 0x00000003,
1378} PERFCOUNTER_CNT2_STATE;
1379
1380/*
1381 * PERFCOUNTER_CNT3_STATE enum
1382 */
1383
1384typedef enum PERFCOUNTER_CNT3_STATE {
1385PERFCOUNTER_CNT3_STATE_RESET = 0x00000000,
1386PERFCOUNTER_CNT3_STATE_START = 0x00000001,
1387PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002,
1388PERFCOUNTER_CNT3_STATE_HW = 0x00000003,
1389} PERFCOUNTER_CNT3_STATE;
1390
1391/*
1392 * PERFCOUNTER_CNT4_STATE enum
1393 */
1394
1395typedef enum PERFCOUNTER_CNT4_STATE {
1396PERFCOUNTER_CNT4_STATE_RESET = 0x00000000,
1397PERFCOUNTER_CNT4_STATE_START = 0x00000001,
1398PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002,
1399PERFCOUNTER_CNT4_STATE_HW = 0x00000003,
1400} PERFCOUNTER_CNT4_STATE;
1401
1402/*
1403 * PERFCOUNTER_CNT5_STATE enum
1404 */
1405
1406typedef enum PERFCOUNTER_CNT5_STATE {
1407PERFCOUNTER_CNT5_STATE_RESET = 0x00000000,
1408PERFCOUNTER_CNT5_STATE_START = 0x00000001,
1409PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002,
1410PERFCOUNTER_CNT5_STATE_HW = 0x00000003,
1411} PERFCOUNTER_CNT5_STATE;
1412
1413/*
1414 * PERFCOUNTER_CNT6_STATE enum
1415 */
1416
1417typedef enum PERFCOUNTER_CNT6_STATE {
1418PERFCOUNTER_CNT6_STATE_RESET = 0x00000000,
1419PERFCOUNTER_CNT6_STATE_START = 0x00000001,
1420PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002,
1421PERFCOUNTER_CNT6_STATE_HW = 0x00000003,
1422} PERFCOUNTER_CNT6_STATE;
1423
1424/*
1425 * PERFCOUNTER_CNT7_STATE enum
1426 */
1427
1428typedef enum PERFCOUNTER_CNT7_STATE {
1429PERFCOUNTER_CNT7_STATE_RESET = 0x00000000,
1430PERFCOUNTER_CNT7_STATE_START = 0x00000001,
1431PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002,
1432PERFCOUNTER_CNT7_STATE_HW = 0x00000003,
1433} PERFCOUNTER_CNT7_STATE;
1434
1435/*
1436 * PERFCOUNTER_CNTL_SEL enum
1437 */
1438
1439typedef enum PERFCOUNTER_CNTL_SEL {
1440PERFCOUNTER_CNTL_SEL_0 = 0x00000000,
1441PERFCOUNTER_CNTL_SEL_1 = 0x00000001,
1442PERFCOUNTER_CNTL_SEL_2 = 0x00000002,
1443PERFCOUNTER_CNTL_SEL_3 = 0x00000003,
1444PERFCOUNTER_CNTL_SEL_4 = 0x00000004,
1445PERFCOUNTER_CNTL_SEL_5 = 0x00000005,
1446PERFCOUNTER_CNTL_SEL_6 = 0x00000006,
1447PERFCOUNTER_CNTL_SEL_7 = 0x00000007,
1448} PERFCOUNTER_CNTL_SEL;
1449
1450/*
1451 * PERFCOUNTER_CNTOFF_START_DIS enum
1452 */
1453
1454typedef enum PERFCOUNTER_CNTOFF_START_DIS {
1455PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000,
1456PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001,
1457} PERFCOUNTER_CNTOFF_START_DIS;
1458
1459/*
1460 * PERFCOUNTER_COUNTED_VALUE_TYPE enum
1461 */
1462
1463typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
1464PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000,
1465PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001,
1466PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002,
1467} PERFCOUNTER_COUNTED_VALUE_TYPE;
1468
1469/*
1470 * PERFCOUNTER_CVALUE_SEL enum
1471 */
1472
1473typedef enum PERFCOUNTER_CVALUE_SEL {
1474PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000,
1475PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001,
1476PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002,
1477PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003,
1478PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004,
1479PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005,
1480PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006,
1481PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007,
1482} PERFCOUNTER_CVALUE_SEL;
1483
1484/*
1485 * PERFCOUNTER_HW_CNTL_SEL enum
1486 */
1487
1488typedef enum PERFCOUNTER_HW_CNTL_SEL {
1489PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000,
1490PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001,
1491} PERFCOUNTER_HW_CNTL_SEL;
1492
1493/*
1494 * PERFCOUNTER_HW_STOP1_SEL enum
1495 */
1496
1497typedef enum PERFCOUNTER_HW_STOP1_SEL {
1498PERFCOUNTER_HW_STOP1_0 = 0x00000000,
1499PERFCOUNTER_HW_STOP1_1 = 0x00000001,
1500} PERFCOUNTER_HW_STOP1_SEL;
1501
1502/*
1503 * PERFCOUNTER_HW_STOP2_SEL enum
1504 */
1505
1506typedef enum PERFCOUNTER_HW_STOP2_SEL {
1507PERFCOUNTER_HW_STOP2_0 = 0x00000000,
1508PERFCOUNTER_HW_STOP2_1 = 0x00000001,
1509} PERFCOUNTER_HW_STOP2_SEL;
1510
1511/*
1512 * PERFCOUNTER_INC_MODE enum
1513 */
1514
1515typedef enum PERFCOUNTER_INC_MODE {
1516PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000,
1517PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001,
1518PERFCOUNTER_INC_MODE_LSB = 0x00000002,
1519PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003,
1520PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004,
1521} PERFCOUNTER_INC_MODE;
1522
1523/*
1524 * PERFCOUNTER_INT_EN enum
1525 */
1526
1527typedef enum PERFCOUNTER_INT_EN {
1528PERFCOUNTER_INT_DISABLE = 0x00000000,
1529PERFCOUNTER_INT_ENABLE = 0x00000001,
1530} PERFCOUNTER_INT_EN;
1531
1532/*
1533 * PERFCOUNTER_INT_TYPE enum
1534 */
1535
1536typedef enum PERFCOUNTER_INT_TYPE {
1537PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000,
1538PERFCOUNTER_INT_TYPE_PULSE = 0x00000001,
1539} PERFCOUNTER_INT_TYPE;
1540
1541/*
1542 * PERFCOUNTER_OFF_MASK enum
1543 */
1544
1545typedef enum PERFCOUNTER_OFF_MASK {
1546PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000,
1547PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001,
1548} PERFCOUNTER_OFF_MASK;
1549
1550/*
1551 * PERFCOUNTER_RESTART_EN enum
1552 */
1553
1554typedef enum PERFCOUNTER_RESTART_EN {
1555PERFCOUNTER_RESTART_DISABLE = 0x00000000,
1556PERFCOUNTER_RESTART_ENABLE = 0x00000001,
1557} PERFCOUNTER_RESTART_EN;
1558
1559/*
1560 * PERFCOUNTER_RUNEN_MODE enum
1561 */
1562
1563typedef enum PERFCOUNTER_RUNEN_MODE {
1564PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000,
1565PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001,
1566} PERFCOUNTER_RUNEN_MODE;
1567
1568/*
1569 * PERFCOUNTER_STATE_SEL0 enum
1570 */
1571
1572typedef enum PERFCOUNTER_STATE_SEL0 {
1573PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000,
1574PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001,
1575} PERFCOUNTER_STATE_SEL0;
1576
1577/*
1578 * PERFCOUNTER_STATE_SEL1 enum
1579 */
1580
1581typedef enum PERFCOUNTER_STATE_SEL1 {
1582PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000,
1583PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001,
1584} PERFCOUNTER_STATE_SEL1;
1585
1586/*
1587 * PERFCOUNTER_STATE_SEL2 enum
1588 */
1589
1590typedef enum PERFCOUNTER_STATE_SEL2 {
1591PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000,
1592PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001,
1593} PERFCOUNTER_STATE_SEL2;
1594
1595/*
1596 * PERFCOUNTER_STATE_SEL3 enum
1597 */
1598
1599typedef enum PERFCOUNTER_STATE_SEL3 {
1600PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000,
1601PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001,
1602} PERFCOUNTER_STATE_SEL3;
1603
1604/*
1605 * PERFCOUNTER_STATE_SEL4 enum
1606 */
1607
1608typedef enum PERFCOUNTER_STATE_SEL4 {
1609PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000,
1610PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001,
1611} PERFCOUNTER_STATE_SEL4;
1612
1613/*
1614 * PERFCOUNTER_STATE_SEL5 enum
1615 */
1616
1617typedef enum PERFCOUNTER_STATE_SEL5 {
1618PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000,
1619PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001,
1620} PERFCOUNTER_STATE_SEL5;
1621
1622/*
1623 * PERFCOUNTER_STATE_SEL6 enum
1624 */
1625
1626typedef enum PERFCOUNTER_STATE_SEL6 {
1627PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000,
1628PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001,
1629} PERFCOUNTER_STATE_SEL6;
1630
1631/*
1632 * PERFCOUNTER_STATE_SEL7 enum
1633 */
1634
1635typedef enum PERFCOUNTER_STATE_SEL7 {
1636PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000,
1637PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001,
1638} PERFCOUNTER_STATE_SEL7;
1639
1640/*
1641 * PERFMON_CNTOFF_AND_OR enum
1642 */
1643
1644typedef enum PERFMON_CNTOFF_AND_OR {
1645PERFMON_CNTOFF_OR = 0x00000000,
1646PERFMON_CNTOFF_AND = 0x00000001,
1647} PERFMON_CNTOFF_AND_OR;
1648
1649/*
1650 * PERFMON_CNTOFF_INT_EN enum
1651 */
1652
1653typedef enum PERFMON_CNTOFF_INT_EN {
1654PERFMON_CNTOFF_INT_DISABLE = 0x00000000,
1655PERFMON_CNTOFF_INT_ENABLE = 0x00000001,
1656} PERFMON_CNTOFF_INT_EN;
1657
1658/*
1659 * PERFMON_CNTOFF_INT_TYPE enum
1660 */
1661
1662typedef enum PERFMON_CNTOFF_INT_TYPE {
1663PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000,
1664PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001,
1665} PERFMON_CNTOFF_INT_TYPE;
1666
1667/*
1668 * PERFMON_STATE enum
1669 */
1670
1671typedef enum PERFMON_STATE {
1672PERFMON_STATE_RESET = 0x00000000,
1673PERFMON_STATE_START = 0x00000001,
1674PERFMON_STATE_FREEZE = 0x00000002,
1675PERFMON_STATE_HW = 0x00000003,
1676} PERFMON_STATE;
1677
1678/*******************************************************
1679 * HUBP Enums
1680 *******************************************************/
1681
1682/*
1683 * BIGK_FRAGMENT_SIZE enum
1684 */
1685
1686typedef enum BIGK_FRAGMENT_SIZE {
1687VM_PG_SIZE_4KB = 0x00000000,
1688VM_PG_SIZE_8KB = 0x00000001,
1689VM_PG_SIZE_16KB = 0x00000002,
1690VM_PG_SIZE_32KB = 0x00000003,
1691VM_PG_SIZE_64KB = 0x00000004,
1692VM_PG_SIZE_128KB = 0x00000005,
1693VM_PG_SIZE_256KB = 0x00000006,
1694VM_PG_SIZE_512KB = 0x00000007,
1695VM_PG_SIZE_1024KB = 0x00000008,
1696VM_PG_SIZE_2048KB = 0x00000009,
1697} BIGK_FRAGMENT_SIZE;
1698
1699/*
1700 * CHUNK_SIZE enum
1701 */
1702
1703typedef enum CHUNK_SIZE {
1704CHUNK_SIZE_1KB = 0x00000000,
1705CHUNK_SIZE_2KB = 0x00000001,
1706CHUNK_SIZE_4KB = 0x00000002,
1707CHUNK_SIZE_8KB = 0x00000003,
1708CHUNK_SIZE_16KB = 0x00000004,
1709CHUNK_SIZE_32KB = 0x00000005,
1710CHUNK_SIZE_64KB = 0x00000006,
1711} CHUNK_SIZE;
1712
1713/*
1714 * COMPAT_LEVEL enum
1715 */
1716
1717typedef enum COMPAT_LEVEL {
1718ADDR_GEN_ZERO = 0x00000000,
1719ADDR_GEN_ONE = 0x00000001,
1720ADDR_GEN_TWO = 0x00000002,
1721ADDR_RESERVED = 0x00000003,
1722} COMPAT_LEVEL;
1723
1724/*
1725 * DPTE_GROUP_SIZE enum
1726 */
1727
1728typedef enum DPTE_GROUP_SIZE {
1729DPTE_GROUP_SIZE_64B = 0x00000000,
1730DPTE_GROUP_SIZE_128B = 0x00000001,
1731DPTE_GROUP_SIZE_256B = 0x00000002,
1732DPTE_GROUP_SIZE_512B = 0x00000003,
1733DPTE_GROUP_SIZE_1024B = 0x00000004,
1734DPTE_GROUP_SIZE_2048B = 0x00000005,
1735} DPTE_GROUP_SIZE;
1736
1737/*
1738 * FORCE_ONE_ROW_FOR_FRAME enum
1739 */
1740
1741typedef enum FORCE_ONE_ROW_FOR_FRAME {
1742FORCE_ONE_ROW_FOR_FRAME_0 = 0x00000000,
1743FORCE_ONE_ROW_FOR_FRAME_1 = 0x00000001,
1744} FORCE_ONE_ROW_FOR_FRAME;
1745
1746/*
1747 * HUBP_BLANK_EN enum
1748 */
1749
1750typedef enum HUBP_BLANK_EN {
1751HUBP_BLANK_SW_DEASSERT = 0x00000000,
1752HUBP_BLANK_SW_ASSERT = 0x00000001,
1753} HUBP_BLANK_EN;
1754
1755/*
1756 * HUBP_IN_BLANK enum
1757 */
1758
1759typedef enum HUBP_IN_BLANK {
1760HUBP_IN_ACTIVE = 0x00000000,
1761HUBP_IN_VBLANK = 0x00000001,
1762} HUBP_IN_BLANK;
1763
1764/*
1765 * HUBP_MEASURE_WIN_MODE_DCFCLK enum
1766 */
1767
1768typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK {
1769HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0x00000000,
1770HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 0x00000001,
1771HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 0x00000002,
1772HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 0x00000003,
1773} HUBP_MEASURE_WIN_MODE_DCFCLK;
1774
1775/*
1776 * HUBP_NO_OUTSTANDING_REQ enum
1777 */
1778
1779typedef enum HUBP_NO_OUTSTANDING_REQ {
1780OUTSTANDING_REQ = 0x00000000,
1781NO_OUTSTANDING_REQ = 0x00000001,
1782} HUBP_NO_OUTSTANDING_REQ;
1783
1784/*
1785 * HUBP_SOFT_RESET enum
1786 */
1787
1788typedef enum HUBP_SOFT_RESET {
1789HUBP_SOFT_RESET_ON = 0x00000000,
1790HUBP_SOFT_RESET_OFF = 0x00000001,
1791} HUBP_SOFT_RESET;
1792
1793/*
1794 * HUBP_TTU_DISABLE enum
1795 */
1796
1797typedef enum HUBP_TTU_DISABLE {
1798HUBP_TTU_ENABLED = 0x00000000,
1799HUBP_TTU_DISABLED = 0x00000001,
1800} HUBP_TTU_DISABLE;
1801
1802/*
1803 * HUBP_VREADY_AT_OR_AFTER_VSYNC enum
1804 */
1805
1806typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC {
1807VREADY_BEFORE_VSYNC = 0x00000000,
1808VREADY_AT_OR_AFTER_VSYNC = 0x00000001,
1809} HUBP_VREADY_AT_OR_AFTER_VSYNC;
1810
1811/*
1812 * HUBP_VTG_SEL enum
1813 */
1814
1815typedef enum HUBP_VTG_SEL {
1816VTG_SEL_0 = 0x00000000,
1817VTG_SEL_1 = 0x00000001,
1818VTG_SEL_2 = 0x00000002,
1819VTG_SEL_3 = 0x00000003,
1820VTG_SEL_4 = 0x00000004,
1821VTG_SEL_5 = 0x00000005,
1822} HUBP_VTG_SEL;
1823
1824/*
1825 * H_MIRROR_EN enum
1826 */
1827
1828typedef enum H_MIRROR_EN {
1829HW_MIRRORING_DISABLE = 0x00000000,
1830HW_MIRRORING_ENABLE = 0x00000001,
1831} H_MIRROR_EN;
1832
1833/*
1834 * LEGACY_PIPE_INTERLEAVE enum
1835 */
1836
1837typedef enum LEGACY_PIPE_INTERLEAVE {
1838LEGACY_PIPE_INTERLEAVE_256B = 0x00000000,
1839LEGACY_PIPE_INTERLEAVE_512B = 0x00000001,
1840} LEGACY_PIPE_INTERLEAVE;
1841
1842/*
1843 * META_CHUNK_SIZE enum
1844 */
1845
1846typedef enum META_CHUNK_SIZE {
1847META_CHUNK_SIZE_1KB = 0x00000000,
1848META_CHUNK_SIZE_2KB = 0x00000001,
1849META_CHUNK_SIZE_4KB = 0x00000002,
1850META_CHUNK_SIZE_8KB = 0x00000003,
1851} META_CHUNK_SIZE;
1852
1853/*
1854 * META_LINEAR enum
1855 */
1856
1857typedef enum META_LINEAR {
1858META_SURF_TILED = 0x00000000,
1859META_SURF_LINEAR = 0x00000001,
1860} META_LINEAR;
1861
1862/*
1863 * MIN_CHUNK_SIZE enum
1864 */
1865
1866typedef enum MIN_CHUNK_SIZE {
1867NO_MIN_CHUNK_SIZE = 0x00000000,
1868MIN_CHUNK_SIZE_256B = 0x00000001,
1869MIN_CHUNK_SIZE_512B = 0x00000002,
1870MIN_CHUNK_SIZE_1024B = 0x00000003,
1871} MIN_CHUNK_SIZE;
1872
1873/*
1874 * MIN_META_CHUNK_SIZE enum
1875 */
1876
1877typedef enum MIN_META_CHUNK_SIZE {
1878NO_MIN_META_CHUNK_SIZE = 0x00000000,
1879MIN_META_CHUNK_SIZE_64B = 0x00000001,
1880MIN_META_CHUNK_SIZE_128B = 0x00000002,
1881MIN_META_CHUNK_SIZE_256B = 0x00000003,
1882} MIN_META_CHUNK_SIZE;
1883
1884/*
1885 * PIPE_ALIGNED enum
1886 */
1887
1888typedef enum PIPE_ALIGNED {
1889PIPE_UNALIGNED_SURF = 0x00000000,
1890PIPE_ALIGNED_SURF = 0x00000001,
1891} PIPE_ALIGNED;
1892
1893/*
1894 * PTE_BUFFER_MODE enum
1895 */
1896
1897typedef enum PTE_BUFFER_MODE {
1898PTE_BUFFER_MODE_0 = 0x00000000,
1899PTE_BUFFER_MODE_1 = 0x00000001,
1900} PTE_BUFFER_MODE;
1901
1902/*
1903 * PTE_ROW_HEIGHT_LINEAR enum
1904 */
1905
1906typedef enum PTE_ROW_HEIGHT_LINEAR {
1907PTE_ROW_HEIGHT_LINEAR_8L = 0x00000000,
1908PTE_ROW_HEIGHT_LINEAR_16L = 0x00000001,
1909PTE_ROW_HEIGHT_LINEAR_32L = 0x00000002,
1910PTE_ROW_HEIGHT_LINEAR_64L = 0x00000003,
1911PTE_ROW_HEIGHT_LINEAR_128L = 0x00000004,
1912PTE_ROW_HEIGHT_LINEAR_256L = 0x00000005,
1913PTE_ROW_HEIGHT_LINEAR_512L = 0x00000006,
1914PTE_ROW_HEIGHT_LINEAR_1024L = 0x00000007,
1915} PTE_ROW_HEIGHT_LINEAR;
1916
1917/*
1918 * ROTATION_ANGLE enum
1919 */
1920
1921typedef enum ROTATION_ANGLE {
1922ROTATE_0_DEGREES = 0x00000000,
1923ROTATE_90_DEGREES = 0x00000001,
1924ROTATE_180_DEGREES = 0x00000002,
1925ROTATE_270_DEGREES = 0x00000003,
1926} ROTATION_ANGLE;
1927
1928/*
1929 * SWATH_HEIGHT enum
1930 */
1931
1932typedef enum SWATH_HEIGHT {
1933SWATH_HEIGHT_1L = 0x00000000,
1934SWATH_HEIGHT_2L = 0x00000001,
1935SWATH_HEIGHT_4L = 0x00000002,
1936SWATH_HEIGHT_8L = 0x00000003,
1937SWATH_HEIGHT_16L = 0x00000004,
1938} SWATH_HEIGHT;
1939
1940/*
1941 * USE_MALL_FOR_CURSOR enum
1942 */
1943
1944typedef enum USE_MALL_FOR_CURSOR {
1945USE_MALL_FOR_CURSOR_0 = 0x00000000,
1946USE_MALL_FOR_CURSOR_1 = 0x00000001,
1947} USE_MALL_FOR_CURSOR;
1948
1949/*
1950 * USE_MALL_FOR_PSTATE_CHANGE enum
1951 */
1952
1953typedef enum USE_MALL_FOR_PSTATE_CHANGE {
1954USE_MALL_FOR_PSTATE_CHANGE_0 = 0x00000000,
1955USE_MALL_FOR_PSTATE_CHANGE_1 = 0x00000001,
1956} USE_MALL_FOR_PSTATE_CHANGE;
1957
1958/*
1959 * USE_MALL_FOR_STATIC_SCREEN enum
1960 */
1961
1962typedef enum USE_MALL_FOR_STATIC_SCREEN {
1963USE_MALL_FOR_STATIC_SCREEN_0 = 0x00000000,
1964USE_MALL_FOR_STATIC_SCREEN_1 = 0x00000001,
1965} USE_MALL_FOR_STATIC_SCREEN;
1966
1967/*
1968 * VMPG_SIZE enum
1969 */
1970
1971typedef enum VMPG_SIZE {
1972VMPG_SIZE_4KB = 0x00000000,
1973VMPG_SIZE_64KB = 0x00000001,
1974} VMPG_SIZE;
1975
1976/*
1977 * VM_GROUP_SIZE enum
1978 */
1979
1980typedef enum VM_GROUP_SIZE {
1981VM_GROUP_SIZE_64B = 0x00000000,
1982VM_GROUP_SIZE_128B = 0x00000001,
1983VM_GROUP_SIZE_256B = 0x00000002,
1984VM_GROUP_SIZE_512B = 0x00000003,
1985VM_GROUP_SIZE_1024B = 0x00000004,
1986VM_GROUP_SIZE_2048B = 0x00000005,
1987} VM_GROUP_SIZE;
1988
1989/*******************************************************
1990 * HUBPREQ Enums
1991 *******************************************************/
1992
1993/*
1994 * DFQ_MIN_FREE_ENTRIES enum
1995 */
1996
1997typedef enum DFQ_MIN_FREE_ENTRIES {
1998DFQ_MIN_FREE_ENTRIES_0 = 0x00000000,
1999DFQ_MIN_FREE_ENTRIES_1 = 0x00000001,
2000DFQ_MIN_FREE_ENTRIES_2 = 0x00000002,
2001DFQ_MIN_FREE_ENTRIES_3 = 0x00000003,
2002DFQ_MIN_FREE_ENTRIES_4 = 0x00000004,
2003DFQ_MIN_FREE_ENTRIES_5 = 0x00000005,
2004DFQ_MIN_FREE_ENTRIES_6 = 0x00000006,
2005DFQ_MIN_FREE_ENTRIES_7 = 0x00000007,
2006} DFQ_MIN_FREE_ENTRIES;
2007
2008/*
2009 * DFQ_NUM_ENTRIES enum
2010 */
2011
2012typedef enum DFQ_NUM_ENTRIES {
2013DFQ_NUM_ENTRIES_0 = 0x00000000,
2014DFQ_NUM_ENTRIES_1 = 0x00000001,
2015DFQ_NUM_ENTRIES_2 = 0x00000002,
2016DFQ_NUM_ENTRIES_3 = 0x00000003,
2017DFQ_NUM_ENTRIES_4 = 0x00000004,
2018DFQ_NUM_ENTRIES_5 = 0x00000005,
2019DFQ_NUM_ENTRIES_6 = 0x00000006,
2020DFQ_NUM_ENTRIES_7 = 0x00000007,
2021DFQ_NUM_ENTRIES_8 = 0x00000008,
2022} DFQ_NUM_ENTRIES;
2023
2024/*
2025 * DFQ_SIZE enum
2026 */
2027
2028typedef enum DFQ_SIZE {
2029DFQ_SIZE_0 = 0x00000000,
2030DFQ_SIZE_1 = 0x00000001,
2031DFQ_SIZE_2 = 0x00000002,
2032DFQ_SIZE_3 = 0x00000003,
2033DFQ_SIZE_4 = 0x00000004,
2034DFQ_SIZE_5 = 0x00000005,
2035DFQ_SIZE_6 = 0x00000006,
2036DFQ_SIZE_7 = 0x00000007,
2037} DFQ_SIZE;
2038
2039/*
2040 * DMDATA_VM_DONE enum
2041 */
2042
2043typedef enum DMDATA_VM_DONE {
2044DMDATA_VM_IS_NOT_DONE = 0x00000000,
2045DMDATA_VM_IS_DONE = 0x00000001,
2046} DMDATA_VM_DONE;
2047
2048/*
2049 * EXPANSION_MODE enum
2050 */
2051
2052typedef enum EXPANSION_MODE {
2053EXPANSION_MODE_ZERO = 0x00000000,
2054EXPANSION_MODE_CONSERVATIVE = 0x00000001,
2055EXPANSION_MODE_OPTIMAL = 0x00000002,
2056} EXPANSION_MODE;
2057
2058/*
2059 * FLIP_RATE enum
2060 */
2061
2062typedef enum FLIP_RATE {
2063FLIP_RATE_0 = 0x00000000,
2064FLIP_RATE_1 = 0x00000001,
2065FLIP_RATE_2 = 0x00000002,
2066FLIP_RATE_3 = 0x00000003,
2067FLIP_RATE_4 = 0x00000004,
2068FLIP_RATE_5 = 0x00000005,
2069FLIP_RATE_6 = 0x00000006,
2070FLIP_RATE_7 = 0x00000007,
2071} FLIP_RATE;
2072
2073/*
2074 * INT_MASK enum
2075 */
2076
2077typedef enum INT_MASK {
2078INT_DISABLED = 0x00000000,
2079INT_ENABLED = 0x00000001,
2080} INT_MASK;
2081
2082/*
2083 * PIPE_IN_FLUSH_URGENT enum
2084 */
2085
2086typedef enum PIPE_IN_FLUSH_URGENT {
2087PIPE_IN_FLUSH_URGENT_ENABLE = 0x00000000,
2088PIPE_IN_FLUSH_URGENT_DISABLE = 0x00000001,
2089} PIPE_IN_FLUSH_URGENT;
2090
2091/*
2092 * PRQ_MRQ_FLUSH_URGENT enum
2093 */
2094
2095typedef enum PRQ_MRQ_FLUSH_URGENT {
2096PRQ_MRQ_FLUSH_URGENT_ENABLE = 0x00000000,
2097PRQ_MRQ_FLUSH_URGENT_DISABLE = 0x00000001,
2098} PRQ_MRQ_FLUSH_URGENT;
2099
2100/*
2101 * ROW_TTU_MODE enum
2102 */
2103
2104typedef enum ROW_TTU_MODE {
2105END_OF_ROW_MODE = 0x00000000,
2106WATERMARK_MODE = 0x00000001,
2107} ROW_TTU_MODE;
2108
2109/*
2110 * SURFACE_DCC enum
2111 */
2112
2113typedef enum SURFACE_DCC {
2114SURFACE_IS_NOT_DCC = 0x00000000,
2115SURFACE_IS_DCC = 0x00000001,
2116} SURFACE_DCC;
2117
2118/*
2119 * SURFACE_DCC_IND_128B enum
2120 */
2121
2122typedef enum SURFACE_DCC_IND_128B {
2123SURFACE_DCC_IS_NOT_IND_128B = 0x00000000,
2124SURFACE_DCC_IS_IND_128B = 0x00000001,
2125} SURFACE_DCC_IND_128B;
2126
2127/*
2128 * SURFACE_DCC_IND_64B enum
2129 */
2130
2131typedef enum SURFACE_DCC_IND_64B {
2132SURFACE_DCC_IS_NOT_IND_64B = 0x00000000,
2133SURFACE_DCC_IS_IND_64B = 0x00000001,
2134} SURFACE_DCC_IND_64B;
2135
2136/*
2137 * SURFACE_DCC_IND_BLK enum
2138 */
2139
2140typedef enum SURFACE_DCC_IND_BLK {
2141SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0x00000000,
2142SURFACE_DCC_BLOCK_IS_IND_64B = 0x00000001,
2143SURFACE_DCC_BLOCK_IS_IND_128B = 0x00000002,
2144SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 0x00000003,
2145} SURFACE_DCC_IND_BLK;
2146
2147/*
2148 * SURFACE_FLIP_AWAY_INT_TYPE enum
2149 */
2150
2151typedef enum SURFACE_FLIP_AWAY_INT_TYPE {
2152SURFACE_FLIP_AWAY_INT_LEVEL = 0x00000000,
2153SURFACE_FLIP_AWAY_INT_PULSE = 0x00000001,
2154} SURFACE_FLIP_AWAY_INT_TYPE;
2155
2156/*
2157 * SURFACE_FLIP_EXEC_DEBUG_MODE enum
2158 */
2159
2160typedef enum SURFACE_FLIP_EXEC_DEBUG_MODE {
2161SURFACE_FLIP_EXEC_NORMAL_MODE = 0x00000000,
2162SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 0x00000001,
2163} SURFACE_FLIP_EXEC_DEBUG_MODE;
2164
2165/*
2166 * SURFACE_FLIP_INT_TYPE enum
2167 */
2168
2169typedef enum SURFACE_FLIP_INT_TYPE {
2170SURFACE_FLIP_INT_LEVEL = 0x00000000,
2171SURFACE_FLIP_INT_PULSE = 0x00000001,
2172} SURFACE_FLIP_INT_TYPE;
2173
2174/*
2175 * SURFACE_FLIP_IN_STEREOSYNC enum
2176 */
2177
2178typedef enum SURFACE_FLIP_IN_STEREOSYNC {
2179SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0x00000000,
2180SURFACE_FLIP_IN_STEREOSYNC_MODE = 0x00000001,
2181} SURFACE_FLIP_IN_STEREOSYNC;
2182
2183/*
2184 * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum
2185 */
2186
2187typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC {
2188FLIP_ANY_FRAME = 0x00000000,
2189FLIP_LEFT_EYE = 0x00000001,
2190FLIP_RIGHT_EYE = 0x00000002,
2191SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 0x00000003,
2192} SURFACE_FLIP_MODE_FOR_STEREOSYNC;
2193
2194/*
2195 * SURFACE_FLIP_STEREO_SELECT_DISABLE enum
2196 */
2197
2198typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE {
2199SURFACE_FLIP_STEREO_SELECT_ENABLED = 0x00000000,
2200SURFACE_FLIP_STEREO_SELECT_DISABLED = 0x00000001,
2201} SURFACE_FLIP_STEREO_SELECT_DISABLE;
2202
2203/*
2204 * SURFACE_FLIP_STEREO_SELECT_POLARITY enum
2205 */
2206
2207typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY {
2208SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0x00000000,
2209SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 0x00000001,
2210} SURFACE_FLIP_STEREO_SELECT_POLARITY;
2211
2212/*
2213 * SURFACE_FLIP_TYPE enum
2214 */
2215
2216typedef enum SURFACE_FLIP_TYPE {
2217SURFACE_V_FLIP = 0x00000000,
2218SURFACE_I_FLIP = 0x00000001,
2219} SURFACE_FLIP_TYPE;
2220
2221/*
2222 * SURFACE_FLIP_VUPDATE_SKIP_NUM enum
2223 */
2224
2225typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM {
2226SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0x00000000,
2227SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 0x00000001,
2228SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 0x00000002,
2229SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 0x00000003,
2230SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 0x00000004,
2231SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 0x00000005,
2232SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 0x00000006,
2233SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 0x00000007,
2234SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 0x00000008,
2235SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 0x00000009,
2236SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 0x0000000a,
2237SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 0x0000000b,
2238SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 0x0000000c,
2239SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 0x0000000d,
2240SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 0x0000000e,
2241SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 0x0000000f,
2242} SURFACE_FLIP_VUPDATE_SKIP_NUM;
2243
2244/*
2245 * SURFACE_INUSE_RAED_NO_LATCH enum
2246 */
2247
2248typedef enum SURFACE_INUSE_RAED_NO_LATCH {
2249SURFACE_INUSE_IS_LATCHED = 0x00000000,
2250SURFACE_INUSE_IS_NOT_LATCHED = 0x00000001,
2251} SURFACE_INUSE_RAED_NO_LATCH;
2252
2253/*
2254 * SURFACE_TMZ enum
2255 */
2256
2257typedef enum SURFACE_TMZ {
2258SURFACE_IS_NOT_TMZ = 0x00000000,
2259SURFACE_IS_TMZ = 0x00000001,
2260} SURFACE_TMZ;
2261
2262/*
2263 * SURFACE_UPDATE_LOCK enum
2264 */
2265
2266typedef enum SURFACE_UPDATE_LOCK {
2267SURFACE_UPDATE_IS_UNLOCKED = 0x00000000,
2268SURFACE_UPDATE_IS_LOCKED = 0x00000001,
2269} SURFACE_UPDATE_LOCK;
2270
2271/*******************************************************
2272 * HUBPRET Enums
2273 *******************************************************/
2274
2275/*
2276 * CROSSBAR_FOR_ALPHA enum
2277 */
2278
2279typedef enum CROSSBAR_FOR_ALPHA {
2280ALPHA_DATA_ONTO_ALPHA_PORT = 0x00000000,
2281Y_G_DATA_ONTO_ALPHA_PORT = 0x00000001,
2282CB_B_DATA_ONTO_ALPHA_PORT = 0x00000002,
2283CR_R_DATA_ONTO_ALPHA_PORT = 0x00000003,
2284} CROSSBAR_FOR_ALPHA;
2285
2286/*
2287 * CROSSBAR_FOR_CB_B enum
2288 */
2289
2290typedef enum CROSSBAR_FOR_CB_B {
2291ALPHA_DATA_ONTO_CB_B_PORT = 0x00000000,
2292Y_G_DATA_ONTO_CB_B_PORT = 0x00000001,
2293CB_B_DATA_ONTO_CB_B_PORT = 0x00000002,
2294CR_R_DATA_ONTO_CB_B_PORT = 0x00000003,
2295} CROSSBAR_FOR_CB_B;
2296
2297/*
2298 * CROSSBAR_FOR_CR_R enum
2299 */
2300
2301typedef enum CROSSBAR_FOR_CR_R {
2302ALPHA_DATA_ONTO_CR_R_PORT = 0x00000000,
2303Y_G_DATA_ONTO_CR_R_PORT = 0x00000001,
2304CB_B_DATA_ONTO_CR_R_PORT = 0x00000002,
2305CR_R_DATA_ONTO_CR_R_PORT = 0x00000003,
2306} CROSSBAR_FOR_CR_R;
2307
2308/*
2309 * CROSSBAR_FOR_Y_G enum
2310 */
2311
2312typedef enum CROSSBAR_FOR_Y_G {
2313ALPHA_DATA_ONTO_Y_G_PORT = 0x00000000,
2314Y_G_DATA_ONTO_Y_G_PORT = 0x00000001,
2315CB_B_DATA_ONTO_Y_G_PORT = 0x00000002,
2316CR_R_DATA_ONTO_Y_G_PORT = 0x00000003,
2317} CROSSBAR_FOR_Y_G;
2318
2319/*
2320 * DETILE_BUFFER_PACKER_ENABLE enum
2321 */
2322
2323typedef enum DETILE_BUFFER_PACKER_ENABLE {
2324DETILE_BUFFER_PACKER_IS_DISABLE = 0x00000000,
2325DETILE_BUFFER_PACKER_IS_ENABLE = 0x00000001,
2326} DETILE_BUFFER_PACKER_ENABLE;
2327
2328/*
2329 * MEM_PWR_DIS_MODE enum
2330 */
2331
2332typedef enum MEM_PWR_DIS_MODE {
2333MEM_POWER_DIS_MODE_ENABLE = 0x00000000,
2334MEM_POWER_DIS_MODE_DISABLE = 0x00000001,
2335} MEM_PWR_DIS_MODE;
2336
2337/*
2338 * MEM_PWR_FORCE_MODE enum
2339 */
2340
2341typedef enum MEM_PWR_FORCE_MODE {
2342MEM_POWER_FORCE_MODE_OFF = 0x00000000,
2343MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 0x00000001,
2344MEM_POWER_FORCE_MODE_DEEP_SLEEP = 0x00000002,
2345MEM_POWER_FORCE_MODE_SHUT_DOWN = 0x00000003,
2346} MEM_PWR_FORCE_MODE;
2347
2348/*
2349 * MEM_PWR_STATUS enum
2350 */
2351
2352typedef enum MEM_PWR_STATUS {
2353MEM_POWER_STATUS_ON = 0x00000000,
2354MEM_POWER_STATUS_LIGHT_SLEEP = 0x00000001,
2355MEM_POWER_STATUS_DEEP_SLEEP = 0x00000002,
2356MEM_POWER_STATUS_SHUT_DOWN = 0x00000003,
2357} MEM_PWR_STATUS;
2358
2359/*
2360 * PIPE_INT_MASK_MODE enum
2361 */
2362
2363typedef enum PIPE_INT_MASK_MODE {
2364PIPE_INT_MASK_MODE_DISABLE = 0x00000000,
2365PIPE_INT_MASK_MODE_ENABLE = 0x00000001,
2366} PIPE_INT_MASK_MODE;
2367
2368/*
2369 * PIPE_INT_TYPE_MODE enum
2370 */
2371
2372typedef enum PIPE_INT_TYPE_MODE {
2373PIPE_INT_TYPE_MODE_DISABLE = 0x00000000,
2374PIPE_INT_TYPE_MODE_ENABLE = 0x00000001,
2375} PIPE_INT_TYPE_MODE;
2376
2377/*
2378 * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum
2379 */
2380
2381typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE {
2382PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
2383PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
2384} PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE;
2385
2386/*******************************************************
2387 * CURSOR Enums
2388 *******************************************************/
2389
2390/*
2391 * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum
2392 */
2393
2394typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE {
2395CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
2396CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
2397CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002,
2398} CROB_MEM_PWR_LIGHT_SLEEP_MODE;
2399
2400/*
2401 * CURSOR_2X_MAGNIFY enum
2402 */
2403
2404typedef enum CURSOR_2X_MAGNIFY {
2405CURSOR_2X_MAGNIFY_IS_DISABLE = 0x00000000,
2406CURSOR_2X_MAGNIFY_IS_ENABLE = 0x00000001,
2407} CURSOR_2X_MAGNIFY;
2408
2409/*
2410 * CURSOR_ENABLE enum
2411 */
2412
2413typedef enum CURSOR_ENABLE {
2414CURSOR_IS_DISABLE = 0x00000000,
2415CURSOR_IS_ENABLE = 0x00000001,
2416} CURSOR_ENABLE;
2417
2418/*
2419 * CURSOR_LINES_PER_CHUNK enum
2420 */
2421
2422typedef enum CURSOR_LINES_PER_CHUNK {
2423CURSOR_LINE_PER_CHUNK_1 = 0x00000000,
2424CURSOR_LINE_PER_CHUNK_2 = 0x00000001,
2425CURSOR_LINE_PER_CHUNK_4 = 0x00000002,
2426CURSOR_LINE_PER_CHUNK_8 = 0x00000003,
2427CURSOR_LINE_PER_CHUNK_16 = 0x00000004,
2428} CURSOR_LINES_PER_CHUNK;
2429
2430/*
2431 * CURSOR_MODE enum
2432 */
2433
2434typedef enum CURSOR_MODE {
2435CURSOR_MONO_2BIT = 0x00000000,
2436CURSOR_COLOR_24BIT_1BIT_AND = 0x00000001,
2437CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002,
2438CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003,
2439CURSOR_COLOR_64BIT_FP_PREMULT = 0x00000004,
2440CURSOR_COLOR_64BIT_FP_UNPREMULT = 0x00000005,
2441} CURSOR_MODE;
2442
2443/*
2444 * CURSOR_PERFMON_LATENCY_MEASURE_EN enum
2445 */
2446
2447typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN {
2448CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0x00000000,
2449CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 0x00000001,
2450} CURSOR_PERFMON_LATENCY_MEASURE_EN;
2451
2452/*
2453 * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum
2454 */
2455
2456typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL {
2457CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0x00000000,
2458CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 0x00000001,
2459} CURSOR_PERFMON_LATENCY_MEASURE_SEL;
2460
2461/*
2462 * CURSOR_PITCH enum
2463 */
2464
2465typedef enum CURSOR_PITCH {
2466CURSOR_PITCH_64_PIXELS = 0x00000000,
2467CURSOR_PITCH_128_PIXELS = 0x00000001,
2468CURSOR_PITCH_256_PIXELS = 0x00000002,
2469} CURSOR_PITCH;
2470
2471/*
2472 * CURSOR_REQ_MODE enum
2473 */
2474
2475typedef enum CURSOR_REQ_MODE {
2476CURSOR_REQUEST_NORMALLY = 0x00000000,
2477CURSOR_REQUEST_EARLY = 0x00000001,
2478} CURSOR_REQ_MODE;
2479
2480/*
2481 * CURSOR_SNOOP enum
2482 */
2483
2484typedef enum CURSOR_SNOOP {
2485CURSOR_IS_NOT_SNOOP = 0x00000000,
2486CURSOR_IS_SNOOP = 0x00000001,
2487} CURSOR_SNOOP;
2488
2489/*
2490 * CURSOR_STEREO_EN enum
2491 */
2492
2493typedef enum CURSOR_STEREO_EN {
2494CURSOR_STEREO_IS_DISABLED = 0x00000000,
2495CURSOR_STEREO_IS_ENABLED = 0x00000001,
2496} CURSOR_STEREO_EN;
2497
2498/*
2499 * CURSOR_SURFACE_TMZ enum
2500 */
2501
2502typedef enum CURSOR_SURFACE_TMZ {
2503CURSOR_SURFACE_IS_NOT_TMZ = 0x00000000,
2504CURSOR_SURFACE_IS_TMZ = 0x00000001,
2505} CURSOR_SURFACE_TMZ;
2506
2507/*
2508 * CURSOR_SYSTEM enum
2509 */
2510
2511typedef enum CURSOR_SYSTEM {
2512CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0x00000000,
2513CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 0x00000001,
2514} CURSOR_SYSTEM;
2515
2516/*
2517 * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum
2518 */
2519
2520typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS {
2521CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0x00000000,
2522CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 0x00000001,
2523} CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS;
2524
2525/*
2526 * DMDATA_DONE enum
2527 */
2528
2529typedef enum DMDATA_DONE {
2530DMDATA_NOT_SENT_TO_DIG = 0x00000000,
2531DMDATA_SENT_TO_DIG = 0x00000001,
2532} DMDATA_DONE;
2533
2534/*
2535 * DMDATA_MODE enum
2536 */
2537
2538typedef enum DMDATA_MODE {
2539DMDATA_SOFTWARE_UPDATE_MODE = 0x00000000,
2540DMDATA_HARDWARE_UPDATE_MODE = 0x00000001,
2541} DMDATA_MODE;
2542
2543/*
2544 * DMDATA_QOS_MODE enum
2545 */
2546
2547typedef enum DMDATA_QOS_MODE {
2548DMDATA_QOS_LEVEL_FROM_TTU = 0x00000000,
2549DMDATA_QOS_LEVEL_FROM_SOFTWARE = 0x00000001,
2550} DMDATA_QOS_MODE;
2551
2552/*
2553 * DMDATA_REPEAT enum
2554 */
2555
2556typedef enum DMDATA_REPEAT {
2557DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0x00000000,
2558DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 0x00000001,
2559} DMDATA_REPEAT;
2560
2561/*
2562 * DMDATA_UNDERFLOW enum
2563 */
2564
2565typedef enum DMDATA_UNDERFLOW {
2566DMDATA_NOT_UNDERFLOW = 0x00000000,
2567DMDATA_UNDERFLOWED = 0x00000001,
2568} DMDATA_UNDERFLOW;
2569
2570/*
2571 * DMDATA_UNDERFLOW_CLEAR enum
2572 */
2573
2574typedef enum DMDATA_UNDERFLOW_CLEAR {
2575DMDATA_DONT_CLEAR = 0x00000000,
2576DMDATA_CLEAR_UNDERFLOW_STATUS = 0x00000001,
2577} DMDATA_UNDERFLOW_CLEAR;
2578
2579/*
2580 * DMDATA_UPDATED enum
2581 */
2582
2583typedef enum DMDATA_UPDATED {
2584DMDATA_NOT_UPDATED = 0x00000000,
2585DMDATA_WAS_UPDATED = 0x00000001,
2586} DMDATA_UPDATED;
2587
2588/*******************************************************
2589 * HUBBUB_SDPIF Enums
2590 *******************************************************/
2591
2592/*
2593 * RESPONSE_STATUS enum
2594 */
2595
2596typedef enum RESPONSE_STATUS {
2597OKAY = 0x00000000,
2598EXOKAY = 0x00000001,
2599SLVERR = 0x00000002,
2600DECERR = 0x00000003,
2601EARLY = 0x00000004,
2602OKAY_NODATA = 0x00000005,
2603PROTVIOL = 0x00000006,
2604TRANSERR = 0x00000007,
2605CMPTO = 0x00000008,
2606CRS = 0x0000000c,
2607} RESPONSE_STATUS;
2608
2609/*******************************************************
2610 * HUBBUB_RET_PATH Enums
2611 *******************************************************/
2612
2613/*
2614 * DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE enum
2615 */
2616
2617typedef enum DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE {
2618DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
2619DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
2620DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002,
2621} DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE;
2622
2623/*
2624 * DCHUBBUB_MEM_PWR_DIS_MODE enum
2625 */
2626
2627typedef enum DCHUBBUB_MEM_PWR_DIS_MODE {
2628DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0x00000000,
2629DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 0x00000001,
2630} DCHUBBUB_MEM_PWR_DIS_MODE;
2631
2632/*
2633 * DCHUBBUB_MEM_PWR_MODE enum
2634 */
2635
2636typedef enum DCHUBBUB_MEM_PWR_MODE {
2637DCHUBBUB_MEM_POWER_MODE_OFF = 0x00000000,
2638DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 0x00000001,
2639DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 0x00000002,
2640DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 0x00000003,
2641} DCHUBBUB_MEM_PWR_MODE;
2642
2643/*******************************************************
2644 * MPC_CFG Enums
2645 *******************************************************/
2646
2647/*
2648 * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum
2649 */
2650
2651typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET {
2652MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2653MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2654} MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET;
2655
2656/*
2657 * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum
2658 */
2659
2660typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET {
2661MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2662MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2663} MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET;
2664
2665/*
2666 * MPC_CFG_ADR_VUPDATE_LOCK_SET enum
2667 */
2668
2669typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET {
2670MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2671MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2672} MPC_CFG_ADR_VUPDATE_LOCK_SET;
2673
2674/*
2675 * MPC_CFG_CFG_VUPDATE_LOCK_SET enum
2676 */
2677
2678typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET {
2679MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2680MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2681} MPC_CFG_CFG_VUPDATE_LOCK_SET;
2682
2683/*
2684 * MPC_CFG_CUR_VUPDATE_LOCK_SET enum
2685 */
2686
2687typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET {
2688MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2689MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2690} MPC_CFG_CUR_VUPDATE_LOCK_SET;
2691
2692/*
2693 * MPC_CFG_MPC_TEST_CLK_SEL enum
2694 */
2695
2696typedef enum MPC_CFG_MPC_TEST_CLK_SEL {
2697MPC_CFG_MPC_TEST_CLK_SEL_0 = 0x00000000,
2698MPC_CFG_MPC_TEST_CLK_SEL_1 = 0x00000001,
2699MPC_CFG_MPC_TEST_CLK_SEL_2 = 0x00000002,
2700MPC_CFG_MPC_TEST_CLK_SEL_3 = 0x00000003,
2701} MPC_CFG_MPC_TEST_CLK_SEL;
2702
2703/*
2704 * MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN enum
2705 */
2706
2707typedef enum MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN {
2708MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
2709MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
2710} MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN;
2711
2712/*
2713 * MPC_CRC_CALC_INTERLACE_MODE enum
2714 */
2715
2716typedef enum MPC_CRC_CALC_INTERLACE_MODE {
2717MPC_CRC_INTERLACE_MODE_TOP = 0x00000000,
2718MPC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
2719MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 0x00000002,
2720MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 0x00000003,
2721} MPC_CRC_CALC_INTERLACE_MODE;
2722
2723/*
2724 * MPC_CRC_CALC_MODE enum
2725 */
2726
2727typedef enum MPC_CRC_CALC_MODE {
2728MPC_CRC_ONE_SHOT_MODE = 0x00000000,
2729MPC_CRC_CONTINUOUS_MODE = 0x00000001,
2730} MPC_CRC_CALC_MODE;
2731
2732/*
2733 * MPC_CRC_CALC_STEREO_MODE enum
2734 */
2735
2736typedef enum MPC_CRC_CALC_STEREO_MODE {
2737MPC_CRC_STEREO_MODE_LEFT = 0x00000000,
2738MPC_CRC_STEREO_MODE_RIGHT = 0x00000001,
2739MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 0x00000002,
2740MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 0x00000003,
2741} MPC_CRC_CALC_STEREO_MODE;
2742
2743/*
2744 * MPC_CRC_SOURCE_SELECT enum
2745 */
2746
2747typedef enum MPC_CRC_SOURCE_SELECT {
2748MPC_CRC_SOURCE_SEL_DPP = 0x00000000,
2749MPC_CRC_SOURCE_SEL_OPP = 0x00000001,
2750MPC_CRC_SOURCE_SEL_DWB = 0x00000002,
2751MPC_CRC_SOURCE_SEL_OTHER = 0x00000003,
2752} MPC_CRC_SOURCE_SELECT;
2753
2754/*
2755 * MPC_DEBUG_BUS1_DATA_SELECT enum
2756 */
2757
2758typedef enum MPC_DEBUG_BUS1_DATA_SELECT {
2759MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG = 0x00000000,
2760MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT = 0x00000001,
2761MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1 = 0x00000002,
2762MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV = 0x00000003,
2763} MPC_DEBUG_BUS1_DATA_SELECT;
2764
2765/*
2766 * MPC_DEBUG_BUS2_DATA_SELECT enum
2767 */
2768
2769typedef enum MPC_DEBUG_BUS2_DATA_SELECT {
2770MPC_DEBUG_BUS2_DATA_SELECT_MPCC = 0x00000000,
2771MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT = 0x00000001,
2772MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM = 0x00000002,
2773MPC_DEBUG_BUS2_DATA_SELECT_RES = 0x00000003,
2774} MPC_DEBUG_BUS2_DATA_SELECT;
2775
2776/*
2777 * MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT enum
2778 */
2779
2780typedef enum MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT {
2781MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID = 0x00000000,
2782MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID = 0x00000001,
2783MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID = 0x00000002,
2784MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID = 0x00000003,
2785MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA = 0x00000004,
2786MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA = 0x00000005,
2787MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1 = 0x00000006,
2788MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID = 0x00000007,
2789} MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT;
2790
2791/*
2792 * MPC_DEBUG_BUS_MPCC_BYTE_SELECT enum
2793 */
2794
2795typedef enum MPC_DEBUG_BUS_MPCC_BYTE_SELECT {
2796MPC_DEBUG_BUS_MPCC_BYTE0 = 0x00000000,
2797MPC_DEBUG_BUS_MPCC_BYTE1 = 0x00000001,
2798MPC_DEBUG_BUS_MPCC_BYTE2 = 0x00000002,
2799MPC_DEBUG_BUS_MPCC_BYTE3 = 0x00000003,
2800} MPC_DEBUG_BUS_MPCC_BYTE_SELECT;
2801
2802/*******************************************************
2803 * MPC_OCSC Enums
2804 *******************************************************/
2805
2806/*
2807 * MPC_OCSC_COEF_FORMAT enum
2808 */
2809
2810typedef enum MPC_OCSC_COEF_FORMAT {
2811MPC_OCSC_COEF_FORMAT_S2_13 = 0x00000000,
2812MPC_OCSC_COEF_FORMAT_S3_12 = 0x00000001,
2813} MPC_OCSC_COEF_FORMAT;
2814
2815/*
2816 * MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN enum
2817 */
2818
2819typedef enum MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN {
2820MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
2821MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
2822} MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN;
2823
2824/*
2825 * MPC_OUT_CSC_MODE enum
2826 */
2827
2828typedef enum MPC_OUT_CSC_MODE {
2829MPC_OUT_CSC_MODE_0 = 0x00000000,
2830MPC_OUT_CSC_MODE_1 = 0x00000001,
2831MPC_OUT_CSC_MODE_2 = 0x00000002,
2832MPC_OUT_CSC_MODE_RSV = 0x00000003,
2833} MPC_OUT_CSC_MODE;
2834
2835/*
2836 * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum
2837 */
2838
2839typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE {
2840MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0x00000000,
2841MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 0x00000001,
2842MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 0x00000002,
2843MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 0x00000003,
2844MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 0x00000004,
2845MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 0x00000005,
2846MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 0x00000006,
2847MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 0x00000007,
2848} MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE;
2849
2850/*
2851 * MPC_OUT_RATE_CONTROL_DISABLE_SET enum
2852 */
2853
2854typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET {
2855MPC_OUT_RATE_CONTROL_SET_ENABLE = 0x00000000,
2856MPC_OUT_RATE_CONTROL_SET_DISABLE = 0x00000001,
2857} MPC_OUT_RATE_CONTROL_DISABLE_SET;
2858
2859/*******************************************************
2860 * MPCC Enums
2861 *******************************************************/
2862
2863/*
2864 * MPCC_BG_COLOR_BPC enum
2865 */
2866
2867typedef enum MPCC_BG_COLOR_BPC {
2868MPCC_BG_COLOR_BPC_8bit = 0x00000000,
2869MPCC_BG_COLOR_BPC_9bit = 0x00000001,
2870MPCC_BG_COLOR_BPC_10bit = 0x00000002,
2871MPCC_BG_COLOR_BPC_11bit = 0x00000003,
2872MPCC_BG_COLOR_BPC_12bit = 0x00000004,
2873} MPCC_BG_COLOR_BPC;
2874
2875/*
2876 * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum
2877 */
2878
2879typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY {
2880MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000,
2881MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001,
2882} MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY;
2883
2884/*
2885 * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum
2886 */
2887
2888typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE {
2889MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0x00000000,
2890MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
2891MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 0x00000002,
2892MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 0x00000003,
2893} MPCC_CONTROL_MPCC_ALPHA_BLND_MODE;
2894
2895/*
2896 * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum
2897 */
2898
2899typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE {
2900MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0x00000000,
2901MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 0x00000001,
2902} MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE;
2903
2904/*
2905 * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum
2906 */
2907
2908typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE {
2909MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0x00000000,
2910MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 0x00000001,
2911} MPCC_CONTROL_MPCC_BOT_GAIN_MODE;
2912
2913/*
2914 * MPCC_CONTROL_MPCC_MODE enum
2915 */
2916
2917typedef enum MPCC_CONTROL_MPCC_MODE {
2918MPCC_CONTROL_MPCC_MODE_BYPASS = 0x00000000,
2919MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 0x00000001,
2920MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 0x00000002,
2921MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 0x00000003,
2922} MPCC_CONTROL_MPCC_MODE;
2923
2924/*
2925 * MPCC_SM_CONTROL_MPCC_SM_EN enum
2926 */
2927
2928typedef enum MPCC_SM_CONTROL_MPCC_SM_EN {
2929MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0x00000000,
2930MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 0x00000001,
2931} MPCC_SM_CONTROL_MPCC_SM_EN;
2932
2933/*
2934 * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum
2935 */
2936
2937typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT {
2938MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0x00000000,
2939MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 0x00000001,
2940} MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT;
2941
2942/*
2943 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum
2944 */
2945
2946typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL {
2947MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
2948MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
2949MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
2950MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
2951} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL;
2952
2953/*
2954 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum
2955 */
2956
2957typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL {
2958MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
2959MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
2960MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
2961MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
2962} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL;
2963
2964/*
2965 * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum
2966 */
2967
2968typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT {
2969MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0x00000000,
2970MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 0x00000001,
2971} MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT;
2972
2973/*
2974 * MPCC_SM_CONTROL_MPCC_SM_MODE enum
2975 */
2976
2977typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE {
2978MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0x00000000,
2979MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
2980MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
2981MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
2982} MPCC_SM_CONTROL_MPCC_SM_MODE;
2983
2984/*
2985 * MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN enum
2986 */
2987
2988typedef enum MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN {
2989MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
2990MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
2991} MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN;
2992
2993/*******************************************************
2994 * MPCC_OGAM Enums
2995 *******************************************************/
2996
2997/*
2998 * MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM enum
2999 */
3000
3001typedef enum MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM {
3002MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0x00000000,
3003MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 0x00000001,
3004} MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM;
3005
3006/*
3007 * MPCC_GAMUT_REMAP_MODE_ENUM enum
3008 */
3009
3010typedef enum MPCC_GAMUT_REMAP_MODE_ENUM {
3011MPCC_GAMUT_REMAP_MODE_0 = 0x00000000,
3012MPCC_GAMUT_REMAP_MODE_1 = 0x00000001,
3013MPCC_GAMUT_REMAP_MODE_2 = 0x00000002,
3014MPCC_GAMUT_REMAP_MODE_RSV = 0x00000003,
3015} MPCC_GAMUT_REMAP_MODE_ENUM;
3016
3017/*
3018 * MPCC_OGAM_LUT_2_CONFIG_ENUM enum
3019 */
3020
3021typedef enum MPCC_OGAM_LUT_2_CONFIG_ENUM {
3022MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0x00000000,
3023MPCC_OGAM_LUT_2CFG_MEMORY_A = 0x00000001,
3024MPCC_OGAM_LUT_2CFG_MEMORY_B = 0x00000002,
3025} MPCC_OGAM_LUT_2_CONFIG_ENUM;
3026
3027/*
3028 * MPCC_OGAM_LUT_CONFIG_MODE enum
3029 */
3030
3031typedef enum MPCC_OGAM_LUT_CONFIG_MODE {
3032MPCC_OGAM_DIFFERENT_RGB = 0x00000000,
3033MPCC_OGAM_ALL_USE_R = 0x00000001,
3034} MPCC_OGAM_LUT_CONFIG_MODE;
3035
3036/*
3037 * MPCC_OGAM_LUT_PWL_DISABLE_ENUM enum
3038 */
3039
3040typedef enum MPCC_OGAM_LUT_PWL_DISABLE_ENUM {
3041MPCC_OGAM_ENABLE_PWL = 0x00000000,
3042MPCC_OGAM_DISABLE_PWL = 0x00000001,
3043} MPCC_OGAM_LUT_PWL_DISABLE_ENUM;
3044
3045/*
3046 * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum
3047 */
3048
3049typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL {
3050MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0x00000000,
3051MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 0x00000001,
3052} MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL;
3053
3054/*
3055 * MPCC_OGAM_LUT_RAM_SEL enum
3056 */
3057
3058typedef enum MPCC_OGAM_LUT_RAM_SEL {
3059MPCC_OGAM_RAMA_ACCESS = 0x00000000,
3060MPCC_OGAM_RAMB_ACCESS = 0x00000001,
3061} MPCC_OGAM_LUT_RAM_SEL;
3062
3063/*
3064 * MPCC_OGAM_LUT_READ_COLOR_SEL enum
3065 */
3066
3067typedef enum MPCC_OGAM_LUT_READ_COLOR_SEL {
3068MPCC_OGAM_BLUE_LUT = 0x00000000,
3069MPCC_OGAM_GREEN_LUT = 0x00000001,
3070MPCC_OGAM_RED_LUT = 0x00000002,
3071} MPCC_OGAM_LUT_READ_COLOR_SEL;
3072
3073/*
3074 * MPCC_OGAM_LUT_READ_DBG enum
3075 */
3076
3077typedef enum MPCC_OGAM_LUT_READ_DBG {
3078MPCC_OGAM_DISABLE_DEBUG = 0x00000000,
3079MPCC_OGAM_ENABLE_DEBUG = 0x00000001,
3080} MPCC_OGAM_LUT_READ_DBG;
3081
3082/*
3083 * MPCC_OGAM_LUT_SEL_ENUM enum
3084 */
3085
3086typedef enum MPCC_OGAM_LUT_SEL_ENUM {
3087MPCC_OGAM_RAMA = 0x00000000,
3088MPCC_OGAM_RAMB = 0x00000001,
3089} MPCC_OGAM_LUT_SEL_ENUM;
3090
3091/*
3092 * MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM enum
3093 */
3094
3095typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM {
3096MPCC_OGAM_MODE_0 = 0x00000000,
3097MPCC_OGAM_MODE_RSV1 = 0x00000001,
3098MPCC_OGAM_MODE_2 = 0x00000002,
3099MPCC_OGAM_MODE_RSV = 0x00000003,
3100} MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM;
3101
3102/*
3103 * MPCC_OGAM_NUM_SEG enum
3104 */
3105
3106typedef enum MPCC_OGAM_NUM_SEG {
3107MPCC_OGAM_SEGMENTS_1 = 0x00000000,
3108MPCC_OGAM_SEGMENTS_2 = 0x00000001,
3109MPCC_OGAM_SEGMENTS_4 = 0x00000002,
3110MPCC_OGAM_SEGMENTS_8 = 0x00000003,
3111MPCC_OGAM_SEGMENTS_16 = 0x00000004,
3112MPCC_OGAM_SEGMENTS_32 = 0x00000005,
3113MPCC_OGAM_SEGMENTS_64 = 0x00000006,
3114MPCC_OGAM_SEGMENTS_128 = 0x00000007,
3115} MPCC_OGAM_NUM_SEG;
3116
3117/*
3118 * MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN enum
3119 */
3120
3121typedef enum MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN {
3122MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
3123MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
3124} MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN;
3125
3126/*******************************************************
3127 * MPCC_MCM Enums
3128 *******************************************************/
3129
3130/*
3131 * MPCC_MCM_3DLUT_30BIT_ENUM enum
3132 */
3133
3134typedef enum MPCC_MCM_3DLUT_30BIT_ENUM {
3135MPCC_MCM_3DLUT_36BIT = 0x00000000,
3136MPCC_MCM_3DLUT_30BIT = 0x00000001,
3137} MPCC_MCM_3DLUT_30BIT_ENUM;
3138
3139/*
3140 * MPCC_MCM_3DLUT_RAM_SEL enum
3141 */
3142
3143typedef enum MPCC_MCM_3DLUT_RAM_SEL {
3144MPCC_MCM_RAM0_ACCESS = 0x00000000,
3145MPCC_MCM_RAM1_ACCESS = 0x00000001,
3146MPCC_MCM_RAM2_ACCESS = 0x00000002,
3147MPCC_MCM_RAM3_ACCESS = 0x00000003,
3148} MPCC_MCM_3DLUT_RAM_SEL;
3149
3150/*
3151 * MPCC_MCM_3DLUT_SIZE_ENUM enum
3152 */
3153
3154typedef enum MPCC_MCM_3DLUT_SIZE_ENUM {
3155MPCC_MCM_3DLUT_17CUBE = 0x00000000,
3156MPCC_MCM_3DLUT_9CUBE = 0x00000001,
3157} MPCC_MCM_3DLUT_SIZE_ENUM;
3158
3159/*
3160 * MPCC_MCM_GAMMA_LUT_MODE_ENUM enum
3161 */
3162
3163typedef enum MPCC_MCM_GAMMA_LUT_MODE_ENUM {
3164MPCC_MCM_GAMMA_LUT_BYPASS = 0x00000000,
3165MPCC_MCM_GAMMA_LUT_RESERVED_1 = 0x00000001,
3166MPCC_MCM_GAMMA_LUT_RAM_LUT = 0x00000002,
3167MPCC_MCM_GAMMA_LUT_RESERVED_3 = 0x00000003,
3168} MPCC_MCM_GAMMA_LUT_MODE_ENUM;
3169
3170/*
3171 * MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM enum
3172 */
3173
3174typedef enum MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM {
3175MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0x00000000,
3176MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 0x00000001,
3177} MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM;
3178
3179/*
3180 * MPCC_MCM_GAMMA_LUT_SEL_ENUM enum
3181 */
3182
3183typedef enum MPCC_MCM_GAMMA_LUT_SEL_ENUM {
3184MPCC_MCM_GAMMA_LUT_RAMA = 0x00000000,
3185MPCC_MCM_GAMMA_LUT_RAMB = 0x00000001,
3186} MPCC_MCM_GAMMA_LUT_SEL_ENUM;
3187
3188/*
3189 * MPCC_MCM_LUT_2_MODE_ENUM enum
3190 */
3191
3192typedef enum MPCC_MCM_LUT_2_MODE_ENUM {
3193MPCC_MCM_LUT_2_MODE_BYPASS = 0x00000000,
3194MPCC_MCM_LUT_2_MODE_RAMA_LUT = 0x00000001,
3195MPCC_MCM_LUT_2_MODE_RAMB_LUT = 0x00000002,
3196} MPCC_MCM_LUT_2_MODE_ENUM;
3197
3198/*
3199 * MPCC_MCM_LUT_CONFIG_MODE enum
3200 */
3201
3202typedef enum MPCC_MCM_LUT_CONFIG_MODE {
3203MPCC_MCM_LUT_DIFFERENT_RGB = 0x00000000,
3204MPCC_MCM_LUT_ALL_USE_R = 0x00000001,
3205} MPCC_MCM_LUT_CONFIG_MODE;
3206
3207/*
3208 * MPCC_MCM_LUT_NUM_SEG enum
3209 */
3210
3211typedef enum MPCC_MCM_LUT_NUM_SEG {
3212MPCC_MCM_LUT_SEGMENTS_1 = 0x00000000,
3213MPCC_MCM_LUT_SEGMENTS_2 = 0x00000001,
3214MPCC_MCM_LUT_SEGMENTS_4 = 0x00000002,
3215MPCC_MCM_LUT_SEGMENTS_8 = 0x00000003,
3216MPCC_MCM_LUT_SEGMENTS_16 = 0x00000004,
3217MPCC_MCM_LUT_SEGMENTS_32 = 0x00000005,
3218MPCC_MCM_LUT_SEGMENTS_64 = 0x00000006,
3219MPCC_MCM_LUT_SEGMENTS_128 = 0x00000007,
3220} MPCC_MCM_LUT_NUM_SEG;
3221
3222/*
3223 * MPCC_MCM_LUT_RAM_SEL enum
3224 */
3225
3226typedef enum MPCC_MCM_LUT_RAM_SEL {
3227MPCC_MCM_LUT_RAMA_ACCESS = 0x00000000,
3228MPCC_MCM_LUT_RAMB_ACCESS = 0x00000001,
3229} MPCC_MCM_LUT_RAM_SEL;
3230
3231/*
3232 * MPCC_MCM_LUT_READ_COLOR_SEL enum
3233 */
3234
3235typedef enum MPCC_MCM_LUT_READ_COLOR_SEL {
3236MPCC_MCM_LUT_BLUE_LUT = 0x00000000,
3237MPCC_MCM_LUT_GREEN_LUT = 0x00000001,
3238MPCC_MCM_LUT_RED_LUT = 0x00000002,
3239} MPCC_MCM_LUT_READ_COLOR_SEL;
3240
3241/*
3242 * MPCC_MCM_LUT_READ_DBG enum
3243 */
3244
3245typedef enum MPCC_MCM_LUT_READ_DBG {
3246MPCC_MCM_LUT_DISABLE_DEBUG = 0x00000000,
3247MPCC_MCM_LUT_ENABLE_DEBUG = 0x00000001,
3248} MPCC_MCM_LUT_READ_DBG;
3249
3250/*
3251 * MPCC_MCM_MEM_PWR_FORCE_ENUM enum
3252 */
3253
3254typedef enum MPCC_MCM_MEM_PWR_FORCE_ENUM {
3255MPCC_MCM_MEM_PWR_FORCE_DIS = 0x00000000,
3256MPCC_MCM_MEM_PWR_FORCE_LS = 0x00000001,
3257MPCC_MCM_MEM_PWR_FORCE_DS = 0x00000002,
3258MPCC_MCM_MEM_PWR_FORCE_SD = 0x00000003,
3259} MPCC_MCM_MEM_PWR_FORCE_ENUM;
3260
3261/*
3262 * MPCC_MCM_MEM_PWR_STATE_ENUM enum
3263 */
3264
3265typedef enum MPCC_MCM_MEM_PWR_STATE_ENUM {
3266MPCC_MCM_MEM_PWR_STATE_ON = 0x00000000,
3267MPCC_MCM_MEM_PWR_STATE_LS = 0x00000001,
3268MPCC_MCM_MEM_PWR_STATE_DS = 0x00000002,
3269MPCC_MCM_MEM_PWR_STATE_SD = 0x00000003,
3270} MPCC_MCM_MEM_PWR_STATE_ENUM;
3271
3272/*******************************************************
3273 * ABM Enums
3274 *******************************************************/
3275
3276/*******************************************************
3277 * DPG Enums
3278 *******************************************************/
3279
3280/*
3281 * ENUM_DPG_BIT_DEPTH enum
3282 */
3283
3284typedef enum ENUM_DPG_BIT_DEPTH {
3285ENUM_DPG_BIT_DEPTH_6BPC = 0x00000000,
3286ENUM_DPG_BIT_DEPTH_8BPC = 0x00000001,
3287ENUM_DPG_BIT_DEPTH_10BPC = 0x00000002,
3288ENUM_DPG_BIT_DEPTH_12BPC = 0x00000003,
3289} ENUM_DPG_BIT_DEPTH;
3290
3291/*
3292 * ENUM_DPG_DYNAMIC_RANGE enum
3293 */
3294
3295typedef enum ENUM_DPG_DYNAMIC_RANGE {
3296ENUM_DPG_DYNAMIC_RANGE_VESA = 0x00000000,
3297ENUM_DPG_DYNAMIC_RANGE_CEA = 0x00000001,
3298} ENUM_DPG_DYNAMIC_RANGE;
3299
3300/*
3301 * ENUM_DPG_EN enum
3302 */
3303
3304typedef enum ENUM_DPG_EN {
3305ENUM_DPG_DISABLE = 0x00000000,
3306ENUM_DPG_ENABLE = 0x00000001,
3307} ENUM_DPG_EN;
3308
3309/*
3310 * ENUM_DPG_FIELD_POLARITY enum
3311 */
3312
3313typedef enum ENUM_DPG_FIELD_POLARITY {
3314ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000,
3315ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001,
3316} ENUM_DPG_FIELD_POLARITY;
3317
3318/*
3319 * ENUM_DPG_MODE enum
3320 */
3321
3322typedef enum ENUM_DPG_MODE {
3323ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0x00000000,
3324ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 0x00000001,
3325ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 0x00000002,
3326ENUM_DPG_MODE_VERTICAL_BAR = 0x00000003,
3327ENUM_DPG_MODE_HORIZONTAL_BAR = 0x00000004,
3328ENUM_DPG_MODE_RGB_SINGLE_RAMP = 0x00000005,
3329ENUM_DPG_MODE_RGB_DUAL_RAMP = 0x00000006,
3330ENUM_DPG_MODE_RGB_XR_BIAS = 0x00000007,
3331} ENUM_DPG_MODE;
3332
3333/*******************************************************
3334 * FMT Enums
3335 *******************************************************/
3336
3337/*
3338 * FMTMEM_PWR_DIS_CTRL enum
3339 */
3340
3341typedef enum FMTMEM_PWR_DIS_CTRL {
3342FMTMEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
3343FMTMEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
3344} FMTMEM_PWR_DIS_CTRL;
3345
3346/*
3347 * FMTMEM_PWR_FORCE_CTRL enum
3348 */
3349
3350typedef enum FMTMEM_PWR_FORCE_CTRL {
3351FMTMEM_NO_FORCE_REQUEST = 0x00000000,
3352FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
3353FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
3354FMTMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
3355} FMTMEM_PWR_FORCE_CTRL;
3356
3357/*
3358 * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3359 */
3360
3361typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3362FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000,
3363FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001,
3364FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002,
3365FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003,
3366} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3367
3368/*
3369 * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3370 */
3371
3372typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3373FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000,
3374FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001,
3375FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002,
3376FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003,
3377} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3378
3379/*
3380 * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3381 */
3382
3383typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3384FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000,
3385FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001,
3386FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002,
3387FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003,
3388} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3389
3390/*
3391 * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3392 */
3393
3394typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3395FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000,
3396FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
3397FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002,
3398} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3399
3400/*
3401 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3402 */
3403
3404typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3405FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000,
3406FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001,
3407FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002,
3408} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3409
3410/*
3411 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3412 */
3413
3414typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3415FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000,
3416FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001,
3417} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3418
3419/*
3420 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3421 */
3422
3423typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3424FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000,
3425FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001,
3426FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002,
3427} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3428
3429/*
3430 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3431 */
3432
3433typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3434FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000,
3435FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001,
3436} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3437
3438/*
3439 * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3440 */
3441
3442typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3443FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000,
3444FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001,
3445FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002,
3446FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003,
3447FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004,
3448FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005,
3449FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006,
3450FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007,
3451} FMT_CLAMP_CNTL_COLOR_FORMAT;
3452
3453/*
3454 * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3455 */
3456
3457typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3458FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000,
3459FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001,
3460} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
3461
3462/*
3463 * FMT_CONTROL_PIXEL_ENCODING enum
3464 */
3465
3466typedef enum FMT_CONTROL_PIXEL_ENCODING {
3467FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000,
3468FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001,
3469FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002,
3470FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003,
3471} FMT_CONTROL_PIXEL_ENCODING;
3472
3473/*
3474 * FMT_CONTROL_SUBSAMPLING_MODE enum
3475 */
3476
3477typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3478FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000,
3479FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001,
3480FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002,
3481FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003,
3482} FMT_CONTROL_SUBSAMPLING_MODE;
3483
3484/*
3485 * FMT_CONTROL_SUBSAMPLING_ORDER enum
3486 */
3487
3488typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3489FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000,
3490FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001,
3491} FMT_CONTROL_SUBSAMPLING_ORDER;
3492
3493/*
3494 * FMT_DEBUG_CNTL_COLOR_SELECT enum
3495 */
3496
3497typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3498FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x00000000,
3499FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x00000001,
3500FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x00000002,
3501FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x00000003,
3502} FMT_DEBUG_CNTL_COLOR_SELECT;
3503
3504/*
3505 * FMT_DYNAMIC_EXP_MODE enum
3506 */
3507
3508typedef enum FMT_DYNAMIC_EXP_MODE {
3509FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000,
3510FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001,
3511} FMT_DYNAMIC_EXP_MODE;
3512
3513/*
3514 * FMT_FRAME_RANDOM_ENABLE_CONTROL enum
3515 */
3516
3517typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL {
3518FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0x00000000,
3519FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 0x00000001,
3520} FMT_FRAME_RANDOM_ENABLE_CONTROL;
3521
3522/*
3523 * FMT_POWER_STATE_ENUM enum
3524 */
3525
3526typedef enum FMT_POWER_STATE_ENUM {
3527FMT_POWER_STATE_ENUM_ON = 0x00000000,
3528FMT_POWER_STATE_ENUM_LS = 0x00000001,
3529FMT_POWER_STATE_ENUM_DS = 0x00000002,
3530FMT_POWER_STATE_ENUM_SD = 0x00000003,
3531} FMT_POWER_STATE_ENUM;
3532
3533/*
3534 * FMT_RGB_RANDOM_ENABLE_CONTROL enum
3535 */
3536
3537typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL {
3538FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0x00000000,
3539FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 0x00000001,
3540} FMT_RGB_RANDOM_ENABLE_CONTROL;
3541
3542/*
3543 * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum
3544 */
3545
3546typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL {
3547FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0x00000000,
3548FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 0x00000001,
3549FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 0x00000002,
3550FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 0x00000003,
3551} FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL;
3552
3553/*
3554 * FMT_SPATIAL_DITHER_MODE enum
3555 */
3556
3557typedef enum FMT_SPATIAL_DITHER_MODE {
3558FMT_SPATIAL_DITHER_MODE_0 = 0x00000000,
3559FMT_SPATIAL_DITHER_MODE_1 = 0x00000001,
3560FMT_SPATIAL_DITHER_MODE_2 = 0x00000002,
3561FMT_SPATIAL_DITHER_MODE_3 = 0x00000003,
3562} FMT_SPATIAL_DITHER_MODE;
3563
3564/*
3565 * FMT_STEREOSYNC_OVERRIDE_CONTROL enum
3566 */
3567
3568typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL {
3569FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0x00000000,
3570FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 0x00000001,
3571} FMT_STEREOSYNC_OVERRIDE_CONTROL;
3572
3573/*
3574 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3575 */
3576
3577typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3578FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000,
3579FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001,
3580} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3581
3582/*******************************************************
3583 * OPPBUF Enums
3584 *******************************************************/
3585
3586/*
3587 * OPPBUF_DISPLAY_SEGMENTATION enum
3588 */
3589
3590typedef enum OPPBUF_DISPLAY_SEGMENTATION {
3591OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0x00000000,
3592OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 0x00000001,
3593OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 0x00000002,
3594OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 0x00000003,
3595OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 0x00000004,
3596} OPPBUF_DISPLAY_SEGMENTATION;
3597
3598/*******************************************************
3599 * OPP_PIPE Enums
3600 *******************************************************/
3601
3602/*
3603 * OPP_PIPE_CLOCK_ENABLE_CONTROL enum
3604 */
3605
3606typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL {
3607OPP_PIPE_CLOCK_DISABLE = 0x00000000,
3608OPP_PIPE_CLOCK_ENABLE = 0x00000001,
3609} OPP_PIPE_CLOCK_ENABLE_CONTROL;
3610
3611/*
3612 * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum
3613 */
3614
3615typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL {
3616OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0x00000000,
3617OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 0x00000001,
3618} OPP_PIPE_DIGTIAL_BYPASS_CONTROL;
3619
3620/*******************************************************
3621 * OPP_PIPE_CRC Enums
3622 *******************************************************/
3623
3624/*
3625 * OPP_PIPE_CRC_CONT_EN enum
3626 */
3627
3628typedef enum OPP_PIPE_CRC_CONT_EN {
3629OPP_PIPE_CRC_MODE_ONE_SHOT = 0x00000000,
3630OPP_PIPE_CRC_MODE_CONTINUOUS = 0x00000001,
3631} OPP_PIPE_CRC_CONT_EN;
3632
3633/*
3634 * OPP_PIPE_CRC_EN enum
3635 */
3636
3637typedef enum OPP_PIPE_CRC_EN {
3638OPP_PIPE_CRC_DISABLE = 0x00000000,
3639OPP_PIPE_CRC_ENABLE = 0x00000001,
3640} OPP_PIPE_CRC_EN;
3641
3642/*
3643 * OPP_PIPE_CRC_INTERLACE_EN enum
3644 */
3645
3646typedef enum OPP_PIPE_CRC_INTERLACE_EN {
3647OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0x00000000,
3648OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 0x00000001,
3649} OPP_PIPE_CRC_INTERLACE_EN;
3650
3651/*
3652 * OPP_PIPE_CRC_INTERLACE_MODE enum
3653 */
3654
3655typedef enum OPP_PIPE_CRC_INTERLACE_MODE {
3656OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0x00000000,
3657OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
3658OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 0x00000002,
3659OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 0x00000003,
3660} OPP_PIPE_CRC_INTERLACE_MODE;
3661
3662/*
3663 * OPP_PIPE_CRC_ONE_SHOT_PENDING enum
3664 */
3665
3666typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING {
3667OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0x00000000,
3668OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 0x00000001,
3669} OPP_PIPE_CRC_ONE_SHOT_PENDING;
3670
3671/*
3672 * OPP_PIPE_CRC_PIXEL_SELECT enum
3673 */
3674
3675typedef enum OPP_PIPE_CRC_PIXEL_SELECT {
3676OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0x00000000,
3677OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 0x00000001,
3678OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 0x00000002,
3679OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 0x00000003,
3680} OPP_PIPE_CRC_PIXEL_SELECT;
3681
3682/*
3683 * OPP_PIPE_CRC_SOURCE_SELECT enum
3684 */
3685
3686typedef enum OPP_PIPE_CRC_SOURCE_SELECT {
3687OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0x00000000,
3688OPP_PIPE_CRC_SOURCE_SELECT_SFT = 0x00000001,
3689} OPP_PIPE_CRC_SOURCE_SELECT;
3690
3691/*
3692 * OPP_PIPE_CRC_STEREO_EN enum
3693 */
3694
3695typedef enum OPP_PIPE_CRC_STEREO_EN {
3696OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0x00000000,
3697OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 0x00000001,
3698} OPP_PIPE_CRC_STEREO_EN;
3699
3700/*
3701 * OPP_PIPE_CRC_STEREO_MODE enum
3702 */
3703
3704typedef enum OPP_PIPE_CRC_STEREO_MODE {
3705OPP_PIPE_CRC_STEREO_MODE_LEFT = 0x00000000,
3706OPP_PIPE_CRC_STEREO_MODE_RIGHT = 0x00000001,
3707OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 0x00000002,
3708OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 0x00000003,
3709} OPP_PIPE_CRC_STEREO_MODE;
3710
3711/*******************************************************
3712 * OPP_TOP Enums
3713 *******************************************************/
3714
3715/*
3716 * OPP_ABM_DEBUG_BUS_SELECT_CONTROL enum
3717 */
3718
3719typedef enum OPP_ABM_DEBUG_BUS_SELECT_CONTROL {
3720DEBUG_BUS_SELECT_ABM0 = 0x00000000,
3721DEBUG_BUS_SELECT_ABM1 = 0x00000001,
3722DEBUG_BUS_SELECT_ABM2 = 0x00000002,
3723DEBUG_BUS_SELECT_ABM3 = 0x00000003,
3724DEBUG_BUS_SELECT_ABM_RESERVED0 = 0x00000004,
3725DEBUG_BUS_SELECT_ABM_RESERVED1 = 0x00000005,
3726} OPP_ABM_DEBUG_BUS_SELECT_CONTROL;
3727
3728/*
3729 * OPP_DPG_DEBUG_BUS_SELECT_CONTROL enum
3730 */
3731
3732typedef enum OPP_DPG_DEBUG_BUS_SELECT_CONTROL {
3733DEBUG_BUS_SELECT_DPG0 = 0x00000000,
3734DEBUG_BUS_SELECT_DPG1 = 0x00000001,
3735DEBUG_BUS_SELECT_DPG2 = 0x00000002,
3736DEBUG_BUS_SELECT_DPG3 = 0x00000003,
3737DEBUG_BUS_SELECT_DPG_RESERVED0 = 0x00000004,
3738DEBUG_BUS_SELECT_DPG_RESERVED1 = 0x00000005,
3739} OPP_DPG_DEBUG_BUS_SELECT_CONTROL;
3740
3741/*
3742 * OPP_FMT_DEBUG_BUS_SELECT_CONTROL enum
3743 */
3744
3745typedef enum OPP_FMT_DEBUG_BUS_SELECT_CONTROL {
3746DEBUG_BUS_SELECT_FMT0 = 0x00000000,
3747DEBUG_BUS_SELECT_FMT1 = 0x00000001,
3748DEBUG_BUS_SELECT_FMT2 = 0x00000002,
3749DEBUG_BUS_SELECT_FMT3 = 0x00000003,
3750DEBUG_BUS_SELECT_FMT_RESERVED0 = 0x00000004,
3751DEBUG_BUS_SELECT_FMT_RESERVED1 = 0x00000005,
3752} OPP_FMT_DEBUG_BUS_SELECT_CONTROL;
3753
3754/*
3755 * OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL enum
3756 */
3757
3758typedef enum OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL {
3759DEBUG_BUS_SELECT_OPPBUF0 = 0x00000000,
3760DEBUG_BUS_SELECT_OPPBUF1 = 0x00000001,
3761DEBUG_BUS_SELECT_OPPBUF2 = 0x00000002,
3762DEBUG_BUS_SELECT_OPPBUF3 = 0x00000003,
3763DEBUG_BUS_SELECT_OPPBUF_RESERVED0 = 0x00000004,
3764DEBUG_BUS_SELECT_OPPBUF_RESERVED1 = 0x00000005,
3765} OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL;
3766
3767/*
3768 * OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL enum
3769 */
3770
3771typedef enum OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL {
3772DEBUG_BUS_SELECT_OPP_PIPE0 = 0x00000000,
3773DEBUG_BUS_SELECT_OPP_PIPE1 = 0x00000001,
3774DEBUG_BUS_SELECT_OPP_PIPE2 = 0x00000002,
3775DEBUG_BUS_SELECT_OPP_PIPE3 = 0x00000003,
3776DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0 = 0x00000004,
3777DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1 = 0x00000005,
3778} OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL;
3779
3780/*
3781 * OPP_TEST_CLK_SEL_CONTROL enum
3782 */
3783
3784typedef enum OPP_TEST_CLK_SEL_CONTROL {
3785OPP_TEST_CLK_SEL_DISPCLK_P = 0x00000000,
3786OPP_TEST_CLK_SEL_DISPCLK_R = 0x00000001,
3787OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 0x00000002,
3788OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 0x00000003,
3789OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 0x00000004,
3790OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 0x00000005,
3791OPP_TEST_CLK_SEL_RESERVED0 = 0x00000006,
3792OPP_TEST_CLK_SEL_RESERVED1 = 0x00000007,
3793OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 0x00000008,
3794OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 0x00000009,
3795OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 0x0000000a,
3796OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 0x0000000b,
3797OPP_TEST_CLK_SEL_RESERVED2 = 0x0000000c,
3798OPP_TEST_CLK_SEL_RESERVED3 = 0x0000000d,
3799} OPP_TEST_CLK_SEL_CONTROL;
3800
3801/*
3802 * OPP_TOP_CLOCK_ENABLE_STATUS enum
3803 */
3804
3805typedef enum OPP_TOP_CLOCK_ENABLE_STATUS {
3806OPP_TOP_CLOCK_DISABLED_STATUS = 0x00000000,
3807OPP_TOP_CLOCK_ENABLED_STATUS = 0x00000001,
3808} OPP_TOP_CLOCK_ENABLE_STATUS;
3809
3810/*
3811 * OPP_TOP_CLOCK_GATING_CONTROL enum
3812 */
3813
3814typedef enum OPP_TOP_CLOCK_GATING_CONTROL {
3815OPP_TOP_CLOCK_GATING_ENABLED = 0x00000000,
3816OPP_TOP_CLOCK_GATING_DISABLED = 0x00000001,
3817} OPP_TOP_CLOCK_GATING_CONTROL;
3818
3819/*******************************************************
3820 * DSCRM Enums
3821 *******************************************************/
3822
3823/*
3824 * ENUM_DSCRM_EN enum
3825 */
3826
3827typedef enum ENUM_DSCRM_EN {
3828ENUM_DSCRM_DISABLE = 0x00000000,
3829ENUM_DSCRM_ENABLE = 0x00000001,
3830} ENUM_DSCRM_EN;
3831
3832/*******************************************************
3833 * OTG Enums
3834 *******************************************************/
3835
3836/*
3837 * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
3838 */
3839
3840typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
3841MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
3842MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
3843} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
3844
3845/*
3846 * MASTER_UPDATE_LOCK_SEL enum
3847 */
3848
3849typedef enum MASTER_UPDATE_LOCK_SEL {
3850MASTER_UPDATE_LOCK_SEL_0 = 0x00000000,
3851MASTER_UPDATE_LOCK_SEL_1 = 0x00000001,
3852MASTER_UPDATE_LOCK_SEL_2 = 0x00000002,
3853MASTER_UPDATE_LOCK_SEL_3 = 0x00000003,
3854MASTER_UPDATE_LOCK_SEL_RESERVED4 = 0x00000004,
3855MASTER_UPDATE_LOCK_SEL_RESERVED5 = 0x00000005,
3856} MASTER_UPDATE_LOCK_SEL;
3857
3858/*
3859 * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
3860 */
3861
3862typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
3863MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000,
3864MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 0x00000001,
3865MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 0x00000002,
3866MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003,
3867} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
3868
3869/*
3870 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum
3871 */
3872
3873typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN {
3874OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0x00000000,
3875OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 0x00000001,
3876} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN;
3877
3878/*
3879 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum
3880 */
3881
3882typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB {
3883OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0x00000000,
3884OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 0x00000001,
3885} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB;
3886
3887/*
3888 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum
3889 */
3890
3891typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR {
3892OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000,
3893OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001,
3894} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR;
3895
3896/*
3897 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum
3898 */
3899
3900typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE {
3901OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000,
3902OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001,
3903OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002,
3904OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003,
3905} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE;
3906
3907/*
3908 * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum
3909 */
3910
3911typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL {
3912OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0x00000000,
3913OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001,
3914OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 0x00000002,
3915OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003,
3916} OTG_CONTROL_OTG_DISABLE_POINT_CNTL;
3917
3918/*
3919 * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum
3920 */
3921
3922typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL {
3923OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
3924OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 0x00000001,
3925} OTG_CONTROL_OTG_FIELD_NUMBER_CNTL;
3926
3927/*
3928 * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum
3929 */
3930
3931typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY {
3932OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0x00000000,
3933OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 0x00000001,
3934} OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY;
3935
3936/*
3937 * OTG_CONTROL_OTG_MASTER_EN enum
3938 */
3939
3940typedef enum OTG_CONTROL_OTG_MASTER_EN {
3941OTG_CONTROL_OTG_MASTER_EN_FALSE = 0x00000000,
3942OTG_CONTROL_OTG_MASTER_EN_TRUE = 0x00000001,
3943} OTG_CONTROL_OTG_MASTER_EN;
3944
3945/*
3946 * OTG_CONTROL_OTG_OUT_MUX enum
3947 */
3948
3949typedef enum OTG_CONTROL_OTG_OUT_MUX {
3950OTG_CONTROL_OTG_OUT_MUX_0 = 0x00000000,
3951OTG_CONTROL_OTG_OUT_MUX_1 = 0x00000001,
3952OTG_CONTROL_OTG_OUT_MUX_2 = 0x00000002,
3953} OTG_CONTROL_OTG_OUT_MUX;
3954
3955/*
3956 * OTG_CONTROL_OTG_START_POINT_CNTL enum
3957 */
3958
3959typedef enum OTG_CONTROL_OTG_START_POINT_CNTL {
3960OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0x00000000,
3961OTG_CONTROL_OTG_START_POINT_CNTL_DP = 0x00000001,
3962} OTG_CONTROL_OTG_START_POINT_CNTL;
3963
3964/*
3965 * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum
3966 */
3967
3968typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN {
3969OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0x00000000,
3970OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 0x00000001,
3971} OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN;
3972
3973/*
3974 * OTG_CRC_CNTL_OTG_CRC1_EN enum
3975 */
3976
3977typedef enum OTG_CRC_CNTL_OTG_CRC1_EN {
3978OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0x00000000,
3979OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 0x00000001,
3980} OTG_CRC_CNTL_OTG_CRC1_EN;
3981
3982/*
3983 * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum
3984 */
3985
3986typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN {
3987OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0x00000000,
3988OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 0x00000001,
3989} OTG_CRC_CNTL_OTG_CRC_CONT_EN;
3990
3991/*
3992 * OTG_CRC_CNTL_OTG_CRC_CONT_MODE enum
3993 */
3994
3995typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_MODE {
3996OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0x00000000,
3997OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 0x00000001,
3998} OTG_CRC_CNTL_OTG_CRC_CONT_MODE;
3999
4000/*
4001 * OTG_CRC_CNTL_OTG_CRC_EN enum
4002 */
4003
4004typedef enum OTG_CRC_CNTL_OTG_CRC_EN {
4005OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0x00000000,
4006OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 0x00000001,
4007} OTG_CRC_CNTL_OTG_CRC_EN;
4008
4009/*
4010 * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum
4011 */
4012
4013typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE {
4014OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0x00000000,
4015OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
4016OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
4017OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003,
4018} OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE;
4019
4020/*
4021 * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum
4022 */
4023
4024typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE {
4025OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0x00000000,
4026OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 0x00000001,
4027OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 0x00000002,
4028OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003,
4029} OTG_CRC_CNTL_OTG_CRC_STEREO_MODE;
4030
4031/*
4032 * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum
4033 */
4034
4035typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS {
4036OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
4037OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001,
4038} OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS;
4039
4040/*
4041 * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum
4042 */
4043
4044typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT {
4045OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0x00000000,
4046OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 0x00000001,
4047OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 0x00000002,
4048OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 0x00000003,
4049OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 0x00000004,
4050OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 0x00000005,
4051OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 0x00000006,
4052OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 0x00000007,
4053} OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT;
4054
4055/*
4056 * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum
4057 */
4058
4059typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT {
4060OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0x00000000,
4061OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 0x00000001,
4062OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 0x00000002,
4063OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 0x00000003,
4064OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 0x00000004,
4065OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 0x00000005,
4066OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 0x00000006,
4067OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 0x00000007,
4068} OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT;
4069
4070/*
4071 * OTG_DIG_UPDATE_VCOUNT_MODE enum
4072 */
4073
4074typedef enum OTG_DIG_UPDATE_VCOUNT_MODE {
4075OTG_DIG_UPDATE_VCOUNT_0 = 0x00000000,
4076OTG_DIG_UPDATE_VCOUNT_1 = 0x00000001,
4077} OTG_DIG_UPDATE_VCOUNT_MODE;
4078
4079/*
4080 * OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE enum
4081 */
4082
4083typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE {
4084OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000,
4085OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001,
4086OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 0x00000002,
4087OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 0x00000003,
4088} OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE;
4089
4090/*
4091 * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum
4092 */
4093
4094typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY {
4095OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0x00000000,
4096OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 0x00000001,
4097} OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY;
4098
4099/*
4100 * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum
4101 */
4102
4103typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME {
4104OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0x00000000,
4105OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 0x00000001,
4106OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 0x00000002,
4107OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 0x00000003,
4108} OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME;
4109
4110/*
4111 * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum
4112 */
4113
4114typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN {
4115OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0x00000000,
4116OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 0x00000001,
4117} OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN;
4118
4119/*
4120 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum
4121 */
4122
4123typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY {
4124OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000,
4125OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001,
4126} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY;
4127
4128/*
4129 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum
4130 */
4131
4132typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY {
4133OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0x00000000,
4134OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 0x00000001,
4135} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY;
4136
4137/*
4138 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum
4139 */
4140
4141typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT {
4142OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000,
4143OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x00000001,
4144OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x00000002,
4145OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x00000003,
4146OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x00000004,
4147OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x00000005,
4148OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000006,
4149OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000007,
4150OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000008,
4151OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000009,
4152OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x0000000a,
4153OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x0000000b,
4154OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x0000000c,
4155OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x0000000d,
4156OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x0000000e,
4157OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 0x0000000f,
4158OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 0x00000010,
4159OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 0x00000011,
4160OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 0x00000012,
4161OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 0x00000013,
4162} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT;
4163
4164/*
4165 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum
4166 */
4167
4168typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK {
4169OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000,
4170OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001,
4171} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK;
4172
4173/*
4174 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum
4175 */
4176
4177typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR {
4178OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
4179OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001,
4180} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR;
4181
4182/*
4183 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum
4184 */
4185
4186typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE {
4187OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000,
4188OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001,
4189OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002,
4190OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003,
4191} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE;
4192
4193/*
4194 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum
4195 */
4196
4197typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL {
4198OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000,
4199OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001,
4200} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL;
4201
4202/*
4203 * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum
4204 */
4205
4206typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL {
4207OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0x00000000,
4208OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 0x00000001,
4209OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 0x00000002,
4210OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 0x00000003,
4211OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 0x00000004,
4212OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 0x00000005,
4213} OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL;
4214
4215/*
4216 * OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL enum
4217 */
4218
4219typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL {
4220DIG_UPDATE_EYE_SEL_BOTH = 0x00000000,
4221DIG_UPDATE_EYE_SEL_LEFT = 0x00000001,
4222DIG_UPDATE_EYE_SEL_RIGHT = 0x00000002,
4223} OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL;
4224
4225/*
4226 * OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL enum
4227 */
4228
4229typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL {
4230DIG_UPDATE_FIELD_SEL_BOTH = 0x00000000,
4231DIG_UPDATE_FIELD_SEL_TOP = 0x00000001,
4232DIG_UPDATE_FIELD_SEL_BOTTOM = 0x00000002,
4233DIG_UPDATE_FIELD_SEL_RESERVED = 0x00000003,
4234} OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL;
4235
4236/*
4237 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum
4238 */
4239
4240typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD {
4241MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0x00000000,
4242MASTER_UPDATE_LOCK_DB_FIELD_TOP = 0x00000001,
4243MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 0x00000002,
4244MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 0x00000003,
4245} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD;
4246
4247/*
4248 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum
4249 */
4250
4251typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL {
4252MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0x00000000,
4253MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 0x00000001,
4254MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 0x00000002,
4255MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 0x00000003,
4256} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL;
4257
4258/*
4259 * OTG_GLOBAL_UPDATE_LOCK_EN enum
4260 */
4261
4262typedef enum OTG_GLOBAL_UPDATE_LOCK_EN {
4263OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0x00000000,
4264OTG_GLOBAL_UPDATE_LOCK_ENABLE = 0x00000001,
4265} OTG_GLOBAL_UPDATE_LOCK_EN;
4266
4267/*
4268 * OTG_GSL_MASTER_MODE enum
4269 */
4270
4271typedef enum OTG_GSL_MASTER_MODE {
4272OTG_GSL_MASTER_MODE_0 = 0x00000000,
4273OTG_GSL_MASTER_MODE_1 = 0x00000001,
4274OTG_GSL_MASTER_MODE_2 = 0x00000002,
4275OTG_GSL_MASTER_MODE_3 = 0x00000003,
4276} OTG_GSL_MASTER_MODE;
4277
4278/*
4279 * OTG_HORZ_REPETITION_COUNT enum
4280 */
4281
4282typedef enum OTG_HORZ_REPETITION_COUNT {
4283OTG_HORZ_REPETITION_COUNT_0 = 0x00000000,
4284OTG_HORZ_REPETITION_COUNT_1 = 0x00000001,
4285OTG_HORZ_REPETITION_COUNT_2 = 0x00000002,
4286OTG_HORZ_REPETITION_COUNT_3 = 0x00000003,
4287OTG_HORZ_REPETITION_COUNT_4 = 0x00000004,
4288OTG_HORZ_REPETITION_COUNT_5 = 0x00000005,
4289OTG_HORZ_REPETITION_COUNT_6 = 0x00000006,
4290OTG_HORZ_REPETITION_COUNT_7 = 0x00000007,
4291OTG_HORZ_REPETITION_COUNT_8 = 0x00000008,
4292OTG_HORZ_REPETITION_COUNT_9 = 0x00000009,
4293OTG_HORZ_REPETITION_COUNT_10 = 0x0000000a,
4294OTG_HORZ_REPETITION_COUNT_11 = 0x0000000b,
4295OTG_HORZ_REPETITION_COUNT_12 = 0x0000000c,
4296OTG_HORZ_REPETITION_COUNT_13 = 0x0000000d,
4297OTG_HORZ_REPETITION_COUNT_14 = 0x0000000e,
4298OTG_HORZ_REPETITION_COUNT_15 = 0x0000000f,
4299} OTG_HORZ_REPETITION_COUNT;
4300
4301/*
4302 * OTG_H_SYNC_A_POL enum
4303 */
4304
4305typedef enum OTG_H_SYNC_A_POL {
4306OTG_H_SYNC_A_POL_HIGH = 0x00000000,
4307OTG_H_SYNC_A_POL_LOW = 0x00000001,
4308} OTG_H_SYNC_A_POL;
4309
4310/*
4311 * OTG_H_TIMING_DIV_MODE enum
4312 */
4313
4314typedef enum OTG_H_TIMING_DIV_MODE {
4315OTG_H_TIMING_DIV_MODE_NO_DIV = 0x00000000,
4316OTG_H_TIMING_DIV_MODE_DIV_BY2 = 0x00000001,
4317OTG_H_TIMING_DIV_MODE_RESERVED = 0x00000002,
4318OTG_H_TIMING_DIV_MODE_DIV_BY4 = 0x00000003,
4319} OTG_H_TIMING_DIV_MODE;
4320
4321/*
4322 * OTG_H_TIMING_DIV_MODE_MANUAL enum
4323 */
4324
4325typedef enum OTG_H_TIMING_DIV_MODE_MANUAL {
4326OTG_H_TIMING_DIV_MODE_AUTO = 0x00000000,
4327OTG_H_TIMING_DIV_MODE_NOAUTO = 0x00000001,
4328} OTG_H_TIMING_DIV_MODE_MANUAL;
4329
4330/*
4331 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum
4332 */
4333
4334typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE {
4335OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0x00000000,
4336OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 0x00000001,
4337} OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE;
4338
4339/*
4340 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum
4341 */
4342
4343typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD {
4344OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000,
4345OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 0x00000001,
4346OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 0x00000002,
4347OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003,
4348} OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD;
4349
4350/*
4351 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum
4352 */
4353
4354typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK {
4355OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000,
4356OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001,
4357} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK;
4358
4359/*
4360 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum
4361 */
4362
4363typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE {
4364OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000,
4365OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001,
4366} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE;
4367
4368/*
4369 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
4370 */
4371
4372typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK {
4373OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000,
4374OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001,
4375} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK;
4376
4377/*
4378 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
4379 */
4380
4381typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
4382OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000,
4383OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001,
4384} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
4385
4386/*
4387 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum
4388 */
4389
4390typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK {
4391OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000,
4392OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001,
4393} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK;
4394
4395/*
4396 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum
4397 */
4398
4399typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE {
4400OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000,
4401OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001,
4402} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE;
4403
4404/*
4405 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum
4406 */
4407
4408typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK {
4409OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0x00000000,
4410OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 0x00000001,
4411} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK;
4412
4413/*
4414 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum
4415 */
4416
4417typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE {
4418OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0x00000000,
4419OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 0x00000001,
4420} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE;
4421
4422/*
4423 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum
4424 */
4425
4426typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK {
4427OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0x00000000,
4428OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 0x00000001,
4429} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK;
4430
4431/*
4432 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum
4433 */
4434
4435typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE {
4436OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0x00000000,
4437OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 0x00000001,
4438} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE;
4439
4440/*
4441 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum
4442 */
4443
4444typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK {
4445OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0x00000000,
4446OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 0x00000001,
4447} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK;
4448
4449/*
4450 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum
4451 */
4452
4453typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE {
4454OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0x00000000,
4455OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 0x00000001,
4456} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE;
4457
4458/*
4459 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum
4460 */
4461
4462typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK {
4463OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0x00000000,
4464OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 0x00000001,
4465} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK;
4466
4467/*
4468 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum
4469 */
4470
4471typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE {
4472OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000,
4473OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001,
4474} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE;
4475
4476/*
4477 * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum
4478 */
4479
4480typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE {
4481OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
4482OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001,
4483} OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE;
4484
4485/*
4486 * OTG_MASTER_UPDATE_LOCK_DB_EN enum
4487 */
4488
4489typedef enum OTG_MASTER_UPDATE_LOCK_DB_EN {
4490OTG_MASTER_UPDATE_LOCK_DISABLE = 0x00000000,
4491OTG_MASTER_UPDATE_LOCK_ENABLE = 0x00000001,
4492} OTG_MASTER_UPDATE_LOCK_DB_EN;
4493
4494/*
4495 * OTG_MASTER_UPDATE_LOCK_GSL_EN enum
4496 */
4497
4498typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN {
4499OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0x00000000,
4500OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 0x00000001,
4501} OTG_MASTER_UPDATE_LOCK_GSL_EN;
4502
4503/*
4504 * OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE enum
4505 */
4506
4507typedef enum OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE {
4508OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0x00000000,
4509OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 0x00000001,
4510} OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE;
4511
4512/*
4513 * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum
4514 */
4515
4516typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL {
4517OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000,
4518OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001,
4519OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002,
4520OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003,
4521} OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL;
4522
4523/*
4524 * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum
4525 */
4526
4527typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR {
4528OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0x00000000,
4529OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 0x00000001,
4530} OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR;
4531
4532/*
4533 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum
4534 */
4535
4536typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR {
4537OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
4538OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 0x00000001,
4539} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR;
4540
4541/*
4542 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum
4543 */
4544
4545typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE {
4546OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0x00000000,
4547OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 0x00000001,
4548} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE;
4549
4550/*
4551 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum
4552 */
4553
4554typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE {
4555OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0x00000000,
4556OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 0x00000001,
4557} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE;
4558
4559/*
4560 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum
4561 */
4562
4563typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE {
4564OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000,
4565OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001,
4566} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE;
4567
4568/*
4569 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum
4570 */
4571
4572typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE {
4573OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000,
4574OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001,
4575} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE;
4576
4577/*
4578 * OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL enum
4579 */
4580
4581typedef enum OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL {
4582OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0x00000000,
4583OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 0x00000001,
4584} OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL;
4585
4586/*
4587 * OTG_STEREO_CONTROL_OTG_STEREO_EN enum
4588 */
4589
4590typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN {
4591OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0x00000000,
4592OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 0x00000001,
4593} OTG_STEREO_CONTROL_OTG_STEREO_EN;
4594
4595/*
4596 * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum
4597 */
4598
4599typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY {
4600OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000,
4601OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001,
4602} OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY;
4603
4604/*
4605 * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum
4606 */
4607
4608typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY {
4609OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000,
4610OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001,
4611} OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY;
4612
4613/*
4614 * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum
4615 */
4616
4617typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE {
4618OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0x00000000,
4619OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001,
4620OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002,
4621OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003,
4622} OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE;
4623
4624/*
4625 * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum
4626 */
4627
4628typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR {
4629OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0x00000000,
4630OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 0x00000001,
4631} OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR;
4632
4633/*
4634 * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum
4635 */
4636
4637typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT {
4638OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0x00000000,
4639OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001,
4640OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002,
4641OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003,
4642OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004,
4643OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 0x00000005,
4644OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 0x00000006,
4645OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 0x00000007,
4646} OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT;
4647
4648/*
4649 * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum
4650 */
4651
4652typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN {
4653OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000,
4654OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001,
4655} OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN;
4656
4657/*
4658 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum
4659 */
4660
4661typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT {
4662OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0x00000000,
4663OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 0x00000001,
4664OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 0x00000002,
4665OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 0x00000003,
4666OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004,
4667OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005,
4668} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT;
4669
4670/*
4671 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum
4672 */
4673
4674typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT {
4675OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0x00000000,
4676OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 0x00000001,
4677OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 0x00000002,
4678OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 0x00000003,
4679OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 0x00000004,
4680OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 0x00000005,
4681OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 0x00000006,
4682OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007,
4683OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008,
4684OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009,
4685OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a,
4686OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b,
4687OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c,
4688OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d,
4689OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 0x0000000e,
4690OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f,
4691OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010,
4692OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 0x00000011,
4693OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 0x00000012,
4694OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 0x00000013,
4695OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 0x00000014,
4696OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015,
4697OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016,
4698OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 0x00000017,
4699OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 0x00000018,
4700} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT;
4701
4702/*
4703 * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum
4704 */
4705
4706typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL {
4707OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000,
4708OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001,
4709OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002,
4710OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003,
4711} OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;
4712
4713/*
4714 * OTG_TRIGA_FREQUENCY_SELECT enum
4715 */
4716
4717typedef enum OTG_TRIGA_FREQUENCY_SELECT {
4718OTG_TRIGA_FREQUENCY_SELECT_0 = 0x00000000,
4719OTG_TRIGA_FREQUENCY_SELECT_1 = 0x00000001,
4720OTG_TRIGA_FREQUENCY_SELECT_2 = 0x00000002,
4721OTG_TRIGA_FREQUENCY_SELECT_3 = 0x00000003,
4722} OTG_TRIGA_FREQUENCY_SELECT;
4723
4724/*
4725 * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum
4726 */
4727
4728typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL {
4729OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0x00000000,
4730OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 0x00000001,
4731OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 0x00000002,
4732OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 0x00000003,
4733} OTG_TRIGA_RISING_EDGE_DETECT_CNTL;
4734
4735/*
4736 * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum
4737 */
4738
4739typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR {
4740OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0x00000000,
4741OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 0x00000001,
4742} OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR;
4743
4744/*
4745 * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum
4746 */
4747
4748typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT {
4749OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0x00000000,
4750OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001,
4751OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002,
4752OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003,
4753OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004,
4754OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 0x00000005,
4755OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 0x00000006,
4756OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 0x00000007,
4757} OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT;
4758
4759/*
4760 * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum
4761 */
4762
4763typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN {
4764OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000,
4765OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001,
4766} OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN;
4767
4768/*
4769 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum
4770 */
4771
4772typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT {
4773OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0x00000000,
4774OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 0x00000001,
4775OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 0x00000002,
4776OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 0x00000003,
4777OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004,
4778OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005,
4779} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT;
4780
4781/*
4782 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum
4783 */
4784
4785typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT {
4786OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0x00000000,
4787OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 0x00000001,
4788OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 0x00000002,
4789OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 0x00000003,
4790OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 0x00000004,
4791OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 0x00000005,
4792OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 0x00000006,
4793OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007,
4794OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008,
4795OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009,
4796OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a,
4797OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b,
4798OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c,
4799OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d,
4800OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 0x0000000e,
4801OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f,
4802OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010,
4803OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 0x00000011,
4804OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 0x00000012,
4805OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 0x00000013,
4806OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 0x00000014,
4807OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015,
4808OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016,
4809OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 0x00000017,
4810OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 0x00000018,
4811} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT;
4812
4813/*
4814 * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum
4815 */
4816
4817typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL {
4818OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000,
4819OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001,
4820OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002,
4821OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003,
4822} OTG_TRIGB_FALLING_EDGE_DETECT_CNTL;
4823
4824/*
4825 * OTG_TRIGB_FREQUENCY_SELECT enum
4826 */
4827
4828typedef enum OTG_TRIGB_FREQUENCY_SELECT {
4829OTG_TRIGB_FREQUENCY_SELECT_0 = 0x00000000,
4830OTG_TRIGB_FREQUENCY_SELECT_1 = 0x00000001,
4831OTG_TRIGB_FREQUENCY_SELECT_2 = 0x00000002,
4832OTG_TRIGB_FREQUENCY_SELECT_3 = 0x00000003,
4833} OTG_TRIGB_FREQUENCY_SELECT;
4834
4835/*
4836 * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum
4837 */
4838
4839typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL {
4840OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0x00000000,
4841OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 0x00000001,
4842OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 0x00000002,
4843OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 0x00000003,
4844} OTG_TRIGB_RISING_EDGE_DETECT_CNTL;
4845
4846/*
4847 * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum
4848 */
4849
4850typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK {
4851OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0x00000000,
4852OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 0x00000001,
4853} OTG_UPDATE_LOCK_OTG_UPDATE_LOCK;
4854
4855/*
4856 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum
4857 */
4858
4859typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR {
4860OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
4861OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001,
4862} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR;
4863
4864/*
4865 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum
4866 */
4867
4868typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE {
4869OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
4870OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001,
4871} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE;
4872
4873/*
4874 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum
4875 */
4876
4877typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE {
4878OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000,
4879OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001,
4880} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE;
4881
4882/*
4883 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
4884 */
4885
4886typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
4887OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000,
4888OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001,
4889} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
4890
4891/*
4892 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum
4893 */
4894
4895typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR {
4896OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
4897OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001,
4898} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR;
4899
4900/*
4901 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum
4902 */
4903
4904typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE {
4905OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
4906OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001,
4907} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE;
4908
4909/*
4910 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum
4911 */
4912
4913typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE {
4914OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000,
4915OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001,
4916} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE;
4917
4918/*
4919 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum
4920 */
4921
4922typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR {
4923OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
4924OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001,
4925} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR;
4926
4927/*
4928 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum
4929 */
4930
4931typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE {
4932OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
4933OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001,
4934} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE;
4935
4936/*
4937 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum
4938 */
4939
4940typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE {
4941OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000,
4942OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001,
4943} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE;
4944
4945/*
4946 * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum
4947 */
4948
4949typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE {
4950OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000,
4951OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001,
4952OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002,
4953OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003,
4954} OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE;
4955
4956/*
4957 * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum
4958 */
4959
4960typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR {
4961OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
4962OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001,
4963} OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;
4964
4965/*
4966 * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum
4967 */
4968
4969typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR {
4970OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
4971OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001,
4972} OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR;
4973
4974/*
4975 * OTG_VUPDATE_BLOCK_DISABLE enum
4976 */
4977
4978typedef enum OTG_VUPDATE_BLOCK_DISABLE {
4979OTG_VUPDATE_BLOCK_DISABLE_OFF = 0x00000000,
4980OTG_VUPDATE_BLOCK_DISABLE_ON = 0x00000001,
4981} OTG_VUPDATE_BLOCK_DISABLE;
4982
4983/*
4984 * OTG_V_SYNC_A_POL enum
4985 */
4986
4987typedef enum OTG_V_SYNC_A_POL {
4988OTG_V_SYNC_A_POL_HIGH = 0x00000000,
4989OTG_V_SYNC_A_POL_LOW = 0x00000001,
4990} OTG_V_SYNC_A_POL;
4991
4992/*
4993 * OTG_V_SYNC_MODE enum
4994 */
4995
4996typedef enum OTG_V_SYNC_MODE {
4997OTG_V_SYNC_MODE_HSYNC = 0x00000000,
4998OTG_V_SYNC_MODE_HBLANK = 0x00000001,
4999} OTG_V_SYNC_MODE;
5000
5001/*
5002 * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum
5003 */
5004
5005typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD {
5006OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0x00000000,
5007OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 0x00000001,
5008} OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD;
5009
5010/*
5011 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum
5012 */
5013
5014typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT {
5015OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
5016OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001,
5017} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT;
5018
5019/*
5020 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum
5021 */
5022
5023typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC {
5024OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
5025OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001,
5026} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC;
5027
5028/*
5029 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum
5030 */
5031
5032typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL {
5033OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0x00000000,
5034OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 0x00000001,
5035} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL;
5036
5037/*
5038 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum
5039 */
5040
5041typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL {
5042OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0x00000000,
5043OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 0x00000001,
5044} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL;
5045
5046/*
5047 * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK enum
5048 */
5049
5050typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK {
5051OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0x00000000,
5052OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 0x00000001,
5053} OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK;
5054
5055/*******************************************************
5056 * OPTC_MISC Enums
5057 *******************************************************/
5058
5059/*
5060 * OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL enum
5061 */
5062
5063typedef enum OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL {
5064OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0x00000000,
5065OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 0x00000001,
5066OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 0x00000002,
5067OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 0x00000003,
5068OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 0x00000004,
5069OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 0x00000005,
5070} OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL;
5071
5072/*******************************************************
5073 * DMCUB Enums
5074 *******************************************************/
5075
5076/*
5077 * DC_DMCUB_INT_TYPE enum
5078 */
5079
5080typedef enum DC_DMCUB_INT_TYPE {
5081INT_LEVEL = 0x00000000,
5082INT_PULSE = 0x00000001,
5083} DC_DMCUB_INT_TYPE;
5084
5085/*
5086 * DC_DMCUB_TIMER_WINDOW enum
5087 */
5088
5089typedef enum DC_DMCUB_TIMER_WINDOW {
5090BITS_31_0 = 0x00000000,
5091BITS_32_1 = 0x00000001,
5092BITS_33_2 = 0x00000002,
5093BITS_34_3 = 0x00000003,
5094BITS_35_4 = 0x00000004,
5095BITS_36_5 = 0x00000005,
5096BITS_37_6 = 0x00000006,
5097BITS_38_7 = 0x00000007,
5098} DC_DMCUB_TIMER_WINDOW;
5099
5100/*******************************************************
5101 * RBBMIF Enums
5102 *******************************************************/
5103
5104/*
5105 * INVALID_REG_ACCESS_TYPE enum
5106 */
5107
5108typedef enum INVALID_REG_ACCESS_TYPE {
5109REG_UNALLOCATED_ADDR_WRITE = 0x00000000,
5110REG_UNALLOCATED_ADDR_READ = 0x00000001,
5111REG_VIRTUAL_WRITE = 0x00000002,
5112REG_VIRTUAL_READ = 0x00000003,
5113REG_SECURE_VIOLATE_WRITE = 0x00000004,
5114REG_SECURE_VIOLATE_READ = 0x00000005,
5115} INVALID_REG_ACCESS_TYPE;
5116
5117/*******************************************************
5118 * IHC Enums
5119 *******************************************************/
5120
5121/*
5122 * DMU_DC_GPU_TIMER_READ_SELECT enum
5123 */
5124
5125typedef enum DMU_DC_GPU_TIMER_READ_SELECT {
5126DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0x00000000,
5127DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 0x00000001,
5128DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 0x00000002,
5129DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 0x00000003,
5130DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 0x00000004,
5131DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 0x00000005,
5132DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 0x00000006,
5133DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 0x00000007,
5134RESERVED_8 = 0x00000008,
5135RESERVED_9 = 0x00000009,
5136RESERVED_10 = 0x0000000a,
5137RESERVED_11 = 0x0000000b,
5138DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 0x0000000c,
5139DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 0x0000000d,
5140DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 0x0000000e,
5141DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 0x0000000f,
5142DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 0x00000010,
5143DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 0x00000011,
5144DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 0x00000012,
5145DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 0x00000013,
5146RESERVED_20 = 0x00000014,
5147RESERVED_21 = 0x00000015,
5148RESERVED_22 = 0x00000016,
5149RESERVED_23 = 0x00000017,
5150DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 0x00000018,
5151DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 0x00000019,
5152DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 0x0000001a,
5153DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 0x0000001b,
5154DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 0x0000001c,
5155DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 0x0000001d,
5156DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 0x0000001e,
5157DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 0x0000001f,
5158RESERVED_32 = 0x00000020,
5159RESERVED_33 = 0x00000021,
5160RESERVED_34 = 0x00000022,
5161RESERVED_35 = 0x00000023,
5162DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 0x00000024,
5163DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 0x00000025,
5164DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 0x00000026,
5165DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 0x00000027,
5166DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 0x00000028,
5167DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 0x00000029,
5168DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 0x0000002a,
5169DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 0x0000002b,
5170RESERVED_44 = 0x0000002c,
5171RESERVED_45 = 0x0000002d,
5172RESERVED_46 = 0x0000002e,
5173RESERVED_47 = 0x0000002f,
5174DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 0x00000030,
5175DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 0x00000031,
5176DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 0x00000032,
5177DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 0x00000033,
5178DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 0x00000034,
5179DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 0x00000035,
5180DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 0x00000036,
5181DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 0x00000037,
5182RESERVED_56 = 0x00000038,
5183RESERVED_57 = 0x00000039,
5184RESERVED_58 = 0x0000003a,
5185RESERVED_59 = 0x0000003b,
5186RESERVED_60 = 0x0000003c,
5187RESERVED_61 = 0x0000003d,
5188RESERVED_62 = 0x0000003e,
5189RESERVED_63 = 0x0000003f,
5190DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 0x00000040,
5191DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 0x00000041,
5192DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 0x00000042,
5193DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 0x00000043,
5194DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 0x00000044,
5195DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 0x00000045,
5196DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 0x00000046,
5197DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 0x00000047,
5198RESERVED_72 = 0x00000048,
5199RESERVED_73 = 0x00000049,
5200RESERVED_74 = 0x0000004a,
5201RESERVED_75 = 0x0000004b,
5202DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 0x0000004c,
5203DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 0x0000004d,
5204DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 0x0000004e,
5205DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 0x0000004f,
5206DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 0x00000050,
5207DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 0x00000051,
5208DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 0x00000052,
5209DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 0x00000053,
5210RESERVED_84 = 0x00000054,
5211RESERVED_85 = 0x00000055,
5212RESERVED_86 = 0x00000056,
5213RESERVED_87 = 0x00000057,
5214RESERVED_88 = 0x00000058,
5215RESERVED_89 = 0x00000059,
5216RESERVED_90 = 0x0000005a,
5217RESERVED_91 = 0x0000005b,
5218} DMU_DC_GPU_TIMER_READ_SELECT;
5219
5220/*
5221 * DMU_DC_GPU_TIMER_START_POSITION enum
5222 */
5223
5224typedef enum DMU_DC_GPU_TIMER_START_POSITION {
5225DMU_GPU_TIMER_START_0_END_27 = 0x00000000,
5226DMU_GPU_TIMER_START_1_END_28 = 0x00000001,
5227DMU_GPU_TIMER_START_2_END_29 = 0x00000002,
5228DMU_GPU_TIMER_START_3_END_30 = 0x00000003,
5229DMU_GPU_TIMER_START_4_END_31 = 0x00000004,
5230DMU_GPU_TIMER_START_6_END_33 = 0x00000005,
5231DMU_GPU_TIMER_START_8_END_35 = 0x00000006,
5232DMU_GPU_TIMER_START_10_END_37 = 0x00000007,
5233} DMU_DC_GPU_TIMER_START_POSITION;
5234
5235/*
5236 * IHC_INTERRUPT_DEST enum
5237 */
5238
5239typedef enum IHC_INTERRUPT_DEST {
5240INTERRUPT_SENT_TO_IH = 0x00000000,
5241INTERRUPT_SENT_TO_DMCUB = 0x00000001,
5242} IHC_INTERRUPT_DEST;
5243
5244/*
5245 * IHC_INTERRUPT_LINE_STATUS enum
5246 */
5247
5248typedef enum IHC_INTERRUPT_LINE_STATUS {
5249INTERRUPT_LINE_NOT_ASSERTED = 0x00000000,
5250INTERRUPT_LINE_ASSERTED = 0x00000001,
5251} IHC_INTERRUPT_LINE_STATUS;
5252
5253/*******************************************************
5254 * DMU_MISC Enums
5255 *******************************************************/
5256
5257/*
5258 * DC_SMU_INTERRUPT_ENABLE enum
5259 */
5260
5261typedef enum DC_SMU_INTERRUPT_ENABLE {
5262DISABLE_THE_INTERRUPT = 0x00000000,
5263ENABLE_THE_INTERRUPT = 0x00000001,
5264} DC_SMU_INTERRUPT_ENABLE;
5265
5266/*
5267 * DMU_CLOCK_ON enum
5268 */
5269
5270typedef enum DMU_CLOCK_ON {
5271DMU_CLOCK_STATUS_ON = 0x00000000,
5272DMU_CLOCK_STATUS_OFF = 0x00000001,
5273} DMU_CLOCK_ON;
5274
5275/*
5276 * SMU_INTR enum
5277 */
5278
5279typedef enum SMU_INTR {
5280SMU_MSG_INTR_NOOP = 0x00000000,
5281SET_SMU_MSG_INTR = 0x00000001,
5282} SMU_INTR;
5283
5284/*******************************************************
5285 * DCCG Enums
5286 *******************************************************/
5287
5288/*
5289 * ALLOW_SR_ON_TRANS_REQ enum
5290 */
5291
5292typedef enum ALLOW_SR_ON_TRANS_REQ {
5293ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000,
5294ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001,
5295} ALLOW_SR_ON_TRANS_REQ;
5296
5297/*
5298 * AMCLOCK_ENABLE enum
5299 */
5300
5301typedef enum AMCLOCK_ENABLE {
5302ENABLE_AMCLK0 = 0x00000000,
5303ENABLE_AMCLK1 = 0x00000001,
5304} AMCLOCK_ENABLE;
5305
5306/*
5307 * CLEAR_SMU_INTR enum
5308 */
5309
5310typedef enum CLEAR_SMU_INTR {
5311SMU_INTR_STATUS_NOOP = 0x00000000,
5312SMU_INTR_STATUS_CLEAR = 0x00000001,
5313} CLEAR_SMU_INTR;
5314
5315/*
5316 * CLOCK_BRANCH_SOFT_RESET enum
5317 */
5318
5319typedef enum CLOCK_BRANCH_SOFT_RESET {
5320CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000,
5321CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001,
5322} CLOCK_BRANCH_SOFT_RESET;
5323
5324/*
5325 * DCCG_AUDIO_DTO0_SOURCE_SEL enum
5326 */
5327
5328typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
5329DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0x00000000,
5330DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 0x00000001,
5331DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 0x00000002,
5332DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 0x00000003,
5333DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000004,
5334} DCCG_AUDIO_DTO0_SOURCE_SEL;
5335
5336/*
5337 * DCCG_AUDIO_DTO2_SOURCE_SEL enum
5338 */
5339
5340typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
5341DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000,
5342DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 0x00000001,
5343} DCCG_AUDIO_DTO2_SOURCE_SEL;
5344
5345/*
5346 * DCCG_AUDIO_DTO_SEL enum
5347 */
5348
5349typedef enum DCCG_AUDIO_DTO_SEL {
5350DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000,
5351DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001,
5352DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002,
5353DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK = 0x00000003,
5354} DCCG_AUDIO_DTO_SEL;
5355
5356/*
5357 * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
5358 */
5359
5360typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
5361DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000,
5362DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001,
5363} DCCG_AUDIO_DTO_USE_512FBR_DTO;
5364
5365/*
5366 * DCCG_DBG_BLOCK_SEL enum
5367 */
5368
5369typedef enum DCCG_DBG_BLOCK_SEL {
5370DCCG_DBG_BLOCK_SEL_DCCG = 0x00000000,
5371DCCG_DBG_BLOCK_SEL_PMON = 0x00000001,
5372DCCG_DBG_BLOCK_SEL_PMON2 = 0x00000002,
5373} DCCG_DBG_BLOCK_SEL;
5374
5375/*
5376 * DCCG_DBG_EN enum
5377 */
5378
5379typedef enum DCCG_DBG_EN {
5380DCCG_DBG_EN_DISABLE = 0x00000000,
5381DCCG_DBG_EN_ENABLE = 0x00000001,
5382} DCCG_DBG_EN;
5383
5384/*
5385 * DCCG_DEEP_COLOR_CNTL enum
5386 */
5387
5388typedef enum DCCG_DEEP_COLOR_CNTL {
5389DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000,
5390DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001,
5391DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002,
5392DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003,
5393} DCCG_DEEP_COLOR_CNTL;
5394
5395/*
5396 * DCCG_FIFO_ERRDET_OVR_EN enum
5397 */
5398
5399typedef enum DCCG_FIFO_ERRDET_OVR_EN {
5400DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000,
5401DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001,
5402} DCCG_FIFO_ERRDET_OVR_EN;
5403
5404/*
5405 * DCCG_FIFO_ERRDET_RESET enum
5406 */
5407
5408typedef enum DCCG_FIFO_ERRDET_RESET {
5409DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000,
5410DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001,
5411} DCCG_FIFO_ERRDET_RESET;
5412
5413/*
5414 * DCCG_FIFO_ERRDET_STATE enum
5415 */
5416
5417typedef enum DCCG_FIFO_ERRDET_STATE {
5418DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000000,
5419DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000001,
5420} DCCG_FIFO_ERRDET_STATE;
5421
5422/*
5423 * DCCG_PERF_MODE_HSYNC enum
5424 */
5425
5426typedef enum DCCG_PERF_MODE_HSYNC {
5427DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000,
5428DCCG_PERF_MODE_HSYNC_START = 0x00000001,
5429} DCCG_PERF_MODE_HSYNC;
5430
5431/*
5432 * DCCG_PERF_MODE_VSYNC enum
5433 */
5434
5435typedef enum DCCG_PERF_MODE_VSYNC {
5436DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000,
5437DCCG_PERF_MODE_VSYNC_START = 0x00000001,
5438} DCCG_PERF_MODE_VSYNC;
5439
5440/*
5441 * DCCG_PERF_OTG_SELECT enum
5442 */
5443
5444typedef enum DCCG_PERF_OTG_SELECT {
5445DCCG_PERF_SEL_OTG0 = 0x00000000,
5446DCCG_PERF_SEL_OTG1 = 0x00000001,
5447DCCG_PERF_SEL_OTG2 = 0x00000002,
5448DCCG_PERF_SEL_OTG3 = 0x00000003,
5449DCCG_PERF_SEL_RESERVED = 0x00000004,
5450} DCCG_PERF_OTG_SELECT;
5451
5452/*
5453 * DCCG_PERF_RUN enum
5454 */
5455
5456typedef enum DCCG_PERF_RUN {
5457DCCG_PERF_RUN_NOOP = 0x00000000,
5458DCCG_PERF_RUN_START = 0x00000001,
5459} DCCG_PERF_RUN;
5460
5461/*
5462 * DC_MEM_GLOBAL_PWR_REQ_DIS enum
5463 */
5464
5465typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
5466DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000,
5467DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001,
5468} DC_MEM_GLOBAL_PWR_REQ_DIS;
5469
5470/*
5471 * DIO_FIFO_ERROR enum
5472 */
5473
5474typedef enum DIO_FIFO_ERROR {
5475DIO_FIFO_ERROR_00 = 0x00000000,
5476DIO_FIFO_ERROR_01 = 0x00000001,
5477DIO_FIFO_ERROR_10 = 0x00000002,
5478DIO_FIFO_ERROR_11 = 0x00000003,
5479} DIO_FIFO_ERROR;
5480
5481/*
5482 * DISABLE_CLOCK_GATING enum
5483 */
5484
5485typedef enum DISABLE_CLOCK_GATING {
5486CLOCK_GATING_ENABLED = 0x00000000,
5487CLOCK_GATING_DISABLED = 0x00000001,
5488} DISABLE_CLOCK_GATING;
5489
5490/*
5491 * DISABLE_CLOCK_GATING_IN_DCO enum
5492 */
5493
5494typedef enum DISABLE_CLOCK_GATING_IN_DCO {
5495CLOCK_GATING_ENABLED_IN_DCO = 0x00000000,
5496CLOCK_GATING_DISABLED_IN_DCO = 0x00000001,
5497} DISABLE_CLOCK_GATING_IN_DCO;
5498
5499/*
5500 * DISPCLK_CHG_FWD_CORR_DISABLE enum
5501 */
5502
5503typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
5504DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000,
5505DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001,
5506} DISPCLK_CHG_FWD_CORR_DISABLE;
5507
5508/*
5509 * DISPCLK_FREQ_RAMP_DONE enum
5510 */
5511
5512typedef enum DISPCLK_FREQ_RAMP_DONE {
5513DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000,
5514DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001,
5515} DISPCLK_FREQ_RAMP_DONE;
5516
5517/*
5518 * DPREFCLK_SRC_SEL enum
5519 */
5520
5521typedef enum DPREFCLK_SRC_SEL {
5522DPREFCLK_SRC_SEL_CK = 0x00000000,
5523DPREFCLK_SRC_SEL_P0PLL = 0x00000001,
5524DPREFCLK_SRC_SEL_P1PLL = 0x00000002,
5525DPREFCLK_SRC_SEL_P2PLL = 0x00000003,
5526} DPREFCLK_SRC_SEL;
5527
5528/*
5529 * DP_DTO_DS_DISABLE enum
5530 */
5531
5532typedef enum DP_DTO_DS_DISABLE {
5533DP_DTO_DESPREAD_DISABLE = 0x00000000,
5534DP_DTO_DESPREAD_ENABLE = 0x00000001,
5535} DP_DTO_DS_DISABLE;
5536
5537/*
5538 * DS_HW_CAL_ENABLE enum
5539 */
5540
5541typedef enum DS_HW_CAL_ENABLE {
5542DS_HW_CAL_DIS = 0x00000000,
5543DS_HW_CAL_EN = 0x00000001,
5544} DS_HW_CAL_ENABLE;
5545
5546/*
5547 * DS_JITTER_COUNT_SRC_SEL enum
5548 */
5549
5550typedef enum DS_JITTER_COUNT_SRC_SEL {
5551DS_JITTER_COUNT_SRC_SEL0 = 0x00000000,
5552DS_JITTER_COUNT_SRC_SEL1 = 0x00000001,
5553} DS_JITTER_COUNT_SRC_SEL;
5554
5555/*
5556 * DS_REF_SRC enum
5557 */
5558
5559typedef enum DS_REF_SRC {
5560DS_REF_IS_XTALIN = 0x00000000,
5561DS_REF_IS_EXT_GENLOCK = 0x00000001,
5562DS_REF_IS_PCIE = 0x00000002,
5563} DS_REF_SRC;
5564
5565/*
5566 * DVOACLKC_IN_PHASE enum
5567 */
5568
5569typedef enum DVOACLKC_IN_PHASE {
5570DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
5571DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
5572} DVOACLKC_IN_PHASE;
5573
5574/*
5575 * DVOACLKC_MVP_IN_PHASE enum
5576 */
5577
5578typedef enum DVOACLKC_MVP_IN_PHASE {
5579DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
5580DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
5581} DVOACLKC_MVP_IN_PHASE;
5582
5583/*
5584 * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
5585 */
5586
5587typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
5588DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x00000000,
5589DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x00000001,
5590} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
5591
5592/*
5593 * DVOACLKD_IN_PHASE enum
5594 */
5595
5596typedef enum DVOACLKD_IN_PHASE {
5597DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
5598DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
5599} DVOACLKD_IN_PHASE;
5600
5601/*
5602 * DVOACLK_COARSE_SKEW_CNTL enum
5603 */
5604
5605typedef enum DVOACLK_COARSE_SKEW_CNTL {
5606DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
5607DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
5608DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
5609DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
5610DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x00000004,
5611DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x00000005,
5612DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x00000006,
5613DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x00000007,
5614DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x00000008,
5615DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x00000009,
5616DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0x0000000a,
5617DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0x0000000b,
5618DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0x0000000c,
5619DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0x0000000d,
5620DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0x0000000e,
5621DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0x0000000f,
5622DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x00000010,
5623DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x00000011,
5624DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x00000012,
5625DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x00000013,
5626DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x00000014,
5627DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x00000015,
5628DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x00000016,
5629DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x00000017,
5630DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x00000018,
5631DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x00000019,
5632DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x0000001a,
5633DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x0000001b,
5634DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x0000001c,
5635DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x0000001d,
5636DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x0000001e,
5637} DVOACLK_COARSE_SKEW_CNTL;
5638
5639/*
5640 * DVOACLK_FINE_SKEW_CNTL enum
5641 */
5642
5643typedef enum DVOACLK_FINE_SKEW_CNTL {
5644DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
5645DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
5646DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
5647DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
5648DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x00000004,
5649DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x00000005,
5650DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x00000006,
5651DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x00000007,
5652} DVOACLK_FINE_SKEW_CNTL;
5653
5654/*
5655 * DVO_ENABLE_RST enum
5656 */
5657
5658typedef enum DVO_ENABLE_RST {
5659DVO_ENABLE_RST_DISABLE = 0x00000000,
5660DVO_ENABLE_RST_ENABLE = 0x00000001,
5661} DVO_ENABLE_RST;
5662
5663/*
5664 * ENABLE enum
5665 */
5666
5667typedef enum ENABLE {
5668DISABLE_THE_FEATURE = 0x00000000,
5669ENABLE_THE_FEATURE = 0x00000001,
5670} ENABLE;
5671
5672/*
5673 * ENABLE_CLOCK enum
5674 */
5675
5676typedef enum ENABLE_CLOCK {
5677ENABLE_THE_REFCLK = 0x00000000,
5678ENABLE_THE_FUNC_CLOCK = 0x00000001,
5679} ENABLE_CLOCK;
5680
5681/*
5682 * FORCE_DISABLE_CLOCK enum
5683 */
5684
5685typedef enum FORCE_DISABLE_CLOCK {
5686NOT_FORCE_THE_CLOCK_DISABLED = 0x00000000,
5687FORCE_THE_CLOCK_DISABLED = 0x00000001,
5688} FORCE_DISABLE_CLOCK;
5689
5690/*
5691 * HDMICHARCLK_SRC_SEL enum
5692 */
5693
5694typedef enum HDMICHARCLK_SRC_SEL {
5695HDMICHARCLK_SRC_SEL_UNIPHYA = 0x00000000,
5696HDMICHARCLK_SRC_SEL_UNIPHYB = 0x00000001,
5697HDMICHARCLK_SRC_SEL_UNIPHYC = 0x00000002,
5698HDMICHARCLK_SRC_SEL_UNIPHYD = 0x00000003,
5699HDMICHARCLK_SRC_SEL_UNIPHYE = 0x00000004,
5700HDMICHARCLK_SRC_SEL_SRC_RESERVED = 0x00000005,
5701} HDMICHARCLK_SRC_SEL;
5702
5703/*
5704 * HDMISTREAMCLK_DTO_FORCE_DIS enum
5705 */
5706
5707typedef enum HDMISTREAMCLK_DTO_FORCE_DIS {
5708DTO_FORCE_NO_BYPASS = 0x00000000,
5709DTO_FORCE_BYPASS = 0x00000001,
5710} HDMISTREAMCLK_DTO_FORCE_DIS;
5711
5712/*
5713 * HDMISTREAMCLK_SRC_SEL enum
5714 */
5715
5716typedef enum HDMISTREAMCLK_SRC_SEL {
5717SEL_REFCLK0 = 0x00000000,
5718SEL_DTBCLK0 = 0x00000001,
5719SEL_DTBCLK1 = 0x00000002,
5720} HDMISTREAMCLK_SRC_SEL;
5721
5722/*
5723 * JITTER_REMOVE_DISABLE enum
5724 */
5725
5726typedef enum JITTER_REMOVE_DISABLE {
5727ENABLE_JITTER_REMOVAL = 0x00000000,
5728DISABLE_JITTER_REMOVAL = 0x00000001,
5729} JITTER_REMOVE_DISABLE;
5730
5731/*
5732 * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5733 */
5734
5735typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5736MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
5737MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001,
5738} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
5739
5740/*
5741 * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5742 */
5743
5744typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5745MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
5746MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001,
5747} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
5748
5749/*
5750 * OTG_ADD_PIXEL enum
5751 */
5752
5753typedef enum OTG_ADD_PIXEL {
5754OTG_ADD_PIXEL_NOOP = 0x00000000,
5755OTG_ADD_PIXEL_FORCE = 0x00000001,
5756} OTG_ADD_PIXEL;
5757
5758/*
5759 * OTG_DROP_PIXEL enum
5760 */
5761
5762typedef enum OTG_DROP_PIXEL {
5763OTG_DROP_PIXEL_NOOP = 0x00000000,
5764OTG_DROP_PIXEL_FORCE = 0x00000001,
5765} OTG_DROP_PIXEL;
5766
5767/*
5768 * PHYSYMCLK_FORCE_EN enum
5769 */
5770
5771typedef enum PHYSYMCLK_FORCE_EN {
5772PHYSYMCLK_FORCE_EN_DISABLE = 0x00000000,
5773PHYSYMCLK_FORCE_EN_ENABLE = 0x00000001,
5774} PHYSYMCLK_FORCE_EN;
5775
5776/*
5777 * PHYSYMCLK_FORCE_SRC_SEL enum
5778 */
5779
5780typedef enum PHYSYMCLK_FORCE_SRC_SEL {
5781PHYSYMCLK_FORCE_SRC_SYMCLK = 0x00000000,
5782PHYSYMCLK_FORCE_SRC_PHYD18CLK = 0x00000001,
5783PHYSYMCLK_FORCE_SRC_PHYD32CLK = 0x00000002,
5784} PHYSYMCLK_FORCE_SRC_SEL;
5785
5786/*
5787 * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
5788 */
5789
5790typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
5791PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000,
5792PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001,
5793PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002,
5794PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003,
5795PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 0x00000004,
5796} PIPE_PHYPLL_PIXEL_RATE_SOURCE;
5797
5798/*
5799 * PIPE_PIXEL_RATE_PLL_SOURCE enum
5800 */
5801
5802typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
5803PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000,
5804PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001,
5805} PIPE_PIXEL_RATE_PLL_SOURCE;
5806
5807/*
5808 * PIPE_PIXEL_RATE_SOURCE enum
5809 */
5810
5811typedef enum PIPE_PIXEL_RATE_SOURCE {
5812PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000,
5813PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001,
5814PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002,
5815} PIPE_PIXEL_RATE_SOURCE;
5816
5817/*
5818 * PLL_CFG_IF_SOFT_RESET enum
5819 */
5820
5821typedef enum PLL_CFG_IF_SOFT_RESET {
5822PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000,
5823PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001,
5824} PLL_CFG_IF_SOFT_RESET;
5825
5826/*
5827 * SYMCLK_FE_FORCE_EN enum
5828 */
5829
5830typedef enum SYMCLK_FE_FORCE_EN {
5831SYMCLK_FE_FORCE_EN_DISABLE = 0x00000000,
5832SYMCLK_FE_FORCE_EN_ENABLE = 0x00000001,
5833} SYMCLK_FE_FORCE_EN;
5834
5835/*
5836 * SYMCLK_FE_FORCE_SRC enum
5837 */
5838
5839typedef enum SYMCLK_FE_FORCE_SRC {
5840SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x00000000,
5841SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x00000001,
5842SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x00000002,
5843SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x00000003,
5844SYMCLK_FE_FORCE_SRC_RESERVED = 0x00000004,
5845} SYMCLK_FE_FORCE_SRC;
5846
5847/*
5848 * TEST_CLK_DIV_SEL enum
5849 */
5850
5851typedef enum TEST_CLK_DIV_SEL {
5852NO_DIV = 0x00000000,
5853DIV_2 = 0x00000001,
5854DIV_4 = 0x00000002,
5855DIV_8 = 0x00000003,
5856} TEST_CLK_DIV_SEL;
5857
5858/*
5859 * VSYNC_CNT_LATCH_MASK enum
5860 */
5861
5862typedef enum VSYNC_CNT_LATCH_MASK {
5863VSYNC_CNT_LATCH_MASK_0 = 0x00000000,
5864VSYNC_CNT_LATCH_MASK_1 = 0x00000001,
5865} VSYNC_CNT_LATCH_MASK;
5866
5867/*
5868 * VSYNC_CNT_RESET_SEL enum
5869 */
5870
5871typedef enum VSYNC_CNT_RESET_SEL {
5872VSYNC_CNT_RESET_SEL_0 = 0x00000000,
5873VSYNC_CNT_RESET_SEL_1 = 0x00000001,
5874} VSYNC_CNT_RESET_SEL;
5875
5876/*
5877 * XTAL_REF_CLOCK_SOURCE_SEL enum
5878 */
5879
5880typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
5881XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000,
5882XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 0x00000001,
5883} XTAL_REF_CLOCK_SOURCE_SEL;
5884
5885/*
5886 * XTAL_REF_SEL enum
5887 */
5888
5889typedef enum XTAL_REF_SEL {
5890XTAL_REF_SEL_1X = 0x00000000,
5891XTAL_REF_SEL_2X = 0x00000001,
5892} XTAL_REF_SEL;
5893
5894/*******************************************************
5895 * HPD Enums
5896 *******************************************************/
5897
5898/*
5899 * HPD_INT_CONTROL_ACK enum
5900 */
5901
5902typedef enum HPD_INT_CONTROL_ACK {
5903HPD_INT_CONTROL_ACK_0 = 0x00000000,
5904HPD_INT_CONTROL_ACK_1 = 0x00000001,
5905} HPD_INT_CONTROL_ACK;
5906
5907/*
5908 * HPD_INT_CONTROL_POLARITY enum
5909 */
5910
5911typedef enum HPD_INT_CONTROL_POLARITY {
5912HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000,
5913HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001,
5914} HPD_INT_CONTROL_POLARITY;
5915
5916/*
5917 * HPD_INT_CONTROL_RX_INT_ACK enum
5918 */
5919
5920typedef enum HPD_INT_CONTROL_RX_INT_ACK {
5921HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000,
5922HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001,
5923} HPD_INT_CONTROL_RX_INT_ACK;
5924
5925/*******************************************************
5926 * DP Enums
5927 *******************************************************/
5928
5929/*
5930 * DPHY_8B10B_CUR_DISP enum
5931 */
5932
5933typedef enum DPHY_8B10B_CUR_DISP {
5934DPHY_8B10B_CUR_DISP_ZERO = 0x00000000,
5935DPHY_8B10B_CUR_DISP_ONE = 0x00000001,
5936} DPHY_8B10B_CUR_DISP;
5937
5938/*
5939 * DPHY_8B10B_RESET enum
5940 */
5941
5942typedef enum DPHY_8B10B_RESET {
5943DPHY_8B10B_NOT_RESET = 0x00000000,
5944DPHY_8B10B_RESETET = 0x00000001,
5945} DPHY_8B10B_RESET;
5946
5947/*
5948 * DPHY_ALT_SCRAMBLER_RESET_EN enum
5949 */
5950
5951typedef enum DPHY_ALT_SCRAMBLER_RESET_EN {
5952DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0x00000000,
5953DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 0x00000001,
5954} DPHY_ALT_SCRAMBLER_RESET_EN;
5955
5956/*
5957 * DPHY_ALT_SCRAMBLER_RESET_SEL enum
5958 */
5959
5960typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL {
5961DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0x00000000,
5962DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 0x00000001,
5963} DPHY_ALT_SCRAMBLER_RESET_SEL;
5964
5965/*
5966 * DPHY_ATEST_SEL_LANE0 enum
5967 */
5968
5969typedef enum DPHY_ATEST_SEL_LANE0 {
5970DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000,
5971DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001,
5972} DPHY_ATEST_SEL_LANE0;
5973
5974/*
5975 * DPHY_ATEST_SEL_LANE1 enum
5976 */
5977
5978typedef enum DPHY_ATEST_SEL_LANE1 {
5979DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000,
5980DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001,
5981} DPHY_ATEST_SEL_LANE1;
5982
5983/*
5984 * DPHY_ATEST_SEL_LANE2 enum
5985 */
5986
5987typedef enum DPHY_ATEST_SEL_LANE2 {
5988DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000,
5989DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001,
5990} DPHY_ATEST_SEL_LANE2;
5991
5992/*
5993 * DPHY_ATEST_SEL_LANE3 enum
5994 */
5995
5996typedef enum DPHY_ATEST_SEL_LANE3 {
5997DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000,
5998DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001,
5999} DPHY_ATEST_SEL_LANE3;
6000
6001/*
6002 * DPHY_BYPASS enum
6003 */
6004
6005typedef enum DPHY_BYPASS {
6006DPHY_8B10B_OUTPUT = 0x00000000,
6007DPHY_DBG_OUTPUT = 0x00000001,
6008} DPHY_BYPASS;
6009
6010/*
6011 * DPHY_CRC_CONT_EN enum
6012 */
6013
6014typedef enum DPHY_CRC_CONT_EN {
6015DPHY_CRC_ONE_SHOT = 0x00000000,
6016DPHY_CRC_CONTINUOUS = 0x00000001,
6017} DPHY_CRC_CONT_EN;
6018
6019/*
6020 * DPHY_CRC_EN enum
6021 */
6022
6023typedef enum DPHY_CRC_EN {
6024DPHY_CRC_DISABLED = 0x00000000,
6025DPHY_CRC_ENABLED = 0x00000001,
6026} DPHY_CRC_EN;
6027
6028/*
6029 * DPHY_CRC_FIELD enum
6030 */
6031
6032typedef enum DPHY_CRC_FIELD {
6033DPHY_CRC_START_FROM_TOP_FIELD = 0x00000000,
6034DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x00000001,
6035} DPHY_CRC_FIELD;
6036
6037/*
6038 * DPHY_CRC_MST_PHASE_ERROR_ACK enum
6039 */
6040
6041typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
6042DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x00000000,
6043DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x00000001,
6044} DPHY_CRC_MST_PHASE_ERROR_ACK;
6045
6046/*
6047 * DPHY_CRC_SEL enum
6048 */
6049
6050typedef enum DPHY_CRC_SEL {
6051DPHY_CRC_LANE0_SELECTED = 0x00000000,
6052DPHY_CRC_LANE1_SELECTED = 0x00000001,
6053DPHY_CRC_LANE2_SELECTED = 0x00000002,
6054DPHY_CRC_LANE3_SELECTED = 0x00000003,
6055} DPHY_CRC_SEL;
6056
6057/*
6058 * DPHY_FEC_ENABLE enum
6059 */
6060
6061typedef enum DPHY_FEC_ENABLE {
6062DPHY_FEC_DISABLED = 0x00000000,
6063DPHY_FEC_ENABLED = 0x00000001,
6064} DPHY_FEC_ENABLE;
6065
6066/*
6067 * DPHY_FEC_READY enum
6068 */
6069
6070typedef enum DPHY_FEC_READY {
6071DPHY_FEC_READY_EN = 0x00000000,
6072DPHY_FEC_READY_DIS = 0x00000001,
6073} DPHY_FEC_READY;
6074
6075/*
6076 * DPHY_LOAD_BS_COUNT_START enum
6077 */
6078
6079typedef enum DPHY_LOAD_BS_COUNT_START {
6080DPHY_LOAD_BS_COUNT_STARTED = 0x00000000,
6081DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x00000001,
6082} DPHY_LOAD_BS_COUNT_START;
6083
6084/*
6085 * DPHY_PRBS_EN enum
6086 */
6087
6088typedef enum DPHY_PRBS_EN {
6089DPHY_PRBS_DISABLE = 0x00000000,
6090DPHY_PRBS_ENABLE = 0x00000001,
6091} DPHY_PRBS_EN;
6092
6093/*
6094 * DPHY_PRBS_SEL enum
6095 */
6096
6097typedef enum DPHY_PRBS_SEL {
6098DPHY_PRBS7_SELECTED = 0x00000000,
6099DPHY_PRBS23_SELECTED = 0x00000001,
6100DPHY_PRBS11_SELECTED = 0x00000002,
6101} DPHY_PRBS_SEL;
6102
6103/*
6104 * DPHY_RX_FAST_TRAINING_CAPABLE enum
6105 */
6106
6107typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
6108DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x00000000,
6109DPHY_FAST_TRAINING_CAPABLE = 0x00000001,
6110} DPHY_RX_FAST_TRAINING_CAPABLE;
6111
6112/*
6113 * DPHY_SCRAMBLER_ADVANCE enum
6114 */
6115
6116typedef enum DPHY_SCRAMBLER_ADVANCE {
6117DPHY_DPHY_SCRAMBLER_ADVANCE_ON_DATA_SYMBOL_ONLY = 0x00000000,
6118DPHY_SCRAMBLER_ADVANCE_ON_BOTH_DATA_AND_CTRL = 0x00000001,
6119} DPHY_SCRAMBLER_ADVANCE;
6120
6121/*
6122 * DPHY_SCRAMBLER_DIS enum
6123 */
6124
6125typedef enum DPHY_SCRAMBLER_DIS {
6126DPHY_SCR_ENABLED = 0x00000000,
6127DPHY_SCR_DISABLED = 0x00000001,
6128} DPHY_SCRAMBLER_DIS;
6129
6130/*
6131 * DPHY_SCRAMBLER_KCODE enum
6132 */
6133
6134typedef enum DPHY_SCRAMBLER_KCODE {
6135DPHY_SCRAMBLER_KCODE_DISABLED = 0x00000000,
6136DPHY_SCRAMBLER_KCODE_ENABLED = 0x00000001,
6137} DPHY_SCRAMBLER_KCODE;
6138
6139/*
6140 * DPHY_SCRAMBLER_SEL enum
6141 */
6142
6143typedef enum DPHY_SCRAMBLER_SEL {
6144DPHY_SCRAMBLER_SEL_LANE_DATA = 0x00000000,
6145DPHY_SCRAMBLER_SEL_DBG_DATA = 0x00000001,
6146} DPHY_SCRAMBLER_SEL;
6147
6148/*
6149 * DPHY_SKEW_BYPASS enum
6150 */
6151
6152typedef enum DPHY_SKEW_BYPASS {
6153DPHY_WITH_SKEW = 0x00000000,
6154DPHY_NO_SKEW = 0x00000001,
6155} DPHY_SKEW_BYPASS;
6156
6157/*
6158 * DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM enum
6159 */
6160
6161typedef enum DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM {
6162DPHY_STREAM_RESET_DURING_FAST_TRAINING_RESET = 0x00000000,
6163DPHY_STREAM_RESET_DURING_FAST_TRAINING_NOT_RESET = 0x00000001,
6164} DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM;
6165
6166/*
6167 * DPHY_SW_FAST_TRAINING_START enum
6168 */
6169
6170typedef enum DPHY_SW_FAST_TRAINING_START {
6171DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x00000000,
6172DPHY_SW_FAST_TRAINING_STARTED = 0x00000001,
6173} DPHY_SW_FAST_TRAINING_START;
6174
6175/*
6176 * DPHY_TRAINING_PATTERN_SEL enum
6177 */
6178
6179typedef enum DPHY_TRAINING_PATTERN_SEL {
6180DPHY_TRAINING_PATTERN_1 = 0x00000000,
6181DPHY_TRAINING_PATTERN_2 = 0x00000001,
6182DPHY_TRAINING_PATTERN_3 = 0x00000002,
6183DPHY_TRAINING_PATTERN_4 = 0x00000003,
6184} DPHY_TRAINING_PATTERN_SEL;
6185
6186/*
6187 * DP_COMPONENT_DEPTH enum
6188 */
6189
6190typedef enum DP_COMPONENT_DEPTH {
6191DP_COMPONENT_DEPTH_6BPC = 0x00000000,
6192DP_COMPONENT_DEPTH_8BPC = 0x00000001,
6193DP_COMPONENT_DEPTH_10BPC = 0x00000002,
6194DP_COMPONENT_DEPTH_12BPC = 0x00000003,
6195DP_COMPONENT_DEPTH_16BPC = 0x00000004,
6196} DP_COMPONENT_DEPTH;
6197
6198/*
6199 * DP_CP_ENCRYPTION_TYPE enum
6200 */
6201
6202typedef enum DP_CP_ENCRYPTION_TYPE {
6203DP_CP_ENCRYPTION_TYPE_0 = 0x00000000,
6204DP_CP_ENCRYPTION_TYPE_1 = 0x00000001,
6205} DP_CP_ENCRYPTION_TYPE;
6206
6207/*
6208 * DP_DPHY_8B10B_EXT_DISP enum
6209 */
6210
6211typedef enum DP_DPHY_8B10B_EXT_DISP {
6212DP_DPHY_8B10B_EXT_DISP_ZERO = 0x00000000,
6213DP_DPHY_8B10B_EXT_DISP_ONE = 0x00000001,
6214} DP_DPHY_8B10B_EXT_DISP;
6215
6216/*
6217 * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
6218 */
6219
6220typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
6221DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x00000000,
6222DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x00000001,
6223} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
6224
6225/*
6226 * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
6227 */
6228
6229typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
6230DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x00000000,
6231DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x00000001,
6232} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
6233
6234/*
6235 * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
6236 */
6237
6238typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
6239DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0x00000000,
6240DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x00000001,
6241} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
6242
6243/*
6244 * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
6245 */
6246
6247typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
6248DP_DPHY_HBR2_PASS_THROUGH = 0x00000000,
6249DP_DPHY_HBR2_PATTERN_1 = 0x00000001,
6250DP_DPHY_HBR2_PATTERN_2_NEG = 0x00000002,
6251DP_DPHY_HBR2_PATTERN_3 = 0x00000003,
6252DP_DPHY_HBR2_PATTERN_2_POS = 0x00000006,
6253} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
6254
6255/*
6256 * DP_DSC_MODE enum
6257 */
6258
6259typedef enum DP_DSC_MODE {
6260DP_DSC_DISABLE = 0x00000000,
6261DP_DSC_444_SIMPLE_422 = 0x00000001,
6262DP_DSC_NATIVE_422_420 = 0x00000002,
6263} DP_DSC_MODE;
6264
6265/*
6266 * DP_EMBEDDED_PANEL_MODE enum
6267 */
6268
6269typedef enum DP_EMBEDDED_PANEL_MODE {
6270DP_EXTERNAL_PANEL = 0x00000000,
6271DP_EMBEDDED_PANEL = 0x00000001,
6272} DP_EMBEDDED_PANEL_MODE;
6273
6274/*
6275 * DP_LINK_TRAINING_COMPLETE enum
6276 */
6277
6278typedef enum DP_LINK_TRAINING_COMPLETE {
6279DP_LINK_TRAINING_NOT_COMPLETE = 0x00000000,
6280DP_LINK_TRAINING_ALREADY_COMPLETE = 0x00000001,
6281} DP_LINK_TRAINING_COMPLETE;
6282
6283/*
6284 * DP_LINK_TRAINING_SWITCH_MODE enum
6285 */
6286
6287typedef enum DP_LINK_TRAINING_SWITCH_MODE {
6288DP_LINK_TRAINING_SWITCH_TO_IDLE = 0x00000000,
6289DP_LINK_TRAINING_SWITCH_TO_VIDEO = 0x00000001,
6290} DP_LINK_TRAINING_SWITCH_MODE;
6291
6292/*
6293 * DP_ML_PHY_SEQ_MODE enum
6294 */
6295
6296typedef enum DP_ML_PHY_SEQ_MODE {
6297DP_ML_PHY_SEQ_LINE_NUM = 0x00000000,
6298DP_ML_PHY_SEQ_IMMEDIATE = 0x00000001,
6299} DP_ML_PHY_SEQ_MODE;
6300
6301/*
6302 * DP_MSA_V_TIMING_OVERRIDE_EN enum
6303 */
6304
6305typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
6306MSA_V_TIMING_OVERRIDE_DISABLED = 0x00000000,
6307MSA_V_TIMING_OVERRIDE_ENABLED = 0x00000001,
6308} DP_MSA_V_TIMING_OVERRIDE_EN;
6309
6310/*
6311 * DP_MSE_BLANK_CODE enum
6312 */
6313
6314typedef enum DP_MSE_BLANK_CODE {
6315DP_MSE_BLANK_CODE_SF_FILLED = 0x00000000,
6316DP_MSE_BLANK_CODE_ZERO_FILLED = 0x00000001,
6317} DP_MSE_BLANK_CODE;
6318
6319/*
6320 * DP_MSE_LINK_LINE enum
6321 */
6322
6323typedef enum DP_MSE_LINK_LINE {
6324DP_MSE_LINK_LINE_32_MTP_LONG = 0x00000000,
6325DP_MSE_LINK_LINE_64_MTP_LONG = 0x00000001,
6326DP_MSE_LINK_LINE_128_MTP_LONG = 0x00000002,
6327DP_MSE_LINK_LINE_256_MTP_LONG = 0x00000003,
6328} DP_MSE_LINK_LINE;
6329
6330/*
6331 * DP_MSE_SAT_ENCRYPT0 enum
6332 */
6333
6334typedef enum DP_MSE_SAT_ENCRYPT0 {
6335DP_MSE_SAT_ENCRYPT0_DISABLED = 0x00000000,
6336DP_MSE_SAT_ENCRYPT0_ENABLED = 0x00000001,
6337} DP_MSE_SAT_ENCRYPT0;
6338
6339/*
6340 * DP_MSE_SAT_ENCRYPT1 enum
6341 */
6342
6343typedef enum DP_MSE_SAT_ENCRYPT1 {
6344DP_MSE_SAT_ENCRYPT1_DISABLED = 0x00000000,
6345DP_MSE_SAT_ENCRYPT1_ENABLED = 0x00000001,
6346} DP_MSE_SAT_ENCRYPT1;
6347
6348/*
6349 * DP_MSE_SAT_ENCRYPT2 enum
6350 */
6351
6352typedef enum DP_MSE_SAT_ENCRYPT2 {
6353DP_MSE_SAT_ENCRYPT2_DISABLED = 0x00000000,
6354DP_MSE_SAT_ENCRYPT2_ENABLED = 0x00000001,
6355} DP_MSE_SAT_ENCRYPT2;
6356
6357/*
6358 * DP_MSE_SAT_ENCRYPT3 enum
6359 */
6360
6361typedef enum DP_MSE_SAT_ENCRYPT3 {
6362DP_MSE_SAT_ENCRYPT3_DISABLED = 0x00000000,
6363DP_MSE_SAT_ENCRYPT3_ENABLED = 0x00000001,
6364} DP_MSE_SAT_ENCRYPT3;
6365
6366/*
6367 * DP_MSE_SAT_ENCRYPT4 enum
6368 */
6369
6370typedef enum DP_MSE_SAT_ENCRYPT4 {
6371DP_MSE_SAT_ENCRYPT4_DISABLED = 0x00000000,
6372DP_MSE_SAT_ENCRYPT4_ENABLED = 0x00000001,
6373} DP_MSE_SAT_ENCRYPT4;
6374
6375/*
6376 * DP_MSE_SAT_ENCRYPT5 enum
6377 */
6378
6379typedef enum DP_MSE_SAT_ENCRYPT5 {
6380DP_MSE_SAT_ENCRYPT5_DISABLED = 0x00000000,
6381DP_MSE_SAT_ENCRYPT5_ENABLED = 0x00000001,
6382} DP_MSE_SAT_ENCRYPT5;
6383
6384/*
6385 * DP_MSE_SAT_UPDATE_ACT enum
6386 */
6387
6388typedef enum DP_MSE_SAT_UPDATE_ACT {
6389DP_MSE_SAT_UPDATE_NO_ACTION = 0x00000000,
6390DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x00000001,
6391DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x00000002,
6392} DP_MSE_SAT_UPDATE_ACT;
6393
6394/*
6395 * DP_MSE_TIMESTAMP_MODE enum
6396 */
6397
6398typedef enum DP_MSE_TIMESTAMP_MODE {
6399DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x00000000,
6400DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x00000001,
6401} DP_MSE_TIMESTAMP_MODE;
6402
6403/*
6404 * DP_MSE_ZERO_ENCODER enum
6405 */
6406
6407typedef enum DP_MSE_ZERO_ENCODER {
6408DP_MSE_NOT_ZERO_FE_ENCODER = 0x00000000,
6409DP_MSE_ZERO_FE_ENCODER = 0x00000001,
6410} DP_MSE_ZERO_ENCODER;
6411
6412/*
6413 * DP_MSO_NUM_OF_SST_LINKS enum
6414 */
6415
6416typedef enum DP_MSO_NUM_OF_SST_LINKS {
6417DP_MSO_ONE_SSTLINK = 0x00000000,
6418DP_MSO_TWO_SSTLINK = 0x00000001,
6419DP_MSO_FOUR_SSTLINK = 0x00000002,
6420} DP_MSO_NUM_OF_SST_LINKS;
6421
6422/*
6423 * DP_PIXEL_ENCODING enum
6424 */
6425
6426typedef enum DP_PIXEL_ENCODING {
6427DP_PIXEL_ENCODING_RGB444 = 0x00000000,
6428DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
6429DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
6430DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
6431DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
6432DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
6433} DP_PIXEL_ENCODING;
6434
6435/*
6436 * DP_PIXEL_PER_CYCLE_PROCESSING_NUM enum
6437 */
6438
6439typedef enum DP_PIXEL_PER_CYCLE_PROCESSING_NUM {
6440DP_ONE_PIXEL_PER_CYCLE = 0x00000000,
6441DP_TWO_PIXEL_PER_CYCLE = 0x00000001,
6442} DP_PIXEL_PER_CYCLE_PROCESSING_NUM;
6443
6444/*
6445 * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
6446 */
6447
6448typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
6449DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000,
6450DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001,
6451} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
6452
6453/*
6454 * DP_SEC_ASP_PRIORITY enum
6455 */
6456
6457typedef enum DP_SEC_ASP_PRIORITY {
6458DP_SEC_ASP_LOW_PRIORITY = 0x00000000,
6459DP_SEC_ASP_HIGH_PRIORITY = 0x00000001,
6460} DP_SEC_ASP_PRIORITY;
6461
6462/*
6463 * DP_SEC_AUDIO_MUTE enum
6464 */
6465
6466typedef enum DP_SEC_AUDIO_MUTE {
6467DP_SEC_AUDIO_MUTE_HW_CTRL = 0x00000000,
6468DP_SEC_AUDIO_MUTE_SW_CTRL = 0x00000001,
6469} DP_SEC_AUDIO_MUTE;
6470
6471/*
6472 * DP_SEC_COLLISION_ACK enum
6473 */
6474
6475typedef enum DP_SEC_COLLISION_ACK {
6476DP_SEC_COLLISION_ACK_NO_EFFECT = 0x00000000,
6477DP_SEC_COLLISION_ACK_CLR_FLAG = 0x00000001,
6478} DP_SEC_COLLISION_ACK;
6479
6480/*
6481 * DP_SEC_GSP0_PRIORITY enum
6482 */
6483
6484typedef enum DP_SEC_GSP0_PRIORITY {
6485SEC_GSP0_PRIORITY_LOW = 0x00000000,
6486SEC_GSP0_PRIORITY_HIGH = 0x00000001,
6487} DP_SEC_GSP0_PRIORITY;
6488
6489/*
6490 * DP_SEC_GSP_SEND enum
6491 */
6492
6493typedef enum DP_SEC_GSP_SEND {
6494NOT_SENT = 0x00000000,
6495FORCE_SENT = 0x00000001,
6496} DP_SEC_GSP_SEND;
6497
6498/*
6499 * DP_SEC_GSP_SEND_ANY_LINE enum
6500 */
6501
6502typedef enum DP_SEC_GSP_SEND_ANY_LINE {
6503SEND_AT_LINK_NUMBER = 0x00000000,
6504SEND_AT_EARLIEST_TIME = 0x00000001,
6505} DP_SEC_GSP_SEND_ANY_LINE;
6506
6507/*
6508 * DP_SEC_GSP_SEND_PPS enum
6509 */
6510
6511typedef enum DP_SEC_GSP_SEND_PPS {
6512SEND_NORMAL_PACKET = 0x00000000,
6513SEND_PPS_PACKET = 0x00000001,
6514} DP_SEC_GSP_SEND_PPS;
6515
6516/*
6517 * DP_SEC_LINE_REFERENCE enum
6518 */
6519
6520typedef enum DP_SEC_LINE_REFERENCE {
6521REFER_TO_DP_SOF = 0x00000000,
6522REFER_TO_OTG_SOF = 0x00000001,
6523} DP_SEC_LINE_REFERENCE;
6524
6525/*
6526 * DP_SEC_TIMESTAMP_MODE enum
6527 */
6528
6529typedef enum DP_SEC_TIMESTAMP_MODE {
6530DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x00000000,
6531DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x00000001,
6532} DP_SEC_TIMESTAMP_MODE;
6533
6534/*
6535 * DP_STEER_OVERFLOW_ACK enum
6536 */
6537
6538typedef enum DP_STEER_OVERFLOW_ACK {
6539DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
6540DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
6541} DP_STEER_OVERFLOW_ACK;
6542
6543/*
6544 * DP_STEER_OVERFLOW_MASK enum
6545 */
6546
6547typedef enum DP_STEER_OVERFLOW_MASK {
6548DP_STEER_OVERFLOW_MASKED = 0x00000000,
6549DP_STEER_OVERFLOW_UNMASK = 0x00000001,
6550} DP_STEER_OVERFLOW_MASK;
6551
6552/*
6553 * DP_SYNC_POLARITY enum
6554 */
6555
6556typedef enum DP_SYNC_POLARITY {
6557DP_SYNC_POLARITY_ACTIVE_HIGH = 0x00000000,
6558DP_SYNC_POLARITY_ACTIVE_LOW = 0x00000001,
6559} DP_SYNC_POLARITY;
6560
6561/*
6562 * DP_TU_OVERFLOW_ACK enum
6563 */
6564
6565typedef enum DP_TU_OVERFLOW_ACK {
6566DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
6567DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
6568} DP_TU_OVERFLOW_ACK;
6569
6570/*
6571 * DP_UDI_LANES enum
6572 */
6573
6574typedef enum DP_UDI_LANES {
6575DP_UDI_1_LANE = 0x00000000,
6576DP_UDI_2_LANES = 0x00000001,
6577DP_UDI_LANES_RESERVED = 0x00000002,
6578DP_UDI_4_LANES = 0x00000003,
6579} DP_UDI_LANES;
6580
6581/*
6582 * DP_VID_ENHANCED_FRAME_MODE enum
6583 */
6584
6585typedef enum DP_VID_ENHANCED_FRAME_MODE {
6586VID_NORMAL_FRAME_MODE = 0x00000000,
6587VID_ENHANCED_MODE = 0x00000001,
6588} DP_VID_ENHANCED_FRAME_MODE;
6589
6590/*
6591 * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
6592 */
6593
6594typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
6595DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000,
6596DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x00000001,
6597} DP_VID_M_N_DOUBLE_BUFFER_MODE;
6598
6599/*
6600 * DP_VID_M_N_GEN_EN enum
6601 */
6602
6603typedef enum DP_VID_M_N_GEN_EN {
6604DP_VID_M_N_PROGRAMMED_VIA_REG = 0x00000000,
6605DP_VID_M_N_CALC_AUTO = 0x00000001,
6606} DP_VID_M_N_GEN_EN;
6607
6608/*
6609 * DP_VID_N_MUL enum
6610 */
6611
6612typedef enum DP_VID_N_MUL {
6613DP_VID_M_1X_INPUT_PIXEL_RATE = 0x00000000,
6614DP_VID_M_2X_INPUT_PIXEL_RATE = 0x00000001,
6615DP_VID_M_4X_INPUT_PIXEL_RATE = 0x00000002,
6616DP_VID_M_8X_INPUT_PIXEL_RATE = 0x00000003,
6617} DP_VID_N_MUL;
6618
6619/*
6620 * DP_VID_STREAM_DISABLE_ACK enum
6621 */
6622
6623typedef enum DP_VID_STREAM_DISABLE_ACK {
6624ID_STREAM_DISABLE_NO_ACK = 0x00000000,
6625ID_STREAM_DISABLE_ACKED = 0x00000001,
6626} DP_VID_STREAM_DISABLE_ACK;
6627
6628/*
6629 * DP_VID_STREAM_DISABLE_MASK enum
6630 */
6631
6632typedef enum DP_VID_STREAM_DISABLE_MASK {
6633VID_STREAM_DISABLE_MASKED = 0x00000000,
6634VID_STREAM_DISABLE_UNMASK = 0x00000001,
6635} DP_VID_STREAM_DISABLE_MASK;
6636
6637/*
6638 * DP_VID_STREAM_DIS_DEFER enum
6639 */
6640
6641typedef enum DP_VID_STREAM_DIS_DEFER {
6642DP_VID_STREAM_DIS_NO_DEFER = 0x00000000,
6643DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x00000001,
6644DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x00000002,
6645} DP_VID_STREAM_DIS_DEFER;
6646
6647/*
6648 * DP_VID_VBID_FIELD_POL enum
6649 */
6650
6651typedef enum DP_VID_VBID_FIELD_POL {
6652DP_VID_VBID_FIELD_POL_NORMAL = 0x00000000,
6653DP_VID_VBID_FIELD_POL_INV = 0x00000001,
6654} DP_VID_VBID_FIELD_POL;
6655
6656/*
6657 * FEC_ACTIVE_STATUS enum
6658 */
6659
6660typedef enum FEC_ACTIVE_STATUS {
6661DPHY_FEC_NOT_ACTIVE = 0x00000000,
6662DPHY_FEC_ACTIVE = 0x00000001,
6663} FEC_ACTIVE_STATUS;
6664
6665/*******************************************************
6666 * DIG Enums
6667 *******************************************************/
6668
6669/*
6670 * DIG_BE_CNTL_HPD_SELECT enum
6671 */
6672
6673typedef enum DIG_BE_CNTL_HPD_SELECT {
6674DIG_BE_CNTL_HPD1 = 0x00000000,
6675DIG_BE_CNTL_HPD2 = 0x00000001,
6676DIG_BE_CNTL_HPD3 = 0x00000002,
6677DIG_BE_CNTL_HPD4 = 0x00000003,
6678DIG_BE_CNTL_HPD5 = 0x00000004,
6679DIG_BE_CNTL_NO_HPD = 0x00000005,
6680} DIG_BE_CNTL_HPD_SELECT;
6681
6682/*
6683 * DIG_BE_CNTL_MODE enum
6684 */
6685
6686typedef enum DIG_BE_CNTL_MODE {
6687DIG_BE_DP_SST_MODE = 0x00000000,
6688DIG_BE_RESERVED1 = 0x00000001,
6689DIG_BE_TMDS_DVI_MODE = 0x00000002,
6690DIG_BE_TMDS_HDMI_MODE = 0x00000003,
6691DIG_BE_RESERVED4 = 0x00000004,
6692DIG_BE_DP_MST_MODE = 0x00000005,
6693DIG_BE_RESERVED2 = 0x00000006,
6694DIG_BE_RESERVED3 = 0x00000007,
6695} DIG_BE_CNTL_MODE;
6696
6697/*
6698 * DIG_DIGITAL_BYPASS_ENABLE enum
6699 */
6700
6701typedef enum DIG_DIGITAL_BYPASS_ENABLE {
6702DIG_DIGITAL_BYPASS_OFF = 0x00000000,
6703DIG_DIGITAL_BYPASS_ON = 0x00000001,
6704} DIG_DIGITAL_BYPASS_ENABLE;
6705
6706/*
6707 * DIG_DIGITAL_BYPASS_SEL enum
6708 */
6709
6710typedef enum DIG_DIGITAL_BYPASS_SEL {
6711DIG_DIGITAL_BYPASS_SEL_BYPASS = 0x00000000,
6712DIG_DIGITAL_BYPASS_SEL_36BPP = 0x00000001,
6713DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 0x00000002,
6714DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 0x00000003,
6715DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 0x00000004,
6716DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 0x00000005,
6717DIG_DIGITAL_BYPASS_SEL_ALPHA = 0x00000006,
6718} DIG_DIGITAL_BYPASS_SEL;
6719
6720/*
6721 * DIG_FE_CNTL_SOURCE_SELECT enum
6722 */
6723
6724typedef enum DIG_FE_CNTL_SOURCE_SELECT {
6725DIG_FE_SOURCE_FROM_OTG0 = 0x00000000,
6726DIG_FE_SOURCE_FROM_OTG1 = 0x00000001,
6727DIG_FE_SOURCE_FROM_OTG2 = 0x00000002,
6728DIG_FE_SOURCE_FROM_OTG3 = 0x00000003,
6729DIG_FE_SOURCE_RESERVED = 0x00000004,
6730} DIG_FE_CNTL_SOURCE_SELECT;
6731
6732/*
6733 * DIG_FE_CNTL_STEREOSYNC_SELECT enum
6734 */
6735
6736typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
6737DIG_FE_STEREOSYNC_FROM_OTG0 = 0x00000000,
6738DIG_FE_STEREOSYNC_FROM_OTG1 = 0x00000001,
6739DIG_FE_STEREOSYNC_FROM_OTG2 = 0x00000002,
6740DIG_FE_STEREOSYNC_FROM_OTG3 = 0x00000003,
6741DIG_FE_STEREOSYNC_RESERVED = 0x00000004,
6742} DIG_FE_CNTL_STEREOSYNC_SELECT;
6743
6744/*
6745 * DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX enum
6746 */
6747
6748typedef enum DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX {
6749DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x00000000,
6750DIG_FIFO_FORCE_RECOMP_MINMAX = 0x00000001,
6751} DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX;
6752
6753/*
6754 * DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL enum
6755 */
6756
6757typedef enum DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL {
6758DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000000,
6759DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x00000001,
6760} DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL;
6761
6762/*
6763 * DIG_FIFO_FORCE_RECAL_AVERAGE enum
6764 */
6765
6766typedef enum DIG_FIFO_FORCE_RECAL_AVERAGE {
6767DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x00000000,
6768DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x00000001,
6769} DIG_FIFO_FORCE_RECAL_AVERAGE;
6770
6771/*
6772 * DIG_FIFO_OUTPUT_PROCESSING_MODE enum
6773 */
6774
6775typedef enum DIG_FIFO_OUTPUT_PROCESSING_MODE {
6776DIG_FIFO_1_PIX_PER_CYCLE = 0x00000000,
6777DIG_FIFO_2_PIX_PER_CYCLE = 0x00000001,
6778} DIG_FIFO_OUTPUT_PROCESSING_MODE;
6779
6780/*
6781 * DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR enum
6782 */
6783
6784typedef enum DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR {
6785DIG_FIFO_NO_ERROR_OCCURRED = 0x00000000,
6786DIG_FIFO_UNDERFLOW_OCCURRED = 0x00000001,
6787DIG_FIFO_OVERFLOW_OCCURRED = 0x00000002,
6788} DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR;
6789
6790/*
6791 * DIG_FIFO_READ_CLOCK_SRC enum
6792 */
6793
6794typedef enum DIG_FIFO_READ_CLOCK_SRC {
6795DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x00000000,
6796DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001,
6797} DIG_FIFO_READ_CLOCK_SRC;
6798
6799/*
6800 * DIG_INPUT_PIXEL_SEL enum
6801 */
6802
6803typedef enum DIG_INPUT_PIXEL_SEL {
6804DIG_ALL_PIXEL = 0x00000000,
6805DIG_EVEN_PIXEL_ONLY = 0x00000001,
6806DIG_ODD_PIXEL_ONLY = 0x00000002,
6807} DIG_INPUT_PIXEL_SEL;
6808
6809/*
6810 * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
6811 */
6812
6813typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
6814DIG_OUTPUT_CRC_ON_LINK0 = 0x00000000,
6815DIG_OUTPUT_CRC_ON_LINK1 = 0x00000001,
6816} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
6817
6818/*
6819 * DIG_OUTPUT_CRC_DATA_SEL enum
6820 */
6821
6822typedef enum DIG_OUTPUT_CRC_DATA_SEL {
6823DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x00000000,
6824DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x00000001,
6825DIG_OUTPUT_CRC_FOR_VBI = 0x00000002,
6826DIG_OUTPUT_CRC_FOR_AUDIO = 0x00000003,
6827} DIG_OUTPUT_CRC_DATA_SEL;
6828
6829/*
6830 * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
6831 */
6832
6833typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
6834DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000,
6835DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x00000001,
6836} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
6837
6838/*
6839 * DIG_SL_PIXEL_GROUPING enum
6840 */
6841
6842typedef enum DIG_SL_PIXEL_GROUPING {
6843DIG_SINGLETON_PIXELS = 0x00000000,
6844DIG_PAIR_PIXELS = 0x00000001,
6845} DIG_SL_PIXEL_GROUPING;
6846
6847/*
6848 * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
6849 */
6850
6851typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
6852DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x00000000,
6853DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001,
6854} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
6855
6856/*
6857 * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
6858 */
6859
6860typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
6861DIG_10BIT_TEST_PATTERN = 0x00000000,
6862DIG_ALTERNATING_TEST_PATTERN = 0x00000001,
6863} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
6864
6865/*
6866 * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
6867 */
6868
6869typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
6870DIG_TEST_PATTERN_NORMAL = 0x00000000,
6871DIG_TEST_PATTERN_RANDOM = 0x00000001,
6872} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
6873
6874/*
6875 * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
6876 */
6877
6878typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
6879DIG_RANDOM_PATTERN_ENABLED = 0x00000000,
6880DIG_RANDOM_PATTERN_RESETED = 0x00000001,
6881} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
6882
6883/*
6884 * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
6885 */
6886
6887typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
6888DIG_IN_NORMAL_OPERATION = 0x00000000,
6889DIG_IN_DEBUG_MODE = 0x00000001,
6890} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
6891
6892/*
6893 * DOLBY_VISION_ENABLE enum
6894 */
6895
6896typedef enum DOLBY_VISION_ENABLE {
6897DOLBY_VISION_DISABLED = 0x00000000,
6898DOLBY_VISION_ENABLED = 0x00000001,
6899} DOLBY_VISION_ENABLE;
6900
6901/*
6902 * HDMI_ACP_SEND enum
6903 */
6904
6905typedef enum HDMI_ACP_SEND {
6906HDMI_ACP_NOT_SEND = 0x00000000,
6907HDMI_ACP_PKT_SEND = 0x00000001,
6908} HDMI_ACP_SEND;
6909
6910/*
6911 * HDMI_ACR_AUDIO_PRIORITY enum
6912 */
6913
6914typedef enum HDMI_ACR_AUDIO_PRIORITY {
6915HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000,
6916HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001,
6917} HDMI_ACR_AUDIO_PRIORITY;
6918
6919/*
6920 * HDMI_ACR_CONT enum
6921 */
6922
6923typedef enum HDMI_ACR_CONT {
6924HDMI_ACR_CONT_DISABLE = 0x00000000,
6925HDMI_ACR_CONT_ENABLE = 0x00000001,
6926} HDMI_ACR_CONT;
6927
6928/*
6929 * HDMI_ACR_N_MULTIPLE enum
6930 */
6931
6932typedef enum HDMI_ACR_N_MULTIPLE {
6933HDMI_ACR_0_MULTIPLE_RESERVED = 0x00000000,
6934HDMI_ACR_1_MULTIPLE = 0x00000001,
6935HDMI_ACR_2_MULTIPLE = 0x00000002,
6936HDMI_ACR_3_MULTIPLE_RESERVED = 0x00000003,
6937HDMI_ACR_4_MULTIPLE = 0x00000004,
6938HDMI_ACR_5_MULTIPLE_RESERVED = 0x00000005,
6939HDMI_ACR_6_MULTIPLE_RESERVED = 0x00000006,
6940HDMI_ACR_7_MULTIPLE_RESERVED = 0x00000007,
6941} HDMI_ACR_N_MULTIPLE;
6942
6943/*
6944 * HDMI_ACR_SELECT enum
6945 */
6946
6947typedef enum HDMI_ACR_SELECT {
6948HDMI_ACR_SELECT_HW = 0x00000000,
6949HDMI_ACR_SELECT_32K = 0x00000001,
6950HDMI_ACR_SELECT_44K = 0x00000002,
6951HDMI_ACR_SELECT_48K = 0x00000003,
6952} HDMI_ACR_SELECT;
6953
6954/*
6955 * HDMI_ACR_SEND enum
6956 */
6957
6958typedef enum HDMI_ACR_SEND {
6959HDMI_ACR_NOT_SEND = 0x00000000,
6960HDMI_ACR_PKT_SEND = 0x00000001,
6961} HDMI_ACR_SEND;
6962
6963/*
6964 * HDMI_ACR_SOURCE enum
6965 */
6966
6967typedef enum HDMI_ACR_SOURCE {
6968HDMI_ACR_SOURCE_HW = 0x00000000,
6969HDMI_ACR_SOURCE_SW = 0x00000001,
6970} HDMI_ACR_SOURCE;
6971
6972/*
6973 * HDMI_AUDIO_DELAY_EN enum
6974 */
6975
6976typedef enum HDMI_AUDIO_DELAY_EN {
6977HDMI_AUDIO_DELAY_DISABLE = 0x00000000,
6978HDMI_AUDIO_DELAY_58CLK = 0x00000001,
6979HDMI_AUDIO_DELAY_56CLK = 0x00000002,
6980HDMI_AUDIO_DELAY_RESERVED = 0x00000003,
6981} HDMI_AUDIO_DELAY_EN;
6982
6983/*
6984 * HDMI_AUDIO_INFO_CONT enum
6985 */
6986
6987typedef enum HDMI_AUDIO_INFO_CONT {
6988HDMI_AUDIO_INFO_CONT_DISABLE = 0x00000000,
6989HDMI_AUDIO_INFO_CONT_ENABLE = 0x00000001,
6990} HDMI_AUDIO_INFO_CONT;
6991
6992/*
6993 * HDMI_AUDIO_INFO_SEND enum
6994 */
6995
6996typedef enum HDMI_AUDIO_INFO_SEND {
6997HDMI_AUDIO_INFO_NOT_SEND = 0x00000000,
6998HDMI_AUDIO_INFO_PKT_SEND = 0x00000001,
6999} HDMI_AUDIO_INFO_SEND;
7000
7001/*
7002 * HDMI_CLOCK_CHANNEL_RATE enum
7003 */
7004
7005typedef enum HDMI_CLOCK_CHANNEL_RATE {
7006HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000,
7007HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001,
7008} HDMI_CLOCK_CHANNEL_RATE;
7009
7010/*
7011 * HDMI_DATA_SCRAMBLE_EN enum
7012 */
7013
7014typedef enum HDMI_DATA_SCRAMBLE_EN {
7015HDMI_DATA_SCRAMBLE_DISABLE = 0x00000000,
7016HDMI_DATA_SCRAMBLE_ENABLE = 0x00000001,
7017} HDMI_DATA_SCRAMBLE_EN;
7018
7019/*
7020 * HDMI_DEEP_COLOR_DEPTH enum
7021 */
7022
7023typedef enum HDMI_DEEP_COLOR_DEPTH {
7024HDMI_DEEP_COLOR_DEPTH_24BPP = 0x00000000,
7025HDMI_DEEP_COLOR_DEPTH_30BPP = 0x00000001,
7026HDMI_DEEP_COLOR_DEPTH_36BPP = 0x00000002,
7027HDMI_DEEP_COLOR_DEPTH_48BPP = 0x00000003,
7028} HDMI_DEEP_COLOR_DEPTH;
7029
7030/*
7031 * HDMI_DEFAULT_PAHSE enum
7032 */
7033
7034typedef enum HDMI_DEFAULT_PAHSE {
7035HDMI_DEFAULT_PHASE_IS_0 = 0x00000000,
7036HDMI_DEFAULT_PHASE_IS_1 = 0x00000001,
7037} HDMI_DEFAULT_PAHSE;
7038
7039/*
7040 * HDMI_ERROR_ACK enum
7041 */
7042
7043typedef enum HDMI_ERROR_ACK {
7044HDMI_ERROR_ACK_INT = 0x00000000,
7045HDMI_ERROR_NOT_ACK = 0x00000001,
7046} HDMI_ERROR_ACK;
7047
7048/*
7049 * HDMI_ERROR_MASK enum
7050 */
7051
7052typedef enum HDMI_ERROR_MASK {
7053HDMI_ERROR_MASK_INT = 0x00000000,
7054HDMI_ERROR_NOT_MASK = 0x00000001,
7055} HDMI_ERROR_MASK;
7056
7057/*
7058 * HDMI_GC_AVMUTE enum
7059 */
7060
7061typedef enum HDMI_GC_AVMUTE {
7062HDMI_GC_AVMUTE_SET = 0x00000000,
7063HDMI_GC_AVMUTE_UNSET = 0x00000001,
7064} HDMI_GC_AVMUTE;
7065
7066/*
7067 * HDMI_GC_AVMUTE_CONT enum
7068 */
7069
7070typedef enum HDMI_GC_AVMUTE_CONT {
7071HDMI_GC_AVMUTE_CONT_DISABLE = 0x00000000,
7072HDMI_GC_AVMUTE_CONT_ENABLE = 0x00000001,
7073} HDMI_GC_AVMUTE_CONT;
7074
7075/*
7076 * HDMI_GC_CONT enum
7077 */
7078
7079typedef enum HDMI_GC_CONT {
7080HDMI_GC_CONT_DISABLE = 0x00000000,
7081HDMI_GC_CONT_ENABLE = 0x00000001,
7082} HDMI_GC_CONT;
7083
7084/*
7085 * HDMI_GC_SEND enum
7086 */
7087
7088typedef enum HDMI_GC_SEND {
7089HDMI_GC_NOT_SEND = 0x00000000,
7090HDMI_GC_PKT_SEND = 0x00000001,
7091} HDMI_GC_SEND;
7092
7093/*
7094 * HDMI_GENERIC_CONT enum
7095 */
7096
7097typedef enum HDMI_GENERIC_CONT {
7098HDMI_GENERIC_CONT_DISABLE = 0x00000000,
7099HDMI_GENERIC_CONT_ENABLE = 0x00000001,
7100} HDMI_GENERIC_CONT;
7101
7102/*
7103 * HDMI_GENERIC_SEND enum
7104 */
7105
7106typedef enum HDMI_GENERIC_SEND {
7107HDMI_GENERIC_NOT_SEND = 0x00000000,
7108HDMI_GENERIC_PKT_SEND = 0x00000001,
7109} HDMI_GENERIC_SEND;
7110
7111/*
7112 * HDMI_ISRC_CONT enum
7113 */
7114
7115typedef enum HDMI_ISRC_CONT {
7116HDMI_ISRC_CONT_DISABLE = 0x00000000,
7117HDMI_ISRC_CONT_ENABLE = 0x00000001,
7118} HDMI_ISRC_CONT;
7119
7120/*
7121 * HDMI_ISRC_SEND enum
7122 */
7123
7124typedef enum HDMI_ISRC_SEND {
7125HDMI_ISRC_NOT_SEND = 0x00000000,
7126HDMI_ISRC_PKT_SEND = 0x00000001,
7127} HDMI_ISRC_SEND;
7128
7129/*
7130 * HDMI_KEEPOUT_MODE enum
7131 */
7132
7133typedef enum HDMI_KEEPOUT_MODE {
7134HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x00000000,
7135HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x00000001,
7136} HDMI_KEEPOUT_MODE;
7137
7138/*
7139 * HDMI_METADATA_ENABLE enum
7140 */
7141
7142typedef enum HDMI_METADATA_ENABLE {
7143HDMI_METADATA_NOT_SEND = 0x00000000,
7144HDMI_METADATA_PKT_SEND = 0x00000001,
7145} HDMI_METADATA_ENABLE;
7146
7147/*
7148 * HDMI_MPEG_INFO_CONT enum
7149 */
7150
7151typedef enum HDMI_MPEG_INFO_CONT {
7152HDMI_MPEG_INFO_CONT_DISABLE = 0x00000000,
7153HDMI_MPEG_INFO_CONT_ENABLE = 0x00000001,
7154} HDMI_MPEG_INFO_CONT;
7155
7156/*
7157 * HDMI_MPEG_INFO_SEND enum
7158 */
7159
7160typedef enum HDMI_MPEG_INFO_SEND {
7161HDMI_MPEG_INFO_NOT_SEND = 0x00000000,
7162HDMI_MPEG_INFO_PKT_SEND = 0x00000001,
7163} HDMI_MPEG_INFO_SEND;
7164
7165/*
7166 * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
7167 */
7168
7169typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
7170HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x00000000,
7171HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x00000001,
7172} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
7173
7174/*
7175 * HDMI_NULL_SEND enum
7176 */
7177
7178typedef enum HDMI_NULL_SEND {
7179HDMI_NULL_NOT_SEND = 0x00000000,
7180HDMI_NULL_PKT_SEND = 0x00000001,
7181} HDMI_NULL_SEND;
7182
7183/*
7184 * HDMI_PACKET_GEN_VERSION enum
7185 */
7186
7187typedef enum HDMI_PACKET_GEN_VERSION {
7188HDMI_PACKET_GEN_VERSION_OLD = 0x00000000,
7189HDMI_PACKET_GEN_VERSION_NEW = 0x00000001,
7190} HDMI_PACKET_GEN_VERSION;
7191
7192/*
7193 * HDMI_PACKET_LINE_REFERENCE enum
7194 */
7195
7196typedef enum HDMI_PACKET_LINE_REFERENCE {
7197HDMI_PKT_LINE_REF_VSYNC = 0x00000000,
7198HDMI_PKT_LINE_REF_OTGSOF = 0x00000001,
7199} HDMI_PACKET_LINE_REFERENCE;
7200
7201/*
7202 * HDMI_PACKING_PHASE_OVERRIDE enum
7203 */
7204
7205typedef enum HDMI_PACKING_PHASE_OVERRIDE {
7206HDMI_PACKING_PHASE_SET_BY_HW = 0x00000000,
7207HDMI_PACKING_PHASE_SET_BY_SW = 0x00000001,
7208} HDMI_PACKING_PHASE_OVERRIDE;
7209
7210/*
7211 * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
7212 */
7213
7214typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
7215LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x00000000,
7216LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x00000001,
7217} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
7218
7219/*
7220 * TMDS_COLOR_FORMAT enum
7221 */
7222
7223typedef enum TMDS_COLOR_FORMAT {
7224TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000,
7225TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x00000001,
7226TMDS_COLOR_FORMAT_DUAL30BPP = 0x00000002,
7227TMDS_COLOR_FORMAT_RESERVED = 0x00000003,
7228} TMDS_COLOR_FORMAT;
7229
7230/*
7231 * TMDS_CTL0_DATA_INVERT enum
7232 */
7233
7234typedef enum TMDS_CTL0_DATA_INVERT {
7235TMDS_CTL0_DATA_NORMAL = 0x00000000,
7236TMDS_CTL0_DATA_INVERT_EN = 0x00000001,
7237} TMDS_CTL0_DATA_INVERT;
7238
7239/*
7240 * TMDS_CTL0_DATA_MODULATION enum
7241 */
7242
7243typedef enum TMDS_CTL0_DATA_MODULATION {
7244TMDS_CTL0_DATA_MODULATION_DISABLE = 0x00000000,
7245TMDS_CTL0_DATA_MODULATION_BIT0 = 0x00000001,
7246TMDS_CTL0_DATA_MODULATION_BIT1 = 0x00000002,
7247TMDS_CTL0_DATA_MODULATION_BIT2 = 0x00000003,
7248} TMDS_CTL0_DATA_MODULATION;
7249
7250/*
7251 * TMDS_CTL0_DATA_SEL enum
7252 */
7253
7254typedef enum TMDS_CTL0_DATA_SEL {
7255TMDS_CTL0_DATA_SEL0_RESERVED = 0x00000000,
7256TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
7257TMDS_CTL0_DATA_SEL2_VSYNC = 0x00000002,
7258TMDS_CTL0_DATA_SEL3_RESERVED = 0x00000003,
7259TMDS_CTL0_DATA_SEL4_HSYNC = 0x00000004,
7260TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x00000005,
7261TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x00000006,
7262TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x00000007,
7263} TMDS_CTL0_DATA_SEL;
7264
7265/*
7266 * TMDS_CTL0_PATTERN_OUT_EN enum
7267 */
7268
7269typedef enum TMDS_CTL0_PATTERN_OUT_EN {
7270TMDS_CTL0_PATTERN_OUT_DISABLE = 0x00000000,
7271TMDS_CTL0_PATTERN_OUT_ENABLE = 0x00000001,
7272} TMDS_CTL0_PATTERN_OUT_EN;
7273
7274/*
7275 * TMDS_CTL1_DATA_INVERT enum
7276 */
7277
7278typedef enum TMDS_CTL1_DATA_INVERT {
7279TMDS_CTL1_DATA_NORMAL = 0x00000000,
7280TMDS_CTL1_DATA_INVERT_EN = 0x00000001,
7281} TMDS_CTL1_DATA_INVERT;
7282
7283/*
7284 * TMDS_CTL1_DATA_MODULATION enum
7285 */
7286
7287typedef enum TMDS_CTL1_DATA_MODULATION {
7288TMDS_CTL1_DATA_MODULATION_DISABLE = 0x00000000,
7289TMDS_CTL1_DATA_MODULATION_BIT0 = 0x00000001,
7290TMDS_CTL1_DATA_MODULATION_BIT1 = 0x00000002,
7291TMDS_CTL1_DATA_MODULATION_BIT2 = 0x00000003,
7292} TMDS_CTL1_DATA_MODULATION;
7293
7294/*
7295 * TMDS_CTL1_DATA_SEL enum
7296 */
7297
7298typedef enum TMDS_CTL1_DATA_SEL {
7299TMDS_CTL1_DATA_SEL0_RESERVED = 0x00000000,
7300TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
7301TMDS_CTL1_DATA_SEL2_VSYNC = 0x00000002,
7302TMDS_CTL1_DATA_SEL3_RESERVED = 0x00000003,
7303TMDS_CTL1_DATA_SEL4_HSYNC = 0x00000004,
7304TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x00000005,
7305TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x00000006,
7306TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x00000007,
7307} TMDS_CTL1_DATA_SEL;
7308
7309/*
7310 * TMDS_CTL1_PATTERN_OUT_EN enum
7311 */
7312
7313typedef enum TMDS_CTL1_PATTERN_OUT_EN {
7314TMDS_CTL1_PATTERN_OUT_DISABLE = 0x00000000,
7315TMDS_CTL1_PATTERN_OUT_ENABLE = 0x00000001,
7316} TMDS_CTL1_PATTERN_OUT_EN;
7317
7318/*
7319 * TMDS_CTL2_DATA_INVERT enum
7320 */
7321
7322typedef enum TMDS_CTL2_DATA_INVERT {
7323TMDS_CTL2_DATA_NORMAL = 0x00000000,
7324TMDS_CTL2_DATA_INVERT_EN = 0x00000001,
7325} TMDS_CTL2_DATA_INVERT;
7326
7327/*
7328 * TMDS_CTL2_DATA_MODULATION enum
7329 */
7330
7331typedef enum TMDS_CTL2_DATA_MODULATION {
7332TMDS_CTL2_DATA_MODULATION_DISABLE = 0x00000000,
7333TMDS_CTL2_DATA_MODULATION_BIT0 = 0x00000001,
7334TMDS_CTL2_DATA_MODULATION_BIT1 = 0x00000002,
7335TMDS_CTL2_DATA_MODULATION_BIT2 = 0x00000003,
7336} TMDS_CTL2_DATA_MODULATION;
7337
7338/*
7339 * TMDS_CTL2_DATA_SEL enum
7340 */
7341
7342typedef enum TMDS_CTL2_DATA_SEL {
7343TMDS_CTL2_DATA_SEL0_RESERVED = 0x00000000,
7344TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
7345TMDS_CTL2_DATA_SEL2_VSYNC = 0x00000002,
7346TMDS_CTL2_DATA_SEL3_RESERVED = 0x00000003,
7347TMDS_CTL2_DATA_SEL4_HSYNC = 0x00000004,
7348TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x00000005,
7349TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x00000006,
7350TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x00000007,
7351} TMDS_CTL2_DATA_SEL;
7352
7353/*
7354 * TMDS_CTL2_PATTERN_OUT_EN enum
7355 */
7356
7357typedef enum TMDS_CTL2_PATTERN_OUT_EN {
7358TMDS_CTL2_PATTERN_OUT_DISABLE = 0x00000000,
7359TMDS_CTL2_PATTERN_OUT_ENABLE = 0x00000001,
7360} TMDS_CTL2_PATTERN_OUT_EN;
7361
7362/*
7363 * TMDS_CTL3_DATA_INVERT enum
7364 */
7365
7366typedef enum TMDS_CTL3_DATA_INVERT {
7367TMDS_CTL3_DATA_NORMAL = 0x00000000,
7368TMDS_CTL3_DATA_INVERT_EN = 0x00000001,
7369} TMDS_CTL3_DATA_INVERT;
7370
7371/*
7372 * TMDS_CTL3_DATA_MODULATION enum
7373 */
7374
7375typedef enum TMDS_CTL3_DATA_MODULATION {
7376TMDS_CTL3_DATA_MODULATION_DISABLE = 0x00000000,
7377TMDS_CTL3_DATA_MODULATION_BIT0 = 0x00000001,
7378TMDS_CTL3_DATA_MODULATION_BIT1 = 0x00000002,
7379TMDS_CTL3_DATA_MODULATION_BIT2 = 0x00000003,
7380} TMDS_CTL3_DATA_MODULATION;
7381
7382/*
7383 * TMDS_CTL3_DATA_SEL enum
7384 */
7385
7386typedef enum TMDS_CTL3_DATA_SEL {
7387TMDS_CTL3_DATA_SEL0_RESERVED = 0x00000000,
7388TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
7389TMDS_CTL3_DATA_SEL2_VSYNC = 0x00000002,
7390TMDS_CTL3_DATA_SEL3_RESERVED = 0x00000003,
7391TMDS_CTL3_DATA_SEL4_HSYNC = 0x00000004,
7392TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x00000005,
7393TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x00000006,
7394TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x00000007,
7395} TMDS_CTL3_DATA_SEL;
7396
7397/*
7398 * TMDS_CTL3_PATTERN_OUT_EN enum
7399 */
7400
7401typedef enum TMDS_CTL3_PATTERN_OUT_EN {
7402TMDS_CTL3_PATTERN_OUT_DISABLE = 0x00000000,
7403TMDS_CTL3_PATTERN_OUT_ENABLE = 0x00000001,
7404} TMDS_CTL3_PATTERN_OUT_EN;
7405
7406/*
7407 * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
7408 */
7409
7410typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
7411TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x00000000,
7412TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x00000001,
7413} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
7414
7415/*
7416 * TMDS_PIXEL_ENCODING enum
7417 */
7418
7419typedef enum TMDS_PIXEL_ENCODING {
7420TMDS_PIXEL_ENCODING_444_OR_420 = 0x00000000,
7421TMDS_PIXEL_ENCODING_422 = 0x00000001,
7422} TMDS_PIXEL_ENCODING;
7423
7424/*
7425 * TMDS_REG_TEST_OUTPUTA_CNTLA enum
7426 */
7427
7428typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
7429TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x00000000,
7430TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x00000001,
7431TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x00000002,
7432TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x00000003,
7433} TMDS_REG_TEST_OUTPUTA_CNTLA;
7434
7435/*
7436 * TMDS_REG_TEST_OUTPUTB_CNTLB enum
7437 */
7438
7439typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
7440TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x00000000,
7441TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x00000001,
7442TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x00000002,
7443TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x00000003,
7444} TMDS_REG_TEST_OUTPUTB_CNTLB;
7445
7446/*
7447 * TMDS_STEREOSYNC_CTL_SEL_REG enum
7448 */
7449
7450typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
7451TMDS_STEREOSYNC_CTL0 = 0x00000000,
7452TMDS_STEREOSYNC_CTL1 = 0x00000001,
7453TMDS_STEREOSYNC_CTL2 = 0x00000002,
7454TMDS_STEREOSYNC_CTL3 = 0x00000003,
7455} TMDS_STEREOSYNC_CTL_SEL_REG;
7456
7457/*
7458 * TMDS_SYNC_PHASE enum
7459 */
7460
7461typedef enum TMDS_SYNC_PHASE {
7462TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000,
7463TMDS_SYNC_PHASE_ON_FRAME_START = 0x00000001,
7464} TMDS_SYNC_PHASE;
7465
7466/*
7467 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
7468 */
7469
7470typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
7471TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x00000000,
7472TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x00000001,
7473} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
7474
7475/*
7476 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
7477 */
7478
7479typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
7480TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x00000000,
7481TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x00000001,
7482} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
7483
7484/*
7485 * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
7486 */
7487
7488typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
7489TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x00000000,
7490TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x00000001,
7491} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
7492
7493/*
7494 * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
7495 */
7496
7497typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
7498TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x00000000,
7499TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x00000001,
7500} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
7501
7502/*
7503 * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
7504 */
7505
7506typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
7507TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x00000000,
7508TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x00000001,
7509} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
7510
7511/*
7512 * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
7513 */
7514
7515typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
7516TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x00000000,
7517TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 0x00000001,
7518TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x00000002,
7519TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x00000003,
7520} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
7521
7522/*
7523 * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
7524 */
7525
7526typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
7527TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x00000000,
7528TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x00000001,
7529} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
7530
7531/*
7532 * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
7533 */
7534
7535typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
7536TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x00000000,
7537TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x00000001,
7538} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
7539
7540/*
7541 * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
7542 */
7543
7544typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
7545TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x00000000,
7546TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x00000001,
7547} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
7548
7549/*
7550 * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
7551 */
7552
7553typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
7554TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x00000000,
7555TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x00000001,
7556} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
7557
7558/*
7559 * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
7560 */
7561
7562typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
7563TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x00000000,
7564TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x00000001,
7565} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
7566
7567/*
7568 * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
7569 */
7570
7571typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
7572TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
7573TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x00000001,
7574} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
7575
7576/*
7577 * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
7578 */
7579
7580typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
7581TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
7582TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x00000001,
7583} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
7584
7585/*******************************************************
7586 * DP_AUX Enums
7587 *******************************************************/
7588
7589/*
7590 * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
7591 */
7592
7593typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
7594DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x00000000,
7595DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x00000001,
7596DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x00000002,
7597DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x00000003,
7598} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
7599
7600/*
7601 * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
7602 */
7603
7604typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
7605DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000,
7606DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x00000001,
7607} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
7608
7609/*
7610 * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
7611 */
7612
7613typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
7614DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x00000000,
7615DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x00000001,
7616} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
7617
7618/*
7619 * DP_AUX_ARB_STATUS enum
7620 */
7621
7622typedef enum DP_AUX_ARB_STATUS {
7623DP_AUX_IDLE = 0x00000000,
7624DP_AUX_IN_USE_LS = 0x00000001,
7625DP_AUX_IN_USE_GTC = 0x00000002,
7626DP_AUX_IN_USE_SW = 0x00000003,
7627DP_AUX_IN_USE_PHYWAKE = 0x00000004,
7628} DP_AUX_ARB_STATUS;
7629
7630/*
7631 * DP_AUX_CONTROL_HPD_SEL enum
7632 */
7633
7634typedef enum DP_AUX_CONTROL_HPD_SEL {
7635DP_AUX_CONTROL_HPD1_SELECTED = 0x00000000,
7636DP_AUX_CONTROL_HPD2_SELECTED = 0x00000001,
7637DP_AUX_CONTROL_HPD3_SELECTED = 0x00000002,
7638DP_AUX_CONTROL_HPD4_SELECTED = 0x00000003,
7639DP_AUX_CONTROL_HPD5_SELECTED = 0x00000004,
7640DP_AUX_CONTROL_NO_HPD_SELECTED = 0x00000005,
7641} DP_AUX_CONTROL_HPD_SEL;
7642
7643/*
7644 * DP_AUX_CONTROL_TEST_MODE enum
7645 */
7646
7647typedef enum DP_AUX_CONTROL_TEST_MODE {
7648DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x00000000,
7649DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x00000001,
7650} DP_AUX_CONTROL_TEST_MODE;
7651
7652/*
7653 * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
7654 */
7655
7656typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
7657ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000,
7658ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x00000001,
7659} DP_AUX_DEFINITE_ERR_REACHED_ACK;
7660
7661/*
7662 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
7663 */
7664
7665typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
7666DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000,
7667DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001,
7668} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
7669
7670/*
7671 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
7672 */
7673
7674typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
7675DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000,
7676DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001,
7677} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
7678
7679/*
7680 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
7681 */
7682
7683typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
7684DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000,
7685DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001,
7686} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
7687
7688/*
7689 * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
7690 */
7691
7692typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
7693DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000,
7694DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001,
7695DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002,
7696DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003,
7697} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
7698
7699/*
7700 * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
7701 */
7702
7703typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
7704DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000,
7705DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001,
7706DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002,
7707DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003,
7708} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
7709
7710/*
7711 * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
7712 */
7713
7714typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
7715DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0x00000000,
7716DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 0x00000001,
7717DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 0x00000002,
7718DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 0x00000003,
7719DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 0x00000004,
7720DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 0x00000005,
7721DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 0x00000006,
7722DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 0x00000007,
7723} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
7724
7725/*
7726 * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
7727 */
7728
7729typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
7730DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x00000000,
7731DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x00000001,
7732DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x00000002,
7733DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 0x00000003,
7734DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 0x00000004,
7735DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 0x00000005,
7736DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 0x00000006,
7737DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 0x00000007,
7738} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
7739
7740/*
7741 * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
7742 */
7743
7744typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
7745DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x00000000,
7746DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x00000001,
7747DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x00000002,
7748DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x00000003,
7749DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x00000004,
7750DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x00000005,
7751DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x00000006,
7752DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x00000007,
7753} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
7754
7755/*
7756 * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
7757 */
7758
7759typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
7760DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000,
7761DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001,
7762DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002,
7763DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003,
7764DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004,
7765DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005,
7766} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
7767
7768/*
7769 * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
7770 */
7771
7772typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
7773DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000,
7774DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001,
7775DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002,
7776DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003,
7777} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
7778
7779/*
7780 * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
7781 */
7782
7783typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
7784DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0x00000000,
7785DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 0x00000001,
7786} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
7787
7788/*
7789 * DP_AUX_ERR_OCCURRED_ACK enum
7790 */
7791
7792typedef enum DP_AUX_ERR_OCCURRED_ACK {
7793DP_AUX_ERR_OCCURRED__NOT_ACK = 0x00000000,
7794DP_AUX_ERR_OCCURRED__ACK = 0x00000001,
7795} DP_AUX_ERR_OCCURRED_ACK;
7796
7797/*
7798 * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
7799 */
7800
7801typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
7802DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0x00000000,
7803DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 0x00000001,
7804} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
7805
7806/*
7807 * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
7808 */
7809
7810typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
7811DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000,
7812DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001,
7813DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002,
7814DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003,
7815} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
7816
7817/*
7818 * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
7819 */
7820
7821typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
7822DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000,
7823DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001,
7824DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002,
7825DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003,
7826} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
7827
7828/*
7829 * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
7830 */
7831
7832typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
7833DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0x00000000,
7834DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 0x00000001,
7835DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 0x00000002,
7836DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 0x00000003,
7837} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
7838
7839/*
7840 * DP_AUX_INT_ACK enum
7841 */
7842
7843typedef enum DP_AUX_INT_ACK {
7844DP_AUX_INT__NOT_ACK = 0x00000000,
7845DP_AUX_INT__ACK = 0x00000001,
7846} DP_AUX_INT_ACK;
7847
7848/*
7849 * DP_AUX_LS_UPDATE_ACK enum
7850 */
7851
7852typedef enum DP_AUX_LS_UPDATE_ACK {
7853DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x00000000,
7854DP_AUX_INT_LS_UPDATE_ACK = 0x00000001,
7855} DP_AUX_LS_UPDATE_ACK;
7856
7857/*
7858 * DP_AUX_PHY_WAKE_PRIORITY enum
7859 */
7860
7861typedef enum DP_AUX_PHY_WAKE_PRIORITY {
7862DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0x00000000,
7863DP_AUX_PHY_WAKE_LOW_PRIORITY = 0x00000001,
7864} DP_AUX_PHY_WAKE_PRIORITY;
7865
7866/*
7867 * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
7868 */
7869
7870typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
7871DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x00000000,
7872DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x00000001,
7873} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
7874
7875/*
7876 * DP_AUX_RESET enum
7877 */
7878
7879typedef enum DP_AUX_RESET {
7880DP_AUX_RESET_DEASSERTED = 0x00000000,
7881DP_AUX_RESET_ASSERTED = 0x00000001,
7882} DP_AUX_RESET;
7883
7884/*
7885 * DP_AUX_RESET_DONE enum
7886 */
7887
7888typedef enum DP_AUX_RESET_DONE {
7889DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x00000000,
7890DP_AUX_RESET_SEQUENCE_DONE = 0x00000001,
7891} DP_AUX_RESET_DONE;
7892
7893/*
7894 * DP_AUX_RX_TIMEOUT_LEN_MUL enum
7895 */
7896
7897typedef enum DP_AUX_RX_TIMEOUT_LEN_MUL {
7898DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0x00000000,
7899DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 0x00000001,
7900DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 0x00000002,
7901DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 0x00000003,
7902} DP_AUX_RX_TIMEOUT_LEN_MUL;
7903
7904/*
7905 * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
7906 */
7907
7908typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
7909DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x00000000,
7910DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x00000001,
7911} DP_AUX_SW_CONTROL_LS_READ_TRIG;
7912
7913/*
7914 * DP_AUX_SW_CONTROL_SW_GO enum
7915 */
7916
7917typedef enum DP_AUX_SW_CONTROL_SW_GO {
7918DP_AUX_SW_CONTROL_SW__NOT_GO = 0x00000000,
7919DP_AUX_SW_CONTROL_SW__GO = 0x00000001,
7920} DP_AUX_SW_CONTROL_SW_GO;
7921
7922/*
7923 * DP_AUX_TX_PRECHARGE_LEN_MUL enum
7924 */
7925
7926typedef enum DP_AUX_TX_PRECHARGE_LEN_MUL {
7927DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0x00000000,
7928DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 0x00000001,
7929DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 0x00000002,
7930DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 0x00000003,
7931} DP_AUX_TX_PRECHARGE_LEN_MUL;
7932
7933/*******************************************************
7934 * DOUT_I2C Enums
7935 *******************************************************/
7936
7937/*
7938 * DOUT_I2C_ACK enum
7939 */
7940
7941typedef enum DOUT_I2C_ACK {
7942DOUT_I2C_NO_ACK = 0x00000000,
7943DOUT_I2C_ACK_TO_CLEAN = 0x00000001,
7944} DOUT_I2C_ACK;
7945
7946/*
7947 * DOUT_I2C_ARBITRATION_ABORT_XFER enum
7948 */
7949
7950typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
7951DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000,
7952DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x00000001,
7953} DOUT_I2C_ARBITRATION_ABORT_XFER;
7954
7955/*
7956 * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
7957 */
7958
7959typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
7960DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000,
7961DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x00000001,
7962} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
7963
7964/*
7965 * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
7966 */
7967
7968typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
7969DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x00000000,
7970DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x00000001,
7971} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
7972
7973/*
7974 * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
7975 */
7976
7977typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
7978DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x00000000,
7979DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x00000001,
7980DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002,
7981DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003,
7982} DOUT_I2C_ARBITRATION_SW_PRIORITY;
7983
7984/*
7985 * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
7986 */
7987
7988typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
7989DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000,
7990DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x00000001,
7991} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
7992
7993/*
7994 * DOUT_I2C_CONTROL_DBG_REF_SEL enum
7995 */
7996
7997typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
7998DOUT_I2C_CONTROL_NORMAL_DEBUG = 0x00000000,
7999DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG = 0x00000001,
8000} DOUT_I2C_CONTROL_DBG_REF_SEL;
8001
8002/*
8003 * DOUT_I2C_CONTROL_DDC_SELECT enum
8004 */
8005
8006typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
8007DOUT_I2C_CONTROL_SELECT_DDC1 = 0x00000000,
8008DOUT_I2C_CONTROL_SELECT_DDC2 = 0x00000001,
8009DOUT_I2C_CONTROL_SELECT_DDC3 = 0x00000002,
8010DOUT_I2C_CONTROL_SELECT_DDC4 = 0x00000003,
8011DOUT_I2C_CONTROL_SELECT_DDC5 = 0x00000004,
8012DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x00000005,
8013} DOUT_I2C_CONTROL_DDC_SELECT;
8014
8015/*
8016 * DOUT_I2C_CONTROL_GO enum
8017 */
8018
8019typedef enum DOUT_I2C_CONTROL_GO {
8020DOUT_I2C_CONTROL_STOP_TRANSFER = 0x00000000,
8021DOUT_I2C_CONTROL_START_TRANSFER = 0x00000001,
8022} DOUT_I2C_CONTROL_GO;
8023
8024/*
8025 * DOUT_I2C_CONTROL_SEND_RESET enum
8026 */
8027
8028typedef enum DOUT_I2C_CONTROL_SEND_RESET {
8029DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x00000000,
8030DOUT_I2C_CONTROL__SEND_RESET = 0x00000001,
8031} DOUT_I2C_CONTROL_SEND_RESET;
8032
8033/*
8034 * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum
8035 */
8036
8037typedef enum DOUT_I2C_CONTROL_SEND_RESET_LENGTH {
8038DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0x00000000,
8039DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 0x00000001,
8040} DOUT_I2C_CONTROL_SEND_RESET_LENGTH;
8041
8042/*
8043 * DOUT_I2C_CONTROL_SOFT_RESET enum
8044 */
8045
8046typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
8047DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000,
8048DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x00000001,
8049} DOUT_I2C_CONTROL_SOFT_RESET;
8050
8051/*
8052 * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
8053 */
8054
8055typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
8056DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x00000000,
8057DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x00000001,
8058} DOUT_I2C_CONTROL_SW_STATUS_RESET;
8059
8060/*
8061 * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
8062 */
8063
8064typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
8065DOUT_I2C_CONTROL_TRANS0 = 0x00000000,
8066DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x00000001,
8067DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x00000002,
8068DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x00000003,
8069} DOUT_I2C_CONTROL_TRANSACTION_COUNT;
8070
8071/*
8072 * DOUT_I2C_DATA_INDEX_WRITE enum
8073 */
8074
8075typedef enum DOUT_I2C_DATA_INDEX_WRITE {
8076DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x00000000,
8077DOUT_I2C_DATA__INDEX_WRITE = 0x00000001,
8078} DOUT_I2C_DATA_INDEX_WRITE;
8079
8080/*
8081 * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
8082 */
8083
8084typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
8085DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
8086DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x00000001,
8087} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
8088
8089/*
8090 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
8091 */
8092
8093typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
8094DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
8095DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x00000001,
8096} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
8097
8098/*
8099 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
8100 */
8101
8102typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
8103DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x00000000,
8104DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x00000001,
8105} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
8106
8107/*
8108 * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
8109 */
8110
8111typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
8112DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x00000000,
8113DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x00000001,
8114} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
8115
8116/*
8117 * DOUT_I2C_DDC_SPEED_THRESHOLD enum
8118 */
8119
8120typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
8121DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x00000000,
8122DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 0x00000001,
8123DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 0x00000002,
8124DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 0x00000003,
8125} DOUT_I2C_DDC_SPEED_THRESHOLD;
8126
8127/*
8128 * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
8129 */
8130
8131typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
8132DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000,
8133DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000001,
8134} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
8135
8136/*
8137 * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
8138 */
8139
8140typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
8141DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x00000000,
8142DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x00000001,
8143} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
8144
8145/*
8146 * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
8147 */
8148
8149typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
8150DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x00000000,
8151DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x00000001,
8152} DOUT_I2C_TRANSACTION_STOP_ON_NACK;
8153
8154/*******************************************************
8155 * DIO_MISC Enums
8156 *******************************************************/
8157
8158/*
8159 * CLOCK_GATING_EN enum
8160 */
8161
8162typedef enum CLOCK_GATING_EN {
8163CLOCK_GATING_ENABLE = 0x00000000,
8164CLOCK_GATING_DISABLE = 0x00000001,
8165} CLOCK_GATING_EN;
8166
8167/*
8168 * DAC_MUX_SELECT enum
8169 */
8170
8171typedef enum DAC_MUX_SELECT {
8172DAC_MUX_SELECT_DACA = 0x00000000,
8173DAC_MUX_SELECT_DACB = 0x00000001,
8174} DAC_MUX_SELECT;
8175
8176/*
8177 * DIOMEM_PWR_DIS_CTRL enum
8178 */
8179
8180typedef enum DIOMEM_PWR_DIS_CTRL {
8181DIOMEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
8182DIOMEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
8183} DIOMEM_PWR_DIS_CTRL;
8184
8185/*
8186 * DIOMEM_PWR_FORCE_CTRL enum
8187 */
8188
8189typedef enum DIOMEM_PWR_FORCE_CTRL {
8190DIOMEM_NO_FORCE_REQUEST = 0x00000000,
8191DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
8192DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
8193DIOMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
8194} DIOMEM_PWR_FORCE_CTRL;
8195
8196/*
8197 * DIOMEM_PWR_FORCE_CTRL2 enum
8198 */
8199
8200typedef enum DIOMEM_PWR_FORCE_CTRL2 {
8201DIOMEM_NO_FORCE_REQ = 0x00000000,
8202DIOMEM_FORCE_LIGHT_SLEEP_REQ = 0x00000001,
8203} DIOMEM_PWR_FORCE_CTRL2;
8204
8205/*
8206 * DIOMEM_PWR_SEL_CTRL enum
8207 */
8208
8209typedef enum DIOMEM_PWR_SEL_CTRL {
8210DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
8211DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001,
8212DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002,
8213} DIOMEM_PWR_SEL_CTRL;
8214
8215/*
8216 * DIOMEM_PWR_SEL_CTRL2 enum
8217 */
8218
8219typedef enum DIOMEM_PWR_SEL_CTRL2 {
8220DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0x00000000,
8221DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 0x00000001,
8222} DIOMEM_PWR_SEL_CTRL2;
8223
8224/*
8225 * DIO_DBG_BLOCK_SEL enum
8226 */
8227
8228typedef enum DIO_DBG_BLOCK_SEL {
8229DIO_DBG_BLOCK_SEL_DIO = 0x00000000,
8230DIO_DBG_BLOCK_SEL_DIGFE_A = 0x0000000b,
8231DIO_DBG_BLOCK_SEL_DIGFE_B = 0x0000000c,
8232DIO_DBG_BLOCK_SEL_DIGFE_C = 0x0000000d,
8233DIO_DBG_BLOCK_SEL_DIGFE_D = 0x0000000e,
8234DIO_DBG_BLOCK_SEL_DIGFE_E = 0x0000000f,
8235DIO_DBG_BLOCK_SEL_DIGA = 0x00000012,
8236DIO_DBG_BLOCK_SEL_DIGB = 0x00000013,
8237DIO_DBG_BLOCK_SEL_DIGC = 0x00000014,
8238DIO_DBG_BLOCK_SEL_DIGD = 0x00000015,
8239DIO_DBG_BLOCK_SEL_DIGE = 0x00000016,
8240DIO_DBG_BLOCK_SEL_DPFE_A = 0x00000019,
8241DIO_DBG_BLOCK_SEL_DPFE_B = 0x0000001a,
8242DIO_DBG_BLOCK_SEL_DPFE_C = 0x0000001b,
8243DIO_DBG_BLOCK_SEL_DPFE_D = 0x0000001c,
8244DIO_DBG_BLOCK_SEL_DPFE_E = 0x0000001d,
8245DIO_DBG_BLOCK_SEL_DPA = 0x00000020,
8246DIO_DBG_BLOCK_SEL_DPB = 0x00000021,
8247DIO_DBG_BLOCK_SEL_DPC = 0x00000022,
8248DIO_DBG_BLOCK_SEL_DPD = 0x00000023,
8249DIO_DBG_BLOCK_SEL_DPE = 0x00000024,
8250DIO_DBG_BLOCK_SEL_AUX0 = 0x00000027,
8251DIO_DBG_BLOCK_SEL_AUX1 = 0x00000028,
8252DIO_DBG_BLOCK_SEL_AUX2 = 0x00000029,
8253DIO_DBG_BLOCK_SEL_AUX3 = 0x0000002a,
8254DIO_DBG_BLOCK_SEL_AUX4 = 0x0000002b,
8255DIO_DBG_BLOCK_SEL_PERFMON_DIO = 0x0000002d,
8256DIO_DBG_BLOCK_SEL_RESERVED = 0x0000002e,
8257} DIO_DBG_BLOCK_SEL;
8258
8259/*
8260 * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum
8261 */
8262
8263typedef enum DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE {
8264DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x00000000,
8265DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x00000001,
8266} DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE;
8267
8268/*
8269 * DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE enum
8270 */
8271
8272typedef enum DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE {
8273DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0x00000000,
8274DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 0x00000001,
8275} DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE;
8276
8277/*
8278 * ENUM_DIO_DCN_ACTIVE_STATUS enum
8279 */
8280
8281typedef enum ENUM_DIO_DCN_ACTIVE_STATUS {
8282ENUM_DCN_NOT_ACTIVE = 0x00000000,
8283ENUM_DCN_ACTIVE = 0x00000001,
8284} ENUM_DIO_DCN_ACTIVE_STATUS;
8285
8286/*
8287 * GENERIC_STEREOSYNC_SEL enum
8288 */
8289
8290typedef enum GENERIC_STEREOSYNC_SEL {
8291GENERIC_STEREOSYNC_SEL_D1 = 0x00000000,
8292GENERIC_STEREOSYNC_SEL_D2 = 0x00000001,
8293GENERIC_STEREOSYNC_SEL_D3 = 0x00000002,
8294GENERIC_STEREOSYNC_SEL_D4 = 0x00000003,
8295GENERIC_STEREOSYNC_SEL_RESERVED = 0x00000004,
8296} GENERIC_STEREOSYNC_SEL;
8297
8298/*
8299 * PM_ASSERT_RESET enum
8300 */
8301
8302typedef enum PM_ASSERT_RESET {
8303PM_ASSERT_RESET_0 = 0x00000000,
8304PM_ASSERT_RESET_1 = 0x00000001,
8305} PM_ASSERT_RESET;
8306
8307/*
8308 * SOFT_RESET enum
8309 */
8310
8311typedef enum SOFT_RESET {
8312SOFT_RESET_0 = 0x00000000,
8313SOFT_RESET_1 = 0x00000001,
8314} SOFT_RESET;
8315
8316/*
8317 * TMDS_MUX_SELECT enum
8318 */
8319
8320typedef enum TMDS_MUX_SELECT {
8321TMDS_MUX_SELECT_B = 0x00000000,
8322TMDS_MUX_SELECT_G = 0x00000001,
8323TMDS_MUX_SELECT_R = 0x00000002,
8324TMDS_MUX_SELECT_RESERVED = 0x00000003,
8325} TMDS_MUX_SELECT;
8326
8327/*******************************************************
8328 * DME Enums
8329 *******************************************************/
8330
8331/*
8332 * DME_MEM_POWER_STATE_ENUM enum
8333 */
8334
8335typedef enum DME_MEM_POWER_STATE_ENUM {
8336DME_MEM_POWER_STATE_ENUM_ON = 0x00000000,
8337DME_MEM_POWER_STATE_ENUM_LS = 0x00000001,
8338DME_MEM_POWER_STATE_ENUM_DS = 0x00000002,
8339DME_MEM_POWER_STATE_ENUM_SD = 0x00000003,
8340} DME_MEM_POWER_STATE_ENUM;
8341
8342/*
8343 * DME_MEM_PWR_DIS_CTRL enum
8344 */
8345
8346typedef enum DME_MEM_PWR_DIS_CTRL {
8347DME_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
8348DME_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
8349} DME_MEM_PWR_DIS_CTRL;
8350
8351/*
8352 * DME_MEM_PWR_FORCE_CTRL enum
8353 */
8354
8355typedef enum DME_MEM_PWR_FORCE_CTRL {
8356DME_MEM_NO_FORCE_REQUEST = 0x00000000,
8357DME_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
8358DME_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
8359DME_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
8360} DME_MEM_PWR_FORCE_CTRL;
8361
8362/*
8363 * METADATA_HUBP_SEL enum
8364 */
8365
8366typedef enum METADATA_HUBP_SEL {
8367METADATA_HUBP_SEL_0 = 0x00000000,
8368METADATA_HUBP_SEL_1 = 0x00000001,
8369METADATA_HUBP_SEL_2 = 0x00000002,
8370METADATA_HUBP_SEL_3 = 0x00000003,
8371METADATA_HUBP_SEL_RESERVED = 0x00000004,
8372} METADATA_HUBP_SEL;
8373
8374/*
8375 * METADATA_STREAM_TYPE_SEL enum
8376 */
8377
8378typedef enum METADATA_STREAM_TYPE_SEL {
8379METADATA_STREAM_DP = 0x00000000,
8380METADATA_STREAM_DVE = 0x00000001,
8381} METADATA_STREAM_TYPE_SEL;
8382
8383/*******************************************************
8384 * VPG Enums
8385 *******************************************************/
8386
8387/*
8388 * VPG_MEM_PWR_DIS_CTRL enum
8389 */
8390
8391typedef enum VPG_MEM_PWR_DIS_CTRL {
8392VPG_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
8393VPG_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
8394} VPG_MEM_PWR_DIS_CTRL;
8395
8396/*
8397 * VPG_MEM_PWR_FORCE_CTRL enum
8398 */
8399
8400typedef enum VPG_MEM_PWR_FORCE_CTRL {
8401VPG_MEM_NO_FORCE_REQ = 0x00000000,
8402VPG_MEM_FORCE_LIGHT_SLEEP_REQ = 0x00000001,
8403} VPG_MEM_PWR_FORCE_CTRL;
8404
8405/*******************************************************
8406 * AFMT Enums
8407 *******************************************************/
8408
8409/*
8410 * AFMT_ACP_TYPE enum
8411 */
8412
8413typedef enum AFMT_ACP_TYPE {
8414ACP_TYPE_GENERIC_AUDIO = 0x00000000,
8415ACP_TYPE_ICE60958_AUDIO = 0x00000001,
8416ACP_TYPE_DVD_AUDIO = 0x00000002,
8417ACP_TYPE_SUPER_AUDIO_CD = 0x00000003,
8418} AFMT_ACP_TYPE;
8419
8420/*
8421 * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
8422 */
8423
8424typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
8425AFMT_AUDIO_CRC_CH0_SIG = 0x00000000,
8426AFMT_AUDIO_CRC_CH1_SIG = 0x00000001,
8427AFMT_AUDIO_CRC_CH2_SIG = 0x00000002,
8428AFMT_AUDIO_CRC_CH3_SIG = 0x00000003,
8429AFMT_AUDIO_CRC_CH4_SIG = 0x00000004,
8430AFMT_AUDIO_CRC_CH5_SIG = 0x00000005,
8431AFMT_AUDIO_CRC_CH6_SIG = 0x00000006,
8432AFMT_AUDIO_CRC_CH7_SIG = 0x00000007,
8433AFMT_AUDIO_CRC_RESERVED_8 = 0x00000008,
8434AFMT_AUDIO_CRC_RESERVED_9 = 0x00000009,
8435AFMT_AUDIO_CRC_RESERVED_10 = 0x0000000a,
8436AFMT_AUDIO_CRC_RESERVED_11 = 0x0000000b,
8437AFMT_AUDIO_CRC_RESERVED_12 = 0x0000000c,
8438AFMT_AUDIO_CRC_RESERVED_13 = 0x0000000d,
8439AFMT_AUDIO_CRC_RESERVED_14 = 0x0000000e,
8440AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x0000000f,
8441} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
8442
8443/*
8444 * AFMT_AUDIO_CRC_CONTROL_CONT enum
8445 */
8446
8447typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
8448AFMT_AUDIO_CRC_ONESHOT = 0x00000000,
8449AFMT_AUDIO_CRC_AUTO_RESTART = 0x00000001,
8450} AFMT_AUDIO_CRC_CONTROL_CONT;
8451
8452/*
8453 * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
8454 */
8455
8456typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
8457AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x00000000,
8458AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x00000001,
8459} AFMT_AUDIO_CRC_CONTROL_SOURCE;
8460
8461/*
8462 * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
8463 */
8464
8465typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
8466AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000,
8467AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x00000001,
8468} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
8469
8470/*
8471 * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
8472 */
8473
8474typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
8475AFMT_AUDIO_PACKET_SENT_DISABLED = 0x00000000,
8476AFMT_AUDIO_PACKET_SENT_ENABLED = 0x00000001,
8477} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
8478
8479/*
8480 * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
8481 */
8482
8483typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
8484AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0x00000000,
8485AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x00000001,
8486} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
8487
8488/*
8489 * AFMT_AUDIO_SRC_CONTROL_SELECT enum
8490 */
8491
8492typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
8493AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x00000000,
8494AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x00000001,
8495AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x00000002,
8496AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x00000003,
8497AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x00000004,
8498AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x00000005,
8499} AFMT_AUDIO_SRC_CONTROL_SELECT;
8500
8501/*
8502 * AFMT_HDMI_AUDIO_SEND_MAX_PACKETS enum
8503 */
8504
8505typedef enum AFMT_HDMI_AUDIO_SEND_MAX_PACKETS {
8506HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x00000000,
8507HDMI_SEND_MAX_AUDIO_PACKETS = 0x00000001,
8508} AFMT_HDMI_AUDIO_SEND_MAX_PACKETS;
8509
8510/*
8511 * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
8512 */
8513
8514typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
8515AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x00000000,
8516AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x00000001,
8517} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
8518
8519/*
8520 * AFMT_INTERRUPT_STATUS_CHG_MASK enum
8521 */
8522
8523typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
8524AFMT_INTERRUPT_DISABLE = 0x00000000,
8525AFMT_INTERRUPT_ENABLE = 0x00000001,
8526} AFMT_INTERRUPT_STATUS_CHG_MASK;
8527
8528/*
8529 * AFMT_MEM_PWR_DIS_CTRL enum
8530 */
8531
8532typedef enum AFMT_MEM_PWR_DIS_CTRL {
8533AFMT_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
8534AFMT_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
8535} AFMT_MEM_PWR_DIS_CTRL;
8536
8537/*
8538 * AFMT_MEM_PWR_FORCE_CTRL enum
8539 */
8540
8541typedef enum AFMT_MEM_PWR_FORCE_CTRL {
8542AFMT_MEM_NO_FORCE_REQUEST = 0x00000000,
8543AFMT_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
8544AFMT_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
8545AFMT_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
8546} AFMT_MEM_PWR_FORCE_CTRL;
8547
8548/*
8549 * AFMT_RAMP_CONTROL0_SIGN enum
8550 */
8551
8552typedef enum AFMT_RAMP_CONTROL0_SIGN {
8553AFMT_RAMP_SIGNED = 0x00000000,
8554AFMT_RAMP_UNSIGNED = 0x00000001,
8555} AFMT_RAMP_CONTROL0_SIGN;
8556
8557/*
8558 * AFMT_VBI_PACKET_CONTROL_ACP_SOURCE enum
8559 */
8560
8561typedef enum AFMT_VBI_PACKET_CONTROL_ACP_SOURCE {
8562AFMT_ACP_SOURCE_FROM_AZALIA = 0x00000000,
8563AFMT_ACP_SOURCE_FROM_AFMT_REGISTERS = 0x00000001,
8564} AFMT_VBI_PACKET_CONTROL_ACP_SOURCE;
8565
8566/*
8567 * AUDIO_LAYOUT_SELECT enum
8568 */
8569
8570typedef enum AUDIO_LAYOUT_SELECT {
8571AUDIO_LAYOUT_0 = 0x00000000,
8572AUDIO_LAYOUT_1 = 0x00000001,
8573} AUDIO_LAYOUT_SELECT;
8574
8575/*******************************************************
8576 * HPO_TOP Enums
8577 *******************************************************/
8578
8579/*
8580 * HPO_TOP_CLOCK_GATING_DISABLE enum
8581 */
8582
8583typedef enum HPO_TOP_CLOCK_GATING_DISABLE {
8584HPO_TOP_CLOCK_GATING_EN = 0x00000000,
8585HPO_TOP_CLOCK_GATING_DIS = 0x00000001,
8586} HPO_TOP_CLOCK_GATING_DISABLE;
8587
8588/*
8589 * HPO_TOP_TEST_CLK_SEL enum
8590 */
8591
8592typedef enum HPO_TOP_TEST_CLK_SEL {
8593HPO_TOP_PERMANENT_DISPCLK = 0x00000000,
8594HPO_TOP_REGISTER_GATED_DISPCLK = 0x00000001,
8595HPO_TOP_PERMANENT_SOCCLK = 0x00000002,
8596HPO_TOP_TEST_CLOCK_RESERVED = 0x00000003,
8597HPO_TOP_PERMANENT_HDMISTREAMCLK0 = 0x00000004,
8598HPO_TOP_FEATURE_GATED_HDMISTREAMCLK0 = 0x00000005,
8599HPO_TOP_REGISTER_GATED_HDMISTREAMCLK0 = 0x00000006,
8600HPO_TOP_FEATURE_GATED_DISPCLK_IN_HDMISTREAMENC0 = 0x00000007,
8601HPO_TOP_FEATURE_GATED_SOCCLK_IN_HDMISTREAMENC0 = 0x00000008,
8602HPO_TOP_PERMANENT_HDMICHARCLK0 = 0x00000009,
8603HPO_TOP_FEATURE_GATED_HDMICHARCLK0 = 0x0000000a,
8604HPO_TOP_REGISTER_GATED_HDMICHARCLK0 = 0x0000000b,
8605} HPO_TOP_TEST_CLK_SEL;
8606
8607/*******************************************************
8608 * DP_STREAM_MAPPER Enums
8609 *******************************************************/
8610
8611/*
8612 * DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET enum
8613 */
8614
8615typedef enum DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET {
8616DP_STREAM_MAPPER_LINK0 = 0x00000000,
8617DP_STREAM_MAPPER_LINK1 = 0x00000001,
8618DP_STREAM_MAPPER_RESERVED = 0x00000002,
8619} DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET;
8620
8621/*******************************************************
8622 * HDMI_STREAM_ENC Enums
8623 *******************************************************/
8624
8625/*
8626 * HDMI_STREAM_ENC_DB_DISABLE_CONTROL enum
8627 */
8628
8629typedef enum HDMI_STREAM_ENC_DB_DISABLE_CONTROL {
8630HDMI_STREAM_ENC_DB_ENABLE = 0x00000000,
8631HDMI_STREAM_ENC_DB_DISABLE = 0x00000001,
8632} HDMI_STREAM_ENC_DB_DISABLE_CONTROL;
8633
8634/*
8635 * HDMI_STREAM_ENC_DSC_MODE enum
8636 */
8637
8638typedef enum HDMI_STREAM_ENC_DSC_MODE {
8639STREAM_DSC_DISABLE = 0x00000000,
8640STREAM_DSC_444_RGB = 0x00000001,
8641STREAM_DSC_NATIVE_422_420 = 0x00000002,
8642} HDMI_STREAM_ENC_DSC_MODE;
8643
8644/*
8645 * HDMI_STREAM_ENC_ENABLE_CONTROL enum
8646 */
8647
8648typedef enum HDMI_STREAM_ENC_ENABLE_CONTROL {
8649HDMI_STREAM_ENC_DISABLE = 0x00000000,
8650HDMI_STREAM_ENC_ENABLE = 0x00000001,
8651} HDMI_STREAM_ENC_ENABLE_CONTROL;
8652
8653/*
8654 * HDMI_STREAM_ENC_ODM_COMBINE_MODE enum
8655 */
8656
8657typedef enum HDMI_STREAM_ENC_ODM_COMBINE_MODE {
8658STREAM_ODM_COMBINE_1_SEGMENT = 0x00000000,
8659STREAM_ODM_COMBINE_2_SEGMENT = 0x00000001,
8660STREAM_ODM_COMBINE_RESERVED = 0x00000002,
8661STREAM_ODM_COMBINE_4_SEGMENT = 0x00000003,
8662} HDMI_STREAM_ENC_ODM_COMBINE_MODE;
8663
8664/*
8665 * HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum
8666 */
8667
8668typedef enum HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR {
8669HDMI_STREAM_ENC_NO_ERROR_OCCURRED = 0x00000000,
8670HDMI_STREAM_ENC_UNDERFLOW_OCCURRED = 0x00000001,
8671HDMI_STREAM_ENC_OVERFLOW_OCCURRED = 0x00000002,
8672} HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR;
8673
8674/*
8675 * HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum
8676 */
8677
8678typedef enum HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT {
8679HDMI_STREAM_ENC_HARDWARE = 0x00000000,
8680HDMI_STREAM_ENC_PROGRAMMABLE = 0x00000001,
8681} HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT;
8682
8683/*
8684 * HDMI_STREAM_ENC_PIXEL_ENCODING enum
8685 */
8686
8687typedef enum HDMI_STREAM_ENC_PIXEL_ENCODING {
8688STREAM_PIXEL_ENCODING_444_RGB = 0x00000000,
8689STREAM_PIXEL_ENCODING_422 = 0x00000001,
8690STREAM_PIXEL_ENCODING_420 = 0x00000002,
8691} HDMI_STREAM_ENC_PIXEL_ENCODING;
8692
8693/*
8694 * HDMI_STREAM_ENC_READ_CLOCK_CONTROL enum
8695 */
8696
8697typedef enum HDMI_STREAM_ENC_READ_CLOCK_CONTROL {
8698HDMI_STREAM_ENC_DCCG = 0x00000000,
8699HDMI_STREAM_ENC_DISPLAY_PIPE = 0x00000001,
8700} HDMI_STREAM_ENC_READ_CLOCK_CONTROL;
8701
8702/*
8703 * HDMI_STREAM_ENC_RESET_CONTROL enum
8704 */
8705
8706typedef enum HDMI_STREAM_ENC_RESET_CONTROL {
8707HDMI_STREAM_ENC_NOT_RESET = 0x00000000,
8708HDMI_STREAM_ENC_RESET = 0x00000001,
8709} HDMI_STREAM_ENC_RESET_CONTROL;
8710
8711/*
8712 * HDMI_STREAM_ENC_STREAM_ACTIVE enum
8713 */
8714
8715typedef enum HDMI_STREAM_ENC_STREAM_ACTIVE {
8716HDMI_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0x00000000,
8717HDMI_STREAM_ENC_VIDEO_STREAM_ACTIVE = 0x00000001,
8718} HDMI_STREAM_ENC_STREAM_ACTIVE;
8719
8720/*******************************************************
8721 * HDMI_TB_ENC Enums
8722 *******************************************************/
8723
8724/*
8725 * BORROWBUFFER_MEM_POWER_STATE_ENUM enum
8726 */
8727
8728typedef enum BORROWBUFFER_MEM_POWER_STATE_ENUM {
8729BORROWBUFFER_MEM_POWER_STATE_ENUM_ON = 0x00000000,
8730BORROWBUFFER_MEM_POWER_STATE_ENUM_LS = 0x00000001,
8731BORROWBUFFER_MEM_POWER_STATE_ENUM_DS = 0x00000002,
8732BORROWBUFFER_MEM_POWER_STATE_ENUM_SD = 0x00000003,
8733} BORROWBUFFER_MEM_POWER_STATE_ENUM;
8734
8735/*
8736 * HDMI_BORROW_MODE enum
8737 */
8738
8739typedef enum HDMI_BORROW_MODE {
8740TB_BORROW_MODE_NONE = 0x00000000,
8741TB_BORROW_MODE_ACTIVE = 0x00000001,
8742TB_BORROW_MODE_BLANK = 0x00000002,
8743TB_BORROW_MODE_RESERVED = 0x00000003,
8744} HDMI_BORROW_MODE;
8745
8746/*
8747 * HDMI_TB_ENC_ACP_SEND enum
8748 */
8749
8750typedef enum HDMI_TB_ENC_ACP_SEND {
8751TB_ACP_NOT_SEND = 0x00000000,
8752TB_ACP_PKT_SEND = 0x00000001,
8753} HDMI_TB_ENC_ACP_SEND;
8754
8755/*
8756 * HDMI_TB_ENC_ACR_AUDIO_PRIORITY enum
8757 */
8758
8759typedef enum HDMI_TB_ENC_ACR_AUDIO_PRIORITY {
8760TB_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000,
8761TB_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001,
8762} HDMI_TB_ENC_ACR_AUDIO_PRIORITY;
8763
8764/*
8765 * HDMI_TB_ENC_ACR_CONT enum
8766 */
8767
8768typedef enum HDMI_TB_ENC_ACR_CONT {
8769TB_ACR_CONT_DISABLE = 0x00000000,
8770TB_ACR_CONT_ENABLE = 0x00000001,
8771} HDMI_TB_ENC_ACR_CONT;
8772
8773/*
8774 * HDMI_TB_ENC_ACR_N_MULTIPLE enum
8775 */
8776
8777typedef enum HDMI_TB_ENC_ACR_N_MULTIPLE {
8778TB_ACR_0_MULTIPLE_RESERVED = 0x00000000,
8779TB_ACR_1_MULTIPLE = 0x00000001,
8780TB_ACR_2_MULTIPLE = 0x00000002,
8781TB_ACR_3_MULTIPLE_RESERVED = 0x00000003,
8782TB_ACR_4_MULTIPLE = 0x00000004,
8783TB_ACR_5_MULTIPLE_RESERVED = 0x00000005,
8784TB_ACR_6_MULTIPLE_RESERVED = 0x00000006,
8785TB_ACR_7_MULTIPLE_RESERVED = 0x00000007,
8786} HDMI_TB_ENC_ACR_N_MULTIPLE;
8787
8788/*
8789 * HDMI_TB_ENC_ACR_SELECT enum
8790 */
8791
8792typedef enum HDMI_TB_ENC_ACR_SELECT {
8793TB_ACR_SELECT_HW = 0x00000000,
8794TB_ACR_SELECT_32K = 0x00000001,
8795TB_ACR_SELECT_44K = 0x00000002,
8796TB_ACR_SELECT_48K = 0x00000003,
8797} HDMI_TB_ENC_ACR_SELECT;
8798
8799/*
8800 * HDMI_TB_ENC_ACR_SEND enum
8801 */
8802
8803typedef enum HDMI_TB_ENC_ACR_SEND {
8804TB_ACR_NOT_SEND = 0x00000000,
8805TB_ACR_PKT_SEND = 0x00000001,
8806} HDMI_TB_ENC_ACR_SEND;
8807
8808/*
8809 * HDMI_TB_ENC_ACR_SOURCE enum
8810 */
8811
8812typedef enum HDMI_TB_ENC_ACR_SOURCE {
8813TB_ACR_SOURCE_HW = 0x00000000,
8814TB_ACR_SOURCE_SW = 0x00000001,
8815} HDMI_TB_ENC_ACR_SOURCE;
8816
8817/*
8818 * HDMI_TB_ENC_AUDIO_INFO_CONT enum
8819 */
8820
8821typedef enum HDMI_TB_ENC_AUDIO_INFO_CONT {
8822TB_AUDIO_INFO_CONT_DISABLE = 0x00000000,
8823TB_AUDIO_INFO_CONT_ENABLE = 0x00000001,
8824} HDMI_TB_ENC_AUDIO_INFO_CONT;
8825
8826/*
8827 * HDMI_TB_ENC_AUDIO_INFO_SEND enum
8828 */
8829
8830typedef enum HDMI_TB_ENC_AUDIO_INFO_SEND {
8831TB_AUDIO_INFO_NOT_SEND = 0x00000000,
8832TB_AUDIO_INFO_PKT_SEND = 0x00000001,
8833} HDMI_TB_ENC_AUDIO_INFO_SEND;
8834
8835/*
8836 * HDMI_TB_ENC_CRC_SRC_SEL enum
8837 */
8838
8839typedef enum HDMI_TB_ENC_CRC_SRC_SEL {
8840TB_CRC_TB_ENC_INPUT = 0x00000000,
8841TB_CRC_DSC_PACKER = 0x00000001,
8842TB_CRC_DEEP_COLOR_PACKER = 0x00000002,
8843TB_CRC_ENCRYPTOR_INPUT = 0x00000003,
8844} HDMI_TB_ENC_CRC_SRC_SEL;
8845
8846/*
8847 * HDMI_TB_ENC_CRC_TYPE enum
8848 */
8849
8850typedef enum HDMI_TB_ENC_CRC_TYPE {
8851TB_CRC_ALL_TRIBYTES = 0x00000000,
8852TB_CRC_ACTIVE_TRIBYTES = 0x00000001,
8853TB_CRC_DATAISLAND_TRIBYTES = 0x00000002,
8854TB_CRC_ACTIVE_AND_DATAISLAND_TRIBYTES = 0x00000003,
8855} HDMI_TB_ENC_CRC_TYPE;
8856
8857/*
8858 * HDMI_TB_ENC_DEEP_COLOR_DEPTH enum
8859 */
8860
8861typedef enum HDMI_TB_ENC_DEEP_COLOR_DEPTH {
8862TB_DEEP_COLOR_DEPTH_24BPP = 0x00000000,
8863TB_DEEP_COLOR_DEPTH_30BPP = 0x00000001,
8864TB_DEEP_COLOR_DEPTH_36BPP = 0x00000002,
8865TB_DEEP_COLOR_DEPTH_RESERVED = 0x00000003,
8866} HDMI_TB_ENC_DEEP_COLOR_DEPTH;
8867
8868/*
8869 * HDMI_TB_ENC_DEFAULT_PAHSE enum
8870 */
8871
8872typedef enum HDMI_TB_ENC_DEFAULT_PAHSE {
8873TB_DEFAULT_PHASE_IS_0 = 0x00000000,
8874TB_DEFAULT_PHASE_IS_1 = 0x00000001,
8875} HDMI_TB_ENC_DEFAULT_PAHSE;
8876
8877/*
8878 * HDMI_TB_ENC_DSC_MODE enum
8879 */
8880
8881typedef enum HDMI_TB_ENC_DSC_MODE {
8882TB_DSC_DISABLE = 0x00000000,
8883TB_DSC_444_RGB = 0x00000001,
8884TB_DSC_NATIVE_422_420 = 0x00000002,
8885} HDMI_TB_ENC_DSC_MODE;
8886
8887/*
8888 * HDMI_TB_ENC_ENABLE enum
8889 */
8890
8891typedef enum HDMI_TB_ENC_ENABLE {
8892TB_DISABLE = 0x00000000,
8893TB_ENABLE = 0x00000001,
8894} HDMI_TB_ENC_ENABLE;
8895
8896/*
8897 * HDMI_TB_ENC_GC_AVMUTE enum
8898 */
8899
8900typedef enum HDMI_TB_ENC_GC_AVMUTE {
8901TB_GC_AVMUTE_SET = 0x00000000,
8902TB_GC_AVMUTE_UNSET = 0x00000001,
8903} HDMI_TB_ENC_GC_AVMUTE;
8904
8905/*
8906 * HDMI_TB_ENC_GC_AVMUTE_CONT enum
8907 */
8908
8909typedef enum HDMI_TB_ENC_GC_AVMUTE_CONT {
8910TB_GC_AVMUTE_CONT_DISABLE = 0x00000000,
8911TB_GC_AVMUTE_CONT_ENABLE = 0x00000001,
8912} HDMI_TB_ENC_GC_AVMUTE_CONT;
8913
8914/*
8915 * HDMI_TB_ENC_GC_CONT enum
8916 */
8917
8918typedef enum HDMI_TB_ENC_GC_CONT {
8919TB_GC_CONT_DISABLE = 0x00000000,
8920TB_GC_CONT_ENABLE = 0x00000001,
8921} HDMI_TB_ENC_GC_CONT;
8922
8923/*
8924 * HDMI_TB_ENC_GC_SEND enum
8925 */
8926
8927typedef enum HDMI_TB_ENC_GC_SEND {
8928TB_GC_NOT_SEND = 0x00000000,
8929TB_GC_PKT_SEND = 0x00000001,
8930} HDMI_TB_ENC_GC_SEND;
8931
8932/*
8933 * HDMI_TB_ENC_GENERIC_CONT enum
8934 */
8935
8936typedef enum HDMI_TB_ENC_GENERIC_CONT {
8937TB_GENERIC_CONT_DISABLE = 0x00000000,
8938TB_GENERIC_CONT_ENABLE = 0x00000001,
8939} HDMI_TB_ENC_GENERIC_CONT;
8940
8941/*
8942 * HDMI_TB_ENC_GENERIC_LOCK_EN enum
8943 */
8944
8945typedef enum HDMI_TB_ENC_GENERIC_LOCK_EN {
8946HDMI_TB_ENC_GENERIC_LOCK_DISABLE = 0x00000000,
8947HDMI_TB_ENC_GENERIC_LOCK_ENABLE = 0x00000001,
8948} HDMI_TB_ENC_GENERIC_LOCK_EN;
8949
8950/*
8951 * HDMI_TB_ENC_GENERIC_SEND enum
8952 */
8953
8954typedef enum HDMI_TB_ENC_GENERIC_SEND {
8955TB_GENERIC_NOT_SEND = 0x00000000,
8956TB_GENERIC_PKT_SEND = 0x00000001,
8957} HDMI_TB_ENC_GENERIC_SEND;
8958
8959/*
8960 * HDMI_TB_ENC_ISRC_CONT enum
8961 */
8962
8963typedef enum HDMI_TB_ENC_ISRC_CONT {
8964TB_ISRC_CONT_DISABLE = 0x00000000,
8965TB_ISRC_CONT_ENABLE = 0x00000001,
8966} HDMI_TB_ENC_ISRC_CONT;
8967
8968/*
8969 * HDMI_TB_ENC_ISRC_SEND enum
8970 */
8971
8972typedef enum HDMI_TB_ENC_ISRC_SEND {
8973TB_ISRC_NOT_SEND = 0x00000000,
8974TB_ISRC_PKT_SEND = 0x00000001,
8975} HDMI_TB_ENC_ISRC_SEND;
8976
8977/*
8978 * HDMI_TB_ENC_METADATA_ENABLE enum
8979 */
8980
8981typedef enum HDMI_TB_ENC_METADATA_ENABLE {
8982TB_METADATA_NOT_SEND = 0x00000000,
8983TB_METADATA_PKT_SEND = 0x00000001,
8984} HDMI_TB_ENC_METADATA_ENABLE;
8985
8986/*
8987 * HDMI_TB_ENC_PACKET_LINE_REFERENCE enum
8988 */
8989
8990typedef enum HDMI_TB_ENC_PACKET_LINE_REFERENCE {
8991TB_PKT_LINE_REF_END_OF_ACTIVE = 0x00000000,
8992TB_PKT_LINE_REF_OTGSOF = 0x00000001,
8993} HDMI_TB_ENC_PACKET_LINE_REFERENCE;
8994
8995/*
8996 * HDMI_TB_ENC_PIXEL_ENCODING enum
8997 */
8998
8999typedef enum HDMI_TB_ENC_PIXEL_ENCODING {
9000TB_PIXEL_ENCODING_444_RGB = 0x00000000,
9001TB_PIXEL_ENCODING_422 = 0x00000001,
9002TB_PIXEL_ENCODING_420 = 0x00000002,
9003} HDMI_TB_ENC_PIXEL_ENCODING;
9004
9005/*
9006 * HDMI_TB_ENC_RESET enum
9007 */
9008
9009typedef enum HDMI_TB_ENC_RESET {
9010TB_NOT_RESET = 0x00000000,
9011TB_RESET = 0x00000001,
9012} HDMI_TB_ENC_RESET;
9013
9014/*
9015 * HDMI_TB_ENC_SYNC_PHASE enum
9016 */
9017
9018typedef enum HDMI_TB_ENC_SYNC_PHASE {
9019TB_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000,
9020TB_SYNC_PHASE_ON_FRAME_START = 0x00000001,
9021} HDMI_TB_ENC_SYNC_PHASE;
9022
9023/*
9024 * INPUT_FIFO_ERROR_TYPE enum
9025 */
9026
9027typedef enum INPUT_FIFO_ERROR_TYPE {
9028TB_NO_ERROR_OCCURRED = 0x00000000,
9029TB_OVERFLOW_OCCURRED = 0x00000001,
9030} INPUT_FIFO_ERROR_TYPE;
9031
9032/*******************************************************
9033 * DP_STREAM_ENC Enums
9034 *******************************************************/
9035
9036/*
9037 * DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum
9038 */
9039
9040typedef enum DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR {
9041DP_STREAM_ENC_NO_ERROR_OCCURRED = 0x00000000,
9042DP_STREAM_ENC_UNDERFLOW_OCCURRED = 0x00000001,
9043DP_STREAM_ENC_OVERFLOW_OCCURRED = 0x00000002,
9044} DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR;
9045
9046/*
9047 * DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum
9048 */
9049
9050typedef enum DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT {
9051DP_STREAM_ENC_HARDWARE = 0x00000000,
9052DP_STREAM_ENC_PROGRAMMABLE = 0x00000001,
9053} DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT;
9054
9055/*
9056 * DP_STREAM_ENC_READ_CLOCK_CONTROL enum
9057 */
9058
9059typedef enum DP_STREAM_ENC_READ_CLOCK_CONTROL {
9060DP_STREAM_ENC_DCCG = 0x00000000,
9061DP_STREAM_ENC_DISPLAY_PIPE = 0x00000001,
9062} DP_STREAM_ENC_READ_CLOCK_CONTROL;
9063
9064/*
9065 * DP_STREAM_ENC_RESET_CONTROL enum
9066 */
9067
9068typedef enum DP_STREAM_ENC_RESET_CONTROL {
9069DP_STREAM_ENC_NOT_RESET = 0x00000000,
9070DP_STREAM_ENC_RESET = 0x00000001,
9071} DP_STREAM_ENC_RESET_CONTROL;
9072
9073/*
9074 * DP_STREAM_ENC_STREAM_ACTIVE enum
9075 */
9076
9077typedef enum DP_STREAM_ENC_STREAM_ACTIVE {
9078DP_STREAM_ENC_VIDEO_STREAM_NOT_ACTIVE = 0x00000000,
9079DP_STREAM_ENC_VIDEO_STREAM_ACTIVE = 0x00000001,
9080} DP_STREAM_ENC_STREAM_ACTIVE;
9081
9082/*******************************************************
9083 * DP_SYM32_ENC Enums
9084 *******************************************************/
9085
9086/*
9087 * ENUM_DP_SYM32_ENC_AUDIO_MUTE enum
9088 */
9089
9090typedef enum ENUM_DP_SYM32_ENC_AUDIO_MUTE {
9091DP_SYM32_ENC_SDP_AUDIO_MUTE_NOT_FORCED = 0x00000000,
9092DP_SYM32_ENC_SDP_AUDIO_MUTE_FORCED = 0x00000001,
9093} ENUM_DP_SYM32_ENC_AUDIO_MUTE;
9094
9095/*
9096 * ENUM_DP_SYM32_ENC_CONTINUOUS_MODE enum
9097 */
9098
9099typedef enum ENUM_DP_SYM32_ENC_CONTINUOUS_MODE {
9100DP_SYM32_ENC_ONE_SHOT_MODE = 0x00000000,
9101DP_SYM32_ENC_CONTINUOUS_MODE = 0x00000001,
9102} ENUM_DP_SYM32_ENC_CONTINUOUS_MODE;
9103
9104/*
9105 * ENUM_DP_SYM32_ENC_CRC_VALID enum
9106 */
9107
9108typedef enum ENUM_DP_SYM32_ENC_CRC_VALID {
9109DP_SYM32_ENC_CRC_NOT_VALID = 0x00000000,
9110DP_SYM32_ENC_CRC_VALID = 0x00000001,
9111} ENUM_DP_SYM32_ENC_CRC_VALID;
9112
9113/*
9114 * ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH enum
9115 */
9116
9117typedef enum ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH {
9118DP_SYM32_ENC_COMPONENT_DEPTH_6BPC = 0x00000000,
9119DP_SYM32_ENC_COMPONENT_DEPTH_8BPC = 0x00000001,
9120DP_SYM32_ENC_COMPONENT_DEPTH_10BPC = 0x00000002,
9121DP_SYM32_ENC_COMPONENT_DEPTH_12BPC = 0x00000003,
9122} ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH;
9123
9124/*
9125 * ENUM_DP_SYM32_ENC_ENABLE enum
9126 */
9127
9128typedef enum ENUM_DP_SYM32_ENC_ENABLE {
9129DP_SYM32_ENC_DISABLE = 0x00000000,
9130DP_SYM32_ENC_ENABLE = 0x00000001,
9131} ENUM_DP_SYM32_ENC_ENABLE;
9132
9133/*
9134 * ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED enum
9135 */
9136
9137typedef enum ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED {
9138DP_SYM32_ENC_GSP_DEADLINE_NOT_MISSED = 0x00000000,
9139DP_SYM32_ENC_GSP_DEADLINE_MISSED = 0x00000001,
9140} ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED;
9141
9142/*
9143 * ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION enum
9144 */
9145
9146typedef enum ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION {
9147DP_SYM32_ENC_GSP_SEND_AT_LINE_NUMBER = 0x00000000,
9148DP_SYM32_ENC_GSP_SEND_AT_EARLIEST_TIME = 0x00000001,
9149} ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION;
9150
9151/*
9152 * ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE enum
9153 */
9154
9155typedef enum ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE {
9156DP_SYM32_ENC_GSP_PAYLOAD_SIZE_32 = 0x00000000,
9157DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED0 = 0x00000001,
9158DP_SYM32_ENC_GSP_PAYLOAD_SIZE_RESERVED1 = 0x00000002,
9159DP_SYM32_ENC_GSP_PAYLOAD_SIZE_128 = 0x00000003,
9160} ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE;
9161
9162/*
9163 * ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING enum
9164 */
9165
9166typedef enum ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING {
9167DP_SYM32_ENC_GSP_TRIGGER_NOT_PENDING = 0x00000000,
9168DP_SYM32_ENC_GSP_TRIGGER_PENDING = 0x00000001,
9169} ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING;
9170
9171/*
9172 * ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM enum
9173 */
9174
9175typedef enum ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM {
9176DP_SYM32_ENC_MEM_PWR_NO_FORCE_REQUEST = 0x00000000,
9177DP_SYM32_ENC_MEM_PWR_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
9178DP_SYM32_ENC_MEM_PWR_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
9179DP_SYM32_ENC_MEM_PWR_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
9180} ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM;
9181
9182/*
9183 * ENUM_DP_SYM32_ENC_OVERFLOW_STATUS enum
9184 */
9185
9186typedef enum ENUM_DP_SYM32_ENC_OVERFLOW_STATUS {
9187DP_SYM32_ENC_NO_OVERFLOW_OCCURRED = 0x00000000,
9188DP_SYM32_ENC_OVERFLOW_OCCURRED = 0x00000001,
9189} ENUM_DP_SYM32_ENC_OVERFLOW_STATUS;
9190
9191/*
9192 * ENUM_DP_SYM32_ENC_PENDING enum
9193 */
9194
9195typedef enum ENUM_DP_SYM32_ENC_PENDING {
9196DP_SYM32_ENC_NOT_PENDING = 0x00000000,
9197DP_SYM32_ENC_PENDING = 0x00000001,
9198} ENUM_DP_SYM32_ENC_PENDING;
9199
9200/*
9201 * ENUM_DP_SYM32_ENC_PIXEL_ENCODING enum
9202 */
9203
9204typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING {
9205DP_SYM32_ENC_PIXEL_ENCODING_RGB_YCBCR444 = 0x00000000,
9206DP_SYM32_ENC_PIXEL_ENCODING_YCBCR422 = 0x00000001,
9207DP_SYM32_ENC_PIXEL_ENCODING_YCBCR420 = 0x00000002,
9208DP_SYM32_ENC_PIXEL_ENCODING_Y_ONLY = 0x00000003,
9209} ENUM_DP_SYM32_ENC_PIXEL_ENCODING;
9210
9211/*
9212 * ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE enum
9213 */
9214
9215typedef enum ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE {
9216DP_SYM32_ENC_UNCOMPRESSED_FORMAT = 0x00000000,
9217DP_SYM32_ENC_COMPRESSED_FORMAT = 0x00000001,
9218} ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE;
9219
9220/*
9221 * ENUM_DP_SYM32_ENC_POWER_STATE_ENUM enum
9222 */
9223
9224typedef enum ENUM_DP_SYM32_ENC_POWER_STATE_ENUM {
9225DP_SYM32_ENC_POWER_STATE_ENUM_ON = 0x00000000,
9226DP_SYM32_ENC_POWER_STATE_ENUM_LS = 0x00000001,
9227DP_SYM32_ENC_POWER_STATE_ENUM_DS = 0x00000002,
9228DP_SYM32_ENC_POWER_STATE_ENUM_SD = 0x00000003,
9229} ENUM_DP_SYM32_ENC_POWER_STATE_ENUM;
9230
9231/*
9232 * ENUM_DP_SYM32_ENC_RESET enum
9233 */
9234
9235typedef enum ENUM_DP_SYM32_ENC_RESET {
9236DP_SYM32_ENC_NOT_RESET = 0x00000000,
9237DP_SYM32_ENC_RESET = 0x00000001,
9238} ENUM_DP_SYM32_ENC_RESET;
9239
9240/*
9241 * ENUM_DP_SYM32_ENC_SDP_PRIORITY enum
9242 */
9243
9244typedef enum ENUM_DP_SYM32_ENC_SDP_PRIORITY {
9245DP_SYM32_ENC_SDP_LOW_PRIORITY = 0x00000000,
9246DP_SYM32_ENC_SDP_HIGH_PRIORITY = 0x00000001,
9247} ENUM_DP_SYM32_ENC_SDP_PRIORITY;
9248
9249/*
9250 * ENUM_DP_SYM32_ENC_SOF_REFERENCE enum
9251 */
9252
9253typedef enum ENUM_DP_SYM32_ENC_SOF_REFERENCE {
9254DP_SYM32_ENC_DP_SOF = 0x00000000,
9255DP_SYM32_ENC_OTG_SOF = 0x00000001,
9256} ENUM_DP_SYM32_ENC_SOF_REFERENCE;
9257
9258/*
9259 * ENUM_DP_SYM32_ENC_VID_STREAM_DEFER enum
9260 */
9261
9262typedef enum ENUM_DP_SYM32_ENC_VID_STREAM_DEFER {
9263DP_SYM32_ENC_VID_STREAM_NO_DEFER = 0x00000000,
9264DP_SYM32_ENC_VID_STREAM_DEFER_TO_HBLANK = 0x00000001,
9265DP_SYM32_ENC_VID_STREAM_DEFER_TO_VBLANK = 0x00000002,
9266} ENUM_DP_SYM32_ENC_VID_STREAM_DEFER;
9267
9268/*******************************************************
9269 * DP_DPHY_SYM32 Enums
9270 *******************************************************/
9271
9272/*
9273 * ENUM_DP_DPHY_SYM32_CRC_END_EVENT enum
9274 */
9275
9276typedef enum ENUM_DP_DPHY_SYM32_CRC_END_EVENT {
9277DP_DPHY_SYM32_CRC_END_LLCP = 0x00000000,
9278DP_DPHY_SYM32_CRC_END_PS_ONLY = 0x00000001,
9279DP_DPHY_SYM32_CRC_END_PS_LT_SR = 0x00000002,
9280DP_DPHY_SYM32_CRC_END_PS_ANY = 0x00000003,
9281} ENUM_DP_DPHY_SYM32_CRC_END_EVENT;
9282
9283/*
9284 * ENUM_DP_DPHY_SYM32_CRC_START_EVENT enum
9285 */
9286
9287typedef enum ENUM_DP_DPHY_SYM32_CRC_START_EVENT {
9288DP_DPHY_SYM32_CRC_START_LLCP = 0x00000000,
9289DP_DPHY_SYM32_CRC_START_PS_ONLY = 0x00000001,
9290DP_DPHY_SYM32_CRC_START_PS_LT_SR = 0x00000002,
9291DP_DPHY_SYM32_CRC_START_PS_POST_LT_SR = 0x00000003,
9292DP_DPHY_SYM32_CRC_START_TP_START = 0x00000004,
9293} ENUM_DP_DPHY_SYM32_CRC_START_EVENT;
9294
9295/*
9296 * ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE enum
9297 */
9298
9299typedef enum ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE {
9300DP_DPHY_SYM32_CRC_TAP_SOURCE_SCHEDULER = 0x00000000,
9301DP_DPHY_SYM32_CRC_TAP_SOURCE_SYMBOL_HANDLER = 0x00000001,
9302DP_DPHY_SYM32_CRC_TAP_SOURCE_TP_GEN_MUX = 0x00000002,
9303} ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE;
9304
9305/*
9306 * ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS enum
9307 */
9308
9309typedef enum ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS {
9310DP_DPHY_SYM32_CRC_USE_END_EVENT = 0x00000000,
9311DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS = 0x00000001,
9312} ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS;
9313
9314/*
9315 * ENUM_DP_DPHY_SYM32_ENABLE enum
9316 */
9317
9318typedef enum ENUM_DP_DPHY_SYM32_ENABLE {
9319DP_DPHY_SYM32_DISABLE = 0x00000000,
9320DP_DPHY_SYM32_ENABLE = 0x00000001,
9321} ENUM_DP_DPHY_SYM32_ENABLE;
9322
9323/*
9324 * ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE enum
9325 */
9326
9327typedef enum ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE {
9328DP_DPHY_SYM32_ENCRYPT_TYPE0 = 0x00000000,
9329DP_DPHY_SYM32_ENCRYPT_TYPE1 = 0x00000001,
9330} ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE;
9331
9332/*
9333 * ENUM_DP_DPHY_SYM32_MODE enum
9334 */
9335
9336typedef enum ENUM_DP_DPHY_SYM32_MODE {
9337DP_DPHY_SYM32_LT_TPS1 = 0x00000000,
9338DP_DPHY_SYM32_LT_TPS2 = 0x00000001,
9339DP_DPHY_SYM32_ACTIVE = 0x00000002,
9340DP_DPHY_SYM32_TEST = 0x00000003,
9341} ENUM_DP_DPHY_SYM32_MODE;
9342
9343/*
9344 * ENUM_DP_DPHY_SYM32_NUM_LANES enum
9345 */
9346
9347typedef enum ENUM_DP_DPHY_SYM32_NUM_LANES {
9348DP_DPHY_SYM32_1LANE = 0x00000000,
9349DP_DPHY_SYM32_2LANE = 0x00000001,
9350DP_DPHY_SYM32_RESERVED = 0x00000002,
9351DP_DPHY_SYM32_4LANE = 0x00000003,
9352} ENUM_DP_DPHY_SYM32_NUM_LANES;
9353
9354/*
9355 * ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING enum
9356 */
9357
9358typedef enum ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING {
9359DP_DPHY_SYM32_NO_RATE_UPDATE_PENDING = 0x00000000,
9360DP_DPHY_SYM32_RATE_UPDATE_PENDING = 0x00000001,
9361} ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING;
9362
9363/*
9364 * ENUM_DP_DPHY_SYM32_RESET enum
9365 */
9366
9367typedef enum ENUM_DP_DPHY_SYM32_RESET {
9368DP_DPHY_SYM32_NOT_RESET = 0x00000000,
9369DP_DPHY_SYM32_RESET = 0x00000001,
9370} ENUM_DP_DPHY_SYM32_RESET;
9371
9372/*
9373 * ENUM_DP_DPHY_SYM32_RESET_STATUS enum
9374 */
9375
9376typedef enum ENUM_DP_DPHY_SYM32_RESET_STATUS {
9377DP_DPHY_SYM32_RESET_STATUS_DEASSERTED = 0x00000000,
9378DP_DPHY_SYM32_RESET_STATUS_ASSERTED = 0x00000001,
9379} ENUM_DP_DPHY_SYM32_RESET_STATUS;
9380
9381/*
9382 * ENUM_DP_DPHY_SYM32_SAT_UPDATE enum
9383 */
9384
9385typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE {
9386DP_DPHY_SYM32_SAT_NO_UPDATE = 0x00000000,
9387DP_DPHY_SYM32_SAT_TRIGGER_UPDATE = 0x00000001,
9388DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE = 0x00000002,
9389} ENUM_DP_DPHY_SYM32_SAT_UPDATE;
9390
9391/*
9392 * ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING enum
9393 */
9394
9395typedef enum ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING {
9396DP_DPHY_SYM32_SAT_NO_UPDATE_PENDING = 0x00000000,
9397DP_DPHY_SYM32_SAT_TRIGGER_UPDATE_PENDING = 0x00000001,
9398DP_DPHY_SYM32_SAT_NOTRIGGER_UPDATE_PENDING = 0x00000002,
9399} ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING;
9400
9401/*
9402 * ENUM_DP_DPHY_SYM32_STATUS enum
9403 */
9404
9405typedef enum ENUM_DP_DPHY_SYM32_STATUS {
9406DP_DPHY_SYM32_STATUS_IDLE = 0x00000000,
9407DP_DPHY_SYM32_STATUS_ENABLED = 0x00000001,
9408} ENUM_DP_DPHY_SYM32_STATUS;
9409
9410/*
9411 * ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE enum
9412 */
9413
9414typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE {
9415DP_DPHY_SYM32_STREAM_OVR_NONE = 0x00000000,
9416DP_DPHY_SYM32_STREAM_OVR_REPLACE = 0x00000001,
9417DP_DPHY_SYM32_STREAM_OVR_ALWAYS = 0x00000002,
9418} ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE;
9419
9420/*
9421 * ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE enum
9422 */
9423
9424typedef enum ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE {
9425DP_DPHY_SYM32_STREAM_OVR_TYPE_DATA = 0x00000000,
9426DP_DPHY_SYM32_STREAM_OVR_TYPE_CONTROL = 0x00000001,
9427} ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE;
9428
9429/*
9430 * ENUM_DP_DPHY_SYM32_TP_PRBS_SEL enum
9431 */
9432
9433typedef enum ENUM_DP_DPHY_SYM32_TP_PRBS_SEL {
9434DP_DPHY_SYM32_TP_PRBS_SEL_PRBS7 = 0x00000000,
9435DP_DPHY_SYM32_TP_PRBS_SEL_PRBS9 = 0x00000001,
9436DP_DPHY_SYM32_TP_PRBS_SEL_PRBS11 = 0x00000002,
9437DP_DPHY_SYM32_TP_PRBS_SEL_PRBS15 = 0x00000003,
9438DP_DPHY_SYM32_TP_PRBS_SEL_PRBS23 = 0x00000004,
9439DP_DPHY_SYM32_TP_PRBS_SEL_PRBS31 = 0x00000005,
9440} ENUM_DP_DPHY_SYM32_TP_PRBS_SEL;
9441
9442/*
9443 * ENUM_DP_DPHY_SYM32_TP_SELECT enum
9444 */
9445
9446typedef enum ENUM_DP_DPHY_SYM32_TP_SELECT {
9447DP_DPHY_SYM32_TP_SELECT_TPS1 = 0x00000000,
9448DP_DPHY_SYM32_TP_SELECT_TPS2 = 0x00000001,
9449DP_DPHY_SYM32_TP_SELECT_PRBS = 0x00000002,
9450DP_DPHY_SYM32_TP_SELECT_CUSTOM = 0x00000003,
9451DP_DPHY_SYM32_TP_SELECT_SQUARE = 0x00000004,
9452} ENUM_DP_DPHY_SYM32_TP_SELECT;
9453
9454/*******************************************************
9455 * APG Enums
9456 *******************************************************/
9457
9458/*
9459 * APG_AUDIO_CRC_CONTROL_CH_SEL enum
9460 */
9461
9462typedef enum APG_AUDIO_CRC_CONTROL_CH_SEL {
9463APG_AUDIO_CRC_CH0_SIG = 0x00000000,
9464APG_AUDIO_CRC_CH1_SIG = 0x00000001,
9465APG_AUDIO_CRC_CH2_SIG = 0x00000002,
9466APG_AUDIO_CRC_CH3_SIG = 0x00000003,
9467APG_AUDIO_CRC_CH4_SIG = 0x00000004,
9468APG_AUDIO_CRC_CH5_SIG = 0x00000005,
9469APG_AUDIO_CRC_CH6_SIG = 0x00000006,
9470APG_AUDIO_CRC_CH7_SIG = 0x00000007,
9471APG_AUDIO_CRC_RESERVED_8 = 0x00000008,
9472APG_AUDIO_CRC_RESERVED_9 = 0x00000009,
9473APG_AUDIO_CRC_RESERVED_10 = 0x0000000a,
9474APG_AUDIO_CRC_RESERVED_11 = 0x0000000b,
9475APG_AUDIO_CRC_RESERVED_12 = 0x0000000c,
9476APG_AUDIO_CRC_RESERVED_13 = 0x0000000d,
9477APG_AUDIO_CRC_RESERVED_14 = 0x0000000e,
9478APG_AUDIO_CRC_RESERVED_15 = 0x0000000f,
9479} APG_AUDIO_CRC_CONTROL_CH_SEL;
9480
9481/*
9482 * APG_AUDIO_CRC_CONTROL_CONT enum
9483 */
9484
9485typedef enum APG_AUDIO_CRC_CONTROL_CONT {
9486APG_AUDIO_CRC_ONESHOT = 0x00000000,
9487APG_AUDIO_CRC_CONTINUOUS = 0x00000001,
9488} APG_AUDIO_CRC_CONTROL_CONT;
9489
9490/*
9491 * APG_DBG_ACP_TYPE enum
9492 */
9493
9494typedef enum APG_DBG_ACP_TYPE {
9495APG_ACP_TYPE_GENERIC_AUDIO = 0x00000000,
9496APG_ACP_TYPE_ICE60958_AUDIO = 0x00000001,
9497APG_ACP_TYPE_DVD_AUDIO = 0x00000002,
9498APG_ACP_TYPE_SUPER_AUDIO_CD = 0x00000003,
9499} APG_DBG_ACP_TYPE;
9500
9501/*
9502 * APG_DBG_AUDIO_DTO_BASE enum
9503 */
9504
9505typedef enum APG_DBG_AUDIO_DTO_BASE {
9506BASE_RATE_48KHZ = 0x00000000,
9507BASE_RATE_44P1KHZ = 0x00000001,
9508} APG_DBG_AUDIO_DTO_BASE;
9509
9510/*
9511 * APG_DBG_AUDIO_DTO_DIV enum
9512 */
9513
9514typedef enum APG_DBG_AUDIO_DTO_DIV {
9515DIVISOR_BY1 = 0x00000000,
9516DIVISOR_BY2_RESERVED = 0x00000001,
9517DIVISOR_BY3 = 0x00000002,
9518DIVISOR_BY4_RESERVED = 0x00000003,
9519DIVISOR_BY5_RESERVED = 0x00000004,
9520DIVISOR_BY6_RESERVED = 0x00000005,
9521DIVISOR_BY7_RESERVED = 0x00000006,
9522DIVISOR_BY8_RESERVED = 0x00000007,
9523} APG_DBG_AUDIO_DTO_DIV;
9524
9525/*
9526 * APG_DBG_AUDIO_DTO_MULTI enum
9527 */
9528
9529typedef enum APG_DBG_AUDIO_DTO_MULTI {
9530MULTIPLE_BY1 = 0x00000000,
9531MULTIPLE_BY2 = 0x00000001,
9532MULTIPLE_BY3_RESERVED = 0x00000002,
9533MULTIPLE_BY4 = 0x00000003,
9534MULTIPLE_RESERVED = 0x00000004,
9535} APG_DBG_AUDIO_DTO_MULTI;
9536
9537/*
9538 * APG_DBG_MUX_SEL enum
9539 */
9540
9541typedef enum APG_DBG_MUX_SEL {
9542APG_FUNCTIONAL_MODE = 0x00000000,
9543APG_DEBUG_AUDIO_MODE = 0x00000001,
9544} APG_DBG_MUX_SEL;
9545
9546/*
9547 * APG_DP_ASP_CHANNEL_COUNT_OVERRIDE enum
9548 */
9549
9550typedef enum APG_DP_ASP_CHANNEL_COUNT_OVERRIDE {
9551APG_DP_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000,
9552APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001,
9553} APG_DP_ASP_CHANNEL_COUNT_OVERRIDE;
9554
9555/*
9556 * APG_MEM_POWER_STATE enum
9557 */
9558
9559typedef enum APG_MEM_POWER_STATE {
9560APG_MEM_POWER_STATE_ON = 0x00000000,
9561APG_MEM_POWER_STATE_LS = 0x00000001,
9562APG_MEM_POWER_STATE_DS = 0x00000002,
9563APG_MEM_POWER_STATE_SD = 0x00000003,
9564} APG_MEM_POWER_STATE;
9565
9566/*
9567 * APG_MEM_PWR_DIS_CTRL enum
9568 */
9569
9570typedef enum APG_MEM_PWR_DIS_CTRL {
9571APG_MEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
9572APG_MEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
9573} APG_MEM_PWR_DIS_CTRL;
9574
9575/*
9576 * APG_MEM_PWR_FORCE_CTRL enum
9577 */
9578
9579typedef enum APG_MEM_PWR_FORCE_CTRL {
9580APG_MEM_NO_FORCE_REQUEST = 0x00000000,
9581APG_MEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
9582APG_MEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
9583APG_MEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
9584} APG_MEM_PWR_FORCE_CTRL;
9585
9586/*
9587 * APG_PACKET_CONTROL_ACP_SOURCE enum
9588 */
9589
9590typedef enum APG_PACKET_CONTROL_ACP_SOURCE {
9591APG_ACP_SOURCE_NO_OVERRIDE = 0x00000000,
9592APG_ACP_OVERRIDE = 0x00000001,
9593} APG_PACKET_CONTROL_ACP_SOURCE;
9594
9595/*
9596 * APG_PACKET_CONTROL_AUDIO_INFO_SOURCE enum
9597 */
9598
9599typedef enum APG_PACKET_CONTROL_AUDIO_INFO_SOURCE {
9600APG_INFOFRAME_SOURCE_NO_OVERRIDE = 0x00000000,
9601APG_INFOFRAME_SOURCE_FROM_APG_REGISTERS = 0x00000001,
9602} APG_PACKET_CONTROL_AUDIO_INFO_SOURCE;
9603
9604/*
9605 * APG_RAMP_CONTROL_SIGN enum
9606 */
9607
9608typedef enum APG_RAMP_CONTROL_SIGN {
9609APG_RAMP_SIGNED = 0x00000000,
9610APG_RAMP_UNSIGNED = 0x00000001,
9611} APG_RAMP_CONTROL_SIGN;
9612
9613/*******************************************************
9614 * DCIO Enums
9615 *******************************************************/
9616
9617/*
9618 * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
9619 */
9620
9621typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
9622DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0x00000000,
9623DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 0x00000001,
9624DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 0x00000002,
9625DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 0x00000003,
9626DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 0x00000004,
9627DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 0x00000005,
9628} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
9629
9630/*
9631 * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
9632 */
9633
9634typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
9635DCIO_TEST_CLK_SEL_DISPCLK = 0x00000000,
9636DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x00000001,
9637DCIO_TEST_CLK_SEL_SOCCLK = 0x00000002,
9638} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
9639
9640/*
9641 * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
9642 */
9643
9644typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
9645DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x00000000,
9646DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x00000001,
9647} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
9648
9649/*
9650 * DCIO_DBG_ASYNC_4BIT_SEL enum
9651 */
9652
9653typedef enum DCIO_DBG_ASYNC_4BIT_SEL {
9654DCIO_DBG_ASYNC_4BIT_SEL_3TO0 = 0x00000000,
9655DCIO_DBG_ASYNC_4BIT_SEL_7TO4 = 0x00000001,
9656DCIO_DBG_ASYNC_4BIT_SEL_11TO8 = 0x00000002,
9657DCIO_DBG_ASYNC_4BIT_SEL_15TO12 = 0x00000003,
9658DCIO_DBG_ASYNC_4BIT_SEL_19TO16 = 0x00000004,
9659DCIO_DBG_ASYNC_4BIT_SEL_23TO20 = 0x00000005,
9660DCIO_DBG_ASYNC_4BIT_SEL_27TO24 = 0x00000006,
9661DCIO_DBG_ASYNC_4BIT_SEL_31TO28 = 0x00000007,
9662} DCIO_DBG_ASYNC_4BIT_SEL;
9663
9664/*
9665 * DCIO_DBG_ASYNC_BLOCK_SEL enum
9666 */
9667
9668typedef enum DCIO_DBG_ASYNC_BLOCK_SEL {
9669DCIO_DBG_ASYNC_BLOCK_SEL_OVERRIDE = 0x00000000,
9670DCIO_DBG_ASYNC_BLOCK_SEL_DCCG = 0x00000001,
9671DCIO_DBG_ASYNC_BLOCK_SEL_DCIO = 0x00000002,
9672DCIO_DBG_ASYNC_BLOCK_SEL_DIO = 0x00000003,
9673} DCIO_DBG_ASYNC_BLOCK_SEL;
9674
9675/*
9676 * DCIO_DCRXPHY_SOFT_RESET enum
9677 */
9678
9679typedef enum DCIO_DCRXPHY_SOFT_RESET {
9680DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x00000000,
9681DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x00000001,
9682} DCIO_DCRXPHY_SOFT_RESET;
9683
9684/*
9685 * DCIO_DC_GENERICA_SEL enum
9686 */
9687
9688typedef enum DCIO_DC_GENERICA_SEL {
9689DCIO_GENERICA_SEL_STEREOSYNC = 0x00000001,
9690DCIO_GENERICA_SEL_GENERICA_DCCG = 0x0000000a,
9691DCIO_GENERICA_SEL_SYNCEN = 0x0000000b,
9692} DCIO_DC_GENERICA_SEL;
9693
9694/*
9695 * DCIO_DC_GENERICB_SEL enum
9696 */
9697
9698typedef enum DCIO_DC_GENERICB_SEL {
9699DCIO_GENERICB_SEL_STEREOSYNC = 0x00000001,
9700DCIO_GENERICB_SEL_GENERICB_DCCG = 0x0000000a,
9701DCIO_GENERICB_SEL_SYNCEN = 0x0000000b,
9702} DCIO_DC_GENERICB_SEL;
9703
9704/*
9705 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
9706 */
9707
9708typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
9709DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x00000000,
9710DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x00000001,
9711DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x00000002,
9712DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x00000003,
9713DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x00000004,
9714DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x00000005,
9715DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x00000006,
9716} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
9717
9718/*
9719 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
9720 */
9721
9722typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
9723DCIO_UNIPHYA_FBDIV_CLK = 0x00000000,
9724DCIO_UNIPHYB_FBDIV_CLK = 0x00000001,
9725DCIO_UNIPHYC_FBDIV_CLK = 0x00000002,
9726DCIO_UNIPHYD_FBDIV_CLK = 0x00000003,
9727DCIO_UNIPHYE_FBDIV_CLK = 0x00000004,
9728DCIO_UNIPHYF_FBDIV_CLK = 0x00000005,
9729DCIO_UNIPHYG_FBDIV_CLK = 0x00000006,
9730} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
9731
9732/*
9733 * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
9734 */
9735
9736typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
9737DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x00000000,
9738DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x00000001,
9739DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x00000002,
9740DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x00000003,
9741DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x00000004,
9742DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x00000005,
9743DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x00000006,
9744} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
9745
9746/*
9747 * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
9748 */
9749
9750typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
9751DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x00000000,
9752DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x00000001,
9753DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x00000002,
9754DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x00000003,
9755DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x00000004,
9756DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x00000005,
9757DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x00000006,
9758} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
9759
9760/*
9761 * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum
9762 */
9763
9764typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
9765DCIO_DPRX_LOOPBACK_ENABLE_NORMAL = 0x00000000,
9766DCIO_DPRX_LOOPBACK_ENABLE_LOOP = 0x00000001,
9767} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
9768
9769/*
9770 * DCIO_DC_GPU_TIMER_READ_SELECT enum
9771 */
9772
9773typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
9774DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000,
9775DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001,
9776DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x00000002,
9777DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x00000003,
9778DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000004,
9779DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000005,
9780} DCIO_DC_GPU_TIMER_READ_SELECT;
9781
9782/*
9783 * DCIO_DC_GPU_TIMER_START_POSITION enum
9784 */
9785
9786typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
9787DCIO_GPU_TIMER_START_0_END_27 = 0x00000000,
9788DCIO_GPU_TIMER_START_1_END_28 = 0x00000001,
9789DCIO_GPU_TIMER_START_2_END_29 = 0x00000002,
9790DCIO_GPU_TIMER_START_3_END_30 = 0x00000003,
9791DCIO_GPU_TIMER_START_4_END_31 = 0x00000004,
9792DCIO_GPU_TIMER_START_6_END_33 = 0x00000005,
9793DCIO_GPU_TIMER_START_8_END_35 = 0x00000006,
9794DCIO_GPU_TIMER_START_10_END_37 = 0x00000007,
9795} DCIO_DC_GPU_TIMER_START_POSITION;
9796
9797/*
9798 * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
9799 */
9800
9801typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
9802DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x00000000,
9803DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x00000001,
9804DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x00000002,
9805DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003,
9806} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
9807
9808/*
9809 * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
9810 */
9811
9812typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
9813DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x00000000,
9814DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x00000001,
9815DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x00000002,
9816DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x00000003,
9817} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
9818
9819/*
9820 * DCIO_DIO_EXT_VSYNC_MASK enum
9821 */
9822
9823typedef enum DCIO_DIO_EXT_VSYNC_MASK {
9824DCIO_EXT_VSYNC_MASK_NONE = 0x00000000,
9825DCIO_EXT_VSYNC_MASK_PIPE0 = 0x00000001,
9826DCIO_EXT_VSYNC_MASK_PIPE1 = 0x00000002,
9827DCIO_EXT_VSYNC_MASK_PIPE2 = 0x00000003,
9828DCIO_EXT_VSYNC_MASK_PIPE3 = 0x00000004,
9829DCIO_EXT_VSYNC_MASK_PIPE4 = 0x00000005,
9830DCIO_EXT_VSYNC_MASK_PIPE5 = 0x00000006,
9831DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x00000007,
9832} DCIO_DIO_EXT_VSYNC_MASK;
9833
9834/*
9835 * DCIO_DIO_OTG_EXT_VSYNC_MUX enum
9836 */
9837
9838typedef enum DCIO_DIO_OTG_EXT_VSYNC_MUX {
9839DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x00000000,
9840DCIO_EXT_VSYNC_MUX_OTG0 = 0x00000001,
9841DCIO_EXT_VSYNC_MUX_OTG1 = 0x00000002,
9842DCIO_EXT_VSYNC_MUX_OTG2 = 0x00000003,
9843DCIO_EXT_VSYNC_MUX_OTG3 = 0x00000004,
9844DCIO_EXT_VSYNC_MUX_OTG4 = 0x00000005,
9845DCIO_EXT_VSYNC_MUX_OTG5 = 0x00000006,
9846DCIO_EXT_VSYNC_MUX_GENERICB = 0x00000007,
9847} DCIO_DIO_OTG_EXT_VSYNC_MUX;
9848
9849/*
9850 * DCIO_DPCS_INTERRUPT_MASK enum
9851 */
9852
9853typedef enum DCIO_DPCS_INTERRUPT_MASK {
9854DCIO_DPCS_INTERRUPT_DISABLE = 0x00000000,
9855DCIO_DPCS_INTERRUPT_ENABLE = 0x00000001,
9856} DCIO_DPCS_INTERRUPT_MASK;
9857
9858/*
9859 * DCIO_DPCS_INTERRUPT_TYPE enum
9860 */
9861
9862typedef enum DCIO_DPCS_INTERRUPT_TYPE {
9863DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
9864DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
9865} DCIO_DPCS_INTERRUPT_TYPE;
9866
9867/*
9868 * DCIO_DSYNC_SOFT_RESET enum
9869 */
9870
9871typedef enum DCIO_DSYNC_SOFT_RESET {
9872DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x00000000,
9873DCIO_DSYNC_SOFT_RESET_ASSERT = 0x00000001,
9874} DCIO_DSYNC_SOFT_RESET;
9875
9876/*
9877 * DCIO_GENLK_CLK_GSL_MASK enum
9878 */
9879
9880typedef enum DCIO_GENLK_CLK_GSL_MASK {
9881DCIO_GENLK_CLK_GSL_MASK_NO = 0x00000000,
9882DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x00000001,
9883DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x00000002,
9884} DCIO_GENLK_CLK_GSL_MASK;
9885
9886/*
9887 * DCIO_GENLK_VSYNC_GSL_MASK enum
9888 */
9889
9890typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
9891DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x00000000,
9892DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x00000001,
9893DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x00000002,
9894} DCIO_GENLK_VSYNC_GSL_MASK;
9895
9896/*
9897 * DCIO_GSL_SEL enum
9898 */
9899
9900typedef enum DCIO_GSL_SEL {
9901DCIO_GSL_SEL_GROUP_0 = 0x00000000,
9902DCIO_GSL_SEL_GROUP_1 = 0x00000001,
9903DCIO_GSL_SEL_GROUP_2 = 0x00000002,
9904} DCIO_GSL_SEL;
9905
9906/*
9907 * DCIO_PHY_HPO_ENC_SRC_SEL enum
9908 */
9909
9910typedef enum DCIO_PHY_HPO_ENC_SRC_SEL {
9911HPO_SRC0 = 0x00000000,
9912HPO_SRC_RESERVED = 0x00000001,
9913} DCIO_PHY_HPO_ENC_SRC_SEL;
9914
9915/*
9916 * DCIO_SWAPLOCK_A_GSL_MASK enum
9917 */
9918
9919typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
9920DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x00000000,
9921DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x00000001,
9922DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x00000002,
9923} DCIO_SWAPLOCK_A_GSL_MASK;
9924
9925/*
9926 * DCIO_SWAPLOCK_B_GSL_MASK enum
9927 */
9928
9929typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
9930DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x00000000,
9931DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x00000001,
9932DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x00000002,
9933} DCIO_SWAPLOCK_B_GSL_MASK;
9934
9935/*
9936 * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
9937 */
9938
9939typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
9940DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x00000000,
9941DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x00000001,
9942DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x00000002,
9943DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x00000003,
9944} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
9945
9946/*
9947 * DCIO_UNIPHY_IMPCAL_SEL enum
9948 */
9949
9950typedef enum DCIO_UNIPHY_IMPCAL_SEL {
9951DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x00000000,
9952DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x00000001,
9953} DCIO_UNIPHY_IMPCAL_SEL;
9954
9955/*
9956 * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
9957 */
9958
9959typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
9960DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x00000000,
9961DCIO_UNIPHY_CHANNEL_INVERTED = 0x00000001,
9962} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
9963
9964/*
9965 * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
9966 */
9967
9968typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
9969DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000,
9970DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x00000001,
9971DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002,
9972DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 0x00000003,
9973} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
9974
9975/*******************************************************
9976 * DCIO_CHIP Enums
9977 *******************************************************/
9978
9979/*
9980 * DCIOCHIP_AUX_ALL_PWR_OK enum
9981 */
9982
9983typedef enum DCIOCHIP_AUX_ALL_PWR_OK {
9984DCIOCHIP_AUX_ALL_PWR_OK_0 = 0x00000000,
9985DCIOCHIP_AUX_ALL_PWR_OK_1 = 0x00000001,
9986} DCIOCHIP_AUX_ALL_PWR_OK;
9987
9988/*
9989 * DCIOCHIP_AUX_CSEL0P9 enum
9990 */
9991
9992typedef enum DCIOCHIP_AUX_CSEL0P9 {
9993DCIOCHIP_AUX_CSEL_DEC1P0 = 0x00000000,
9994DCIOCHIP_AUX_CSEL_DEC0P9 = 0x00000001,
9995} DCIOCHIP_AUX_CSEL0P9;
9996
9997/*
9998 * DCIOCHIP_AUX_CSEL1P1 enum
9999 */
10000
10001typedef enum DCIOCHIP_AUX_CSEL1P1 {
10002DCIOCHIP_AUX_CSEL_INC1P0 = 0x00000000,
10003DCIOCHIP_AUX_CSEL_INC1P1 = 0x00000001,
10004} DCIOCHIP_AUX_CSEL1P1;
10005
10006/*
10007 * DCIOCHIP_AUX_FALLSLEWSEL enum
10008 */
10009
10010typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
10011DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x00000000,
10012DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x00000001,
10013DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x00000002,
10014DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x00000003,
10015} DCIOCHIP_AUX_FALLSLEWSEL;
10016
10017/*
10018 * DCIOCHIP_AUX_HYS_TUNE enum
10019 */
10020
10021typedef enum DCIOCHIP_AUX_HYS_TUNE {
10022DCIOCHIP_AUX_HYS_TUNE_0 = 0x00000000,
10023DCIOCHIP_AUX_HYS_TUNE_1 = 0x00000001,
10024DCIOCHIP_AUX_HYS_TUNE_2 = 0x00000002,
10025DCIOCHIP_AUX_HYS_TUNE_3 = 0x00000003,
10026} DCIOCHIP_AUX_HYS_TUNE;
10027
10028/*
10029 * DCIOCHIP_AUX_RECEIVER_SEL enum
10030 */
10031
10032typedef enum DCIOCHIP_AUX_RECEIVER_SEL {
10033DCIOCHIP_AUX_RECEIVER_SEL_0 = 0x00000000,
10034DCIOCHIP_AUX_RECEIVER_SEL_1 = 0x00000001,
10035DCIOCHIP_AUX_RECEIVER_SEL_2 = 0x00000002,
10036DCIOCHIP_AUX_RECEIVER_SEL_3 = 0x00000003,
10037} DCIOCHIP_AUX_RECEIVER_SEL;
10038
10039/*
10040 * DCIOCHIP_AUX_RSEL0P9 enum
10041 */
10042
10043typedef enum DCIOCHIP_AUX_RSEL0P9 {
10044DCIOCHIP_AUX_RSEL_DEC1P0 = 0x00000000,
10045DCIOCHIP_AUX_RSEL_DEC0P9 = 0x00000001,
10046} DCIOCHIP_AUX_RSEL0P9;
10047
10048/*
10049 * DCIOCHIP_AUX_RSEL1P1 enum
10050 */
10051
10052typedef enum DCIOCHIP_AUX_RSEL1P1 {
10053DCIOCHIP_AUX_RSEL_INC1P0 = 0x00000000,
10054DCIOCHIP_AUX_RSEL_INC1P1 = 0x00000001,
10055} DCIOCHIP_AUX_RSEL1P1;
10056
10057/*
10058 * DCIOCHIP_AUX_SPIKESEL enum
10059 */
10060
10061typedef enum DCIOCHIP_AUX_SPIKESEL {
10062DCIOCHIP_AUX_SPIKESEL_50NS = 0x00000000,
10063DCIOCHIP_AUX_SPIKESEL_10NS = 0x00000001,
10064} DCIOCHIP_AUX_SPIKESEL;
10065
10066/*
10067 * DCIOCHIP_AUX_VOD_TUNE enum
10068 */
10069
10070typedef enum DCIOCHIP_AUX_VOD_TUNE {
10071DCIOCHIP_AUX_VOD_TUNE_0 = 0x00000000,
10072DCIOCHIP_AUX_VOD_TUNE_1 = 0x00000001,
10073DCIOCHIP_AUX_VOD_TUNE_2 = 0x00000002,
10074DCIOCHIP_AUX_VOD_TUNE_3 = 0x00000003,
10075} DCIOCHIP_AUX_VOD_TUNE;
10076
10077/*
10078 * DCIOCHIP_GPIO_MASK_EN enum
10079 */
10080
10081typedef enum DCIOCHIP_GPIO_MASK_EN {
10082DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x00000000,
10083DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x00000001,
10084} DCIOCHIP_GPIO_MASK_EN;
10085
10086/*
10087 * DCIOCHIP_HPD_SEL enum
10088 */
10089
10090typedef enum DCIOCHIP_HPD_SEL {
10091DCIOCHIP_HPD_SEL_ASYNC = 0x00000000,
10092DCIOCHIP_HPD_SEL_CLOCKED = 0x00000001,
10093} DCIOCHIP_HPD_SEL;
10094
10095/*
10096 * DCIOCHIP_I2C_COMPSEL enum
10097 */
10098
10099typedef enum DCIOCHIP_I2C_COMPSEL {
10100DCIOCHIP_I2C_REC_SCHMIT = 0x00000000,
10101DCIOCHIP_I2C_REC_COMPARATOR = 0x00000001,
10102} DCIOCHIP_I2C_COMPSEL;
10103
10104/*
10105 * DCIOCHIP_I2C_FALLSLEWSEL enum
10106 */
10107
10108typedef enum DCIOCHIP_I2C_FALLSLEWSEL {
10109DCIOCHIP_I2C_FALLSLEWSEL_00 = 0x00000000,
10110DCIOCHIP_I2C_FALLSLEWSEL_01 = 0x00000001,
10111DCIOCHIP_I2C_FALLSLEWSEL_10 = 0x00000002,
10112DCIOCHIP_I2C_FALLSLEWSEL_11 = 0x00000003,
10113} DCIOCHIP_I2C_FALLSLEWSEL;
10114
10115/*
10116 * DCIOCHIP_I2C_RECEIVER_SEL enum
10117 */
10118
10119typedef enum DCIOCHIP_I2C_RECEIVER_SEL {
10120DCIOCHIP_I2C_RECEIVER_SEL_0 = 0x00000000,
10121DCIOCHIP_I2C_RECEIVER_SEL_1 = 0x00000001,
10122DCIOCHIP_I2C_RECEIVER_SEL_2 = 0x00000002,
10123DCIOCHIP_I2C_RECEIVER_SEL_3 = 0x00000003,
10124} DCIOCHIP_I2C_RECEIVER_SEL;
10125
10126/*
10127 * DCIOCHIP_I2C_VPH_1V2_EN enum
10128 */
10129
10130typedef enum DCIOCHIP_I2C_VPH_1V2_EN {
10131DCIOCHIP_I2C_VPH_1V2_EN_0 = 0x00000000,
10132DCIOCHIP_I2C_VPH_1V2_EN_1 = 0x00000001,
10133} DCIOCHIP_I2C_VPH_1V2_EN;
10134
10135/*
10136 * DCIOCHIP_INVERT enum
10137 */
10138
10139typedef enum DCIOCHIP_INVERT {
10140DCIOCHIP_POL_NON_INVERT = 0x00000000,
10141DCIOCHIP_POL_INVERT = 0x00000001,
10142} DCIOCHIP_INVERT;
10143
10144/*
10145 * DCIOCHIP_MASK enum
10146 */
10147
10148typedef enum DCIOCHIP_MASK {
10149DCIOCHIP_MASK_DISABLE = 0x00000000,
10150DCIOCHIP_MASK_ENABLE = 0x00000001,
10151} DCIOCHIP_MASK;
10152
10153/*
10154 * DCIOCHIP_PAD_MODE enum
10155 */
10156
10157typedef enum DCIOCHIP_PAD_MODE {
10158DCIOCHIP_PAD_MODE_DDC = 0x00000000,
10159DCIOCHIP_PAD_MODE_DP = 0x00000001,
10160} DCIOCHIP_PAD_MODE;
10161
10162/*
10163 * DCIOCHIP_PD_EN enum
10164 */
10165
10166typedef enum DCIOCHIP_PD_EN {
10167DCIOCHIP_PD_EN_NOTALLOW = 0x00000000,
10168DCIOCHIP_PD_EN_ALLOW = 0x00000001,
10169} DCIOCHIP_PD_EN;
10170
10171/*
10172 * DCIOCHIP_REF_27_SRC_SEL enum
10173 */
10174
10175typedef enum DCIOCHIP_REF_27_SRC_SEL {
10176DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x00000000,
10177DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001,
10178DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x00000002,
10179DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003,
10180} DCIOCHIP_REF_27_SRC_SEL;
10181
10182/*******************************************************
10183 * PWRSEQ Enums
10184 *******************************************************/
10185
10186/*
10187 * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
10188 */
10189
10190typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
10191PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x00000000,
10192PWRSEQ_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x00000001,
10193} PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
10194
10195/*
10196 * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN enum
10197 */
10198
10199typedef enum PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN {
10200PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_NORMAL = 0x00000000,
10201PWRSEQ_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_PWM = 0x00000001,
10202} PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN;
10203
10204/*
10205 * PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum
10206 */
10207
10208typedef enum PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
10209PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL = 0x00000000,
10210PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1 = 0x00000001,
10211PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2 = 0x00000002,
10212PWRSEQ_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3 = 0x00000003,
10213} PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
10214
10215/*
10216 * PWRSEQ_BL_PWM_CNTL_BL_PWM_EN enum
10217 */
10218
10219typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_EN {
10220PWRSEQ_BL_PWM_DISABLE = 0x00000000,
10221PWRSEQ_BL_PWM_ENABLE = 0x00000001,
10222} PWRSEQ_BL_PWM_CNTL_BL_PWM_EN;
10223
10224/*
10225 * PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
10226 */
10227
10228typedef enum PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
10229PWRSEQ_BL_PWM_FRACTIONAL_DISABLE = 0x00000000,
10230PWRSEQ_BL_PWM_FRACTIONAL_ENABLE = 0x00000001,
10231} PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
10232
10233/*
10234 * PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
10235 */
10236
10237typedef enum PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
10238PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000,
10239PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001,
10240} PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
10241
10242/*
10243 * PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
10244 */
10245
10246typedef enum PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
10247PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000,
10248PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 0x00000001,
10249} PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
10250
10251/*
10252 * PWRSEQ_BL_PWM_GRP1_REG_LOCK enum
10253 */
10254
10255typedef enum PWRSEQ_BL_PWM_GRP1_REG_LOCK {
10256PWRSEQ_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x00000000,
10257PWRSEQ_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x00000001,
10258} PWRSEQ_BL_PWM_GRP1_REG_LOCK;
10259
10260/*
10261 * PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
10262 */
10263
10264typedef enum PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
10265PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000,
10266PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001,
10267} PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
10268
10269/*
10270 * PWRSEQ_GPIO_MASK_EN enum
10271 */
10272
10273typedef enum PWRSEQ_GPIO_MASK_EN {
10274PWRSEQ_GPIO_MASK_EN_HARDWARE = 0x00000000,
10275PWRSEQ_GPIO_MASK_EN_SOFTWARE = 0x00000001,
10276} PWRSEQ_GPIO_MASK_EN;
10277
10278/*
10279 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON enum
10280 */
10281
10282typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON {
10283PWRSEQ_PANEL_BLON_OFF = 0x00000000,
10284PWRSEQ_PANEL_BLON_ON = 0x00000001,
10285} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON;
10286
10287/*
10288 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL enum
10289 */
10290
10291typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL {
10292PWRSEQ_PANEL_BLON_POL_NON_INVERT = 0x00000000,
10293PWRSEQ_PANEL_BLON_POL_INVERT = 0x00000001,
10294} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL;
10295
10296/*
10297 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON enum
10298 */
10299
10300typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON {
10301PWRSEQ_PANEL_DIGON_OFF = 0x00000000,
10302PWRSEQ_PANEL_DIGON_ON = 0x00000001,
10303} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON;
10304
10305/*
10306 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL enum
10307 */
10308
10309typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL {
10310PWRSEQ_PANEL_DIGON_POL_NON_INVERT = 0x00000000,
10311PWRSEQ_PANEL_DIGON_POL_INVERT = 0x00000001,
10312} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL;
10313
10314/*
10315 * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL enum
10316 */
10317
10318typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL {
10319PWRSEQ_PANEL_SYNCEN_POL_NON_INVERT = 0x00000000,
10320PWRSEQ_PANEL_SYNCEN_POL_INVERT = 0x00000001,
10321} PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL;
10322
10323/*
10324 * PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE enum
10325 */
10326
10327typedef enum PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE {
10328PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_OFF = 0x00000000,
10329PWRSEQ_PANEL_PWRSEQ_TARGET_STATE_LCD_ON = 0x00000001,
10330} PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE;
10331
10332/*
10333 * PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN enum
10334 */
10335
10336typedef enum PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN {
10337PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_BLON = 0x00000000,
10338PWRSEQ_PANEL_VARY_BL_OVERRIDE_EN_SEPARATE = 0x00000001,
10339} PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN;
10340
10341/*******************************************************
10342 * AZCONTROLLER Enums
10343 *******************************************************/
10344
10345/*
10346 * AZ_CORB_SIZE enum
10347 */
10348
10349typedef enum AZ_CORB_SIZE {
10350AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x00000000,
10351AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x00000001,
10352AZ_CORB_SIZE_256ENTRIES = 0x00000002,
10353AZ_CORB_SIZE_RESERVED = 0x00000003,
10354} AZ_CORB_SIZE;
10355
10356/*
10357 * AZ_GLOBAL_CAPABILITIES enum
10358 */
10359
10360typedef enum AZ_GLOBAL_CAPABILITIES {
10361AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0x00000000,
10362AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 0x00000001,
10363} AZ_GLOBAL_CAPABILITIES;
10364
10365/*
10366 * AZ_RIRB_SIZE enum
10367 */
10368
10369typedef enum AZ_RIRB_SIZE {
10370AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x00000000,
10371AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x00000001,
10372AZ_RIRB_SIZE_256ENTRIES = 0x00000002,
10373AZ_RIRB_SIZE_UNDEFINED = 0x00000003,
10374} AZ_RIRB_SIZE;
10375
10376/*
10377 * AZ_RIRB_WRITE_POINTER_RESET enum
10378 */
10379
10380typedef enum AZ_RIRB_WRITE_POINTER_RESET {
10381AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x00000000,
10382AZ_RIRB_WRITE_POINTER_DO_RESET = 0x00000001,
10383} AZ_RIRB_WRITE_POINTER_RESET;
10384
10385/*
10386 * AZ_STATE_CHANGE_STATUS enum
10387 */
10388
10389typedef enum AZ_STATE_CHANGE_STATUS {
10390AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x00000000,
10391AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x00000001,
10392} AZ_STATE_CHANGE_STATUS;
10393
10394/*
10395 * CORB_READ_POINTER_RESET enum
10396 */
10397
10398typedef enum CORB_READ_POINTER_RESET {
10399CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x00000000,
10400CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x00000001,
10401} CORB_READ_POINTER_RESET;
10402
10403/*
10404 * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
10405 */
10406
10407typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
10408DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0x00000000,
10409DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 0x00000001,
10410} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
10411
10412/*
10413 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
10414 */
10415
10416typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
10417GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x00000000,
10418GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x00000001,
10419} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
10420
10421/*
10422 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
10423 */
10424
10425typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
10426GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x00000000,
10427GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x00000001,
10428} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
10429
10430/*
10431 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
10432 */
10433
10434typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
10435GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x00000000,
10436GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x00000001,
10437} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
10438
10439/*
10440 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
10441 */
10442
10443typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
10444GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0x00000000,
10445GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 0x00000001,
10446} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
10447
10448/*
10449 * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
10450 */
10451
10452typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
10453ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x00000000,
10454ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x00000001,
10455} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
10456
10457/*
10458 * GLOBAL_CONTROL_CONTROLLER_RESET enum
10459 */
10460
10461typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
10462CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x00000000,
10463CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x00000001,
10464} GLOBAL_CONTROL_CONTROLLER_RESET;
10465
10466/*
10467 * GLOBAL_CONTROL_FLUSH_CONTROL enum
10468 */
10469
10470typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
10471FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x00000000,
10472FLUSH_CONTROL_FLUSH_STARTED = 0x00000001,
10473} GLOBAL_CONTROL_FLUSH_CONTROL;
10474
10475/*
10476 * GLOBAL_STATUS_FLUSH_STATUS enum
10477 */
10478
10479typedef enum GLOBAL_STATUS_FLUSH_STATUS {
10480GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x00000000,
10481GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x00000001,
10482} GLOBAL_STATUS_FLUSH_STATUS;
10483
10484/*
10485 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
10486 */
10487
10488typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
10489IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0x00000000,
10490IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 0x00000001,
10491} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
10492
10493/*
10494 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
10495 */
10496
10497typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
10498IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0x00000000,
10499IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 0x00000001,
10500} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
10501
10502/*
10503 * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
10504 */
10505
10506typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
10507RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
10508RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
10509} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
10510
10511/*
10512 * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
10513 */
10514
10515typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
10516RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
10517RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
10518} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
10519
10520/*
10521 * STREAM_0_SYNCHRONIZATION enum
10522 */
10523
10524typedef enum STREAM_0_SYNCHRONIZATION {
10525STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10526STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10527} STREAM_0_SYNCHRONIZATION;
10528
10529/*
10530 * STREAM_10_SYNCHRONIZATION enum
10531 */
10532
10533typedef enum STREAM_10_SYNCHRONIZATION {
10534STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10535STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10536} STREAM_10_SYNCHRONIZATION;
10537
10538/*
10539 * STREAM_11_SYNCHRONIZATION enum
10540 */
10541
10542typedef enum STREAM_11_SYNCHRONIZATION {
10543STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10544STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10545} STREAM_11_SYNCHRONIZATION;
10546
10547/*
10548 * STREAM_12_SYNCHRONIZATION enum
10549 */
10550
10551typedef enum STREAM_12_SYNCHRONIZATION {
10552STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10553STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10554} STREAM_12_SYNCHRONIZATION;
10555
10556/*
10557 * STREAM_13_SYNCHRONIZATION enum
10558 */
10559
10560typedef enum STREAM_13_SYNCHRONIZATION {
10561STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10562STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10563} STREAM_13_SYNCHRONIZATION;
10564
10565/*
10566 * STREAM_14_SYNCHRONIZATION enum
10567 */
10568
10569typedef enum STREAM_14_SYNCHRONIZATION {
10570STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10571STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10572} STREAM_14_SYNCHRONIZATION;
10573
10574/*
10575 * STREAM_15_SYNCHRONIZATION enum
10576 */
10577
10578typedef enum STREAM_15_SYNCHRONIZATION {
10579STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10580STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10581} STREAM_15_SYNCHRONIZATION;
10582
10583/*
10584 * STREAM_1_SYNCHRONIZATION enum
10585 */
10586
10587typedef enum STREAM_1_SYNCHRONIZATION {
10588STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10589STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10590} STREAM_1_SYNCHRONIZATION;
10591
10592/*
10593 * STREAM_2_SYNCHRONIZATION enum
10594 */
10595
10596typedef enum STREAM_2_SYNCHRONIZATION {
10597STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10598STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10599} STREAM_2_SYNCHRONIZATION;
10600
10601/*
10602 * STREAM_3_SYNCHRONIZATION enum
10603 */
10604
10605typedef enum STREAM_3_SYNCHRONIZATION {
10606STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
10607STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
10608} STREAM_3_SYNCHRONIZATION;
10609
10610/*
10611 * STREAM_4_SYNCHRONIZATION enum
10612 */
10613
10614typedef enum STREAM_4_SYNCHRONIZATION {
10615STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10616STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10617} STREAM_4_SYNCHRONIZATION;
10618
10619/*
10620 * STREAM_5_SYNCHRONIZATION enum
10621 */
10622
10623typedef enum STREAM_5_SYNCHRONIZATION {
10624STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10625STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10626} STREAM_5_SYNCHRONIZATION;
10627
10628/*
10629 * STREAM_6_SYNCHRONIZATION enum
10630 */
10631
10632typedef enum STREAM_6_SYNCHRONIZATION {
10633STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10634STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10635} STREAM_6_SYNCHRONIZATION;
10636
10637/*
10638 * STREAM_7_SYNCHRONIZATION enum
10639 */
10640
10641typedef enum STREAM_7_SYNCHRONIZATION {
10642STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10643STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10644} STREAM_7_SYNCHRONIZATION;
10645
10646/*
10647 * STREAM_8_SYNCHRONIZATION enum
10648 */
10649
10650typedef enum STREAM_8_SYNCHRONIZATION {
10651STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10652STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10653} STREAM_8_SYNCHRONIZATION;
10654
10655/*
10656 * STREAM_9_SYNCHRONIZATION enum
10657 */
10658
10659typedef enum STREAM_9_SYNCHRONIZATION {
10660STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
10661STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
10662} STREAM_9_SYNCHRONIZATION;
10663
10664/*******************************************************
10665 * AZENDPOINT Enums
10666 *******************************************************/
10667
10668/*
10669 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
10670 */
10671
10672typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
10673AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
10674AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
10675AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
10676AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
10677AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
10678AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
10679} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
10680
10681/*
10682 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
10683 */
10684
10685typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
10686AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
10687AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
10688AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
10689AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
10690AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
10691AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
10692AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
10693AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
10694AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
10695} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
10696
10697/*
10698 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
10699 */
10700
10701typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
10702AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
10703AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
10704AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
10705AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
10706AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
10707AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
10708AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
10709AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
10710} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
10711
10712/*
10713 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
10714 */
10715
10716typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
10717AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
10718AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
10719AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
10720AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
10721AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
10722} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
10723
10724/*
10725 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
10726 */
10727
10728typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
10729AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
10730AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
10731} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
10732
10733/*
10734 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
10735 */
10736
10737typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
10738AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
10739AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
10740} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
10741
10742/*
10743 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
10744 */
10745
10746typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
10747AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0x00000000,
10748AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 0x00000001,
10749} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
10750
10751/*
10752 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
10753 */
10754
10755typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
10756AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0x00000000,
10757AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 0x00000001,
10758} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
10759
10760/*
10761 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
10762 */
10763
10764typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
10765AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
10766AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
10767} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
10768
10769/*
10770 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
10771 */
10772
10773typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
10774AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0x00000000,
10775AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 0x00000001,
10776} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
10777
10778/*
10779 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
10780 */
10781
10782typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
10783AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0x00000000,
10784AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 0x00000001,
10785} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
10786
10787/*
10788 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
10789 */
10790
10791typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
10792AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0x00000000,
10793AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 0x00000001,
10794} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
10795
10796/*
10797 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
10798 */
10799
10800typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
10801AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0x00000000,
10802AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 0x00000001,
10803} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
10804
10805/*
10806 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
10807 */
10808
10809typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
10810AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0x00000000,
10811AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 0x00000001,
10812} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
10813
10814/*
10815 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
10816 */
10817
10818typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
10819AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0x00000000,
10820AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 0x00000001,
10821} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
10822
10823/*
10824 * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum
10825 */
10826
10827typedef enum AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE {
10828AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0x00000000,
10829AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 0x00000001,
10830AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 0x00000002,
10831AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 0x00000003,
10832AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 0x00000004,
10833AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 0x00000005,
10834AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 0x00000006,
10835AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 0x00000007,
10836AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 0x00000008,
10837AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 0x00000009,
10838AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 0x0000000a,
10839AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 0x0000000b,
10840AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 0x0000000c,
10841AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 0x0000000d,
10842AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 0x0000000e,
10843AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 0x0000000f,
10844} AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE;
10845
10846/*
10847 * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
10848 */
10849
10850typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
10851AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0x00000000,
10852AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x00000001,
10853} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
10854
10855/*
10856 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
10857 */
10858
10859typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
10860AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0x00000000,
10861AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 0x00000001,
10862} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
10863
10864/*
10865 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
10866 */
10867
10868typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
10869AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
10870AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
10871} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
10872
10873/*
10874 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
10875 */
10876
10877typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
10878AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0x00000000,
10879AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 0x00000001,
10880} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
10881
10882/*
10883 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
10884 */
10885
10886typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
10887AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
10888AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
10889} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
10890
10891/*
10892 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
10893 */
10894
10895typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
10896AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0x00000000,
10897AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 0x00000001,
10898} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
10899
10900/*
10901 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
10902 */
10903
10904typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
10905AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
10906AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
10907} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
10908
10909/*
10910 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
10911 */
10912
10913typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
10914AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0x00000000,
10915AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 0x00000001,
10916} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
10917
10918/*
10919 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
10920 */
10921
10922typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
10923AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
10924AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
10925} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
10926
10927/*
10928 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10929 */
10930
10931typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10932AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
10933AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
10934} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
10935
10936/*
10937 * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
10938 */
10939
10940typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
10941AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
10942AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
10943} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
10944
10945/*
10946 * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
10947 */
10948
10949typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
10950AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0x00000000,
10951AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 0x00000001,
10952} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
10953
10954/*******************************************************
10955 * AZF0CONTROLLER Enums
10956 *******************************************************/
10957
10958/*
10959 * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
10960 */
10961
10962typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
10963AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0x00000000,
10964AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 0x00000001,
10965} AZALIA_SOFT_RESET_REFCLK_SOFT_RESET;
10966
10967/*
10968 * MEM_PWR_DIS_CTRL enum
10969 */
10970
10971typedef enum MEM_PWR_DIS_CTRL {
10972ENABLE_MEM_PWR_CTRL = 0x00000000,
10973DISABLE_MEM_PWR_CTRL = 0x00000001,
10974} MEM_PWR_DIS_CTRL;
10975
10976/*
10977 * MEM_PWR_FORCE_CTRL enum
10978 */
10979
10980typedef enum MEM_PWR_FORCE_CTRL {
10981NO_FORCE_REQUEST = 0x00000000,
10982FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
10983FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
10984FORCE_SHUT_DOWN_REQUEST = 0x00000003,
10985} MEM_PWR_FORCE_CTRL;
10986
10987/*
10988 * MEM_PWR_FORCE_CTRL2 enum
10989 */
10990
10991typedef enum MEM_PWR_FORCE_CTRL2 {
10992NO_FORCE_REQ = 0x00000000,
10993FORCE_LIGHT_SLEEP_REQ = 0x00000001,
10994} MEM_PWR_FORCE_CTRL2;
10995
10996/*
10997 * MEM_PWR_SEL_CTRL enum
10998 */
10999
11000typedef enum MEM_PWR_SEL_CTRL {
11001DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
11002DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001,
11003DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002,
11004} MEM_PWR_SEL_CTRL;
11005
11006/*
11007 * MEM_PWR_SEL_CTRL2 enum
11008 */
11009
11010typedef enum MEM_PWR_SEL_CTRL2 {
11011DYNAMIC_DEEP_SLEEP_EN = 0x00000000,
11012DYNAMIC_LIGHT_SLEEP_EN = 0x00000001,
11013} MEM_PWR_SEL_CTRL2;
11014
11015/*******************************************************
11016 * AZF0ROOT Enums
11017 *******************************************************/
11018
11019/*
11020 * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
11021 */
11022
11023typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
11024CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0x00000000,
11025CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 0x00000001,
11026CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 0x00000002,
11027CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 0x00000003,
11028CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 0x00000004,
11029CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 0x00000005,
11030CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 0x00000006,
11031CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 0x00000007,
11032} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
11033
11034/*
11035 * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
11036 */
11037
11038typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
11039CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0x00000000,
11040CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 0x00000001,
11041CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 0x00000002,
11042CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 0x00000003,
11043CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 0x00000004,
11044CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 0x00000005,
11045CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 0x00000006,
11046CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 0x00000007,
11047} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
11048
11049/*******************************************************
11050 * AZINPUTENDPOINT Enums
11051 *******************************************************/
11052
11053/*
11054 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
11055 */
11056
11057typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
11058AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
11059AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
11060AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
11061AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
11062AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
11063AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
11064} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
11065
11066/*
11067 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
11068 */
11069
11070typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
11071AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
11072AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
11073AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
11074AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
11075AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
11076AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
11077AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
11078AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
11079AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
11080} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
11081
11082/*
11083 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
11084 */
11085
11086typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
11087AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
11088AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
11089AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
11090AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
11091AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
11092AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
11093AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
11094AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
11095} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
11096
11097/*
11098 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
11099 */
11100
11101typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
11102AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
11103AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
11104AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
11105AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
11106AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
11107} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
11108
11109/*
11110 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
11111 */
11112
11113typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
11114AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
11115AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
11116} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
11117
11118/*
11119 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
11120 */
11121
11122typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
11123AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
11124AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
11125} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
11126
11127/*
11128 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
11129 */
11130
11131typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
11132AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
11133AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
11134} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
11135
11136/*
11137 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
11138 */
11139
11140typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
11141AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0x00000000,
11142AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 0x00000001,
11143} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
11144
11145/*
11146 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
11147 */
11148
11149typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
11150AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
11151AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
11152} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
11153
11154/*
11155 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
11156 */
11157
11158typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
11159AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0x00000000,
11160AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 0x00000001,
11161} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
11162
11163/*
11164 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
11165 */
11166
11167typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
11168AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
11169AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
11170} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
11171
11172/*
11173 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
11174 */
11175
11176typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
11177AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0x00000000,
11178AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 0x00000001,
11179} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
11180
11181/*
11182 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
11183 */
11184
11185typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
11186AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
11187AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
11188} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
11189
11190/*
11191 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
11192 */
11193
11194typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
11195AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0x00000000,
11196AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 0x00000001,
11197} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
11198
11199/*
11200 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
11201 */
11202
11203typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
11204AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
11205AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
11206} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
11207
11208/*
11209 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
11210 */
11211
11212typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
11213AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
11214AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
11215} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
11216
11217/*
11218 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
11219 */
11220
11221typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
11222AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0x00000000,
11223AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 0x00000001,
11224} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
11225
11226/*******************************************************
11227 * AZROOT Enums
11228 *******************************************************/
11229
11230/*
11231 * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
11232 */
11233
11234typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
11235AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0x00000000,
11236AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 0x00000001,
11237} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
11238
11239/*******************************************************
11240 * AZF0STREAM Enums
11241 *******************************************************/
11242
11243/*
11244 * AZ_LATENCY_COUNTER_CONTROL enum
11245 */
11246
11247typedef enum AZ_LATENCY_COUNTER_CONTROL {
11248AZ_LATENCY_COUNTER_NO_RESET = 0x00000000,
11249AZ_LATENCY_COUNTER_RESET_DONE = 0x00000001,
11250} AZ_LATENCY_COUNTER_CONTROL;
11251
11252/*******************************************************
11253 * AZSTREAM Enums
11254 *******************************************************/
11255
11256/*
11257 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
11258 */
11259
11260typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
11261OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000,
11262OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001,
11263} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
11264
11265/*
11266 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
11267 */
11268
11269typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
11270OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000,
11271OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001,
11272} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
11273
11274/*
11275 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
11276 */
11277
11278typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
11279OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000,
11280OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001,
11281} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
11282
11283/*
11284 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
11285 */
11286
11287typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
11288OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000,
11289OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001,
11290} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
11291
11292/*
11293 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
11294 */
11295
11296typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
11297OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000,
11298OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001,
11299} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
11300
11301/*
11302 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
11303 */
11304
11305typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
11306OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000,
11307OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001,
11308} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
11309
11310/*
11311 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
11312 */
11313
11314typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
11315OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000,
11316OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001,
11317} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
11318
11319/*
11320 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
11321 */
11322
11323typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
11324OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000,
11325OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001,
11326} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
11327
11328/*
11329 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
11330 */
11331
11332typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
11333OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000,
11334OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001,
11335} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
11336
11337/*
11338 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
11339 */
11340
11341typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
11342OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
11343OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
11344OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
11345OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
11346OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
11347OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
11348} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
11349
11350/*
11351 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
11352 */
11353
11354typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
11355OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
11356OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
11357OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
11358OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
11359OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
11360OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
11361OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
11362OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
11363OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008,
11364OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009,
11365OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a,
11366OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b,
11367OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c,
11368OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d,
11369OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e,
11370OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f,
11371} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
11372
11373/*
11374 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
11375 */
11376
11377typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
11378OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
11379OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
11380OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
11381OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
11382OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
11383OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
11384OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
11385OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
11386} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
11387
11388/*
11389 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
11390 */
11391
11392typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
11393OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
11394OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
11395OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
11396OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
11397OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
11398} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
11399
11400/*
11401 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
11402 */
11403
11404typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
11405OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
11406OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
11407} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
11408
11409/*******************************************************
11410 * AZF0ENDPOINT Enums
11411 *******************************************************/
11412
11413/*
11414 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11415 */
11416
11417typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
11418AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
11419AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
11420} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
11421
11422/*
11423 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
11424 */
11425
11426typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
11427AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
11428AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
11429} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
11430
11431/*
11432 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11433 */
11434
11435typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11436AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
11437AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
11438} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
11439
11440/*
11441 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11442 */
11443
11444typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11445AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
11446AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
11447} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
11448
11449/*
11450 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
11451 */
11452
11453typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
11454AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
11455AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 0x00000001,
11456} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
11457
11458/*
11459 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11460 */
11461
11462typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11463AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
11464AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
11465} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
11466
11467/*
11468 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11469 */
11470
11471typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11472AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
11473AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
11474} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
11475
11476/*
11477 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11478 */
11479
11480typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
11481AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
11482AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
11483} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
11484
11485/*
11486 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11487 */
11488
11489typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11490AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
11491AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
11492} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
11493
11494/*
11495 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11496 */
11497
11498typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11499AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
11500AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
11501} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
11502
11503/*
11504 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11505 */
11506
11507typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11508AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
11509AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
11510} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
11511
11512/*
11513 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11514 */
11515
11516typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11517AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
11518AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
11519AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
11520AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
11521AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
11522AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
11523AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
11524AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
11525AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
11526AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
11527} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
11528
11529/*
11530 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11531 */
11532
11533typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
11534AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
11535AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
11536} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
11537
11538/*
11539 * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
11540 */
11541
11542typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
11543AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
11544AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
11545} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
11546
11547/*
11548 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
11549 */
11550
11551typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
11552AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0x00000000,
11553AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 0x00000001,
11554} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
11555
11556/*
11557 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11558 */
11559
11560typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
11561AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
11562AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
11563} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
11564
11565/*
11566 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11567 */
11568
11569typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11570AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
11571AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
11572} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
11573
11574/*
11575 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11576 */
11577
11578typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11579AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
11580AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
11581} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
11582
11583/*
11584 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11585 */
11586
11587typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11588AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0x00000000,
11589AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
11590} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
11591
11592/*
11593 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11594 */
11595
11596typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11597AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
11598AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
11599} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
11600
11601/*
11602 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11603 */
11604
11605typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
11606AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
11607AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
11608} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
11609
11610/*
11611 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11612 */
11613
11614typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11615AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
11616AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
11617} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
11618
11619/*
11620 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11621 */
11622
11623typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11624AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
11625AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
11626} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
11627
11628/*
11629 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11630 */
11631
11632typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11633AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
11634AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
11635} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
11636
11637/*
11638 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11639 */
11640
11641typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11642AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
11643AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
11644AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
11645AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
11646AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
11647AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
11648AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
11649AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
11650AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
11651AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
11652} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
11653
11654/*
11655 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11656 */
11657
11658typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
11659AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
11660AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
11661} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
11662
11663/*
11664 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
11665 */
11666
11667typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
11668AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0x00000000,
11669AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
11670} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
11671
11672/*
11673 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
11674 */
11675
11676typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
11677AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0x00000000,
11678AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 0x00000001,
11679} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
11680
11681/*
11682 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
11683 */
11684
11685typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
11686AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
11687AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
11688} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
11689
11690/*
11691 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
11692 */
11693
11694typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
11695AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
11696AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
11697} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
11698
11699/*
11700 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
11701 */
11702
11703typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
11704AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
11705AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
11706} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
11707
11708/*
11709 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
11710 */
11711
11712typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
11713AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0x00000000,
11714AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 0x00000001,
11715} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
11716
11717/*
11718 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
11719 */
11720
11721typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
11722AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
11723AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
11724} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
11725
11726/*
11727 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
11728 */
11729
11730typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
11731AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
11732AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
11733} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
11734
11735/*******************************************************
11736 * AZF0INPUTENDPOINT Enums
11737 *******************************************************/
11738
11739/*
11740 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11741 */
11742
11743typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
11744AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
11745AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 0x00000001,
11746} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
11747
11748/*
11749 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
11750 */
11751
11752typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
11753AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
11754AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
11755} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
11756
11757/*
11758 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11759 */
11760
11761typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11762AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
11763AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
11764} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
11765
11766/*
11767 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11768 */
11769
11770typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11771AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0x00000000,
11772AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 0x00000001,
11773} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
11774
11775/*
11776 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
11777 */
11778
11779typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
11780AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
11781AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 0x00000001,
11782} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
11783
11784/*
11785 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11786 */
11787
11788typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11789AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
11790AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
11791} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
11792
11793/*
11794 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11795 */
11796
11797typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11798AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
11799AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
11800} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
11801
11802/*
11803 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11804 */
11805
11806typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
11807AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
11808AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
11809} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
11810
11811/*
11812 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11813 */
11814
11815typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11816AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
11817AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
11818} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
11819
11820/*
11821 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11822 */
11823
11824typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11825AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0x00000000,
11826AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
11827} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
11828
11829/*
11830 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11831 */
11832
11833typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11834AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0x00000000,
11835AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
11836} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
11837
11838/*
11839 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11840 */
11841
11842typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11843AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
11844AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
11845AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
11846AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
11847AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
11848AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
11849AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
11850AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
11851AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
11852AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
11853} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
11854
11855/*
11856 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11857 */
11858
11859typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
11860AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
11861AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
11862} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
11863
11864/*
11865 * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
11866 */
11867
11868typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
11869AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0x00000000,
11870AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 0x00000001,
11871} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
11872
11873/*
11874 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
11875 */
11876
11877typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
11878AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
11879AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
11880} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
11881
11882/*
11883 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
11884 */
11885
11886typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
11887AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
11888AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
11889} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
11890
11891/*
11892 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
11893 */
11894
11895typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
11896AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
11897AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
11898} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
11899
11900/*
11901 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
11902 */
11903
11904typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
11905AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
11906AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
11907} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
11908
11909/*
11910 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
11911 */
11912
11913typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
11914AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0x00000000,
11915AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 0x00000001,
11916} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
11917
11918/*
11919 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
11920 */
11921
11922typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
11923AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
11924AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
11925} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
11926
11927/*
11928 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
11929 */
11930
11931typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
11932AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
11933AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
11934} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
11935
11936/*
11937 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
11938 */
11939
11940typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
11941AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0x00000000,
11942AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 0x00000001,
11943} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
11944
11945/*
11946 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
11947 */
11948
11949typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
11950AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
11951AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
11952} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
11953
11954/*
11955 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
11956 */
11957
11958typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
11959AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
11960AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
11961AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
11962AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
11963AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
11964AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
11965AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
11966AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
11967AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
11968AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
11969} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
11970
11971/*
11972 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
11973 */
11974
11975typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
11976AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
11977AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
11978} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
11979
11980/*
11981 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
11982 */
11983
11984typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
11985AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0x00000000,
11986AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
11987} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
11988
11989/*
11990 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
11991 */
11992
11993typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
11994AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0x00000000,
11995AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 0x00000001,
11996} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
11997
11998/*
11999 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
12000 */
12001
12002typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
12003AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0x00000000,
12004AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 0x00000001,
12005} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
12006
12007/*
12008 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
12009 */
12010
12011typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
12012AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0x00000000,
12013AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 0x00000001,
12014} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
12015
12016/*
12017 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
12018 */
12019
12020typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
12021AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
12022AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
12023} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
12024
12025/*
12026 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
12027 */
12028
12029typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
12030AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
12031AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
12032} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
12033
12034/*
12035 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
12036 */
12037
12038typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
12039AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
12040AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
12041} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
12042
12043/*
12044 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
12045 */
12046
12047typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
12048AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000000,
12049AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000001,
12050} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
12051
12052/*
12053 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
12054 */
12055
12056typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
12057AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
12058AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
12059} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
12060
12061/*
12062 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
12063 */
12064
12065typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
12066AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
12067AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
12068} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
12069
12070/*******************************************************
12071 * DSCC Enums
12072 *******************************************************/
12073
12074/*
12075 * DSCC_BITS_PER_COMPONENT_ENUM enum
12076 */
12077
12078typedef enum DSCC_BITS_PER_COMPONENT_ENUM {
12079DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008,
12080DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a,
12081DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c,
12082} DSCC_BITS_PER_COMPONENT_ENUM;
12083
12084/*
12085 * DSCC_DSC_VERSION_MAJOR_ENUM enum
12086 */
12087
12088typedef enum DSCC_DSC_VERSION_MAJOR_ENUM {
12089DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 0x00000001,
12090} DSCC_DSC_VERSION_MAJOR_ENUM;
12091
12092/*
12093 * DSCC_DSC_VERSION_MINOR_ENUM enum
12094 */
12095
12096typedef enum DSCC_DSC_VERSION_MINOR_ENUM {
12097DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 0x00000001,
12098DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 0x00000002,
12099} DSCC_DSC_VERSION_MINOR_ENUM;
12100
12101/*
12102 * DSCC_ENABLE_ENUM enum
12103 */
12104
12105typedef enum DSCC_ENABLE_ENUM {
12106DSCC_ENABLE_ENUM_DISABLED = 0x00000000,
12107DSCC_ENABLE_ENUM_ENABLED = 0x00000001,
12108} DSCC_ENABLE_ENUM;
12109
12110/*
12111 * DSCC_ICH_RESET_ENUM enum
12112 */
12113
12114typedef enum DSCC_ICH_RESET_ENUM {
12115DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 0x00000001,
12116DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 0x00000002,
12117DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 0x00000004,
12118DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 0x00000008,
12119} DSCC_ICH_RESET_ENUM;
12120
12121/*
12122 * DSCC_LINEBUF_DEPTH_ENUM enum
12123 */
12124
12125typedef enum DSCC_LINEBUF_DEPTH_ENUM {
12126DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 0x00000008,
12127DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 0x00000009,
12128DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 0x0000000a,
12129DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 0x0000000b,
12130DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 0x0000000c,
12131DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 0x0000000d,
12132} DSCC_LINEBUF_DEPTH_ENUM;
12133
12134/*
12135 * DSCC_MEM_PWR_DIS_ENUM enum
12136 */
12137
12138typedef enum DSCC_MEM_PWR_DIS_ENUM {
12139DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0x00000000,
12140DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 0x00000001,
12141} DSCC_MEM_PWR_DIS_ENUM;
12142
12143/*
12144 * DSCC_MEM_PWR_FORCE_ENUM enum
12145 */
12146
12147typedef enum DSCC_MEM_PWR_FORCE_ENUM {
12148DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0x00000000,
12149DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
12150DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
12151DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
12152} DSCC_MEM_PWR_FORCE_ENUM;
12153
12154/*
12155 * POWER_STATE_ENUM enum
12156 */
12157
12158typedef enum POWER_STATE_ENUM {
12159POWER_STATE_ENUM_ON = 0x00000000,
12160POWER_STATE_ENUM_LS = 0x00000001,
12161POWER_STATE_ENUM_DS = 0x00000002,
12162POWER_STATE_ENUM_SD = 0x00000003,
12163} POWER_STATE_ENUM;
12164
12165/*******************************************************
12166 * DSCCIF Enums
12167 *******************************************************/
12168
12169/*
12170 * DSCCIF_BITS_PER_COMPONENT_ENUM enum
12171 */
12172
12173typedef enum DSCCIF_BITS_PER_COMPONENT_ENUM {
12174DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008,
12175DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a,
12176DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c,
12177} DSCCIF_BITS_PER_COMPONENT_ENUM;
12178
12179/*
12180 * DSCCIF_ENABLE_ENUM enum
12181 */
12182
12183typedef enum DSCCIF_ENABLE_ENUM {
12184DSCCIF_ENABLE_ENUM_DISABLED = 0x00000000,
12185DSCCIF_ENABLE_ENUM_ENABLED = 0x00000001,
12186} DSCCIF_ENABLE_ENUM;
12187
12188/*
12189 * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum
12190 */
12191
12192typedef enum DSCCIF_INPUT_PIXEL_FORMAT_ENUM {
12193DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0x00000000,
12194DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 0x00000001,
12195DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 0x00000002,
12196DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 0x00000003,
12197DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 0x00000004,
12198} DSCCIF_INPUT_PIXEL_FORMAT_ENUM;
12199
12200/*******************************************************
12201 * DSC_TOP Enums
12202 *******************************************************/
12203
12204/*
12205 * CLOCK_GATING_DISABLE_ENUM enum
12206 */
12207
12208typedef enum CLOCK_GATING_DISABLE_ENUM {
12209CLOCK_GATING_DISABLE_ENUM_ENABLED = 0x00000000,
12210CLOCK_GATING_DISABLE_ENUM_DISABLED = 0x00000001,
12211} CLOCK_GATING_DISABLE_ENUM;
12212
12213/*
12214 * ENABLE_ENUM enum
12215 */
12216
12217typedef enum ENABLE_ENUM {
12218ENABLE_ENUM_DISABLED = 0x00000000,
12219ENABLE_ENUM_ENABLED = 0x00000001,
12220} ENABLE_ENUM;
12221
12222/*
12223 * TEST_CLOCK_MUX_SELECT_ENUM enum
12224 */
12225
12226typedef enum TEST_CLOCK_MUX_SELECT_ENUM {
12227TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0x00000000,
12228TEST_CLOCK_MUX_SELECT_DISPCLK_G = 0x00000001,
12229TEST_CLOCK_MUX_SELECT_DISPCLK_R = 0x00000002,
12230TEST_CLOCK_MUX_SELECT_DSCCLK_P = 0x00000003,
12231TEST_CLOCK_MUX_SELECT_DSCCLK_G = 0x00000004,
12232TEST_CLOCK_MUX_SELECT_DSCCLK_R = 0x00000005,
12233} TEST_CLOCK_MUX_SELECT_ENUM;
12234
12235/*******************************************************
12236 * DWB_TOP Enums
12237 *******************************************************/
12238
12239/*
12240 * DWB_CRC_CONT_EN_ENUM enum
12241 */
12242
12243typedef enum DWB_CRC_CONT_EN_ENUM {
12244DWB_CRC_CONT_EN_ONE_SHOT = 0x00000000,
12245DWB_CRC_CONT_EN_CONT = 0x00000001,
12246} DWB_CRC_CONT_EN_ENUM;
12247
12248/*
12249 * DWB_CRC_SRC_SEL_ENUM enum
12250 */
12251
12252typedef enum DWB_CRC_SRC_SEL_ENUM {
12253DWB_CRC_SRC_SEL_DWB_IN = 0x00000000,
12254DWB_CRC_SRC_SEL_OGAM_OUT = 0x00000001,
12255DWB_CRC_SRC_SEL_DWB_OUT = 0x00000002,
12256} DWB_CRC_SRC_SEL_ENUM;
12257
12258/*
12259 * DWB_DATA_OVERFLOW_INT_TYPE_ENUM enum
12260 */
12261
12262typedef enum DWB_DATA_OVERFLOW_INT_TYPE_ENUM {
12263DWB_DATA_OVERFLOW_INT_TYPE_0 = 0x00000000,
12264DWB_DATA_OVERFLOW_INT_TYPE_1 = 0x00000001,
12265} DWB_DATA_OVERFLOW_INT_TYPE_ENUM;
12266
12267/*
12268 * DWB_DATA_OVERFLOW_TYPE_ENUM enum
12269 */
12270
12271typedef enum DWB_DATA_OVERFLOW_TYPE_ENUM {
12272DWB_DATA_OVERFLOW_TYPE_NO_OVERFLOW = 0x00000000,
12273DWB_DATA_OVERFLOW_TYPE_BUFFER = 0x00000001,
12274DWB_DATA_OVERFLOW_TYPE_VUPDATE = 0x00000002,
12275DWB_DATA_OVERFLOW_TYPE_VREADY = 0x00000003,
12276} DWB_DATA_OVERFLOW_TYPE_ENUM;
12277
12278/*
12279 * DWB_DEBUG_SEL_ENUM enum
12280 */
12281
12282typedef enum DWB_DEBUG_SEL_ENUM {
12283DWB_DEBUG_SEL_FC = 0x00000000,
12284DWB_DEBUG_SEL_RESERVED = 0x00000001,
12285DWB_DEBUG_SEL_DWBCP = 0x00000002,
12286DWB_DEBUG_SEL_PERFMON = 0x00000003,
12287} DWB_DEBUG_SEL_ENUM;
12288
12289/*
12290 * DWB_MEM_PWR_FORCE_ENUM enum
12291 */
12292
12293typedef enum DWB_MEM_PWR_FORCE_ENUM {
12294DWB_MEM_PWR_FORCE_DIS = 0x00000000,
12295DWB_MEM_PWR_FORCE_LS = 0x00000001,
12296DWB_MEM_PWR_FORCE_DS = 0x00000002,
12297DWB_MEM_PWR_FORCE_SD = 0x00000003,
12298} DWB_MEM_PWR_FORCE_ENUM;
12299
12300/*
12301 * DWB_MEM_PWR_STATE_ENUM enum
12302 */
12303
12304typedef enum DWB_MEM_PWR_STATE_ENUM {
12305DWB_MEM_PWR_STATE_ON = 0x00000000,
12306DWB_MEM_PWR_STATE_LS = 0x00000001,
12307DWB_MEM_PWR_STATE_DS = 0x00000002,
12308DWB_MEM_PWR_STATE_SD = 0x00000003,
12309} DWB_MEM_PWR_STATE_ENUM;
12310
12311/*
12312 * DWB_TEST_CLK_SEL_ENUM enum
12313 */
12314
12315typedef enum DWB_TEST_CLK_SEL_ENUM {
12316DWB_TEST_CLK_SEL_R = 0x00000000,
12317DWB_TEST_CLK_SEL_G = 0x00000001,
12318DWB_TEST_CLK_SEL_P = 0x00000002,
12319} DWB_TEST_CLK_SEL_ENUM;
12320
12321/*
12322 * FC_EYE_SELECTION_ENUM enum
12323 */
12324
12325typedef enum FC_EYE_SELECTION_ENUM {
12326FC_EYE_SELECTION_STEREO_DIS = 0x00000000,
12327FC_EYE_SELECTION_LEFT_EYE = 0x00000001,
12328FC_EYE_SELECTION_RIGHT_EYE = 0x00000002,
12329} FC_EYE_SELECTION_ENUM;
12330
12331/*
12332 * FC_FRAME_CAPTURE_RATE_ENUM enum
12333 */
12334
12335typedef enum FC_FRAME_CAPTURE_RATE_ENUM {
12336FC_FRAME_CAPTURE_RATE_FULL = 0x00000000,
12337FC_FRAME_CAPTURE_RATE_HALF = 0x00000001,
12338FC_FRAME_CAPTURE_RATE_THIRD = 0x00000002,
12339FC_FRAME_CAPTURE_RATE_QUARTER = 0x00000003,
12340} FC_FRAME_CAPTURE_RATE_ENUM;
12341
12342/*
12343 * FC_STEREO_EYE_POLARITY_ENUM enum
12344 */
12345
12346typedef enum FC_STEREO_EYE_POLARITY_ENUM {
12347FC_STEREO_EYE_POLARITY_LEFT = 0x00000000,
12348FC_STEREO_EYE_POLARITY_RIGHT = 0x00000001,
12349} FC_STEREO_EYE_POLARITY_ENUM;
12350
12351/*******************************************************
12352 * DWBCP Enums
12353 *******************************************************/
12354
12355/*
12356 * DWB_GAMUT_REMAP_COEF_FORMAT_ENUM enum
12357 */
12358
12359typedef enum DWB_GAMUT_REMAP_COEF_FORMAT_ENUM {
12360DWB_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0x00000000,
12361DWB_GAMUT_REMAP_COEF_FORMAT_S3_12 = 0x00000001,
12362} DWB_GAMUT_REMAP_COEF_FORMAT_ENUM;
12363
12364/*
12365 * DWB_GAMUT_REMAP_MODE_ENUM enum
12366 */
12367
12368typedef enum DWB_GAMUT_REMAP_MODE_ENUM {
12369DWB_GAMUT_REMAP_MODE_BYPASS = 0x00000000,
12370DWB_GAMUT_REMAP_MODE_COEF_A = 0x00000001,
12371DWB_GAMUT_REMAP_MODE_COEF_B = 0x00000002,
12372DWB_GAMUT_REMAP_MODE_RESERVED = 0x00000003,
12373} DWB_GAMUT_REMAP_MODE_ENUM;
12374
12375/*
12376 * DWB_LUT_NUM_SEG enum
12377 */
12378
12379typedef enum DWB_LUT_NUM_SEG {
12380DWB_SEGMENTS_1 = 0x00000000,
12381DWB_SEGMENTS_2 = 0x00000001,
12382DWB_SEGMENTS_4 = 0x00000002,
12383DWB_SEGMENTS_8 = 0x00000003,
12384DWB_SEGMENTS_16 = 0x00000004,
12385DWB_SEGMENTS_32 = 0x00000005,
12386DWB_SEGMENTS_64 = 0x00000006,
12387DWB_SEGMENTS_128 = 0x00000007,
12388} DWB_LUT_NUM_SEG;
12389
12390/*
12391 * DWB_OGAM_LUT_CONFIG_MODE_ENUM enum
12392 */
12393
12394typedef enum DWB_OGAM_LUT_CONFIG_MODE_ENUM {
12395DWB_OGAM_LUT_CONFIG_MODE_DIFF = 0x00000000,
12396DWB_OGAM_LUT_CONFIG_MODE_SAME = 0x00000001,
12397} DWB_OGAM_LUT_CONFIG_MODE_ENUM;
12398
12399/*
12400 * DWB_OGAM_LUT_HOST_SEL_ENUM enum
12401 */
12402
12403typedef enum DWB_OGAM_LUT_HOST_SEL_ENUM {
12404DWB_OGAM_LUT_HOST_SEL_RAMA = 0x00000000,
12405DWB_OGAM_LUT_HOST_SEL_RAMB = 0x00000001,
12406} DWB_OGAM_LUT_HOST_SEL_ENUM;
12407
12408/*
12409 * DWB_OGAM_LUT_READ_COLOR_SEL_ENUM enum
12410 */
12411
12412typedef enum DWB_OGAM_LUT_READ_COLOR_SEL_ENUM {
12413DWB_OGAM_LUT_READ_COLOR_SEL_B = 0x00000000,
12414DWB_OGAM_LUT_READ_COLOR_SEL_G = 0x00000001,
12415DWB_OGAM_LUT_READ_COLOR_SEL_R = 0x00000002,
12416DWB_OGAM_LUT_READ_COLOR_SEL_RESERVED = 0x00000003,
12417} DWB_OGAM_LUT_READ_COLOR_SEL_ENUM;
12418
12419/*
12420 * DWB_OGAM_LUT_READ_DBG_ENUM enum
12421 */
12422
12423typedef enum DWB_OGAM_LUT_READ_DBG_ENUM {
12424DWB_OGAM_LUT_READ_DBG_DISABLE = 0x00000000,
12425DWB_OGAM_LUT_READ_DBG_ENABLE = 0x00000001,
12426} DWB_OGAM_LUT_READ_DBG_ENUM;
12427
12428/*
12429 * DWB_OGAM_MODE_ENUM enum
12430 */
12431
12432typedef enum DWB_OGAM_MODE_ENUM {
12433DWB_OGAM_MODE_BYPASS = 0x00000000,
12434DWB_OGAM_MODE_RESERVED = 0x00000001,
12435DWB_OGAM_MODE_RAM_LUT_ENABLED = 0x00000002,
12436} DWB_OGAM_MODE_ENUM;
12437
12438/*
12439 * DWB_OGAM_PWL_DISABLE_ENUM enum
12440 */
12441
12442typedef enum DWB_OGAM_PWL_DISABLE_ENUM {
12443DWB_OGAM_PWL_DISABLE_FALSE = 0x00000000,
12444DWB_OGAM_PWL_DISABLE_TRUE = 0x00000001,
12445} DWB_OGAM_PWL_DISABLE_ENUM;
12446
12447/*
12448 * DWB_OGAM_SELECT_ENUM enum
12449 */
12450
12451typedef enum DWB_OGAM_SELECT_ENUM {
12452DWB_OGAM_SELECT_A = 0x00000000,
12453DWB_OGAM_SELECT_B = 0x00000001,
12454} DWB_OGAM_SELECT_ENUM;
12455
12456/*******************************************************
12457 * RDPCSPIPE Enums
12458 *******************************************************/
12459
12460/*
12461 * RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN enum
12462 */
12463
12464typedef enum RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN {
12465RDPCSPIPE_EXT_PCLK_EN_DISABLE = 0x00000000,
12466RDPCSPIPE_EXT_PCLK_EN_ENABLE = 0x00000001,
12467} RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN;
12468
12469/*
12470 * RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN enum
12471 */
12472
12473typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN {
12474RDPCSPIPE_APBCLK_DISABLE = 0x00000000,
12475RDPCSPIPE_APBCLK_ENABLE = 0x00000001,
12476} RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN;
12477
12478/*
12479 * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON enum
12480 */
12481
12482typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON {
12483RDPCS_PIPE_CLK_CLOCK_OFF = 0x00000000,
12484RDPCS_PIPE_CLK_CLOCK_ON = 0x00000001,
12485} RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON;
12486
12487/*
12488 * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN enum
12489 */
12490
12491typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN {
12492RDPCS_PIPE_CLK_DISABLE = 0x00000000,
12493RDPCS_PIPE_CLK_ENABLE = 0x00000001,
12494} RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN;
12495
12496/*
12497 * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS enum
12498 */
12499
12500typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS {
12501RDPCS_PIPE_CLK_GATE_ENABLE = 0x00000000,
12502RDPCS_PIPE_CLK_GATE_DISABLE = 0x00000001,
12503} RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS;
12504
12505/*
12506 * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON enum
12507 */
12508
12509typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON {
12510RDPCS_PIPE_PHYD32CLK_CLOCK_OFF = 0x00000000,
12511RDPCS_PIPE_PHYD32CLK_CLOCK_ON = 0x00000001,
12512} RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON;
12513
12514/*
12515 * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum
12516 */
12517
12518typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON {
12519RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_OFF = 0x00000000,
12520RDPCSPIPE_SYMCLK_SRAMCLK_CLOCK_ON = 0x00000001,
12521} RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON;
12522
12523/*
12524 * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum
12525 */
12526
12527typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN {
12528RDPCSPIPE_SRAMCLK_DISABLE = 0x00000000,
12529RDPCSPIPE_SRAMCLK_ENABLE = 0x00000001,
12530} RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN;
12531
12532/*
12533 * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum
12534 */
12535
12536typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS {
12537RDPCSPIPE_SRAMCLK_GATE_ENABLE = 0x00000000,
12538RDPCSPIPE_SRAMCLK_GATE_DISABLE = 0x00000001,
12539} RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS;
12540
12541/*
12542 * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS enum
12543 */
12544
12545typedef enum RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS {
12546RDPCSPIPE_SRAMCLK_NOT_PASS = 0x00000000,
12547RDPCSPIPE_SRAMCLK_PASS = 0x00000001,
12548} RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS;
12549
12550/*
12551 * RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN enum
12552 */
12553
12554typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN {
12555RDPCS_PIPE_FIFO_DISABLE = 0x00000000,
12556RDPCS_PIPE_FIFO_ENABLE = 0x00000001,
12557} RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN;
12558
12559/*
12560 * RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN enum
12561 */
12562
12563typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN {
12564RDPCS_PIPE_FIFO_LANE_DISABLE = 0x00000000,
12565RDPCS_PIPE_FIFO_LANE_ENABLE = 0x00000001,
12566} RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN;
12567
12568/*
12569 * RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET enum
12570 */
12571
12572typedef enum RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET {
12573RDPCS_PIPE_SOFT_RESET_DISABLE = 0x00000000,
12574RDPCS_PIPE_SOFT_RESET_ENABLE = 0x00000001,
12575} RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET;
12576
12577/*
12578 * RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET enum
12579 */
12580
12581typedef enum RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET {
12582RDPCSPIPE_SRAM_SRAM_RESET_DISABLE = 0x00000000,
12583RDPCSPIPE_SRAM_SRAM_RESET_ENABLE = 0x00000001,
12584} RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET;
12585
12586/*
12587 * RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK enum
12588 */
12589
12590typedef enum RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK {
12591RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_DISABLE = 0x00000000,
12592RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK_ENABLE = 0x00000001,
12593} RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK;
12594
12595/*
12596 * RDPCSPIPE_DBG_OCLA_SEL enum
12597 */
12598
12599typedef enum RDPCSPIPE_DBG_OCLA_SEL {
12600RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_7_0 = 0x00000000,
12601RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_15_8 = 0x00000001,
12602RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_23_16 = 0x00000002,
12603RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_31_24 = 0x00000003,
12604RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_39_32 = 0x00000004,
12605RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_47_40 = 0x00000005,
12606RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_55_48 = 0x00000006,
12607RDPCSPIPE_DBG_OCLA_SEL_MON_OUT_63_56 = 0x00000007,
12608} RDPCSPIPE_DBG_OCLA_SEL;
12609
12610/*
12611 * RDPCSPIPE_ENC_TYPE enum
12612 */
12613
12614typedef enum RDPCSPIPE_ENC_TYPE {
12615HDMI_TMDS_OR_DP_8B10B = 0x00000000,
12616HDMI_FRL = 0x00000001,
12617DP_128B132B = 0x00000002,
12618} RDPCSPIPE_ENC_TYPE;
12619
12620/*
12621 * RDPCSPIPE_FIFO_EMPTY enum
12622 */
12623
12624typedef enum RDPCSPIPE_FIFO_EMPTY {
12625RDPCSPIPE_FIFO_NOT_EMPTY = 0x00000000,
12626RDPCSPIPE_FIFO_IS_EMPTY = 0x00000001,
12627} RDPCSPIPE_FIFO_EMPTY;
12628
12629/*
12630 * RDPCSPIPE_FIFO_FULL enum
12631 */
12632
12633typedef enum RDPCSPIPE_FIFO_FULL {
12634RDPCSPIPE_FIFO_NOT_FULL = 0x00000000,
12635RDPCSPIPE_FIFO_IS_FULL = 0x00000001,
12636} RDPCSPIPE_FIFO_FULL;
12637
12638/*
12639 * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK enum
12640 */
12641
12642typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK {
12643RDPCSPIPE_APB_PSLVERR_MASK_DISABLE = 0x00000000,
12644RDPCSPIPE_APB_PSLVERR_MASK_ENABLE = 0x00000001,
12645} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK;
12646
12647/*
12648 * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum
12649 */
12650
12651typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE {
12652RDPCSPIPE_DPALT_4LANE_TOGGLE_2LANE = 0x00000000,
12653RDPCSPIPE_DPALT_4LANE_TOGGLE_4LANE = 0x00000001,
12654} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE;
12655
12656/*
12657 * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum
12658 */
12659
12660typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK {
12661RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0x00000000,
12662RDPCSPIPE_DPALT_4LANE_TOGGLE_MASK_ENABLE = 0x00000001,
12663} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK;
12664
12665/*
12666 * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum
12667 */
12668
12669typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE {
12670RDPCSPIPE_DPALT_DISABLE_TOGGLE_ENABLE = 0x00000000,
12671RDPCSPIPE_DPALT_DISABLE_TOGGLE_DISABLE = 0x00000001,
12672} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE;
12673
12674/*
12675 * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum
12676 */
12677
12678typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK {
12679RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0x00000000,
12680RDPCSPIPE_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 0x00000001,
12681} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK;
12682
12683/*
12684 * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK enum
12685 */
12686
12687typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK {
12688RDPCSPIPE_PIPE_FIFO_ERROR_MASK_DISABLE = 0x00000000,
12689RDPCSPIPE_PIPE_FIFO_ERROR_MASK_ENABLE = 0x00000001,
12690} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK;
12691
12692/*
12693 * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum
12694 */
12695
12696typedef enum RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK {
12697RDPCSPIPE_REG_FIFO_ERROR_MASK_DISABLE = 0x00000000,
12698RDPCSPIPE_REG_FIFO_ERROR_MASK_ENABLE = 0x00000001,
12699} RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK;
12700
12701/*
12702 * RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK enum
12703 */
12704
12705typedef enum RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK {
12706RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_DISABLE = 0x00000000,
12707RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK_ENABLE = 0x00000001,
12708} RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK;
12709
12710/*
12711 * RDPCSPIPE_PACK_MODE enum
12712 */
12713
12714typedef enum RDPCSPIPE_PACK_MODE {
12715TIGHT_PACK = 0x00000000,
12716LOOSE_PACK = 0x00000001,
12717} RDPCSPIPE_PACK_MODE;
12718
12719/*
12720 * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL enum
12721 */
12722
12723typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL {
12724RDPCSPIPE_PHY_CR_MUX_SEL_FOR_USB = 0x00000000,
12725RDPCSPIPE_PHY_CR_MUX_SEL_FOR_DC = 0x00000001,
12726} RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL;
12727
12728/*
12729 * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum
12730 */
12731
12732typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL {
12733RDPCSPIPE_PHY_CR_PARA_SEL_JTAG = 0x00000000,
12734RDPCSPIPE_PHY_CR_PARA_SEL_CR = 0x00000001,
12735} RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL;
12736
12737/*
12738 * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum
12739 */
12740
12741typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE {
12742RDPCSPIPE_PHY_REF_RANGE_0 = 0x00000000,
12743RDPCSPIPE_PHY_REF_RANGE_1 = 0x00000001,
12744RDPCSPIPE_PHY_REF_RANGE_2 = 0x00000002,
12745RDPCSPIPE_PHY_REF_RANGE_3 = 0x00000003,
12746RDPCSPIPE_PHY_REF_RANGE_4 = 0x00000004,
12747RDPCSPIPE_PHY_REF_RANGE_5 = 0x00000005,
12748RDPCSPIPE_PHY_REF_RANGE_6 = 0x00000006,
12749RDPCSPIPE_PHY_REF_RANGE_7 = 0x00000007,
12750} RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE;
12751
12752/*
12753 * RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE enum
12754 */
12755
12756typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE {
12757RDPCSPIPE_SRAM_EXT_LD_NOT_DONE = 0x00000000,
12758RDPCSPIPE_SRAM_EXT_LD_DONE = 0x00000001,
12759} RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE;
12760
12761/*
12762 * RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE enum
12763 */
12764
12765typedef enum RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE {
12766RDPCSPIPE_SRAM_INIT_NOT_DONE = 0x00000000,
12767RDPCSPIPE_SRAM_INIT_DONE = 0x00000001,
12768} RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE;
12769
12770/*
12771 * RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV enum
12772 */
12773
12774typedef enum RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV {
12775RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV1 = 0x00000000,
12776RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV2 = 0x00000001,
12777RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV3 = 0x00000002,
12778RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV8 = 0x00000003,
12779RDPCSPIPE_PHY_DP_REF_CLK_MPLLB_DIV16 = 0x00000004,
12780} RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;
12781
12782/*
12783 * RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV enum
12784 */
12785
12786typedef enum RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV {
12787RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0x00000000,
12788RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 0x00000001,
12789RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 0x00000002,
12790RDPCSPIPE_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 0x00000003,
12791} RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV;
12792
12793/*
12794 * RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV enum
12795 */
12796
12797typedef enum RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV {
12798RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV = 0x00000000,
12799RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV2 = 0x00000001,
12800RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV4 = 0x00000002,
12801RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV8 = 0x00000003,
12802RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV3 = 0x00000004,
12803RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV5 = 0x00000005,
12804RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV6 = 0x00000006,
12805RDPCSPIPE_PHY_DP_MPLLB_TX_CLK_DIV10 = 0x00000007,
12806} RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;
12807
12808/*
12809 * RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL enum
12810 */
12811
12812typedef enum RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL {
12813RDPCSPIPE_PHY_DP_TX_TERM_CTRL_54 = 0x00000000,
12814RDPCSPIPE_PHY_DP_TX_TERM_CTRL_52 = 0x00000001,
12815RDPCSPIPE_PHY_DP_TX_TERM_CTRL_50 = 0x00000002,
12816RDPCSPIPE_PHY_DP_TX_TERM_CTRL_48 = 0x00000003,
12817RDPCSPIPE_PHY_DP_TX_TERM_CTRL_46 = 0x00000004,
12818RDPCSPIPE_PHY_DP_TX_TERM_CTRL_44 = 0x00000005,
12819RDPCSPIPE_PHY_DP_TX_TERM_CTRL_42 = 0x00000006,
12820RDPCSPIPE_PHY_DP_TX_TERM_CTRL_40 = 0x00000007,
12821} RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL;
12822
12823/*
12824 * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT enum
12825 */
12826
12827typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT {
12828RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0x00000000,
12829RDPCSPIPE_PHY_DP_TX_DETRX_RESULT_DETECT = 0x00000001,
12830} RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT;
12831
12832/*
12833 * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE enum
12834 */
12835
12836typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE {
12837RDPCSPIPE_PHY_DP_TX_RATE = 0x00000000,
12838RDPCSPIPE_PHY_DP_TX_RATE_DIV2 = 0x00000001,
12839RDPCSPIPE_PHY_DP_TX_RATE_DIV4 = 0x00000002,
12840} RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE;
12841
12842/*
12843 * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH enum
12844 */
12845
12846typedef enum RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH {
12847RDPCSPIPE_PHY_DP_TX_WIDTH_8 = 0x00000000,
12848RDPCSPIPE_PHY_DP_TX_WIDTH_10 = 0x00000001,
12849RDPCSPIPE_PHY_DP_TX_WIDTH_16 = 0x00000002,
12850RDPCSPIPE_PHY_DP_TX_WIDTH_20 = 0x00000003,
12851} RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH;
12852
12853/*
12854 * RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE enum
12855 */
12856
12857typedef enum RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE {
12858RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_UP = 0x00000000,
12859RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD = 0x00000001,
12860RRDPCSPIPE_PHY_DP_TX_PSTATE_HOLD_OFF = 0x00000002,
12861RRDPCSPIPE_PHY_DP_TX_PSTATE_POWER_DOWN = 0x00000003,
12862} RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE;
12863
12864/*
12865 * RDPCSPIPE_PHY_IF_WIDTH enum
12866 */
12867
12868typedef enum RDPCSPIPE_PHY_IF_WIDTH {
12869PHY_IF_WIDTH_10BIT = 0x00000000,
12870PHY_IF_WIDTH_20BIT = 0x00000001,
12871PHY_IF_WIDTH_40BIT = 0x00000002,
12872PHY_IF_WIDTH_80BIT = 0x00000003,
12873} RDPCSPIPE_PHY_IF_WIDTH;
12874
12875/*
12876 * RDPCSPIPE_PHY_RATE enum
12877 */
12878
12879typedef enum RDPCSPIPE_PHY_RATE {
12880PHY_DP_RATE_1P62 = 0x00000000,
12881PHY_DP_RATE_2P7 = 0x00000001,
12882PHY_DP_RATE_5P4 = 0x00000002,
12883PHY_DP_RATE_8P1 = 0x00000003,
12884PHY_DP_RATE_2P16 = 0x00000004,
12885PHY_DP_RATE_2P43 = 0x00000005,
12886PHY_DP_RATE_3P24 = 0x00000006,
12887PHY_DP_RATE_4P32 = 0x00000007,
12888PHY_DP_RATE_10P = 0x00000008,
12889PHY_DP_RATE_13P5 = 0x00000009,
12890PHY_DP_RATE_20P = 0x0000000a,
12891PHY_CUSTOM_RATE = 0x0000000f,
12892} RDPCSPIPE_PHY_RATE;
12893
12894/*
12895 * RDPCSPIPE_PHY_REF_ALT_CLK_EN enum
12896 */
12897
12898typedef enum RDPCSPIPE_PHY_REF_ALT_CLK_EN {
12899RDPCSPIPE_PHY_REF_ALT_CLK_DISABLE = 0x00000000,
12900RDPCSPIPE_PHY_REF_ALT_CLK_ENABLE = 0x00000001,
12901} RDPCSPIPE_PHY_REF_ALT_CLK_EN;
12902
12903/*
12904 * RDPCSPIPE_TEST_CLK_SEL enum
12905 */
12906
12907typedef enum RDPCSPIPE_TEST_CLK_SEL {
12908RDPCSPIPE_TEST_CLK_SEL_NONE = 0x00000000,
12909RDPCSPIPE_TEST_CLK_SEL_CFGCLK = 0x00000001,
12910RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 0x00000002,
12911RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 0x00000003,
12912RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 0x00000004,
12913RDPCSPIPE_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 0x00000005,
12914RDPCSPIPE_TEST_CLK_SEL_SRAMCLK = 0x00000006,
12915RDPCSPIPE_TEST_CLK_SEL_EXT_CR_CLK = 0x00000007,
12916RDPCSPIPE_TEST_CLK_SEL_DP_TX0_WORD_CLK = 0x00000008,
12917RDPCSPIPE_TEST_CLK_SEL_DP_TX1_WORD_CLK = 0x00000009,
12918RDPCSPIPE_TEST_CLK_SEL_DP_TX2_WORD_CLK = 0x0000000a,
12919RDPCSPIPE_TEST_CLK_SEL_DP_TX3_WORD_CLK = 0x0000000b,
12920RDPCSPIPE_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 0x0000000c,
12921RDPCSPIPE_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 0x0000000d,
12922RDPCSPIPE_TEST_CLK_SEL_PHY_REF_DIG_CLK = 0x0000000e,
12923RDPCSPIPE_TEST_CLK_SEL_REF_DIG_FR_clk = 0x0000000f,
12924RDPCSPIPE_TEST_CLK_SEL_dtb_out0 = 0x00000010,
12925RDPCSPIPE_TEST_CLK_SEL_dtb_out1 = 0x00000011,
12926} RDPCSPIPE_TEST_CLK_SEL;
12927
12928/*
12929 * RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB enum
12930 */
12931
12932typedef enum RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB {
12933RDPCSPIPE_LANE_PACK_FROM_MSB_DISABLE = 0x00000000,
12934RDPCSPIPE_LANE_PACK_FROM_MSB_ENABLE = 0x00000001,
12935} RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB;
12936
12937/*
12938 * RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum
12939 */
12940
12941typedef enum RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE {
12942RDPCSPIPE_MEM_PWR_NO_FORCE = 0x00000000,
12943RDPCSPIPE_MEM_PWR_LIGHT_SLEEP = 0x00000001,
12944RDPCSPIPE_MEM_PWR_DEEP_SLEEP = 0x00000002,
12945RDPCSPIPE_MEM_PWR_SHUT_DOWN = 0x00000003,
12946} RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE;
12947
12948/*
12949 * RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum
12950 */
12951
12952typedef enum RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE {
12953RDPCSPIPE_MEM_PWR_PWR_STATE_ON = 0x00000000,
12954RDPCSPIPE_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 0x00000001,
12955RDPCSPIPE_MEM_PWR_PWR_STATE_DEEP_SLEEP = 0x00000002,
12956RDPCSPIPE_MEM_PWR_PWR_STATE_SHUT_DOWN = 0x00000003,
12957} RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE;
12958
12959/*
12960 * RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK enum
12961 */
12962
12963typedef enum RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK {
12964RDPCSPIPE_LANE_BIT_ORDER_REVERSE_DISABLE = 0x00000000,
12965RDPCSPIPE_LANE_BIT_ORDER_REVERSE_ENABLE = 0x00000001,
12966} RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK;
12967
12968/*******************************************************
12969 * GDS Enums
12970 *******************************************************/
12971
12972/*
12973 * GDS_PERFCOUNT_SELECT enum
12974 */
12975
12976typedef enum GDS_PERFCOUNT_SELECT {
12977GDS_PERF_SEL_WR_COMP = 0x00000000,
12978GDS_PERF_SEL_WBUF_WR = 0x00000001,
12979GDS_PERF_SEL_SE0_NORET = 0x00000002,
12980GDS_PERF_SEL_SE0_RET = 0x00000003,
12981GDS_PERF_SEL_SE0_ORD_CNT = 0x00000004,
12982GDS_PERF_SEL_SE0_2COMP_REQ = 0x00000005,
12983GDS_PERF_SEL_SE0_ORD_WAVE_VALID = 0x00000006,
12984GDS_PERF_SEL_SE0_GDS_STALL_BY_ORD = 0x00000007,
12985GDS_PERF_SEL_SE0_GDS_WR_OP = 0x00000008,
12986GDS_PERF_SEL_SE0_GDS_RD_OP = 0x00000009,
12987GDS_PERF_SEL_SE0_GDS_ATOM_OP = 0x0000000a,
12988GDS_PERF_SEL_SE0_GDS_REL_OP = 0x0000000b,
12989GDS_PERF_SEL_SE0_GDS_CMPXCH_OP = 0x0000000c,
12990GDS_PERF_SEL_SE0_GDS_BYTE_OP = 0x0000000d,
12991GDS_PERF_SEL_SE0_GDS_SHORT_OP = 0x0000000e,
12992GDS_PERF_SEL_SE1_NORET = 0x0000000f,
12993GDS_PERF_SEL_SE1_RET = 0x00000010,
12994GDS_PERF_SEL_SE1_ORD_CNT = 0x00000011,
12995GDS_PERF_SEL_SE1_2COMP_REQ = 0x00000012,
12996GDS_PERF_SEL_SE1_ORD_WAVE_VALID = 0x00000013,
12997GDS_PERF_SEL_SE1_GDS_STALL_BY_ORD = 0x00000014,
12998GDS_PERF_SEL_SE1_GDS_WR_OP = 0x00000015,
12999GDS_PERF_SEL_SE1_GDS_RD_OP = 0x00000016,
13000GDS_PERF_SEL_SE1_GDS_ATOM_OP = 0x00000017,
13001GDS_PERF_SEL_SE1_GDS_REL_OP = 0x00000018,
13002GDS_PERF_SEL_SE1_GDS_CMPXCH_OP = 0x00000019,
13003GDS_PERF_SEL_SE1_GDS_BYTE_OP = 0x0000001a,
13004GDS_PERF_SEL_SE1_GDS_SHORT_OP = 0x0000001b,
13005GDS_PERF_SEL_SE2_NORET = 0x0000001c,
13006GDS_PERF_SEL_SE2_RET = 0x0000001d,
13007GDS_PERF_SEL_SE2_ORD_CNT = 0x0000001e,
13008GDS_PERF_SEL_SE2_2COMP_REQ = 0x0000001f,
13009GDS_PERF_SEL_SE2_ORD_WAVE_VALID = 0x00000020,
13010GDS_PERF_SEL_SE2_GDS_STALL_BY_ORD = 0x00000021,
13011GDS_PERF_SEL_SE2_GDS_WR_OP = 0x00000022,
13012GDS_PERF_SEL_SE2_GDS_RD_OP = 0x00000023,
13013GDS_PERF_SEL_SE2_GDS_ATOM_OP = 0x00000024,
13014GDS_PERF_SEL_SE2_GDS_REL_OP = 0x00000025,
13015GDS_PERF_SEL_SE2_GDS_CMPXCH_OP = 0x00000026,
13016GDS_PERF_SEL_SE2_GDS_BYTE_OP = 0x00000027,
13017GDS_PERF_SEL_SE2_GDS_SHORT_OP = 0x00000028,
13018GDS_PERF_SEL_SE3_NORET = 0x00000029,
13019GDS_PERF_SEL_SE3_RET = 0x0000002a,
13020GDS_PERF_SEL_SE3_ORD_CNT = 0x0000002b,
13021GDS_PERF_SEL_SE3_2COMP_REQ = 0x0000002c,
13022GDS_PERF_SEL_SE3_ORD_WAVE_VALID = 0x0000002d,
13023GDS_PERF_SEL_SE3_GDS_STALL_BY_ORD = 0x0000002e,
13024GDS_PERF_SEL_SE3_GDS_WR_OP = 0x0000002f,
13025GDS_PERF_SEL_SE3_GDS_RD_OP = 0x00000030,
13026GDS_PERF_SEL_SE3_GDS_ATOM_OP = 0x00000031,
13027GDS_PERF_SEL_SE3_GDS_REL_OP = 0x00000032,
13028GDS_PERF_SEL_SE3_GDS_CMPXCH_OP = 0x00000033,
13029GDS_PERF_SEL_SE3_GDS_BYTE_OP = 0x00000034,
13030GDS_PERF_SEL_SE3_GDS_SHORT_OP = 0x00000035,
13031GDS_PERF_SEL_SE4_NORET = 0x00000036,
13032GDS_PERF_SEL_SE4_RET = 0x00000037,
13033GDS_PERF_SEL_SE4_ORD_CNT = 0x00000038,
13034GDS_PERF_SEL_SE4_2COMP_REQ = 0x00000039,
13035GDS_PERF_SEL_SE4_ORD_WAVE_VALID = 0x0000003a,
13036GDS_PERF_SEL_SE4_GDS_STALL_BY_ORD = 0x0000003b,
13037GDS_PERF_SEL_SE4_GDS_WR_OP = 0x0000003c,
13038GDS_PERF_SEL_SE4_GDS_RD_OP = 0x0000003d,
13039GDS_PERF_SEL_SE4_GDS_ATOM_OP = 0x0000003e,
13040GDS_PERF_SEL_SE4_GDS_REL_OP = 0x0000003f,
13041GDS_PERF_SEL_SE4_GDS_CMPXCH_OP = 0x00000040,
13042GDS_PERF_SEL_SE4_GDS_BYTE_OP = 0x00000041,
13043GDS_PERF_SEL_SE4_GDS_SHORT_OP = 0x00000042,
13044GDS_PERF_SEL_SE5_NORET = 0x00000043,
13045GDS_PERF_SEL_SE5_RET = 0x00000044,
13046GDS_PERF_SEL_SE5_ORD_CNT = 0x00000045,
13047GDS_PERF_SEL_SE5_2COMP_REQ = 0x00000046,
13048GDS_PERF_SEL_SE5_ORD_WAVE_VALID = 0x00000047,
13049GDS_PERF_SEL_SE5_GDS_STALL_BY_ORD = 0x00000048,
13050GDS_PERF_SEL_SE5_GDS_WR_OP = 0x00000049,
13051GDS_PERF_SEL_SE5_GDS_RD_OP = 0x0000004a,
13052GDS_PERF_SEL_SE5_GDS_ATOM_OP = 0x0000004b,
13053GDS_PERF_SEL_SE5_GDS_REL_OP = 0x0000004c,
13054GDS_PERF_SEL_SE5_GDS_CMPXCH_OP = 0x0000004d,
13055GDS_PERF_SEL_SE5_GDS_BYTE_OP = 0x0000004e,
13056GDS_PERF_SEL_SE5_GDS_SHORT_OP = 0x0000004f,
13057GDS_PERF_SEL_SE6_NORET = 0x00000050,
13058GDS_PERF_SEL_SE6_RET = 0x00000051,
13059GDS_PERF_SEL_SE6_ORD_CNT = 0x00000052,
13060GDS_PERF_SEL_SE6_2COMP_REQ = 0x00000053,
13061GDS_PERF_SEL_SE6_ORD_WAVE_VALID = 0x00000054,
13062GDS_PERF_SEL_SE6_GDS_STALL_BY_ORD = 0x00000055,
13063GDS_PERF_SEL_SE6_GDS_WR_OP = 0x00000056,
13064GDS_PERF_SEL_SE6_GDS_RD_OP = 0x00000057,
13065GDS_PERF_SEL_SE6_GDS_ATOM_OP = 0x00000058,
13066GDS_PERF_SEL_SE6_GDS_REL_OP = 0x00000059,
13067GDS_PERF_SEL_SE6_GDS_CMPXCH_OP = 0x0000005a,
13068GDS_PERF_SEL_SE6_GDS_BYTE_OP = 0x0000005b,
13069GDS_PERF_SEL_SE6_GDS_SHORT_OP = 0x0000005c,
13070GDS_PERF_SEL_SE7_NORET = 0x0000005d,
13071GDS_PERF_SEL_SE7_RET = 0x0000005e,
13072GDS_PERF_SEL_SE7_ORD_CNT = 0x0000005f,
13073GDS_PERF_SEL_SE7_2COMP_REQ = 0x00000060,
13074GDS_PERF_SEL_SE7_ORD_WAVE_VALID = 0x00000061,
13075GDS_PERF_SEL_SE7_GDS_STALL_BY_ORD = 0x00000062,
13076GDS_PERF_SEL_SE7_GDS_WR_OP = 0x00000063,
13077GDS_PERF_SEL_SE7_GDS_RD_OP = 0x00000064,
13078GDS_PERF_SEL_SE7_GDS_ATOM_OP = 0x00000065,
13079GDS_PERF_SEL_SE7_GDS_REL_OP = 0x00000066,
13080GDS_PERF_SEL_SE7_GDS_CMPXCH_OP = 0x00000067,
13081GDS_PERF_SEL_SE7_GDS_BYTE_OP = 0x00000068,
13082GDS_PERF_SEL_SE7_GDS_SHORT_OP = 0x00000069,
13083GDS_PERF_SEL_GWS_RELEASED = 0x0000006a,
13084GDS_PERF_SEL_GWS_BYPASS = 0x0000006b,
13085} GDS_PERFCOUNT_SELECT;
13086
13087/*******************************************************
13088 * CB Enums
13089 *******************************************************/
13090
13091/*
13092 * BlendOp enum
13093 */
13094
13095typedef enum BlendOp {
13096BLEND_ZERO = 0x00000000,
13097BLEND_ONE = 0x00000001,
13098BLEND_SRC_COLOR = 0x00000002,
13099BLEND_ONE_MINUS_SRC_COLOR = 0x00000003,
13100BLEND_SRC_ALPHA = 0x00000004,
13101BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005,
13102BLEND_DST_ALPHA = 0x00000006,
13103BLEND_ONE_MINUS_DST_ALPHA = 0x00000007,
13104BLEND_DST_COLOR = 0x00000008,
13105BLEND_ONE_MINUS_DST_COLOR = 0x00000009,
13106BLEND_SRC_ALPHA_SATURATE = 0x0000000a,
13107BLEND_CONSTANT_COLOR = 0x0000000b,
13108BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000c,
13109BLEND_SRC1_COLOR = 0x0000000d,
13110BLEND_INV_SRC1_COLOR = 0x0000000e,
13111BLEND_SRC1_ALPHA = 0x0000000f,
13112BLEND_INV_SRC1_ALPHA = 0x00000010,
13113BLEND_CONSTANT_ALPHA = 0x00000011,
13114BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000012,
13115} BlendOp;
13116
13117/*
13118 * BlendOpt enum
13119 */
13120
13121typedef enum BlendOpt {
13122FORCE_OPT_AUTO = 0x00000000,
13123FORCE_OPT_DISABLE = 0x00000001,
13124FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002,
13125FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003,
13126FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004,
13127FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005,
13128FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006,
13129FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007,
13130} BlendOpt;
13131
13132/*
13133 * CBMode enum
13134 */
13135
13136typedef enum CBMode {
13137CB_DISABLE = 0x00000000,
13138CB_NORMAL = 0x00000001,
13139CB_ELIMINATE_FAST_CLEAR = 0x00000002,
13140CB_DCC_DECOMPRESS = 0x00000003,
13141CB_RESERVED = 0x00000004,
13142} CBMode;
13143
13144/*
13145 * CBPerfClearFilterSel enum
13146 */
13147
13148typedef enum CBPerfClearFilterSel {
13149CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000,
13150CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001,
13151} CBPerfClearFilterSel;
13152
13153/*
13154 * CBPerfOpFilterSel enum
13155 */
13156
13157typedef enum CBPerfOpFilterSel {
13158CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000,
13159CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001,
13160CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002,
13161CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003,
13162CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004,
13163CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005,
13164} CBPerfOpFilterSel;
13165
13166/*
13167 * CBPerfSel enum
13168 */
13169
13170typedef enum CBPerfSel {
13171CB_PERF_SEL_NONE = 0x00000000,
13172CB_PERF_SEL_DRAWN_PIXEL = 0x00000001,
13173CB_PERF_SEL_DRAWN_QUAD = 0x00000002,
13174CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000003,
13175CB_PERF_SEL_DRAWN_TILE = 0x00000004,
13176CB_PERF_SEL_FILTER_DRAWN_PIXEL = 0x00000005,
13177CB_PERF_SEL_FILTER_DRAWN_QUAD = 0x00000006,
13178CB_PERF_SEL_FILTER_DRAWN_QUAD_FRAGMENT = 0x00000007,
13179CB_PERF_SEL_FILTER_DRAWN_TILE = 0x00000008,
13180CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_IN = 0x00000009,
13181CB_PERF_SEL_CC_DCC_DECOMPRESS_TID_OUT = 0x0000000a,
13182CB_PERF_SEL_CC_DCC_COMPRESS_TID_IN = 0x0000000b,
13183CB_PERF_SEL_CC_DCC_COMPRESS_TID_OUT = 0x0000000c,
13184CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x0000000d,
13185CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x0000000e,
13186CB_PERF_SEL_CC_MC_READ_REQUEST = 0x0000000f,
13187CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000010,
13188CB_PERF_SEL_DB_CB_EXPORT_VALID_READY = 0x00000011,
13189CB_PERF_SEL_DB_CB_EXPORT_VALID_READYB = 0x00000012,
13190CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READY = 0x00000013,
13191CB_PERF_SEL_DB_CB_EXPORT_VALIDB_READYB = 0x00000014,
13192CB_PERF_SEL_RESERVED_21 = 0x00000015,
13193CB_PERF_SEL_RESERVED_22 = 0x00000016,
13194CB_PERF_SEL_RESERVED_23 = 0x00000017,
13195CB_PERF_SEL_RESERVED_24 = 0x00000018,
13196CB_PERF_SEL_RESERVED_25 = 0x00000019,
13197CB_PERF_SEL_RESERVED_26 = 0x0000001a,
13198CB_PERF_SEL_RESERVED_27 = 0x0000001b,
13199CB_PERF_SEL_RESERVED_28 = 0x0000001c,
13200CB_PERF_SEL_RESERVED_29 = 0x0000001d,
13201CB_PERF_SEL_CB_RMI_WRREQ_VALID_READY = 0x0000001e,
13202CB_PERF_SEL_CB_RMI_WRREQ_VALID_READYB = 0x0000001f,
13203CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READY = 0x00000020,
13204CB_PERF_SEL_CB_RMI_WRREQ_VALIDB_READYB = 0x00000021,
13205CB_PERF_SEL_CB_RMI_RDREQ_VALID_READY = 0x00000022,
13206CB_PERF_SEL_CB_RMI_RDREQ_VALID_READYB = 0x00000023,
13207CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READY = 0x00000024,
13208CB_PERF_SEL_CB_RMI_RDREQ_VALIDB_READYB = 0x00000025,
13209CB_PERF_SEL_RESERVED_38 = 0x00000026,
13210CB_PERF_SEL_RESERVED_39 = 0x00000027,
13211CB_PERF_SEL_RESERVED_40 = 0x00000028,
13212CB_PERF_SEL_RESERVED_41 = 0x00000029,
13213CB_PERF_SEL_RESERVED_42 = 0x0000002a,
13214CB_PERF_SEL_RESERVED_43 = 0x0000002b,
13215CB_PERF_SEL_RESERVED_44 = 0x0000002c,
13216CB_PERF_SEL_RESERVED_45 = 0x0000002d,
13217CB_PERF_SEL_RESERVED_46 = 0x0000002e,
13218CB_PERF_SEL_RESERVED_47 = 0x0000002f,
13219CB_PERF_SEL_RESERVED_48 = 0x00000030,
13220CB_PERF_SEL_RESERVED_49 = 0x00000031,
13221CB_PERF_SEL_STATIC_CLOCK_EN = 0x00000032,
13222CB_PERF_SEL_PERFMON_CLOCK_EN = 0x00000033,
13223CB_PERF_SEL_BLEND_CLOCK_EN = 0x00000034,
13224CB_PERF_SEL_COLOR_STORE_CLOCK_EN = 0x00000035,
13225CB_PERF_SEL_BACKEND_READ_CLOCK_EN = 0x00000036,
13226CB_PERF_SEL_GRBM_CLOCK_EN = 0x00000037,
13227CB_PERF_SEL_MEMARB_CLOCK_EN = 0x00000038,
13228CB_PERF_SEL_BACKEND_EVICT_PIPE_CLOCK_EN = 0x00000039,
13229CB_PERF_SEL_BACKEND_FRAGOP_CLOCK_EN = 0x0000003a,
13230CB_PERF_SEL_BACKEND_SRC_FIFO_CLOCK_EN = 0x0000003b,
13231CB_PERF_SEL_BACKEND_CACHE_CTL_CLOCK_EN = 0x0000003c,
13232CB_PERF_SEL_FRONTEND_INPUT_CLOCK_EN = 0x0000003d,
13233CB_PERF_SEL_FRONTEND_ADDR_CLOCK_EN = 0x0000003e,
13234CB_PERF_SEL_FRONTEND_FDCC_CLOCK_EN = 0x0000003f,
13235CB_PERF_SEL_FRONTEND_SAMPLE_MASK_TRACKER_CLOCK_EN = 0x00000040,
13236CB_PERF_SEL_RESERVED_65 = 0x00000041,
13237CB_PERF_SEL_RESERVED_66 = 0x00000042,
13238CB_PERF_SEL_RESERVED_67 = 0x00000043,
13239CB_PERF_SEL_RESERVED_68 = 0x00000044,
13240CB_PERF_SEL_RESERVED_69 = 0x00000045,
13241CB_PERF_SEL_RESERVED_70 = 0x00000046,
13242CB_PERF_SEL_RESERVED_71 = 0x00000047,
13243CB_PERF_SEL_RESERVED_72 = 0x00000048,
13244CB_PERF_SEL_RESERVED_73 = 0x00000049,
13245CB_PERF_SEL_RESERVED_74 = 0x0000004a,
13246CB_PERF_SEL_RESERVED_75 = 0x0000004b,
13247CB_PERF_SEL_RESERVED_76 = 0x0000004c,
13248CB_PERF_SEL_RESERVED_77 = 0x0000004d,
13249CB_PERF_SEL_RESERVED_78 = 0x0000004e,
13250CB_PERF_SEL_RESERVED_79 = 0x0000004f,
13251CB_PERF_SEL_RESERVED_80 = 0x00000050,
13252CB_PERF_SEL_RESERVED_81 = 0x00000051,
13253CB_PERF_SEL_RESERVED_82 = 0x00000052,
13254CB_PERF_SEL_RESERVED_83 = 0x00000053,
13255CB_PERF_SEL_RESERVED_84 = 0x00000054,
13256CB_PERF_SEL_RESERVED_85 = 0x00000055,
13257CB_PERF_SEL_RESERVED_86 = 0x00000056,
13258CB_PERF_SEL_RESERVED_87 = 0x00000057,
13259CB_PERF_SEL_RESERVED_88 = 0x00000058,
13260CB_PERF_SEL_RESERVED_89 = 0x00000059,
13261CB_PERF_SEL_RESERVED_90 = 0x0000005a,
13262CB_PERF_SEL_RESERVED_91 = 0x0000005b,
13263CB_PERF_SEL_RESERVED_92 = 0x0000005c,
13264CB_PERF_SEL_RESERVED_93 = 0x0000005d,
13265CB_PERF_SEL_RESERVED_94 = 0x0000005e,
13266CB_PERF_SEL_RESERVED_95 = 0x0000005f,
13267CB_PERF_SEL_RESERVED_96 = 0x00000060,
13268CB_PERF_SEL_RESERVED_97 = 0x00000061,
13269CB_PERF_SEL_RESERVED_98 = 0x00000062,
13270CB_PERF_SEL_RESERVED_99 = 0x00000063,
13271CB_PERF_SEL_CC_TAG_HIT = 0x00000064,
13272CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000065,
13273CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000066,
13274CB_PERF_SEL_CC_CACHE_SECTOR_HIT = 0x00000067,
13275CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x00000068,
13276CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000069,
13277CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000006a,
13278CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000006b,
13279CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x0000006c,
13280CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x0000006d,
13281CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x0000006e,
13282CB_PERF_SEL_CC_CACHE_STALL = 0x0000006f,
13283CB_PERF_SEL_CC_CACHE_FLUSH = 0x00000070,
13284CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x00000071,
13285CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x00000072,
13286CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x00000073,
13287CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x00000074,
13288CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x00000075,
13289CB_PERF_SEL_RESERVED_118 = 0x00000076,
13290CB_PERF_SEL_RESERVED_119 = 0x00000077,
13291CB_PERF_SEL_RESERVED_120 = 0x00000078,
13292CB_PERF_SEL_RESERVED_121 = 0x00000079,
13293CB_PERF_SEL_RESERVED_122 = 0x0000007a,
13294CB_PERF_SEL_RESERVED_123 = 0x0000007b,
13295CB_PERF_SEL_RESERVED_124 = 0x0000007c,
13296CB_PERF_SEL_RESERVED_125 = 0x0000007d,
13297CB_PERF_SEL_RESERVED_126 = 0x0000007e,
13298CB_PERF_SEL_RESERVED_127 = 0x0000007f,
13299CB_PERF_SEL_RESERVED_128 = 0x00000080,
13300CB_PERF_SEL_RESERVED_129 = 0x00000081,
13301CB_PERF_SEL_RESERVED_130 = 0x00000082,
13302CB_PERF_SEL_RESERVED_131 = 0x00000083,
13303CB_PERF_SEL_RESERVED_132 = 0x00000084,
13304CB_PERF_SEL_RESERVED_133 = 0x00000085,
13305CB_PERF_SEL_RESERVED_134 = 0x00000086,
13306CB_PERF_SEL_RESERVED_135 = 0x00000087,
13307CB_PERF_SEL_RESERVED_136 = 0x00000088,
13308CB_PERF_SEL_RESERVED_137 = 0x00000089,
13309CB_PERF_SEL_RESERVED_138 = 0x0000008a,
13310CB_PERF_SEL_RESERVED_139 = 0x0000008b,
13311CB_PERF_SEL_RESERVED_140 = 0x0000008c,
13312CB_PERF_SEL_RESERVED_141 = 0x0000008d,
13313CB_PERF_SEL_RESERVED_142 = 0x0000008e,
13314CB_PERF_SEL_RESERVED_143 = 0x0000008f,
13315CB_PERF_SEL_RESERVED_144 = 0x00000090,
13316CB_PERF_SEL_RESERVED_145 = 0x00000091,
13317CB_PERF_SEL_RESERVED_146 = 0x00000092,
13318CB_PERF_SEL_RESERVED_147 = 0x00000093,
13319CB_PERF_SEL_RESERVED_148 = 0x00000094,
13320CB_PERF_SEL_RESERVED_149 = 0x00000095,
13321CB_PERF_SEL_DCC_CACHE_PERF_HIT = 0x00000096,
13322CB_PERF_SEL_DCC_CACHE_TAG_MISS = 0x00000097,
13323CB_PERF_SEL_DCC_CACHE_SECTOR_MISS = 0x00000098,
13324CB_PERF_SEL_DCC_CACHE_REEVICTION_STALL = 0x00000099,
13325CB_PERF_SEL_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x0000009a,
13326CB_PERF_SEL_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x0000009b,
13327CB_PERF_SEL_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x0000009c,
13328CB_PERF_SEL_DCC_CACHE_READ_OUTPUT_STALL = 0x0000009d,
13329CB_PERF_SEL_DCC_CACHE_WRITE_OUTPUT_STALL = 0x0000009e,
13330CB_PERF_SEL_DCC_CACHE_ACK_OUTPUT_STALL = 0x0000009f,
13331CB_PERF_SEL_DCC_CACHE_STALL = 0x000000a0,
13332CB_PERF_SEL_DCC_CACHE_FLUSH = 0x000000a1,
13333CB_PERF_SEL_DCC_CACHE_SECTORS_FLUSHED = 0x000000a2,
13334CB_PERF_SEL_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0x000000a3,
13335CB_PERF_SEL_DCC_CACHE_TAGS_FLUSHED = 0x000000a4,
13336CB_PERF_SEL_RESERVED_165 = 0x000000a5,
13337CB_PERF_SEL_RESERVED_166 = 0x000000a6,
13338CB_PERF_SEL_RESERVED_167 = 0x000000a7,
13339CB_PERF_SEL_RESERVED_168 = 0x000000a8,
13340CB_PERF_SEL_RESERVED_169 = 0x000000a9,
13341CB_PERF_SEL_RESERVED_170 = 0x000000aa,
13342CB_PERF_SEL_RESERVED_171 = 0x000000ab,
13343CB_PERF_SEL_RESERVED_172 = 0x000000ac,
13344CB_PERF_SEL_RESERVED_173 = 0x000000ad,
13345CB_PERF_SEL_RESERVED_174 = 0x000000ae,
13346CB_PERF_SEL_RESERVED_175 = 0x000000af,
13347CB_PERF_SEL_RESERVED_176 = 0x000000b0,
13348CB_PERF_SEL_RESERVED_177 = 0x000000b1,
13349CB_PERF_SEL_RESERVED_178 = 0x000000b2,
13350CB_PERF_SEL_RESERVED_179 = 0x000000b3,
13351CB_PERF_SEL_RESERVED_180 = 0x000000b4,
13352CB_PERF_SEL_RESERVED_181 = 0x000000b5,
13353CB_PERF_SEL_RESERVED_182 = 0x000000b6,
13354CB_PERF_SEL_RESERVED_183 = 0x000000b7,
13355CB_PERF_SEL_RESERVED_184 = 0x000000b8,
13356CB_PERF_SEL_RESERVED_185 = 0x000000b9,
13357CB_PERF_SEL_RESERVED_186 = 0x000000ba,
13358CB_PERF_SEL_RESERVED_187 = 0x000000bb,
13359CB_PERF_SEL_RESERVED_188 = 0x000000bc,
13360CB_PERF_SEL_RESERVED_189 = 0x000000bd,
13361CB_PERF_SEL_RESERVED_190 = 0x000000be,
13362CB_PERF_SEL_RESERVED_191 = 0x000000bf,
13363CB_PERF_SEL_RESERVED_192 = 0x000000c0,
13364CB_PERF_SEL_RESERVED_193 = 0x000000c1,
13365CB_PERF_SEL_RESERVED_194 = 0x000000c2,
13366CB_PERF_SEL_RESERVED_195 = 0x000000c3,
13367CB_PERF_SEL_RESERVED_196 = 0x000000c4,
13368CB_PERF_SEL_RESERVED_197 = 0x000000c5,
13369CB_PERF_SEL_RESERVED_198 = 0x000000c6,
13370CB_PERF_SEL_RESERVED_199 = 0x000000c7,
13371CB_PERF_SEL_BLEND_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000c8,
13372CB_PERF_SEL_BLEND_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000c9,
13373CB_PERF_SEL_BLEND_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000ca,
13374CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000cb,
13375CB_PERF_SEL_BLEND_STALL_AT_OUTPUT = 0x000000cc,
13376CB_PERF_SEL_RESERVED_205 = 0x000000cd,
13377CB_PERF_SEL_RESERVED_206 = 0x000000ce,
13378CB_PERF_SEL_RESERVED_207 = 0x000000cf,
13379CB_PERF_SEL_RESERVED_208 = 0x000000d0,
13380CB_PERF_SEL_RESERVED_209 = 0x000000d1,
13381CB_PERF_SEL_RESERVED_210 = 0x000000d2,
13382CB_PERF_SEL_RESERVED_211 = 0x000000d3,
13383CB_PERF_SEL_RESERVED_212 = 0x000000d4,
13384CB_PERF_SEL_RESERVED_213 = 0x000000d5,
13385CB_PERF_SEL_RESERVED_214 = 0x000000d6,
13386CB_PERF_SEL_RESERVED_215 = 0x000000d7,
13387CB_PERF_SEL_RESERVED_216 = 0x000000d8,
13388CB_PERF_SEL_RESERVED_217 = 0x000000d9,
13389CB_PERF_SEL_RESERVED_218 = 0x000000da,
13390CB_PERF_SEL_RESERVED_219 = 0x000000db,
13391CB_PERF_SEL_RESERVED_220 = 0x000000dc,
13392CB_PERF_SEL_RESERVED_221 = 0x000000dd,
13393CB_PERF_SEL_RESERVED_222 = 0x000000de,
13394CB_PERF_SEL_RESERVED_223 = 0x000000df,
13395CB_PERF_SEL_RESERVED_224 = 0x000000e0,
13396CB_PERF_SEL_RESERVED_225 = 0x000000e1,
13397CB_PERF_SEL_RESERVED_226 = 0x000000e2,
13398CB_PERF_SEL_RESERVED_227 = 0x000000e3,
13399CB_PERF_SEL_RESERVED_228 = 0x000000e4,
13400CB_PERF_SEL_RESERVED_229 = 0x000000e5,
13401CB_PERF_SEL_RESERVED_230 = 0x000000e6,
13402CB_PERF_SEL_RESERVED_231 = 0x000000e7,
13403CB_PERF_SEL_RESERVED_232 = 0x000000e8,
13404CB_PERF_SEL_RESERVED_233 = 0x000000e9,
13405CB_PERF_SEL_RESERVED_234 = 0x000000ea,
13406CB_PERF_SEL_RESERVED_235 = 0x000000eb,
13407CB_PERF_SEL_RESERVED_236 = 0x000000ec,
13408CB_PERF_SEL_RESERVED_237 = 0x000000ed,
13409CB_PERF_SEL_RESERVED_238 = 0x000000ee,
13410CB_PERF_SEL_RESERVED_239 = 0x000000ef,
13411CB_PERF_SEL_RESERVED_240 = 0x000000f0,
13412CB_PERF_SEL_RESERVED_241 = 0x000000f1,
13413CB_PERF_SEL_RESERVED_242 = 0x000000f2,
13414CB_PERF_SEL_RESERVED_243 = 0x000000f3,
13415CB_PERF_SEL_RESERVED_244 = 0x000000f4,
13416CB_PERF_SEL_RESERVED_245 = 0x000000f5,
13417CB_PERF_SEL_RESERVED_246 = 0x000000f6,
13418CB_PERF_SEL_RESERVED_247 = 0x000000f7,
13419CB_PERF_SEL_RESERVED_248 = 0x000000f8,
13420CB_PERF_SEL_RESERVED_249 = 0x000000f9,
13421CB_PERF_SEL_EVENT = 0x000000fa,
13422CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x000000fb,
13423CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x000000fc,
13424CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x000000fd,
13425CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x000000fe,
13426CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x000000ff,
13427CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x00000100,
13428CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x00000101,
13429CB_PERF_SEL_CC_SURFACE_SYNC = 0x00000102,
13430CB_PERF_SEL_RESERVED_259 = 0x00000103,
13431CB_PERF_SEL_RESERVED_260 = 0x00000104,
13432CB_PERF_SEL_RESERVED_261 = 0x00000105,
13433CB_PERF_SEL_RESERVED_262 = 0x00000106,
13434CB_PERF_SEL_RESERVED_263 = 0x00000107,
13435CB_PERF_SEL_RESERVED_264 = 0x00000108,
13436CB_PERF_SEL_RESERVED_265 = 0x00000109,
13437CB_PERF_SEL_RESERVED_266 = 0x0000010a,
13438CB_PERF_SEL_RESERVED_267 = 0x0000010b,
13439CB_PERF_SEL_RESERVED_268 = 0x0000010c,
13440CB_PERF_SEL_RESERVED_269 = 0x0000010d,
13441CB_PERF_SEL_RESERVED_270 = 0x0000010e,
13442CB_PERF_SEL_RESERVED_271 = 0x0000010f,
13443CB_PERF_SEL_RESERVED_272 = 0x00000110,
13444CB_PERF_SEL_RESERVED_273 = 0x00000111,
13445CB_PERF_SEL_RESERVED_274 = 0x00000112,
13446CB_PERF_SEL_RESERVED_275 = 0x00000113,
13447CB_PERF_SEL_RESERVED_276 = 0x00000114,
13448CB_PERF_SEL_RESERVED_277 = 0x00000115,
13449CB_PERF_SEL_RESERVED_278 = 0x00000116,
13450CB_PERF_SEL_RESERVED_279 = 0x00000117,
13451CB_PERF_SEL_RESERVED_280 = 0x00000118,
13452CB_PERF_SEL_RESERVED_281 = 0x00000119,
13453CB_PERF_SEL_RESERVED_282 = 0x0000011a,
13454CB_PERF_SEL_RESERVED_283 = 0x0000011b,
13455CB_PERF_SEL_RESERVED_284 = 0x0000011c,
13456CB_PERF_SEL_RESERVED_285 = 0x0000011d,
13457CB_PERF_SEL_RESERVED_286 = 0x0000011e,
13458CB_PERF_SEL_RESERVED_287 = 0x0000011f,
13459CB_PERF_SEL_RESERVED_288 = 0x00000120,
13460CB_PERF_SEL_RESERVED_289 = 0x00000121,
13461CB_PERF_SEL_RESERVED_290 = 0x00000122,
13462CB_PERF_SEL_RESERVED_291 = 0x00000123,
13463CB_PERF_SEL_RESERVED_292 = 0x00000124,
13464CB_PERF_SEL_RESERVED_293 = 0x00000125,
13465CB_PERF_SEL_RESERVED_294 = 0x00000126,
13466CB_PERF_SEL_RESERVED_295 = 0x00000127,
13467CB_PERF_SEL_RESERVED_296 = 0x00000128,
13468CB_PERF_SEL_RESERVED_297 = 0x00000129,
13469CB_PERF_SEL_RESERVED_298 = 0x0000012a,
13470CB_PERF_SEL_RESERVED_299 = 0x0000012b,
13471CB_PERF_SEL_NACK_CC_READ = 0x0000012c,
13472CB_PERF_SEL_NACK_CC_WRITE = 0x0000012d,
13473CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0x0000012e,
13474CB_PERF_SEL_RESERVED_303 = 0x0000012f,
13475CB_PERF_SEL_RESERVED_304 = 0x00000130,
13476CB_PERF_SEL_RESERVED_305 = 0x00000131,
13477CB_PERF_SEL_RESERVED_306 = 0x00000132,
13478CB_PERF_SEL_RESERVED_307 = 0x00000133,
13479CB_PERF_SEL_RESERVED_308 = 0x00000134,
13480CB_PERF_SEL_RESERVED_309 = 0x00000135,
13481CB_PERF_SEL_RESERVED_310 = 0x00000136,
13482CB_PERF_SEL_RESERVED_311 = 0x00000137,
13483CB_PERF_SEL_RESERVED_312 = 0x00000138,
13484CB_PERF_SEL_RESERVED_313 = 0x00000139,
13485CB_PERF_SEL_RESERVED_314 = 0x0000013a,
13486CB_PERF_SEL_RESERVED_315 = 0x0000013b,
13487CB_PERF_SEL_RESERVED_316 = 0x0000013c,
13488CB_PERF_SEL_RESERVED_317 = 0x0000013d,
13489CB_PERF_SEL_RESERVED_318 = 0x0000013e,
13490CB_PERF_SEL_RESERVED_319 = 0x0000013f,
13491CB_PERF_SEL_RESERVED_320 = 0x00000140,
13492CB_PERF_SEL_RESERVED_321 = 0x00000141,
13493CB_PERF_SEL_RESERVED_322 = 0x00000142,
13494CB_PERF_SEL_RESERVED_323 = 0x00000143,
13495CB_PERF_SEL_RESERVED_324 = 0x00000144,
13496CB_PERF_SEL_RESERVED_325 = 0x00000145,
13497CB_PERF_SEL_RESERVED_326 = 0x00000146,
13498CB_PERF_SEL_RESERVED_327 = 0x00000147,
13499CB_PERF_SEL_RESERVED_328 = 0x00000148,
13500CB_PERF_SEL_RESERVED_329 = 0x00000149,
13501CB_PERF_SEL_RESERVED_330 = 0x0000014a,
13502CB_PERF_SEL_RESERVED_331 = 0x0000014b,
13503CB_PERF_SEL_RESERVED_332 = 0x0000014c,
13504CB_PERF_SEL_RESERVED_333 = 0x0000014d,
13505CB_PERF_SEL_RESERVED_334 = 0x0000014e,
13506CB_PERF_SEL_RESERVED_335 = 0x0000014f,
13507CB_PERF_SEL_RESERVED_336 = 0x00000150,
13508CB_PERF_SEL_RESERVED_337 = 0x00000151,
13509CB_PERF_SEL_RESERVED_338 = 0x00000152,
13510CB_PERF_SEL_RESERVED_339 = 0x00000153,
13511CB_PERF_SEL_RESERVED_340 = 0x00000154,
13512CB_PERF_SEL_RESERVED_341 = 0x00000155,
13513CB_PERF_SEL_RESERVED_342 = 0x00000156,
13514CB_PERF_SEL_RESERVED_343 = 0x00000157,
13515CB_PERF_SEL_RESERVED_344 = 0x00000158,
13516CB_PERF_SEL_RESERVED_345 = 0x00000159,
13517CB_PERF_SEL_RESERVED_346 = 0x0000015a,
13518CB_PERF_SEL_RESERVED_347 = 0x0000015b,
13519CB_PERF_SEL_RESERVED_348 = 0x0000015c,
13520CB_PERF_SEL_RESERVED_349 = 0x0000015d,
13521CB_PERF_SEL_RESERVED_350 = 0x0000015e,
13522CB_PERF_SEL_RESERVED_351 = 0x0000015f,
13523CB_PERF_SEL_RESERVED_352 = 0x00000160,
13524CB_PERF_SEL_RESERVED_353 = 0x00000161,
13525CB_PERF_SEL_RESERVED_354 = 0x00000162,
13526CB_PERF_SEL_RESERVED_355 = 0x00000163,
13527CB_PERF_SEL_RESERVED_356 = 0x00000164,
13528CB_PERF_SEL_RESERVED_357 = 0x00000165,
13529CB_PERF_SEL_RESERVED_358 = 0x00000166,
13530CB_PERF_SEL_RESERVED_359 = 0x00000167,
13531CB_PERF_SEL_RESERVED_360 = 0x00000168,
13532CB_PERF_SEL_RESERVED_361 = 0x00000169,
13533CB_PERF_SEL_RESERVED_362 = 0x0000016a,
13534CB_PERF_SEL_RESERVED_363 = 0x0000016b,
13535CB_PERF_SEL_RESERVED_364 = 0x0000016c,
13536CB_PERF_SEL_RESERVED_365 = 0x0000016d,
13537CB_PERF_SEL_RESERVED_366 = 0x0000016e,
13538CB_PERF_SEL_RESERVED_367 = 0x0000016f,
13539CB_PERF_SEL_RESERVED_368 = 0x00000170,
13540CB_PERF_SEL_RESERVED_369 = 0x00000171,
13541CB_PERF_SEL_RESERVED_370 = 0x00000172,
13542CB_PERF_SEL_RESERVED_371 = 0x00000173,
13543CB_PERF_SEL_RESERVED_372 = 0x00000174,
13544CB_PERF_SEL_RESERVED_373 = 0x00000175,
13545CB_PERF_SEL_RESERVED_374 = 0x00000176,
13546CB_PERF_SEL_RESERVED_375 = 0x00000177,
13547CB_PERF_SEL_RESERVED_376 = 0x00000178,
13548CB_PERF_SEL_RESERVED_377 = 0x00000179,
13549CB_PERF_SEL_RESERVED_378 = 0x0000017a,
13550CB_PERF_SEL_RESERVED_379 = 0x0000017b,
13551CB_PERF_SEL_RESERVED_380 = 0x0000017c,
13552CB_PERF_SEL_RESERVED_381 = 0x0000017d,
13553CB_PERF_SEL_RESERVED_382 = 0x0000017e,
13554CB_PERF_SEL_RESERVED_383 = 0x0000017f,
13555CB_PERF_SEL_RESERVED_384 = 0x00000180,
13556CB_PERF_SEL_RESERVED_385 = 0x00000181,
13557CB_PERF_SEL_RESERVED_386 = 0x00000182,
13558CB_PERF_SEL_RESERVED_387 = 0x00000183,
13559CB_PERF_SEL_RESERVED_388 = 0x00000184,
13560CB_PERF_SEL_RESERVED_389 = 0x00000185,
13561CB_PERF_SEL_RESERVED_390 = 0x00000186,
13562CB_PERF_SEL_RESERVED_391 = 0x00000187,
13563CB_PERF_SEL_RESERVED_392 = 0x00000188,
13564CB_PERF_SEL_RESERVED_393 = 0x00000189,
13565CB_PERF_SEL_RESERVED_394 = 0x0000018a,
13566CB_PERF_SEL_RESERVED_395 = 0x0000018b,
13567CB_PERF_SEL_RESERVED_396 = 0x0000018c,
13568CB_PERF_SEL_RESERVED_397 = 0x0000018d,
13569CB_PERF_SEL_RESERVED_398 = 0x0000018e,
13570CB_PERF_SEL_RESERVED_399 = 0x0000018f,
13571CB_PERF_SEL_RESERVED_400 = 0x00000190,
13572CB_PERF_SEL_RESERVED_401 = 0x00000191,
13573CB_PERF_SEL_RESERVED_402 = 0x00000192,
13574CB_PERF_SEL_RESERVED_403 = 0x00000193,
13575CB_PERF_SEL_RESERVED_404 = 0x00000194,
13576CB_PERF_SEL_RESERVED_405 = 0x00000195,
13577CB_PERF_SEL_RESERVED_406 = 0x00000196,
13578CB_PERF_SEL_RESERVED_407 = 0x00000197,
13579CB_PERF_SEL_RESERVED_408 = 0x00000198,
13580CB_PERF_SEL_RESERVED_409 = 0x00000199,
13581CB_PERF_SEL_RESERVED_410 = 0x0000019a,
13582CB_PERF_SEL_RESERVED_411 = 0x0000019b,
13583CB_PERF_SEL_RESERVED_412 = 0x0000019c,
13584CB_PERF_SEL_RESERVED_413 = 0x0000019d,
13585CB_PERF_SEL_RESERVED_414 = 0x0000019e,
13586CB_PERF_SEL_RESERVED_415 = 0x0000019f,
13587CB_PERF_SEL_RESERVED_416 = 0x000001a0,
13588CB_PERF_SEL_RESERVED_417 = 0x000001a1,
13589CB_PERF_SEL_RESERVED_418 = 0x000001a2,
13590CB_PERF_SEL_RESERVED_419 = 0x000001a3,
13591CB_PERF_SEL_RESERVED_420 = 0x000001a4,
13592CB_PERF_SEL_RESERVED_421 = 0x000001a5,
13593CB_PERF_SEL_RESERVED_422 = 0x000001a6,
13594CB_PERF_SEL_RESERVED_423 = 0x000001a7,
13595CB_PERF_SEL_RESERVED_424 = 0x000001a8,
13596CB_PERF_SEL_RESERVED_425 = 0x000001a9,
13597CB_PERF_SEL_RESERVED_426 = 0x000001aa,
13598CB_PERF_SEL_RESERVED_427 = 0x000001ab,
13599CB_PERF_SEL_RESERVED_428 = 0x000001ac,
13600CB_PERF_SEL_RESERVED_429 = 0x000001ad,
13601CB_PERF_SEL_RESERVED_430 = 0x000001ae,
13602CB_PERF_SEL_RESERVED_431 = 0x000001af,
13603CB_PERF_SEL_RESERVED_432 = 0x000001b0,
13604CB_PERF_SEL_RESERVED_433 = 0x000001b1,
13605CB_PERF_SEL_RESERVED_434 = 0x000001b2,
13606CB_PERF_SEL_RESERVED_435 = 0x000001b3,
13607CB_PERF_SEL_RESERVED_436 = 0x000001b4,
13608CB_PERF_SEL_RESERVED_437 = 0x000001b5,
13609CB_PERF_SEL_RESERVED_438 = 0x000001b6,
13610CB_PERF_SEL_RESERVED_439 = 0x000001b7,
13611CB_PERF_SEL_RESERVED_440 = 0x000001b8,
13612CB_PERF_SEL_RESERVED_441 = 0x000001b9,
13613CB_PERF_SEL_RESERVED_442 = 0x000001ba,
13614CB_PERF_SEL_RESERVED_443 = 0x000001bb,
13615CB_PERF_SEL_RESERVED_444 = 0x000001bc,
13616CB_PERF_SEL_RESERVED_445 = 0x000001bd,
13617CB_PERF_SEL_RESERVED_446 = 0x000001be,
13618CB_PERF_SEL_RESERVED_447 = 0x000001bf,
13619CB_PERF_SEL_RESERVED_448 = 0x000001c0,
13620CB_PERF_SEL_RESERVED_449 = 0x000001c1,
13621CB_PERF_SEL_RESERVED_450 = 0x000001c2,
13622CB_PERF_SEL_RESERVED_451 = 0x000001c3,
13623CB_PERF_SEL_RESERVED_452 = 0x000001c4,
13624CB_PERF_SEL_RESERVED_453 = 0x000001c5,
13625CB_PERF_SEL_RESERVED_454 = 0x000001c6,
13626CB_PERF_SEL_RESERVED_455 = 0x000001c7,
13627CB_PERF_SEL_RESERVED_456 = 0x000001c8,
13628CB_PERF_SEL_RESERVED_457 = 0x000001c9,
13629CB_PERF_SEL_RESERVED_458 = 0x000001ca,
13630CB_PERF_SEL_RESERVED_459 = 0x000001cb,
13631CB_PERF_SEL_RESERVED_460 = 0x000001cc,
13632CB_PERF_SEL_RESERVED_461 = 0x000001cd,
13633CB_PERF_SEL_RESERVED_462 = 0x000001ce,
13634CB_PERF_SEL_RESERVED_463 = 0x000001cf,
13635CB_PERF_SEL_RESERVED_464 = 0x000001d0,
13636CB_PERF_SEL_RESERVED_465 = 0x000001d1,
13637} CBPerfSel;
13638
13639/*
13640 * CBRamList enum
13641 */
13642
13643typedef enum CBRamList {
13644CB_DCG_CCC_CAS_TAG_ARRAY = 0x00000000,
13645CB_DCG_CCC_CAS_FRAG_PTR = 0x00000001,
13646CB_DCG_CCC_CAS_COLOR_PTR = 0x00000002,
13647CB_DCG_CCC_CAS_SURF_PARAM = 0x00000003,
13648CB_DCG_CCC_CAS_KEYID = 0x00000004,
13649CB_DCG_BACKEND_RDLAT_FIFO = 0x00000005,
13650CB_DCG_FRONTEND_RDLAT_FIFO = 0x00000006,
13651CB_DCG_SRC_FIFO = 0x00000007,
13652CB_DCG_COLOR_STORE = 0x00000008,
13653CB_DCG_COLOR_STORE_DIRTY_BYTE = 0x00000009,
13654CB_DCG_FMASK_CACHE_STORE = 0x0000000a,
13655CB_DCG_READ_SKID_FIFO = 0x0000000b,
13656CB_DCG_QUAD_PTR_FIFO = 0x0000000c,
13657CB_DCG_OUTPUT_FIFO = 0x0000000d,
13658CB_DCG_DCC_CACHE = 0x0000000e,
13659CB_DCG_DCC_DIRTY_BITS = 0x0000000f,
13660CB_DCG_QBLOCK_ALLOC = 0x00000010,
13661} CBRamList;
13662
13663/*
13664 * CmaskCode enum
13665 */
13666
13667typedef enum CmaskCode {
13668CMASK_CLR00_F0 = 0x00000000,
13669CMASK_CLR00_F1 = 0x00000001,
13670CMASK_CLR00_F2 = 0x00000002,
13671CMASK_CLR00_FX = 0x00000003,
13672CMASK_CLR01_F0 = 0x00000004,
13673CMASK_CLR01_F1 = 0x00000005,
13674CMASK_CLR01_F2 = 0x00000006,
13675CMASK_CLR01_FX = 0x00000007,
13676CMASK_CLR10_F0 = 0x00000008,
13677CMASK_CLR10_F1 = 0x00000009,
13678CMASK_CLR10_F2 = 0x0000000a,
13679CMASK_CLR10_FX = 0x0000000b,
13680CMASK_CLR11_F0 = 0x0000000c,
13681CMASK_CLR11_F1 = 0x0000000d,
13682CMASK_CLR11_F2 = 0x0000000e,
13683CMASK_CLR11_FX = 0x0000000f,
13684} CmaskCode;
13685
13686/*
13687 * CombFunc enum
13688 */
13689
13690typedef enum CombFunc {
13691COMB_DST_PLUS_SRC = 0x00000000,
13692COMB_SRC_MINUS_DST = 0x00000001,
13693COMB_MIN_DST_SRC = 0x00000002,
13694COMB_MAX_DST_SRC = 0x00000003,
13695COMB_DST_MINUS_SRC = 0x00000004,
13696} CombFunc;
13697
13698/*
13699 * MemArbMode enum
13700 */
13701
13702typedef enum MemArbMode {
13703MEM_ARB_MODE_FIXED = 0x00000000,
13704MEM_ARB_MODE_AGE = 0x00000001,
13705MEM_ARB_MODE_WEIGHT = 0x00000002,
13706MEM_ARB_MODE_BOTH = 0x00000003,
13707} MemArbMode;
13708
13709/*
13710 * SourceFormat enum
13711 */
13712
13713typedef enum SourceFormat {
13714EXPORT_4C_32BPC = 0x00000000,
13715EXPORT_4C_16BPC = 0x00000001,
13716EXPORT_2C_32BPC_GR = 0x00000002,
13717EXPORT_2C_32BPC_AR = 0x00000003,
13718} SourceFormat;
13719
13720/*******************************************************
13721 * SC Enums
13722 *******************************************************/
13723
13724/*
13725 * BinEventCntl enum
13726 */
13727
13728typedef enum BinEventCntl {
13729BINNER_BREAK_BATCH = 0x00000000,
13730BINNER_PIPELINE = 0x00000001,
13731BINNER_DROP = 0x00000002,
13732BINNER_PIPELINE_BREAK = 0x00000003,
13733} BinEventCntl;
13734
13735/*
13736 * BinMapMode enum
13737 */
13738
13739typedef enum BinMapMode {
13740BIN_MAP_MODE_NONE = 0x00000000,
13741BIN_MAP_MODE_RTA_INDEX = 0x00000001,
13742BIN_MAP_MODE_POPS = 0x00000002,
13743} BinMapMode;
13744
13745/*
13746 * BinSizeExtend enum
13747 */
13748
13749typedef enum BinSizeExtend {
13750BIN_SIZE_32_PIXELS = 0x00000000,
13751BIN_SIZE_64_PIXELS = 0x00000001,
13752BIN_SIZE_128_PIXELS = 0x00000002,
13753BIN_SIZE_256_PIXELS = 0x00000003,
13754BIN_SIZE_512_PIXELS = 0x00000004,
13755} BinSizeExtend;
13756
13757/*
13758 * BinningMode enum
13759 */
13760
13761typedef enum BinningMode {
13762BINNING_ALLOWED = 0x00000000,
13763FORCE_BINNING_ON = 0x00000001,
13764DISABLE_BINNING_USE_NEW_SC = 0x00000002,
13765DISABLE_BINNING_USE_LEGACY_SC = 0x00000003,
13766} BinningMode;
13767
13768/*
13769 * CovToShaderSel enum
13770 */
13771
13772typedef enum CovToShaderSel {
13773INPUT_COVERAGE = 0x00000000,
13774INPUT_INNER_COVERAGE = 0x00000001,
13775INPUT_DEPTH_COVERAGE = 0x00000002,
13776RAW = 0x00000003,
13777} CovToShaderSel;
13778
13779/*
13780 * PkrMap enum
13781 */
13782
13783typedef enum PkrMap {
13784RASTER_CONFIG_PKR_MAP_0 = 0x00000000,
13785RASTER_CONFIG_PKR_MAP_1 = 0x00000001,
13786RASTER_CONFIG_PKR_MAP_2 = 0x00000002,
13787RASTER_CONFIG_PKR_MAP_3 = 0x00000003,
13788} PkrMap;
13789
13790/*
13791 * PkrXsel enum
13792 */
13793
13794typedef enum PkrXsel {
13795RASTER_CONFIG_PKR_XSEL_0 = 0x00000000,
13796RASTER_CONFIG_PKR_XSEL_1 = 0x00000001,
13797RASTER_CONFIG_PKR_XSEL_2 = 0x00000002,
13798RASTER_CONFIG_PKR_XSEL_3 = 0x00000003,
13799} PkrXsel;
13800
13801/*
13802 * PkrXsel2 enum
13803 */
13804
13805typedef enum PkrXsel2 {
13806RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000,
13807RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001,
13808RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002,
13809RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003,
13810} PkrXsel2;
13811
13812/*
13813 * PkrYsel enum
13814 */
13815
13816typedef enum PkrYsel {
13817RASTER_CONFIG_PKR_YSEL_0 = 0x00000000,
13818RASTER_CONFIG_PKR_YSEL_1 = 0x00000001,
13819RASTER_CONFIG_PKR_YSEL_2 = 0x00000002,
13820RASTER_CONFIG_PKR_YSEL_3 = 0x00000003,
13821} PkrYsel;
13822
13823/*
13824 * RbMap enum
13825 */
13826
13827typedef enum RbMap {
13828RASTER_CONFIG_RB_MAP_0 = 0x00000000,
13829RASTER_CONFIG_RB_MAP_1 = 0x00000001,
13830RASTER_CONFIG_RB_MAP_2 = 0x00000002,
13831RASTER_CONFIG_RB_MAP_3 = 0x00000003,
13832} RbMap;
13833
13834/*
13835 * RbXsel enum
13836 */
13837
13838typedef enum RbXsel {
13839RASTER_CONFIG_RB_XSEL_0 = 0x00000000,
13840RASTER_CONFIG_RB_XSEL_1 = 0x00000001,
13841} RbXsel;
13842
13843/*
13844 * RbXsel2 enum
13845 */
13846
13847typedef enum RbXsel2 {
13848RASTER_CONFIG_RB_XSEL2_0 = 0x00000000,
13849RASTER_CONFIG_RB_XSEL2_1 = 0x00000001,
13850RASTER_CONFIG_RB_XSEL2_2 = 0x00000002,
13851RASTER_CONFIG_RB_XSEL2_3 = 0x00000003,
13852} RbXsel2;
13853
13854/*
13855 * RbYsel enum
13856 */
13857
13858typedef enum RbYsel {
13859RASTER_CONFIG_RB_YSEL_0 = 0x00000000,
13860RASTER_CONFIG_RB_YSEL_1 = 0x00000001,
13861} RbYsel;
13862
13863/*
13864 * SC_PERFCNT_SEL enum
13865 */
13866
13867typedef enum SC_PERFCNT_SEL {
13868SC_SRPS_WINDOW_VALID = 0x00000000,
13869SC_PSSW_WINDOW_VALID = 0x00000001,
13870SC_TPQZ_WINDOW_VALID = 0x00000002,
13871SC_QZQP_WINDOW_VALID = 0x00000003,
13872SC_TRPK_WINDOW_VALID = 0x00000004,
13873SC_SRPS_WINDOW_VALID_BUSY = 0x00000005,
13874SC_PSSW_WINDOW_VALID_BUSY = 0x00000006,
13875SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007,
13876SC_QZQP_WINDOW_VALID_BUSY = 0x00000008,
13877SC_TRPK_WINDOW_VALID_BUSY = 0x00000009,
13878SC_STARVED_BY_PA = 0x0000000a,
13879SC_STALLED_BY_PRIMFIFO = 0x0000000b,
13880SC_STALLED_BY_DB_TILE = 0x0000000c,
13881SC_STARVED_BY_DB_TILE = 0x0000000d,
13882SC_STALLED_BY_TILEORDERFIFO = 0x0000000e,
13883SC_STALLED_BY_TILEFIFO = 0x0000000f,
13884SC_STALLED_BY_DB_QUAD = 0x00000010,
13885SC_STARVED_BY_DB_QUAD = 0x00000011,
13886SC_STALLED_BY_QUADFIFO = 0x00000012,
13887SC_STALLED_BY_BCI = 0x00000013,
13888SC_STALLED_BY_SPI = 0x00000014,
13889SC_SCISSOR_DISCARD = 0x00000015,
13890SC_BB_DISCARD = 0x00000016,
13891SC_SUPERTILE_COUNT = 0x00000017,
13892SC_SUPERTILE_PER_PRIM_H0 = 0x00000018,
13893SC_SUPERTILE_PER_PRIM_H1 = 0x00000019,
13894SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a,
13895SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b,
13896SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c,
13897SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d,
13898SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e,
13899SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f,
13900SC_SUPERTILE_PER_PRIM_H8 = 0x00000020,
13901SC_SUPERTILE_PER_PRIM_H9 = 0x00000021,
13902SC_SUPERTILE_PER_PRIM_H10 = 0x00000022,
13903SC_SUPERTILE_PER_PRIM_H11 = 0x00000023,
13904SC_SUPERTILE_PER_PRIM_H12 = 0x00000024,
13905SC_SUPERTILE_PER_PRIM_H13 = 0x00000025,
13906SC_SUPERTILE_PER_PRIM_H14 = 0x00000026,
13907SC_SUPERTILE_PER_PRIM_H15 = 0x00000027,
13908SC_SUPERTILE_PER_PRIM_H16 = 0x00000028,
13909SC_TILE_PER_PRIM_H0 = 0x00000029,
13910SC_TILE_PER_PRIM_H1 = 0x0000002a,
13911SC_TILE_PER_PRIM_H2 = 0x0000002b,
13912SC_TILE_PER_PRIM_H3 = 0x0000002c,
13913SC_TILE_PER_PRIM_H4 = 0x0000002d,
13914SC_TILE_PER_PRIM_H5 = 0x0000002e,
13915SC_TILE_PER_PRIM_H6 = 0x0000002f,
13916SC_TILE_PER_PRIM_H7 = 0x00000030,
13917SC_TILE_PER_PRIM_H8 = 0x00000031,
13918SC_TILE_PER_PRIM_H9 = 0x00000032,
13919SC_TILE_PER_PRIM_H10 = 0x00000033,
13920SC_TILE_PER_PRIM_H11 = 0x00000034,
13921SC_TILE_PER_PRIM_H12 = 0x00000035,
13922SC_TILE_PER_PRIM_H13 = 0x00000036,
13923SC_TILE_PER_PRIM_H14 = 0x00000037,
13924SC_TILE_PER_PRIM_H15 = 0x00000038,
13925SC_TILE_PER_PRIM_H16 = 0x00000039,
13926SC_TILE_PER_SUPERTILE_H0 = 0x0000003a,
13927SC_TILE_PER_SUPERTILE_H1 = 0x0000003b,
13928SC_TILE_PER_SUPERTILE_H2 = 0x0000003c,
13929SC_TILE_PER_SUPERTILE_H3 = 0x0000003d,
13930SC_TILE_PER_SUPERTILE_H4 = 0x0000003e,
13931SC_TILE_PER_SUPERTILE_H5 = 0x0000003f,
13932SC_TILE_PER_SUPERTILE_H6 = 0x00000040,
13933SC_TILE_PER_SUPERTILE_H7 = 0x00000041,
13934SC_TILE_PER_SUPERTILE_H8 = 0x00000042,
13935SC_TILE_PER_SUPERTILE_H9 = 0x00000043,
13936SC_TILE_PER_SUPERTILE_H10 = 0x00000044,
13937SC_TILE_PER_SUPERTILE_H11 = 0x00000045,
13938SC_TILE_PER_SUPERTILE_H12 = 0x00000046,
13939SC_TILE_PER_SUPERTILE_H13 = 0x00000047,
13940SC_TILE_PER_SUPERTILE_H14 = 0x00000048,
13941SC_TILE_PER_SUPERTILE_H15 = 0x00000049,
13942SC_TILE_PER_SUPERTILE_H16 = 0x0000004a,
13943SC_TILE_PICKED_H1 = 0x0000004b,
13944SC_TILE_PICKED_H2 = 0x0000004c,
13945SC_TILE_PICKED_H3 = 0x0000004d,
13946SC_TILE_PICKED_H4 = 0x0000004e,
13947SC_QZ0_TILE_COUNT = 0x0000004f,
13948SC_QZ1_TILE_COUNT = 0x00000050,
13949SC_QZ2_TILE_COUNT = 0x00000051,
13950SC_QZ3_TILE_COUNT = 0x00000052,
13951SC_QZ0_TILE_COVERED_COUNT = 0x00000053,
13952SC_QZ1_TILE_COVERED_COUNT = 0x00000054,
13953SC_QZ2_TILE_COVERED_COUNT = 0x00000055,
13954SC_QZ3_TILE_COVERED_COUNT = 0x00000056,
13955SC_QZ0_TILE_NOT_COVERED_COUNT = 0x00000057,
13956SC_QZ1_TILE_NOT_COVERED_COUNT = 0x00000058,
13957SC_QZ2_TILE_NOT_COVERED_COUNT = 0x00000059,
13958SC_QZ3_TILE_NOT_COVERED_COUNT = 0x0000005a,
13959SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005b,
13960SC_QZ0_QUAD_PER_TILE_H1 = 0x0000005c,
13961SC_QZ0_QUAD_PER_TILE_H2 = 0x0000005d,
13962SC_QZ0_QUAD_PER_TILE_H3 = 0x0000005e,
13963SC_QZ0_QUAD_PER_TILE_H4 = 0x0000005f,
13964SC_QZ0_QUAD_PER_TILE_H5 = 0x00000060,
13965SC_QZ0_QUAD_PER_TILE_H6 = 0x00000061,
13966SC_QZ0_QUAD_PER_TILE_H7 = 0x00000062,
13967SC_QZ0_QUAD_PER_TILE_H8 = 0x00000063,
13968SC_QZ0_QUAD_PER_TILE_H9 = 0x00000064,
13969SC_QZ0_QUAD_PER_TILE_H10 = 0x00000065,
13970SC_QZ0_QUAD_PER_TILE_H11 = 0x00000066,
13971SC_QZ0_QUAD_PER_TILE_H12 = 0x00000067,
13972SC_QZ0_QUAD_PER_TILE_H13 = 0x00000068,
13973SC_QZ0_QUAD_PER_TILE_H14 = 0x00000069,
13974SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006a,
13975SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006b,
13976SC_QZ1_QUAD_PER_TILE_H0 = 0x0000006c,
13977SC_QZ1_QUAD_PER_TILE_H1 = 0x0000006d,
13978SC_QZ1_QUAD_PER_TILE_H2 = 0x0000006e,
13979SC_QZ1_QUAD_PER_TILE_H3 = 0x0000006f,
13980SC_QZ1_QUAD_PER_TILE_H4 = 0x00000070,
13981SC_QZ1_QUAD_PER_TILE_H5 = 0x00000071,
13982SC_QZ1_QUAD_PER_TILE_H6 = 0x00000072,
13983SC_QZ1_QUAD_PER_TILE_H7 = 0x00000073,
13984SC_QZ1_QUAD_PER_TILE_H8 = 0x00000074,
13985SC_QZ1_QUAD_PER_TILE_H9 = 0x00000075,
13986SC_QZ1_QUAD_PER_TILE_H10 = 0x00000076,
13987SC_QZ1_QUAD_PER_TILE_H11 = 0x00000077,
13988SC_QZ1_QUAD_PER_TILE_H12 = 0x00000078,
13989SC_QZ1_QUAD_PER_TILE_H13 = 0x00000079,
13990SC_QZ1_QUAD_PER_TILE_H14 = 0x0000007a,
13991SC_QZ1_QUAD_PER_TILE_H15 = 0x0000007b,
13992SC_QZ1_QUAD_PER_TILE_H16 = 0x0000007c,
13993SC_QZ2_QUAD_PER_TILE_H0 = 0x0000007d,
13994SC_QZ2_QUAD_PER_TILE_H1 = 0x0000007e,
13995SC_QZ2_QUAD_PER_TILE_H2 = 0x0000007f,
13996SC_QZ2_QUAD_PER_TILE_H3 = 0x00000080,
13997SC_QZ2_QUAD_PER_TILE_H4 = 0x00000081,
13998SC_QZ2_QUAD_PER_TILE_H5 = 0x00000082,
13999SC_QZ2_QUAD_PER_TILE_H6 = 0x00000083,
14000SC_QZ2_QUAD_PER_TILE_H7 = 0x00000084,
14001SC_QZ2_QUAD_PER_TILE_H8 = 0x00000085,
14002SC_QZ2_QUAD_PER_TILE_H9 = 0x00000086,
14003SC_QZ2_QUAD_PER_TILE_H10 = 0x00000087,
14004SC_QZ2_QUAD_PER_TILE_H11 = 0x00000088,
14005SC_QZ2_QUAD_PER_TILE_H12 = 0x00000089,
14006SC_QZ2_QUAD_PER_TILE_H13 = 0x0000008a,
14007SC_QZ2_QUAD_PER_TILE_H14 = 0x0000008b,
14008SC_QZ2_QUAD_PER_TILE_H15 = 0x0000008c,
14009SC_QZ2_QUAD_PER_TILE_H16 = 0x0000008d,
14010SC_QZ3_QUAD_PER_TILE_H0 = 0x0000008e,
14011SC_QZ3_QUAD_PER_TILE_H1 = 0x0000008f,
14012SC_QZ3_QUAD_PER_TILE_H2 = 0x00000090,
14013SC_QZ3_QUAD_PER_TILE_H3 = 0x00000091,
14014SC_QZ3_QUAD_PER_TILE_H4 = 0x00000092,
14015SC_QZ3_QUAD_PER_TILE_H5 = 0x00000093,
14016SC_QZ3_QUAD_PER_TILE_H6 = 0x00000094,
14017SC_QZ3_QUAD_PER_TILE_H7 = 0x00000095,
14018SC_QZ3_QUAD_PER_TILE_H8 = 0x00000096,
14019SC_QZ3_QUAD_PER_TILE_H9 = 0x00000097,
14020SC_QZ3_QUAD_PER_TILE_H10 = 0x00000098,
14021SC_QZ3_QUAD_PER_TILE_H11 = 0x00000099,
14022SC_QZ3_QUAD_PER_TILE_H12 = 0x0000009a,
14023SC_QZ3_QUAD_PER_TILE_H13 = 0x0000009b,
14024SC_QZ3_QUAD_PER_TILE_H14 = 0x0000009c,
14025SC_QZ3_QUAD_PER_TILE_H15 = 0x0000009d,
14026SC_QZ3_QUAD_PER_TILE_H16 = 0x0000009e,
14027SC_QZ0_QUAD_COUNT = 0x0000009f,
14028SC_QZ1_QUAD_COUNT = 0x000000a0,
14029SC_QZ2_QUAD_COUNT = 0x000000a1,
14030SC_QZ3_QUAD_COUNT = 0x000000a2,
14031SC_P0_HIZ_TILE_COUNT = 0x000000a3,
14032SC_P1_HIZ_TILE_COUNT = 0x000000a4,
14033SC_P2_HIZ_TILE_COUNT = 0x000000a5,
14034SC_P3_HIZ_TILE_COUNT = 0x000000a6,
14035SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000a7,
14036SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000a8,
14037SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000a9,
14038SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000aa,
14039SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000ab,
14040SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000ac,
14041SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000ad,
14042SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000ae,
14043SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000af,
14044SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b0,
14045SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b1,
14046SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b2,
14047SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b3,
14048SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b4,
14049SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b5,
14050SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000b6,
14051SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000b7,
14052SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x000000b8,
14053SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x000000b9,
14054SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x000000ba,
14055SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x000000bb,
14056SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x000000bc,
14057SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x000000bd,
14058SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x000000be,
14059SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x000000bf,
14060SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x000000c0,
14061SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x000000c1,
14062SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x000000c2,
14063SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x000000c3,
14064SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000000c4,
14065SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000000c5,
14066SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000000c6,
14067SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000000c7,
14068SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000000c8,
14069SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000000c9,
14070SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000000ca,
14071SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000000cb,
14072SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000000cc,
14073SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000000cd,
14074SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000000ce,
14075SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000000cf,
14076SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000000d0,
14077SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000000d1,
14078SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000000d2,
14079SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000000d3,
14080SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000000d4,
14081SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000000d5,
14082SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000000d6,
14083SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000000d7,
14084SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000000d8,
14085SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000000d9,
14086SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000000da,
14087SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000000db,
14088SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000000dc,
14089SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000000dd,
14090SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000000de,
14091SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000000df,
14092SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000000e0,
14093SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000000e1,
14094SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000000e2,
14095SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000000e3,
14096SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000000e4,
14097SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000000e5,
14098SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000000e6,
14099SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000000e7,
14100SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000000e8,
14101SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000000e9,
14102SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000000ea,
14103SC_P0_HIZ_QUAD_COUNT = 0x000000eb,
14104SC_P1_HIZ_QUAD_COUNT = 0x000000ec,
14105SC_P2_HIZ_QUAD_COUNT = 0x000000ed,
14106SC_P3_HIZ_QUAD_COUNT = 0x000000ee,
14107SC_P0_DETAIL_QUAD_COUNT = 0x000000ef,
14108SC_P1_DETAIL_QUAD_COUNT = 0x000000f0,
14109SC_P2_DETAIL_QUAD_COUNT = 0x000000f1,
14110SC_P3_DETAIL_QUAD_COUNT = 0x000000f2,
14111SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f3,
14112SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f4,
14113SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f5,
14114SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000f6,
14115SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000000f7,
14116SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000000f8,
14117SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000000f9,
14118SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000000fa,
14119SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000000fb,
14120SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x000000fc,
14121SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x000000fd,
14122SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x000000fe,
14123SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x000000ff,
14124SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x00000100,
14125SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x00000101,
14126SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x00000102,
14127SC_EARLYZ_QUAD_COUNT = 0x00000103,
14128SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000104,
14129SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000105,
14130SC_EARLYZ_QUAD_WITH_3_PIX = 0x00000106,
14131SC_EARLYZ_QUAD_WITH_4_PIX = 0x00000107,
14132SC_PKR_QUAD_PER_ROW_H1 = 0x00000108,
14133SC_PKR_QUAD_PER_ROW_H2 = 0x00000109,
14134SC_PKR_4X2_QUAD_SPLIT = 0x0000010a,
14135SC_PKR_4X2_FILL_QUAD = 0x0000010b,
14136SC_PKR_END_OF_VECTOR = 0x0000010c,
14137SC_PKR_CONTROL_XFER = 0x0000010d,
14138SC_PKR_DBHANG_FORCE_EOV = 0x0000010e,
14139SC_REG_SCLK_BUSY = 0x0000010f,
14140SC_GRP0_DYN_SCLK_BUSY = 0x00000110,
14141SC_GRP1_DYN_SCLK_BUSY = 0x00000111,
14142SC_GRP2_DYN_SCLK_BUSY = 0x00000112,
14143SC_GRP3_DYN_SCLK_BUSY = 0x00000113,
14144SC_GRP4_DYN_SCLK_BUSY = 0x00000114,
14145SC_PA0_SC_DATA_FIFO_RD = 0x00000115,
14146SC_PA0_SC_DATA_FIFO_WE = 0x00000116,
14147SC_PA1_SC_DATA_FIFO_RD = 0x00000117,
14148SC_PA1_SC_DATA_FIFO_WE = 0x00000118,
14149SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000119,
14150SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011a,
14151SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011b,
14152SC_PS_ARB_STALLED_FROM_BELOW = 0x0000011c,
14153SC_PS_ARB_STARVED_FROM_ABOVE = 0x0000011d,
14154SC_PS_ARB_SC_BUSY = 0x0000011e,
14155SC_PS_ARB_PA_SC_BUSY = 0x0000011f,
14156SC_PA2_SC_DATA_FIFO_RD = 0x00000120,
14157SC_PA2_SC_DATA_FIFO_WE = 0x00000121,
14158SC_PA3_SC_DATA_FIFO_RD = 0x00000122,
14159SC_PA3_SC_DATA_FIFO_WE = 0x00000123,
14160SC_PA_SC_DEALLOC_0_0_WE = 0x00000124,
14161SC_PA_SC_DEALLOC_0_1_WE = 0x00000125,
14162SC_PA_SC_DEALLOC_1_0_WE = 0x00000126,
14163SC_PA_SC_DEALLOC_1_1_WE = 0x00000127,
14164SC_PA_SC_DEALLOC_2_0_WE = 0x00000128,
14165SC_PA_SC_DEALLOC_2_1_WE = 0x00000129,
14166SC_PA_SC_DEALLOC_3_0_WE = 0x0000012a,
14167SC_PA_SC_DEALLOC_3_1_WE = 0x0000012b,
14168SC_PA0_SC_EOP_WE = 0x0000012c,
14169SC_PA0_SC_EOPG_WE = 0x0000012d,
14170SC_PA0_SC_EVENT_WE = 0x0000012e,
14171SC_PA1_SC_EOP_WE = 0x0000012f,
14172SC_PA1_SC_EOPG_WE = 0x00000130,
14173SC_PA1_SC_EVENT_WE = 0x00000131,
14174SC_PA2_SC_EOP_WE = 0x00000132,
14175SC_PA2_SC_EOPG_WE = 0x00000133,
14176SC_PA2_SC_EVENT_WE = 0x00000134,
14177SC_PA3_SC_EOP_WE = 0x00000135,
14178SC_PA3_SC_EOPG_WE = 0x00000136,
14179SC_PA3_SC_EVENT_WE = 0x00000137,
14180SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x00000138,
14181SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x00000139,
14182SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x0000013a,
14183SC_PS_ARB_EOP_POP_SYNC_POP = 0x0000013b,
14184SC_PS_ARB_EVENT_SYNC_POP = 0x0000013c,
14185SC_PS_ENG_MULTICYCLE_BUBBLE = 0x0000013d,
14186SC_PA0_SC_FPOV_WE = 0x0000013e,
14187SC_PA1_SC_FPOV_WE = 0x0000013f,
14188SC_PA2_SC_FPOV_WE = 0x00000140,
14189SC_PA3_SC_FPOV_WE = 0x00000141,
14190SC_PA0_SC_LPOV_WE = 0x00000142,
14191SC_PA1_SC_LPOV_WE = 0x00000143,
14192SC_PA2_SC_LPOV_WE = 0x00000144,
14193SC_PA3_SC_LPOV_WE = 0x00000145,
14194SC_SPI_DEALLOC_0_0 = 0x00000146,
14195SC_SPI_DEALLOC_0_1 = 0x00000147,
14196SC_SPI_DEALLOC_0_2 = 0x00000148,
14197SC_SPI_DEALLOC_1_0 = 0x00000149,
14198SC_SPI_DEALLOC_1_1 = 0x0000014a,
14199SC_SPI_DEALLOC_1_2 = 0x0000014b,
14200SC_SPI_DEALLOC_2_0 = 0x0000014c,
14201SC_SPI_DEALLOC_2_1 = 0x0000014d,
14202SC_SPI_DEALLOC_2_2 = 0x0000014e,
14203SC_SPI_DEALLOC_3_0 = 0x0000014f,
14204SC_SPI_DEALLOC_3_1 = 0x00000150,
14205SC_SPI_DEALLOC_3_2 = 0x00000151,
14206SC_SPI_FPOV_0 = 0x00000152,
14207SC_SPI_FPOV_1 = 0x00000153,
14208SC_SPI_FPOV_2 = 0x00000154,
14209SC_SPI_FPOV_3 = 0x00000155,
14210SC_SPI_EVENT = 0x00000156,
14211SC_PS_TS_EVENT_FIFO_PUSH = 0x00000157,
14212SC_PS_TS_EVENT_FIFO_POP = 0x00000158,
14213SC_PS_CTX_DONE_FIFO_PUSH = 0x00000159,
14214SC_PS_CTX_DONE_FIFO_POP = 0x0000015a,
14215SC_MULTICYCLE_BUBBLE_FREEZE = 0x0000015b,
14216SC_EOP_SYNC_WINDOW = 0x0000015c,
14217SC_PA0_SC_NULL_WE = 0x0000015d,
14218SC_PA0_SC_NULL_DEALLOC_WE = 0x0000015e,
14219SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x0000015f,
14220SC_PA0_SC_DATA_FIFO_EOP_RD = 0x00000160,
14221SC_PA0_SC_DEALLOC_0_RD = 0x00000161,
14222SC_PA0_SC_DEALLOC_1_RD = 0x00000162,
14223SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x00000163,
14224SC_PA1_SC_DATA_FIFO_EOP_RD = 0x00000164,
14225SC_PA1_SC_DEALLOC_0_RD = 0x00000165,
14226SC_PA1_SC_DEALLOC_1_RD = 0x00000166,
14227SC_PA1_SC_NULL_WE = 0x00000167,
14228SC_PA1_SC_NULL_DEALLOC_WE = 0x00000168,
14229SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x00000169,
14230SC_PA2_SC_DATA_FIFO_EOP_RD = 0x0000016a,
14231SC_PA2_SC_DEALLOC_0_RD = 0x0000016b,
14232SC_PA2_SC_DEALLOC_1_RD = 0x0000016c,
14233SC_PA2_SC_NULL_WE = 0x0000016d,
14234SC_PA2_SC_NULL_DEALLOC_WE = 0x0000016e,
14235SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x0000016f,
14236SC_PA3_SC_DATA_FIFO_EOP_RD = 0x00000170,
14237SC_PA3_SC_DEALLOC_0_RD = 0x00000171,
14238SC_PA3_SC_DEALLOC_1_RD = 0x00000172,
14239SC_PA3_SC_NULL_WE = 0x00000173,
14240SC_PA3_SC_NULL_DEALLOC_WE = 0x00000174,
14241SC_PS_PA0_SC_FIFO_EMPTY = 0x00000175,
14242SC_PS_PA0_SC_FIFO_FULL = 0x00000176,
14243SC_RESERVED_0 = 0x00000177,
14244SC_PS_PA1_SC_FIFO_EMPTY = 0x00000178,
14245SC_PS_PA1_SC_FIFO_FULL = 0x00000179,
14246SC_RESERVED_1 = 0x0000017a,
14247SC_PS_PA2_SC_FIFO_EMPTY = 0x0000017b,
14248SC_PS_PA2_SC_FIFO_FULL = 0x0000017c,
14249SC_RESERVED_2 = 0x0000017d,
14250SC_PS_PA3_SC_FIFO_EMPTY = 0x0000017e,
14251SC_PS_PA3_SC_FIFO_FULL = 0x0000017f,
14252SC_RESERVED_3 = 0x00000180,
14253SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000181,
14254SC_BUSY_CNT_NOT_ZERO = 0x00000182,
14255SC_BM_BUSY = 0x00000183,
14256SC_BACKEND_BUSY = 0x00000184,
14257SC_SCF_SCB_INTERFACE_BUSY = 0x00000185,
14258SC_SCB_BUSY = 0x00000186,
14259SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x00000187,
14260SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x00000188,
14261SC_PBB_BIN_HIST_NUM_PRIMS = 0x00000189,
14262SC_PBB_BATCH_HIST_NUM_PRIMS = 0x0000018a,
14263SC_PBB_BIN_HIST_NUM_CONTEXTS = 0x0000018b,
14264SC_PBB_BATCH_HIST_NUM_CONTEXTS = 0x0000018c,
14265SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 0x0000018d,
14266SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 0x0000018e,
14267SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 0x0000018f,
14268SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000190,
14269SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 0x00000191,
14270SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 0x00000192,
14271SC_PBB_BUSY = 0x00000193,
14272SC_PBB_BUSY_AND_NO_SENDS = 0x00000194,
14273SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 0x00000195,
14274SC_PBB_NUM_BINS = 0x00000196,
14275SC_PBB_END_OF_BIN = 0x00000197,
14276SC_PBB_END_OF_BATCH = 0x00000198,
14277SC_PBB_PRIMBIN_PROCESSED = 0x00000199,
14278SC_PBB_PRIM_ADDED_TO_BATCH = 0x0000019a,
14279SC_PBB_NONBINNED_PRIM = 0x0000019b,
14280SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 0x0000019c,
14281SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 0x0000019d,
14282SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x0000019e,
14283SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x0000019f,
14284SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a0,
14285SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a1,
14286SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 0x000001a2,
14287SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 0x000001a3,
14288SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 0x000001a4,
14289SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 0x000001a5,
14290SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 0x000001a6,
14291SC_POPS_INTRA_WAVE_OVERLAPS = 0x000001a7,
14292SC_POPS_FORCE_EOV = 0x000001a8,
14293SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 0x000001a9,
14294SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 0x000001aa,
14295SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 0x000001ab,
14296SC_FULL_FULL_QUAD = 0x000001ac,
14297SC_FULL_HALF_QUAD = 0x000001ad,
14298SC_FULL_QTR_QUAD = 0x000001ae,
14299SC_HALF_FULL_QUAD = 0x000001af,
14300SC_HALF_HALF_QUAD = 0x000001b0,
14301SC_HALF_QTR_QUAD = 0x000001b1,
14302SC_QTR_FULL_QUAD = 0x000001b2,
14303SC_QTR_HALF_QUAD = 0x000001b3,
14304SC_QTR_QTR_QUAD = 0x000001b4,
14305SC_GRP5_DYN_SCLK_BUSY = 0x000001b5,
14306SC_GRP6_DYN_SCLK_BUSY = 0x000001b6,
14307SC_GRP7_DYN_SCLK_BUSY = 0x000001b7,
14308SC_GRP8_DYN_SCLK_BUSY = 0x000001b8,
14309SC_GRP9_DYN_SCLK_BUSY = 0x000001b9,
14310SC_PS_TO_BE_SCLK_GATE_STALL = 0x000001ba,
14311SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 0x000001bb,
14312SC_PK_BUSY = 0x000001bc,
14313SC_PK_MAX_DEALLOC_FORCE_EOV = 0x000001bd,
14314SC_PK_DEALLOC_WAVE_BREAK = 0x000001be,
14315SC_SPI_SEND = 0x000001bf,
14316SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c0,
14317SC_SPI_CREDIT_AT_MAX = 0x000001c1,
14318SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c2,
14319SC_BCI_SEND = 0x000001c3,
14320SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c4,
14321SC_BCI_CREDIT_AT_MAX = 0x000001c5,
14322SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c6,
14323SC_SPIBC_FULL_FREEZE = 0x000001c7,
14324SC_PW_BM_PASS_EMPTY_PRIM = 0x000001c8,
14325SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 0x000001c9,
14326SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 0x000001ca,
14327SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 0x000001cb,
14328SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 0x000001cc,
14329SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 0x000001cd,
14330SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 0x000001ce,
14331SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 0x000001cf,
14332SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 0x000001d0,
14333SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 0x000001d1,
14334SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 0x000001d2,
14335SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 0x000001d3,
14336SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 0x000001d4,
14337SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 0x000001d5,
14338SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 0x000001d6,
14339SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 0x000001d7,
14340SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 0x000001d8,
14341SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 0x000001d9,
14342SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 0x000001da,
14343SC_DB0_TILE_INTERFACE_BUSY = 0x000001db,
14344SC_DB0_TILE_INTERFACE_SEND = 0x000001dc,
14345SC_DB0_TILE_INTERFACE_SEND_EVENT = 0x000001dd,
14346SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001de,
14347SC_DB0_TILE_INTERFACE_SEND_SOP = 0x000001df,
14348SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e0,
14349SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e1,
14350SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001e2,
14351SC_DB1_TILE_INTERFACE_BUSY = 0x000001e3,
14352SC_DB1_TILE_INTERFACE_SEND = 0x000001e4,
14353SC_DB1_TILE_INTERFACE_SEND_EVENT = 0x000001e5,
14354SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001e6,
14355SC_DB1_TILE_INTERFACE_SEND_SOP = 0x000001e7,
14356SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e8,
14357SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e9,
14358SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001ea,
14359SC_BACKEND_PRIM_FIFO_FULL = 0x000001eb,
14360SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 0x000001ec,
14361SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 0x000001ed,
14362SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 0x000001ee,
14363SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 0x000001ef,
14364SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 0x000001f0,
14365SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 0x000001f1,
14366SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 0x000001f2,
14367SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 0x000001f3,
14368SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 0x000001f4,
14369SC_PBB_BATCH_BREAK_DUE_TO_PIPE_RESET = 0x000001f5,
14370SC_PBB_BATCH_BREAK_DUE_TO_GFX_PIPE_CHANGE = 0x000001f6,
14371SC_STALLED_BY_DB0_TILEFIFO = 0x000001f7,
14372SC_DB0_QUAD_INTF_SEND = 0x000001f8,
14373SC_DB0_QUAD_INTF_BUSY = 0x000001f9,
14374SC_DB0_QUAD_INTF_STALLED_BY_DB = 0x000001fa,
14375SC_DB0_QUAD_INTF_CREDIT_AT_MAX = 0x000001fb,
14376SC_DB0_QUAD_INTF_IDLE = 0x000001fc,
14377SC_DB1_QUAD_INTF_SEND = 0x000001fd,
14378SC_STALLED_BY_DB1_TILEFIFO = 0x000001fe,
14379SC_DB1_QUAD_INTF_BUSY = 0x000001ff,
14380SC_DB1_QUAD_INTF_STALLED_BY_DB = 0x00000200,
14381SC_DB1_QUAD_INTF_CREDIT_AT_MAX = 0x00000201,
14382SC_DB1_QUAD_INTF_IDLE = 0x00000202,
14383SC_PKR_WAVE_BREAK_OUTSIDE_REGION = 0x00000203,
14384SC_PKR_WAVE_BREAK_FULL_TILE = 0x00000204,
14385SC_FSR_WALKED = 0x00000205,
14386SC_PBB_EMPTY_INPUT_CYCLE_WHEN_BATCH_OPEN = 0x00000206,
14387SC_PBB_BATCH_BREAK_DUE_TO_NULL_PRIM_BREAK_BATCH_LIMIT = 0x00000207,
14388SC_DB0_WE_STALLED_BY_RSLT_FIFO_FULL = 0x00000208,
14389SC_DB0_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 0x00000209,
14390SC_DB0_TILE_MASK_FIFO_FULL = 0x0000020a,
14391SC_DB1_WE_STALLED_BY_RSLT_FIFO_FULL = 0x0000020b,
14392SC_DB1_WE_TILE_MASK_RETURN_FIFO_FULL_WITH_WE_RSLT_FIFO_STALL = 0x0000020c,
14393SC_DB1_TILE_MASK_FIFO_FULL = 0x0000020d,
14394SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PFF_PW_FULL = 0x0000020e,
14395SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_ZFF_PW_FULL = 0x0000020f,
14396SC_PS_PM_PBB_TO_PSE_FIFO_WE_STALL_BY_PBB_TO_PSE_FIFO_FULL = 0x00000210,
14397SC_PS_PM_PFF_PW_FULL = 0x00000211,
14398SC_PS_PM_ZFF_PW_FULL = 0x00000212,
14399SC_PS_PM_PBB_TO_PSE_FIFO_FULL = 0x00000213,
14400SC_PK_PM_QD1_FD_CONFLICT_WAVE_BRK_1H = 0x00000214,
14401SC_PK_PM_QD1_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 0x00000215,
14402SC_PK_PM_QD1_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 0x00000216,
14403SC_PK_PM_4X2_SPLIT_WAVE_BRK_1H = 0x00000217,
14404SC_PK_PM_PKR_FILL_4X2_WAVE_BRK_1H = 0x00000218,
14405SC_PK_PM_SPLIT_OR_FILL_4X2_WAVE_BRK_1H = 0x00000219,
14406SC_PK_PM_END_OF_VECTOR_WAVE_BRK_1H = 0x0000021a,
14407SC_PK_PM_LAST_AND_DEALLOC_WAVE_BRK_1H = 0x0000021b,
14408SC_PK_PM_CTL_ONLY_CMD_WAVE_BRK_1H = 0x0000021c,
14409SC_PK_PM_AVOID_DEALLOC_ADD_WAVE_BRK_1H = 0x0000021d,
14410SC_PK_PM_FD_CONFLICT_WAVE_BRK_1H = 0x0000021e,
14411SC_PK_PM_FORCE_PARTIAL_FOR_DEALLOC_WAVE_BRK_1H = 0x0000021f,
14412SC_PK_PM_AE_CONFLICT_WAVE_BRK_1H = 0x00000220,
14413SC_PK_PM_EOP_OR_LAD_WAVE_BRK_1H = 0x00000221,
14414SC_PK_PM_FULL_TILE_WAVE_BRK_1H = 0x00000222,
14415SC_PK_PM_POPS_FORCE_EOV_WAVE_BRK_1H = 0x00000223,
14416SC_PK_PM_MAX_DEALLOC_FORCE_EOV_WAVE_BRK_1H = 0x00000224,
14417SC_PK_PM_WAVE_BREAK_OUTSIDE_REGION_WAVE_BRK_1H = 0x00000225,
14418SC_PK_PM_MAX_CLK_CNT_FORCE_EOV_WAVE_BRK_1H = 0x00000226,
14419SC_PK_PM_MAX_REZ_CNT_FORCE_EOV_WAVE_BRK_1H = 0x00000227,
14420SC_PK_PM_VRS_RATE_X_00_Y_00_QUAD = 0x00000228,
14421SC_PK_PM_VRS_RATE_X_00_Y_01_QUAD = 0x00000229,
14422SC_PK_PM_VRS_RATE_X_00_Y_10_QUAD = 0x0000022a,
14423SC_PK_PM_VRS_RATE_X_00_Y_11_QUAD = 0x0000022b,
14424SC_PK_PM_VRS_RATE_X_01_Y_00_QUAD = 0x0000022c,
14425SC_PK_PM_VRS_RATE_X_01_Y_01_QUAD = 0x0000022d,
14426SC_PK_PM_VRS_RATE_X_01_Y_10_QUAD = 0x0000022e,
14427SC_PK_PM_VRS_RATE_X_01_Y_11_QUAD = 0x0000022f,
14428SC_PK_PM_VRS_RATE_X_10_Y_00_QUAD = 0x00000230,
14429SC_PK_PM_VRS_RATE_X_10_Y_01_QUAD = 0x00000231,
14430SC_PK_PM_VRS_RATE_X_10_Y_10_QUAD = 0x00000232,
14431SC_PK_PM_VRS_RATE_X_10_Y_11_QUAD = 0x00000233,
14432SC_PK_PM_VRS_RATE_X_11_Y_00_QUAD = 0x00000234,
14433SC_PK_PM_VRS_RATE_X_11_Y_01_QUAD = 0x00000235,
14434SC_PK_PM_VRS_RATE_X_11_Y_10_QUAD = 0x00000236,
14435SC_PK_PM_VRS_RATE_X_11_Y_11_QUAD = 0x00000237,
14436SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_MODE_CHANGE = 0x00000238,
14437SC_PBB_RESERVED = 0x00000239,
14438SC_BM_BE0_STALLED = 0x0000023a,
14439SC_BM_BE1_STALLED = 0x0000023b,
14440SC_BM_BE2_STALLED = 0x0000023c,
14441SC_BM_BE3_STALLED = 0x0000023d,
14442SC_BM_MULTI_ACCUM_1_BE_STALLED = 0x0000023e,
14443SC_BM_MULTI_ACCUM_2_BE_STALLED = 0x0000023f,
14444SC_BM_MULTI_ACCUM_3_BE_STALLED = 0x00000240,
14445SC_BM_MULTI_ACCUM_4_BE_STALLED = 0x00000241,
14446} SC_PERFCNT_SEL;
14447
14448/*
14449 * ScMap enum
14450 */
14451
14452typedef enum ScMap {
14453RASTER_CONFIG_SC_MAP_0 = 0x00000000,
14454RASTER_CONFIG_SC_MAP_1 = 0x00000001,
14455RASTER_CONFIG_SC_MAP_2 = 0x00000002,
14456RASTER_CONFIG_SC_MAP_3 = 0x00000003,
14457} ScMap;
14458
14459/*
14460 * ScUncertaintyRegionMode enum
14461 */
14462
14463typedef enum ScUncertaintyRegionMode {
14464SC_HALF_LSB = 0x00000000,
14465SC_LSB_ONE_SIDED = 0x00000001,
14466SC_LSB_TWO_SIDED = 0x00000002,
14467} ScUncertaintyRegionMode;
14468
14469/*
14470 * ScUncertaintyRegionMult enum
14471 */
14472
14473typedef enum ScUncertaintyRegionMult {
14474SC_UR_1X = 0x00000000,
14475SC_UR_2X = 0x00000001,
14476SC_UR_4X = 0x00000002,
14477SC_UR_8X = 0x00000003,
14478} ScUncertaintyRegionMult;
14479
14480/*
14481 * ScXsel enum
14482 */
14483
14484typedef enum ScXsel {
14485RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000,
14486RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001,
14487RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002,
14488RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003,
14489} ScXsel;
14490
14491/*
14492 * ScYsel enum
14493 */
14494
14495typedef enum ScYsel {
14496RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000,
14497RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001,
14498RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002,
14499RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003,
14500} ScYsel;
14501
14502/*
14503 * SeMap enum
14504 */
14505
14506typedef enum SeMap {
14507RASTER_CONFIG_SE_MAP_0 = 0x00000000,
14508RASTER_CONFIG_SE_MAP_1 = 0x00000001,
14509RASTER_CONFIG_SE_MAP_2 = 0x00000002,
14510RASTER_CONFIG_SE_MAP_3 = 0x00000003,
14511} SeMap;
14512
14513/*
14514 * SePairMap enum
14515 */
14516
14517typedef enum SePairMap {
14518RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000,
14519RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001,
14520RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002,
14521RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003,
14522} SePairMap;
14523
14524/*
14525 * SePairXsel enum
14526 */
14527
14528typedef enum SePairXsel {
14529RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000,
14530RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001,
14531RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002,
14532RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003,
14533} SePairXsel;
14534
14535/*
14536 * SePairYsel enum
14537 */
14538
14539typedef enum SePairYsel {
14540RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000,
14541RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001,
14542RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002,
14543RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003,
14544} SePairYsel;
14545
14546/*
14547 * SeXsel enum
14548 */
14549
14550typedef enum SeXsel {
14551RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000,
14552RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001,
14553RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002,
14554RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003,
14555} SeXsel;
14556
14557/*
14558 * SeYsel enum
14559 */
14560
14561typedef enum SeYsel {
14562RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000,
14563RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001,
14564RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002,
14565RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003,
14566} SeYsel;
14567
14568/*
14569 * VRSCombinerModeSC enum
14570 */
14571
14572typedef enum VRSCombinerModeSC {
14573SC_VRS_COMB_MODE_PASSTHRU = 0x00000000,
14574SC_VRS_COMB_MODE_OVERRIDE = 0x00000001,
14575SC_VRS_COMB_MODE_MIN = 0x00000002,
14576SC_VRS_COMB_MODE_MAX = 0x00000003,
14577SC_VRS_COMB_MODE_SATURATE = 0x00000004,
14578} VRSCombinerModeSC;
14579
14580/*
14581 * VRSrate enum
14582 */
14583
14584typedef enum VRSrate {
14585VRS_SHADING_RATE_1X1 = 0x00000000,
14586VRS_SHADING_RATE_1X2 = 0x00000001,
14587VRS_SHADING_RATE_UNDEFINED0 = 0x00000002,
14588VRS_SHADING_RATE_UNDEFINED1 = 0x00000003,
14589VRS_SHADING_RATE_2X1 = 0x00000004,
14590VRS_SHADING_RATE_2X2 = 0x00000005,
14591VRS_SHADING_RATE_2X4 = 0x00000006,
14592VRS_SHADING_RATE_UNDEFINED2 = 0x00000007,
14593VRS_SHADING_RATE_UNDEFINED3 = 0x00000008,
14594VRS_SHADING_RATE_4X2 = 0x00000009,
14595VRS_SHADING_RATE_4X4 = 0x0000000a,
14596VRS_SHADING_RATE_UNDEFINED4 = 0x0000000b,
14597VRS_SHADING_RATE_16X_SSAA = 0x0000000c,
14598VRS_SHADING_RATE_8X_SSAA = 0x0000000d,
14599VRS_SHADING_RATE_4X_SSAA = 0x0000000e,
14600VRS_SHADING_RATE_2X_SSAA = 0x0000000f,
14601} VRSrate;
14602
14603/*******************************************************
14604 * TC Enums
14605 *******************************************************/
14606
14607/*
14608 * TC_EA_CID enum
14609 */
14610
14611typedef enum TC_EA_CID {
14612TC_EA_CID_RT = 0x00000000,
14613TC_EA_CID_FMASK = 0x00000001,
14614TC_EA_CID_DCC = 0x00000002,
14615TC_EA_CID_TCPMETA = 0x00000003,
14616TC_EA_CID_Z = 0x00000004,
14617TC_EA_CID_STENCIL = 0x00000005,
14618TC_EA_CID_HTILE = 0x00000006,
14619TC_EA_CID_MISC = 0x00000007,
14620TC_EA_CID_TCP = 0x00000008,
14621TC_EA_CID_SQC = 0x00000009,
14622TC_EA_CID_CPF = 0x0000000a,
14623TC_EA_CID_CPG = 0x0000000b,
14624TC_EA_CID_IA = 0x0000000c,
14625TC_EA_CID_WD = 0x0000000d,
14626TC_EA_CID_PA = 0x0000000e,
14627TC_EA_CID_UTCL2_TPI = 0x0000000f,
14628} TC_EA_CID;
14629
14630/*
14631 * TC_NACKS enum
14632 */
14633
14634typedef enum TC_NACKS {
14635TC_NACK_NO_FAULT = 0x00000000,
14636TC_NACK_PAGE_FAULT = 0x00000001,
14637TC_NACK_PROTECTION_FAULT = 0x00000002,
14638TC_NACK_DATA_ERROR = 0x00000003,
14639} TC_NACKS;
14640
14641/*
14642 * TC_OP enum
14643 */
14644
14645typedef enum TC_OP {
14646TC_OP_READ = 0x00000000,
14647TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001,
14648TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002,
14649TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003,
14650TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004,
14651TC_OP_RESERVED_FADD_RTN_32 = 0x00000005,
14652TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006,
14653TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007,
14654TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008,
14655TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
14656TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a,
14657TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b,
14658TC_OP_PROBE_FILTER = 0x0000000c,
14659TC_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 0x0000000d,
14660TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
14661TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f,
14662TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010,
14663TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011,
14664TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012,
14665TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013,
14666TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014,
14667TC_OP_ATOMIC_AND_RTN_32 = 0x00000015,
14668TC_OP_ATOMIC_OR_RTN_32 = 0x00000016,
14669TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017,
14670TC_OP_ATOMIC_INC_RTN_32 = 0x00000018,
14671TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019,
14672TC_OP_WBINVL1_VOL = 0x0000001a,
14673TC_OP_WBINVL1_SD = 0x0000001b,
14674TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c,
14675TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d,
14676TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e,
14677TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f,
14678TC_OP_WRITE = 0x00000020,
14679TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021,
14680TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022,
14681TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023,
14682TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024,
14683TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025,
14684TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026,
14685TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027,
14686TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028,
14687TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
14688TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a,
14689TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b,
14690TC_OP_WBINVL2_SD = 0x0000002c,
14691TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d,
14692TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e,
14693TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f,
14694TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030,
14695TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031,
14696TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032,
14697TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033,
14698TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034,
14699TC_OP_ATOMIC_AND_RTN_64 = 0x00000035,
14700TC_OP_ATOMIC_OR_RTN_64 = 0x00000036,
14701TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037,
14702TC_OP_ATOMIC_INC_RTN_64 = 0x00000038,
14703TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039,
14704TC_OP_WBL2_NC = 0x0000003a,
14705TC_OP_WBL2_WC = 0x0000003b,
14706TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c,
14707TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d,
14708TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e,
14709TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f,
14710TC_OP_WBINVL1 = 0x00000040,
14711TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041,
14712TC_OP_ATOMIC_FMIN_32 = 0x00000042,
14713TC_OP_ATOMIC_FMAX_32 = 0x00000043,
14714TC_OP_RESERVED_FOP_32_0 = 0x00000044,
14715TC_OP_RESERVED_FADD_32 = 0x00000045,
14716TC_OP_RESERVED_FOP_32_2 = 0x00000046,
14717TC_OP_ATOMIC_SWAP_32 = 0x00000047,
14718TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048,
14719TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049,
14720TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a,
14721TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b,
14722TC_OP_INV_METADATA = 0x0000004c,
14723TC_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 0x0000004d,
14724TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e,
14725TC_OP_ATOMIC_ADD_32 = 0x0000004f,
14726TC_OP_ATOMIC_SUB_32 = 0x00000050,
14727TC_OP_ATOMIC_SMIN_32 = 0x00000051,
14728TC_OP_ATOMIC_UMIN_32 = 0x00000052,
14729TC_OP_ATOMIC_SMAX_32 = 0x00000053,
14730TC_OP_ATOMIC_UMAX_32 = 0x00000054,
14731TC_OP_ATOMIC_AND_32 = 0x00000055,
14732TC_OP_ATOMIC_OR_32 = 0x00000056,
14733TC_OP_ATOMIC_XOR_32 = 0x00000057,
14734TC_OP_ATOMIC_INC_32 = 0x00000058,
14735TC_OP_ATOMIC_DEC_32 = 0x00000059,
14736TC_OP_INVL2_NC = 0x0000005a,
14737TC_OP_NOP_RTN0 = 0x0000005b,
14738TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c,
14739TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d,
14740TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e,
14741TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f,
14742TC_OP_WBINVL2 = 0x00000060,
14743TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061,
14744TC_OP_ATOMIC_FMIN_64 = 0x00000062,
14745TC_OP_ATOMIC_FMAX_64 = 0x00000063,
14746TC_OP_RESERVED_FOP_64_0 = 0x00000064,
14747TC_OP_RESERVED_FOP_64_1 = 0x00000065,
14748TC_OP_RESERVED_FOP_64_2 = 0x00000066,
14749TC_OP_ATOMIC_SWAP_64 = 0x00000067,
14750TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068,
14751TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069,
14752TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a,
14753TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b,
14754TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c,
14755TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d,
14756TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e,
14757TC_OP_ATOMIC_ADD_64 = 0x0000006f,
14758TC_OP_ATOMIC_SUB_64 = 0x00000070,
14759TC_OP_ATOMIC_SMIN_64 = 0x00000071,
14760TC_OP_ATOMIC_UMIN_64 = 0x00000072,
14761TC_OP_ATOMIC_SMAX_64 = 0x00000073,
14762TC_OP_ATOMIC_UMAX_64 = 0x00000074,
14763TC_OP_ATOMIC_AND_64 = 0x00000075,
14764TC_OP_ATOMIC_OR_64 = 0x00000076,
14765TC_OP_ATOMIC_XOR_64 = 0x00000077,
14766TC_OP_ATOMIC_INC_64 = 0x00000078,
14767TC_OP_ATOMIC_DEC_64 = 0x00000079,
14768TC_OP_WBINVL2_NC = 0x0000007a,
14769TC_OP_NOP_ACK = 0x0000007b,
14770TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c,
14771TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d,
14772TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e,
14773TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f,
14774} TC_OP;
14775
14776/*
14777 * TC_OP_MASKS enum
14778 */
14779
14780typedef enum TC_OP_MASKS {
14781TC_OP_MASK_FLUSH_DENROM = 0x00000008,
14782TC_OP_MASK_64 = 0x00000020,
14783TC_OP_MASK_NO_RTN = 0x00000040,
14784} TC_OP_MASKS;
14785
14786/*******************************************************
14787 * GL2 Enums
14788 *******************************************************/
14789
14790/*
14791 * GL2_EA_CID enum
14792 */
14793
14794typedef enum GL2_EA_CID {
14795GL2_EA_CID_CLIENT = 0x00000000,
14796GL2_EA_CID_SDMA = 0x00000001,
14797GL2_EA_CID_RLC = 0x00000002,
14798GL2_EA_CID_SQC = 0x00000003,
14799GL2_EA_CID_CP = 0x00000004,
14800GL2_EA_CID_CPDMA = 0x00000005,
14801GL2_EA_CID_UTCL2 = 0x00000006,
14802GL2_EA_CID_RT = 0x00000007,
14803GL2_EA_CID_FMASK = 0x00000008,
14804GL2_EA_CID_DCC = 0x00000009,
14805GL2_EA_CID_Z_STENCIL = 0x0000000a,
14806GL2_EA_CID_ZPCPSD = 0x0000000b,
14807GL2_EA_CID_HTILE = 0x0000000c,
14808GL2_EA_CID_MES = 0x0000000d,
14809GL2_EA_CID_TCPMETA = 0x0000000f,
14810} GL2_EA_CID;
14811
14812/*
14813 * GL2_NACKS enum
14814 */
14815
14816typedef enum GL2_NACKS {
14817GL2_NACK_NO_FAULT = 0x00000000,
14818GL2_NACK_PAGE_FAULT = 0x00000001,
14819GL2_NACK_PROTECTION_FAULT = 0x00000002,
14820GL2_NACK_DATA_ERROR = 0x00000003,
14821} GL2_NACKS;
14822
14823/*
14824 * GL2_OP enum
14825 */
14826
14827typedef enum GL2_OP {
14828GL2_OP_READ = 0x00000000,
14829GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001,
14830GL2_OP_ATOMIC_FMIN_RTN_32 = 0x00000002,
14831GL2_OP_ATOMIC_FMAX_RTN_32 = 0x00000003,
14832GL2_OP_ATOMIC_SWAP_RTN_32 = 0x00000007,
14833GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008,
14834GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
14835GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a,
14836GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b,
14837GL2_OP_PROBE_FILTER = 0x0000000c,
14838GL2_OP_ATOMIC_FADD_FLUSH_DENORM_RTN_32 = 0x0000000d,
14839GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
14840GL2_OP_ATOMIC_ADD_RTN_32 = 0x0000000f,
14841GL2_OP_ATOMIC_SUB_RTN_32 = 0x00000010,
14842GL2_OP_ATOMIC_SMIN_RTN_32 = 0x00000011,
14843GL2_OP_ATOMIC_UMIN_RTN_32 = 0x00000012,
14844GL2_OP_ATOMIC_SMAX_RTN_32 = 0x00000013,
14845GL2_OP_ATOMIC_UMAX_RTN_32 = 0x00000014,
14846GL2_OP_ATOMIC_AND_RTN_32 = 0x00000015,
14847GL2_OP_ATOMIC_OR_RTN_32 = 0x00000016,
14848GL2_OP_ATOMIC_XOR_RTN_32 = 0x00000017,
14849GL2_OP_ATOMIC_INC_RTN_32 = 0x00000018,
14850GL2_OP_ATOMIC_DEC_RTN_32 = 0x00000019,
14851GL2_OP_ATOMIC_CLAMP_SUB_RTN_32 = 0x0000001a,
14852GL2_OP_WRITE = 0x00000020,
14853GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021,
14854GL2_OP_ATOMIC_FMIN_RTN_64 = 0x00000022,
14855GL2_OP_ATOMIC_FMAX_RTN_64 = 0x00000023,
14856GL2_OP_ATOMIC_SWAP_RTN_64 = 0x00000027,
14857GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028,
14858GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
14859GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a,
14860GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b,
14861GL2_OP_ATOMIC_ADD_RTN_64 = 0x0000002f,
14862GL2_OP_ATOMIC_SUB_RTN_64 = 0x00000030,
14863GL2_OP_ATOMIC_SMIN_RTN_64 = 0x00000031,
14864GL2_OP_ATOMIC_UMIN_RTN_64 = 0x00000032,
14865GL2_OP_ATOMIC_SMAX_RTN_64 = 0x00000033,
14866GL2_OP_ATOMIC_UMAX_RTN_64 = 0x00000034,
14867GL2_OP_ATOMIC_AND_RTN_64 = 0x00000035,
14868GL2_OP_ATOMIC_OR_RTN_64 = 0x00000036,
14869GL2_OP_ATOMIC_XOR_RTN_64 = 0x00000037,
14870GL2_OP_ATOMIC_INC_RTN_64 = 0x00000038,
14871GL2_OP_ATOMIC_DEC_RTN_64 = 0x00000039,
14872GL2_OP_GL1_INV = 0x00000040,
14873GL2_OP_ATOMIC_FCMPSWAP_32 = 0x00000041,
14874GL2_OP_ATOMIC_FMIN_32 = 0x00000042,
14875GL2_OP_ATOMIC_FMAX_32 = 0x00000043,
14876GL2_OP_ATOMIC_SWAP_32 = 0x00000047,
14877GL2_OP_ATOMIC_CMPSWAP_32 = 0x00000048,
14878GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049,
14879GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a,
14880GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b,
14881GL2_OP_ATOMIC_UMIN_8 = 0x0000004c,
14882GL2_OP_ATOMIC_FADD_FLUSH_DENORM_32 = 0x0000004d,
14883GL2_OP_ATOMIC_ADD_32 = 0x0000004f,
14884GL2_OP_ATOMIC_SUB_32 = 0x00000050,
14885GL2_OP_ATOMIC_SMIN_32 = 0x00000051,
14886GL2_OP_ATOMIC_UMIN_32 = 0x00000052,
14887GL2_OP_ATOMIC_SMAX_32 = 0x00000053,
14888GL2_OP_ATOMIC_UMAX_32 = 0x00000054,
14889GL2_OP_ATOMIC_AND_32 = 0x00000055,
14890GL2_OP_ATOMIC_OR_32 = 0x00000056,
14891GL2_OP_ATOMIC_XOR_32 = 0x00000057,
14892GL2_OP_ATOMIC_INC_32 = 0x00000058,
14893GL2_OP_ATOMIC_DEC_32 = 0x00000059,
14894GL2_OP_NOP_RTN0 = 0x0000005b,
14895GL2_OP_ATOMIC_FCMPSWAP_64 = 0x00000061,
14896GL2_OP_ATOMIC_FMIN_64 = 0x00000062,
14897GL2_OP_ATOMIC_FMAX_64 = 0x00000063,
14898GL2_OP_ATOMIC_SWAP_64 = 0x00000067,
14899GL2_OP_ATOMIC_CMPSWAP_64 = 0x00000068,
14900GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069,
14901GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a,
14902GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b,
14903GL2_OP_ATOMIC_ADD_64 = 0x0000006f,
14904GL2_OP_ATOMIC_SUB_64 = 0x00000070,
14905GL2_OP_ATOMIC_SMIN_64 = 0x00000071,
14906GL2_OP_ATOMIC_UMIN_64 = 0x00000072,
14907GL2_OP_ATOMIC_SMAX_64 = 0x00000073,
14908GL2_OP_ATOMIC_UMAX_64 = 0x00000074,
14909GL2_OP_ATOMIC_AND_64 = 0x00000075,
14910GL2_OP_ATOMIC_OR_64 = 0x00000076,
14911GL2_OP_ATOMIC_XOR_64 = 0x00000077,
14912GL2_OP_ATOMIC_INC_64 = 0x00000078,
14913GL2_OP_ATOMIC_DEC_64 = 0x00000079,
14914GL2_OP_ATOMIC_UMAX_8 = 0x0000007a,
14915GL2_OP_NOP_ACK = 0x0000007b,
14916} GL2_OP;
14917
14918/*
14919 * GL2_OP_MASKS enum
14920 */
14921
14922typedef enum GL2_OP_MASKS {
14923GL2_OP_MASK_FLUSH_DENROM = 0x00000008,
14924GL2_OP_MASK_64 = 0x00000020,
14925GL2_OP_MASK_NO_RTN = 0x00000040,
14926} GL2_OP_MASKS;
14927
14928/*******************************************************
14929 * RLC Enums
14930 *******************************************************/
14931
14932/*
14933 * RLC_DOORBELL_MODE enum
14934 */
14935
14936typedef enum RLC_DOORBELL_MODE {
14937RLC_DOORBELL_MODE_DISABLE = 0x00000000,
14938RLC_DOORBELL_MODE_ENABLE = 0x00000001,
14939RLC_DOORBELL_MODE_ENABLE_PF = 0x00000002,
14940RLC_DOORBELL_MODE_ENABLE_PF_VF = 0x00000003,
14941} RLC_DOORBELL_MODE;
14942
14943/*
14944 * RLC_PERFCOUNTER_SEL enum
14945 */
14946
14947typedef enum RLC_PERFCOUNTER_SEL {
14948RLC_PERF_SEL_POWER_FEATURE_0 = 0x00000000,
14949RLC_PERF_SEL_POWER_FEATURE_1 = 0x00000001,
14950RLC_PERF_SEL_CP_INTERRUPT = 0x00000002,
14951RLC_PERF_SEL_GRBM_INTERRUPT = 0x00000003,
14952RLC_PERF_SEL_SPM_INTERRUPT = 0x00000004,
14953RLC_PERF_SEL_IH_INTERRUPT = 0x00000005,
14954RLC_PERF_SEL_SERDES_COMMAND_WRITE = 0x00000006,
14955} RLC_PERFCOUNTER_SEL;
14956
14957/*
14958 * RLC_PERFMON_STATE enum
14959 */
14960
14961typedef enum RLC_PERFMON_STATE {
14962RLC_PERFMON_STATE_RESET = 0x00000000,
14963RLC_PERFMON_STATE_ENABLE = 0x00000001,
14964RLC_PERFMON_STATE_DISABLE = 0x00000002,
14965RLC_PERFMON_STATE_RESERVED_3 = 0x00000003,
14966RLC_PERFMON_STATE_RESERVED_4 = 0x00000004,
14967RLC_PERFMON_STATE_RESERVED_5 = 0x00000005,
14968RLC_PERFMON_STATE_RESERVED_6 = 0x00000006,
14969RLC_PERFMON_STATE_ROLLOVER = 0x00000007,
14970} RLC_PERFMON_STATE;
14971
14972/*
14973 * RSPM_CMD enum
14974 */
14975
14976typedef enum RSPM_CMD {
14977RSPM_CMD_INVALID = 0x00000000,
14978RSPM_CMD_IDLE = 0x00000001,
14979RSPM_CMD_CALIBRATE = 0x00000002,
14980RSPM_CMD_SPM_RESET = 0x00000003,
14981RSPM_CMD_SPM_START = 0x00000004,
14982RSPM_CMD_SPM_STOP = 0x00000005,
14983RSPM_CMD_PERF_RESET = 0x00000006,
14984RSPM_CMD_PERF_SAMPLE = 0x00000007,
14985RSPM_CMD_PROF_START = 0x00000008,
14986RSPM_CMD_PROF_STOP = 0x00000009,
14987RSPM_CMD_FORCE_SAMPLE = 0x0000000a,
14988} RSPM_CMD;
14989
14990/*******************************************************
14991 * SPI Enums
14992 *******************************************************/
14993
14994/*
14995 * CLKGATE_BASE_MODE enum
14996 */
14997
14998typedef enum CLKGATE_BASE_MODE {
14999MULT_8 = 0x00000000,
15000MULT_16 = 0x00000001,
15001} CLKGATE_BASE_MODE;
15002
15003/*
15004 * CLKGATE_SM_MODE enum
15005 */
15006
15007typedef enum CLKGATE_SM_MODE {
15008ON_SEQ = 0x00000000,
15009OFF_SEQ = 0x00000001,
15010PROG_SEQ = 0x00000002,
15011READ_SEQ = 0x00000003,
15012SM_MODE_RESERVED = 0x00000004,
15013} CLKGATE_SM_MODE;
15014
15015/*
15016 * SPI_FOG_MODE enum
15017 */
15018
15019typedef enum SPI_FOG_MODE {
15020SPI_FOG_NONE = 0x00000000,
15021SPI_FOG_EXP = 0x00000001,
15022SPI_FOG_EXP2 = 0x00000002,
15023SPI_FOG_LINEAR = 0x00000003,
15024} SPI_FOG_MODE;
15025
15026/*
15027 * SPI_LB_WAVES_SELECT enum
15028 */
15029
15030typedef enum SPI_LB_WAVES_SELECT {
15031HS_GS = 0x00000000,
15032PS = 0x00000001,
15033CS_NA = 0x00000002,
15034SPI_LB_WAVES_RSVD = 0x00000003,
15035} SPI_LB_WAVES_SELECT;
15036
15037/*
15038 * SPI_PERFCNT_SEL enum
15039 */
15040
15041typedef enum SPI_PERFCNT_SEL {
15042SPI_PERF_GS_WINDOW_VALID = 0x00000001,
15043SPI_PERF_GS_BUSY = 0x00000002,
15044SPI_PERF_GS_CRAWLER_STALL = 0x00000003,
15045SPI_PERF_GS_EVENT_WAVE = 0x00000004,
15046SPI_PERF_GS_WAVE = 0x00000005,
15047SPI_PERF_GS_PERS_UPD_FULL0 = 0x00000006,
15048SPI_PERF_GS_PERS_UPD_FULL1 = 0x00000007,
15049SPI_PERF_GS_FIRST_SUBGRP = 0x00000008,
15050SPI_PERF_GS_HS_DEALLOC = 0x00000009,
15051SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 0x0000000a,
15052SPI_PERF_GS_POS0_STALL = 0x0000000b,
15053SPI_PERF_GS_POS1_STALL = 0x0000000c,
15054SPI_PERF_GS_INDX0_STALL = 0x0000000d,
15055SPI_PERF_GS_INDX1_STALL = 0x0000000e,
15056SPI_PERF_GS_PWS_STALL = 0x0000000f,
15057SPI_PERF_HS_WINDOW_VALID = 0x00000015,
15058SPI_PERF_HS_BUSY = 0x00000016,
15059SPI_PERF_HS_CRAWLER_STALL = 0x00000017,
15060SPI_PERF_HS_FIRST_WAVE = 0x00000018,
15061SPI_PERF_HS_OFFCHIP_LDS_STALL = 0x00000019,
15062SPI_PERF_HS_EVENT_WAVE = 0x0000001a,
15063SPI_PERF_HS_WAVE = 0x0000001b,
15064SPI_PERF_HS_PERS_UPD_FULL0 = 0x0000001c,
15065SPI_PERF_HS_PERS_UPD_FULL1 = 0x0000001d,
15066SPI_PERF_HS_PWS_STALL = 0x0000001e,
15067SPI_PERF_CSGN_WINDOW_VALID = 0x00000025,
15068SPI_PERF_CSGN_BUSY = 0x00000026,
15069SPI_PERF_CSGN_NUM_THREADGROUPS = 0x00000027,
15070SPI_PERF_CSGN_CRAWLER_STALL = 0x00000028,
15071SPI_PERF_CSGN_EVENT_WAVE = 0x00000029,
15072SPI_PERF_CSGN_WAVE = 0x0000002a,
15073SPI_PERF_CSGN_PWS_STALL = 0x0000002b,
15074SPI_PERF_CSN_WINDOW_VALID = 0x0000002c,
15075SPI_PERF_CSN_BUSY = 0x0000002d,
15076SPI_PERF_CSN_NUM_THREADGROUPS = 0x0000002e,
15077SPI_PERF_CSN_CRAWLER_STALL = 0x0000002f,
15078SPI_PERF_CSN_EVENT_WAVE = 0x00000030,
15079SPI_PERF_CSN_WAVE = 0x00000031,
15080SPI_PERF_PS0_WINDOW_VALID = 0x00000035,
15081SPI_PERF_PS1_WINDOW_VALID = 0x00000036,
15082SPI_PERF_PS2_WINDOW_VALID = 0x00000037,
15083SPI_PERF_PS3_WINDOW_VALID = 0x00000038,
15084SPI_PERF_PS0_BUSY = 0x00000039,
15085SPI_PERF_PS1_BUSY = 0x0000003a,
15086SPI_PERF_PS2_BUSY = 0x0000003b,
15087SPI_PERF_PS3_BUSY = 0x0000003c,
15088SPI_PERF_PS0_ACTIVE = 0x0000003d,
15089SPI_PERF_PS1_ACTIVE = 0x0000003e,
15090SPI_PERF_PS2_ACTIVE = 0x0000003f,
15091SPI_PERF_PS3_ACTIVE = 0x00000040,
15092SPI_PERF_PS0_DEALLOC = 0x00000041,
15093SPI_PERF_PS1_DEALLOC = 0x00000042,
15094SPI_PERF_PS2_DEALLOC = 0x00000043,
15095SPI_PERF_PS3_DEALLOC = 0x00000044,
15096SPI_PERF_PS0_EVENT_WAVE = 0x00000045,
15097SPI_PERF_PS1_EVENT_WAVE = 0x00000046,
15098SPI_PERF_PS2_EVENT_WAVE = 0x00000047,
15099SPI_PERF_PS3_EVENT_WAVE = 0x00000048,
15100SPI_PERF_PS0_WAVE = 0x00000049,
15101SPI_PERF_PS1_WAVE = 0x0000004a,
15102SPI_PERF_PS2_WAVE = 0x0000004b,
15103SPI_PERF_PS3_WAVE = 0x0000004c,
15104SPI_PERF_PS0_OPT_WAVE = 0x0000004d,
15105SPI_PERF_PS1_OPT_WAVE = 0x0000004e,
15106SPI_PERF_PS2_OPT_WAVE = 0x0000004f,
15107SPI_PERF_PS3_OPT_WAVE = 0x00000050,
15108SPI_PERF_PS0_PRIM_BIN0 = 0x00000051,
15109SPI_PERF_PS1_PRIM_BIN0 = 0x00000052,
15110SPI_PERF_PS2_PRIM_BIN0 = 0x00000053,
15111SPI_PERF_PS3_PRIM_BIN0 = 0x00000054,
15112SPI_PERF_PS0_PRIM_BIN1 = 0x00000055,
15113SPI_PERF_PS1_PRIM_BIN1 = 0x00000056,
15114SPI_PERF_PS2_PRIM_BIN1 = 0x00000057,
15115SPI_PERF_PS3_PRIM_BIN1 = 0x00000058,
15116SPI_PERF_PS0_CRAWLER_STALL = 0x00000059,
15117SPI_PERF_PS1_CRAWLER_STALL = 0x0000005a,
15118SPI_PERF_PS2_CRAWLER_STALL = 0x0000005b,
15119SPI_PERF_PS3_CRAWLER_STALL = 0x0000005c,
15120SPI_PERF_PS_PERS_UPD_FULL0 = 0x0000005d,
15121SPI_PERF_PS_PERS_UPD_FULL1 = 0x0000005e,
15122SPI_PERF_PS0_2_WAVE_GROUPS = 0x0000005f,
15123SPI_PERF_PS1_2_WAVE_GROUPS = 0x00000060,
15124SPI_PERF_PS2_2_WAVE_GROUPS = 0x00000061,
15125SPI_PERF_PS3_2_WAVE_GROUPS = 0x00000062,
15126SPI_PERF_PS0_WAVE_GROUP_CLOCK_DELAY = 0x00000063,
15127SPI_PERF_PS1_WAVE_GROUP_CLOCK_DELAY = 0x00000064,
15128SPI_PERF_PS2_WAVE_GROUP_CLOCK_DELAY = 0x00000065,
15129SPI_PERF_PS3_WAVE_GROUP_CLOCK_DELAY = 0x00000066,
15130SPI_PERF_PS0_WAVE_GROUP_TIMEOUTS = 0x00000067,
15131SPI_PERF_PS1_WAVE_GROUP_TIMEOUTS = 0x00000068,
15132SPI_PERF_PS2_WAVE_GROUP_TIMEOUTS = 0x00000069,
15133SPI_PERF_PS3_WAVE_GROUP_TIMEOUTS = 0x0000006a,
15134SPI_PERF_PS_PWS_STALL = 0x0000006b,
15135SPI_PERF_RA_PIPE_REQ_BIN2 = 0x0000008d,
15136SPI_PERF_RA_TASK_REQ_BIN3 = 0x0000008e,
15137SPI_PERF_RA_WR_CTL_FULL = 0x0000008f,
15138SPI_PERF_RA_REQ_NO_ALLOC = 0x00000090,
15139SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x00000091,
15140SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x00000092,
15141SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x00000093,
15142SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x00000094,
15143SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x00000095,
15144SPI_PERF_RA_RES_STALL_PS = 0x00000096,
15145SPI_PERF_RA_RES_STALL_GS = 0x00000097,
15146SPI_PERF_RA_RES_STALL_HS = 0x00000098,
15147SPI_PERF_RA_RES_STALL_CSG = 0x00000099,
15148SPI_PERF_RA_RES_STALL_CSN = 0x0000009a,
15149SPI_PERF_RA_TMP_STALL_PS = 0x0000009b,
15150SPI_PERF_RA_TMP_STALL_GS = 0x0000009c,
15151SPI_PERF_RA_TMP_STALL_HS = 0x0000009d,
15152SPI_PERF_RA_TMP_STALL_CSG = 0x0000009e,
15153SPI_PERF_RA_TMP_STALL_CSN = 0x0000009f,
15154SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x000000a0,
15155SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x000000a1,
15156SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x000000a2,
15157SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x000000a3,
15158SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x000000a4,
15159SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x000000a5,
15160SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x000000a6,
15161SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x000000a7,
15162SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x000000a8,
15163SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x000000a9,
15164SPI_PERF_RA_LDS_CU_FULL_PS = 0x000000aa,
15165SPI_PERF_RA_LDS_CU_FULL_HS = 0x000000ab,
15166SPI_PERF_RA_LDS_CU_FULL_GS = 0x000000ac,
15167SPI_PERF_RA_LDS_CU_FULL_CSG = 0x000000ad,
15168SPI_PERF_RA_LDS_CU_FULL_CSN = 0x000000ae,
15169SPI_PERF_RA_BAR_CU_FULL_HS = 0x000000af,
15170SPI_PERF_RA_BAR_CU_FULL_CSG = 0x000000b0,
15171SPI_PERF_RA_BAR_CU_FULL_CSN = 0x000000b1,
15172SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x000000b2,
15173SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x000000b3,
15174SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x000000b4,
15175SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x000000b5,
15176SPI_PERF_RA_WVLIM_STALL_PS = 0x000000b6,
15177SPI_PERF_RA_WVLIM_STALL_GS = 0x000000b7,
15178SPI_PERF_RA_WVLIM_STALL_HS = 0x000000b8,
15179SPI_PERF_RA_WVLIM_STALL_CSG = 0x000000b9,
15180SPI_PERF_RA_WVLIM_STALL_CSN = 0x000000ba,
15181SPI_PERF_RA_GS_LOCK = 0x000000bb,
15182SPI_PERF_RA_HS_LOCK = 0x000000bc,
15183SPI_PERF_RA_CSG_LOCK = 0x000000bd,
15184SPI_PERF_RA_CSN_LOCK = 0x000000be,
15185SPI_PERF_RA_RSV_UPD = 0x000000bf,
15186SPI_PERF_RA_PRE_ALLOC_STALL = 0x000000c0,
15187SPI_PERF_RA_GFX_UNDER_TUNNEL = 0x000000c1,
15188SPI_PERF_RA_CSC_UNDER_TUNNEL = 0x000000c2,
15189SPI_PERF_RA_WVALLOC_STALL = 0x000000c3,
15190SPI_PERF_RA_ACCUM0_SIMD_FULL_PS = 0x000000c4,
15191SPI_PERF_RA_ACCUM1_SIMD_FULL_PS = 0x000000c5,
15192SPI_PERF_RA_ACCUM2_SIMD_FULL_PS = 0x000000c6,
15193SPI_PERF_RA_ACCUM3_SIMD_FULL_PS = 0x000000c7,
15194SPI_PERF_RA_ACCUM0_SIMD_FULL_GS = 0x000000c8,
15195SPI_PERF_RA_ACCUM1_SIMD_FULL_GS = 0x000000c9,
15196SPI_PERF_RA_ACCUM2_SIMD_FULL_GS = 0x000000ca,
15197SPI_PERF_RA_ACCUM3_SIMD_FULL_GS = 0x000000cb,
15198SPI_PERF_RA_ACCUM0_SIMD_FULL_HS = 0x000000cc,
15199SPI_PERF_RA_ACCUM1_SIMD_FULL_HS = 0x000000cd,
15200SPI_PERF_RA_ACCUM2_SIMD_FULL_HS = 0x000000ce,
15201SPI_PERF_RA_ACCUM3_SIMD_FULL_HS = 0x000000cf,
15202SPI_PERF_RA_ACCUM0_SIMD_FULL_CSG = 0x000000d0,
15203SPI_PERF_RA_ACCUM1_SIMD_FULL_CSG = 0x000000d1,
15204SPI_PERF_RA_ACCUM2_SIMD_FULL_CSG = 0x000000d2,
15205SPI_PERF_RA_ACCUM3_SIMD_FULL_CSG = 0x000000d3,
15206SPI_PERF_RA_ACCUM0_SIMD_FULL_CSN = 0x000000d4,
15207SPI_PERF_RA_ACCUM1_SIMD_FULL_CSN = 0x000000d5,
15208SPI_PERF_RA_ACCUM2_SIMD_FULL_CSN = 0x000000d6,
15209SPI_PERF_RA_ACCUM3_SIMD_FULL_CSN = 0x000000d7,
15210SPI_PERF_EXP_ARB_COL_CNT = 0x000000d8,
15211SPI_PERF_EXP_ARB_POS_CNT = 0x000000d9,
15212SPI_PERF_EXP_ARB_GDS_CNT = 0x000000da,
15213SPI_PERF_EXP_ARB_IDX_CNT = 0x000000db,
15214SPI_PERF_EXP_WITH_CONFLICT = 0x000000dc,
15215SPI_PERF_EXP_WITH_CONFLICT_CLEAR = 0x000000dd,
15216SPI_PERF_GS_EXP_DONE = 0x000000de,
15217SPI_PERF_PS_EXP_DONE = 0x000000df,
15218SPI_PERF_PS_EXP_ARB_CONFLICT = 0x000000e0,
15219SPI_PERF_PS_EXP_ALLOC = 0x000000e1,
15220SPI_PERF_PS0_WAVEID_STARVED = 0x000000e2,
15221SPI_PERF_PS1_WAVEID_STARVED = 0x000000e3,
15222SPI_PERF_PS2_WAVEID_STARVED = 0x000000e4,
15223SPI_PERF_PS3_WAVEID_STARVED = 0x000000e5,
15224SPI_PERF_PS0_EXP_ALLOC_WITH_CONFLICT = 0x000000e6,
15225SPI_PERF_PS1_EXP_ALLOC_WITH_CONFLICT = 0x000000e7,
15226SPI_PERF_PS2_EXP_ALLOC_WITH_CONFLICT = 0x000000e8,
15227SPI_PERF_PS3_EXP_ALLOC_WITH_CONFLICT = 0x000000e9,
15228SPI_PERF_NUM_PS_COL_SA0SQ0_EXPORTS = 0x000000ea,
15229SPI_PERF_NUM_PS_COL_SA0SQ1_EXPORTS = 0x000000eb,
15230SPI_PERF_NUM_PS_COL_SA1SQ0_EXPORTS = 0x000000ec,
15231SPI_PERF_NUM_PS_COL_SA1SQ1_EXPORTS = 0x000000ed,
15232SPI_PERF_NUM_POS_SA0SQ0_EXPORTS = 0x000000ee,
15233SPI_PERF_NUM_POS_SA0SQ1_EXPORTS = 0x000000ef,
15234SPI_PERF_NUM_POS_SA1SQ0_EXPORTS = 0x000000f0,
15235SPI_PERF_NUM_POS_SA1SQ1_EXPORTS = 0x000000f1,
15236SPI_PERF_NUM_GDS_SA0SQ0_EXPORTS = 0x000000f2,
15237SPI_PERF_NUM_GDS_SA0SQ1_EXPORTS = 0x000000f3,
15238SPI_PERF_NUM_GDS_SA1SQ0_EXPORTS = 0x000000f4,
15239SPI_PERF_NUM_GDS_SA1SQ1_EXPORTS = 0x000000f5,
15240SPI_PERF_NUM_EXPGRANT_EXPORTS = 0x000000f6,
15241SPI_PERF_PIX_ALLOC_PEND_CNT = 0x000000fd,
15242SPI_PERF_EXPORT_SCB0_STALL = 0x000000fe,
15243SPI_PERF_EXPORT_SCB1_STALL = 0x000000ff,
15244SPI_PERF_EXPORT_SCB2_STALL = 0x00000100,
15245SPI_PERF_EXPORT_SCB3_STALL = 0x00000101,
15246SPI_PERF_EXPORT_DB0_STALL = 0x00000102,
15247SPI_PERF_EXPORT_DB1_STALL = 0x00000103,
15248SPI_PERF_EXPORT_DB2_STALL = 0x00000104,
15249SPI_PERF_EXPORT_DB3_STALL = 0x00000105,
15250SPI_PERF_EXPORT_DB4_STALL = 0x00000106,
15251SPI_PERF_EXPORT_DB5_STALL = 0x00000107,
15252SPI_PERF_EXPORT_DB6_STALL = 0x00000108,
15253SPI_PERF_EXPORT_DB7_STALL = 0x00000109,
15254SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 0x0000010a,
15255SPI_PERF_GS_NGG_STALL_MSG_VAL = 0x0000010b,
15256SPI_PERF_SWC_PS_WR = 0x0000010c,
15257SPI_PERF_SWC_GS_WR = 0x0000010d,
15258SPI_PERF_SWC_HS_WR = 0x0000010e,
15259SPI_PERF_SWC_CSGN_WR = 0x0000010f,
15260SPI_PERF_SWC_CSN_WR = 0x00000110,
15261SPI_PERF_VWC_PS_WR = 0x00000111,
15262SPI_PERF_VWC_ES_WR = 0x00000112,
15263SPI_PERF_VWC_GS_WR = 0x00000113,
15264SPI_PERF_VWC_LS_WR = 0x00000114,
15265SPI_PERF_VWC_HS_WR = 0x00000115,
15266SPI_PERF_VWC_CSGN_WR = 0x00000116,
15267SPI_PERF_VWC_CSN_WR = 0x00000117,
15268SPI_PERF_EXP_THROT_UPSTEP = 0x00000118,
15269SPI_PERF_EXP_THROT_DOWNSTEP = 0x00000119,
15270SPI_PERF_EXP_THROT_CAUSALITY_DETECTED = 0x0000011a,
15271SPI_PERF_BUSY = 0x0000011b,
15272} SPI_PERFCNT_SEL;
15273
15274/*
15275 * SPI_PNT_SPRITE_OVERRIDE enum
15276 */
15277
15278typedef enum SPI_PNT_SPRITE_OVERRIDE {
15279SPI_PNT_SPRITE_SEL_0 = 0x00000000,
15280SPI_PNT_SPRITE_SEL_1 = 0x00000001,
15281SPI_PNT_SPRITE_SEL_S = 0x00000002,
15282SPI_PNT_SPRITE_SEL_T = 0x00000003,
15283SPI_PNT_SPRITE_SEL_NONE = 0x00000004,
15284} SPI_PNT_SPRITE_OVERRIDE;
15285
15286/*
15287 * SPI_PS_LDS_GROUP_SIZE enum
15288 */
15289
15290typedef enum SPI_PS_LDS_GROUP_SIZE {
15291SPI_PS_LDS_GROUP_1 = 0x00000000,
15292SPI_PS_LDS_GROUP_2 = 0x00000001,
15293SPI_PS_LDS_GROUP_4 = 0x00000002,
15294} SPI_PS_LDS_GROUP_SIZE;
15295
15296/*
15297 * SPI_SAMPLE_CNTL enum
15298 */
15299
15300typedef enum SPI_SAMPLE_CNTL {
15301CENTROIDS_ONLY = 0x00000000,
15302CENTERS_ONLY = 0x00000001,
15303CENTROIDS_AND_CENTERS = 0x00000002,
15304UNDEF = 0x00000003,
15305} SPI_SAMPLE_CNTL;
15306
15307/*
15308 * SPI_SHADER_EX_FORMAT enum
15309 */
15310
15311typedef enum SPI_SHADER_EX_FORMAT {
15312SPI_SHADER_ZERO = 0x00000000,
15313SPI_SHADER_32_R = 0x00000001,
15314SPI_SHADER_32_GR = 0x00000002,
15315SPI_SHADER_32_AR = 0x00000003,
15316SPI_SHADER_FP16_ABGR = 0x00000004,
15317SPI_SHADER_UNORM16_ABGR = 0x00000005,
15318SPI_SHADER_SNORM16_ABGR = 0x00000006,
15319SPI_SHADER_UINT16_ABGR = 0x00000007,
15320SPI_SHADER_SINT16_ABGR = 0x00000008,
15321SPI_SHADER_32_ABGR = 0x00000009,
15322} SPI_SHADER_EX_FORMAT;
15323
15324/*
15325 * SPI_SHADER_FORMAT enum
15326 */
15327
15328typedef enum SPI_SHADER_FORMAT {
15329SPI_SHADER_NONE = 0x00000000,
15330SPI_SHADER_1COMP = 0x00000001,
15331SPI_SHADER_2COMP = 0x00000002,
15332SPI_SHADER_4COMPRESS = 0x00000003,
15333SPI_SHADER_4COMP = 0x00000004,
15334} SPI_SHADER_FORMAT;
15335
15336/*******************************************************
15337 * SQ Enums
15338 *******************************************************/
15339
15340/*
15341 * SH_MEM_ADDRESS_MODE enum
15342 */
15343
15344typedef enum SH_MEM_ADDRESS_MODE {
15345SH_MEM_ADDRESS_MODE_64 = 0x00000000,
15346SH_MEM_ADDRESS_MODE_32 = 0x00000001,
15347} SH_MEM_ADDRESS_MODE;
15348
15349/*
15350 * SH_MEM_ALIGNMENT_MODE enum
15351 */
15352
15353typedef enum SH_MEM_ALIGNMENT_MODE {
15354SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000,
15355SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001,
15356SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002,
15357SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003,
15358} SH_MEM_ALIGNMENT_MODE;
15359
15360/*
15361 * SQG_PERF_SEL enum
15362 */
15363
15364typedef enum SQG_PERF_SEL {
15365SQG_PERF_SEL_NONE = 0x00000000,
15366SQG_PERF_SEL_MSG_BUS_BUSY = 0x00000001,
15367SQG_PERF_SEL_EXP_REQ0_BUS_BUSY = 0x00000002,
15368SQG_PERF_SEL_EXP_REQ1_BUS_BUSY = 0x00000003,
15369SQG_PERF_SEL_EXP_BUS0_BUSY = 0x00000004,
15370SQG_PERF_SEL_EXP_BUS1_BUSY = 0x00000005,
15371SQG_PERF_SEL_TTRACE_REQS = 0x00000006,
15372SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x00000007,
15373SQG_PERF_SEL_TTRACE_STALL = 0x00000008,
15374SQG_PERF_SEL_TTRACE_LOST_PACKETS = 0x00000009,
15375SQG_PERF_SEL_WAVES_INITIAL_PREFETCH = 0x0000000a,
15376SQG_PERF_SEL_EVENTS = 0x0000000b,
15377SQG_PERF_SEL_WAVES_RESTORED = 0x0000000c,
15378SQG_PERF_SEL_WAVES_SAVED = 0x0000000d,
15379SQG_PERF_SEL_ACCUM_PREV = 0x0000000e,
15380SQG_PERF_SEL_CYCLES = 0x0000000f,
15381SQG_PERF_SEL_BUSY_CYCLES = 0x00000010,
15382SQG_PERF_SEL_WAVE_CYCLES = 0x00000011,
15383SQG_PERF_SEL_MSG = 0x00000012,
15384SQG_PERF_SEL_MSG_INTERRUPT = 0x00000013,
15385SQG_PERF_SEL_WAVES = 0x00000014,
15386SQG_PERF_SEL_WAVES_32 = 0x00000015,
15387SQG_PERF_SEL_WAVES_64 = 0x00000016,
15388SQG_PERF_SEL_LEVEL_WAVES = 0x00000017,
15389SQG_PERF_SEL_ITEMS = 0x00000018,
15390SQG_PERF_SEL_WAVE32_ITEMS = 0x00000019,
15391SQG_PERF_SEL_WAVE64_ITEMS = 0x0000001a,
15392SQG_PERF_SEL_PS_QUADS = 0x0000001b,
15393SQG_PERF_SEL_WAVES_EQ_64 = 0x0000001c,
15394SQG_PERF_SEL_WAVES_EQ_32 = 0x0000001d,
15395SQG_PERF_SEL_WAVES_LT_64 = 0x0000001e,
15396SQG_PERF_SEL_WAVES_LT_48 = 0x0000001f,
15397SQG_PERF_SEL_WAVES_LT_32 = 0x00000020,
15398SQG_PERF_SEL_WAVES_LT_16 = 0x00000021,
15399SQG_PERF_SEL_DUMMY_LAST = 0x00000022,
15400} SQG_PERF_SEL;
15401
15402/*
15403 * SQ_CAC_POWER_SEL enum
15404 */
15405
15406typedef enum SQ_CAC_POWER_SEL {
15407SQ_CAC_POWER_VALU = 0x00000000,
15408SQ_CAC_POWER_VALU0 = 0x00000001,
15409SQ_CAC_POWER_VALU1 = 0x00000002,
15410SQ_CAC_POWER_VALU2 = 0x00000003,
15411SQ_CAC_POWER_GPR_RD = 0x00000004,
15412SQ_CAC_POWER_GPR_WR = 0x00000005,
15413SQ_CAC_POWER_LDS_BUSY = 0x00000006,
15414SQ_CAC_POWER_ALU_BUSY = 0x00000007,
15415SQ_CAC_POWER_TEX_BUSY = 0x00000008,
15416} SQ_CAC_POWER_SEL;
15417
15418/*
15419 * SQ_EDC_INFO_SOURCE enum
15420 */
15421
15422typedef enum SQ_EDC_INFO_SOURCE {
15423SQ_EDC_INFO_SOURCE_INVALID = 0x00000000,
15424SQ_EDC_INFO_SOURCE_INST = 0x00000001,
15425SQ_EDC_INFO_SOURCE_SGPR = 0x00000002,
15426SQ_EDC_INFO_SOURCE_VGPR = 0x00000003,
15427SQ_EDC_INFO_SOURCE_LDS = 0x00000004,
15428SQ_EDC_INFO_SOURCE_GDS = 0x00000005,
15429SQ_EDC_INFO_SOURCE_TA = 0x00000006,
15430} SQ_EDC_INFO_SOURCE;
15431
15432/*
15433 * SQ_IBUF_ST enum
15434 */
15435
15436typedef enum SQ_IBUF_ST {
15437SQ_IBUF_IB_IDLE = 0x00000000,
15438SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001,
15439SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002,
15440SQ_IBUF_IB_LE_4DW = 0x00000003,
15441SQ_IBUF_IB_WAIT_DRET = 0x00000004,
15442SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005,
15443SQ_IBUF_IB_DRET = 0x00000006,
15444SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007,
15445} SQ_IBUF_ST;
15446
15447/*
15448 * SQ_IMG_FILTER_TYPE enum
15449 */
15450
15451typedef enum SQ_IMG_FILTER_TYPE {
15452SQ_IMG_FILTER_MODE_BLEND = 0x00000000,
15453SQ_IMG_FILTER_MODE_MIN = 0x00000001,
15454SQ_IMG_FILTER_MODE_MAX = 0x00000002,
15455} SQ_IMG_FILTER_TYPE;
15456
15457/*
15458 * SQ_IND_CMD_CMD enum
15459 */
15460
15461typedef enum SQ_IND_CMD_CMD {
15462SQ_IND_CMD_CMD_NULL = 0x00000000,
15463SQ_IND_CMD_CMD_SETHALT = 0x00000001,
15464SQ_IND_CMD_CMD_SAVECTX = 0x00000002,
15465SQ_IND_CMD_CMD_KILL = 0x00000003,
15466SQ_IND_CMD_CMD_TRAP_AFTER_INST = 0x00000004,
15467SQ_IND_CMD_CMD_TRAP = 0x00000005,
15468SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x00000006,
15469SQ_IND_CMD_CMD_SETFATALHALT = 0x00000007,
15470SQ_IND_CMD_CMD_SINGLE_STEP = 0x00000008,
15471} SQ_IND_CMD_CMD;
15472
15473/*
15474 * SQ_IND_CMD_MODE enum
15475 */
15476
15477typedef enum SQ_IND_CMD_MODE {
15478SQ_IND_CMD_MODE_SINGLE = 0x00000000,
15479SQ_IND_CMD_MODE_BROADCAST = 0x00000001,
15480SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002,
15481SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003,
15482SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004,
15483} SQ_IND_CMD_MODE;
15484
15485/*
15486 * SQ_INST_STR_ST enum
15487 */
15488
15489typedef enum SQ_INST_STR_ST {
15490SQ_INST_STR_IB_WAVE_NORML = 0x00000000,
15491SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001,
15492SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002,
15493SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003,
15494SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000004,
15495SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000005,
15496} SQ_INST_STR_ST;
15497
15498/*
15499 * SQ_INST_TYPE enum
15500 */
15501
15502typedef enum SQ_INST_TYPE {
15503SQ_INST_TYPE_VALU = 0x00000000,
15504SQ_INST_TYPE_SCALAR = 0x00000001,
15505SQ_INST_TYPE_TEX = 0x00000002,
15506SQ_INST_TYPE_LDS = 0x00000003,
15507SQ_INST_TYPE_LDS_DIRECT = 0x00000004,
15508SQ_INST_TYPE_EXP = 0x00000005,
15509SQ_INST_TYPE_MSG = 0x00000006,
15510SQ_INST_TYPE_BARRIER = 0x00000007,
15511SQ_INST_TYPE_BRANCH_NOT_TAKEN = 0x00000008,
15512SQ_INST_TYPE_BRANCH_TAKEN = 0x00000009,
15513SQ_INST_TYPE_JUMP = 0x0000000a,
15514SQ_INST_TYPE_OTHER = 0x0000000b,
15515SQ_INST_TYPE_NONE = 0x0000000c,
15516} SQ_INST_TYPE;
15517
15518/*
15519 * SQ_LLC_CTL enum
15520 */
15521
15522typedef enum SQ_LLC_CTL {
15523SQ_LLC_0 = 0x00000000,
15524SQ_LLC_1 = 0x00000001,
15525SQ_LLC_RSVD_2 = 0x00000002,
15526SQ_LLC_BYPASS = 0x00000003,
15527} SQ_LLC_CTL;
15528
15529/*
15530 * SQ_NO_INST_ISSUE enum
15531 */
15532
15533typedef enum SQ_NO_INST_ISSUE {
15534SQ_NO_INST_ISSUE_NO_INSTS = 0x00000000,
15535SQ_NO_INST_ISSUE_ALU_DEP = 0x00000001,
15536SQ_NO_INST_ISSUE_S_WAITCNT = 0x00000002,
15537SQ_NO_INST_ISSUE_NO_ARB_WIN = 0x00000003,
15538SQ_NO_INST_ISSUE_SLEEP_WAIT = 0x00000004,
15539SQ_NO_INST_ISSUE_BARRIER_WAIT = 0x00000005,
15540SQ_NO_INST_ISSUE_OTHER = 0x00000006,
15541} SQ_NO_INST_ISSUE;
15542
15543/*
15544 * SQ_OOB_SELECT enum
15545 */
15546
15547typedef enum SQ_OOB_SELECT {
15548SQ_OOB_INDEX_AND_OFFSET = 0x00000000,
15549SQ_OOB_INDEX_ONLY = 0x00000001,
15550SQ_OOB_NUM_RECORDS_0 = 0x00000002,
15551SQ_OOB_COMPLETE = 0x00000003,
15552} SQ_OOB_SELECT;
15553
15554/*
15555 * SQ_PERF_SEL enum
15556 */
15557
15558typedef enum SQ_PERF_SEL {
15559SQ_PERF_SEL_NONE = 0x00000000,
15560SQ_PERF_SEL_ACCUM_PREV = 0x00000001,
15561SQ_PERF_SEL_CYCLES = 0x00000002,
15562SQ_PERF_SEL_BUSY_CYCLES = 0x00000003,
15563SQ_PERF_SEL_WAVES = 0x00000004,
15564SQ_PERF_SEL_WAVES_32 = 0x00000005,
15565SQ_PERF_SEL_WAVES_64 = 0x00000006,
15566SQ_PERF_SEL_LEVEL_WAVES = 0x00000007,
15567SQ_PERF_SEL_ITEMS = 0x00000008,
15568SQ_PERF_SEL_WAVE32_ITEMS = 0x00000009,
15569SQ_PERF_SEL_WAVE64_ITEMS = 0x0000000a,
15570SQ_PERF_SEL_PS_QUADS = 0x0000000b,
15571SQ_PERF_SEL_EVENTS = 0x0000000c,
15572SQ_PERF_SEL_WAVES_EQ_32 = 0x0000000d,
15573SQ_PERF_SEL_WAVES_EQ_64 = 0x0000000e,
15574SQ_PERF_SEL_WAVES_LT_64 = 0x0000000f,
15575SQ_PERF_SEL_WAVES_LT_48 = 0x00000010,
15576SQ_PERF_SEL_WAVES_LT_32 = 0x00000011,
15577SQ_PERF_SEL_WAVES_LT_16 = 0x00000012,
15578SQ_PERF_SEL_WAVES_RESTORED = 0x00000013,
15579SQ_PERF_SEL_WAVES_SAVED = 0x00000014,
15580SQ_PERF_SEL_MSG = 0x00000015,
15581SQ_PERF_SEL_MSG_INTERRUPT = 0x00000016,
15582SQ_PERF_SEL_WAVES_INITIAL_PREFETCH = 0x00000017,
15583SQ_PERF_SEL_WAVE_CYCLES = 0x00000018,
15584SQ_PERF_SEL_WAVE_READY = 0x00000019,
15585SQ_PERF_SEL_WAIT_INST_ANY = 0x0000001a,
15586SQ_PERF_SEL_WAIT_INST_VALU = 0x0000001b,
15587SQ_PERF_SEL_WAIT_INST_SCA = 0x0000001c,
15588SQ_PERF_SEL_WAIT_INST_LDS = 0x0000001d,
15589SQ_PERF_SEL_WAIT_INST_TEX = 0x0000001e,
15590SQ_PERF_SEL_WAIT_INST_FLAT = 0x0000001f,
15591SQ_PERF_SEL_WAIT_INST_VMEM = 0x00000020,
15592SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x00000021,
15593SQ_PERF_SEL_WAIT_INST_BR_MSG = 0x00000022,
15594SQ_PERF_SEL_WAIT_ANY = 0x00000023,
15595SQ_PERF_SEL_WAIT_CNT_ANY = 0x00000024,
15596SQ_PERF_SEL_WAIT_CNT_VMVS = 0x00000025,
15597SQ_PERF_SEL_WAIT_CNT_LGKM = 0x00000026,
15598SQ_PERF_SEL_WAIT_CNT_EXP = 0x00000027,
15599SQ_PERF_SEL_WAIT_TTRACE = 0x00000028,
15600SQ_PERF_SEL_WAIT_IFETCH = 0x00000029,
15601SQ_PERF_SEL_WAIT_BARRIER = 0x0000002a,
15602SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x0000002b,
15603SQ_PERF_SEL_WAIT_SLEEP = 0x0000002c,
15604SQ_PERF_SEL_WAIT_DELAY_ALU = 0x0000002d,
15605SQ_PERF_SEL_WAIT_DEPCTR = 0x0000002e,
15606SQ_PERF_SEL_WAIT_OTHER = 0x0000002f,
15607SQ_PERF_SEL_INSTS_ALL = 0x00000030,
15608SQ_PERF_SEL_INSTS_BRANCH = 0x00000031,
15609SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 0x00000032,
15610SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 0x00000033,
15611SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 0x00000034,
15612SQ_PERF_SEL_INSTS_EXP_GDS = 0x00000035,
15613SQ_PERF_SEL_INSTS_GDS = 0x00000036,
15614SQ_PERF_SEL_INSTS_EXP = 0x00000037,
15615SQ_PERF_SEL_INSTS_FLAT = 0x00000038,
15616SQ_PERF_SEL_INSTS_LDS = 0x00000039,
15617SQ_PERF_SEL_INSTS_SALU = 0x0000003a,
15618SQ_PERF_SEL_INSTS_SMEM = 0x0000003b,
15619SQ_PERF_SEL_INSTS_SMEM_NORM = 0x0000003c,
15620SQ_PERF_SEL_INSTS_SENDMSG = 0x0000003d,
15621SQ_PERF_SEL_INSTS_VALU = 0x0000003e,
15622SQ_PERF_SEL_INSTS_VALU_TRANS32 = 0x0000003f,
15623SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 0x00000040,
15624SQ_PERF_SEL_INSTS_TEX = 0x00000041,
15625SQ_PERF_SEL_INSTS_TEX_LOAD = 0x00000042,
15626SQ_PERF_SEL_INSTS_TEX_STORE = 0x00000043,
15627SQ_PERF_SEL_INSTS_DELAY_ALU = 0x00000044,
15628SQ_PERF_SEL_INSTS_INTERNAL = 0x00000045,
15629SQ_PERF_SEL_INSTS_WAVE32 = 0x00000046,
15630SQ_PERF_SEL_INSTS_WAVE32_FLAT = 0x00000047,
15631SQ_PERF_SEL_INSTS_WAVE32_LDS = 0x00000048,
15632SQ_PERF_SEL_INSTS_WAVE32_VALU = 0x00000049,
15633SQ_PERF_SEL_WAVE32_INSTS_EXP_GDS = 0x0000004a,
15634SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 0x0000004b,
15635SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 0x0000004c,
15636SQ_PERF_SEL_INSTS_WAVE32_TEX = 0x0000004d,
15637SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 0x0000004e,
15638SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 0x0000004f,
15639SQ_PERF_SEL_ITEM_CYCLES_VALU = 0x00000050,
15640SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 0x00000051,
15641SQ_PERF_SEL_WAVE32_INSTS = 0x00000052,
15642SQ_PERF_SEL_WAVE64_INSTS = 0x00000053,
15643SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 0x00000054,
15644SQ_PERF_SEL_WAVE64_HALF_SKIP = 0x00000055,
15645SQ_PERF_SEL_INST_LEVEL_EXP = 0x00000056,
15646SQ_PERF_SEL_INST_LEVEL_GDS = 0x00000057,
15647SQ_PERF_SEL_INST_LEVEL_LDS = 0x00000058,
15648SQ_PERF_SEL_INST_LEVEL_SMEM = 0x00000059,
15649SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 0x0000005a,
15650SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 0x0000005b,
15651SQ_PERF_SEL_IFETCH_REQS = 0x0000005c,
15652SQ_PERF_SEL_IFETCH_LEVEL = 0x0000005d,
15653SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 0x0000005e,
15654SQ_PERF_SEL_VALU_SGATHER_STALL = 0x0000005f,
15655SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 0x00000060,
15656SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 0x00000061,
15657SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 0x00000062,
15658SQ_PERF_SEL_SALU_SGATHER_STALL = 0x00000063,
15659SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 0x00000064,
15660SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 0x00000065,
15661SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 0x00000066,
15662SQ_PERF_SEL_INST_CYCLES_VALU = 0x00000067,
15663SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 0x00000068,
15664SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 0x00000069,
15665SQ_PERF_SEL_INST_CYCLES_VMEM = 0x0000006a,
15666SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 0x0000006b,
15667SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 0x0000006c,
15668SQ_PERF_SEL_INST_CYCLES_LDS = 0x0000006d,
15669SQ_PERF_SEL_INST_CYCLES_TEX = 0x0000006e,
15670SQ_PERF_SEL_INST_CYCLES_FLAT = 0x0000006f,
15671SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x00000070,
15672SQ_PERF_SEL_INST_CYCLES_EXP = 0x00000071,
15673SQ_PERF_SEL_INST_CYCLES_GDS = 0x00000072,
15674SQ_PERF_SEL_VALU_STARVE = 0x00000073,
15675SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 0x00000074,
15676SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 0x00000075,
15677SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x00000076,
15678SQ_PERF_SEL_VMEM_BUS_ACTIVE = 0x00000077,
15679SQ_PERF_SEL_VMEM_BUS_STALL = 0x00000078,
15680SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 0x00000079,
15681SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 0x0000007a,
15682SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 0x0000007b,
15683SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 0x0000007c,
15684SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 0x0000007d,
15685SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 0x0000007e,
15686SQ_PERF_SEL_SALU_PIPE_STALL = 0x0000007f,
15687SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 0x00000080,
15688SQ_PERF_SEL_MSG_BUS_BUSY = 0x00000081,
15689SQ_PERF_SEL_EXP_REQ_BUS_STALL = 0x00000082,
15690SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 0x00000083,
15691SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 0x00000084,
15692SQ_PERF_SEL_EXP_BUS0_BUSY = 0x00000085,
15693SQ_PERF_SEL_EXP_BUS1_BUSY = 0x00000086,
15694SQ_PERF_SEL_INST_CACHE_REQ_STALL = 0x00000087,
15695SQ_PERF_SEL_USER0 = 0x00000088,
15696SQ_PERF_SEL_USER1 = 0x00000089,
15697SQ_PERF_SEL_USER2 = 0x0000008a,
15698SQ_PERF_SEL_USER3 = 0x0000008b,
15699SQ_PERF_SEL_USER4 = 0x0000008c,
15700SQ_PERF_SEL_USER5 = 0x0000008d,
15701SQ_PERF_SEL_USER6 = 0x0000008e,
15702SQ_PERF_SEL_USER7 = 0x0000008f,
15703SQ_PERF_SEL_USER8 = 0x00000090,
15704SQ_PERF_SEL_USER9 = 0x00000091,
15705SQ_PERF_SEL_USER10 = 0x00000092,
15706SQ_PERF_SEL_USER11 = 0x00000093,
15707SQ_PERF_SEL_USER12 = 0x00000094,
15708SQ_PERF_SEL_USER13 = 0x00000095,
15709SQ_PERF_SEL_USER14 = 0x00000096,
15710SQ_PERF_SEL_USER15 = 0x00000097,
15711SQ_PERF_SEL_USER_LEVEL0 = 0x00000098,
15712SQ_PERF_SEL_USER_LEVEL1 = 0x00000099,
15713SQ_PERF_SEL_USER_LEVEL2 = 0x0000009a,
15714SQ_PERF_SEL_USER_LEVEL3 = 0x0000009b,
15715SQ_PERF_SEL_USER_LEVEL4 = 0x0000009c,
15716SQ_PERF_SEL_USER_LEVEL5 = 0x0000009d,
15717SQ_PERF_SEL_USER_LEVEL6 = 0x0000009e,
15718SQ_PERF_SEL_USER_LEVEL7 = 0x0000009f,
15719SQ_PERF_SEL_USER_LEVEL8 = 0x000000a0,
15720SQ_PERF_SEL_USER_LEVEL9 = 0x000000a1,
15721SQ_PERF_SEL_USER_LEVEL10 = 0x000000a2,
15722SQ_PERF_SEL_USER_LEVEL11 = 0x000000a3,
15723SQ_PERF_SEL_USER_LEVEL12 = 0x000000a4,
15724SQ_PERF_SEL_USER_LEVEL13 = 0x000000a5,
15725SQ_PERF_SEL_USER_LEVEL14 = 0x000000a6,
15726SQ_PERF_SEL_USER_LEVEL15 = 0x000000a7,
15727SQ_PERF_SEL_VALU_RETURN_SDST = 0x000000a8,
15728SQ_PERF_SEL_VMEM_VGPR_READ_STALLED_BY_EXPORT = 0x000000a9,
15729SQ_PERF_SEL_INSTS_VALU_TRANS = 0x000000aa,
15730SQ_PERF_SEL_INSTS_LDS_DIRECT_LOAD = 0x000000ab,
15731SQ_PERF_SEL_INSTS_LDS_PARAM_LOAD = 0x000000ac,
15732SQ_PERF_SEL_INSTS_WAVE32_LDS_PARAM_LOAD = 0x000000ad,
15733SQ_PERF_SEL_INSTS_VALU_ONE_CYCLE_WAVE64 = 0x000000ae,
15734SQ_PERF_SEL_INSTS_VALU_VINTERP = 0x000000af,
15735SQ_PERF_SEL_INSTS_VALU_WAVE32_VINTERP = 0x000000b0,
15736SQ_PERF_SEL_OVERFLOW_PREV = 0x000000b1,
15737SQ_PERF_SEL_INSTS_DUAL_VALU_WAVE32 = 0x000000b2,
15738SQ_PERF_SEL_INSTS_VALU_1_PASS = 0x000000b3,
15739SQ_PERF_SEL_INSTS_VALU_2_PASS = 0x000000b4,
15740SQ_PERF_SEL_INSTS_VALU_4_PASS = 0x000000b5,
15741SQ_PERF_SEL_INSTS_VALU_DP = 0x000000b6,
15742SQ_PERF_SEL_SP_CONST_CYCLES = 0x000000b7,
15743SQ_PERF_SEL_SP_CONST_STALL_CYCLES = 0x000000b8,
15744SQ_PERF_SEL_ITEMS_VALU = 0x000000b9,
15745SQ_PERF_SEL_ITEMS_MAX_VALU = 0x000000ba,
15746SQ_PERF_SEL_ITEM_CYCLES_VMEM = 0x000000bb,
15747SQ_PERF_SEL_DUMMY_END = 0x000000bc,
15748SQ_PERF_SEL_DUMMY_LAST = 0x000000ff,
15749SQC_PERF_SEL_LDS_BANK_CONFLICT = 0x00000100,
15750SQC_PERF_SEL_LDS_ADDR_CONFLICT = 0x00000101,
15751SQC_PERF_SEL_LDS_UNALIGNED_STALL = 0x00000102,
15752SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 0x00000103,
15753SQC_PERF_SEL_LDS_ATOMIC_RETURN = 0x00000104,
15754SQC_PERF_SEL_LDS_IDX_ACTIVE = 0x00000105,
15755SQC_PERF_SEL_LDS_ADDR_STALL = 0x00000106,
15756SQC_PERF_SEL_LDS_ADDR_ACTIVE = 0x00000107,
15757SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 0x00000108,
15758SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 0x00000109,
15759SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 0x0000010a,
15760SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 0x0000010b,
15761SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0x0000010c,
15762SQC_PERF_SEL_ICACHE_REQ = 0x0000010d,
15763SQC_PERF_SEL_ICACHE_HITS = 0x0000010e,
15764SQC_PERF_SEL_ICACHE_MISSES = 0x0000010f,
15765SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0x00000110,
15766SQC_PERF_SEL_ICACHE_INVAL_INST = 0x00000111,
15767SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0x00000112,
15768SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0x00000113,
15769SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0x00000114,
15770SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0x00000115,
15771SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0x00000116,
15772SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0x00000117,
15773SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0x00000118,
15774SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0x00000119,
15775SQC_PERF_SEL_TC_REQ = 0x0000011a,
15776SQC_PERF_SEL_TC_INST_REQ = 0x0000011b,
15777SQC_PERF_SEL_TC_DATA_READ_REQ = 0x0000011c,
15778SQC_PERF_SEL_TC_STALL = 0x0000011d,
15779SQC_PERF_SEL_TC_STARVE = 0x0000011e,
15780SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000011f,
15781SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000120,
15782SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0x00000121,
15783SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000122,
15784SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000123,
15785SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0x00000124,
15786SQC_PERF_SEL_DCACHE_REQ = 0x00000125,
15787SQC_PERF_SEL_DCACHE_HITS = 0x00000126,
15788SQC_PERF_SEL_DCACHE_MISSES = 0x00000127,
15789SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0x00000128,
15790SQC_PERF_SEL_DCACHE_INVAL_INST = 0x00000129,
15791SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0x0000012a,
15792SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0x0000012b,
15793SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000012c,
15794SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x0000012d,
15795SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0x0000012e,
15796SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x0000012f,
15797SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0x00000130,
15798SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x00000131,
15799SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0x00000132,
15800SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0x00000133,
15801SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0x00000134,
15802SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0x00000135,
15803SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0x00000136,
15804SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0x00000137,
15805SQC_PERF_SEL_SQ_DCACHE_REQS = 0x00000138,
15806SQC_PERF_SEL_DCACHE_FLAT_REQ = 0x00000139,
15807SQC_PERF_SEL_TD_VGPR_BUSY = 0x0000013a,
15808SQC_PERF_SEL_LDS_VGPR_BUSY = 0x0000013b,
15809SQC_PERF_SEL_LDS_TD_VGPR_CONF_STALL = 0x0000013c,
15810SQC_PERF_SEL_ICACHE_GCR = 0x0000013d,
15811SQC_PERF_SEL_ICACHE_GCR_HITS = 0x0000013e,
15812SQC_PERF_SEL_DCACHE_GCR = 0x0000013f,
15813SQC_PERF_SEL_DCACHE_GCR_HITS = 0x00000140,
15814SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 0x00000141,
15815SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 0x00000142,
15816SQC_PERF_SEL_DCACHE_SPI_RETURN_STALL = 0x00000143,
15817SQC_PERF_SEL_DUMMY_LAST = 0x00000144,
15818SP_PERF_SEL_DST_BUF_ALLOC_STALL = 0x000001c0,
15819SP_PERF_SEL_DST_BUF_WB_CONF_W_TD_LDS = 0x000001c1,
15820SP_PERF_SEL_DST_BUF_WB_CONF_W_SPI = 0x000001c2,
15821SP_PERF_SEL_DST_BUF_EVEN_DIRTY = 0x000001c3,
15822SP_PERF_SEL_DST_BUF_ODD_DIRTY = 0x000001c4,
15823SP_PERF_SEL_SRC_CACHE_HIT_B0 = 0x000001c5,
15824SP_PERF_SEL_SRC_CACHE_HIT_B1 = 0x000001c6,
15825SP_PERF_SEL_SRC_CACHE_HIT_B2 = 0x000001c7,
15826SP_PERF_SEL_SRC_CACHE_HIT_B3 = 0x000001c8,
15827SP_PERF_SEL_SRC_CACHE_PROBE_B0 = 0x000001c9,
15828SP_PERF_SEL_SRC_CACHE_PROBE_B1 = 0x000001ca,
15829SP_PERF_SEL_SRC_CACHE_PROBE_B2 = 0x000001cb,
15830SP_PERF_SEL_SRC_CACHE_PROBE_B3 = 0x000001cc,
15831SP_PERF_SEL_SRC_CACHE_VGPR_RD_B0 = 0x000001cd,
15832SP_PERF_SEL_SRC_CACHE_VGPR_RD_B1 = 0x000001ce,
15833SP_PERF_SEL_SRC_CACHE_VGPR_RD_B2 = 0x000001cf,
15834SP_PERF_SEL_SRC_CACHE_VGPR_RD_B3 = 0x000001d0,
15835SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B0 = 0x000001d1,
15836SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B1 = 0x000001d2,
15837SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B2 = 0x000001d3,
15838SP_PERF_SEL_SRC_CACHE_RECYCLE_HIT_B3 = 0x000001d4,
15839SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B0 = 0x000001d5,
15840SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B1 = 0x000001d6,
15841SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B2 = 0x000001d7,
15842SP_PERF_SEL_SRC_CACHE_PROBE_SUCCESS_B3 = 0x000001d8,
15843SP_PERF_SEL_VALU_PENDING_QUEUE_STALL = 0x000001d9,
15844SP_PERF_SEL_VALU_OPERAND = 0x000001da,
15845SP_PERF_SEL_VALU_VGPR_OPERAND = 0x000001db,
15846SP_PERF_SEL_VALU_OPERAND_FROM_DST_BUF = 0x000001dc,
15847SP_PERF_SEL_VALU_EXEC_MASK_CHANGE = 0x000001dd,
15848SP_PERF_SEL_VALU_COEXEC_WITH_TRANS = 0x000001de,
15849SP_PERF_SEL_VALU_SGPR_FWD_BUF_FULL = 0x000001df,
15850SP_PERF_SEL_VALU_STALL = 0x000001e0,
15851SP_PERF_SEL_VALU_STALL_VGPR_NOT_READY = 0x000001e1,
15852SP_PERF_SEL_VALU_STALL_SGPR_NOT_READY = 0x000001e2,
15853SP_PERF_SEL_VALU_STALL_VDST_FWD = 0x000001e3,
15854SP_PERF_SEL_VALU_STALL_SDST_FWD = 0x000001e4,
15855SP_PERF_SEL_VALU_STALL_DST_STALL = 0x000001e5,
15856SP_PERF_SEL_VALU_FAST_OP_STALL_VGPR_NOT_READY = 0x000001e6,
15857SP_PERF_SEL_VGPR_VMEM_RD = 0x000001e7,
15858SP_PERF_SEL_VGPR_EXP_RD = 0x000001e8,
15859SP_PERF_SEL_VGPR_SPI_WR = 0x000001e9,
15860SP_PERF_SEL_VGPR_TDLDS_DATA_WR = 0x000001ea,
15861SP_PERF_SEL_VGPR_WR = 0x000001eb,
15862SP_PERF_SEL_VGPR_RD = 0x000001ec,
15863SP_PERF_SEL_DUMMY_LAST = 0x000001ed,
15864SQ_PERF_SEL_NONE2 = 0x000001ff,
15865} SQ_PERF_SEL;
15866
15867/*
15868 * SQ_ROUND_MODE enum
15869 */
15870
15871typedef enum SQ_ROUND_MODE {
15872SQ_ROUND_NEAREST_EVEN = 0x00000000,
15873SQ_ROUND_PLUS_INFINITY = 0x00000001,
15874SQ_ROUND_MINUS_INFINITY = 0x00000002,
15875SQ_ROUND_TO_ZERO = 0x00000003,
15876} SQ_ROUND_MODE;
15877
15878/*
15879 * SQ_RSRC_BUF_TYPE enum
15880 */
15881
15882typedef enum SQ_RSRC_BUF_TYPE {
15883SQ_RSRC_BUF = 0x00000000,
15884SQ_RSRC_BUF_RSVD_1 = 0x00000001,
15885SQ_RSRC_BUF_RSVD_2 = 0x00000002,
15886SQ_RSRC_BUF_RSVD_3 = 0x00000003,
15887} SQ_RSRC_BUF_TYPE;
15888
15889/*
15890 * SQ_RSRC_FLAT_TYPE enum
15891 */
15892
15893typedef enum SQ_RSRC_FLAT_TYPE {
15894SQ_RSRC_FLAT_RSVD_0 = 0x00000000,
15895SQ_RSRC_FLAT = 0x00000001,
15896SQ_RSRC_FLAT_RSVD_2 = 0x00000002,
15897SQ_RSRC_FLAT_RSVD_3 = 0x00000003,
15898} SQ_RSRC_FLAT_TYPE;
15899
15900/*
15901 * SQ_RSRC_IMG_TYPE enum
15902 */
15903
15904typedef enum SQ_RSRC_IMG_TYPE {
15905SQ_RSRC_IMG_RSVD_0 = 0x00000000,
15906SQ_RSRC_IMG_RSVD_1 = 0x00000001,
15907SQ_RSRC_IMG_RSVD_2 = 0x00000002,
15908SQ_RSRC_IMG_RSVD_3 = 0x00000003,
15909SQ_RSRC_IMG_RSVD_4 = 0x00000004,
15910SQ_RSRC_IMG_RSVD_5 = 0x00000005,
15911SQ_RSRC_IMG_RSVD_6 = 0x00000006,
15912SQ_RSRC_IMG_RSVD_7 = 0x00000007,
15913SQ_RSRC_IMG_1D = 0x00000008,
15914SQ_RSRC_IMG_2D = 0x00000009,
15915SQ_RSRC_IMG_3D = 0x0000000a,
15916SQ_RSRC_IMG_CUBE = 0x0000000b,
15917SQ_RSRC_IMG_1D_ARRAY = 0x0000000c,
15918SQ_RSRC_IMG_2D_ARRAY = 0x0000000d,
15919SQ_RSRC_IMG_2D_MSAA = 0x0000000e,
15920SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f,
15921} SQ_RSRC_IMG_TYPE;
15922
15923/*
15924 * SQ_SEL_XYZW01 enum
15925 */
15926
15927typedef enum SQ_SEL_XYZW01 {
15928SQ_SEL_0 = 0x00000000,
15929SQ_SEL_1 = 0x00000001,
15930SQ_SEL_N_BC_1 = 0x00000002,
15931SQ_SEL_RESERVED_1 = 0x00000003,
15932SQ_SEL_X = 0x00000004,
15933SQ_SEL_Y = 0x00000005,
15934SQ_SEL_Z = 0x00000006,
15935SQ_SEL_W = 0x00000007,
15936} SQ_SEL_XYZW01;
15937
15938/*
15939 * SQ_TEX_ANISO_RATIO enum
15940 */
15941
15942typedef enum SQ_TEX_ANISO_RATIO {
15943SQ_TEX_ANISO_RATIO_1 = 0x00000000,
15944SQ_TEX_ANISO_RATIO_2 = 0x00000001,
15945SQ_TEX_ANISO_RATIO_4 = 0x00000002,
15946SQ_TEX_ANISO_RATIO_8 = 0x00000003,
15947SQ_TEX_ANISO_RATIO_16 = 0x00000004,
15948} SQ_TEX_ANISO_RATIO;
15949
15950/*
15951 * SQ_TEX_BORDER_COLOR enum
15952 */
15953
15954typedef enum SQ_TEX_BORDER_COLOR {
15955SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000,
15956SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001,
15957SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002,
15958SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003,
15959} SQ_TEX_BORDER_COLOR;
15960
15961/*
15962 * SQ_TEX_CLAMP enum
15963 */
15964
15965typedef enum SQ_TEX_CLAMP {
15966SQ_TEX_WRAP = 0x00000000,
15967SQ_TEX_MIRROR = 0x00000001,
15968SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002,
15969SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003,
15970SQ_TEX_CLAMP_HALF_BORDER = 0x00000004,
15971SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005,
15972SQ_TEX_CLAMP_BORDER = 0x00000006,
15973SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007,
15974} SQ_TEX_CLAMP;
15975
15976/*
15977 * SQ_TEX_DEPTH_COMPARE enum
15978 */
15979
15980typedef enum SQ_TEX_DEPTH_COMPARE {
15981SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000,
15982SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001,
15983SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002,
15984SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003,
15985SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004,
15986SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005,
15987SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006,
15988SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007,
15989} SQ_TEX_DEPTH_COMPARE;
15990
15991/*
15992 * SQ_TEX_MIP_FILTER enum
15993 */
15994
15995typedef enum SQ_TEX_MIP_FILTER {
15996SQ_TEX_MIP_FILTER_NONE = 0x00000000,
15997SQ_TEX_MIP_FILTER_POINT = 0x00000001,
15998SQ_TEX_MIP_FILTER_LINEAR = 0x00000002,
15999SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x00000003,
16000} SQ_TEX_MIP_FILTER;
16001
16002/*
16003 * SQ_TEX_XY_FILTER enum
16004 */
16005
16006typedef enum SQ_TEX_XY_FILTER {
16007SQ_TEX_XY_FILTER_POINT = 0x00000000,
16008SQ_TEX_XY_FILTER_BILINEAR = 0x00000001,
16009SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002,
16010SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003,
16011} SQ_TEX_XY_FILTER;
16012
16013/*
16014 * SQ_TEX_Z_FILTER enum
16015 */
16016
16017typedef enum SQ_TEX_Z_FILTER {
16018SQ_TEX_Z_FILTER_NONE = 0x00000000,
16019SQ_TEX_Z_FILTER_POINT = 0x00000001,
16020SQ_TEX_Z_FILTER_LINEAR = 0x00000002,
16021} SQ_TEX_Z_FILTER;
16022
16023/*
16024 * SQ_TT_MODE enum
16025 */
16026
16027typedef enum SQ_TT_MODE {
16028SQ_TT_MODE_OFF = 0x00000000,
16029SQ_TT_MODE_ON = 0x00000001,
16030SQ_TT_MODE_GLOBAL = 0x00000002,
16031SQ_TT_MODE_DETAIL = 0x00000003,
16032} SQ_TT_MODE;
16033
16034/*
16035 * SQ_TT_RT_FREQ enum
16036 */
16037
16038typedef enum SQ_TT_RT_FREQ {
16039SQ_TT_RT_FREQ_NEVER = 0x00000000,
16040SQ_TT_RT_FREQ_1024_CLK = 0x00000001,
16041SQ_TT_RT_FREQ_4096_CLK = 0x00000002,
16042} SQ_TT_RT_FREQ;
16043
16044/*
16045 * SQ_TT_TOKEN_MASK_INST_EXCLUDE enum
16046 */
16047
16048typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE {
16049SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_BIT = 0x00000001,
16050SQ_TT_INST_EXCLUDE_EXPGNT234_BIT = 0x00000002,
16051} SQ_TT_TOKEN_MASK_INST_EXCLUDE;
16052
16053/*
16054 * SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT enum
16055 */
16056
16057typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT {
16058SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD_SHIFT = 0x00000000,
16059SQ_TT_INST_EXCLUDE_EXPGNT234_SHIFT = 0x00000001,
16060} SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT;
16061
16062/*
16063 * SQ_TT_TOKEN_MASK_REG_EXCLUDE enum
16064 */
16065
16066typedef enum SQ_TT_TOKEN_MASK_REG_EXCLUDE {
16067SQ_TT_REG_EXCLUDE_USER_DATA_BIT = 0x00000001,
16068SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_BIT = 0x00000002,
16069SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_BIT = 0x00000004,
16070} SQ_TT_TOKEN_MASK_REG_EXCLUDE;
16071
16072/*
16073 * SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT enum
16074 */
16075
16076typedef enum SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT {
16077SQ_TT_REG_EXCLUDE_USER_DATA_SHIFT = 0x00000000,
16078SQ_TT_REG_EXCLUDE_CP_ME_MC_RADDR_SHIFT = 0x00000001,
16079SQ_TT_REG_EXCLUDE_GRBM_COMPUTE_EXCLUDE_SHIFT = 0x00000002,
16080} SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT;
16081
16082/*
16083 * SQ_TT_TOKEN_MASK_REG_INCLUDE enum
16084 */
16085
16086typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE {
16087SQ_TT_TOKEN_MASK_SQDEC_BIT = 0x00000001,
16088SQ_TT_TOKEN_MASK_SHDEC_BIT = 0x00000002,
16089SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 0x00000004,
16090SQ_TT_TOKEN_MASK_COMP_BIT = 0x00000008,
16091SQ_TT_TOKEN_MASK_CONTEXT_BIT = 0x00000010,
16092SQ_TT_TOKEN_MASK_CONFIG_BIT = 0x00000020,
16093SQ_TT_TOKEN_MASK_ALL_BIT = 0x00000040,
16094SQ_TT_TOKEN_MASK_RSVD_BIT = 0x00000080,
16095} SQ_TT_TOKEN_MASK_REG_INCLUDE;
16096
16097/*
16098 * SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT enum
16099 */
16100
16101typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT {
16102SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0x00000000,
16103SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 0x00000001,
16104SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 0x00000002,
16105SQ_TT_TOKEN_MASK_COMP_SHIFT = 0x00000003,
16106SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 0x00000004,
16107SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 0x00000005,
16108SQ_TT_TOKEN_MASK_ALL_SHIFT = 0x00000006,
16109SQ_TT_TOKEN_MASK_RSVD_SHIFT = 0x00000007,
16110} SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT;
16111
16112/*
16113 * SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT enum
16114 */
16115
16116typedef enum SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT {
16117SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0x00000000,
16118SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 0x00000001,
16119SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 0x00000002,
16120SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 0x00000003,
16121SQ_TT_TOKEN_EXCLUDE_WAVESTARTEND_SHIFT = 0x00000004,
16122SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 0x00000005,
16123SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 0x00000006,
16124SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 0x00000007,
16125SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 0x00000008,
16126SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 0x00000009,
16127SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 0x0000000a,
16128SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 0x0000000b,
16129} SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT;
16130
16131/*
16132 * SQ_TT_UTIL_TIMER enum
16133 */
16134
16135typedef enum SQ_TT_UTIL_TIMER {
16136SQ_TT_UTIL_TIMER_100_CLK = 0x00000000,
16137SQ_TT_UTIL_TIMER_250_CLK = 0x00000001,
16138} SQ_TT_UTIL_TIMER;
16139
16140/*
16141 * SQ_TT_WAVESTART_MODE enum
16142 */
16143
16144typedef enum SQ_TT_WAVESTART_MODE {
16145SQ_TT_WAVESTART_MODE_SHORT = 0x00000000,
16146SQ_TT_WAVESTART_MODE_ALLOC = 0x00000001,
16147SQ_TT_WAVESTART_MODE_PBB_ID = 0x00000002,
16148} SQ_TT_WAVESTART_MODE;
16149
16150/*
16151 * SQ_TT_WTYPE_INCLUDE enum
16152 */
16153
16154typedef enum SQ_TT_WTYPE_INCLUDE {
16155SQ_TT_WTYPE_INCLUDE_PS_BIT = 0x00000001,
16156SQ_TT_WTYPE_INCLUDE_RSVD0_BIT = 0x00000002,
16157SQ_TT_WTYPE_INCLUDE_GS_BIT = 0x00000004,
16158SQ_TT_WTYPE_INCLUDE_RSVD1_BIT = 0x00000008,
16159SQ_TT_WTYPE_INCLUDE_HS_BIT = 0x00000010,
16160SQ_TT_WTYPE_INCLUDE_RSVD2_BIT = 0x00000020,
16161SQ_TT_WTYPE_INCLUDE_CS_BIT = 0x00000040,
16162} SQ_TT_WTYPE_INCLUDE;
16163
16164/*
16165 * SQ_TT_WTYPE_INCLUDE_SHIFT enum
16166 */
16167
16168typedef enum SQ_TT_WTYPE_INCLUDE_SHIFT {
16169SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0x00000000,
16170SQ_TT_WTYPE_INCLUDE_RSVD0_SHIFT = 0x00000001,
16171SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 0x00000002,
16172SQ_TT_WTYPE_INCLUDE_RSVD1_SHIFT = 0x00000003,
16173SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 0x00000004,
16174SQ_TT_WTYPE_INCLUDE_RSVD2_SHIFT = 0x00000005,
16175SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 0x00000006,
16176} SQ_TT_WTYPE_INCLUDE_SHIFT;
16177
16178/*
16179 * SQ_WATCH_MODES enum
16180 */
16181
16182typedef enum SQ_WATCH_MODES {
16183SQ_WATCH_MODE_READ = 0x00000000,
16184SQ_WATCH_MODE_NONREAD = 0x00000001,
16185SQ_WATCH_MODE_ATOMIC = 0x00000002,
16186SQ_WATCH_MODE_ALL = 0x00000003,
16187} SQ_WATCH_MODES;
16188
16189/*
16190 * SQ_WAVE_FWD_PROG_INTERVAL enum
16191 */
16192
16193typedef enum SQ_WAVE_FWD_PROG_INTERVAL {
16194SQ_WAVE_FWD_PROG_INTERVAL_NEVER = 0x00000000,
16195SQ_WAVE_FWD_PROG_INTERVAL_256 = 0x00000001,
16196SQ_WAVE_FWD_PROG_INTERVAL_1024 = 0x00000002,
16197SQ_WAVE_FWD_PROG_INTERVAL_4096 = 0x00000003,
16198} SQ_WAVE_FWD_PROG_INTERVAL;
16199
16200/*
16201 * SQ_WAVE_IB_ECC_ST enum
16202 */
16203
16204typedef enum SQ_WAVE_IB_ECC_ST {
16205SQ_WAVE_IB_ECC_CLEAN = 0x00000000,
16206SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x00000001,
16207SQ_WAVE_IB_ECC_ERR_HALT = 0x00000002,
16208SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x00000003,
16209} SQ_WAVE_IB_ECC_ST;
16210
16211/*
16212 * SQ_WAVE_SCHED_MODES enum
16213 */
16214
16215typedef enum SQ_WAVE_SCHED_MODES {
16216SQ_WAVE_SCHED_MODE_NORMAL = 0x00000000,
16217SQ_WAVE_SCHED_MODE_EXPERT = 0x00000001,
16218SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 0x00000002,
16219} SQ_WAVE_SCHED_MODES;
16220
16221/*
16222 * SQ_WAVE_TYPE enum
16223 */
16224
16225typedef enum SQ_WAVE_TYPE {
16226SQ_WAVE_TYPE_PS = 0x00000000,
16227SQ_WAVE_TYPE_RSVD0 = 0x00000001,
16228SQ_WAVE_TYPE_GS = 0x00000002,
16229SQ_WAVE_TYPE_RSVD1 = 0x00000003,
16230SQ_WAVE_TYPE_HS = 0x00000004,
16231SQ_WAVE_TYPE_RSVD2 = 0x00000005,
16232SQ_WAVE_TYPE_CS = 0x00000006,
16233SQ_WAVE_TYPE_PS1 = 0x00000007,
16234SQ_WAVE_TYPE_PS2 = 0x00000008,
16235SQ_WAVE_TYPE_PS3 = 0x00000009,
16236} SQ_WAVE_TYPE;
16237
16238/*
16239 * SQ_WAVE_TYPE value
16240 */
16241
16242#define SQ_WAVE_TYPE_PS0 0x00000000
16243
16244/*
16245 * SQIND_PARTITIONS value
16246 */
16247
16248#define SQIND_GLOBAL_REGS_OFFSET 0x00000000
16249#define SQIND_GLOBAL_REGS_SIZE 0x00000008
16250#define SQIND_LOCAL_REGS_OFFSET 0x00000008
16251#define SQIND_LOCAL_REGS_SIZE 0x00000008
16252#define SQIND_WAVE_HWREGS_OFFSET 0x00000100
16253#define SQIND_WAVE_HWREGS_SIZE 0x00000100
16254#define SQIND_WAVE_SGPRS_OFFSET 0x00000200
16255#define SQIND_WAVE_SGPRS_SIZE 0x00000200
16256#define SQIND_WAVE_VGPRS_OFFSET 0x00000400
16257#define SQIND_WAVE_VGPRS_SIZE 0x00000400
16258
16259/*
16260 * SQ_GFXDEC value
16261 */
16262
16263#define SQ_GFXDEC_BEGIN 0x0000a000
16264#define SQ_GFXDEC_END 0x0000c000
16265#define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a
16266
16267/*
16268 * SQDEC value
16269 */
16270
16271#define SQDEC_BEGIN 0x00002300
16272#define SQDEC_END 0x000023ff
16273
16274/*
16275 * SQPERFSDEC value
16276 */
16277
16278#define SQPERFSDEC_BEGIN 0x0000d9c0
16279#define SQPERFSDEC_END 0x0000da40
16280
16281/*
16282 * SQPERFDDEC value
16283 */
16284
16285#define SQPERFDDEC_BEGIN 0x0000d1c0
16286#define SQPERFDDEC_END 0x0000d240
16287
16288/*
16289 * SQGFXUDEC value
16290 */
16291
16292#define SQGFXUDEC_BEGIN 0x0000c330
16293#define SQGFXUDEC_END 0x0000c380
16294
16295/*
16296 * SQPWRDEC value
16297 */
16298
16299#define SQPWRDEC_BEGIN 0x0000f08c
16300#define SQPWRDEC_END 0x0000f094
16301
16302/*
16303 * SQ_DISPATCHER value
16304 */
16305
16306#define SQ_DISPATCHER_GFX_MIN 0x00000010
16307#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008
16308
16309/*
16310 * SQ_MAX value
16311 */
16312
16313#define SQ_MAX_PGM_SGPRS 0x00000068
16314#define SQ_MAX_PGM_VGPRS 0x00000100
16315
16316/*
16317 * SQ_EXCP_BITS value
16318 */
16319
16320#define SQ_EX_MODE_EXCP_VALU_BASE 0x00000000
16321#define SQ_EX_MODE_EXCP_VALU_SIZE 0x00000007
16322#define SQ_EX_MODE_EXCP_INVALID 0x00000000
16323#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x00000001
16324#define SQ_EX_MODE_EXCP_DIV0 0x00000002
16325#define SQ_EX_MODE_EXCP_OVERFLOW 0x00000003
16326#define SQ_EX_MODE_EXCP_UNDERFLOW 0x00000004
16327#define SQ_EX_MODE_EXCP_INEXACT 0x00000005
16328#define SQ_EX_MODE_EXCP_INT_DIV0 0x00000006
16329#define SQ_EX_MODE_EXCP_ADDR_WATCH0 0x00000007
16330#define SQ_EX_MODE_EXCP_MEM_VIOL 0x00000008
16331
16332/*
16333 * SQ_EXCP_HI_BITS value
16334 */
16335
16336#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000
16337#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001
16338#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002
16339
16340/*
16341 * HW_INSERTED_INST_ID value
16342 */
16343
16344#define INST_ID_PRIV_START 0x80000000
16345#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0
16346#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1
16347#define INST_ID_HW_TRAP 0xfffffff2
16348#define INST_ID_KILL_SEQ 0xfffffff3
16349#define INST_ID_SPI_WREXEC 0xfffffff4
16350#define INST_ID_HW_TRAP_GET_TBA 0xfffffff5
16351#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe
16352
16353/*
16354 * SIMM16_WAITCNT_PARTITIONS value
16355 */
16356
16357#define SIMM16_WAITCNT_EXP_CNT_START 0x00000000
16358#define SIMM16_WAITCNT_EXP_CNT_SIZE 0x00000003
16359#define SIMM16_WAITCNT_LGKM_CNT_START 0x00000004
16360#define SIMM16_WAITCNT_LGKM_CNT_SIZE 0x00000006
16361#define SIMM16_WAITCNT_VM_CNT_START 0x0000000a
16362#define SIMM16_WAITCNT_VM_CNT_SIZE 0x00000006
16363#define SIMM16_WAITCNT_DEPCTR_SA_SDST_START 0x00000000
16364#define SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE 0x00000001
16365#define SIMM16_WAITCNT_DEPCTR_VA_VCC_START 0x00000001
16366#define SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE 0x00000001
16367#define SIMM16_WAITCNT_DEPCTR_VM_VSRC_START 0x00000002
16368#define SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE 0x00000003
16369#define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START 0x00000006
16370#define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE 0x00000001
16371#define SIMM16_WAITCNT_DEPCTR_VA_SSRC_START 0x00000007
16372#define SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE 0x00000001
16373#define SIMM16_WAITCNT_DEPCTR_VA_SDST_START 0x00000008
16374#define SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE 0x00000003
16375#define SIMM16_WAITCNT_DEPCTR_VA_VDST_START 0x0000000b
16376#define SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE 0x00000005
16377
16378/*
16379 * SIMM16_WAIT_EVENT_PARTITIONS value
16380 */
16381
16382#define SIMM16_WAIT_EVENT_EXP_RDY_START 0x00000000
16383#define SIMM16_WAIT_EVENT_EXP_RDY_SIZE 0x00000001
16384
16385/*
16386 * SQ_WAVE_IB_DEP_COUNTER_SIZES value
16387 */
16388
16389#define SQ_WAVE_IB_DEP_SA_SDST_SIZE 0x00000004
16390#define SQ_WAVE_IB_DEP_SA_EXEC_SIZE 0x00000002
16391#define SQ_WAVE_IB_DEP_SA_M0_SIZE 0x00000001
16392#define SQ_WAVE_IB_DEP_VM_VSRC_SIZE 0x00000004
16393#define SQ_WAVE_IB_DEP_HOLD_CNT_SIZE 0x00000001
16394#define SQ_WAVE_IB_DEP_VA_SSRC_SIZE 0x00000003
16395#define SQ_WAVE_IB_DEP_VA_SDST_SIZE 0x00000004
16396#define SQ_WAVE_IB_DEP_VA_VCC_SIZE 0x00000003
16397#define SQ_WAVE_IB_DEP_VA_EXEC_SIZE 0x00000002
16398#define SQ_WAVE_IB_DEP_VA_VDST_SIZE 0x00000005
16399#define SQ_WAVE_IB_DEP_LDS_DIR_SIZE 0x00000003
16400
16401/*
16402 * SQ_EDC_FUE_CNTL_BITS value
16403 */
16404
16405#define SQ_EDC_FUE_CNTL_SIMD0 0x00000000
16406#define SQ_EDC_FUE_CNTL_SIMD1 0x00000001
16407#define SQ_EDC_FUE_CNTL_SIMD2 0x00000002
16408#define SQ_EDC_FUE_CNTL_SIMD3 0x00000003
16409#define SQ_EDC_FUE_CNTL_SQ 0x00000004
16410#define SQ_EDC_FUE_CNTL_LDS 0x00000005
16411#define SQ_EDC_FUE_CNTL_TD 0x00000006
16412#define SQ_EDC_FUE_CNTL_TA 0x00000007
16413#define SQ_EDC_FUE_CNTL_TCP 0x00000008
16414
16415/*******************************************************
16416 * COMP Enums
16417 *******************************************************/
16418
16419/*
16420 * CSCNTL_TYPE enum
16421 */
16422
16423typedef enum CSCNTL_TYPE {
16424CSCNTL_TYPE_TG = 0x00000000,
16425CSCNTL_TYPE_STATE = 0x00000001,
16426CSCNTL_TYPE_EVENT = 0x00000002,
16427CSCNTL_TYPE_PRIVATE = 0x00000003,
16428} CSCNTL_TYPE;
16429
16430/*
16431 * CSDATA_TYPE enum
16432 */
16433
16434typedef enum CSDATA_TYPE {
16435CSDATA_TYPE_TG = 0x00000000,
16436CSDATA_TYPE_STATE = 0x00000001,
16437CSDATA_TYPE_EVENT = 0x00000002,
16438CSDATA_TYPE_PRIVATE = 0x00000003,
16439} CSDATA_TYPE;
16440
16441/*
16442 * CSDATA_TYPE_WIDTH value
16443 */
16444
16445#define CSDATA_TYPE_WIDTH 0x00000002
16446
16447/*
16448 * CSDATA_ADDR_WIDTH value
16449 */
16450
16451#define CSDATA_ADDR_WIDTH 0x00000007
16452
16453/*
16454 * CSDATA_DATA_WIDTH value
16455 */
16456
16457#define CSDATA_DATA_WIDTH 0x00000020
16458
16459/*
16460 * CSCNTL_TYPE_WIDTH value
16461 */
16462
16463#define CSCNTL_TYPE_WIDTH 0x00000002
16464
16465/*
16466 * CSCNTL_ADDR_WIDTH value
16467 */
16468
16469#define CSCNTL_ADDR_WIDTH 0x00000007
16470
16471/*
16472 * CSCNTL_DATA_WIDTH value
16473 */
16474
16475#define CSCNTL_DATA_WIDTH 0x00000020
16476
16477/*******************************************************
16478 * GE Enums
16479 *******************************************************/
16480
16481/*
16482 * GE1_PERFCOUNT_SELECT enum
16483 */
16484
16485typedef enum GE1_PERFCOUNT_SELECT {
16486ge1_assembler_busy = 0x00000000,
16487ge1_assembler_stalled = 0x00000001,
16488ge1_dma_busy = 0x00000002,
16489ge1_dma_lat_bin_0 = 0x00000003,
16490ge1_dma_lat_bin_1 = 0x00000004,
16491ge1_dma_lat_bin_2 = 0x00000005,
16492ge1_dma_lat_bin_3 = 0x00000006,
16493ge1_dma_lat_bin_4 = 0x00000007,
16494ge1_dma_lat_bin_5 = 0x00000008,
16495ge1_dma_lat_bin_6 = 0x00000009,
16496ge1_dma_lat_bin_7 = 0x0000000a,
16497ge1_dma_return_cl0 = 0x0000000b,
16498ge1_dma_return_cl1 = 0x0000000c,
16499ge1_dma_utcl1_consecutive_retry_event = 0x0000000d,
16500ge1_dma_utcl1_request_event = 0x0000000e,
16501ge1_dma_utcl1_retry_event = 0x0000000f,
16502ge1_dma_utcl1_stall_event = 0x00000010,
16503ge1_dma_utcl1_stall_utcl2_event = 0x00000011,
16504ge1_dma_utcl1_translation_hit_event = 0x00000012,
16505ge1_dma_utcl1_translation_miss_event = 0x00000013,
16506ge1_assembler_dma_starved = 0x00000014,
16507ge1_rbiu_di_fifo_stalled_p0 = 0x00000015,
16508ge1_rbiu_di_fifo_starved_p0 = 0x00000016,
16509ge1_rbiu_dr_fifo_stalled_p0 = 0x00000017,
16510ge1_rbiu_dr_fifo_starved_p0 = 0x00000018,
16511ge1_sclk_reg_vld = 0x00000019,
16512ge1_stat_busy = 0x0000001a,
16513ge1_stat_no_dma_busy = 0x0000001b,
16514ge1_pipe0_to_pipe1 = 0x0000001c,
16515ge1_pipe1_to_pipe0 = 0x0000001d,
16516ge1_dma_return_size_cl0 = 0x0000001e,
16517ge1_dma_return_size_cl1 = 0x0000001f,
16518ge1_small_draws_one_instance = 0x00000020,
16519ge1_sclk_input_vld = 0x00000021,
16520ge1_prim_group_limit_hit = 0x00000022,
16521ge1_unopt_multi_instance_draws = 0x00000023,
16522ge1_rbiu_di_fifo_stalled_p1 = 0x00000024,
16523ge1_rbiu_di_fifo_starved_p1 = 0x00000025,
16524ge1_rbiu_dr_fifo_stalled_p1 = 0x00000026,
16525ge1_rbiu_dr_fifo_starved_p1 = 0x00000027,
16526} GE1_PERFCOUNT_SELECT;
16527
16528/*
16529 * GE2_DIST_PERFCOUNT_SELECT enum
16530 */
16531
16532typedef enum GE2_DIST_PERFCOUNT_SELECT {
16533ge_dist_hs_done = 0x00000000,
16534ge_dist_hs_done_latency_se0 = 0x00000001,
16535ge_dist_hs_done_latency_se1 = 0x00000002,
16536ge_dist_hs_done_latency_se2 = 0x00000003,
16537ge_dist_hs_done_latency_se3 = 0x00000004,
16538ge_dist_hs_done_latency_se4 = 0x00000005,
16539ge_dist_hs_done_latency_se5 = 0x00000006,
16540ge_dist_hs_done_latency_se6 = 0x00000007,
16541ge_dist_hs_done_latency_se7 = 0x00000008,
16542ge_dist_inside_tf_bin_0 = 0x00000009,
16543ge_dist_inside_tf_bin_1 = 0x0000000a,
16544ge_dist_inside_tf_bin_2 = 0x0000000b,
16545ge_dist_inside_tf_bin_3 = 0x0000000c,
16546ge_dist_inside_tf_bin_4 = 0x0000000d,
16547ge_dist_inside_tf_bin_5 = 0x0000000e,
16548ge_dist_inside_tf_bin_6 = 0x0000000f,
16549ge_dist_inside_tf_bin_7 = 0x00000010,
16550ge_dist_inside_tf_bin_8 = 0x00000011,
16551ge_dist_null_patch = 0x00000012,
16552ge_dist_sclk_core_vld = 0x00000013,
16553ge_dist_sclk_wd_te11_vld = 0x00000014,
16554ge_dist_tfreq_lat_bin_0 = 0x00000015,
16555ge_dist_tfreq_lat_bin_1 = 0x00000016,
16556ge_dist_tfreq_lat_bin_2 = 0x00000017,
16557ge_dist_tfreq_lat_bin_3 = 0x00000018,
16558ge_dist_tfreq_lat_bin_4 = 0x00000019,
16559ge_dist_tfreq_lat_bin_5 = 0x0000001a,
16560ge_dist_tfreq_lat_bin_6 = 0x0000001b,
16561ge_dist_tfreq_lat_bin_7 = 0x0000001c,
16562ge_dist_tfreq_utcl1_consecutive_retry_event = 0x0000001d,
16563ge_dist_tfreq_utcl1_request_event = 0x0000001e,
16564ge_dist_tfreq_utcl1_retry_event = 0x0000001f,
16565ge_dist_tfreq_utcl1_stall_event = 0x00000020,
16566ge_dist_tfreq_utcl1_stall_utcl2_event = 0x00000021,
16567ge_dist_tfreq_utcl1_translation_hit_event = 0x00000022,
16568ge_dist_tfreq_utcl1_translation_miss_event = 0x00000023,
16569ge_dist_vs_pc_stall = 0x00000024,
16570ge_dist_pc_feorder_fifo_full = 0x00000025,
16571ge_dist_pc_ge_manager_busy = 0x00000026,
16572ge_dist_pc_req_stall_se0 = 0x00000027,
16573ge_dist_pc_req_stall_se1 = 0x00000028,
16574ge_dist_pc_req_stall_se2 = 0x00000029,
16575ge_dist_pc_req_stall_se3 = 0x0000002a,
16576ge_dist_pc_req_stall_se4 = 0x0000002b,
16577ge_dist_pc_req_stall_se5 = 0x0000002c,
16578ge_dist_pc_req_stall_se6 = 0x0000002d,
16579ge_dist_pc_req_stall_se7 = 0x0000002e,
16580ge_dist_pc_space_zero = 0x0000002f,
16581ge_dist_sclk_input_vld = 0x00000030,
16582ge_dist_reserved = 0x00000031,
16583ge_dist_wd_te11_busy = 0x00000032,
16584ge_dist_te11_starved = 0x00000033,
16585ge_dist_switch_mode_stall = 0x00000034,
16586ge_all_tf_eq = 0x00000035,
16587ge_all_tf2 = 0x00000036,
16588ge_all_tf3 = 0x00000037,
16589ge_all_tf4 = 0x00000038,
16590ge_all_tf5 = 0x00000039,
16591ge_all_tf6 = 0x0000003a,
16592ge_se0_te11_starved_on_hs_done = 0x0000003b,
16593ge_se1_te11_starved_on_hs_done = 0x0000003c,
16594ge_se2_te11_starved_on_hs_done = 0x0000003d,
16595ge_se3_te11_starved_on_hs_done = 0x0000003e,
16596ge_se4_te11_starved_on_hs_done = 0x0000003f,
16597ge_se5_te11_starved_on_hs_done = 0x00000040,
16598ge_se6_te11_starved_on_hs_done = 0x00000041,
16599ge_se7_te11_starved_on_hs_done = 0x00000042,
16600ge_dist_op_fifo_full_starve = 0x00000043,
16601ge_dist_hs_done_se0 = 0x00000044,
16602ge_dist_hs_done_se1 = 0x00000045,
16603ge_dist_hs_done_se2 = 0x00000046,
16604ge_dist_hs_done_se3 = 0x00000047,
16605ge_dist_hs_done_se4 = 0x00000048,
16606ge_dist_hs_done_se5 = 0x00000049,
16607ge_dist_hs_done_se6 = 0x0000004a,
16608ge_dist_hs_done_se7 = 0x0000004b,
16609ge_dist_hs_done_latency = 0x0000004c,
16610ge_dist_distributer_busy = 0x0000004d,
16611ge_tf_ret_data_stalling_hs_done = 0x0000004e,
16612ge_num_of_no_dist_patches = 0x0000004f,
16613ge_num_of_donut_dist_patches = 0x00000050,
16614ge_num_of_patch_dist_patches = 0x00000051,
16615ge_num_of_se_switches_due_to_patch_accum = 0x00000052,
16616ge_num_of_se_switches_due_to_donut = 0x00000053,
16617ge_num_of_se_switches_due_to_trap = 0x00000054,
16618ge_num_of_hs_alloc_events = 0x00000055,
16619ge_agm_gcr_req = 0x00000056,
16620ge_agm_gcr_tag_stall = 0x00000057,
16621ge_agm_gcr_crd_stall = 0x00000058,
16622ge_agm_gcr_stall = 0x00000059,
16623ge_agm_gcr_latency = 0x0000005a,
16624ge_distclk_vld = 0x0000005b,
16625} GE2_DIST_PERFCOUNT_SELECT;
16626
16627/*
16628 * GE2_SE_PERFCOUNT_SELECT enum
16629 */
16630
16631typedef enum GE2_SE_PERFCOUNT_SELECT {
16632ge_se_ds_prims = 0x00000000,
16633ge_se_es_thread_groups = 0x00000001,
16634ge_se_esvert_stalled_gsprim = 0x00000002,
16635ge_se_hs_tfm_stall = 0x00000003,
16636ge_se_hs_tgs_active_high_water_mark = 0x00000004,
16637ge_se_hs_thread_groups = 0x00000005,
16638ge_se_reused_es_indices = 0x00000006,
16639ge_se_sclk_ngg_vld = 0x00000007,
16640ge_se_sclk_te11_vld = 0x00000008,
16641ge_se_spi_esvert_eov = 0x00000009,
16642ge_se_spi_esvert_stalled = 0x0000000a,
16643ge_se_spi_esvert_starved_busy = 0x0000000b,
16644ge_se_spi_esvert_valid = 0x0000000c,
16645ge_se_spi_gsprim_cont = 0x0000000d,
16646ge_se_spi_gsprim_eov = 0x0000000e,
16647ge_se_spi_gsprim_stalled = 0x0000000f,
16648ge_se_spi_gsprim_starved_busy = 0x00000010,
16649ge_se_spi_gsprim_valid = 0x00000011,
16650ge_se_spi_gssubgrp_is_event = 0x00000012,
16651ge_se_spi_gssubgrp_send = 0x00000013,
16652ge_se_spi_hsvert_eov = 0x00000014,
16653ge_se_spi_hsvert_stalled = 0x00000015,
16654ge_se_spi_hsvert_starved_busy = 0x00000016,
16655ge_se_spi_hsvert_valid = 0x00000017,
16656ge_se_spi_hswave_is_event = 0x00000018,
16657ge_se_spi_hswave_send = 0x00000019,
16658ge_se_spi_lsvert_eov = 0x0000001a,
16659ge_se_spi_lsvert_stalled = 0x0000001b,
16660ge_se_spi_lsvert_starved_busy = 0x0000001c,
16661ge_se_spi_lsvert_valid = 0x0000001d,
16662ge_se_spi_hsvert_fifo_full_stall = 0x0000001e,
16663ge_se_spi_tgrp_fifo_stall = 0x0000001f,
16664ge_spi_hsgrp_spi_stall = 0x00000020,
16665ge_se_spi_gssubgrp_event_window_active = 0x00000021,
16666ge_se_hs_input_stall = 0x00000022,
16667ge_se_sending_vert_or_prim = 0x00000023,
16668ge_se_sclk_input_vld = 0x00000024,
16669ge_spi_lswave_fifo_full_stall = 0x00000025,
16670ge_spi_hswave_fifo_full_stall = 0x00000026,
16671ge_hs_tif_stall = 0x00000027,
16672ge_csb_spi_bp = 0x00000028,
16673ge_ngg_starving_for_pc_grant = 0x00000029,
16674ge_pa0_csb_eop = 0x0000002a,
16675ge_pa1_csb_eop = 0x0000002b,
16676ge_ngg_starved_idle = 0x0000002c,
16677ge_gsprim_send = 0x0000002d,
16678ge_esvert_send = 0x0000002e,
16679ge_ngg_starved_after_work = 0x0000002f,
16680ge_ngg_subgrp_fifo_stall = 0x00000030,
16681ge_ngg_ord_id_req_stall = 0x00000031,
16682ge_ngg_indx_bus_stall = 0x00000032,
16683ge_hs_stall_tfmm_fifo_full = 0x00000033,
16684ge_gs_issue_rtr_stalled = 0x00000034,
16685ge_gsprim_stalled_esvert = 0x00000035,
16686ge_gsthread_stalled = 0x00000036,
16687ge_te11_stall_prim_funnel = 0x00000037,
16688ge_te11_stall_vert_funnel = 0x00000038,
16689ge_ngg_attr_grp_alloc = 0x00000039,
16690ge_ngg_attr_discard_alloc = 0x0000003a,
16691ge_ngg_pc_space_not_avail = 0x0000003b,
16692ge_ngg_agm_req_stall = 0x0000003c,
16693ge_ngg_spi_esvert_partial_eov = 0x0000003d,
16694ge_ngg_spi_gsprim_partial_eov = 0x0000003e,
16695ge_spi_gsgrp_valid = 0x0000003f,
16696ge_ngg_attr_grp_latency = 0x00000040,
16697ge_ngg_reuse_prim_limit_hit = 0x00000041,
16698ge_ngg_reuse_vert_limit_hit = 0x00000042,
16699ge_te11_con_stall = 0x00000043,
16700ge_te11_compactor_starved = 0x00000044,
16701ge_ngg_stall_tess_off_tess_on = 0x00000045,
16702ge_ngg_stall_tess_on_tess_off = 0x00000046,
16703} GE2_SE_PERFCOUNT_SELECT;
16704
16705/*
16706 * VGT_DETECT_ONE enum
16707 */
16708
16709typedef enum VGT_DETECT_ONE {
16710ENABLE_TF1_OPT = 0x00000000,
16711DISABLE_TF1_OPT = 0x00000001,
16712} VGT_DETECT_ONE;
16713
16714/*
16715 * VGT_DETECT_ZERO enum
16716 */
16717
16718typedef enum VGT_DETECT_ZERO {
16719ENABLE_TF0_OPT = 0x00000000,
16720DISABLE_TF0_OPT = 0x00000001,
16721} VGT_DETECT_ZERO;
16722
16723/*
16724 * VGT_DIST_MODE enum
16725 */
16726
16727typedef enum VGT_DIST_MODE {
16728NO_DIST = 0x00000000,
16729PATCHES = 0x00000001,
16730DONUTS = 0x00000002,
16731TRAPEZOIDS = 0x00000003,
16732} VGT_DIST_MODE;
16733
16734/*
16735 * VGT_DI_INDEX_SIZE enum
16736 */
16737
16738typedef enum VGT_DI_INDEX_SIZE {
16739DI_INDEX_SIZE_16_BIT = 0x00000000,
16740DI_INDEX_SIZE_32_BIT = 0x00000001,
16741DI_INDEX_SIZE_8_BIT = 0x00000002,
16742} VGT_DI_INDEX_SIZE;
16743
16744/*
16745 * VGT_DI_MAJOR_MODE_SELECT enum
16746 */
16747
16748typedef enum VGT_DI_MAJOR_MODE_SELECT {
16749DI_MAJOR_MODE_0 = 0x00000000,
16750DI_MAJOR_MODE_1 = 0x00000001,
16751} VGT_DI_MAJOR_MODE_SELECT;
16752
16753/*
16754 * VGT_DI_PRIM_TYPE enum
16755 */
16756
16757typedef enum VGT_DI_PRIM_TYPE {
16758DI_PT_NONE = 0x00000000,
16759DI_PT_POINTLIST = 0x00000001,
16760DI_PT_LINELIST = 0x00000002,
16761DI_PT_LINESTRIP = 0x00000003,
16762DI_PT_TRILIST = 0x00000004,
16763DI_PT_TRIFAN = 0x00000005,
16764DI_PT_TRISTRIP = 0x00000006,
16765DI_PT_2D_RECTANGLE = 0x00000007,
16766DI_PT_UNUSED_1 = 0x00000008,
16767DI_PT_PATCH = 0x00000009,
16768DI_PT_LINELIST_ADJ = 0x0000000a,
16769DI_PT_LINESTRIP_ADJ = 0x0000000b,
16770DI_PT_TRILIST_ADJ = 0x0000000c,
16771DI_PT_TRISTRIP_ADJ = 0x0000000d,
16772DI_PT_UNUSED_3 = 0x0000000e,
16773DI_PT_UNUSED_4 = 0x0000000f,
16774DI_PT_UNUSED_5 = 0x00000010,
16775DI_PT_RECTLIST = 0x00000011,
16776DI_PT_LINELOOP = 0x00000012,
16777DI_PT_QUADLIST = 0x00000013,
16778DI_PT_QUADSTRIP = 0x00000014,
16779DI_PT_POLYGON = 0x00000015,
16780} VGT_DI_PRIM_TYPE;
16781
16782/*
16783 * VGT_DI_SOURCE_SELECT enum
16784 */
16785
16786typedef enum VGT_DI_SOURCE_SELECT {
16787DI_SRC_SEL_DMA = 0x00000000,
16788DI_SRC_SEL_IMMEDIATE = 0x00000001,
16789DI_SRC_SEL_AUTO_INDEX = 0x00000002,
16790DI_SRC_SEL_RESERVED = 0x00000003,
16791} VGT_DI_SOURCE_SELECT;
16792
16793/*
16794 * VGT_DMA_BUF_TYPE enum
16795 */
16796
16797typedef enum VGT_DMA_BUF_TYPE {
16798VGT_DMA_BUF_MEM = 0x00000000,
16799VGT_DMA_BUF_RING = 0x00000001,
16800VGT_DMA_BUF_SETUP = 0x00000002,
16801VGT_DMA_PTR_UPDATE = 0x00000003,
16802} VGT_DMA_BUF_TYPE;
16803
16804/*
16805 * VGT_DMA_SWAP_MODE enum
16806 */
16807
16808typedef enum VGT_DMA_SWAP_MODE {
16809VGT_DMA_SWAP_NONE = 0x00000000,
16810VGT_DMA_SWAP_16_BIT = 0x00000001,
16811VGT_DMA_SWAP_32_BIT = 0x00000002,
16812VGT_DMA_SWAP_WORD = 0x00000003,
16813} VGT_DMA_SWAP_MODE;
16814
16815/*
16816 * VGT_EVENT_TYPE enum
16817 */
16818
16819typedef enum VGT_EVENT_TYPE {
16820Reserved_0x00 = 0x00000000,
16821SAMPLE_STREAMOUTSTATS1 = 0x00000001,
16822SAMPLE_STREAMOUTSTATS2 = 0x00000002,
16823SAMPLE_STREAMOUTSTATS3 = 0x00000003,
16824CACHE_FLUSH_TS = 0x00000004,
16825CONTEXT_DONE = 0x00000005,
16826CACHE_FLUSH = 0x00000006,
16827CS_PARTIAL_FLUSH = 0x00000007,
16828VGT_STREAMOUT_SYNC = 0x00000008,
16829Reserved_0x09 = 0x00000009,
16830VGT_STREAMOUT_RESET = 0x0000000a,
16831END_OF_PIPE_INCR_DE = 0x0000000b,
16832END_OF_PIPE_IB_END = 0x0000000c,
16833RST_PIX_CNT = 0x0000000d,
16834BREAK_BATCH = 0x0000000e,
16835VS_PARTIAL_FLUSH = 0x0000000f,
16836PS_PARTIAL_FLUSH = 0x00000010,
16837FLUSH_HS_OUTPUT = 0x00000011,
16838FLUSH_DFSM = 0x00000012,
16839RESET_TO_LOWEST_VGT = 0x00000013,
16840CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014,
16841WAIT_SYNC = 0x00000015,
16842CACHE_FLUSH_AND_INV_EVENT = 0x00000016,
16843PERFCOUNTER_START = 0x00000017,
16844PERFCOUNTER_STOP = 0x00000018,
16845PIPELINESTAT_START = 0x00000019,
16846PIPELINESTAT_STOP = 0x0000001a,
16847PERFCOUNTER_SAMPLE = 0x0000001b,
16848FLUSH_ES_OUTPUT = 0x0000001c,
16849BIN_CONF_OVERRIDE_CHECK = 0x0000001d,
16850SAMPLE_PIPELINESTAT = 0x0000001e,
16851SO_VGTSTREAMOUT_FLUSH = 0x0000001f,
16852SAMPLE_STREAMOUTSTATS = 0x00000020,
16853RESET_VTX_CNT = 0x00000021,
16854BLOCK_CONTEXT_DONE = 0x00000022,
16855CS_CONTEXT_DONE = 0x00000023,
16856VGT_FLUSH = 0x00000024,
16857TGID_ROLLOVER = 0x00000025,
16858SQ_NON_EVENT = 0x00000026,
16859SC_SEND_DB_VPZ = 0x00000027,
16860BOTTOM_OF_PIPE_TS = 0x00000028,
16861FLUSH_SX_TS = 0x00000029,
16862DB_CACHE_FLUSH_AND_INV = 0x0000002a,
16863FLUSH_AND_INV_DB_DATA_TS = 0x0000002b,
16864FLUSH_AND_INV_DB_META = 0x0000002c,
16865FLUSH_AND_INV_CB_DATA_TS = 0x0000002d,
16866FLUSH_AND_INV_CB_META = 0x0000002e,
16867CS_DONE = 0x0000002f,
16868PS_DONE = 0x00000030,
16869FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031,
16870SX_CB_RAT_ACK_REQUEST = 0x00000032,
16871THREAD_TRACE_START = 0x00000033,
16872THREAD_TRACE_STOP = 0x00000034,
16873THREAD_TRACE_MARKER = 0x00000035,
16874THREAD_TRACE_DRAW = 0x00000036,
16875THREAD_TRACE_FINISH = 0x00000037,
16876PIXEL_PIPE_STAT_CONTROL = 0x00000038,
16877PIXEL_PIPE_STAT_DUMP = 0x00000039,
16878PIXEL_PIPE_STAT_RESET = 0x0000003a,
16879CONTEXT_SUSPEND = 0x0000003b,
16880OFFCHIP_HS_DEALLOC = 0x0000003c,
16881ENABLE_NGG_PIPELINE = 0x0000003d,
16882ENABLE_LEGACY_PIPELINE = 0x0000003e,
16883DRAW_DONE = 0x0000003f,
16884} VGT_EVENT_TYPE;
16885
16886/*
16887 * VGT_GROUP_CONV_SEL enum
16888 */
16889
16890typedef enum VGT_GROUP_CONV_SEL {
16891VGT_GRP_INDEX_16 = 0x00000000,
16892VGT_GRP_INDEX_32 = 0x00000001,
16893VGT_GRP_UINT_16 = 0x00000002,
16894VGT_GRP_UINT_32 = 0x00000003,
16895VGT_GRP_SINT_16 = 0x00000004,
16896VGT_GRP_SINT_32 = 0x00000005,
16897VGT_GRP_FLOAT_32 = 0x00000006,
16898VGT_GRP_AUTO_PRIM = 0x00000007,
16899VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008,
16900} VGT_GROUP_CONV_SEL;
16901
16902/*
16903 * VGT_GS_MODE_TYPE enum
16904 */
16905
16906typedef enum VGT_GS_MODE_TYPE {
16907GS_OFF = 0x00000000,
16908GS_SCENARIO_A = 0x00000001,
16909GS_SCENARIO_B = 0x00000002,
16910GS_SCENARIO_G = 0x00000003,
16911GS_SCENARIO_C = 0x00000004,
16912SPRITE_EN = 0x00000005,
16913} VGT_GS_MODE_TYPE;
16914
16915/*
16916 * VGT_GS_OUTPRIM_TYPE enum
16917 */
16918
16919typedef enum VGT_GS_OUTPRIM_TYPE {
16920POINTLIST = 0x00000000,
16921LINESTRIP = 0x00000001,
16922TRISTRIP = 0x00000002,
16923RECT_2D = 0x00000003,
16924RECTLIST = 0x00000004,
16925} VGT_GS_OUTPRIM_TYPE;
16926
16927/*
16928 * VGT_INDEX_TYPE_MODE enum
16929 */
16930
16931typedef enum VGT_INDEX_TYPE_MODE {
16932VGT_INDEX_16 = 0x00000000,
16933VGT_INDEX_32 = 0x00000001,
16934VGT_INDEX_8 = 0x00000002,
16935} VGT_INDEX_TYPE_MODE;
16936
16937/*
16938 * VGT_OUTPATH_SELECT enum
16939 */
16940
16941typedef enum VGT_OUTPATH_SELECT {
16942VGT_OUTPATH_VTX_REUSE = 0x00000000,
16943VGT_OUTPATH_GS_BLOCK = 0x00000001,
16944VGT_OUTPATH_HS_BLOCK = 0x00000002,
16945VGT_OUTPATH_PRIM_GEN = 0x00000003,
16946VGT_OUTPATH_TE_PRIM_GEN = 0x00000004,
16947VGT_OUTPATH_TE_GS_BLOCK = 0x00000005,
16948VGT_OUTPATH_TE_OUTPUT = 0x00000006,
16949} VGT_OUTPATH_SELECT;
16950
16951/*
16952 * VGT_OUT_PRIM_TYPE enum
16953 */
16954
16955typedef enum VGT_OUT_PRIM_TYPE {
16956VGT_OUT_POINT = 0x00000000,
16957VGT_OUT_LINE = 0x00000001,
16958VGT_OUT_TRI = 0x00000002,
16959VGT_OUT_RECT_V0 = 0x00000003,
16960VGT_OUT_RECT_V1 = 0x00000004,
16961VGT_OUT_RECT_V2 = 0x00000005,
16962VGT_OUT_RECT_V3 = 0x00000006,
16963VGT_OUT_2D_RECT = 0x00000007,
16964VGT_TE_QUAD = 0x00000008,
16965VGT_TE_PRIM_INDEX_LINE = 0x00000009,
16966VGT_TE_PRIM_INDEX_TRI = 0x0000000a,
16967VGT_TE_PRIM_INDEX_QUAD = 0x0000000b,
16968VGT_OUT_LINE_ADJ = 0x0000000c,
16969VGT_OUT_TRI_ADJ = 0x0000000d,
16970VGT_OUT_PATCH = 0x0000000e,
16971} VGT_OUT_PRIM_TYPE;
16972
16973/*
16974 * VGT_RDREQ_POLICY enum
16975 */
16976
16977typedef enum VGT_RDREQ_POLICY {
16978VGT_POLICY_LRU = 0x00000000,
16979VGT_POLICY_STREAM = 0x00000001,
16980VGT_POLICY_BYPASS = 0x00000002,
16981} VGT_RDREQ_POLICY;
16982
16983/*
16984 * VGT_STAGES_ES_EN enum
16985 */
16986
16987typedef enum VGT_STAGES_ES_EN {
16988ES_STAGE_OFF = 0x00000000,
16989ES_STAGE_DS = 0x00000001,
16990ES_STAGE_REAL = 0x00000002,
16991RESERVED_ES = 0x00000003,
16992} VGT_STAGES_ES_EN;
16993
16994/*
16995 * VGT_STAGES_GS_EN enum
16996 */
16997
16998typedef enum VGT_STAGES_GS_EN {
16999GS_STAGE_OFF = 0x00000000,
17000GS_STAGE_ON = 0x00000001,
17001} VGT_STAGES_GS_EN;
17002
17003/*
17004 * VGT_STAGES_HS_EN enum
17005 */
17006
17007typedef enum VGT_STAGES_HS_EN {
17008HS_STAGE_OFF = 0x00000000,
17009HS_STAGE_ON = 0x00000001,
17010} VGT_STAGES_HS_EN;
17011
17012/*
17013 * VGT_STAGES_LS_EN enum
17014 */
17015
17016typedef enum VGT_STAGES_LS_EN {
17017LS_STAGE_OFF = 0x00000000,
17018LS_STAGE_ON = 0x00000001,
17019CS_STAGE_ON = 0x00000002,
17020RESERVED_LS = 0x00000003,
17021} VGT_STAGES_LS_EN;
17022
17023/*
17024 * VGT_STAGES_VS_EN enum
17025 */
17026
17027typedef enum VGT_STAGES_VS_EN {
17028VS_STAGE_REAL = 0x00000000,
17029VS_STAGE_DS = 0x00000001,
17030VS_STAGE_COPY_SHADER = 0x00000002,
17031RESERVED_VS = 0x00000003,
17032} VGT_STAGES_VS_EN;
17033
17034/*
17035 * VGT_TESS_PARTITION enum
17036 */
17037
17038typedef enum VGT_TESS_PARTITION {
17039PART_INTEGER = 0x00000000,
17040PART_POW2 = 0x00000001,
17041PART_FRAC_ODD = 0x00000002,
17042PART_FRAC_EVEN = 0x00000003,
17043} VGT_TESS_PARTITION;
17044
17045/*
17046 * VGT_TESS_TOPOLOGY enum
17047 */
17048
17049typedef enum VGT_TESS_TOPOLOGY {
17050OUTPUT_POINT = 0x00000000,
17051OUTPUT_LINE = 0x00000001,
17052OUTPUT_TRIANGLE_CW = 0x00000002,
17053OUTPUT_TRIANGLE_CCW = 0x00000003,
17054} VGT_TESS_TOPOLOGY;
17055
17056/*
17057 * VGT_TESS_TYPE enum
17058 */
17059
17060typedef enum VGT_TESS_TYPE {
17061TESS_ISOLINE = 0x00000000,
17062TESS_TRIANGLE = 0x00000001,
17063TESS_QUAD = 0x00000002,
17064} VGT_TESS_TYPE;
17065
17066/*
17067 * WD_IA_DRAW_REG_XFER enum
17068 */
17069
17070typedef enum WD_IA_DRAW_REG_XFER {
17071WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0x00000000,
17072WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001,
17073WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 0x00000002,
17074WD_IA_DRAW_REG_XFER_GE_CNTL = 0x00000003,
17075WD_IA_DRAW_REG_XFER_GE_USER_VGPR_EN = 0x00000004,
17076WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM = 0x00000005,
17077WD_IA_DRAW_REG_XFER_FL_MS_WG_DIM_1 = 0x00000006,
17078WD_IA_DRAW_REG_XFER_FL_MS_TG_SIZE = 0x00000007,
17079WD_IA_DRAW_REG_XFER_FL_MS_EXP_ALLOC = 0x00000008,
17080} WD_IA_DRAW_REG_XFER;
17081
17082/*
17083 * WD_IA_DRAW_SOURCE enum
17084 */
17085
17086typedef enum WD_IA_DRAW_SOURCE {
17087WD_IA_DRAW_SOURCE_DMA = 0x00000000,
17088WD_IA_DRAW_SOURCE_IMMD = 0x00000001,
17089WD_IA_DRAW_SOURCE_AUTO = 0x00000002,
17090WD_IA_DRAW_SOURCE_OPAQ = 0x00000003,
17091} WD_IA_DRAW_SOURCE;
17092
17093/*
17094 * WD_IA_DRAW_TYPE enum
17095 */
17096
17097typedef enum WD_IA_DRAW_TYPE {
17098WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000,
17099WD_IA_DRAW_TYPE_REG_XFER = 0x00000001,
17100WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002,
17101WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003,
17102WD_IA_DRAW_TYPE_MIN_INDX = 0x00000004,
17103WD_IA_DRAW_TYPE_MAX_INDX = 0x00000005,
17104WD_IA_DRAW_TYPE_INDX_OFF = 0x00000006,
17105WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007,
17106} WD_IA_DRAW_TYPE;
17107
17108/*
17109 * GS_THREADID_SIZE value
17110 */
17111
17112#define GSTHREADID_SIZE 0x00000002
17113
17114/*******************************************************
17115 * GB Enums
17116 *******************************************************/
17117
17118/*
17119 * GB_EDC_DED_MODE enum
17120 */
17121
17122typedef enum GB_EDC_DED_MODE {
17123GB_EDC_DED_MODE_LOG = 0x00000000,
17124GB_EDC_DED_MODE_HALT = 0x00000001,
17125GB_EDC_DED_MODE_INT_HALT = 0x00000002,
17126} GB_EDC_DED_MODE;
17127
17128/*
17129 * VALUE_GB_TILING_CONFIG_TABLE_SIZE value
17130 */
17131
17132#define GB_TILING_CONFIG_TABLE_SIZE 0x00000020
17133
17134/*
17135 * VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value
17136 */
17137
17138#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x00000010
17139
17140/*******************************************************
17141 * GLX Enums
17142 *******************************************************/
17143
17144/*
17145 * CHA_PERF_SEL enum
17146 */
17147
17148typedef enum CHA_PERF_SEL {
17149CHA_PERF_SEL_BUSY = 0x00000000,
17150CHA_PERF_SEL_STALL_CHC0 = 0x00000001,
17151CHA_PERF_SEL_STALL_CHC1 = 0x00000002,
17152CHA_PERF_SEL_STALL_CHC2 = 0x00000003,
17153CHA_PERF_SEL_STALL_CHC3 = 0x00000004,
17154CHA_PERF_SEL_STALL_CHC4 = 0x00000005,
17155CHA_PERF_SEL_STALL_CHC5 = 0x00000006,
17156CHA_PERF_SEL_REQUEST_CHC0 = 0x00000007,
17157CHA_PERF_SEL_REQUEST_CHC1 = 0x00000008,
17158CHA_PERF_SEL_REQUEST_CHC2 = 0x00000009,
17159CHA_PERF_SEL_REQUEST_CHC3 = 0x0000000a,
17160CHA_PERF_SEL_REQUEST_CHC4 = 0x0000000b,
17161CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 0x0000000c,
17162CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 0x0000000d,
17163CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 0x0000000e,
17164CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 0x0000000f,
17165CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 0x00000010,
17166CHA_PERF_SEL_IO_32B_WDS_CHC0 = 0x00000011,
17167CHA_PERF_SEL_IO_32B_WDS_CHC1 = 0x00000012,
17168CHA_PERF_SEL_IO_32B_WDS_CHC2 = 0x00000013,
17169CHA_PERF_SEL_IO_32B_WDS_CHC3 = 0x00000014,
17170CHA_PERF_SEL_IO_32B_WDS_CHC4 = 0x00000015,
17171CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 0x00000016,
17172CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 0x00000017,
17173CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 0x00000018,
17174CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 0x00000019,
17175CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 0x0000001a,
17176CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 0x0000001b,
17177CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 0x0000001c,
17178CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 0x0000001d,
17179CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 0x0000001e,
17180CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 0x0000001f,
17181CHA_PERF_SEL_ARB_REQUESTS = 0x00000020,
17182CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000021,
17183CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 0x00000022,
17184CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 0x00000023,
17185CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 0x00000024,
17186CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 0x00000025,
17187CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 0x00000026,
17188CHA_PERF_SEL_CYCLE = 0x00000027,
17189} CHA_PERF_SEL;
17190
17191/*
17192 * CHCG_PERF_SEL enum
17193 */
17194
17195typedef enum CHCG_PERF_SEL {
17196CHCG_PERF_SEL_CYCLE = 0x00000000,
17197CHCG_PERF_SEL_BUSY = 0x00000001,
17198CHCG_PERF_SEL_STARVE = 0x00000002,
17199CHCG_PERF_SEL_ARB_RET_LEVEL = 0x00000003,
17200CHCG_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000004,
17201CHCG_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x00000005,
17202CHCG_PERF_SEL_REQ = 0x00000006,
17203CHCG_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x00000007,
17204CHCG_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000008,
17205CHCG_PERF_SEL_REQ_NOP_ACK = 0x00000009,
17206CHCG_PERF_SEL_REQ_NOP_RTN0 = 0x0000000a,
17207CHCG_PERF_SEL_REQ_READ = 0x0000000b,
17208CHCG_PERF_SEL_REQ_READ_128B = 0x0000000c,
17209CHCG_PERF_SEL_REQ_READ_32B = 0x0000000d,
17210CHCG_PERF_SEL_REQ_READ_64B = 0x0000000e,
17211CHCG_PERF_SEL_REQ_WRITE = 0x0000000f,
17212CHCG_PERF_SEL_REQ_WRITE_32B = 0x00000010,
17213CHCG_PERF_SEL_REQ_WRITE_64B = 0x00000011,
17214CHCG_PERF_SEL_STALL_GUS_GL1 = 0x00000012,
17215CHCG_PERF_SEL_STALL_BUFFER_FULL = 0x00000013,
17216CHCG_PERF_SEL_REQ_CLIENT0 = 0x00000014,
17217CHCG_PERF_SEL_REQ_CLIENT1 = 0x00000015,
17218CHCG_PERF_SEL_REQ_CLIENT2 = 0x00000016,
17219CHCG_PERF_SEL_REQ_CLIENT3 = 0x00000017,
17220CHCG_PERF_SEL_REQ_CLIENT4 = 0x00000018,
17221CHCG_PERF_SEL_REQ_CLIENT5 = 0x00000019,
17222CHCG_PERF_SEL_REQ_CLIENT6 = 0x0000001a,
17223CHCG_PERF_SEL_REQ_CLIENT7 = 0x0000001b,
17224CHCG_PERF_SEL_REQ_CLIENT8 = 0x0000001c,
17225CHCG_PERF_SEL_REQ_CLIENT9 = 0x0000001d,
17226CHCG_PERF_SEL_REQ_CLIENT10 = 0x0000001e,
17227CHCG_PERF_SEL_REQ_CLIENT11 = 0x0000001f,
17228CHCG_PERF_SEL_REQ_CLIENT12 = 0x00000020,
17229CHCG_PERF_SEL_REQ_CLIENT13 = 0x00000021,
17230CHCG_PERF_SEL_REQ_CLIENT14 = 0x00000022,
17231CHCG_PERF_SEL_REQ_CLIENT15 = 0x00000023,
17232CHCG_PERF_SEL_REQ_CLIENT16 = 0x00000024,
17233CHCG_PERF_SEL_REQ_CLIENT17 = 0x00000025,
17234CHCG_PERF_SEL_REQ_CLIENT18 = 0x00000026,
17235CHCG_PERF_SEL_REQ_CLIENT19 = 0x00000027,
17236CHCG_PERF_SEL_REQ_CLIENT20 = 0x00000028,
17237CHCG_PERF_SEL_REQ_CLIENT21 = 0x00000029,
17238CHCG_PERF_SEL_REQ_CLIENT22 = 0x0000002a,
17239CHCG_PERF_SEL_REQ_CLIENT23 = 0x0000002b,
17240} CHCG_PERF_SEL;
17241
17242/*
17243 * CHC_PERF_SEL enum
17244 */
17245
17246typedef enum CHC_PERF_SEL {
17247CHC_PERF_SEL_CYCLE = 0x00000000,
17248CHC_PERF_SEL_BUSY = 0x00000001,
17249CHC_PERF_SEL_STARVE = 0x00000002,
17250CHC_PERF_SEL_ARB_RET_LEVEL = 0x00000003,
17251CHC_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000004,
17252CHC_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x00000005,
17253CHC_PERF_SEL_REQ = 0x00000006,
17254CHC_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x00000007,
17255CHC_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000008,
17256CHC_PERF_SEL_REQ_NOP_ACK = 0x00000009,
17257CHC_PERF_SEL_REQ_NOP_RTN0 = 0x0000000a,
17258CHC_PERF_SEL_REQ_READ = 0x0000000b,
17259CHC_PERF_SEL_REQ_READ_128B = 0x0000000c,
17260CHC_PERF_SEL_REQ_READ_32B = 0x0000000d,
17261CHC_PERF_SEL_REQ_READ_64B = 0x0000000e,
17262CHC_PERF_SEL_REQ_WRITE = 0x0000000f,
17263CHC_PERF_SEL_REQ_WRITE_32B = 0x00000010,
17264CHC_PERF_SEL_REQ_WRITE_64B = 0x00000011,
17265CHC_PERF_SEL_STALL_GL2_GL1 = 0x00000012,
17266CHC_PERF_SEL_STALL_BUFFER_FULL = 0x00000013,
17267CHC_PERF_SEL_REQ_CLIENT0 = 0x00000014,
17268CHC_PERF_SEL_REQ_CLIENT1 = 0x00000015,
17269CHC_PERF_SEL_REQ_CLIENT2 = 0x00000016,
17270CHC_PERF_SEL_REQ_CLIENT3 = 0x00000017,
17271CHC_PERF_SEL_REQ_CLIENT4 = 0x00000018,
17272CHC_PERF_SEL_REQ_CLIENT5 = 0x00000019,
17273CHC_PERF_SEL_REQ_CLIENT6 = 0x0000001a,
17274CHC_PERF_SEL_REQ_CLIENT7 = 0x0000001b,
17275CHC_PERF_SEL_REQ_CLIENT8 = 0x0000001c,
17276CHC_PERF_SEL_REQ_CLIENT9 = 0x0000001d,
17277CHC_PERF_SEL_REQ_CLIENT10 = 0x0000001e,
17278CHC_PERF_SEL_REQ_CLIENT11 = 0x0000001f,
17279CHC_PERF_SEL_REQ_CLIENT12 = 0x00000020,
17280CHC_PERF_SEL_REQ_CLIENT13 = 0x00000021,
17281CHC_PERF_SEL_REQ_CLIENT14 = 0x00000022,
17282CHC_PERF_SEL_REQ_CLIENT15 = 0x00000023,
17283CHC_PERF_SEL_REQ_CLIENT16 = 0x00000024,
17284CHC_PERF_SEL_REQ_CLIENT17 = 0x00000025,
17285CHC_PERF_SEL_REQ_CLIENT18 = 0x00000026,
17286CHC_PERF_SEL_REQ_CLIENT19 = 0x00000027,
17287CHC_PERF_SEL_REQ_CLIENT20 = 0x00000028,
17288CHC_PERF_SEL_REQ_CLIENT21 = 0x00000029,
17289CHC_PERF_SEL_REQ_CLIENT22 = 0x0000002a,
17290CHC_PERF_SEL_REQ_CLIENT23 = 0x0000002b,
17291} CHC_PERF_SEL;
17292
17293/*
17294 * GL1A_PERF_SEL enum
17295 */
17296
17297typedef enum GL1A_PERF_SEL {
17298GL1A_PERF_SEL_BUSY = 0x00000000,
17299GL1A_PERF_SEL_STALL_GL1C0 = 0x00000001,
17300GL1A_PERF_SEL_STALL_GL1C1 = 0x00000002,
17301GL1A_PERF_SEL_STALL_GL1C2 = 0x00000003,
17302GL1A_PERF_SEL_STALL_GL1C3 = 0x00000004,
17303GL1A_PERF_SEL_REQUEST_GL1C0 = 0x00000005,
17304GL1A_PERF_SEL_REQUEST_GL1C1 = 0x00000006,
17305GL1A_PERF_SEL_REQUEST_GL1C2 = 0x00000007,
17306GL1A_PERF_SEL_REQUEST_GL1C3 = 0x00000008,
17307GL1A_PERF_SEL_WDS_32B_GL1C0 = 0x00000009,
17308GL1A_PERF_SEL_WDS_32B_GL1C1 = 0x0000000a,
17309GL1A_PERF_SEL_WDS_32B_GL1C2 = 0x0000000b,
17310GL1A_PERF_SEL_WDS_32B_GL1C3 = 0x0000000c,
17311GL1A_PERF_SEL_BURST_COUNT_GL1C0 = 0x0000000d,
17312GL1A_PERF_SEL_BURST_COUNT_GL1C1 = 0x0000000e,
17313GL1A_PERF_SEL_BURST_COUNT_GL1C2 = 0x0000000f,
17314GL1A_PERF_SEL_BURST_COUNT_GL1C3 = 0x00000010,
17315GL1A_PERF_SEL_ARB_REQUESTS = 0x00000011,
17316GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000012,
17317GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 0x00000013,
17318GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 0x00000014,
17319GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 0x00000015,
17320GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 0x00000016,
17321GL1A_PERF_SEL_CYCLE = 0x00000017,
17322} GL1A_PERF_SEL;
17323
17324/*
17325 * GL1C_PERF_SEL enum
17326 */
17327
17328typedef enum GL1C_PERF_SEL {
17329GL1C_PERF_SEL_CYCLE = 0x00000000,
17330GL1C_PERF_SEL_BUSY = 0x00000001,
17331GL1C_PERF_SEL_STARVE = 0x00000002,
17332GL1C_PERF_SEL_ARB_RET_LEVEL = 0x00000003,
17333GL1C_PERF_SEL_GL2_REQ_READ = 0x00000004,
17334GL1C_PERF_SEL_GL2_REQ_READ_128B = 0x00000005,
17335GL1C_PERF_SEL_GL2_REQ_READ_32B = 0x00000006,
17336GL1C_PERF_SEL_GL2_REQ_READ_64B = 0x00000007,
17337GL1C_PERF_SEL_GL2_REQ_READ_LATENCY = 0x00000008,
17338GL1C_PERF_SEL_GL2_REQ_WRITE = 0x00000009,
17339GL1C_PERF_SEL_GL2_REQ_WRITE_32B = 0x0000000a,
17340GL1C_PERF_SEL_GL2_REQ_WRITE_64B = 0x0000000b,
17341GL1C_PERF_SEL_GL2_REQ_WRITE_LATENCY = 0x0000000c,
17342GL1C_PERF_SEL_GL2_REQ_PREFETCH = 0x0000000d,
17343GL1C_PERF_SEL_REQ = 0x0000000e,
17344GL1C_PERF_SEL_REQ_ATOMIC_WITH_RET = 0x0000000f,
17345GL1C_PERF_SEL_REQ_ATOMIC_WITHOUT_RET = 0x00000010,
17346GL1C_PERF_SEL_REQ_SHADER_INV = 0x00000011,
17347GL1C_PERF_SEL_REQ_MISS = 0x00000012,
17348GL1C_PERF_SEL_REQ_NOP_ACK = 0x00000013,
17349GL1C_PERF_SEL_REQ_NOP_RTN0 = 0x00000014,
17350GL1C_PERF_SEL_REQ_READ = 0x00000015,
17351GL1C_PERF_SEL_REQ_READ_128B = 0x00000016,
17352GL1C_PERF_SEL_REQ_READ_32B = 0x00000017,
17353GL1C_PERF_SEL_REQ_READ_64B = 0x00000018,
17354GL1C_PERF_SEL_REQ_READ_POLICY_HIT_EVICT = 0x00000019,
17355GL1C_PERF_SEL_REQ_READ_POLICY_HIT_LRU = 0x0000001a,
17356GL1C_PERF_SEL_REQ_READ_POLICY_MISS_EVICT = 0x0000001b,
17357GL1C_PERF_SEL_REQ_WRITE = 0x0000001c,
17358GL1C_PERF_SEL_REQ_WRITE_32B = 0x0000001d,
17359GL1C_PERF_SEL_REQ_WRITE_64B = 0x0000001e,
17360GL1C_PERF_SEL_STALL_GL2_GL1 = 0x0000001f,
17361GL1C_PERF_SEL_STALL_LFIFO_FULL = 0x00000020,
17362GL1C_PERF_SEL_STALL_NO_AVAILABLE_ACK_ALLOC = 0x00000021,
17363GL1C_PERF_SEL_STALL_NOTHING_REPLACEABLE = 0x00000022,
17364GL1C_PERF_SEL_STALL_GCR_INV = 0x00000023,
17365GL1C_PERF_SEL_STALL_VM = 0x00000024,
17366GL1C_PERF_SEL_REQ_CLIENT0 = 0x00000025,
17367GL1C_PERF_SEL_REQ_CLIENT1 = 0x00000026,
17368GL1C_PERF_SEL_REQ_CLIENT2 = 0x00000027,
17369GL1C_PERF_SEL_REQ_CLIENT3 = 0x00000028,
17370GL1C_PERF_SEL_REQ_CLIENT4 = 0x00000029,
17371GL1C_PERF_SEL_REQ_CLIENT5 = 0x0000002a,
17372GL1C_PERF_SEL_REQ_CLIENT6 = 0x0000002b,
17373GL1C_PERF_SEL_REQ_CLIENT7 = 0x0000002c,
17374GL1C_PERF_SEL_REQ_CLIENT8 = 0x0000002d,
17375GL1C_PERF_SEL_REQ_CLIENT9 = 0x0000002e,
17376GL1C_PERF_SEL_REQ_CLIENT10 = 0x0000002f,
17377GL1C_PERF_SEL_REQ_CLIENT11 = 0x00000030,
17378GL1C_PERF_SEL_REQ_CLIENT12 = 0x00000031,
17379GL1C_PERF_SEL_REQ_CLIENT13 = 0x00000032,
17380GL1C_PERF_SEL_REQ_CLIENT14 = 0x00000033,
17381GL1C_PERF_SEL_REQ_CLIENT15 = 0x00000034,
17382GL1C_PERF_SEL_REQ_CLIENT16 = 0x00000035,
17383GL1C_PERF_SEL_REQ_CLIENT17 = 0x00000036,
17384GL1C_PERF_SEL_REQ_CLIENT18 = 0x00000037,
17385GL1C_PERF_SEL_REQ_CLIENT19 = 0x00000038,
17386GL1C_PERF_SEL_REQ_CLIENT20 = 0x00000039,
17387GL1C_PERF_SEL_REQ_CLIENT21 = 0x0000003a,
17388GL1C_PERF_SEL_REQ_CLIENT22 = 0x0000003b,
17389GL1C_PERF_SEL_REQ_CLIENT23 = 0x0000003c,
17390GL1C_PERF_SEL_REQ_CLIENT24 = 0x0000003d,
17391GL1C_PERF_SEL_REQ_CLIENT25 = 0x0000003e,
17392GL1C_PERF_SEL_REQ_CLIENT26 = 0x0000003f,
17393GL1C_PERF_SEL_REQ_CLIENT27 = 0x00000040,
17394GL1C_PERF_SEL_UTCL0_REQUEST = 0x00000041,
17395GL1C_PERF_SEL_UTCL0_TRANSLATION_HIT = 0x00000042,
17396GL1C_PERF_SEL_UTCL0_TRANSLATION_MISS = 0x00000043,
17397GL1C_PERF_SEL_UTCL0_PERMISSION_MISS = 0x00000044,
17398GL1C_PERF_SEL_UTCL0_MISS_UNDER_MISS = 0x00000045,
17399GL1C_PERF_SEL_UTCL0_LFIFO_FULL = 0x00000046,
17400GL1C_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 0x00000047,
17401GL1C_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 0x00000048,
17402GL1C_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 0x00000049,
17403GL1C_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 0x0000004a,
17404GL1C_PERF_SEL_UTCL0_STALL_MULTI_MISS = 0x0000004b,
17405GL1C_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x0000004c,
17406GL1C_PERF_SEL_UTCL0_UTCL1_PERM_FAULT = 0x0000004d,
17407GL1C_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 0x0000004e,
17408GL1C_PERF_SEL_UTCL0_UTCL1_INFLIGHT = 0x0000004f,
17409GL1C_PERF_SEL_UTCL0_INTERNAL_RETRY_REQ = 0x00000050,
17410GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_RETRY_FAULT = 0x00000051,
17411GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_PRT_FAULT = 0x00000052,
17412GL1C_PERF_SEL_UTCL0_UTCL1_XNACK_NO_RETRY_FAULT = 0x00000053,
17413} GL1C_PERF_SEL;
17414
17415/*******************************************************
17416 * GL1H Enums
17417 *******************************************************/
17418
17419/*
17420 * GL1H_REQ_PERF_SEL enum
17421 */
17422
17423typedef enum GL1H_REQ_PERF_SEL {
17424GL1H_REQ_PERF_SEL_BUSY = 0x00000000,
17425GL1H_REQ_PERF_SEL_STALL_GL1_0 = 0x00000001,
17426GL1H_REQ_PERF_SEL_STALL_GL1_1 = 0x00000002,
17427GL1H_REQ_PERF_SEL_REQUEST_GL1_0 = 0x00000003,
17428GL1H_REQ_PERF_SEL_REQUEST_GL1_1 = 0x00000004,
17429GL1H_REQ_PERF_SEL_WDS_32B_GL1_0 = 0x00000005,
17430GL1H_REQ_PERF_SEL_WDS_32B_GL1_1 = 0x00000006,
17431GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_0 = 0x00000007,
17432GL1H_REQ_PERF_SEL_BURST_COUNT_GL1_1 = 0x00000008,
17433GL1H_REQ_PERF_SEL_ARB_REQUESTS = 0x00000009,
17434GL1H_REQ_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x0000000a,
17435GL1H_REQ_PERF_SEL_CYCLE = 0x0000000b,
17436} GL1H_REQ_PERF_SEL;
17437
17438/*******************************************************
17439 * TA Enums
17440 *******************************************************/
17441
17442/*
17443 * TA_PERFCOUNT_SEL enum
17444 */
17445
17446typedef enum TA_PERFCOUNT_SEL {
17447TA_PERF_SEL_NULL = 0x00000000,
17448TA_PERF_SEL_image_sampler_has_offset_instructions = 0x00000001,
17449TA_PERF_SEL_image_sampler_has_bias_instructions = 0x00000002,
17450TA_PERF_SEL_image_sampler_has_reference_instructions = 0x00000003,
17451TA_PERF_SEL_image_sampler_has_ds_instructions = 0x00000004,
17452TA_PERF_SEL_image_sampler_has_dt_instructions = 0x00000005,
17453TA_PERF_SEL_image_sampler_has_dr_instructions = 0x00000006,
17454TA_PERF_SEL_gradient_busy = 0x00000007,
17455TA_PERF_SEL_gradient_fifo_busy = 0x00000008,
17456TA_PERF_SEL_lod_busy = 0x00000009,
17457TA_PERF_SEL_lod_fifo_busy = 0x0000000a,
17458TA_PERF_SEL_addresser_busy = 0x0000000b,
17459TA_PERF_SEL_addresser_fifo_busy = 0x0000000c,
17460TA_PERF_SEL_aligner_busy = 0x0000000d,
17461TA_PERF_SEL_write_path_busy = 0x0000000e,
17462TA_PERF_SEL_ta_busy = 0x0000000f,
17463TA_PERF_SEL_image_sampler_1_input_vgpr_instructions = 0x00000010,
17464TA_PERF_SEL_image_sampler_2_input_vgpr_instructions = 0x00000011,
17465TA_PERF_SEL_image_sampler_3_input_vgpr_instructions = 0x00000012,
17466TA_PERF_SEL_image_sampler_4_input_vgpr_instructions = 0x00000013,
17467TA_PERF_SEL_image_sampler_5_input_vgpr_instructions = 0x00000014,
17468TA_PERF_SEL_image_sampler_6_input_vgpr_instructions = 0x00000015,
17469TA_PERF_SEL_image_sampler_7_input_vgpr_instructions = 0x00000016,
17470TA_PERF_SEL_image_sampler_8_input_vgpr_instructions = 0x00000017,
17471TA_PERF_SEL_image_sampler_9_input_vgpr_instructions = 0x00000018,
17472TA_PERF_SEL_image_sampler_10_input_vgpr_instructions = 0x00000019,
17473TA_PERF_SEL_image_sampler_11_input_vgpr_instructions = 0x0000001a,
17474TA_PERF_SEL_image_sampler_12_input_vgpr_instructions = 0x0000001b,
17475TA_PERF_SEL_image_sampler_has_t_instructions = 0x0000001c,
17476TA_PERF_SEL_image_sampler_has_r_instructions = 0x0000001d,
17477TA_PERF_SEL_image_sampler_has_q_instructions = 0x0000001e,
17478TA_PERF_SEL_total_wavefronts = 0x00000020,
17479TA_PERF_SEL_gradient_cycles = 0x00000021,
17480TA_PERF_SEL_walker_cycles = 0x00000022,
17481TA_PERF_SEL_aligner_cycles = 0x00000023,
17482TA_PERF_SEL_image_wavefronts = 0x00000024,
17483TA_PERF_SEL_image_read_wavefronts = 0x00000025,
17484TA_PERF_SEL_image_store_wavefronts = 0x00000026,
17485TA_PERF_SEL_image_atomic_wavefronts = 0x00000027,
17486TA_PERF_SEL_image_sampler_total_cycles = 0x00000028,
17487TA_PERF_SEL_image_nosampler_total_cycles = 0x00000029,
17488TA_PERF_SEL_flat_total_cycles = 0x0000002a,
17489TA_PERF_SEL_bvh_total_cycles = 0x0000002b,
17490TA_PERF_SEL_buffer_wavefronts = 0x0000002c,
17491TA_PERF_SEL_buffer_load_wavefronts = 0x0000002d,
17492TA_PERF_SEL_buffer_store_wavefronts = 0x0000002e,
17493TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f,
17494TA_PERF_SEL_buffer_total_cycles = 0x00000031,
17495TA_PERF_SEL_buffer_1_address_input_vgpr_instructions = 0x00000032,
17496TA_PERF_SEL_buffer_2_address_input_vgpr_instructions = 0x00000033,
17497TA_PERF_SEL_buffer_has_index_instructions = 0x00000034,
17498TA_PERF_SEL_buffer_has_offset_instructions = 0x00000035,
17499TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036,
17500TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037,
17501TA_PERF_SEL_image_sampler_wavefronts = 0x00000038,
17502TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039,
17503TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a,
17504TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b,
17505TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c,
17506TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d,
17507TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e,
17508TA_PERF_SEL_aniso_gt1_cycle_quads = 0x0000003f,
17509TA_PERF_SEL_color_1_cycle_quads = 0x00000040,
17510TA_PERF_SEL_color_2_cycle_quads = 0x00000041,
17511TA_PERF_SEL_color_3_cycle_quads = 0x00000042,
17512TA_PERF_SEL_mip_1_cycle_quads = 0x00000044,
17513TA_PERF_SEL_mip_2_cycle_quads = 0x00000045,
17514TA_PERF_SEL_vol_1_cycle_quads = 0x00000046,
17515TA_PERF_SEL_vol_2_cycle_quads = 0x00000047,
17516TA_PERF_SEL_sampler_op_quads = 0x00000048,
17517TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049,
17518TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a,
17519TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b,
17520TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c,
17521TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d,
17522TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e,
17523TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f,
17524TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050,
17525TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051,
17526TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052,
17527TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053,
17528TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054,
17529TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055,
17530TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056,
17531TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057,
17532TA_PERF_SEL_mipmap_invalid_samples = 0x00000058,
17533TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059,
17534TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a,
17535TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b,
17536TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c,
17537TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d,
17538TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e,
17539TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f,
17540TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060,
17541TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061,
17542TA_PERF_SEL_store_write_data_input_cycles = 0x00000062,
17543TA_PERF_SEL_store_write_data_output_cycles = 0x00000063,
17544TA_PERF_SEL_flat_wavefronts = 0x00000064,
17545TA_PERF_SEL_flat_load_wavefronts = 0x00000065,
17546TA_PERF_SEL_flat_store_wavefronts = 0x00000066,
17547TA_PERF_SEL_flat_atomic_wavefronts = 0x00000067,
17548TA_PERF_SEL_flat_1_address_input_vgpr_instructions = 0x00000068,
17549TA_PERF_SEL_register_clk_valid_cycles = 0x00000069,
17550TA_PERF_SEL_non_harvestable_clk_enabled_cycles = 0x0000006a,
17551TA_PERF_SEL_harvestable_clk_enabled_cycles = 0x0000006b,
17552TA_PERF_SEL_harvestable_register_clk_enabled_cycles = 0x0000006c,
17553TA_PERF_SEL_boundary_non_harvestable_clk_enabled_cycles = 0x0000006d,
17554TA_PERF_SEL_boundary_harvestable_clk_enabled_cycles = 0x0000006e,
17555TA_PERF_SEL_store_2_write_data_vgpr_instructions = 0x00000072,
17556TA_PERF_SEL_store_3_write_data_vgpr_instructions = 0x00000073,
17557TA_PERF_SEL_store_4_write_data_vgpr_instructions = 0x00000074,
17558TA_PERF_SEL_store_has_x_instructions = 0x00000075,
17559TA_PERF_SEL_store_has_y_instructions = 0x00000076,
17560TA_PERF_SEL_store_has_z_instructions = 0x00000077,
17561TA_PERF_SEL_store_has_w_instructions = 0x00000078,
17562TA_PERF_SEL_image_nosampler_has_t_instructions = 0x00000079,
17563TA_PERF_SEL_image_nosampler_has_r_instructions = 0x0000007a,
17564TA_PERF_SEL_image_nosampler_has_q_instructions = 0x0000007b,
17565TA_PERF_SEL_image_nosampler_1_address_input_vgpr_instructions = 0x0000007c,
17566TA_PERF_SEL_image_nosampler_2_address_input_vgpr_instructions = 0x0000007d,
17567TA_PERF_SEL_image_nosampler_3_address_input_vgpr_instructions = 0x0000007e,
17568TA_PERF_SEL_image_nosampler_4_address_input_vgpr_instructions = 0x0000007f,
17569TA_PERF_SEL_in_busy = 0x00000080,
17570TA_PERF_SEL_in_fifos_busy = 0x00000081,
17571TA_PERF_SEL_in_cfifo_busy = 0x00000082,
17572TA_PERF_SEL_in_qfifo_busy = 0x00000083,
17573TA_PERF_SEL_in_wfifo_busy = 0x00000084,
17574TA_PERF_SEL_in_rfifo_busy = 0x00000085,
17575TA_PERF_SEL_bf_busy = 0x00000086,
17576TA_PERF_SEL_ns_busy = 0x00000087,
17577TA_PERF_SEL_smp_busy_ns_idle = 0x00000088,
17578TA_PERF_SEL_smp_idle_ns_busy = 0x00000089,
17579TA_PERF_SEL_vmemcmd_cycles = 0x00000090,
17580TA_PERF_SEL_vmemreq_cycles = 0x00000091,
17581TA_PERF_SEL_in_waiting_on_req_cycles = 0x00000092,
17582TA_PERF_SEL_in_addr_cycles = 0x00000096,
17583TA_PERF_SEL_in_data_cycles = 0x00000097,
17584TA_PERF_SEL_latency_ram_weights_written_cycles = 0x0000009a,
17585TA_PERF_SEL_latency_ram_ws_required_quads = 0x0000009b,
17586TA_PERF_SEL_latency_ram_whv_required_quads = 0x0000009c,
17587TA_PERF_SEL_latency_ram_ws_required_instructions = 0x0000009d,
17588TA_PERF_SEL_latency_ram_whv_required_instructions = 0x0000009e,
17589TA_PERF_SEL_latency_ram_ref_required_instructions = 0x0000009f,
17590TA_PERF_SEL_point_sampled_quads = 0x000000a0,
17591TA_PERF_SEL_atomic_2_write_data_vgpr_instructions = 0x000000a2,
17592TA_PERF_SEL_atomic_4_write_data_vgpr_instructions = 0x000000a3,
17593TA_PERF_SEL_atomic_write_data_input_cycles = 0x000000a4,
17594TA_PERF_SEL_atomic_write_data_output_cycles = 0x000000a5,
17595TA_PERF_SEL_num_unlit_nodes_ta_opt = 0x000000ad,
17596TA_PERF_SEL_num_nodes_invalidated_due_to_bad_input = 0x000000ae,
17597TA_PERF_SEL_num_nodes_invalidated_due_to_oob = 0x000000af,
17598TA_PERF_SEL_num_of_bvh_valid_first_tri = 0x000000b0,
17599TA_PERF_SEL_num_of_bvh_valid_second_tri = 0x000000b1,
17600TA_PERF_SEL_num_of_bvh_valid_third_tri = 0x000000b2,
17601TA_PERF_SEL_num_of_bvh_valid_fourth_tri = 0x000000b3,
17602TA_PERF_SEL_num_of_bvh_valid_fp16_box = 0x000000b4,
17603TA_PERF_SEL_num_of_bvh_valid_fp32_box = 0x000000b5,
17604TA_PERF_SEL_num_of_bvh_invalidated_first_tri = 0x000000b6,
17605TA_PERF_SEL_num_of_bvh_invalidated_second_tri = 0x000000b7,
17606TA_PERF_SEL_num_of_bvh_invalidated_third_tri = 0x000000b8,
17607TA_PERF_SEL_num_of_bvh_invalidated_fourth_tri = 0x000000b9,
17608TA_PERF_SEL_num_of_bvh_invalidated_fp16_box = 0x000000ba,
17609TA_PERF_SEL_num_of_bvh_invalidated_fp32_box = 0x000000bb,
17610TA_PERF_SEL_image_bvh_8_input_vgpr_instructions = 0x000000bc,
17611TA_PERF_SEL_image_bvh_9_input_vgpr_instructions = 0x000000bd,
17612TA_PERF_SEL_image_bvh_11_input_vgpr_instructions = 0x000000be,
17613TA_PERF_SEL_image_bvh_12_input_vgpr_instructions = 0x000000bf,
17614TA_PERF_SEL_image_sampler_1_op_burst = 0x000000c0,
17615TA_PERF_SEL_image_sampler_2to3_op_burst = 0x000000c1,
17616TA_PERF_SEL_image_sampler_4to7_op_burst = 0x000000c2,
17617TA_PERF_SEL_image_sampler_ge8_op_burst = 0x000000c3,
17618TA_PERF_SEL_image_linked_1_op_burst = 0x000000c4,
17619TA_PERF_SEL_image_linked_2to3_op_burst = 0x000000c5,
17620TA_PERF_SEL_image_linked_4to7_op_burst = 0x000000c6,
17621TA_PERF_SEL_image_linked_ge8_op_burst = 0x000000c7,
17622TA_PERF_SEL_image_bvh_1_op_burst = 0x000000c8,
17623TA_PERF_SEL_image_bvh_2to3_op_burst = 0x000000c9,
17624TA_PERF_SEL_image_bvh_4to7_op_burst = 0x000000ca,
17625TA_PERF_SEL_image_bvh_ge8_op_burst = 0x000000cb,
17626TA_PERF_SEL_image_nosampler_1_op_burst = 0x000000cc,
17627TA_PERF_SEL_image_nosampler_2to3_op_burst = 0x000000cd,
17628TA_PERF_SEL_image_nosampler_4to31_op_burst = 0x000000ce,
17629TA_PERF_SEL_image_nosampler_ge32_op_burst = 0x000000cf,
17630TA_PERF_SEL_buffer_flat_1_op_burst = 0x000000d0,
17631TA_PERF_SEL_buffer_flat_2to3_op_burst = 0x000000d1,
17632TA_PERF_SEL_buffer_flat_4to31_op_burst = 0x000000d2,
17633TA_PERF_SEL_buffer_flat_ge32_op_burst = 0x000000d3,
17634TA_PERF_SEL_write_1_op_burst = 0x000000d4,
17635TA_PERF_SEL_write_2to3_op_burst = 0x000000d5,
17636TA_PERF_SEL_write_4to31_op_burst = 0x000000d6,
17637TA_PERF_SEL_write_ge32_op_burst = 0x000000d7,
17638TA_PERF_SEL_ibubble_1_cycle_burst = 0x000000d8,
17639TA_PERF_SEL_ibubble_2to3_cycle_burst = 0x000000d9,
17640TA_PERF_SEL_ibubble_4to15_cycle_burst = 0x000000da,
17641TA_PERF_SEL_ibubble_16to31_cycle_burst = 0x000000db,
17642TA_PERF_SEL_ibubble_32to63_cycle_burst = 0x000000dc,
17643TA_PERF_SEL_ibubble_ge64_cycle_burst = 0x000000dd,
17644TA_PERF_SEL_sampler_clk_valid_cycles = 0x000000e0,
17645TA_PERF_SEL_nonsampler_clk_valid_cycles = 0x000000e1,
17646TA_PERF_SEL_buffer_flat_clk_valid_cycles = 0x000000e2,
17647TA_PERF_SEL_write_data_clk_valid_cycles = 0x000000e3,
17648TA_PERF_SEL_gradient_clk_valid_cycles = 0x000000e4,
17649TA_PERF_SEL_lod_aniso_clk_valid_cycles = 0x000000e5,
17650TA_PERF_SEL_sampler_addressing_clk_valid_cycles = 0x000000e6,
17651TA_PERF_SEL_sync_sampler_sstate_fifo_clk_valid_cycles = 0x000000e7,
17652TA_PERF_SEL_sync_sampler_cstate_fifo_clk_valid_cycles = 0x000000e8,
17653TA_PERF_SEL_sync_nonsampler_fifo_clk_valid_cycles = 0x000000e9,
17654TA_PERF_SEL_aligner_clk_valid_cycles = 0x000000ea,
17655TA_PERF_SEL_tcreq_clk_valid_cycles = 0x000000eb,
17656} TA_PERFCOUNT_SEL;
17657
17658/*
17659 * TEX_BC_SWIZZLE enum
17660 */
17661
17662typedef enum TEX_BC_SWIZZLE {
17663TEX_BC_Swizzle_XYZW = 0x00000000,
17664TEX_BC_Swizzle_XWYZ = 0x00000001,
17665TEX_BC_Swizzle_WZYX = 0x00000002,
17666TEX_BC_Swizzle_WXYZ = 0x00000003,
17667TEX_BC_Swizzle_ZYXW = 0x00000004,
17668TEX_BC_Swizzle_YXWZ = 0x00000005,
17669} TEX_BC_SWIZZLE;
17670
17671/*
17672 * TEX_BORDER_COLOR_TYPE enum
17673 */
17674
17675typedef enum TEX_BORDER_COLOR_TYPE {
17676TEX_BorderColor_TransparentBlack = 0x00000000,
17677TEX_BorderColor_OpaqueBlack = 0x00000001,
17678TEX_BorderColor_OpaqueWhite = 0x00000002,
17679TEX_BorderColor_Register = 0x00000003,
17680} TEX_BORDER_COLOR_TYPE;
17681
17682/*
17683 * TEX_CHROMA_KEY enum
17684 */
17685
17686typedef enum TEX_CHROMA_KEY {
17687TEX_ChromaKey_Disabled = 0x00000000,
17688TEX_ChromaKey_Kill = 0x00000001,
17689TEX_ChromaKey_Blend = 0x00000002,
17690TEX_ChromaKey_RESERVED_3 = 0x00000003,
17691} TEX_CHROMA_KEY;
17692
17693/*
17694 * TEX_CLAMP enum
17695 */
17696
17697typedef enum TEX_CLAMP {
17698TEX_Clamp_Repeat = 0x00000000,
17699TEX_Clamp_Mirror = 0x00000001,
17700TEX_Clamp_ClampToLast = 0x00000002,
17701TEX_Clamp_MirrorOnceToLast = 0x00000003,
17702TEX_Clamp_ClampHalfToBorder = 0x00000004,
17703TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005,
17704TEX_Clamp_ClampToBorder = 0x00000006,
17705TEX_Clamp_MirrorOnceToBorder = 0x00000007,
17706} TEX_CLAMP;
17707
17708/*
17709 * TEX_COORD_TYPE enum
17710 */
17711
17712typedef enum TEX_COORD_TYPE {
17713TEX_CoordType_Unnormalized = 0x00000000,
17714TEX_CoordType_Normalized = 0x00000001,
17715} TEX_COORD_TYPE;
17716
17717/*
17718 * TEX_DEPTH_COMPARE_FUNCTION enum
17719 */
17720
17721typedef enum TEX_DEPTH_COMPARE_FUNCTION {
17722TEX_DepthCompareFunction_Never = 0x00000000,
17723TEX_DepthCompareFunction_Less = 0x00000001,
17724TEX_DepthCompareFunction_Equal = 0x00000002,
17725TEX_DepthCompareFunction_LessEqual = 0x00000003,
17726TEX_DepthCompareFunction_Greater = 0x00000004,
17727TEX_DepthCompareFunction_NotEqual = 0x00000005,
17728TEX_DepthCompareFunction_GreaterEqual = 0x00000006,
17729TEX_DepthCompareFunction_Always = 0x00000007,
17730} TEX_DEPTH_COMPARE_FUNCTION;
17731
17732/*
17733 * TEX_FORMAT_COMP enum
17734 */
17735
17736typedef enum TEX_FORMAT_COMP {
17737TEX_FormatComp_Unsigned = 0x00000000,
17738TEX_FormatComp_Signed = 0x00000001,
17739TEX_FormatComp_UnsignedBiased = 0x00000002,
17740TEX_FormatComp_RESERVED_3 = 0x00000003,
17741} TEX_FORMAT_COMP;
17742
17743/*
17744 * TEX_MAX_ANISO_RATIO enum
17745 */
17746
17747typedef enum TEX_MAX_ANISO_RATIO {
17748TEX_MaxAnisoRatio_1to1 = 0x00000000,
17749TEX_MaxAnisoRatio_2to1 = 0x00000001,
17750TEX_MaxAnisoRatio_4to1 = 0x00000002,
17751TEX_MaxAnisoRatio_8to1 = 0x00000003,
17752TEX_MaxAnisoRatio_16to1 = 0x00000004,
17753TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005,
17754TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006,
17755TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007,
17756} TEX_MAX_ANISO_RATIO;
17757
17758/*
17759 * TEX_MIP_FILTER enum
17760 */
17761
17762typedef enum TEX_MIP_FILTER {
17763TEX_MipFilter_None = 0x00000000,
17764TEX_MipFilter_Point = 0x00000001,
17765TEX_MipFilter_Linear = 0x00000002,
17766TEX_MipFilter_Point_Aniso_Adj = 0x00000003,
17767} TEX_MIP_FILTER;
17768
17769/*
17770 * TEX_REQUEST_SIZE enum
17771 */
17772
17773typedef enum TEX_REQUEST_SIZE {
17774TEX_RequestSize_32B = 0x00000000,
17775TEX_RequestSize_64B = 0x00000001,
17776TEX_RequestSize_128B = 0x00000002,
17777TEX_RequestSize_2X64B = 0x00000003,
17778} TEX_REQUEST_SIZE;
17779
17780/*
17781 * TEX_SAMPLER_TYPE enum
17782 */
17783
17784typedef enum TEX_SAMPLER_TYPE {
17785TEX_SamplerType_Invalid = 0x00000000,
17786TEX_SamplerType_Valid = 0x00000001,
17787} TEX_SAMPLER_TYPE;
17788
17789/*
17790 * TEX_XY_FILTER enum
17791 */
17792
17793typedef enum TEX_XY_FILTER {
17794TEX_XYFilter_Point = 0x00000000,
17795TEX_XYFilter_Linear = 0x00000001,
17796TEX_XYFilter_AnisoPoint = 0x00000002,
17797TEX_XYFilter_AnisoLinear = 0x00000003,
17798} TEX_XY_FILTER;
17799
17800/*
17801 * TEX_Z_FILTER enum
17802 */
17803
17804typedef enum TEX_Z_FILTER {
17805TEX_ZFilter_None = 0x00000000,
17806TEX_ZFilter_Point = 0x00000001,
17807TEX_ZFilter_Linear = 0x00000002,
17808TEX_ZFilter_RESERVED_3 = 0x00000003,
17809} TEX_Z_FILTER;
17810
17811/*
17812 * TVX_TYPE enum
17813 */
17814
17815typedef enum TVX_TYPE {
17816TVX_Type_InvalidTextureResource = 0x00000000,
17817TVX_Type_InvalidVertexBuffer = 0x00000001,
17818TVX_Type_ValidTextureResource = 0x00000002,
17819TVX_Type_ValidVertexBuffer = 0x00000003,
17820} TVX_TYPE;
17821
17822/*******************************************************
17823 * TCP Enums
17824 *******************************************************/
17825
17826/*
17827 * TA_TC_ADDR_MODES enum
17828 */
17829
17830typedef enum TA_TC_ADDR_MODES {
17831TA_TC_ADDR_MODE_DEFAULT = 0x00000000,
17832TA_TC_ADDR_MODE_COMP0 = 0x00000001,
17833TA_TC_ADDR_MODE_COMP1 = 0x00000002,
17834TA_TC_ADDR_MODE_COMP2 = 0x00000003,
17835TA_TC_ADDR_MODE_COMP3 = 0x00000004,
17836TA_TC_ADDR_MODE_UNALIGNED = 0x00000005,
17837TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006,
17838} TA_TC_ADDR_MODES;
17839
17840/*
17841 * TA_TC_REQ_MODES enum
17842 */
17843
17844typedef enum TA_TC_REQ_MODES {
17845TA_TC_REQ_MODE_BORDER = 0x00000000,
17846TA_TC_REQ_MODE_TEX2 = 0x00000001,
17847TA_TC_REQ_MODE_TEX1 = 0x00000002,
17848TA_TC_REQ_MODE_TEX0 = 0x00000003,
17849TA_TC_REQ_MODE_NORMAL = 0x00000004,
17850TA_TC_REQ_MODE_DWORD = 0x00000005,
17851TA_TC_REQ_MODE_BYTE = 0x00000006,
17852TA_TC_REQ_MODE_BYTE_NV = 0x00000007,
17853} TA_TC_REQ_MODES;
17854
17855/*
17856 * TCP_CACHE_POLICIES enum
17857 */
17858
17859typedef enum TCP_CACHE_POLICIES {
17860TCP_CACHE_POLICY_MISS_LRU = 0x00000000,
17861TCP_CACHE_POLICY_MISS_EVICT = 0x00000001,
17862TCP_CACHE_POLICY_HIT_LRU = 0x00000002,
17863TCP_CACHE_POLICY_HIT_EVICT = 0x00000003,
17864} TCP_CACHE_POLICIES;
17865
17866/*
17867 * TCP_CACHE_STORE_POLICIES enum
17868 */
17869
17870typedef enum TCP_CACHE_STORE_POLICIES {
17871TCP_CACHE_STORE_POLICY_WT_LRU = 0x00000000,
17872TCP_CACHE_STORE_POLICY_WT_EVICT = 0x00000001,
17873} TCP_CACHE_STORE_POLICIES;
17874
17875/*
17876 * TCP_DSM_DATA_SEL enum
17877 */
17878
17879typedef enum TCP_DSM_DATA_SEL {
17880TCP_DSM_DISABLE = 0x00000000,
17881TCP_DSM_SEL0 = 0x00000001,
17882TCP_DSM_SEL1 = 0x00000002,
17883TCP_DSM_SEL_BOTH = 0x00000003,
17884} TCP_DSM_DATA_SEL;
17885
17886/*
17887 * TCP_DSM_INJECT_SEL enum
17888 */
17889
17890typedef enum TCP_DSM_INJECT_SEL {
17891TCP_DSM_INJECT_SEL0 = 0x00000000,
17892TCP_DSM_INJECT_SEL1 = 0x00000001,
17893TCP_DSM_INJECT_SEL2 = 0x00000002,
17894TCP_DSM_INJECT_SEL3 = 0x00000003,
17895} TCP_DSM_INJECT_SEL;
17896
17897/*
17898 * TCP_DSM_SINGLE_WRITE enum
17899 */
17900
17901typedef enum TCP_DSM_SINGLE_WRITE {
17902TCP_DSM_SINGLE_WRITE_DIS = 0x00000000,
17903TCP_DSM_SINGLE_WRITE_EN = 0x00000001,
17904} TCP_DSM_SINGLE_WRITE;
17905
17906/*
17907 * TCP_OPCODE_TYPE enum
17908 */
17909
17910typedef enum TCP_OPCODE_TYPE {
17911TCP_OPCODE_READ = 0x00000000,
17912TCP_OPCODE_WRITE = 0x00000001,
17913TCP_OPCODE_ATOMIC = 0x00000002,
17914TCP_OPCODE_INV = 0x00000003,
17915TCP_OPCODE_ATOMIC_CMPSWAP = 0x00000004,
17916TCP_OPCODE_SAMPLER = 0x00000005,
17917TCP_OPCODE_LOAD = 0x00000006,
17918TCP_OPCODE_GATHERH = 0x00000007,
17919} TCP_OPCODE_TYPE;
17920
17921/*
17922 * TCP_PERFCOUNT_SELECT enum
17923 */
17924
17925typedef enum TCP_PERFCOUNT_SELECT {
17926TCP_PERF_SEL_GATE_EN1 = 0x00000000,
17927TCP_PERF_SEL_GATE_EN2 = 0x00000001,
17928TCP_PERF_SEL_TA_REQ = 0x00000002,
17929TCP_PERF_SEL_TA_REQ_STATE_READ = 0x00000003,
17930TCP_PERF_SEL_TA_REQ_READ = 0x00000004,
17931TCP_PERF_SEL_TA_REQ_WRITE = 0x00000005,
17932TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 0x00000006,
17933TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 0x00000007,
17934TCP_PERF_SEL_TA_REQ_GL0_INV = 0x00000008,
17935TCP_PERF_SEL_REQ = 0x00000009,
17936TCP_PERF_SEL_REQ_READ = 0x0000000a,
17937TCP_PERF_SEL_REQ_READ_HIT_EVICT = 0x0000000b,
17938TCP_PERF_SEL_REQ_READ_HIT_LRU = 0x0000000c,
17939TCP_PERF_SEL_REQ_READ_MISS_EVICT = 0x0000000d,
17940TCP_PERF_SEL_REQ_WRITE = 0x0000000e,
17941TCP_PERF_SEL_REQ_WRITE_MISS_EVICT = 0x0000000f,
17942TCP_PERF_SEL_REQ_WRITE_MISS_LRU = 0x00000010,
17943TCP_PERF_SEL_REQ_NON_READ = 0x00000011,
17944TCP_PERF_SEL_REQ_MISS = 0x00000012,
17945TCP_PERF_SEL_REQ_TAGBANK0_SET0 = 0x00000013,
17946TCP_PERF_SEL_REQ_TAGBANK0_SET1 = 0x00000014,
17947TCP_PERF_SEL_REQ_TAGBANK1_SET0 = 0x00000015,
17948TCP_PERF_SEL_REQ_TAGBANK1_SET1 = 0x00000016,
17949TCP_PERF_SEL_REQ_TAGBANK2_SET0 = 0x00000017,
17950TCP_PERF_SEL_REQ_TAGBANK2_SET1 = 0x00000018,
17951TCP_PERF_SEL_REQ_TAGBANK3_SET0 = 0x00000019,
17952TCP_PERF_SEL_REQ_TAGBANK3_SET1 = 0x0000001a,
17953TCP_PERF_SEL_REQ_MISS_TAGBANK0 = 0x0000001b,
17954TCP_PERF_SEL_REQ_MISS_TAGBANK1 = 0x0000001c,
17955TCP_PERF_SEL_REQ_MISS_TAGBANK2 = 0x0000001d,
17956TCP_PERF_SEL_REQ_MISS_TAGBANK3 = 0x0000001e,
17957TCP_PERF_SEL_GL1_REQ_READ = 0x0000001f,
17958TCP_PERF_SEL_GL1_REQ_READ_128B = 0x00000020,
17959TCP_PERF_SEL_GL1_REQ_READ_64B = 0x00000021,
17960TCP_PERF_SEL_GL1_REQ_WRITE = 0x00000022,
17961TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 0x00000023,
17962TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 0x00000024,
17963TCP_PERF_SEL_GL1_READ_LATENCY = 0x00000025,
17964TCP_PERF_SEL_GL1_WRITE_LATENCY = 0x00000026,
17965TCP_PERF_SEL_TCP_LATENCY = 0x00000027,
17966TCP_PERF_SEL_TCP_TA_REQ_STALL = 0x00000028,
17967TCP_PERF_SEL_TA_TCP_REQ_STARVE = 0x00000029,
17968TCP_PERF_SEL_DATA_FIFO_STALL = 0x0000002a,
17969TCP_PERF_SEL_LOD_STALL = 0x0000002b,
17970TCP_PERF_SEL_POWER_STALL = 0x0000002c,
17971TCP_PERF_SEL_ALLOC_STALL = 0x0000002d,
17972TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0x0000002e,
17973TCP_PERF_SEL_READ_TAGCONFLICT_STALL = 0x0000002f,
17974TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL = 0x00000030,
17975TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL = 0x00000031,
17976TCP_PERF_SEL_LFIFO_STALL = 0x00000032,
17977TCP_PERF_SEL_MEM_REQ_FIFO_STALL = 0x00000033,
17978TCP_PERF_SEL_GL1_TCP_BACK_PRESSURE = 0x00000034,
17979TCP_PERF_SEL_GL1_TCP_RDRET_STALL = 0x00000035,
17980TCP_PERF_SEL_GL1_GRANT_READ_STALL = 0x00000036,
17981TCP_PERF_SEL_GL1_PENDING_STALL = 0x00000037,
17982TCP_PERF_SEL_OFIFO_INCOMPLETE_STALL = 0x00000038,
17983TCP_PERF_SEL_OFIFO_AGE_ORDER_STALL = 0x00000039,
17984TCP_PERF_SEL_TD_DATA_CYCLE_STALL = 0x0000003a,
17985TCP_PERF_SEL_COMP_TEX_LOAD_STALL = 0x0000003b,
17986TCP_PERF_SEL_READ_DATACONFLICT_STALL = 0x0000003c,
17987TCP_PERF_SEL_WRITE_DATACONFLICT_STALL = 0x0000003d,
17988TCP_PERF_SEL_TD_TCP_STALL = 0x0000003e,
17989} TCP_PERFCOUNT_SELECT;
17990
17991/*
17992 * TCP_WATCH_MODES enum
17993 */
17994
17995typedef enum TCP_WATCH_MODES {
17996TCP_WATCH_MODE_READ = 0x00000000,
17997TCP_WATCH_MODE_NONREAD = 0x00000001,
17998TCP_WATCH_MODE_ATOMIC = 0x00000002,
17999TCP_WATCH_MODE_ALL = 0x00000003,
18000} TCP_WATCH_MODES;
18001
18002/*******************************************************
18003 * TD Enums
18004 *******************************************************/
18005
18006/*
18007 * TD_PERFCOUNT_SEL enum
18008 */
18009
18010typedef enum TD_PERFCOUNT_SEL {
18011TD_PERF_SEL_none = 0x00000000,
18012TD_PERF_SEL_td_busy = 0x00000001,
18013TD_PERF_SEL_input_busy = 0x00000002,
18014TD_PERF_SEL_sampler_lerp_busy = 0x00000003,
18015TD_PERF_SEL_sampler_out_busy = 0x00000004,
18016TD_PERF_SEL_nofilter_busy = 0x00000005,
18017TD_PERF_SEL_ray_tracing_bvh4_busy = 0x00000006,
18018TD_PERF_SEL_sampler_core_sclk_en = 0x00000007,
18019TD_PERF_SEL_sampler_preformatter_sclk_en = 0x00000008,
18020TD_PERF_SEL_sampler_bilerp_sclk_en = 0x00000009,
18021TD_PERF_SEL_sampler_bypass_sclk_en = 0x0000000a,
18022TD_PERF_SEL_sampler_minmax_sclk_en = 0x0000000b,
18023TD_PERF_SEL_sampler_accum_sclk_en = 0x0000000c,
18024TD_PERF_SEL_sampler_format_flt_sclk_en = 0x0000000d,
18025TD_PERF_SEL_sampler_format_fxdpt_sclk_en = 0x0000000e,
18026TD_PERF_SEL_sampler_out_sclk_en = 0x0000000f,
18027TD_PERF_SEL_nofilter_sclk_en = 0x00000010,
18028TD_PERF_SEL_nofilter_d32_sclk_en = 0x00000011,
18029TD_PERF_SEL_nofilter_d16_sclk_en = 0x00000012,
18030TD_PERF_SEL_ray_tracing_bvh4_sclk_en = 0x00000016,
18031TD_PERF_SEL_ray_tracing_bvh4_ip_sclk_en = 0x00000017,
18032TD_PERF_SEL_ray_tracing_bvh4_box_sclk_en = 0x00000018,
18033TD_PERF_SEL_ray_tracing_bvh4_tri_sclk_en = 0x00000019,
18034TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 0x0000001a,
18035TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 0x0000001b,
18036TD_PERF_SEL_all_pipes_sclk_on_at_same_time = 0x0000001c,
18037TD_PERF_SEL_sampler_and_nofilter_sclk_on_bvh4_sclk_off = 0x0000001d,
18038TD_PERF_SEL_sampler_and_bvh4_sclk_on_nofilter_sclk_off = 0x0000001e,
18039TD_PERF_SEL_nofilter_and_bvh4_sclk_on_sampler_sclk_off = 0x0000001f,
18040TD_PERF_SEL_core_state_ram_max_cnt = 0x00000020,
18041TD_PERF_SEL_core_state_rams_read = 0x00000021,
18042TD_PERF_SEL_weight_data_rams_read = 0x00000022,
18043TD_PERF_SEL_reference_data_rams_read = 0x00000023,
18044TD_PERF_SEL_tc_td_ram_fifo_full = 0x00000024,
18045TD_PERF_SEL_tc_td_ram_fifo_max_cnt = 0x00000025,
18046TD_PERF_SEL_tc_td_data_fifo_full = 0x00000026,
18047TD_PERF_SEL_input_state_fifo_full = 0x00000027,
18048TD_PERF_SEL_ta_data_stall = 0x00000028,
18049TD_PERF_SEL_tc_data_stall = 0x00000029,
18050TD_PERF_SEL_tc_ram_stall = 0x0000002a,
18051TD_PERF_SEL_lds_stall = 0x0000002b,
18052TD_PERF_SEL_sampler_pkr_full = 0x0000002c,
18053TD_PERF_SEL_sampler_pkr_full_due_to_arb = 0x0000002d,
18054TD_PERF_SEL_nofilter_pkr_full = 0x0000002e,
18055TD_PERF_SEL_nofilter_pkr_full_due_to_arb = 0x0000002f,
18056TD_PERF_SEL_ray_tracing_bvh4_pkr_full = 0x00000030,
18057TD_PERF_SEL_ray_tracing_bvh4_pkr_full_due_to_arb = 0x00000031,
18058TD_PERF_SEL_gather4_instr = 0x00000032,
18059TD_PERF_SEL_gather4h_instr = 0x00000033,
18060TD_PERF_SEL_sample_instr = 0x00000036,
18061TD_PERF_SEL_sample_c_instr = 0x00000037,
18062TD_PERF_SEL_load_instr = 0x00000038,
18063TD_PERF_SEL_ldfptr_instr = 0x00000039,
18064TD_PERF_SEL_write_ack_instr = 0x0000003a,
18065TD_PERF_SEL_d16_en_instr = 0x0000003b,
18066TD_PERF_SEL_bypassLerp_instr = 0x0000003c,
18067TD_PERF_SEL_min_max_filter_instr = 0x0000003d,
18068TD_PERF_SEL_one_comp_return_instr = 0x0000003e,
18069TD_PERF_SEL_two_comp_return_instr = 0x0000003f,
18070TD_PERF_SEL_three_comp_return_instr = 0x00000040,
18071TD_PERF_SEL_four_comp_return_instr = 0x00000041,
18072TD_PERF_SEL_user_defined_border = 0x00000042,
18073TD_PERF_SEL_white_border = 0x00000043,
18074TD_PERF_SEL_opaque_black_border = 0x00000044,
18075TD_PERF_SEL_lod_warn_from_ta = 0x00000045,
18076TD_PERF_SEL_instruction_dest_is_lds = 0x00000046,
18077TD_PERF_SEL_td_cycling_of_nofilter_instr_2cycles = 0x00000047,
18078TD_PERF_SEL_td_cycling_of_nofilter_instr_4cycles = 0x00000048,
18079TD_PERF_SEL_tc_cycling_of_nofilter_instr_2cycles = 0x00000049,
18080TD_PERF_SEL_tc_cycling_of_nofilter_instr_4cycles = 0x0000004a,
18081TD_PERF_SEL_out_of_order_instr = 0x0000004b,
18082TD_PERF_SEL_total_num_instr = 0x0000004c,
18083TD_PERF_SEL_total_num_instr_with_perf_wdw = 0x0000004d,
18084TD_PERF_SEL_total_num_sampler_instr = 0x0000004e,
18085TD_PERF_SEL_total_num_sampler_instr_with_perf_wdw = 0x0000004f,
18086TD_PERF_SEL_total_num_nofilter_instr = 0x00000050,
18087TD_PERF_SEL_total_num_nofilter_instr_with_perf_wdw = 0x00000051,
18088TD_PERF_SEL_total_num_ray_tracing_bvh4_instr = 0x00000052,
18089TD_PERF_SEL_total_num_ray_tracing_bvh4_instr_with_perf_wdw = 0x00000053,
18090TD_PERF_SEL_mixmode_instr = 0x00000054,
18091TD_PERF_SEL_mixmode_resource = 0x00000055,
18092TD_PERF_SEL_status_packet = 0x00000056,
18093TD_PERF_SEL_address_cmd_poison = 0x00000057,
18094TD_PERF_SEL_data_poison = 0x00000058,
18095TD_PERF_SEL_done_scoreboard_max_stored_cnt = 0x00000059,
18096TD_PERF_SEL_done_scoreboard_max_waiting_cnt = 0x0000005a,
18097TD_PERF_SEL_done_scoreboard_not_empty = 0x0000005b,
18098TD_PERF_SEL_done_scoreboard_is_full = 0x0000005c,
18099TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 0x0000005d,
18100TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 0x0000005e,
18101TD_PERF_SEL_nofilter_formatters_turned_on = 0x0000005f,
18102TD_PERF_SEL_nofilter_insert_extra_comps = 0x00000060,
18103TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 0x00000061,
18104TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 0x00000062,
18105TD_PERF_SEL_msaa_load_instr = 0x00000063,
18106TD_PERF_SEL_blend_prt_with_prt_default_0 = 0x00000064,
18107TD_PERF_SEL_blend_prt_with_prt_default_1 = 0x00000065,
18108TD_PERF_SEL_resmap_instr = 0x00000066,
18109TD_PERF_SEL_prt_ack_instr = 0x00000067,
18110TD_PERF_SEL_resmap_with_volume_filtering = 0x00000068,
18111TD_PERF_SEL_resmap_with_aniso_filtering = 0x00000069,
18112TD_PERF_SEL_resmap_with_no_more_filtering = 0x0000006a,
18113TD_PERF_SEL_resmap_with_cubemap_corner = 0x0000006b,
18114TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_0 = 0x0000006c,
18115TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_1 = 0x0000006d,
18116TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_2 = 0x0000006e,
18117TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_3to4 = 0x0000006f,
18118TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_5to8 = 0x00000070,
18119TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_9to16 = 0x00000071,
18120TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_17to31 = 0x00000072,
18121TD_PERF_SEL_ray_tracing_bvh4_threads_per_instruction_is_32 = 0x00000073,
18122TD_PERF_SEL_ray_tracing_bvh4_fp16_box_node = 0x00000074,
18123TD_PERF_SEL_ray_tracing_bvh4_fp32_box_node = 0x00000075,
18124TD_PERF_SEL_ray_tracing_bvh4_tri_node = 0x00000076,
18125TD_PERF_SEL_ray_tracing_bvh4_dropped_box_node = 0x00000077,
18126TD_PERF_SEL_ray_tracing_bvh4_dropped_tri_node = 0x00000078,
18127TD_PERF_SEL_ray_tracing_bvh4_invalid_box_node = 0x00000079,
18128TD_PERF_SEL_ray_tracing_bvh4_invalid_tri_node = 0x0000007a,
18129TD_PERF_SEL_ray_tracing_bvh4_box_sort_en = 0x0000007b,
18130TD_PERF_SEL_ray_tracing_bvh4_box_grow_val_nonzero = 0x0000007c,
18131TD_PERF_SEL_ray_tracing_bvh4_num_box_with_inf_or_nan_vtx = 0x0000007d,
18132TD_PERF_SEL_ray_tracing_bvh4_num_tri_with_inf_or_nan_vtx = 0x0000007e,
18133TD_PERF_SEL_ray_tracing_bvh4_num_box_that_squashed_a_nan = 0x0000007f,
18134TD_PERF_SEL_ray_tracing_bvh4_num_box_misses = 0x00000080,
18135TD_PERF_SEL_ray_tracing_bvh4_num_tri_misses = 0x00000081,
18136TD_PERF_SEL_ray_tracing_bvh4_num_tri_tie_breakers = 0x00000082,
18137TD_PERF_SEL_burst_bin_preempting_nofilter_1 = 0x00000083,
18138TD_PERF_SEL_burst_bin_preempting_nofilter_2to4 = 0x00000084,
18139TD_PERF_SEL_burst_bin_preempting_nofilter_5to7 = 0x00000085,
18140TD_PERF_SEL_burst_bin_preempting_nofilter_8to16 = 0x00000086,
18141TD_PERF_SEL_burst_bin_preempting_nofilter_gt16 = 0x00000087,
18142TD_PERF_SEL_burst_bin_sampler_1 = 0x00000088,
18143TD_PERF_SEL_burst_bin_sampler_2to8 = 0x00000089,
18144TD_PERF_SEL_burst_bin_sampler_9to16 = 0x0000008a,
18145TD_PERF_SEL_burst_bin_sampler_gt16 = 0x0000008b,
18146TD_PERF_SEL_burst_bin_gather_1 = 0x0000008c,
18147TD_PERF_SEL_burst_bin_gather_2to8 = 0x0000008d,
18148TD_PERF_SEL_burst_bin_gather_9to16 = 0x0000008e,
18149TD_PERF_SEL_burst_bin_gather_gt16 = 0x0000008f,
18150TD_PERF_SEL_burst_bin_nofilter_1 = 0x00000090,
18151TD_PERF_SEL_burst_bin_nofilter_2to4 = 0x00000091,
18152TD_PERF_SEL_burst_bin_nofilter_5to7 = 0x00000092,
18153TD_PERF_SEL_burst_bin_nofilter_8to16 = 0x00000093,
18154TD_PERF_SEL_burst_bin_nofilter_gt16 = 0x00000094,
18155TD_PERF_SEL_burst_bin_bvh4_1 = 0x00000095,
18156TD_PERF_SEL_burst_bin_bvh4_2to8 = 0x00000096,
18157TD_PERF_SEL_burst_bin_bvh4_9to16 = 0x00000097,
18158TD_PERF_SEL_burst_bin_bvh4_gt16 = 0x00000098,
18159TD_PERF_SEL_burst_bin_bvh4_box_nodes_1 = 0x00000099,
18160TD_PERF_SEL_burst_bin_bvh4_box_nodes_2to4 = 0x0000009a,
18161TD_PERF_SEL_burst_bin_bvh4_box_nodes_5to7 = 0x0000009b,
18162TD_PERF_SEL_burst_bin_bvh4_box_nodes_8to16 = 0x0000009c,
18163TD_PERF_SEL_burst_bin_bvh4_box_nodes_gt16 = 0x0000009d,
18164TD_PERF_SEL_burst_bin_bvh4_tri_nodes_1 = 0x0000009e,
18165TD_PERF_SEL_burst_bin_bvh4_tri_nodes_2to8 = 0x0000009f,
18166TD_PERF_SEL_burst_bin_bvh4_tri_nodes_9to16 = 0x000000a0,
18167TD_PERF_SEL_burst_bin_bvh4_tri_nodes_gt16 = 0x000000a1,
18168TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_1 = 0x000000a2,
18169TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_2to8 = 0x000000a3,
18170TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_9to16 = 0x000000a4,
18171TD_PERF_SEL_burst_bin_bvh4_dropped_nodes_gt16 = 0x000000a5,
18172TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_1 = 0x000000a6,
18173TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_2to8 = 0x000000a7,
18174TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_9to16 = 0x000000a8,
18175TD_PERF_SEL_burst_bin_bvh4_invalid_nodes_gt16 = 0x000000a9,
18176TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_0 = 0x000000aa,
18177TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_1 = 0x000000ab,
18178TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_2to31 = 0x000000ac,
18179TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_32to127 = 0x000000ad,
18180TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_128to511 = 0x000000ae,
18181TD_PERF_SEL_bubble_bin_ta_waiting_for_tc_data_gt511 = 0x000000af,
18182TD_PERF_SEL_bubble_bin_lds_stall_1to3 = 0x000000b0,
18183TD_PERF_SEL_bubble_bin_lds_stall_4to7 = 0x000000b1,
18184TD_PERF_SEL_bubble_bin_lds_stall_8to15 = 0x000000b2,
18185TD_PERF_SEL_bubble_bin_lds_stall_gt15 = 0x000000b3,
18186TD_PERF_SEL_preempting_nofilter_max_cnt = 0x000000b4,
18187TD_PERF_SEL_sampler_lerp0_active = 0x000000b5,
18188TD_PERF_SEL_sampler_lerp1_active = 0x000000b6,
18189TD_PERF_SEL_sampler_lerp2_active = 0x000000b7,
18190TD_PERF_SEL_sampler_lerp3_active = 0x000000b8,
18191TD_PERF_SEL_nofilter_total_num_comps_to_lds = 0x000000b9,
18192TD_PERF_SEL_nofilter_byte_cycling_4cycles = 0x000000ba,
18193TD_PERF_SEL_nofilter_byte_cycling_8cycles = 0x000000bb,
18194TD_PERF_SEL_nofilter_byte_cycling_16cycles = 0x000000bc,
18195TD_PERF_SEL_nofilter_dword_cycling_2cycles = 0x000000bd,
18196TD_PERF_SEL_nofilter_dword_cycling_4cycles = 0x000000be,
18197TD_PERF_SEL_input_bp_due_to_done_scoreboard_full = 0x000000bf,
18198TD_PERF_SEL_ray_tracing_bvh4_instr_invld_thread_cnt = 0x000000c0,
18199} TD_PERFCOUNT_SEL;
18200
18201/*******************************************************
18202 * GL2C Enums
18203 *******************************************************/
18204
18205/*
18206 * GL2A_PERF_SEL enum
18207 */
18208
18209typedef enum GL2A_PERF_SEL {
18210GL2A_PERF_SEL_NONE = 0x00000000,
18211GL2A_PERF_SEL_CYCLE = 0x00000001,
18212GL2A_PERF_SEL_BUSY = 0x00000002,
18213GL2A_PERF_SEL_REQ_GL2C0 = 0x00000003,
18214GL2A_PERF_SEL_REQ_GL2C1 = 0x00000004,
18215GL2A_PERF_SEL_REQ_GL2C2 = 0x00000005,
18216GL2A_PERF_SEL_REQ_GL2C3 = 0x00000006,
18217GL2A_PERF_SEL_REQ_GL2C4 = 0x00000007,
18218GL2A_PERF_SEL_REQ_GL2C5 = 0x00000008,
18219GL2A_PERF_SEL_REQ_GL2C6 = 0x00000009,
18220GL2A_PERF_SEL_REQ_GL2C7 = 0x0000000a,
18221GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 0x0000000b,
18222GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 0x0000000c,
18223GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 0x0000000d,
18224GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 0x0000000e,
18225GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 0x0000000f,
18226GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 0x00000010,
18227GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 0x00000011,
18228GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 0x00000012,
18229GL2A_PERF_SEL_REQ_BURST_GL2C0 = 0x00000013,
18230GL2A_PERF_SEL_REQ_BURST_GL2C1 = 0x00000014,
18231GL2A_PERF_SEL_REQ_BURST_GL2C2 = 0x00000015,
18232GL2A_PERF_SEL_REQ_BURST_GL2C3 = 0x00000016,
18233GL2A_PERF_SEL_REQ_BURST_GL2C4 = 0x00000017,
18234GL2A_PERF_SEL_REQ_BURST_GL2C5 = 0x00000018,
18235GL2A_PERF_SEL_REQ_BURST_GL2C6 = 0x00000019,
18236GL2A_PERF_SEL_REQ_BURST_GL2C7 = 0x0000001a,
18237GL2A_PERF_SEL_REQ_STALL_GL2C0 = 0x0000001b,
18238GL2A_PERF_SEL_REQ_STALL_GL2C1 = 0x0000001c,
18239GL2A_PERF_SEL_REQ_STALL_GL2C2 = 0x0000001d,
18240GL2A_PERF_SEL_REQ_STALL_GL2C3 = 0x0000001e,
18241GL2A_PERF_SEL_REQ_STALL_GL2C4 = 0x0000001f,
18242GL2A_PERF_SEL_REQ_STALL_GL2C5 = 0x00000020,
18243GL2A_PERF_SEL_REQ_STALL_GL2C6 = 0x00000021,
18244GL2A_PERF_SEL_REQ_STALL_GL2C7 = 0x00000022,
18245GL2A_PERF_SEL_RTN_STALL_GL2C0 = 0x00000023,
18246GL2A_PERF_SEL_RTN_STALL_GL2C1 = 0x00000024,
18247GL2A_PERF_SEL_RTN_STALL_GL2C2 = 0x00000025,
18248GL2A_PERF_SEL_RTN_STALL_GL2C3 = 0x00000026,
18249GL2A_PERF_SEL_RTN_STALL_GL2C4 = 0x00000027,
18250GL2A_PERF_SEL_RTN_STALL_GL2C5 = 0x00000028,
18251GL2A_PERF_SEL_RTN_STALL_GL2C6 = 0x00000029,
18252GL2A_PERF_SEL_RTN_STALL_GL2C7 = 0x0000002a,
18253GL2A_PERF_SEL_RTN_CLIENT0 = 0x0000002b,
18254GL2A_PERF_SEL_RTN_CLIENT1 = 0x0000002c,
18255GL2A_PERF_SEL_RTN_CLIENT2 = 0x0000002d,
18256GL2A_PERF_SEL_RTN_CLIENT3 = 0x0000002e,
18257GL2A_PERF_SEL_RTN_CLIENT4 = 0x0000002f,
18258GL2A_PERF_SEL_RTN_CLIENT5 = 0x00000030,
18259GL2A_PERF_SEL_RTN_CLIENT6 = 0x00000031,
18260GL2A_PERF_SEL_RTN_CLIENT7 = 0x00000032,
18261GL2A_PERF_SEL_RTN_CLIENT8 = 0x00000033,
18262GL2A_PERF_SEL_RTN_CLIENT9 = 0x00000034,
18263GL2A_PERF_SEL_RTN_CLIENT10 = 0x00000035,
18264GL2A_PERF_SEL_RTN_CLIENT11 = 0x00000036,
18265GL2A_PERF_SEL_RTN_CLIENT12 = 0x00000037,
18266GL2A_PERF_SEL_RTN_CLIENT13 = 0x00000038,
18267GL2A_PERF_SEL_RTN_CLIENT14 = 0x00000039,
18268GL2A_PERF_SEL_RTN_CLIENT15 = 0x0000003a,
18269GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 0x0000003b,
18270GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 0x0000003c,
18271GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 0x0000003d,
18272GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 0x0000003e,
18273GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 0x0000003f,
18274GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 0x00000040,
18275GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 0x00000041,
18276GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 0x00000042,
18277GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT8 = 0x00000043,
18278GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT9 = 0x00000044,
18279GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT10 = 0x00000045,
18280GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT11 = 0x00000046,
18281GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT12 = 0x00000047,
18282GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT13 = 0x00000048,
18283GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT14 = 0x00000049,
18284GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT15 = 0x0000004a,
18285GL2A_PERF_SEL_REQ_BURST_CLIENT0 = 0x0000004b,
18286GL2A_PERF_SEL_REQ_BURST_CLIENT1 = 0x0000004c,
18287GL2A_PERF_SEL_REQ_BURST_CLIENT2 = 0x0000004d,
18288GL2A_PERF_SEL_REQ_BURST_CLIENT3 = 0x0000004e,
18289GL2A_PERF_SEL_REQ_BURST_CLIENT4 = 0x0000004f,
18290GL2A_PERF_SEL_REQ_BURST_CLIENT5 = 0x00000050,
18291GL2A_PERF_SEL_REQ_BURST_CLIENT6 = 0x00000051,
18292GL2A_PERF_SEL_REQ_BURST_CLIENT7 = 0x00000052,
18293GL2A_PERF_SEL_REQ_BURST_CLIENT8 = 0x00000053,
18294GL2A_PERF_SEL_REQ_BURST_CLIENT9 = 0x00000054,
18295GL2A_PERF_SEL_REQ_BURST_CLIENT10 = 0x00000055,
18296GL2A_PERF_SEL_REQ_BURST_CLIENT11 = 0x00000056,
18297GL2A_PERF_SEL_REQ_BURST_CLIENT12 = 0x00000057,
18298GL2A_PERF_SEL_REQ_BURST_CLIENT13 = 0x00000058,
18299GL2A_PERF_SEL_REQ_BURST_CLIENT14 = 0x00000059,
18300GL2A_PERF_SEL_REQ_BURST_CLIENT15 = 0x0000005a,
18301GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT0 = 0x0000005b,
18302GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT1 = 0x0000005c,
18303GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT2 = 0x0000005d,
18304GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT3 = 0x0000005e,
18305GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT4 = 0x0000005f,
18306GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT5 = 0x00000060,
18307GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT6 = 0x00000061,
18308GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT7 = 0x00000062,
18309GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT8 = 0x00000063,
18310GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT9 = 0x00000064,
18311GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT10 = 0x00000065,
18312GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT11 = 0x00000067,
18313GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT12 = 0x00000068,
18314GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT13 = 0x00000069,
18315GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT14 = 0x0000006a,
18316GL2A_PERF_SEL_RTN_CREDIT_STALL_CLIENT15 = 0x0000006b,
18317} GL2A_PERF_SEL;
18318
18319/*
18320 * GL2C_PERF_SEL enum
18321 */
18322
18323typedef enum GL2C_PERF_SEL {
18324GL2C_PERF_SEL_NONE = 0x00000000,
18325GL2C_PERF_SEL_CYCLE = 0x00000001,
18326GL2C_PERF_SEL_BUSY = 0x00000002,
18327GL2C_PERF_SEL_REQ = 0x00000003,
18328GL2C_PERF_SEL_VOL_REQ = 0x00000004,
18329GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 0x00000005,
18330GL2C_PERF_SEL_READ = 0x00000006,
18331GL2C_PERF_SEL_WRITE = 0x00000007,
18332GL2C_PERF_SEL_ATOMIC = 0x00000008,
18333GL2C_PERF_SEL_NOP_ACK = 0x00000009,
18334GL2C_PERF_SEL_NOP_RTN0 = 0x0000000a,
18335GL2C_PERF_SEL_PROBE = 0x0000000b,
18336GL2C_PERF_SEL_PROBE_ALL = 0x0000000c,
18337GL2C_PERF_SEL_INTERNAL_PROBE = 0x0000000d,
18338GL2C_PERF_SEL_COMPRESSED_READ_REQ = 0x0000000e,
18339GL2C_PERF_SEL_METADATA_READ_REQ = 0x0000000f,
18340GL2C_PERF_SEL_CLIENT0_REQ = 0x00000010,
18341GL2C_PERF_SEL_CLIENT1_REQ = 0x00000011,
18342GL2C_PERF_SEL_CLIENT2_REQ = 0x00000012,
18343GL2C_PERF_SEL_CLIENT3_REQ = 0x00000013,
18344GL2C_PERF_SEL_CLIENT4_REQ = 0x00000014,
18345GL2C_PERF_SEL_CLIENT5_REQ = 0x00000015,
18346GL2C_PERF_SEL_CLIENT6_REQ = 0x00000016,
18347GL2C_PERF_SEL_CLIENT7_REQ = 0x00000017,
18348GL2C_PERF_SEL_CLIENT8_REQ = 0x00000018,
18349GL2C_PERF_SEL_CLIENT9_REQ = 0x00000019,
18350GL2C_PERF_SEL_CLIENT10_REQ = 0x0000001a,
18351GL2C_PERF_SEL_CLIENT11_REQ = 0x0000001b,
18352GL2C_PERF_SEL_CLIENT12_REQ = 0x0000001c,
18353GL2C_PERF_SEL_CLIENT13_REQ = 0x0000001d,
18354GL2C_PERF_SEL_CLIENT14_REQ = 0x0000001e,
18355GL2C_PERF_SEL_CLIENT15_REQ = 0x0000001f,
18356GL2C_PERF_SEL_C_RW_S_REQ = 0x00000020,
18357GL2C_PERF_SEL_C_RW_US_REQ = 0x00000021,
18358GL2C_PERF_SEL_C_RO_S_REQ = 0x00000022,
18359GL2C_PERF_SEL_C_RO_US_REQ = 0x00000023,
18360GL2C_PERF_SEL_UC_REQ = 0x00000024,
18361GL2C_PERF_SEL_LRU_REQ = 0x00000025,
18362GL2C_PERF_SEL_STREAM_REQ = 0x00000026,
18363GL2C_PERF_SEL_BYPASS_REQ = 0x00000027,
18364GL2C_PERF_SEL_NOA_REQ = 0x00000028,
18365GL2C_PERF_SEL_SHARED_REQ = 0x00000029,
18366GL2C_PERF_SEL_HIT = 0x0000002a,
18367GL2C_PERF_SEL_MISS = 0x0000002b,
18368GL2C_PERF_SEL_FULL_HIT = 0x0000002c,
18369GL2C_PERF_SEL_PARTIAL_32B_HIT = 0x0000002d,
18370GL2C_PERF_SEL_PARTIAL_64B_HIT = 0x0000002e,
18371GL2C_PERF_SEL_PARTIAL_96B_HIT = 0x0000002f,
18372GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x00000030,
18373GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 0x00000031,
18374GL2C_PERF_SEL_UNCACHED_WRITE = 0x00000032,
18375GL2C_PERF_SEL_WRITEBACK = 0x00000033,
18376GL2C_PERF_SEL_NORMAL_WRITEBACK = 0x00000034,
18377GL2C_PERF_SEL_EVICT = 0x00000035,
18378GL2C_PERF_SEL_NORMAL_EVICT = 0x00000036,
18379GL2C_PERF_SEL_PROBE_EVICT = 0x00000037,
18380GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 0x00000038,
18381GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 0x00000039,
18382GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 0x0000003a,
18383GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 0x0000003b,
18384GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 0x0000003c,
18385GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 0x0000003d,
18386GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 0x0000003e,
18387GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 0x0000003f,
18388GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 0x00000040,
18389GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT8 = 0x00000041,
18390GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT9 = 0x00000042,
18391GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT10 = 0x00000043,
18392GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT11 = 0x00000044,
18393GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT12 = 0x00000045,
18394GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT13 = 0x00000046,
18395GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT14 = 0x00000047,
18396GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT15 = 0x00000048,
18397GL2C_PERF_SEL_READ_32_REQ = 0x00000049,
18398GL2C_PERF_SEL_READ_64_REQ = 0x0000004a,
18399GL2C_PERF_SEL_READ_128_REQ = 0x0000004b,
18400GL2C_PERF_SEL_WRITE_32_REQ = 0x0000004c,
18401GL2C_PERF_SEL_WRITE_64_REQ = 0x0000004d,
18402GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 0x0000004e,
18403GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 0x0000004f,
18404GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 0x00000050,
18405GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 0x00000051,
18406GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 0x00000052,
18407GL2C_PERF_SEL_MC_WRREQ = 0x00000053,
18408GL2C_PERF_SEL_EA_WRREQ_SNOOP = 0x00000054,
18409GL2C_PERF_SEL_EA_WRREQ_64B = 0x00000055,
18410GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 0x00000056,
18411GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 0x00000057,
18412GL2C_PERF_SEL_MC_WRREQ_STALL = 0x00000058,
18413GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 0x00000059,
18414GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 0x0000005a,
18415GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 0x0000005b,
18416GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 0x0000005c,
18417GL2C_PERF_SEL_MC_WRREQ_LEVEL = 0x0000005d,
18418GL2C_PERF_SEL_EA_ATOMIC = 0x0000005e,
18419GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 0x0000005f,
18420GL2C_PERF_SEL_MC_RDREQ = 0x00000060,
18421GL2C_PERF_SEL_EA_RDREQ_SNOOP = 0x00000061,
18422GL2C_PERF_SEL_EA_RDREQ_SPLIT = 0x00000062,
18423GL2C_PERF_SEL_EA_RDREQ_32B = 0x00000063,
18424GL2C_PERF_SEL_EA_RDREQ_64B = 0x00000064,
18425GL2C_PERF_SEL_EA_RDREQ_96B = 0x00000065,
18426GL2C_PERF_SEL_EA_RDREQ_128B = 0x00000066,
18427GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 0x00000067,
18428GL2C_PERF_SEL_EA_RD_MDC_32B = 0x00000068,
18429GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 0x00000069,
18430GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 0x0000006a,
18431GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 0x0000006b,
18432GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 0x0000006c,
18433GL2C_PERF_SEL_MC_RDREQ_LEVEL = 0x0000006d,
18434GL2C_PERF_SEL_EA_RDREQ_DRAM = 0x0000006e,
18435GL2C_PERF_SEL_EA_WRREQ_DRAM = 0x0000006f,
18436GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 0x00000070,
18437GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 0x00000071,
18438GL2C_PERF_SEL_ONION_READ = 0x00000072,
18439GL2C_PERF_SEL_ONION_WRITE = 0x00000073,
18440GL2C_PERF_SEL_IO_READ = 0x00000074,
18441GL2C_PERF_SEL_IO_WRITE = 0x00000075,
18442GL2C_PERF_SEL_GARLIC_READ = 0x00000076,
18443GL2C_PERF_SEL_GARLIC_WRITE = 0x00000077,
18444GL2C_PERF_SEL_EA_OUTSTANDING = 0x00000078,
18445GL2C_PERF_SEL_LATENCY_FIFO_FULL = 0x00000079,
18446GL2C_PERF_SEL_SRC_FIFO_FULL = 0x0000007a,
18447GL2C_PERF_SEL_TAG_STALL = 0x0000007b,
18448GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x0000007c,
18449GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x0000007d,
18450GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x0000007e,
18451GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x0000007f,
18452GL2C_PERF_SEL_TAG_PROBE_STALL = 0x00000080,
18453GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x00000081,
18454GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 0x00000082,
18455GL2C_PERF_SEL_TAG_READ_DST_STALL = 0x00000083,
18456GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 0x00000084,
18457GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x00000085,
18458GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x00000086,
18459GL2C_PERF_SEL_BUBBLE = 0x00000087,
18460GL2C_PERF_SEL_IB_REQ = 0x00000088,
18461GL2C_PERF_SEL_IB_STALL = 0x00000089,
18462GL2C_PERF_SEL_IB_TAG_STALL = 0x0000008a,
18463GL2C_PERF_SEL_IB_CM_STALL = 0x0000008b,
18464GL2C_PERF_SEL_RETURN_ACK = 0x0000008c,
18465GL2C_PERF_SEL_RETURN_DATA = 0x0000008d,
18466GL2C_PERF_SEL_EA_RDRET_NACK = 0x0000008e,
18467GL2C_PERF_SEL_EA_WRRET_NACK = 0x0000008f,
18468GL2C_PERF_SEL_GL2A_LEVEL = 0x00000090,
18469GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x00000091,
18470GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 0x00000092,
18471GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x00000093,
18472GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 0x00000094,
18473GL2C_PERF_SEL_GCR_INV = 0x00000095,
18474GL2C_PERF_SEL_GCR_WB = 0x00000096,
18475GL2C_PERF_SEL_GCR_DISCARD = 0x00000097,
18476GL2C_PERF_SEL_GCR_RANGE = 0x00000098,
18477GL2C_PERF_SEL_GCR_ALL = 0x00000099,
18478GL2C_PERF_SEL_GCR_VOL = 0x0000009a,
18479GL2C_PERF_SEL_GCR_UNSHARED = 0x0000009b,
18480GL2C_PERF_SEL_GCR_MDC_INV = 0x0000009c,
18481GL2C_PERF_SEL_GCR_GL2_INV_ALL = 0x0000009d,
18482GL2C_PERF_SEL_GCR_GL2_WB_ALL = 0x0000009e,
18483GL2C_PERF_SEL_GCR_MDC_INV_ALL = 0x0000009f,
18484GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 0x000000a0,
18485GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 0x000000a1,
18486GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 0x000000a2,
18487GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 0x000000a3,
18488GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 0x000000a4,
18489GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 0x000000a5,
18490GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 0x000000a6,
18491GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 0x000000a7,
18492GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 0x000000a8,
18493GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 0x000000a9,
18494GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 0x000000aa,
18495GL2C_PERF_SEL_GCR_INVL2_VOL_START = 0x000000ab,
18496GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 0x000000ac,
18497GL2C_PERF_SEL_GCR_WBL2_VOL_START = 0x000000ad,
18498GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 0x000000ae,
18499GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 0x000000af,
18500GL2C_PERF_SEL_GCR_WBINVL2_START = 0x000000b0,
18501GL2C_PERF_SEL_MDC_INV_METADATA = 0x000000b1,
18502GL2C_PERF_SEL_MDC_REQ = 0x000000b2,
18503GL2C_PERF_SEL_MDC_LEVEL = 0x000000b3,
18504GL2C_PERF_SEL_MDC_TAG_HIT = 0x000000b4,
18505GL2C_PERF_SEL_MDC_SECTOR_HIT = 0x000000b5,
18506GL2C_PERF_SEL_MDC_SECTOR_MISS = 0x000000b6,
18507GL2C_PERF_SEL_MDC_TAG_STALL = 0x000000b7,
18508GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x000000b8,
18509GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x000000b9,
18510GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x000000ba,
18511GL2C_PERF_SEL_CM_CHANNEL0_REQ = 0x000000bb,
18512GL2C_PERF_SEL_CM_CHANNEL1_REQ = 0x000000bc,
18513GL2C_PERF_SEL_CM_CHANNEL2_REQ = 0x000000bd,
18514GL2C_PERF_SEL_CM_CHANNEL3_REQ = 0x000000be,
18515GL2C_PERF_SEL_CM_CHANNEL4_REQ = 0x000000bf,
18516GL2C_PERF_SEL_CM_CHANNEL5_REQ = 0x000000c0,
18517GL2C_PERF_SEL_CM_CHANNEL6_REQ = 0x000000c1,
18518GL2C_PERF_SEL_CM_CHANNEL7_REQ = 0x000000c2,
18519GL2C_PERF_SEL_CM_CHANNEL8_REQ = 0x000000c3,
18520GL2C_PERF_SEL_CM_CHANNEL9_REQ = 0x000000c4,
18521GL2C_PERF_SEL_CM_CHANNEL10_REQ = 0x000000c5,
18522GL2C_PERF_SEL_CM_CHANNEL11_REQ = 0x000000c6,
18523GL2C_PERF_SEL_CM_CHANNEL12_REQ = 0x000000c7,
18524GL2C_PERF_SEL_CM_CHANNEL13_REQ = 0x000000c8,
18525GL2C_PERF_SEL_CM_CHANNEL14_REQ = 0x000000c9,
18526GL2C_PERF_SEL_CM_CHANNEL15_REQ = 0x000000ca,
18527GL2C_PERF_SEL_CM_CHANNEL16_REQ = 0x000000cb,
18528GL2C_PERF_SEL_CM_CHANNEL17_REQ = 0x000000cc,
18529GL2C_PERF_SEL_CM_CHANNEL18_REQ = 0x000000cd,
18530GL2C_PERF_SEL_CM_CHANNEL19_REQ = 0x000000ce,
18531GL2C_PERF_SEL_CM_CHANNEL20_REQ = 0x000000cf,
18532GL2C_PERF_SEL_CM_CHANNEL21_REQ = 0x000000d0,
18533GL2C_PERF_SEL_CM_CHANNEL22_REQ = 0x000000d1,
18534GL2C_PERF_SEL_CM_CHANNEL23_REQ = 0x000000d2,
18535GL2C_PERF_SEL_CM_CHANNEL24_REQ = 0x000000d3,
18536GL2C_PERF_SEL_CM_CHANNEL25_REQ = 0x000000d4,
18537GL2C_PERF_SEL_CM_CHANNEL26_REQ = 0x000000d5,
18538GL2C_PERF_SEL_CM_CHANNEL27_REQ = 0x000000d6,
18539GL2C_PERF_SEL_CM_CHANNEL28_REQ = 0x000000d7,
18540GL2C_PERF_SEL_CM_CHANNEL29_REQ = 0x000000d8,
18541GL2C_PERF_SEL_CM_CHANNEL30_REQ = 0x000000d9,
18542GL2C_PERF_SEL_CM_CHANNEL31_REQ = 0x000000da,
18543GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 0x000000db,
18544GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 0x000000dc,
18545GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 0x000000dd,
18546GL2C_PERF_SEL_CM_COMP_ATOMIC_STENCIL_REQ = 0x000000de,
18547GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 0x000000df,
18548GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 0x000000e0,
18549GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 0x000000e1,
18550GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 0x000000e2,
18551GL2C_PERF_SEL_CM_COMP_READ_REQ = 0x000000e3,
18552GL2C_PERF_SEL_CM_READ_BACK_REQ = 0x000000e4,
18553GL2C_PERF_SEL_CM_METADATA_WR_REQ = 0x000000e5,
18554GL2C_PERF_SEL_CM_WR_ACK_REQ = 0x000000e6,
18555GL2C_PERF_SEL_CM_NO_ACK_REQ = 0x000000e7,
18556GL2C_PERF_SEL_CM_NOOP_REQ = 0x000000e8,
18557GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 0x000000e9,
18558GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 0x000000ea,
18559GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 0x000000eb,
18560GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 0x000000ec,
18561GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 0x000000ed,
18562GL2C_PERF_SEL_CM_COMP_RB_SKIP_REQ = 0x000000ee,
18563GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 0x000000ef,
18564GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 0x000000f0,
18565GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 0x000000f1,
18566GL2C_PERF_SEL_CM_RVF_FULL = 0x000000f2,
18567GL2C_PERF_SEL_CM_SDR_FULL = 0x000000f3,
18568GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 0x000000f4,
18569GL2C_PERF_SEL_CM_DCC_STALL = 0x000000f5,
18570GL2C_PERF_SEL_CM_DCC_IN_XFC = 0x000000f6,
18571GL2C_PERF_SEL_CM_DCC_OUT_XFC = 0x000000f7,
18572GL2C_PERF_SEL_CM_DCC_OUT_1x1 = 0x000000f8,
18573GL2C_PERF_SEL_CM_DCC_OUT_1x2 = 0x000000f9,
18574GL2C_PERF_SEL_CM_DCC_OUT_2x1 = 0x000000fa,
18575GL2C_PERF_SEL_CM_DCC_OUT_2x2 = 0x000000fb,
18576GL2C_PERF_SEL_CM_DCC_OUT_UNCOMP = 0x000000fc,
18577GL2C_PERF_SEL_CM_DCC_OUT_CONST = 0x000000fd,
18578GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT16 = 0x000000fe,
18579GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT17 = 0x000000ff,
18580GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT18 = 0x00000100,
18581GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT19 = 0x00000101,
18582} GL2C_PERF_SEL;
18583
18584/*******************************************************
18585 * GRBM Enums
18586 *******************************************************/
18587
18588/*
18589 * GRBM_PERF_SEL enum
18590 */
18591
18592typedef enum GRBM_PERF_SEL {
18593GRBM_PERF_SEL_COUNT = 0x00000000,
18594GRBM_PERF_SEL_USER_DEFINED = 0x00000001,
18595GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002,
18596GRBM_PERF_SEL_CP_BUSY = 0x00000003,
18597GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004,
18598GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005,
18599GRBM_PERF_SEL_CB_BUSY = 0x00000006,
18600GRBM_PERF_SEL_DB_BUSY = 0x00000007,
18601GRBM_PERF_SEL_PA_BUSY = 0x00000008,
18602GRBM_PERF_SEL_SC_BUSY = 0x00000009,
18603GRBM_PERF_SEL_SPI_BUSY = 0x0000000b,
18604GRBM_PERF_SEL_SX_BUSY = 0x0000000c,
18605GRBM_PERF_SEL_TA_BUSY = 0x0000000d,
18606GRBM_PERF_SEL_CB_CLEAN = 0x0000000e,
18607GRBM_PERF_SEL_DB_CLEAN = 0x0000000f,
18608GRBM_PERF_SEL_GDS_BUSY = 0x00000019,
18609GRBM_PERF_SEL_BCI_BUSY = 0x0000001a,
18610GRBM_PERF_SEL_RLC_BUSY = 0x0000001b,
18611GRBM_PERF_SEL_TCP_BUSY = 0x0000001c,
18612GRBM_PERF_SEL_CPG_BUSY = 0x0000001d,
18613GRBM_PERF_SEL_CPC_BUSY = 0x0000001e,
18614GRBM_PERF_SEL_CPF_BUSY = 0x0000001f,
18615GRBM_PERF_SEL_GE_BUSY = 0x00000020,
18616GRBM_PERF_SEL_GE_NO_DMA_BUSY = 0x00000021,
18617GRBM_PERF_SEL_UTCL2_BUSY = 0x00000022,
18618GRBM_PERF_SEL_EA_BUSY = 0x00000023,
18619GRBM_PERF_SEL_RMI_BUSY = 0x00000024,
18620GRBM_PERF_SEL_CPAXI_BUSY = 0x00000025,
18621GRBM_PERF_SEL_UTCL1_BUSY = 0x00000027,
18622GRBM_PERF_SEL_GL2CC_BUSY = 0x00000028,
18623GRBM_PERF_SEL_SDMA_BUSY = 0x00000029,
18624GRBM_PERF_SEL_CH_BUSY = 0x0000002a,
18625GRBM_PERF_SEL_PH_BUSY = 0x0000002b,
18626GRBM_PERF_SEL_PMM_BUSY = 0x0000002c,
18627GRBM_PERF_SEL_GUS_BUSY = 0x0000002d,
18628GRBM_PERF_SEL_GL1CC_BUSY = 0x0000002e,
18629GRBM_PERF_SEL_ANY_ACTIVE_F_BUSY = 0x0000002f,
18630GRBM_PERF_SEL_GL1H_BUSY = 0x00000030,
18631GRBM_PERF_SEL_PC_BUSY = 0x00000031,
18632} GRBM_PERF_SEL;
18633
18634/*
18635 * GRBM_SE0_PERF_SEL enum
18636 */
18637
18638typedef enum GRBM_SE0_PERF_SEL {
18639GRBM_SE0_PERF_SEL_COUNT = 0x00000000,
18640GRBM_SE0_PERF_SEL_USER_DEFINED = 0x00000001,
18641GRBM_SE0_PERF_SEL_CB_BUSY = 0x00000002,
18642GRBM_SE0_PERF_SEL_DB_BUSY = 0x00000003,
18643GRBM_SE0_PERF_SEL_SC_BUSY = 0x00000004,
18644GRBM_SE0_PERF_SEL_SPI_BUSY = 0x00000006,
18645GRBM_SE0_PERF_SEL_SX_BUSY = 0x00000007,
18646GRBM_SE0_PERF_SEL_TA_BUSY = 0x00000008,
18647GRBM_SE0_PERF_SEL_CB_CLEAN = 0x00000009,
18648GRBM_SE0_PERF_SEL_DB_CLEAN = 0x0000000a,
18649GRBM_SE0_PERF_SEL_PA_BUSY = 0x0000000c,
18650GRBM_SE0_PERF_SEL_BCI_BUSY = 0x0000000e,
18651GRBM_SE0_PERF_SEL_RMI_BUSY = 0x0000000f,
18652GRBM_SE0_PERF_SEL_UTCL1_BUSY = 0x00000010,
18653GRBM_SE0_PERF_SEL_TCP_BUSY = 0x00000011,
18654GRBM_SE0_PERF_SEL_GL1CC_BUSY = 0x00000012,
18655GRBM_SE0_PERF_SEL_GL1H_BUSY = 0x00000013,
18656GRBM_SE0_PERF_SEL_PC_BUSY = 0x00000014,
18657} GRBM_SE0_PERF_SEL;
18658
18659/*
18660 * GRBM_SE1_PERF_SEL enum
18661 */
18662
18663typedef enum GRBM_SE1_PERF_SEL {
18664GRBM_SE1_PERF_SEL_COUNT = 0x00000000,
18665GRBM_SE1_PERF_SEL_USER_DEFINED = 0x00000001,
18666GRBM_SE1_PERF_SEL_CB_BUSY = 0x00000002,
18667GRBM_SE1_PERF_SEL_DB_BUSY = 0x00000003,
18668GRBM_SE1_PERF_SEL_SC_BUSY = 0x00000004,
18669GRBM_SE1_PERF_SEL_SPI_BUSY = 0x00000006,
18670GRBM_SE1_PERF_SEL_SX_BUSY = 0x00000007,
18671GRBM_SE1_PERF_SEL_TA_BUSY = 0x00000008,
18672GRBM_SE1_PERF_SEL_CB_CLEAN = 0x00000009,
18673GRBM_SE1_PERF_SEL_DB_CLEAN = 0x0000000a,
18674GRBM_SE1_PERF_SEL_PA_BUSY = 0x0000000c,
18675GRBM_SE1_PERF_SEL_BCI_BUSY = 0x0000000e,
18676GRBM_SE1_PERF_SEL_RMI_BUSY = 0x0000000f,
18677GRBM_SE1_PERF_SEL_UTCL1_BUSY = 0x00000010,
18678GRBM_SE1_PERF_SEL_TCP_BUSY = 0x00000011,
18679GRBM_SE1_PERF_SEL_GL1CC_BUSY = 0x00000012,
18680GRBM_SE1_PERF_SEL_GL1H_BUSY = 0x00000013,
18681GRBM_SE1_PERF_SEL_PC_BUSY = 0x00000014,
18682} GRBM_SE1_PERF_SEL;
18683
18684/*
18685 * GRBM_SE2_PERF_SEL enum
18686 */
18687
18688typedef enum GRBM_SE2_PERF_SEL {
18689GRBM_SE2_PERF_SEL_COUNT = 0x00000000,
18690GRBM_SE2_PERF_SEL_USER_DEFINED = 0x00000001,
18691GRBM_SE2_PERF_SEL_CB_BUSY = 0x00000002,
18692GRBM_SE2_PERF_SEL_DB_BUSY = 0x00000003,
18693GRBM_SE2_PERF_SEL_SC_BUSY = 0x00000004,
18694GRBM_SE2_PERF_SEL_SPI_BUSY = 0x00000006,
18695GRBM_SE2_PERF_SEL_SX_BUSY = 0x00000007,
18696GRBM_SE2_PERF_SEL_TA_BUSY = 0x00000008,
18697GRBM_SE2_PERF_SEL_CB_CLEAN = 0x00000009,
18698GRBM_SE2_PERF_SEL_DB_CLEAN = 0x0000000a,
18699GRBM_SE2_PERF_SEL_PA_BUSY = 0x0000000c,
18700GRBM_SE2_PERF_SEL_BCI_BUSY = 0x0000000e,
18701GRBM_SE2_PERF_SEL_RMI_BUSY = 0x0000000f,
18702GRBM_SE2_PERF_SEL_UTCL1_BUSY = 0x00000010,
18703GRBM_SE2_PERF_SEL_TCP_BUSY = 0x00000011,
18704GRBM_SE2_PERF_SEL_GL1CC_BUSY = 0x00000012,
18705GRBM_SE2_PERF_SEL_GL1H_BUSY = 0x00000013,
18706GRBM_SE2_PERF_SEL_PC_BUSY = 0x00000014,
18707} GRBM_SE2_PERF_SEL;
18708
18709/*
18710 * GRBM_SE3_PERF_SEL enum
18711 */
18712
18713typedef enum GRBM_SE3_PERF_SEL {
18714GRBM_SE3_PERF_SEL_COUNT = 0x00000000,
18715GRBM_SE3_PERF_SEL_USER_DEFINED = 0x00000001,
18716GRBM_SE3_PERF_SEL_CB_BUSY = 0x00000002,
18717GRBM_SE3_PERF_SEL_DB_BUSY = 0x00000003,
18718GRBM_SE3_PERF_SEL_SC_BUSY = 0x00000004,
18719GRBM_SE3_PERF_SEL_SPI_BUSY = 0x00000006,
18720GRBM_SE3_PERF_SEL_SX_BUSY = 0x00000007,
18721GRBM_SE3_PERF_SEL_TA_BUSY = 0x00000008,
18722GRBM_SE3_PERF_SEL_CB_CLEAN = 0x00000009,
18723GRBM_SE3_PERF_SEL_DB_CLEAN = 0x0000000a,
18724GRBM_SE3_PERF_SEL_PA_BUSY = 0x0000000c,
18725GRBM_SE3_PERF_SEL_BCI_BUSY = 0x0000000e,
18726GRBM_SE3_PERF_SEL_RMI_BUSY = 0x0000000f,
18727GRBM_SE3_PERF_SEL_UTCL1_BUSY = 0x00000010,
18728GRBM_SE3_PERF_SEL_TCP_BUSY = 0x00000011,
18729GRBM_SE3_PERF_SEL_GL1CC_BUSY = 0x00000012,
18730GRBM_SE3_PERF_SEL_GL1H_BUSY = 0x00000013,
18731GRBM_SE3_PERF_SEL_PC_BUSY = 0x00000014,
18732} GRBM_SE3_PERF_SEL;
18733
18734/*
18735 * GRBM_SE4_PERF_SEL enum
18736 */
18737
18738typedef enum GRBM_SE4_PERF_SEL {
18739GRBM_SE4_PERF_SEL_COUNT = 0x00000000,
18740GRBM_SE4_PERF_SEL_USER_DEFINED = 0x00000001,
18741GRBM_SE4_PERF_SEL_CB_BUSY = 0x00000002,
18742GRBM_SE4_PERF_SEL_DB_BUSY = 0x00000003,
18743GRBM_SE4_PERF_SEL_SC_BUSY = 0x00000004,
18744GRBM_SE4_PERF_SEL_SPI_BUSY = 0x00000006,
18745GRBM_SE4_PERF_SEL_SX_BUSY = 0x00000007,
18746GRBM_SE4_PERF_SEL_TA_BUSY = 0x00000008,
18747GRBM_SE4_PERF_SEL_CB_CLEAN = 0x00000009,
18748GRBM_SE4_PERF_SEL_DB_CLEAN = 0x0000000a,
18749GRBM_SE4_PERF_SEL_PA_BUSY = 0x0000000c,
18750GRBM_SE4_PERF_SEL_BCI_BUSY = 0x0000000e,
18751GRBM_SE4_PERF_SEL_RMI_BUSY = 0x0000000f,
18752GRBM_SE4_PERF_SEL_UTCL1_BUSY = 0x00000010,
18753GRBM_SE4_PERF_SEL_TCP_BUSY = 0x00000011,
18754GRBM_SE4_PERF_SEL_GL1CC_BUSY = 0x00000012,
18755GRBM_SE4_PERF_SEL_GL1H_BUSY = 0x00000013,
18756GRBM_SE4_PERF_SEL_PC_BUSY = 0x00000014,
18757} GRBM_SE4_PERF_SEL;
18758
18759/*
18760 * GRBM_SE5_PERF_SEL enum
18761 */
18762
18763typedef enum GRBM_SE5_PERF_SEL {
18764GRBM_SE5_PERF_SEL_COUNT = 0x00000000,
18765GRBM_SE5_PERF_SEL_USER_DEFINED = 0x00000001,
18766GRBM_SE5_PERF_SEL_CB_BUSY = 0x00000002,
18767GRBM_SE5_PERF_SEL_DB_BUSY = 0x00000003,
18768GRBM_SE5_PERF_SEL_SC_BUSY = 0x00000004,
18769GRBM_SE5_PERF_SEL_SPI_BUSY = 0x00000006,
18770GRBM_SE5_PERF_SEL_SX_BUSY = 0x00000007,
18771GRBM_SE5_PERF_SEL_TA_BUSY = 0x00000008,
18772GRBM_SE5_PERF_SEL_CB_CLEAN = 0x00000009,
18773GRBM_SE5_PERF_SEL_DB_CLEAN = 0x0000000a,
18774GRBM_SE5_PERF_SEL_PA_BUSY = 0x0000000c,
18775GRBM_SE5_PERF_SEL_BCI_BUSY = 0x0000000e,
18776GRBM_SE5_PERF_SEL_RMI_BUSY = 0x0000000f,
18777GRBM_SE5_PERF_SEL_UTCL1_BUSY = 0x00000010,
18778GRBM_SE5_PERF_SEL_TCP_BUSY = 0x00000011,
18779GRBM_SE5_PERF_SEL_GL1CC_BUSY = 0x00000012,
18780GRBM_SE5_PERF_SEL_GL1H_BUSY = 0x00000013,
18781GRBM_SE5_PERF_SEL_PC_BUSY = 0x00000014,
18782} GRBM_SE5_PERF_SEL;
18783
18784/*
18785 * GRBM_SE6_PERF_SEL enum
18786 */
18787
18788typedef enum GRBM_SE6_PERF_SEL {
18789GRBM_SE6_PERF_SEL_COUNT = 0x00000000,
18790GRBM_SE6_PERF_SEL_USER_DEFINED = 0x00000001,
18791GRBM_SE6_PERF_SEL_CB_BUSY = 0x00000002,
18792GRBM_SE6_PERF_SEL_DB_BUSY = 0x00000003,
18793GRBM_SE6_PERF_SEL_SC_BUSY = 0x00000004,
18794GRBM_SE6_PERF_SEL_SPI_BUSY = 0x00000006,
18795GRBM_SE6_PERF_SEL_SX_BUSY = 0x00000007,
18796GRBM_SE6_PERF_SEL_TA_BUSY = 0x00000008,
18797GRBM_SE6_PERF_SEL_CB_CLEAN = 0x00000009,
18798GRBM_SE6_PERF_SEL_DB_CLEAN = 0x0000000a,
18799GRBM_SE6_PERF_SEL_PA_BUSY = 0x0000000c,
18800GRBM_SE6_PERF_SEL_BCI_BUSY = 0x0000000e,
18801GRBM_SE6_PERF_SEL_RMI_BUSY = 0x0000000f,
18802GRBM_SE6_PERF_SEL_UTCL1_BUSY = 0x00000010,
18803GRBM_SE6_PERF_SEL_TCP_BUSY = 0x00000011,
18804GRBM_SE6_PERF_SEL_GL1CC_BUSY = 0x00000012,
18805GRBM_SE6_PERF_SEL_GL1H_BUSY = 0x00000013,
18806GRBM_SE6_PERF_SEL_PC_BUSY = 0x00000014,
18807} GRBM_SE6_PERF_SEL;
18808
18809/*
18810 * GRBM_SE7_PERF_SEL enum
18811 */
18812
18813typedef enum GRBM_SE7_PERF_SEL {
18814GRBM_SE7_PERF_SEL_COUNT = 0x00000000,
18815GRBM_SE7_PERF_SEL_USER_DEFINED = 0x00000001,
18816GRBM_SE7_PERF_SEL_CB_BUSY = 0x00000002,
18817GRBM_SE7_PERF_SEL_DB_BUSY = 0x00000003,
18818GRBM_SE7_PERF_SEL_SC_BUSY = 0x00000004,
18819GRBM_SE7_PERF_SEL_SPI_BUSY = 0x00000006,
18820GRBM_SE7_PERF_SEL_SX_BUSY = 0x00000007,
18821GRBM_SE7_PERF_SEL_TA_BUSY = 0x00000008,
18822GRBM_SE7_PERF_SEL_CB_CLEAN = 0x00000009,
18823GRBM_SE7_PERF_SEL_DB_CLEAN = 0x0000000a,
18824GRBM_SE7_PERF_SEL_PA_BUSY = 0x0000000c,
18825GRBM_SE7_PERF_SEL_BCI_BUSY = 0x0000000e,
18826GRBM_SE7_PERF_SEL_RMI_BUSY = 0x0000000f,
18827GRBM_SE7_PERF_SEL_UTCL1_BUSY = 0x00000010,
18828GRBM_SE7_PERF_SEL_TCP_BUSY = 0x00000011,
18829GRBM_SE7_PERF_SEL_GL1CC_BUSY = 0x00000012,
18830GRBM_SE7_PERF_SEL_GL1H_BUSY = 0x00000013,
18831GRBM_SE7_PERF_SEL_PC_BUSY = 0x00000014,
18832} GRBM_SE7_PERF_SEL;
18833
18834/*
18835 * PIPE_COMPAT_LEVEL enum
18836 */
18837
18838typedef enum PIPE_COMPAT_LEVEL {
18839GEN_ZERO = 0x00000000,
18840GEN_ONE = 0x00000001,
18841GEN_TWO = 0x00000002,
18842GEN_RESERVED = 0x00000003,
18843} PIPE_COMPAT_LEVEL;
18844
18845/*******************************************************
18846 * CP Enums
18847 *******************************************************/
18848
18849/*
18850 * CPC_LATENCY_STATS_SEL enum
18851 */
18852
18853typedef enum CPC_LATENCY_STATS_SEL {
18854CPC_LATENCY_STATS_SEL_XACK_MAX = 0x00000000,
18855CPC_LATENCY_STATS_SEL_XACK_MIN = 0x00000001,
18856CPC_LATENCY_STATS_SEL_XACK_LAST = 0x00000002,
18857CPC_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003,
18858CPC_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004,
18859CPC_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005,
18860CPC_LATENCY_STATS_SEL_INVAL_MAX = 0x00000006,
18861CPC_LATENCY_STATS_SEL_INVAL_MIN = 0x00000007,
18862CPC_LATENCY_STATS_SEL_INVAL_LAST = 0x00000008,
18863} CPC_LATENCY_STATS_SEL;
18864
18865/*
18866 * CPC_PERFCOUNT_SEL enum
18867 */
18868
18869typedef enum CPC_PERFCOUNT_SEL {
18870CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000,
18871CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001,
18872CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002,
18873CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005,
18874CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006,
18875CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007,
18876CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008,
18877CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 0x00000009,
18878CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 0x0000000a,
18879CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b,
18880CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c,
18881CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d,
18882CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e,
18883CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f,
18884CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010,
18885CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 0x00000011,
18886CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 0x00000012,
18887CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013,
18888CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014,
18889CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015,
18890CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000016,
18891CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000017,
18892CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000018,
18893CPC_PERF_SEL_CPC_STAT_BUSY = 0x00000019,
18894CPC_PERF_SEL_CPC_STAT_IDLE = 0x0000001a,
18895CPC_PERF_SEL_CPC_STAT_STALL = 0x0000001b,
18896CPC_PERF_SEL_CPC_TCIU_BUSY = 0x0000001c,
18897CPC_PERF_SEL_CPC_TCIU_IDLE = 0x0000001d,
18898CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 0x0000001e,
18899CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 0x0000001f,
18900CPC_PERF_SEL_CPC_UTCL2IU_STALL = 0x00000020,
18901CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 0x00000021,
18902CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 0x00000022,
18903CPC_PERF_SEL_CPC_GCRIU_BUSY = 0x00000023,
18904CPC_PERF_SEL_CPC_GCRIU_IDLE = 0x00000024,
18905CPC_PERF_SEL_CPC_GCRIU_STALL = 0x00000025,
18906CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000026,
18907CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 0x00000027,
18908CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 0x00000028,
18909CPC_PERF_SEL_CPC_UTCL2IU_XACK = 0x00000029,
18910CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 0x0000002a,
18911CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 0x0000002b,
18912CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 0x0000002c,
18913CPC_PERF_SEL_MES_THREAD0 = 0x0000002d,
18914CPC_PERF_SEL_MES_THREAD1 = 0x0000002e,
18915} CPC_PERFCOUNT_SEL;
18916
18917/*
18918 * CPF_LATENCY_STATS_SEL enum
18919 */
18920
18921typedef enum CPF_LATENCY_STATS_SEL {
18922CPF_LATENCY_STATS_SEL_XACK_MAX = 0x00000000,
18923CPF_LATENCY_STATS_SEL_XACK_MIN = 0x00000001,
18924CPF_LATENCY_STATS_SEL_XACK_LAST = 0x00000002,
18925CPF_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003,
18926CPF_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004,
18927CPF_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005,
18928CPF_LATENCY_STATS_SEL_READ_MAX = 0x00000006,
18929CPF_LATENCY_STATS_SEL_READ_MIN = 0x00000007,
18930CPF_LATENCY_STATS_SEL_READ_LAST = 0x00000008,
18931CPF_LATENCY_STATS_SEL_INVAL_MAX = 0x00000009,
18932CPF_LATENCY_STATS_SEL_INVAL_MIN = 0x0000000a,
18933CPF_LATENCY_STATS_SEL_INVAL_LAST = 0x0000000b,
18934} CPF_LATENCY_STATS_SEL;
18935
18936/*
18937 * CPF_PERFCOUNTWINDOW_SEL enum
18938 */
18939
18940typedef enum CPF_PERFCOUNTWINDOW_SEL {
18941CPF_PERFWINDOW_SEL_CSF = 0x00000000,
18942CPF_PERFWINDOW_SEL_HQD1 = 0x00000001,
18943CPF_PERFWINDOW_SEL_HQD2 = 0x00000002,
18944CPF_PERFWINDOW_SEL_RDMA = 0x00000003,
18945CPF_PERFWINDOW_SEL_RWPP = 0x00000004,
18946} CPF_PERFCOUNTWINDOW_SEL;
18947
18948/*
18949 * CPF_PERFCOUNT_SEL enum
18950 */
18951
18952typedef enum CPF_PERFCOUNT_SEL {
18953CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000,
18954CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002,
18955CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003,
18956CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004,
18957CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005,
18958CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006,
18959CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_STATE = 0x00000007,
18960CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a,
18961CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b,
18962CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c,
18963CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d,
18964CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e,
18965CPF_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x0000000f,
18966CPF_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000010,
18967CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000011,
18968CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000012,
18969CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 0x00000013,
18970CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 0x00000014,
18971CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000015,
18972CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000016,
18973CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000017,
18974CPF_PERF_SEL_CPF_STAT_BUSY = 0x00000018,
18975CPF_PERF_SEL_CPF_STAT_IDLE = 0x00000019,
18976CPF_PERF_SEL_CPF_STAT_STALL = 0x0000001a,
18977CPF_PERF_SEL_CPF_TCIU_BUSY = 0x0000001b,
18978CPF_PERF_SEL_CPF_TCIU_IDLE = 0x0000001c,
18979CPF_PERF_SEL_CPF_TCIU_STALL = 0x0000001d,
18980CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 0x0000001e,
18981CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 0x0000001f,
18982CPF_PERF_SEL_CPF_UTCL2IU_STALL = 0x00000020,
18983CPF_PERF_SEL_CPF_GCRIU_BUSY = 0x00000021,
18984CPF_PERF_SEL_CPF_GCRIU_IDLE = 0x00000022,
18985CPF_PERF_SEL_CPF_GCRIU_STALL = 0x00000023,
18986CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000024,
18987CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 0x00000025,
18988CPF_PERF_SEL_CPF_UTCL2IU_XACK = 0x00000026,
18989CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 0x00000027,
18990CPF_PERF_SEL_CP_SDMA_MNGR_DMA_REQ = 0x00000028,
18991CPF_PERF_SEL_CP_SDMA_MNGR_DMA_DONE = 0x00000029,
18992CPF_PERF_SEL_CP_SDMA_MNGR_LATENCY = 0x0000002a,
18993CPF_PERF_SEL_CP_SDMA_MNGR_SDMABUSY = 0x0000002b,
18994} CPF_PERFCOUNT_SEL;
18995
18996/*
18997 * CPF_SCRATCH_REG_ATOMIC_OP enum
18998 */
18999
19000typedef enum CPF_SCRATCH_REG_ATOMIC_OP {
19001CPF_SCRATCH_REG_ATOMIC_ADD = 0x00000000,
19002CPF_SCRATCH_REG_ATOMIC_SUB = 0x00000001,
19003CPF_SCRATCH_REG_ATOMIC_OR = 0x00000002,
19004CPF_SCRATCH_REG_ATOMIC_AND = 0x00000003,
19005CPF_SCRATCH_REG_ATOMIC_NOT = 0x00000004,
19006CPF_SCRATCH_REG_ATOMIC_MIN = 0x00000005,
19007CPF_SCRATCH_REG_ATOMIC_MAX = 0x00000006,
19008CPF_SCRATCH_REG_ATOMIC_CMPSWAP = 0x00000007,
19009} CPF_SCRATCH_REG_ATOMIC_OP;
19010
19011/*
19012 * CPG_LATENCY_STATS_SEL enum
19013 */
19014
19015typedef enum CPG_LATENCY_STATS_SEL {
19016CPG_LATENCY_STATS_SEL_XACK_MAX = 0x00000000,
19017CPG_LATENCY_STATS_SEL_XACK_MIN = 0x00000001,
19018CPG_LATENCY_STATS_SEL_XACK_LAST = 0x00000002,
19019CPG_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003,
19020CPG_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004,
19021CPG_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005,
19022CPG_LATENCY_STATS_SEL_WRITE_MAX = 0x00000006,
19023CPG_LATENCY_STATS_SEL_WRITE_MIN = 0x00000007,
19024CPG_LATENCY_STATS_SEL_WRITE_LAST = 0x00000008,
19025CPG_LATENCY_STATS_SEL_READ_MAX = 0x00000009,
19026CPG_LATENCY_STATS_SEL_READ_MIN = 0x0000000a,
19027CPG_LATENCY_STATS_SEL_READ_LAST = 0x0000000b,
19028CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 0x0000000c,
19029CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 0x0000000d,
19030CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 0x0000000e,
19031CPG_LATENCY_STATS_SEL_INVAL_MAX = 0x0000000f,
19032CPG_LATENCY_STATS_SEL_INVAL_MIN = 0x00000010,
19033CPG_LATENCY_STATS_SEL_INVAL_LAST = 0x00000011,
19034} CPG_LATENCY_STATS_SEL;
19035
19036/*
19037 * CPG_PERFCOUNTWINDOW_SEL enum
19038 */
19039
19040typedef enum CPG_PERFCOUNTWINDOW_SEL {
19041CPG_PERFWINDOW_SEL_PFP = 0x00000000,
19042CPG_PERFWINDOW_SEL_ME = 0x00000001,
19043CPG_PERFWINDOW_SEL_CE = 0x00000002,
19044CPG_PERFWINDOW_SEL_MES = 0x00000003,
19045CPG_PERFWINDOW_SEL_MEC1 = 0x00000004,
19046CPG_PERFWINDOW_SEL_MEC2 = 0x00000005,
19047CPG_PERFWINDOW_SEL_DFY = 0x00000006,
19048CPG_PERFWINDOW_SEL_DMA = 0x00000007,
19049CPG_PERFWINDOW_SEL_SHADOW = 0x00000008,
19050CPG_PERFWINDOW_SEL_RB = 0x00000009,
19051CPG_PERFWINDOW_SEL_CEDMA = 0x0000000a,
19052CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 0x0000000b,
19053CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 0x0000000c,
19054CPG_PERFWINDOW_SEL_PQ1 = 0x0000000d,
19055CPG_PERFWINDOW_SEL_PQ2 = 0x0000000e,
19056CPG_PERFWINDOW_SEL_PQ3 = 0x0000000f,
19057CPG_PERFWINDOW_SEL_MEMWR = 0x00000010,
19058CPG_PERFWINDOW_SEL_MEMRD = 0x00000011,
19059CPG_PERFWINDOW_SEL_VGT0 = 0x00000012,
19060CPG_PERFWINDOW_SEL_VGT1 = 0x00000013,
19061CPG_PERFWINDOW_SEL_APPEND = 0x00000014,
19062CPG_PERFWINDOW_SEL_QURD = 0x00000015,
19063CPG_PERFWINDOW_SEL_DDID = 0x00000016,
19064CPG_PERFWINDOW_SEL_SR = 0x00000017,
19065CPG_PERFWINDOW_SEL_QU_EOP = 0x00000018,
19066CPG_PERFWINDOW_SEL_QU_STRM = 0x00000019,
19067CPG_PERFWINDOW_SEL_QU_PIPE = 0x0000001a,
19068CPG_PERFWINDOW_SEL_RESERVED1 = 0x0000001b,
19069CPG_PERFWINDOW_SEL_CPC_IC = 0x0000001c,
19070CPG_PERFWINDOW_SEL_RESERVED2 = 0x0000001d,
19071CPG_PERFWINDOW_SEL_CPG_IC = 0x0000001e,
19072} CPG_PERFCOUNTWINDOW_SEL;
19073
19074/*
19075 * CPG_PERFCOUNT_SEL enum
19076 */
19077
19078typedef enum CPG_PERFCOUNT_SEL {
19079CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000,
19080CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001,
19081CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004,
19082CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005,
19083CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006,
19084CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007,
19085CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009,
19086CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a,
19087CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b,
19088CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c,
19089CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d,
19090CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e,
19091CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f,
19092CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010,
19093CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011,
19094CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012,
19095CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013,
19096CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014,
19097CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015,
19098CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016,
19099CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017,
19100CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018,
19101CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019,
19102CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a,
19103CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b,
19104CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c,
19105CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d,
19106CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f,
19107CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020,
19108CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021,
19109CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x00000022,
19110CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000023,
19111CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024,
19112CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025,
19113CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026,
19114CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027,
19115CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029,
19116CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a,
19117CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b,
19118CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c,
19119CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d,
19120CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x0000002e,
19121CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x0000002f,
19122CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000030,
19123CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000031,
19124CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000032,
19125CPG_PERF_SEL_CPG_STAT_BUSY = 0x00000033,
19126CPG_PERF_SEL_CPG_STAT_IDLE = 0x00000034,
19127CPG_PERF_SEL_CPG_STAT_STALL = 0x00000035,
19128CPG_PERF_SEL_CPG_TCIU_BUSY = 0x00000036,
19129CPG_PERF_SEL_CPG_TCIU_IDLE = 0x00000037,
19130CPG_PERF_SEL_CPG_TCIU_STALL = 0x00000038,
19131CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 0x00000039,
19132CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 0x0000003a,
19133CPG_PERF_SEL_CPG_UTCL2IU_STALL = 0x0000003b,
19134CPG_PERF_SEL_CPG_GCRIU_BUSY = 0x0000003c,
19135CPG_PERF_SEL_CPG_GCRIU_IDLE = 0x0000003d,
19136CPG_PERF_SEL_CPG_GCRIU_STALL = 0x0000003e,
19137CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x0000003f,
19138CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 0x00000040,
19139CPG_PERF_SEL_CPG_UTCL2IU_XACK = 0x00000041,
19140CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 0x00000042,
19141CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 0x00000043,
19142CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 0x00000044,
19143CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 0x00000045,
19144CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 0x00000046,
19145CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 0x00000047,
19146CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 0x00000048,
19147CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 0x00000049,
19148CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 0x0000004a,
19149CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 0x0000004b,
19150CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 0x0000004c,
19151CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 0x0000004d,
19152CPG_PERF_SEL_DMA_BUSY = 0x0000004e,
19153CPG_PERF_SEL_DMA_STARVED = 0x0000004f,
19154CPG_PERF_SEL_DMA_STALLED = 0x00000050,
19155CPG_PERF_SEL_DMA_FETCHER_STALLED_ON_ROQ_FULL = 0x00000051,
19156CPG_PERF_SEL_PFP_PWS_STALLED0 = 0x00000052,
19157CPG_PERF_SEL_ME_PWS_STALLED0 = 0x00000053,
19158CPG_PERF_SEL_PFP_PWS_STALLED1 = 0x00000054,
19159CPG_PERF_SEL_ME_PWS_STALLED1 = 0x00000055,
19160} CPG_PERFCOUNT_SEL;
19161
19162/*
19163 * CP_ALPHA_TAG_RAM_SEL enum
19164 */
19165
19166typedef enum CP_ALPHA_TAG_RAM_SEL {
19167CPG_TAG_RAM = 0x00000000,
19168CPC_TAG_RAM = 0x00000001,
19169CPF_TAG_RAM = 0x00000002,
19170RSV_TAG_RAM = 0x00000003,
19171} CP_ALPHA_TAG_RAM_SEL;
19172
19173/*
19174 * CP_DDID_CNTL_MODE enum
19175 */
19176
19177typedef enum CP_DDID_CNTL_MODE {
19178STALL = 0x00000000,
19179OVERRUN = 0x00000001,
19180} CP_DDID_CNTL_MODE;
19181
19182/*
19183 * CP_DDID_CNTL_SIZE enum
19184 */
19185
19186typedef enum CP_DDID_CNTL_SIZE {
19187SIZE_8K = 0x00000000,
19188SIZE_16K = 0x00000001,
19189} CP_DDID_CNTL_SIZE;
19190
19191/*
19192 * CP_DDID_CNTL_VMID_SEL enum
19193 */
19194
19195typedef enum CP_DDID_CNTL_VMID_SEL {
19196DDID_VMID_PIPE = 0x00000000,
19197DDID_VMID_CNTL = 0x00000001,
19198} CP_DDID_CNTL_VMID_SEL;
19199
19200/*
19201 * CP_ME_ID enum
19202 */
19203
19204typedef enum CP_ME_ID {
19205ME_ID0 = 0x00000000,
19206ME_ID1 = 0x00000001,
19207ME_ID2 = 0x00000002,
19208ME_ID3 = 0x00000003,
19209} CP_ME_ID;
19210
19211/*
19212 * CP_PERFMON_ENABLE_MODE enum
19213 */
19214
19215typedef enum CP_PERFMON_ENABLE_MODE {
19216CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000,
19217CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001,
19218CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002,
19219CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003,
19220} CP_PERFMON_ENABLE_MODE;
19221
19222/*
19223 * CP_PERFMON_STATE enum
19224 */
19225
19226typedef enum CP_PERFMON_STATE {
19227CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
19228CP_PERFMON_STATE_START_COUNTING = 0x00000001,
19229CP_PERFMON_STATE_STOP_COUNTING = 0x00000002,
19230CP_PERFMON_STATE_RESERVED_3 = 0x00000003,
19231CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
19232CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
19233} CP_PERFMON_STATE;
19234
19235/*
19236 * CP_PIPE_ID enum
19237 */
19238
19239typedef enum CP_PIPE_ID {
19240PIPE_ID0 = 0x00000000,
19241PIPE_ID1 = 0x00000001,
19242PIPE_ID2 = 0x00000002,
19243PIPE_ID3 = 0x00000003,
19244} CP_PIPE_ID;
19245
19246/*
19247 * CP_RING_ID enum
19248 */
19249
19250typedef enum CP_RING_ID {
19251RINGID0 = 0x00000000,
19252RINGID1 = 0x00000001,
19253RINGID2 = 0x00000002,
19254RINGID3 = 0x00000003,
19255} CP_RING_ID;
19256
19257/*
19258 * SPM_PERFMON_STATE enum
19259 */
19260
19261typedef enum SPM_PERFMON_STATE {
19262STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
19263STRM_PERFMON_STATE_START_COUNTING = 0x00000001,
19264STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002,
19265STRM_PERFMON_STATE_RESERVED_3 = 0x00000003,
19266STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
19267STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
19268} SPM_PERFMON_STATE;
19269
19270/*
19271 * SEM_RESPONSE value
19272 */
19273
19274#define SEM_ECC_ERROR 0x00000000
19275#define SEM_TRANS_ERROR 0x00000001
19276#define SEM_RESP_FAILED 0x00000002
19277#define SEM_RESP_PASSED 0x00000003
19278
19279/*
19280 * IQ_RETRY_TYPE value
19281 */
19282
19283#define IQ_QUEUE_SLEEP 0x00000000
19284#define IQ_OFFLOAD_RETRY 0x00000001
19285#define IQ_SCH_WAVE_MSG 0x00000002
19286#define IQ_SEM_REARM 0x00000003
19287#define IQ_DEQUEUE_RETRY 0x00000004
19288
19289/*
19290 * IQ_INTR_TYPE value
19291 */
19292
19293#define IQ_INTR_TYPE_PQ 0x00000000
19294#define IQ_INTR_TYPE_IB 0x00000001
19295#define IQ_INTR_TYPE_MQD 0x00000002
19296
19297/*
19298 * VMID_SIZE value
19299 */
19300
19301#define VMID_SZ 0x00000004
19302
19303/*
19304 * SRCID_SECURE value
19305 */
19306
19307#define SRCID_RLC 0x00000000
19308#define SRCID_RLCV 0x00000006
19309#define SRCID_SECURE_CP 0x00000007
19310#define SRCID_NONSECURE_CP 0x00000001
19311#define SRCID_SECURE_CP_RCIU 0x00000007
19312#define SRCID_NONSECURE_CP_RCIU 0x00000001
19313
19314/*
19315 * CONFIG_SPACE value
19316 */
19317
19318#define CONFIG_SPACE_START 0x00002000
19319#define CONFIG_SPACE_END 0x00009fff
19320
19321/*
19322 * CONFIG_SPACE1 value
19323 */
19324
19325#define CONFIG_SPACE1_START 0x00002000
19326#define CONFIG_SPACE1_END 0x00002bff
19327
19328/*
19329 * CONFIG_SPACE2 value
19330 */
19331
19332#define CONFIG_SPACE2_START 0x00003000
19333#define CONFIG_SPACE2_END 0x00009fff
19334
19335/*
19336 * UCONFIG_SPACE value
19337 */
19338
19339#define UCONFIG_SPACE_START 0x0000c000
19340#define UCONFIG_SPACE_END 0x0000ffff
19341
19342/*
19343 * PERSISTENT_SPACE value
19344 */
19345
19346#define PERSISTENT_SPACE_START 0x00002c00
19347#define PERSISTENT_SPACE_END 0x00002fff
19348
19349/*
19350 * CONTEXT_SPACE value
19351 */
19352
19353#define CONTEXT_SPACE_START 0x0000a000
19354#define CONTEXT_SPACE_END 0x0000a3ff
19355
19356/*******************************************************
19357 * SX Enums
19358 *******************************************************/
19359
19360/*
19361 * SX_BLEND_OPT enum
19362 */
19363
19364typedef enum SX_BLEND_OPT {
19365BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000,
19366BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001,
19367BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002,
19368BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003,
19369BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004,
19370BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005,
19371BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006,
19372BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007,
19373} SX_BLEND_OPT;
19374
19375/*
19376 * SX_DOWNCONVERT_FORMAT enum
19377 */
19378
19379typedef enum SX_DOWNCONVERT_FORMAT {
19380SX_RT_EXPORT_NO_CONVERSION = 0x00000000,
19381SX_RT_EXPORT_32_R = 0x00000001,
19382SX_RT_EXPORT_32_A = 0x00000002,
19383SX_RT_EXPORT_10_11_11 = 0x00000003,
19384SX_RT_EXPORT_2_10_10_10 = 0x00000004,
19385SX_RT_EXPORT_8_8_8_8 = 0x00000005,
19386SX_RT_EXPORT_5_6_5 = 0x00000006,
19387SX_RT_EXPORT_1_5_5_5 = 0x00000007,
19388SX_RT_EXPORT_4_4_4_4 = 0x00000008,
19389SX_RT_EXPORT_16_16_GR = 0x00000009,
19390SX_RT_EXPORT_16_16_AR = 0x0000000a,
19391SX_RT_EXPORT_9_9_9_E5 = 0x0000000b,
19392SX_RT_EXPORT_2_10_10_10_7E3 = 0x0000000c,
19393SX_RT_EXPORT_2_10_10_10_6E4 = 0x0000000d,
19394} SX_DOWNCONVERT_FORMAT;
19395
19396/*
19397 * SX_OPT_COMB_FCN enum
19398 */
19399
19400typedef enum SX_OPT_COMB_FCN {
19401OPT_COMB_NONE = 0x00000000,
19402OPT_COMB_ADD = 0x00000001,
19403OPT_COMB_SUBTRACT = 0x00000002,
19404OPT_COMB_MIN = 0x00000003,
19405OPT_COMB_MAX = 0x00000004,
19406OPT_COMB_REVSUBTRACT = 0x00000005,
19407OPT_COMB_BLEND_DISABLED = 0x00000006,
19408OPT_COMB_SAFE_ADD = 0x00000007,
19409} SX_OPT_COMB_FCN;
19410
19411/*
19412 * SX_PERFCOUNTER_VALS enum
19413 */
19414
19415typedef enum SX_PERFCOUNTER_VALS {
19416SX_PERF_SEL_PA_IDLE_CYCLES = 0x00000000,
19417SX_PERF_SEL_PA_REQ = 0x00000001,
19418SX_PERF_SEL_PA_POS = 0x00000002,
19419SX_PERF_SEL_CLOCK = 0x00000003,
19420SX_PERF_SEL_GATE_EN1 = 0x00000004,
19421SX_PERF_SEL_GATE_EN2 = 0x00000005,
19422SX_PERF_SEL_GATE_EN3 = 0x00000006,
19423SX_PERF_SEL_GATE_EN4 = 0x00000007,
19424SX_PERF_SEL_SH_POS_STARVE = 0x00000008,
19425SX_PERF_SEL_SH_COLOR_STARVE = 0x00000009,
19426SX_PERF_SEL_SH_POS_STALL = 0x0000000a,
19427SX_PERF_SEL_SH_COLOR_STALL = 0x0000000b,
19428SX_PERF_SEL_DB0_PIXELS = 0x0000000c,
19429SX_PERF_SEL_DB0_HALF_QUADS = 0x0000000d,
19430SX_PERF_SEL_DB0_PIXEL_STALL = 0x0000000e,
19431SX_PERF_SEL_DB0_PIXEL_IDLE = 0x0000000f,
19432SX_PERF_SEL_DB0_PRED_PIXELS = 0x00000010,
19433SX_PERF_SEL_DB1_PIXELS = 0x00000011,
19434SX_PERF_SEL_DB1_HALF_QUADS = 0x00000012,
19435SX_PERF_SEL_DB1_PIXEL_STALL = 0x00000013,
19436SX_PERF_SEL_DB1_PIXEL_IDLE = 0x00000014,
19437SX_PERF_SEL_DB1_PRED_PIXELS = 0x00000015,
19438SX_PERF_SEL_DB2_PIXELS = 0x00000016,
19439SX_PERF_SEL_DB2_HALF_QUADS = 0x00000017,
19440SX_PERF_SEL_DB2_PIXEL_STALL = 0x00000018,
19441SX_PERF_SEL_DB2_PIXEL_IDLE = 0x00000019,
19442SX_PERF_SEL_DB2_PRED_PIXELS = 0x0000001a,
19443SX_PERF_SEL_DB3_PIXELS = 0x0000001b,
19444SX_PERF_SEL_DB3_HALF_QUADS = 0x0000001c,
19445SX_PERF_SEL_DB3_PIXEL_STALL = 0x0000001d,
19446SX_PERF_SEL_DB3_PIXEL_IDLE = 0x0000001e,
19447SX_PERF_SEL_DB3_PRED_PIXELS = 0x0000001f,
19448SX_PERF_SEL_COL_BUSY = 0x00000020,
19449SX_PERF_SEL_POS_BUSY = 0x00000021,
19450SX_PERF_SEL_DB0_MRT_BLEND_BYPASS = 0x00000022,
19451SX_PERF_SEL_DB0_MRT_DONT_RD_DEST = 0x00000023,
19452SX_PERF_SEL_DB0_MRT_DISCARD_SRC = 0x00000024,
19453SX_PERF_SEL_DB0_MRT_SINGLE_QUADS = 0x00000025,
19454SX_PERF_SEL_DB0_MRT_DOUBLE_QUADS = 0x00000026,
19455SX_PERF_SEL_DB1_MRT_BLEND_BYPASS = 0x00000027,
19456SX_PERF_SEL_DB1_MRT_DONT_RD_DEST = 0x00000028,
19457SX_PERF_SEL_DB1_MRT_DISCARD_SRC = 0x00000029,
19458SX_PERF_SEL_DB1_MRT_SINGLE_QUADS = 0x0000002a,
19459SX_PERF_SEL_DB1_MRT_DOUBLE_QUADS = 0x0000002b,
19460SX_PERF_SEL_DB2_MRT_BLEND_BYPASS = 0x0000002c,
19461SX_PERF_SEL_DB2_MRT_DONT_RD_DEST = 0x0000002d,
19462SX_PERF_SEL_DB2_MRT_DISCARD_SRC = 0x0000002e,
19463SX_PERF_SEL_DB2_MRT_SINGLE_QUADS = 0x0000002f,
19464SX_PERF_SEL_DB2_MRT_DOUBLE_QUADS = 0x00000030,
19465SX_PERF_SEL_DB3_MRT_BLEND_BYPASS = 0x00000031,
19466SX_PERF_SEL_DB3_MRT_DONT_RD_DEST = 0x00000032,
19467SX_PERF_SEL_DB3_MRT_DISCARD_SRC = 0x00000033,
19468SX_PERF_SEL_DB3_MRT_SINGLE_QUADS = 0x00000034,
19469SX_PERF_SEL_DB3_MRT_DOUBLE_QUADS = 0x00000035,
19470SX_PERF_SEL_PA_REQ_LATENCY = 0x00000036,
19471SX_PERF_SEL_POS_SCBD_STALL = 0x00000037,
19472SX_PERF_SEL_CLOCK_DROP_STALL = 0x00000038,
19473SX_PERF_SEL_GATE_EN5 = 0x00000039,
19474SX_PERF_SEL_GATE_EN6 = 0x0000003a,
19475SX_PERF_SEL_DB0_SIZE = 0x0000003b,
19476SX_PERF_SEL_DB1_SIZE = 0x0000003c,
19477SX_PERF_SEL_DB2_SIZE = 0x0000003d,
19478SX_PERF_SEL_DB3_SIZE = 0x0000003e,
19479SX_PERF_SEL_IDX_STALL_CYCLES = 0x0000003f,
19480SX_PERF_SEL_IDX_IDLE_CYCLES = 0x00000040,
19481SX_PERF_SEL_IDX_REQ = 0x00000041,
19482SX_PERF_SEL_IDX_RET = 0x00000042,
19483SX_PERF_SEL_IDX_REQ_LATENCY = 0x00000043,
19484SX_PERF_SEL_IDX_SCBD_STALL = 0x00000044,
19485SX_PERF_SEL_GATE_EN7 = 0x00000045,
19486SX_PERF_SEL_GATE_EN8 = 0x00000046,
19487SX_PERF_SEL_SH_IDX_STARVE = 0x00000047,
19488SX_PERF_SEL_IDX_BUSY = 0x00000048,
19489SX_PERF_SEL_PA_POS_BANK_CONF = 0x00000049,
19490SX_PERF_SEL_DB0_END_OF_WAVE = 0x0000004a,
19491SX_PERF_SEL_DB0_4X2_DISCARD = 0x0000004b,
19492SX_PERF_SEL_DB1_END_OF_WAVE = 0x0000004c,
19493SX_PERF_SEL_DB1_4X2_DISCARD = 0x0000004d,
19494SX_PERF_SEL_DB2_END_OF_WAVE = 0x0000004e,
19495SX_PERF_SEL_DB2_4X2_DISCARD = 0x0000004f,
19496SX_PERF_SEL_DB3_END_OF_WAVE = 0x00000050,
19497SX_PERF_SEL_DB3_4X2_DISCARD = 0x00000051,
19498} SX_PERFCOUNTER_VALS;
19499
19500/*******************************************************
19501 * DB Enums
19502 *******************************************************/
19503
19504/*
19505 * CompareFrag enum
19506 */
19507
19508typedef enum CompareFrag {
19509FRAG_NEVER = 0x00000000,
19510FRAG_LESS = 0x00000001,
19511FRAG_EQUAL = 0x00000002,
19512FRAG_LEQUAL = 0x00000003,
19513FRAG_GREATER = 0x00000004,
19514FRAG_NOTEQUAL = 0x00000005,
19515FRAG_GEQUAL = 0x00000006,
19516FRAG_ALWAYS = 0x00000007,
19517} CompareFrag;
19518
19519/*
19520 * ConservativeZExport enum
19521 */
19522
19523typedef enum ConservativeZExport {
19524EXPORT_ANY_Z = 0x00000000,
19525EXPORT_LESS_THAN_Z = 0x00000001,
19526EXPORT_GREATER_THAN_Z = 0x00000002,
19527EXPORT_RESERVED = 0x00000003,
19528} ConservativeZExport;
19529
19530/*
19531 * DFSMFlushEvents enum
19532 */
19533
19534typedef enum DFSMFlushEvents {
19535DB_FLUSH_AND_INV_DB_DATA_TS = 0x00000000,
19536DB_FLUSH_AND_INV_DB_META = 0x00000001,
19537DB_CACHE_FLUSH = 0x00000002,
19538DB_CACHE_FLUSH_TS = 0x00000003,
19539DB_CACHE_FLUSH_AND_INV_EVENT = 0x00000004,
19540DB_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000005,
19541DB_VPORT_CHANGED_EVENT = 0x00000006,
19542DB_CONTEXT_DONE_EVENT = 0x00000007,
19543DB_BREAK_BATCH_EVENT = 0x00000008,
19544DB_INVOKE_CHANGE_EVENT = 0x00000009,
19545DB_CONTEXT_SUSPEND_EVENT = 0x0000000a,
19546} DFSMFlushEvents;
19547
19548/*
19549 * DbMemArbWatermarks enum
19550 */
19551
19552typedef enum DbMemArbWatermarks {
19553TRANSFERRED_64_BYTES = 0x00000000,
19554TRANSFERRED_128_BYTES = 0x00000001,
19555TRANSFERRED_256_BYTES = 0x00000002,
19556TRANSFERRED_512_BYTES = 0x00000003,
19557TRANSFERRED_1024_BYTES = 0x00000004,
19558TRANSFERRED_2048_BYTES = 0x00000005,
19559TRANSFERRED_4096_BYTES = 0x00000006,
19560TRANSFERRED_8192_BYTES = 0x00000007,
19561} DbMemArbWatermarks;
19562
19563/*
19564 * DbPRTFaultBehavior enum
19565 */
19566
19567typedef enum DbPRTFaultBehavior {
19568FAULT_ZERO = 0x00000000,
19569FAULT_ONE = 0x00000001,
19570FAULT_FAIL = 0x00000002,
19571FAULT_PASS = 0x00000003,
19572} DbPRTFaultBehavior;
19573
19574/*
19575 * DbPSLControl enum
19576 */
19577
19578typedef enum DbPSLControl {
19579PSLC_AUTO = 0x00000000,
19580PSLC_ON_HANG_ONLY = 0x00000001,
19581PSLC_ASAP = 0x00000002,
19582PSLC_COUNTDOWN = 0x00000003,
19583} DbPSLControl;
19584
19585/*
19586 * ForceControl enum
19587 */
19588
19589typedef enum ForceControl {
19590FORCE_OFF = 0x00000000,
19591FORCE_ENABLE = 0x00000001,
19592FORCE_DISABLE = 0x00000002,
19593FORCE_RESERVED = 0x00000003,
19594} ForceControl;
19595
19596/*
19597 * OreoMode enum
19598 */
19599
19600typedef enum OreoMode {
19601OMODE_BLEND = 0x00000000,
19602OMODE_O_THEN_B = 0x00000001,
19603OMODE_P_THEN_O_THEN_B = 0x00000002,
19604OMODE_RESERVED_3 = 0x00000003,
19605} OreoMode;
19606
19607/*
19608 * PerfCounter_Vals enum
19609 */
19610
19611typedef enum PerfCounter_Vals {
19612DB_PERF_SEL_SC_DB_tile_sends = 0x00000000,
19613DB_PERF_SEL_SC_DB_tile_busy = 0x00000001,
19614DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002,
19615DB_PERF_SEL_SC_DB_tile_events = 0x00000003,
19616DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004,
19617DB_PERF_SEL_SC_DB_tile_covered = 0x00000005,
19618DB_PERF_SEL_hiz_tc_read_starved = 0x00000006,
19619DB_PERF_SEL_hiz_tc_write_stall = 0x00000007,
19620DB_PERF_SEL_hiz_tile_culled = 0x00000008,
19621DB_PERF_SEL_his_tile_culled = 0x00000009,
19622DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a,
19623DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b,
19624DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c,
19625DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d,
19626DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e,
19627DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f,
19628DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010,
19629DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011,
19630DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012,
19631DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013,
19632DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014,
19633DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015,
19634DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016,
19635DB_PERF_SEL_SC_DB_quad_sends = 0x00000017,
19636DB_PERF_SEL_SC_DB_quad_busy = 0x00000018,
19637DB_PERF_SEL_SC_DB_quad_squads = 0x00000019,
19638DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a,
19639DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b,
19640DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c,
19641DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d,
19642DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e,
19643DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f,
19644DB_PERF_SEL_DB_SC_quad_tiles = 0x00000020,
19645DB_PERF_SEL_DB_SC_quad_lit_quad = 0x00000021,
19646DB_PERF_SEL_DB_CB_tile_sends = 0x00000022,
19647DB_PERF_SEL_DB_CB_tile_busy = 0x00000023,
19648DB_PERF_SEL_DB_CB_tile_stalls = 0x00000024,
19649DB_PERF_SEL_SX_DB_quad_sends = 0x00000025,
19650DB_PERF_SEL_SX_DB_quad_busy = 0x00000026,
19651DB_PERF_SEL_SX_DB_quad_stalls = 0x00000027,
19652DB_PERF_SEL_SX_DB_quad_quads = 0x00000028,
19653DB_PERF_SEL_SX_DB_quad_pixels = 0x00000029,
19654DB_PERF_SEL_SX_DB_quad_exports = 0x0000002a,
19655DB_PERF_SEL_SH_quads_outstanding_sum = 0x0000002b,
19656DB_PERF_SEL_DB_CB_lquad_sends = 0x0000002c,
19657DB_PERF_SEL_DB_CB_lquad_busy = 0x0000002d,
19658DB_PERF_SEL_DB_CB_lquad_stalls = 0x0000002e,
19659DB_PERF_SEL_DB_CB_lquad_quads = 0x0000002f,
19660DB_PERF_SEL_tile_rd_sends = 0x00000030,
19661DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x00000031,
19662DB_PERF_SEL_quad_rd_sends = 0x00000032,
19663DB_PERF_SEL_quad_rd_busy = 0x00000033,
19664DB_PERF_SEL_quad_rd_mi_stall = 0x00000034,
19665DB_PERF_SEL_quad_rd_rw_collision = 0x00000035,
19666DB_PERF_SEL_quad_rd_tag_stall = 0x00000036,
19667DB_PERF_SEL_quad_rd_32byte_reqs = 0x00000037,
19668DB_PERF_SEL_quad_rd_panic = 0x00000038,
19669DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x00000039,
19670DB_PERF_SEL_quad_rdret_sends = 0x0000003a,
19671DB_PERF_SEL_quad_rdret_busy = 0x0000003b,
19672DB_PERF_SEL_tile_wr_sends = 0x0000003c,
19673DB_PERF_SEL_tile_wr_acks = 0x0000003d,
19674DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x0000003e,
19675DB_PERF_SEL_quad_wr_sends = 0x0000003f,
19676DB_PERF_SEL_quad_wr_busy = 0x00000040,
19677DB_PERF_SEL_quad_wr_mi_stall = 0x00000041,
19678DB_PERF_SEL_quad_wr_coherency_stall = 0x00000042,
19679DB_PERF_SEL_quad_wr_acks = 0x00000043,
19680DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x00000044,
19681DB_PERF_SEL_Tile_Cache_misses = 0x00000045,
19682DB_PERF_SEL_Tile_Cache_hits = 0x00000046,
19683DB_PERF_SEL_Tile_Cache_flushes = 0x00000047,
19684DB_PERF_SEL_Tile_Cache_surface_stall = 0x00000048,
19685DB_PERF_SEL_Tile_Cache_starves = 0x00000049,
19686DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a,
19687DB_PERF_SEL_tcp_dispatcher_reads = 0x0000004b,
19688DB_PERF_SEL_tcp_prefetcher_reads = 0x0000004c,
19689DB_PERF_SEL_tcp_preloader_reads = 0x0000004d,
19690DB_PERF_SEL_tcp_dispatcher_flushes = 0x0000004e,
19691DB_PERF_SEL_tcp_prefetcher_flushes = 0x0000004f,
19692DB_PERF_SEL_tcp_preloader_flushes = 0x00000050,
19693DB_PERF_SEL_Depth_Tile_Cache_sends = 0x00000051,
19694DB_PERF_SEL_Depth_Tile_Cache_busy = 0x00000052,
19695DB_PERF_SEL_Depth_Tile_Cache_starves = 0x00000053,
19696DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054,
19697DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055,
19698DB_PERF_SEL_Depth_Tile_Cache_misses = 0x00000056,
19699DB_PERF_SEL_Depth_Tile_Cache_hits = 0x00000057,
19700DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x00000058,
19701DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x00000059,
19702DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a,
19703DB_PERF_SEL_Depth_Tile_Cache_event = 0x0000005b,
19704DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x0000005c,
19705DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x0000005d,
19706DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e,
19707DB_PERF_SEL_Stencil_Cache_misses = 0x0000005f,
19708DB_PERF_SEL_Stencil_Cache_hits = 0x00000060,
19709DB_PERF_SEL_Stencil_Cache_flushes = 0x00000061,
19710DB_PERF_SEL_Stencil_Cache_starves = 0x00000062,
19711DB_PERF_SEL_Stencil_Cache_frees = 0x00000063,
19712DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x00000064,
19713DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x00000065,
19714DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x00000066,
19715DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x00000067,
19716DB_PERF_SEL_Z_Cache_pmask_misses = 0x00000068,
19717DB_PERF_SEL_Z_Cache_pmask_hits = 0x00000069,
19718DB_PERF_SEL_Z_Cache_pmask_flushes = 0x0000006a,
19719DB_PERF_SEL_Z_Cache_pmask_starves = 0x0000006b,
19720DB_PERF_SEL_Z_Cache_frees = 0x0000006c,
19721DB_PERF_SEL_Plane_Cache_misses = 0x0000006d,
19722DB_PERF_SEL_Plane_Cache_hits = 0x0000006e,
19723DB_PERF_SEL_Plane_Cache_flushes = 0x0000006f,
19724DB_PERF_SEL_Plane_Cache_starves = 0x00000070,
19725DB_PERF_SEL_Plane_Cache_frees = 0x00000071,
19726DB_PERF_SEL_flush_expanded_stencil = 0x00000072,
19727DB_PERF_SEL_flush_compressed_stencil = 0x00000073,
19728DB_PERF_SEL_flush_single_stencil = 0x00000074,
19729DB_PERF_SEL_planes_flushed = 0x00000075,
19730DB_PERF_SEL_flush_1plane = 0x00000076,
19731DB_PERF_SEL_flush_2plane = 0x00000077,
19732DB_PERF_SEL_flush_3plane = 0x00000078,
19733DB_PERF_SEL_flush_4plane = 0x00000079,
19734DB_PERF_SEL_flush_5plane = 0x0000007a,
19735DB_PERF_SEL_flush_6plane = 0x0000007b,
19736DB_PERF_SEL_flush_7plane = 0x0000007c,
19737DB_PERF_SEL_flush_8plane = 0x0000007d,
19738DB_PERF_SEL_flush_9plane = 0x0000007e,
19739DB_PERF_SEL_flush_10plane = 0x0000007f,
19740DB_PERF_SEL_flush_11plane = 0x00000080,
19741DB_PERF_SEL_flush_12plane = 0x00000081,
19742DB_PERF_SEL_flush_13plane = 0x00000082,
19743DB_PERF_SEL_flush_14plane = 0x00000083,
19744DB_PERF_SEL_flush_15plane = 0x00000084,
19745DB_PERF_SEL_flush_16plane = 0x00000085,
19746DB_PERF_SEL_flush_expanded_z = 0x00000086,
19747DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087,
19748DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x00000088,
19749DB_PERF_SEL_dk_tile_sends = 0x00000089,
19750DB_PERF_SEL_dk_tile_busy = 0x0000008a,
19751DB_PERF_SEL_dk_tile_quad_starves = 0x0000008b,
19752DB_PERF_SEL_dk_tile_stalls = 0x0000008c,
19753DB_PERF_SEL_dk_squad_sends = 0x0000008d,
19754DB_PERF_SEL_dk_squad_busy = 0x0000008e,
19755DB_PERF_SEL_dk_squad_stalls = 0x0000008f,
19756DB_PERF_SEL_Op_Pipe_Busy = 0x00000090,
19757DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x00000091,
19758DB_PERF_SEL_qc_busy = 0x00000092,
19759DB_PERF_SEL_qc_xfc = 0x00000093,
19760DB_PERF_SEL_qc_conflicts = 0x00000094,
19761DB_PERF_SEL_qc_full_stall = 0x00000095,
19762DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096,
19763DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097,
19764DB_PERF_SEL_tsc_insert_summarize_stall = 0x00000098,
19765DB_PERF_SEL_tl_busy = 0x00000099,
19766DB_PERF_SEL_tl_dtc_read_starved = 0x0000009a,
19767DB_PERF_SEL_tl_z_fetch_stall = 0x0000009b,
19768DB_PERF_SEL_tl_stencil_stall = 0x0000009c,
19769DB_PERF_SEL_tl_z_decompress_stall = 0x0000009d,
19770DB_PERF_SEL_tl_stencil_locked_stall = 0x0000009e,
19771DB_PERF_SEL_tl_events = 0x0000009f,
19772DB_PERF_SEL_tl_summarize_squads = 0x000000a0,
19773DB_PERF_SEL_tl_flush_expand_squads = 0x000000a1,
19774DB_PERF_SEL_tl_expand_squads = 0x000000a2,
19775DB_PERF_SEL_tl_preZ_squads = 0x000000a3,
19776DB_PERF_SEL_tl_postZ_squads = 0x000000a4,
19777DB_PERF_SEL_tl_preZ_noop_squads = 0x000000a5,
19778DB_PERF_SEL_tl_postZ_noop_squads = 0x000000a6,
19779DB_PERF_SEL_tl_tile_ops = 0x000000a7,
19780DB_PERF_SEL_tl_in_xfc = 0x000000a8,
19781DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9,
19782DB_PERF_SEL_tl_in_fast_z_stall = 0x000000aa,
19783DB_PERF_SEL_tl_out_xfc = 0x000000ab,
19784DB_PERF_SEL_tl_out_squads = 0x000000ac,
19785DB_PERF_SEL_zf_plane_multicycle = 0x000000ad,
19786DB_PERF_SEL_PostZ_Samples_passing_Z = 0x000000ae,
19787DB_PERF_SEL_PostZ_Samples_failing_Z = 0x000000af,
19788DB_PERF_SEL_PostZ_Samples_failing_S = 0x000000b0,
19789DB_PERF_SEL_PreZ_Samples_passing_Z = 0x000000b1,
19790DB_PERF_SEL_PreZ_Samples_failing_Z = 0x000000b2,
19791DB_PERF_SEL_PreZ_Samples_failing_S = 0x000000b3,
19792DB_PERF_SEL_ts_tc_update_stall = 0x000000b4,
19793DB_PERF_SEL_sc_kick_start = 0x000000b5,
19794DB_PERF_SEL_sc_kick_end = 0x000000b6,
19795DB_PERF_SEL_clock_reg_active = 0x000000b7,
19796DB_PERF_SEL_clock_main_active = 0x000000b8,
19797DB_PERF_SEL_clock_mem_export_active = 0x000000b9,
19798DB_PERF_SEL_esr_ps_out_busy = 0x000000ba,
19799DB_PERF_SEL_esr_ps_lqf_busy = 0x000000bb,
19800DB_PERF_SEL_esr_ps_lqf_stall = 0x000000bc,
19801DB_PERF_SEL_etr_out_send = 0x000000bd,
19802DB_PERF_SEL_etr_out_busy = 0x000000be,
19803DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf,
19804DB_PERF_SEL_etr_out_cb_tile_stall = 0x000000c0,
19805DB_PERF_SEL_etr_out_esr_stall = 0x000000c1,
19806DB_PERF_SEL_esr_ps_vic_busy = 0x000000c2,
19807DB_PERF_SEL_esr_ps_vic_stall = 0x000000c3,
19808DB_PERF_SEL_esr_eot_fwd_busy = 0x000000c4,
19809DB_PERF_SEL_esr_eot_fwd_holding_squad = 0x000000c5,
19810DB_PERF_SEL_esr_eot_fwd_forward = 0x000000c6,
19811DB_PERF_SEL_esr_sqq_zi_busy = 0x000000c7,
19812DB_PERF_SEL_esr_sqq_zi_stall = 0x000000c8,
19813DB_PERF_SEL_postzl_sq_pt_busy = 0x000000c9,
19814DB_PERF_SEL_postzl_sq_pt_stall = 0x000000ca,
19815DB_PERF_SEL_postzl_se_busy = 0x000000cb,
19816DB_PERF_SEL_postzl_se_stall = 0x000000cc,
19817DB_PERF_SEL_postzl_partial_launch = 0x000000cd,
19818DB_PERF_SEL_postzl_full_launch = 0x000000ce,
19819DB_PERF_SEL_postzl_partial_waiting = 0x000000cf,
19820DB_PERF_SEL_postzl_tile_mem_stall = 0x000000d0,
19821DB_PERF_SEL_postzl_tile_init_stall = 0x000000d1,
19822DB_PERF_SEL_prezl_tile_mem_stall = 0x000000d2,
19823DB_PERF_SEL_prezl_tile_init_stall = 0x000000d3,
19824DB_PERF_SEL_dtt_sm_clash_stall = 0x000000d4,
19825DB_PERF_SEL_dtt_sm_slot_stall = 0x000000d5,
19826DB_PERF_SEL_dtt_sm_miss_stall = 0x000000d6,
19827DB_PERF_SEL_mi_rdreq_busy = 0x000000d7,
19828DB_PERF_SEL_mi_rdreq_stall = 0x000000d8,
19829DB_PERF_SEL_mi_wrreq_busy = 0x000000d9,
19830DB_PERF_SEL_mi_wrreq_stall = 0x000000da,
19831DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db,
19832DB_PERF_SEL_dkg_tile_rate_tile = 0x000000dc,
19833DB_PERF_SEL_prezl_src_in_sends = 0x000000dd,
19834DB_PERF_SEL_prezl_src_in_stall = 0x000000de,
19835DB_PERF_SEL_prezl_src_in_squads = 0x000000df,
19836DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0,
19837DB_PERF_SEL_prezl_src_in_tile_rate = 0x000000e1,
19838DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2,
19839DB_PERF_SEL_prezl_src_out_stall = 0x000000e3,
19840DB_PERF_SEL_postzl_src_in_sends = 0x000000e4,
19841DB_PERF_SEL_postzl_src_in_stall = 0x000000e5,
19842DB_PERF_SEL_postzl_src_in_squads = 0x000000e6,
19843DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7,
19844DB_PERF_SEL_postzl_src_in_tile_rate = 0x000000e8,
19845DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9,
19846DB_PERF_SEL_postzl_src_out_stall = 0x000000ea,
19847DB_PERF_SEL_esr_ps_src_in_sends = 0x000000eb,
19848DB_PERF_SEL_esr_ps_src_in_stall = 0x000000ec,
19849DB_PERF_SEL_esr_ps_src_in_squads = 0x000000ed,
19850DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee,
19851DB_PERF_SEL_esr_ps_src_in_tile_rate = 0x000000ef,
19852DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0,
19853DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1,
19854DB_PERF_SEL_esr_ps_src_out_stall = 0x000000f2,
19855DB_PERF_SEL_depth_bounds_tile_culled = 0x000000f3,
19856DB_PERF_SEL_PreZ_Samples_failing_DB = 0x000000f4,
19857DB_PERF_SEL_PostZ_Samples_failing_DB = 0x000000f5,
19858DB_PERF_SEL_flush_compressed = 0x000000f6,
19859DB_PERF_SEL_flush_plane_le4 = 0x000000f7,
19860DB_PERF_SEL_tiles_z_fully_summarized = 0x000000f8,
19861DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9,
19862DB_PERF_SEL_tiles_z_clear_on_expclear = 0x000000fa,
19863DB_PERF_SEL_tiles_s_clear_on_expclear = 0x000000fb,
19864DB_PERF_SEL_tiles_decomp_on_expclear = 0x000000fc,
19865DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd,
19866DB_PERF_SEL_Op_Pipe_Prez_Busy = 0x000000fe,
19867DB_PERF_SEL_Op_Pipe_Postz_Busy = 0x000000ff,
19868DB_PERF_SEL_di_dt_stall = 0x00000100,
19869Spare_257 = 0x00000101,
19870DB_PERF_SEL_DB_SC_s_tile_rate = 0x00000102,
19871DB_PERF_SEL_DB_SC_c_tile_rate = 0x00000103,
19872DB_PERF_SEL_DB_SC_z_tile_rate = 0x00000104,
19873DB_PERF_SEL_DB_CB_lquad_export_quads = 0x00000105,
19874DB_PERF_SEL_DB_CB_lquad_double_format = 0x00000106,
19875DB_PERF_SEL_DB_CB_lquad_fast_format = 0x00000107,
19876DB_PERF_SEL_DB_CB_lquad_slow_format = 0x00000108,
19877DB_PERF_SEL_CB_DB_rdreq_sends = 0x00000109,
19878DB_PERF_SEL_CB_DB_rdreq_prt_sends = 0x0000010a,
19879DB_PERF_SEL_CB_DB_wrreq_sends = 0x0000010b,
19880DB_PERF_SEL_CB_DB_wrreq_prt_sends = 0x0000010c,
19881DB_PERF_SEL_DB_CB_rdret_ack = 0x0000010d,
19882DB_PERF_SEL_DB_CB_rdret_nack = 0x0000010e,
19883DB_PERF_SEL_DB_CB_wrret_ack = 0x0000010f,
19884DB_PERF_SEL_DB_CB_wrret_nack = 0x00000110,
19885DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 0x00000111,
19886DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 0x00000112,
19887DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 0x00000113,
19888DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 0x00000114,
19889DB_PERF_SEL_unmapped_z_tile_culled = 0x00000115,
19890DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 0x00000116,
19891DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000117,
19892DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 0x00000118,
19893DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 0x00000119,
19894DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 0x0000011a,
19895DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 0x0000011b,
19896DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 0x0000011c,
19897DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 0x0000011d,
19898DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 0x0000011e,
19899DB_PERF_SEL_DB_CB_context_dones = 0x0000011f,
19900DB_PERF_SEL_DB_CB_eop_dones = 0x00000120,
19901DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 0x00000121,
19902DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 0x00000122,
19903DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 0x00000123,
19904DB_PERF_SEL_SC_DB_tile_backface = 0x00000124,
19905DB_PERF_SEL_SC_DB_quad_quads = 0x00000125,
19906DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 0x00000126,
19907DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 0x00000127,
19908DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 0x00000128,
19909DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 0x00000129,
19910DB_PERF_SEL_DB_SC_quad_double_quad = 0x0000012a,
19911DB_PERF_SEL_SX_DB_quad_export_quads = 0x0000012b,
19912DB_PERF_SEL_SX_DB_quad_double_format = 0x0000012c,
19913DB_PERF_SEL_SX_DB_quad_fast_format = 0x0000012d,
19914DB_PERF_SEL_SX_DB_quad_slow_format = 0x0000012e,
19915DB_PERF_SEL_quad_rd_sends_unc = 0x0000012f,
19916DB_PERF_SEL_quad_rd_mi_stall_unc = 0x00000130,
19917DB_PERF_SEL_SC_DB_tile_tiles_pipe0 = 0x00000131,
19918DB_PERF_SEL_SC_DB_tile_tiles_pipe1 = 0x00000132,
19919DB_PERF_SEL_SC_DB_quad_quads_pipe0 = 0x00000133,
19920DB_PERF_SEL_SC_DB_quad_quads_pipe1 = 0x00000134,
19921DB_PERF_SEL_PERF_fg_lob_fwdr_timeout_hits = 0x00000135,
19922DB_PERF_SEL_noz_waiting_for_postz_done = 0x00000136,
19923DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x1 = 0x00000137,
19924DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x1 = 0x00000138,
19925DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_1x2 = 0x00000139,
19926DB_PERF_SEL_DB_CB_lquad_quads_vrs_rate_2x2 = 0x0000013a,
19927DB_PERF_SEL_RMI_rd_tile_32byte_req = 0x0000013b,
19928DB_PERF_SEL_RMI_rd_z_32byte_req = 0x0000013c,
19929DB_PERF_SEL_RMI_rd_s_32byte_req = 0x0000013d,
19930DB_PERF_SEL_RMI_wr_tile_32byte_req = 0x0000013e,
19931DB_PERF_SEL_RMI_wr_z_32byte_req = 0x0000013f,
19932DB_PERF_SEL_RMI_wr_s_32byte_req = 0x00000140,
19933DB_PERF_SEL_RMI_wr_psdzpc_32byte_req = 0x00000141,
19934DB_PERF_SEL_RMI_rd_tile_32byte_ret = 0x00000142,
19935DB_PERF_SEL_RMI_rd_z_32byte_ret = 0x00000143,
19936DB_PERF_SEL_RMI_rd_s_32byte_ret = 0x00000144,
19937DB_PERF_SEL_RMI_wr_tile_32byte_ack = 0x00000145,
19938DB_PERF_SEL_RMI_wr_z_32byte_ack = 0x00000146,
19939DB_PERF_SEL_RMI_wr_s_32byte_ack = 0x00000147,
19940DB_PERF_SEL_RMI_wr_psdzpc_32byte_ack = 0x00000148,
19941DB_PERF_SEL_esr_vic_sqq_busy = 0x00000149,
19942DB_PERF_SEL_esr_vic_sqq_stall = 0x0000014a,
19943DB_PERF_SEL_esr_psi_vic_tile_rate = 0x0000014b,
19944DB_PERF_SEL_esr_vic_footprint_match_2x2 = 0x0000014c,
19945DB_PERF_SEL_esr_vic_footprint_match_2x1 = 0x0000014d,
19946DB_PERF_SEL_esr_vic_footprint_match_1x2 = 0x0000014e,
19947DB_PERF_SEL_DB_SC_quad_num_null_2x2_coarse_pixels = 0x0000014f,
19948DB_PERF_SEL_DB_SC_quad_num_null_2x1_coarse_pixels = 0x00000150,
19949DB_PERF_SEL_DB_SC_quad_num_null_1x2_coarse_pixels = 0x00000151,
19950DB_PERF_SEL_hi_z_s_checker_force_coarse_vrs_1x1 = 0x00000152,
19951DB_PERF_SEL_hi_z_s_checker_force_ssaa_vrs_1x1 = 0x00000153,
19952DB_PERF_SEL_esr_ps_woc_1squadIn_2squadOut = 0x00000154,
19953DB_PERF_SEL_esr_ps_woc_2squadIn_1squadOut = 0x00000155,
19954DB_PERF_SEL_prez_ps_invoked_pixel_cnt = 0x00000156,
19955DB_PERF_SEL_postz_ps_invoked_pixel_cnt = 0x00000157,
19956DB_PERF_SEL_ts_events_pws_enable = 0x00000158,
19957DB_PERF_SEL_ps_events_pws_enable = 0x00000159,
19958DB_PERF_SEL_cs_events_pws_enable = 0x0000015a,
19959DB_PERF_SEL_DB_SC_quad_noz_tiles = 0x0000015b,
19960DB_PERF_SEL_DB_SC_quad_lit_noz_quad = 0x0000015c,
19961} PerfCounter_Vals;
19962
19963/*
19964 * PixelPipeCounterId enum
19965 */
19966
19967typedef enum PixelPipeCounterId {
19968PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000,
19969PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001,
19970PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002,
19971PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003,
19972PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x00000004,
19973PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x00000005,
19974PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x00000006,
19975PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x00000007,
19976} PixelPipeCounterId;
19977
19978/*
19979 * PixelPipeStride enum
19980 */
19981
19982typedef enum PixelPipeStride {
19983PIXEL_PIPE_STRIDE_32_BITS = 0x00000000,
19984PIXEL_PIPE_STRIDE_64_BITS = 0x00000001,
19985PIXEL_PIPE_STRIDE_128_BITS = 0x00000002,
19986PIXEL_PIPE_STRIDE_256_BITS = 0x00000003,
19987} PixelPipeStride;
19988
19989/*
19990 * RingCounterControl enum
19991 */
19992
19993typedef enum RingCounterControl {
19994COUNTER_RING_SPLIT = 0x00000000,
19995COUNTER_RING_0 = 0x00000001,
19996COUNTER_RING_1 = 0x00000002,
19997} RingCounterControl;
19998
19999/*
20000 * StencilOp enum
20001 */
20002
20003typedef enum StencilOp {
20004STENCIL_KEEP = 0x00000000,
20005STENCIL_ZERO = 0x00000001,
20006STENCIL_ONES = 0x00000002,
20007STENCIL_REPLACE_TEST = 0x00000003,
20008STENCIL_REPLACE_OP = 0x00000004,
20009STENCIL_ADD_CLAMP = 0x00000005,
20010STENCIL_SUB_CLAMP = 0x00000006,
20011STENCIL_INVERT = 0x00000007,
20012STENCIL_ADD_WRAP = 0x00000008,
20013STENCIL_SUB_WRAP = 0x00000009,
20014STENCIL_AND = 0x0000000a,
20015STENCIL_OR = 0x0000000b,
20016STENCIL_XOR = 0x0000000c,
20017STENCIL_NAND = 0x0000000d,
20018STENCIL_NOR = 0x0000000e,
20019STENCIL_XNOR = 0x0000000f,
20020} StencilOp;
20021
20022/*
20023 * ZLimitSumm enum
20024 */
20025
20026typedef enum ZLimitSumm {
20027FORCE_SUMM_OFF = 0x00000000,
20028FORCE_SUMM_MINZ = 0x00000001,
20029FORCE_SUMM_MAXZ = 0x00000002,
20030FORCE_SUMM_BOTH = 0x00000003,
20031} ZLimitSumm;
20032
20033/*
20034 * ZModeForce enum
20035 */
20036
20037typedef enum ZModeForce {
20038NO_FORCE = 0x00000000,
20039FORCE_EARLY_Z = 0x00000001,
20040FORCE_LATE_Z = 0x00000002,
20041FORCE_RE_Z = 0x00000003,
20042} ZModeForce;
20043
20044/*
20045 * ZOrder enum
20046 */
20047
20048typedef enum ZOrder {
20049LATE_Z = 0x00000000,
20050EARLY_Z_THEN_LATE_Z = 0x00000001,
20051RE_Z = 0x00000002,
20052EARLY_Z_THEN_RE_Z = 0x00000003,
20053} ZOrder;
20054
20055/*
20056 * ZSamplePosition enum
20057 */
20058
20059typedef enum ZSamplePosition {
20060Z_SAMPLE_CENTER = 0x00000000,
20061Z_SAMPLE_CENTROID = 0x00000001,
20062} ZSamplePosition;
20063
20064/*
20065 * ZpassControl enum
20066 */
20067
20068typedef enum ZpassControl {
20069ZPASS_DISABLE = 0x00000000,
20070ZPASS_SAMPLES = 0x00000001,
20071ZPASS_PIXELS = 0x00000002,
20072} ZpassControl;
20073
20074/*******************************************************
20075 * PA Enums
20076 *******************************************************/
20077
20078/*
20079 * SU_PERFCNT_SEL enum
20080 */
20081
20082typedef enum SU_PERFCNT_SEL {
20083PERF_PAPC_PASX_REQ = 0x00000000,
20084PERF_PAPC_PASX_DISABLE_PIPE = 0x00000001,
20085PERF_PAPC_PASX_FIRST_VECTOR = 0x00000002,
20086PERF_PAPC_PASX_SECOND_VECTOR = 0x00000003,
20087PERF_PAPC_PASX_FIRST_DEAD = 0x00000004,
20088PERF_PAPC_PASX_SECOND_DEAD = 0x00000005,
20089PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006,
20090PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007,
20091PERF_PAPC_PA_INPUT_PRIM = 0x00000008,
20092PERF_PAPC_PA_INPUT_NULL_PRIM = 0x00000009,
20093PERF_PAPC_PA_INPUT_EVENT_FLAG = 0x0000000a,
20094PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0x0000000b,
20095PERF_PAPC_PA_INPUT_END_OF_PACKET = 0x0000000c,
20096PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0x0000000d,
20097PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e,
20098PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f,
20099PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010,
20100PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011,
20101PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012,
20102PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013,
20103PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014,
20104PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015,
20105PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016,
20106PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017,
20107PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018,
20108PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019,
20109PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a,
20110PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b,
20111PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c,
20112PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d,
20113PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000001e,
20114PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f,
20115PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020,
20116PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021,
20117PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022,
20118PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023,
20119PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024,
20120PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x00000025,
20121PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026,
20122PERF_PAPC_CLSM_NULL_PRIM = 0x00000027,
20123PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028,
20124PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029,
20125PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a,
20126PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b,
20127PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c,
20128PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d,
20129PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e,
20130PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x0000002f,
20131PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030,
20132PERF_PAPC_SU_INPUT_PRIM = 0x00000031,
20133PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032,
20134PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033,
20135PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034,
20136PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035,
20137PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036,
20138PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037,
20139PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038,
20140PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039,
20141PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a,
20142PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b,
20143PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c,
20144PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d,
20145PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e,
20146PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f,
20147PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040,
20148PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041,
20149PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042,
20150PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043,
20151PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044,
20152PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045,
20153PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046,
20154PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047,
20155PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048,
20156PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049,
20157PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a,
20158PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b,
20159PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c,
20160PERF_PAPC_PASX_REQ_IDLE = 0x0000004d,
20161PERF_PAPC_PASX_REQ_BUSY = 0x0000004e,
20162PERF_PAPC_PASX_REQ_STALLED = 0x0000004f,
20163PERF_PAPC_PASX_REC_IDLE = 0x00000050,
20164PERF_PAPC_PASX_REC_BUSY = 0x00000051,
20165PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052,
20166PERF_PAPC_PASX_REC_STALLED = 0x00000053,
20167PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054,
20168PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055,
20169PERF_PAPC_CCGSM_IDLE = 0x00000056,
20170PERF_PAPC_CCGSM_BUSY = 0x00000057,
20171PERF_PAPC_CCGSM_STALLED = 0x00000058,
20172PERF_PAPC_CLPRIM_IDLE = 0x00000059,
20173PERF_PAPC_CLPRIM_BUSY = 0x0000005a,
20174PERF_PAPC_CLPRIM_STALLED = 0x0000005b,
20175PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c,
20176PERF_PAPC_CLIPSM_IDLE = 0x0000005d,
20177PERF_PAPC_CLIPSM_BUSY = 0x0000005e,
20178PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f,
20179PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060,
20180PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061,
20181PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062,
20182PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063,
20183PERF_PAPC_CLIPGA_IDLE = 0x00000064,
20184PERF_PAPC_CLIPGA_BUSY = 0x00000065,
20185PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066,
20186PERF_PAPC_CLIPGA_STALLED = 0x00000067,
20187PERF_PAPC_CLIP_IDLE = 0x00000068,
20188PERF_PAPC_CLIP_BUSY = 0x00000069,
20189PERF_PAPC_SU_IDLE = 0x0000006a,
20190PERF_PAPC_SU_BUSY = 0x0000006b,
20191PERF_PAPC_SU_STARVED_CLIP = 0x0000006c,
20192PERF_PAPC_SU_STALLED_SC = 0x0000006d,
20193PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e,
20194PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f,
20195PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070,
20196PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x00000071,
20197PERF_PAPC_PASX_SE0_REQ = 0x00000072,
20198PERF_PAPC_PASX_SE1_REQ = 0x00000073,
20199PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x00000074,
20200PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x00000075,
20201PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x00000076,
20202PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x00000077,
20203PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078,
20204PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079,
20205PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x0000007a,
20206PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b,
20207PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c,
20208PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x0000007d,
20209PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e,
20210PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f,
20211PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x00000080,
20212PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x00000081,
20213PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x00000082,
20214PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083,
20215PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084,
20216PERF_PAPC_SU_SE01_STALLED_SC = 0x00000085,
20217PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086,
20218PERF_PAPC_SU_CULLED_PRIM = 0x00000087,
20219PERF_PAPC_SU_OUTPUT_EOPG = 0x00000088,
20220PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x00000089,
20221PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x0000008a,
20222PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x0000008b,
20223PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x0000008c,
20224PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x0000008d,
20225PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x0000008e,
20226PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x0000008f,
20227PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x00000090,
20228PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x00000091,
20229PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x00000092,
20230PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x00000093,
20231PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x00000094,
20232PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x00000095,
20233PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x00000096,
20234PERF_PAPC_SU_SE2_STALLED_SC = 0x00000097,
20235PERF_PAPC_SU_SE3_STALLED_SC = 0x00000098,
20236PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 0x00000099,
20237PERF_SMALL_PRIM_CULL_PRIM_1X1 = 0x0000009a,
20238PERF_SMALL_PRIM_CULL_PRIM_2X1 = 0x0000009b,
20239PERF_SMALL_PRIM_CULL_PRIM_1X2 = 0x0000009c,
20240PERF_SMALL_PRIM_CULL_PRIM_2X2 = 0x0000009d,
20241PERF_SMALL_PRIM_CULL_PRIM_3X1 = 0x0000009e,
20242PERF_SMALL_PRIM_CULL_PRIM_1X3 = 0x0000009f,
20243PERF_SMALL_PRIM_CULL_PRIM_3X2 = 0x000000a0,
20244PERF_SMALL_PRIM_CULL_PRIM_2X3 = 0x000000a1,
20245PERF_SMALL_PRIM_CULL_PRIM_NX1 = 0x000000a2,
20246PERF_SMALL_PRIM_CULL_PRIM_1XN = 0x000000a3,
20247PERF_SMALL_PRIM_CULL_PRIM_NX2 = 0x000000a4,
20248PERF_SMALL_PRIM_CULL_PRIM_2XN = 0x000000a5,
20249PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 0x000000a6,
20250PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 0x000000a7,
20251PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 0x000000a8,
20252PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 0x000000aa,
20253PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ab,
20254PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 0x000000ac,
20255PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ad,
20256PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 0x000000ae,
20257PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000af,
20258PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 0x000000b0,
20259PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000b1,
20260PERF_PA_VERTEX_FIFO_FULL = 0x000000b3,
20261PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 0x000000b4,
20262PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 0x000000b6,
20263PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 0x000000b7,
20264PERF_PA_PIPE0_SWITCHED_GEN = 0x000000b9,
20265PERF_PA_PIPE1_SWITCHED_GEN = 0x000000ba,
20266PERF_ENGG_CSB_MACHINE_IS_STARVED = 0x000000bc,
20267PERF_ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 0x000000bd,
20268PERF_ENGG_CSB_MACHINE_STALLED_BY_SPI = 0x000000be,
20269PERF_ENGG_CSB_GE_INPUT_FIFO_FULL = 0x000000bf,
20270PERF_ENGG_CSB_SPI_INPUT_FIFO_FULL = 0x000000c0,
20271PERF_ENGG_CSB_PAYLOAD_INPUT_FIFO_FULL = 0x000000c1,
20272PERF_ENGG_CSB_GE_INPUT_FIFO_POP_BIT = 0x000000c2,
20273PERF_ENGG_CSB_PRIM_COUNT_EQ0 = 0x000000c3,
20274PERF_ENGG_CSB_NULL_SUBGROUP = 0x000000c4,
20275PERF_ENGG_CSB_GE_SENDING_SUBGROUP = 0x000000c5,
20276PERF_ENGG_CSB_GE_MEMORY_FULL = 0x000000c6,
20277PERF_ENGG_CSB_GE_MEMORY_EMPTY = 0x000000c7,
20278PERF_ENGG_CSB_SPI_MEMORY_FULL = 0x000000c8,
20279PERF_ENGG_CSB_SPI_MEMORY_EMPTY = 0x000000c9,
20280PERF_ENGG_CSB_DELAY_BIN00 = 0x000000ca,
20281PERF_ENGG_CSB_DELAY_BIN01 = 0x000000cb,
20282PERF_ENGG_CSB_DELAY_BIN02 = 0x000000cc,
20283PERF_ENGG_CSB_DELAY_BIN03 = 0x000000cd,
20284PERF_ENGG_CSB_DELAY_BIN04 = 0x000000ce,
20285PERF_ENGG_CSB_DELAY_BIN05 = 0x000000cf,
20286PERF_ENGG_CSB_DELAY_BIN06 = 0x000000d0,
20287PERF_ENGG_CSB_DELAY_BIN07 = 0x000000d1,
20288PERF_ENGG_CSB_DELAY_BIN08 = 0x000000d2,
20289PERF_ENGG_CSB_DELAY_BIN09 = 0x000000d3,
20290PERF_ENGG_CSB_DELAY_BIN10 = 0x000000d4,
20291PERF_ENGG_CSB_DELAY_BIN11 = 0x000000d5,
20292PERF_ENGG_CSB_DELAY_BIN12 = 0x000000d6,
20293PERF_ENGG_CSB_DELAY_BIN13 = 0x000000d7,
20294PERF_ENGG_CSB_DELAY_BIN14 = 0x000000d8,
20295PERF_ENGG_CSB_DELAY_BIN15 = 0x000000d9,
20296PERF_ENGG_CSB_SPI_DELAY_BIN00 = 0x000000da,
20297PERF_ENGG_CSB_SPI_DELAY_BIN01 = 0x000000db,
20298PERF_ENGG_CSB_SPI_DELAY_BIN02 = 0x000000dc,
20299PERF_ENGG_CSB_SPI_DELAY_BIN03 = 0x000000dd,
20300PERF_ENGG_CSB_SPI_DELAY_BIN04 = 0x000000de,
20301PERF_ENGG_CSB_SPI_DELAY_BIN05 = 0x000000df,
20302PERF_ENGG_CSB_SPI_DELAY_BIN06 = 0x000000e0,
20303PERF_ENGG_CSB_SPI_DELAY_BIN07 = 0x000000e1,
20304PERF_ENGG_CSB_SPI_DELAY_BIN08 = 0x000000e2,
20305PERF_ENGG_CSB_SPI_DELAY_BIN09 = 0x000000e3,
20306PERF_ENGG_CSB_SPI_DELAY_BIN10 = 0x000000e4,
20307PERF_ENGG_INDEX_REQ_NULL_REQUEST = 0x000000e5,
20308PERF_ENGG_INDEX_REQ_0_NEW_VERTS_THIS_PRIM = 0x000000e6,
20309PERF_ENGG_INDEX_REQ_1_NEW_VERTS_THIS_PRIM = 0x000000e7,
20310PERF_ENGG_INDEX_REQ_2_NEW_VERTS_THIS_PRIM = 0x000000e8,
20311PERF_ENGG_INDEX_REQ_3_NEW_VERTS_THIS_PRIM = 0x000000e9,
20312PERF_ENGG_INDEX_REQ_STARVED = 0x000000ea,
20313PERF_ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x000000eb,
20314PERF_ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x000000ec,
20315PERF_ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 0x000000ed,
20316PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 0x000000ee,
20317PERF_ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 0x000000ef,
20318PERF_ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 0x000000f0,
20319PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 0x000000f1,
20320PERF_ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 0x000000f2,
20321PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 0x000000f3,
20322PERF_ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 0x000000f4,
20323PERF_ENGG_INDEX_RET_SXRX_READING_EVENT = 0x000000f5,
20324PERF_ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 0x000000f6,
20325PERF_ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 0x000000f7,
20326PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 0x000000f8,
20327PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 0x000000f9,
20328PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_NOPL = 0x000000fa,
20329PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_NOPL = 0x000000fb,
20330PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_NOPL = 0x000000fc,
20331PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 0x000000fd,
20332PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 0x000000fe,
20333PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS_PL = 0x000000ff,
20334PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS_PL = 0x00000100,
20335PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS_PL = 0x00000101,
20336PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_0_NULL_PRIMS = 0x00000102,
20337PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_1_NULL_PRIMS = 0x00000103,
20338PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_2_NULL_PRIMS = 0x00000104,
20339PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_3_NULL_PRIMS = 0x00000105,
20340PERF_ENGG_INDEX_RET_SXRX_READING_QDWORD_4_NULL_PRIMS = 0x00000106,
20341PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 0x00000107,
20342PERF_ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 0x00000108,
20343PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_CSB = 0x00000109,
20344PERF_ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 0x0000010a,
20345PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 0x0000010b,
20346PERF_ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 0x0000010c,
20347PERF_ENGG_POS_REQ_STARVED = 0x0000010d,
20348PERF_ENGG_INDEX_RET_SXRX_NULL_DROPPER_STALLED_BY_FULL_PRIM_FIFO = 0x0000010e,
20349PERF_ENGG_BUSY = 0x0000010f,
20350PERF_CLIPSM_CULL_PRIMS_CNT = 0x00000110,
20351PERF_PH_SEND_1_SC = 0x00000111,
20352PERF_PH_SEND_2_SC = 0x00000112,
20353PERF_PH_SEND_3_SC = 0x00000113,
20354PERF_PH_SEND_4_SC = 0x00000114,
20355PERF_OUTPUT_PRIM_1_SC = 0x00000115,
20356PERF_OUTPUT_PRIM_2_SC = 0x00000116,
20357PERF_OUTPUT_PRIM_3_SC = 0x00000117,
20358PERF_OUTPUT_PRIM_4_SC = 0x00000118,
20359} SU_PERFCNT_SEL;
20360
20361/*******************************************************
20362 * PH Enums
20363 *******************************************************/
20364
20365/*
20366 * PH_PERFCNT_SEL enum
20367 */
20368
20369typedef enum PH_PERFCNT_SEL {
20370PH_PERF_SEL_SC0_SRPS_WINDOW_VALID = 0x00000000,
20371PH_PERF_SEL_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000001,
20372PH_PERF_SEL_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 0x00000002,
20373PH_PERF_SEL_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x00000003,
20374PH_PERF_SEL_SC0_ARB_STALLED_FROM_BELOW = 0x00000004,
20375PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE = 0x00000005,
20376PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x00000006,
20377PH_PERF_SEL_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x00000007,
20378PH_PERF_SEL_SC0_ARB_BUSY = 0x00000008,
20379PH_PERF_SEL_SC0_ARB_PA_BUSY_SOP = 0x00000009,
20380PH_PERF_SEL_SC0_ARB_EOP_POP_SYNC_POP = 0x0000000a,
20381PH_PERF_SEL_SC0_ARB_EVENT_SYNC_POP = 0x0000000b,
20382PH_PERF_SEL_SC0_PS_ENG_MULTICYCLE_BUBBLE = 0x0000000c,
20383PH_PERF_SEL_SC0_EOP_SYNC_WINDOW = 0x0000000d,
20384PH_PERF_SEL_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x0000000e,
20385PH_PERF_SEL_SC0_BUSY_CNT_NOT_ZERO = 0x0000000f,
20386PH_PERF_SEL_SC0_SEND = 0x00000010,
20387PH_PERF_SEL_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000011,
20388PH_PERF_SEL_SC0_CREDIT_AT_MAX = 0x00000012,
20389PH_PERF_SEL_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000013,
20390PH_PERF_SEL_SC0_GFX_PIPE0_TO_1_TRANSITION = 0x00000014,
20391PH_PERF_SEL_SC0_GFX_PIPE1_TO_0_TRANSITION = 0x00000015,
20392PH_PERF_SEL_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 0x00000016,
20393PH_PERF_SEL_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000017,
20394PH_PERF_SEL_SC0_PA0_DATA_FIFO_RD = 0x00000018,
20395PH_PERF_SEL_SC0_PA0_DATA_FIFO_WE = 0x00000019,
20396PH_PERF_SEL_SC0_PA0_FIFO_EMPTY = 0x0000001a,
20397PH_PERF_SEL_SC0_PA0_FIFO_FULL = 0x0000001b,
20398PH_PERF_SEL_SC0_PA0_NULL_WE = 0x0000001c,
20399PH_PERF_SEL_SC0_PA0_EVENT_WE = 0x0000001d,
20400PH_PERF_SEL_SC0_PA0_FPOV_WE = 0x0000001e,
20401PH_PERF_SEL_SC0_PA0_LPOV_WE = 0x0000001f,
20402PH_PERF_SEL_SC0_PA0_EOP_WE = 0x00000020,
20403PH_PERF_SEL_SC0_PA0_DATA_FIFO_EOP_RD = 0x00000021,
20404PH_PERF_SEL_SC0_PA0_EOPG_WE = 0x00000022,
20405PH_PERF_SEL_SC0_PA0_DEALLOC_4_0_RD = 0x00000023,
20406PH_PERF_SEL_SC0_PA1_DATA_FIFO_RD = 0x00000024,
20407PH_PERF_SEL_SC0_PA1_DATA_FIFO_WE = 0x00000025,
20408PH_PERF_SEL_SC0_PA1_FIFO_EMPTY = 0x00000026,
20409PH_PERF_SEL_SC0_PA1_FIFO_FULL = 0x00000027,
20410PH_PERF_SEL_SC0_PA1_NULL_WE = 0x00000028,
20411PH_PERF_SEL_SC0_PA1_EVENT_WE = 0x00000029,
20412PH_PERF_SEL_SC0_PA1_FPOV_WE = 0x0000002a,
20413PH_PERF_SEL_SC0_PA1_LPOV_WE = 0x0000002b,
20414PH_PERF_SEL_SC0_PA1_EOP_WE = 0x0000002c,
20415PH_PERF_SEL_SC0_PA1_DATA_FIFO_EOP_RD = 0x0000002d,
20416PH_PERF_SEL_SC0_PA1_EOPG_WE = 0x0000002e,
20417PH_PERF_SEL_SC0_PA1_DEALLOC_4_0_RD = 0x0000002f,
20418PH_PERF_SEL_SC0_PA2_DATA_FIFO_RD = 0x00000030,
20419PH_PERF_SEL_SC0_PA2_DATA_FIFO_WE = 0x00000031,
20420PH_PERF_SEL_SC0_PA2_FIFO_EMPTY = 0x00000032,
20421PH_PERF_SEL_SC0_PA2_FIFO_FULL = 0x00000033,
20422PH_PERF_SEL_SC0_PA2_NULL_WE = 0x00000034,
20423PH_PERF_SEL_SC0_PA2_EVENT_WE = 0x00000035,
20424PH_PERF_SEL_SC0_PA2_FPOV_WE = 0x00000036,
20425PH_PERF_SEL_SC0_PA2_LPOV_WE = 0x00000037,
20426PH_PERF_SEL_SC0_PA2_EOP_WE = 0x00000038,
20427PH_PERF_SEL_SC0_PA2_DATA_FIFO_EOP_RD = 0x00000039,
20428PH_PERF_SEL_SC0_PA2_EOPG_WE = 0x0000003a,
20429PH_PERF_SEL_SC0_PA2_DEALLOC_4_0_RD = 0x0000003b,
20430PH_PERF_SEL_SC0_PA3_DATA_FIFO_RD = 0x0000003c,
20431PH_PERF_SEL_SC0_PA3_DATA_FIFO_WE = 0x0000003d,
20432PH_PERF_SEL_SC0_PA3_FIFO_EMPTY = 0x0000003e,
20433PH_PERF_SEL_SC0_PA3_FIFO_FULL = 0x0000003f,
20434PH_PERF_SEL_SC0_PA3_NULL_WE = 0x00000040,
20435PH_PERF_SEL_SC0_PA3_EVENT_WE = 0x00000041,
20436PH_PERF_SEL_SC0_PA3_FPOV_WE = 0x00000042,
20437PH_PERF_SEL_SC0_PA3_LPOV_WE = 0x00000043,
20438PH_PERF_SEL_SC0_PA3_EOP_WE = 0x00000044,
20439PH_PERF_SEL_SC0_PA3_DATA_FIFO_EOP_RD = 0x00000045,
20440PH_PERF_SEL_SC0_PA3_EOPG_WE = 0x00000046,
20441PH_PERF_SEL_SC0_PA3_DEALLOC_4_0_RD = 0x00000047,
20442PH_PERF_SEL_SC0_PA4_DATA_FIFO_RD = 0x00000048,
20443PH_PERF_SEL_SC0_PA4_DATA_FIFO_WE = 0x00000049,
20444PH_PERF_SEL_SC0_PA4_FIFO_EMPTY = 0x0000004a,
20445PH_PERF_SEL_SC0_PA4_FIFO_FULL = 0x0000004b,
20446PH_PERF_SEL_SC0_PA4_NULL_WE = 0x0000004c,
20447PH_PERF_SEL_SC0_PA4_EVENT_WE = 0x0000004d,
20448PH_PERF_SEL_SC0_PA4_FPOV_WE = 0x0000004e,
20449PH_PERF_SEL_SC0_PA4_LPOV_WE = 0x0000004f,
20450PH_PERF_SEL_SC0_PA4_EOP_WE = 0x00000050,
20451PH_PERF_SEL_SC0_PA4_DATA_FIFO_EOP_RD = 0x00000051,
20452PH_PERF_SEL_SC0_PA4_EOPG_WE = 0x00000052,
20453PH_PERF_SEL_SC0_PA4_DEALLOC_4_0_RD = 0x00000053,
20454PH_PERF_SEL_SC0_PA5_DATA_FIFO_RD = 0x00000054,
20455PH_PERF_SEL_SC0_PA5_DATA_FIFO_WE = 0x00000055,
20456PH_PERF_SEL_SC0_PA5_FIFO_EMPTY = 0x00000056,
20457PH_PERF_SEL_SC0_PA5_FIFO_FULL = 0x00000057,
20458PH_PERF_SEL_SC0_PA5_NULL_WE = 0x00000058,
20459PH_PERF_SEL_SC0_PA5_EVENT_WE = 0x00000059,
20460PH_PERF_SEL_SC0_PA5_FPOV_WE = 0x0000005a,
20461PH_PERF_SEL_SC0_PA5_LPOV_WE = 0x0000005b,
20462PH_PERF_SEL_SC0_PA5_EOP_WE = 0x0000005c,
20463PH_PERF_SEL_SC0_PA5_DATA_FIFO_EOP_RD = 0x0000005d,
20464PH_PERF_SEL_SC0_PA5_EOPG_WE = 0x0000005e,
20465PH_PERF_SEL_SC0_PA5_DEALLOC_4_0_RD = 0x0000005f,
20466PH_PERF_SEL_SC0_PA6_DATA_FIFO_RD = 0x00000060,
20467PH_PERF_SEL_SC0_PA6_DATA_FIFO_WE = 0x00000061,
20468PH_PERF_SEL_SC0_PA6_FIFO_EMPTY = 0x00000062,
20469PH_PERF_SEL_SC0_PA6_FIFO_FULL = 0x00000063,
20470PH_PERF_SEL_SC0_PA6_NULL_WE = 0x00000064,
20471PH_PERF_SEL_SC0_PA6_EVENT_WE = 0x00000065,
20472PH_PERF_SEL_SC0_PA6_FPOV_WE = 0x00000066,
20473PH_PERF_SEL_SC0_PA6_LPOV_WE = 0x00000067,
20474PH_PERF_SEL_SC0_PA6_EOP_WE = 0x00000068,
20475PH_PERF_SEL_SC0_PA6_DATA_FIFO_EOP_RD = 0x00000069,
20476PH_PERF_SEL_SC0_PA6_EOPG_WE = 0x0000006a,
20477PH_PERF_SEL_SC0_PA6_DEALLOC_4_0_RD = 0x0000006b,
20478PH_PERF_SEL_SC0_PA7_DATA_FIFO_RD = 0x0000006c,
20479PH_PERF_SEL_SC0_PA7_DATA_FIFO_WE = 0x0000006d,
20480PH_PERF_SEL_SC0_PA7_FIFO_EMPTY = 0x0000006e,
20481PH_PERF_SEL_SC0_PA7_FIFO_FULL = 0x0000006f,
20482PH_PERF_SEL_SC0_PA7_NULL_WE = 0x00000070,
20483PH_PERF_SEL_SC0_PA7_EVENT_WE = 0x00000071,
20484PH_PERF_SEL_SC0_PA7_FPOV_WE = 0x00000072,
20485PH_PERF_SEL_SC0_PA7_LPOV_WE = 0x00000073,
20486PH_PERF_SEL_SC0_PA7_EOP_WE = 0x00000074,
20487PH_PERF_SEL_SC0_PA7_DATA_FIFO_EOP_RD = 0x00000075,
20488PH_PERF_SEL_SC0_PA7_EOPG_WE = 0x00000076,
20489PH_PERF_SEL_SC0_PA7_DEALLOC_4_0_RD = 0x00000077,
20490PH_PERF_SEL_SC1_SRPS_WINDOW_VALID = 0x00000078,
20491PH_PERF_SEL_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000079,
20492PH_PERF_SEL_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000007a,
20493PH_PERF_SEL_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000007b,
20494PH_PERF_SEL_SC1_ARB_STALLED_FROM_BELOW = 0x0000007c,
20495PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE = 0x0000007d,
20496PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000007e,
20497PH_PERF_SEL_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000007f,
20498PH_PERF_SEL_SC1_ARB_BUSY = 0x00000080,
20499PH_PERF_SEL_SC1_ARB_PA_BUSY_SOP = 0x00000081,
20500PH_PERF_SEL_SC1_ARB_EOP_POP_SYNC_POP = 0x00000082,
20501PH_PERF_SEL_SC1_ARB_EVENT_SYNC_POP = 0x00000083,
20502PH_PERF_SEL_SC1_PS_ENG_MULTICYCLE_BUBBLE = 0x00000084,
20503PH_PERF_SEL_SC1_EOP_SYNC_WINDOW = 0x00000085,
20504PH_PERF_SEL_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000086,
20505PH_PERF_SEL_SC1_BUSY_CNT_NOT_ZERO = 0x00000087,
20506PH_PERF_SEL_SC1_SEND = 0x00000088,
20507PH_PERF_SEL_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000089,
20508PH_PERF_SEL_SC1_CREDIT_AT_MAX = 0x0000008a,
20509PH_PERF_SEL_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000008b,
20510PH_PERF_SEL_SC1_GFX_PIPE0_TO_1_TRANSITION = 0x0000008c,
20511PH_PERF_SEL_SC1_GFX_PIPE1_TO_0_TRANSITION = 0x0000008d,
20512PH_PERF_SEL_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000008e,
20513PH_PERF_SEL_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000008f,
20514PH_PERF_SEL_SC1_PA0_DATA_FIFO_RD = 0x00000090,
20515PH_PERF_SEL_SC1_PA0_DATA_FIFO_WE = 0x00000091,
20516PH_PERF_SEL_SC1_PA0_FIFO_EMPTY = 0x00000092,
20517PH_PERF_SEL_SC1_PA0_FIFO_FULL = 0x00000093,
20518PH_PERF_SEL_SC1_PA0_NULL_WE = 0x00000094,
20519PH_PERF_SEL_SC1_PA0_EVENT_WE = 0x00000095,
20520PH_PERF_SEL_SC1_PA0_FPOV_WE = 0x00000096,
20521PH_PERF_SEL_SC1_PA0_LPOV_WE = 0x00000097,
20522PH_PERF_SEL_SC1_PA0_EOP_WE = 0x00000098,
20523PH_PERF_SEL_SC1_PA0_DATA_FIFO_EOP_RD = 0x00000099,
20524PH_PERF_SEL_SC1_PA0_EOPG_WE = 0x0000009a,
20525PH_PERF_SEL_SC1_PA0_DEALLOC_4_0_RD = 0x0000009b,
20526PH_PERF_SEL_SC1_PA1_DATA_FIFO_RD = 0x0000009c,
20527PH_PERF_SEL_SC1_PA1_DATA_FIFO_WE = 0x0000009d,
20528PH_PERF_SEL_SC1_PA1_FIFO_EMPTY = 0x0000009e,
20529PH_PERF_SEL_SC1_PA1_FIFO_FULL = 0x0000009f,
20530PH_PERF_SEL_SC1_PA1_NULL_WE = 0x000000a0,
20531PH_PERF_SEL_SC1_PA1_EVENT_WE = 0x000000a1,
20532PH_PERF_SEL_SC1_PA1_FPOV_WE = 0x000000a2,
20533PH_PERF_SEL_SC1_PA1_LPOV_WE = 0x000000a3,
20534PH_PERF_SEL_SC1_PA1_EOP_WE = 0x000000a4,
20535PH_PERF_SEL_SC1_PA1_DATA_FIFO_EOP_RD = 0x000000a5,
20536PH_PERF_SEL_SC1_PA1_EOPG_WE = 0x000000a6,
20537PH_PERF_SEL_SC1_PA1_DEALLOC_4_0_RD = 0x000000a7,
20538PH_PERF_SEL_SC1_PA2_DATA_FIFO_RD = 0x000000a8,
20539PH_PERF_SEL_SC1_PA2_DATA_FIFO_WE = 0x000000a9,
20540PH_PERF_SEL_SC1_PA2_FIFO_EMPTY = 0x000000aa,
20541PH_PERF_SEL_SC1_PA2_FIFO_FULL = 0x000000ab,
20542PH_PERF_SEL_SC1_PA2_NULL_WE = 0x000000ac,
20543PH_PERF_SEL_SC1_PA2_EVENT_WE = 0x000000ad,
20544PH_PERF_SEL_SC1_PA2_FPOV_WE = 0x000000ae,
20545PH_PERF_SEL_SC1_PA2_LPOV_WE = 0x000000af,
20546PH_PERF_SEL_SC1_PA2_EOP_WE = 0x000000b0,
20547PH_PERF_SEL_SC1_PA2_DATA_FIFO_EOP_RD = 0x000000b1,
20548PH_PERF_SEL_SC1_PA2_EOPG_WE = 0x000000b2,
20549PH_PERF_SEL_SC1_PA2_DEALLOC_4_0_RD = 0x000000b3,
20550PH_PERF_SEL_SC1_PA3_DATA_FIFO_RD = 0x000000b4,
20551PH_PERF_SEL_SC1_PA3_DATA_FIFO_WE = 0x000000b5,
20552PH_PERF_SEL_SC1_PA3_FIFO_EMPTY = 0x000000b6,
20553PH_PERF_SEL_SC1_PA3_FIFO_FULL = 0x000000b7,
20554PH_PERF_SEL_SC1_PA3_NULL_WE = 0x000000b8,
20555PH_PERF_SEL_SC1_PA3_EVENT_WE = 0x000000b9,
20556PH_PERF_SEL_SC1_PA3_FPOV_WE = 0x000000ba,
20557PH_PERF_SEL_SC1_PA3_LPOV_WE = 0x000000bb,
20558PH_PERF_SEL_SC1_PA3_EOP_WE = 0x000000bc,
20559PH_PERF_SEL_SC1_PA3_DATA_FIFO_EOP_RD = 0x000000bd,
20560PH_PERF_SEL_SC1_PA3_EOPG_WE = 0x000000be,
20561PH_PERF_SEL_SC1_PA3_DEALLOC_4_0_RD = 0x000000bf,
20562PH_PERF_SEL_SC1_PA4_DATA_FIFO_RD = 0x000000c0,
20563PH_PERF_SEL_SC1_PA4_DATA_FIFO_WE = 0x000000c1,
20564PH_PERF_SEL_SC1_PA4_FIFO_EMPTY = 0x000000c2,
20565PH_PERF_SEL_SC1_PA4_FIFO_FULL = 0x000000c3,
20566PH_PERF_SEL_SC1_PA4_NULL_WE = 0x000000c4,
20567PH_PERF_SEL_SC1_PA4_EVENT_WE = 0x000000c5,
20568PH_PERF_SEL_SC1_PA4_FPOV_WE = 0x000000c6,
20569PH_PERF_SEL_SC1_PA4_LPOV_WE = 0x000000c7,
20570PH_PERF_SEL_SC1_PA4_EOP_WE = 0x000000c8,
20571PH_PERF_SEL_SC1_PA4_DATA_FIFO_EOP_RD = 0x000000c9,
20572PH_PERF_SEL_SC1_PA4_EOPG_WE = 0x000000ca,
20573PH_PERF_SEL_SC1_PA4_DEALLOC_4_0_RD = 0x000000cb,
20574PH_PERF_SEL_SC1_PA5_DATA_FIFO_RD = 0x000000cc,
20575PH_PERF_SEL_SC1_PA5_DATA_FIFO_WE = 0x000000cd,
20576PH_PERF_SEL_SC1_PA5_FIFO_EMPTY = 0x000000ce,
20577PH_PERF_SEL_SC1_PA5_FIFO_FULL = 0x000000cf,
20578PH_PERF_SEL_SC1_PA5_NULL_WE = 0x000000d0,
20579PH_PERF_SEL_SC1_PA5_EVENT_WE = 0x000000d1,
20580PH_PERF_SEL_SC1_PA5_FPOV_WE = 0x000000d2,
20581PH_PERF_SEL_SC1_PA5_LPOV_WE = 0x000000d3,
20582PH_PERF_SEL_SC1_PA5_EOP_WE = 0x000000d4,
20583PH_PERF_SEL_SC1_PA5_DATA_FIFO_EOP_RD = 0x000000d5,
20584PH_PERF_SEL_SC1_PA5_EOPG_WE = 0x000000d6,
20585PH_PERF_SEL_SC1_PA5_DEALLOC_4_0_RD = 0x000000d7,
20586PH_PERF_SEL_SC1_PA6_DATA_FIFO_RD = 0x000000d8,
20587PH_PERF_SEL_SC1_PA6_DATA_FIFO_WE = 0x000000d9,
20588PH_PERF_SEL_SC1_PA6_FIFO_EMPTY = 0x000000da,
20589PH_PERF_SEL_SC1_PA6_FIFO_FULL = 0x000000db,
20590PH_PERF_SEL_SC1_PA6_NULL_WE = 0x000000dc,
20591PH_PERF_SEL_SC1_PA6_EVENT_WE = 0x000000dd,
20592PH_PERF_SEL_SC1_PA6_FPOV_WE = 0x000000de,
20593PH_PERF_SEL_SC1_PA6_LPOV_WE = 0x000000df,
20594PH_PERF_SEL_SC1_PA6_EOP_WE = 0x000000e0,
20595PH_PERF_SEL_SC1_PA6_DATA_FIFO_EOP_RD = 0x000000e1,
20596PH_PERF_SEL_SC1_PA6_EOPG_WE = 0x000000e2,
20597PH_PERF_SEL_SC1_PA6_DEALLOC_4_0_RD = 0x000000e3,
20598PH_PERF_SEL_SC1_PA7_DATA_FIFO_RD = 0x000000e4,
20599PH_PERF_SEL_SC1_PA7_DATA_FIFO_WE = 0x000000e5,
20600PH_PERF_SEL_SC1_PA7_FIFO_EMPTY = 0x000000e6,
20601PH_PERF_SEL_SC1_PA7_FIFO_FULL = 0x000000e7,
20602PH_PERF_SEL_SC1_PA7_NULL_WE = 0x000000e8,
20603PH_PERF_SEL_SC1_PA7_EVENT_WE = 0x000000e9,
20604PH_PERF_SEL_SC1_PA7_FPOV_WE = 0x000000ea,
20605PH_PERF_SEL_SC1_PA7_LPOV_WE = 0x000000eb,
20606PH_PERF_SEL_SC1_PA7_EOP_WE = 0x000000ec,
20607PH_PERF_SEL_SC1_PA7_DATA_FIFO_EOP_RD = 0x000000ed,
20608PH_PERF_SEL_SC1_PA7_EOPG_WE = 0x000000ee,
20609PH_PERF_SEL_SC1_PA7_DEALLOC_4_0_RD = 0x000000ef,
20610PH_PERF_SEL_SC2_SRPS_WINDOW_VALID = 0x000000f0,
20611PH_PERF_SEL_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000000f1,
20612PH_PERF_SEL_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 0x000000f2,
20613PH_PERF_SEL_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000000f3,
20614PH_PERF_SEL_SC2_ARB_STALLED_FROM_BELOW = 0x000000f4,
20615PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE = 0x000000f5,
20616PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000000f6,
20617PH_PERF_SEL_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000000f7,
20618PH_PERF_SEL_SC2_ARB_BUSY = 0x000000f8,
20619PH_PERF_SEL_SC2_ARB_PA_BUSY_SOP = 0x000000f9,
20620PH_PERF_SEL_SC2_ARB_EOP_POP_SYNC_POP = 0x000000fa,
20621PH_PERF_SEL_SC2_ARB_EVENT_SYNC_POP = 0x000000fb,
20622PH_PERF_SEL_SC2_PS_ENG_MULTICYCLE_BUBBLE = 0x000000fc,
20623PH_PERF_SEL_SC2_EOP_SYNC_WINDOW = 0x000000fd,
20624PH_PERF_SEL_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000000fe,
20625PH_PERF_SEL_SC2_BUSY_CNT_NOT_ZERO = 0x000000ff,
20626PH_PERF_SEL_SC2_SEND = 0x00000100,
20627PH_PERF_SEL_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000101,
20628PH_PERF_SEL_SC2_CREDIT_AT_MAX = 0x00000102,
20629PH_PERF_SEL_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000103,
20630PH_PERF_SEL_SC2_GFX_PIPE0_TO_1_TRANSITION = 0x00000104,
20631PH_PERF_SEL_SC2_GFX_PIPE1_TO_0_TRANSITION = 0x00000105,
20632PH_PERF_SEL_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x00000106,
20633PH_PERF_SEL_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000107,
20634PH_PERF_SEL_SC2_PA0_DATA_FIFO_RD = 0x00000108,
20635PH_PERF_SEL_SC2_PA0_DATA_FIFO_WE = 0x00000109,
20636PH_PERF_SEL_SC2_PA0_FIFO_EMPTY = 0x0000010a,
20637PH_PERF_SEL_SC2_PA0_FIFO_FULL = 0x0000010b,
20638PH_PERF_SEL_SC2_PA0_NULL_WE = 0x0000010c,
20639PH_PERF_SEL_SC2_PA0_EVENT_WE = 0x0000010d,
20640PH_PERF_SEL_SC2_PA0_FPOV_WE = 0x0000010e,
20641PH_PERF_SEL_SC2_PA0_LPOV_WE = 0x0000010f,
20642PH_PERF_SEL_SC2_PA0_EOP_WE = 0x00000110,
20643PH_PERF_SEL_SC2_PA0_DATA_FIFO_EOP_RD = 0x00000111,
20644PH_PERF_SEL_SC2_PA0_EOPG_WE = 0x00000112,
20645PH_PERF_SEL_SC2_PA0_DEALLOC_4_0_RD = 0x00000113,
20646PH_PERF_SEL_SC2_PA1_DATA_FIFO_RD = 0x00000114,
20647PH_PERF_SEL_SC2_PA1_DATA_FIFO_WE = 0x00000115,
20648PH_PERF_SEL_SC2_PA1_FIFO_EMPTY = 0x00000116,
20649PH_PERF_SEL_SC2_PA1_FIFO_FULL = 0x00000117,
20650PH_PERF_SEL_SC2_PA1_NULL_WE = 0x00000118,
20651PH_PERF_SEL_SC2_PA1_EVENT_WE = 0x00000119,
20652PH_PERF_SEL_SC2_PA1_FPOV_WE = 0x0000011a,
20653PH_PERF_SEL_SC2_PA1_LPOV_WE = 0x0000011b,
20654PH_PERF_SEL_SC2_PA1_EOP_WE = 0x0000011c,
20655PH_PERF_SEL_SC2_PA1_DATA_FIFO_EOP_RD = 0x0000011d,
20656PH_PERF_SEL_SC2_PA1_EOPG_WE = 0x0000011e,
20657PH_PERF_SEL_SC2_PA1_DEALLOC_4_0_RD = 0x0000011f,
20658PH_PERF_SEL_SC2_PA2_DATA_FIFO_RD = 0x00000120,
20659PH_PERF_SEL_SC2_PA2_DATA_FIFO_WE = 0x00000121,
20660PH_PERF_SEL_SC2_PA2_FIFO_EMPTY = 0x00000122,
20661PH_PERF_SEL_SC2_PA2_FIFO_FULL = 0x00000123,
20662PH_PERF_SEL_SC2_PA2_NULL_WE = 0x00000124,
20663PH_PERF_SEL_SC2_PA2_EVENT_WE = 0x00000125,
20664PH_PERF_SEL_SC2_PA2_FPOV_WE = 0x00000126,
20665PH_PERF_SEL_SC2_PA2_LPOV_WE = 0x00000127,
20666PH_PERF_SEL_SC2_PA2_EOP_WE = 0x00000128,
20667PH_PERF_SEL_SC2_PA2_DATA_FIFO_EOP_RD = 0x00000129,
20668PH_PERF_SEL_SC2_PA2_EOPG_WE = 0x0000012a,
20669PH_PERF_SEL_SC2_PA2_DEALLOC_4_0_RD = 0x0000012b,
20670PH_PERF_SEL_SC2_PA3_DATA_FIFO_RD = 0x0000012c,
20671PH_PERF_SEL_SC2_PA3_DATA_FIFO_WE = 0x0000012d,
20672PH_PERF_SEL_SC2_PA3_FIFO_EMPTY = 0x0000012e,
20673PH_PERF_SEL_SC2_PA3_FIFO_FULL = 0x0000012f,
20674PH_PERF_SEL_SC2_PA3_NULL_WE = 0x00000130,
20675PH_PERF_SEL_SC2_PA3_EVENT_WE = 0x00000131,
20676PH_PERF_SEL_SC2_PA3_FPOV_WE = 0x00000132,
20677PH_PERF_SEL_SC2_PA3_LPOV_WE = 0x00000133,
20678PH_PERF_SEL_SC2_PA3_EOP_WE = 0x00000134,
20679PH_PERF_SEL_SC2_PA3_DATA_FIFO_EOP_RD = 0x00000135,
20680PH_PERF_SEL_SC2_PA3_EOPG_WE = 0x00000136,
20681PH_PERF_SEL_SC2_PA3_DEALLOC_4_0_RD = 0x00000137,
20682PH_PERF_SEL_SC2_PA4_DATA_FIFO_RD = 0x00000138,
20683PH_PERF_SEL_SC2_PA4_DATA_FIFO_WE = 0x00000139,
20684PH_PERF_SEL_SC2_PA4_FIFO_EMPTY = 0x0000013a,
20685PH_PERF_SEL_SC2_PA4_FIFO_FULL = 0x0000013b,
20686PH_PERF_SEL_SC2_PA4_NULL_WE = 0x0000013c,
20687PH_PERF_SEL_SC2_PA4_EVENT_WE = 0x0000013d,
20688PH_PERF_SEL_SC2_PA4_FPOV_WE = 0x0000013e,
20689PH_PERF_SEL_SC2_PA4_LPOV_WE = 0x0000013f,
20690PH_PERF_SEL_SC2_PA4_EOP_WE = 0x00000140,
20691PH_PERF_SEL_SC2_PA4_DATA_FIFO_EOP_RD = 0x00000141,
20692PH_PERF_SEL_SC2_PA4_EOPG_WE = 0x00000142,
20693PH_PERF_SEL_SC2_PA4_DEALLOC_4_0_RD = 0x00000143,
20694PH_PERF_SEL_SC2_PA5_DATA_FIFO_RD = 0x00000144,
20695PH_PERF_SEL_SC2_PA5_DATA_FIFO_WE = 0x00000145,
20696PH_PERF_SEL_SC2_PA5_FIFO_EMPTY = 0x00000146,
20697PH_PERF_SEL_SC2_PA5_FIFO_FULL = 0x00000147,
20698PH_PERF_SEL_SC2_PA5_NULL_WE = 0x00000148,
20699PH_PERF_SEL_SC2_PA5_EVENT_WE = 0x00000149,
20700PH_PERF_SEL_SC2_PA5_FPOV_WE = 0x0000014a,
20701PH_PERF_SEL_SC2_PA5_LPOV_WE = 0x0000014b,
20702PH_PERF_SEL_SC2_PA5_EOP_WE = 0x0000014c,
20703PH_PERF_SEL_SC2_PA5_DATA_FIFO_EOP_RD = 0x0000014d,
20704PH_PERF_SEL_SC2_PA5_EOPG_WE = 0x0000014e,
20705PH_PERF_SEL_SC2_PA5_DEALLOC_4_0_RD = 0x0000014f,
20706PH_PERF_SEL_SC2_PA6_DATA_FIFO_RD = 0x00000150,
20707PH_PERF_SEL_SC2_PA6_DATA_FIFO_WE = 0x00000151,
20708PH_PERF_SEL_SC2_PA6_FIFO_EMPTY = 0x00000152,
20709PH_PERF_SEL_SC2_PA6_FIFO_FULL = 0x00000153,
20710PH_PERF_SEL_SC2_PA6_NULL_WE = 0x00000154,
20711PH_PERF_SEL_SC2_PA6_EVENT_WE = 0x00000155,
20712PH_PERF_SEL_SC2_PA6_FPOV_WE = 0x00000156,
20713PH_PERF_SEL_SC2_PA6_LPOV_WE = 0x00000157,
20714PH_PERF_SEL_SC2_PA6_EOP_WE = 0x00000158,
20715PH_PERF_SEL_SC2_PA6_DATA_FIFO_EOP_RD = 0x00000159,
20716PH_PERF_SEL_SC2_PA6_EOPG_WE = 0x0000015a,
20717PH_PERF_SEL_SC2_PA6_DEALLOC_4_0_RD = 0x0000015b,
20718PH_PERF_SEL_SC2_PA7_DATA_FIFO_RD = 0x0000015c,
20719PH_PERF_SEL_SC2_PA7_DATA_FIFO_WE = 0x0000015d,
20720PH_PERF_SEL_SC2_PA7_FIFO_EMPTY = 0x0000015e,
20721PH_PERF_SEL_SC2_PA7_FIFO_FULL = 0x0000015f,
20722PH_PERF_SEL_SC2_PA7_NULL_WE = 0x00000160,
20723PH_PERF_SEL_SC2_PA7_EVENT_WE = 0x00000161,
20724PH_PERF_SEL_SC2_PA7_FPOV_WE = 0x00000162,
20725PH_PERF_SEL_SC2_PA7_LPOV_WE = 0x00000163,
20726PH_PERF_SEL_SC2_PA7_EOP_WE = 0x00000164,
20727PH_PERF_SEL_SC2_PA7_DATA_FIFO_EOP_RD = 0x00000165,
20728PH_PERF_SEL_SC2_PA7_EOPG_WE = 0x00000166,
20729PH_PERF_SEL_SC2_PA7_DEALLOC_4_0_RD = 0x00000167,
20730PH_PERF_SEL_SC3_SRPS_WINDOW_VALID = 0x00000168,
20731PH_PERF_SEL_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000169,
20732PH_PERF_SEL_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000016a,
20733PH_PERF_SEL_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000016b,
20734PH_PERF_SEL_SC3_ARB_STALLED_FROM_BELOW = 0x0000016c,
20735PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE = 0x0000016d,
20736PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000016e,
20737PH_PERF_SEL_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000016f,
20738PH_PERF_SEL_SC3_ARB_BUSY = 0x00000170,
20739PH_PERF_SEL_SC3_ARB_PA_BUSY_SOP = 0x00000171,
20740PH_PERF_SEL_SC3_ARB_EOP_POP_SYNC_POP = 0x00000172,
20741PH_PERF_SEL_SC3_ARB_EVENT_SYNC_POP = 0x00000173,
20742PH_PERF_SEL_SC3_PS_ENG_MULTICYCLE_BUBBLE = 0x00000174,
20743PH_PERF_SEL_SC3_EOP_SYNC_WINDOW = 0x00000175,
20744PH_PERF_SEL_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000176,
20745PH_PERF_SEL_SC3_BUSY_CNT_NOT_ZERO = 0x00000177,
20746PH_PERF_SEL_SC3_SEND = 0x00000178,
20747PH_PERF_SEL_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000179,
20748PH_PERF_SEL_SC3_CREDIT_AT_MAX = 0x0000017a,
20749PH_PERF_SEL_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000017b,
20750PH_PERF_SEL_SC3_GFX_PIPE0_TO_1_TRANSITION = 0x0000017c,
20751PH_PERF_SEL_SC3_GFX_PIPE1_TO_0_TRANSITION = 0x0000017d,
20752PH_PERF_SEL_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000017e,
20753PH_PERF_SEL_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000017f,
20754PH_PERF_SEL_SC3_PA0_DATA_FIFO_RD = 0x00000180,
20755PH_PERF_SEL_SC3_PA0_DATA_FIFO_WE = 0x00000181,
20756PH_PERF_SEL_SC3_PA0_FIFO_EMPTY = 0x00000182,
20757PH_PERF_SEL_SC3_PA0_FIFO_FULL = 0x00000183,
20758PH_PERF_SEL_SC3_PA0_NULL_WE = 0x00000184,
20759PH_PERF_SEL_SC3_PA0_EVENT_WE = 0x00000185,
20760PH_PERF_SEL_SC3_PA0_FPOV_WE = 0x00000186,
20761PH_PERF_SEL_SC3_PA0_LPOV_WE = 0x00000187,
20762PH_PERF_SEL_SC3_PA0_EOP_WE = 0x00000188,
20763PH_PERF_SEL_SC3_PA0_DATA_FIFO_EOP_RD = 0x00000189,
20764PH_PERF_SEL_SC3_PA0_EOPG_WE = 0x0000018a,
20765PH_PERF_SEL_SC3_PA0_DEALLOC_4_0_RD = 0x0000018b,
20766PH_PERF_SEL_SC3_PA1_DATA_FIFO_RD = 0x0000018c,
20767PH_PERF_SEL_SC3_PA1_DATA_FIFO_WE = 0x0000018d,
20768PH_PERF_SEL_SC3_PA1_FIFO_EMPTY = 0x0000018e,
20769PH_PERF_SEL_SC3_PA1_FIFO_FULL = 0x0000018f,
20770PH_PERF_SEL_SC3_PA1_NULL_WE = 0x00000190,
20771PH_PERF_SEL_SC3_PA1_EVENT_WE = 0x00000191,
20772PH_PERF_SEL_SC3_PA1_FPOV_WE = 0x00000192,
20773PH_PERF_SEL_SC3_PA1_LPOV_WE = 0x00000193,
20774PH_PERF_SEL_SC3_PA1_EOP_WE = 0x00000194,
20775PH_PERF_SEL_SC3_PA1_DATA_FIFO_EOP_RD = 0x00000195,
20776PH_PERF_SEL_SC3_PA1_EOPG_WE = 0x00000196,
20777PH_PERF_SEL_SC3_PA1_DEALLOC_4_0_RD = 0x00000197,
20778PH_PERF_SEL_SC3_PA2_DATA_FIFO_RD = 0x00000198,
20779PH_PERF_SEL_SC3_PA2_DATA_FIFO_WE = 0x00000199,
20780PH_PERF_SEL_SC3_PA2_FIFO_EMPTY = 0x0000019a,
20781PH_PERF_SEL_SC3_PA2_FIFO_FULL = 0x0000019b,
20782PH_PERF_SEL_SC3_PA2_NULL_WE = 0x0000019c,
20783PH_PERF_SEL_SC3_PA2_EVENT_WE = 0x0000019d,
20784PH_PERF_SEL_SC3_PA2_FPOV_WE = 0x0000019e,
20785PH_PERF_SEL_SC3_PA2_LPOV_WE = 0x0000019f,
20786PH_PERF_SEL_SC3_PA2_EOP_WE = 0x000001a0,
20787PH_PERF_SEL_SC3_PA2_DATA_FIFO_EOP_RD = 0x000001a1,
20788PH_PERF_SEL_SC3_PA2_EOPG_WE = 0x000001a2,
20789PH_PERF_SEL_SC3_PA2_DEALLOC_4_0_RD = 0x000001a3,
20790PH_PERF_SEL_SC3_PA3_DATA_FIFO_RD = 0x000001a4,
20791PH_PERF_SEL_SC3_PA3_DATA_FIFO_WE = 0x000001a5,
20792PH_PERF_SEL_SC3_PA3_FIFO_EMPTY = 0x000001a6,
20793PH_PERF_SEL_SC3_PA3_FIFO_FULL = 0x000001a7,
20794PH_PERF_SEL_SC3_PA3_NULL_WE = 0x000001a8,
20795PH_PERF_SEL_SC3_PA3_EVENT_WE = 0x000001a9,
20796PH_PERF_SEL_SC3_PA3_FPOV_WE = 0x000001aa,
20797PH_PERF_SEL_SC3_PA3_LPOV_WE = 0x000001ab,
20798PH_PERF_SEL_SC3_PA3_EOP_WE = 0x000001ac,
20799PH_PERF_SEL_SC3_PA3_DATA_FIFO_EOP_RD = 0x000001ad,
20800PH_PERF_SEL_SC3_PA3_EOPG_WE = 0x000001ae,
20801PH_PERF_SEL_SC3_PA3_DEALLOC_4_0_RD = 0x000001af,
20802PH_PERF_SEL_SC3_PA4_DATA_FIFO_RD = 0x000001b0,
20803PH_PERF_SEL_SC3_PA4_DATA_FIFO_WE = 0x000001b1,
20804PH_PERF_SEL_SC3_PA4_FIFO_EMPTY = 0x000001b2,
20805PH_PERF_SEL_SC3_PA4_FIFO_FULL = 0x000001b3,
20806PH_PERF_SEL_SC3_PA4_NULL_WE = 0x000001b4,
20807PH_PERF_SEL_SC3_PA4_EVENT_WE = 0x000001b5,
20808PH_PERF_SEL_SC3_PA4_FPOV_WE = 0x000001b6,
20809PH_PERF_SEL_SC3_PA4_LPOV_WE = 0x000001b7,
20810PH_PERF_SEL_SC3_PA4_EOP_WE = 0x000001b8,
20811PH_PERF_SEL_SC3_PA4_DATA_FIFO_EOP_RD = 0x000001b9,
20812PH_PERF_SEL_SC3_PA4_EOPG_WE = 0x000001ba,
20813PH_PERF_SEL_SC3_PA4_DEALLOC_4_0_RD = 0x000001bb,
20814PH_PERF_SEL_SC3_PA5_DATA_FIFO_RD = 0x000001bc,
20815PH_PERF_SEL_SC3_PA5_DATA_FIFO_WE = 0x000001bd,
20816PH_PERF_SEL_SC3_PA5_FIFO_EMPTY = 0x000001be,
20817PH_PERF_SEL_SC3_PA5_FIFO_FULL = 0x000001bf,
20818PH_PERF_SEL_SC3_PA5_NULL_WE = 0x000001c0,
20819PH_PERF_SEL_SC3_PA5_EVENT_WE = 0x000001c1,
20820PH_PERF_SEL_SC3_PA5_FPOV_WE = 0x000001c2,
20821PH_PERF_SEL_SC3_PA5_LPOV_WE = 0x000001c3,
20822PH_PERF_SEL_SC3_PA5_EOP_WE = 0x000001c4,
20823PH_PERF_SEL_SC3_PA5_DATA_FIFO_EOP_RD = 0x000001c5,
20824PH_PERF_SEL_SC3_PA5_EOPG_WE = 0x000001c6,
20825PH_PERF_SEL_SC3_PA5_DEALLOC_4_0_RD = 0x000001c7,
20826PH_PERF_SEL_SC3_PA6_DATA_FIFO_RD = 0x000001c8,
20827PH_PERF_SEL_SC3_PA6_DATA_FIFO_WE = 0x000001c9,
20828PH_PERF_SEL_SC3_PA6_FIFO_EMPTY = 0x000001ca,
20829PH_PERF_SEL_SC3_PA6_FIFO_FULL = 0x000001cb,
20830PH_PERF_SEL_SC3_PA6_NULL_WE = 0x000001cc,
20831PH_PERF_SEL_SC3_PA6_EVENT_WE = 0x000001cd,
20832PH_PERF_SEL_SC3_PA6_FPOV_WE = 0x000001ce,
20833PH_PERF_SEL_SC3_PA6_LPOV_WE = 0x000001cf,
20834PH_PERF_SEL_SC3_PA6_EOP_WE = 0x000001d0,
20835PH_PERF_SEL_SC3_PA6_DATA_FIFO_EOP_RD = 0x000001d1,
20836PH_PERF_SEL_SC3_PA6_EOPG_WE = 0x000001d2,
20837PH_PERF_SEL_SC3_PA6_DEALLOC_4_0_RD = 0x000001d3,
20838PH_PERF_SEL_SC3_PA7_DATA_FIFO_RD = 0x000001d4,
20839PH_PERF_SEL_SC3_PA7_DATA_FIFO_WE = 0x000001d5,
20840PH_PERF_SEL_SC3_PA7_FIFO_EMPTY = 0x000001d6,
20841PH_PERF_SEL_SC3_PA7_FIFO_FULL = 0x000001d7,
20842PH_PERF_SEL_SC3_PA7_NULL_WE = 0x000001d8,
20843PH_PERF_SEL_SC3_PA7_EVENT_WE = 0x000001d9,
20844PH_PERF_SEL_SC3_PA7_FPOV_WE = 0x000001da,
20845PH_PERF_SEL_SC3_PA7_LPOV_WE = 0x000001db,
20846PH_PERF_SEL_SC3_PA7_EOP_WE = 0x000001dc,
20847PH_PERF_SEL_SC3_PA7_DATA_FIFO_EOP_RD = 0x000001dd,
20848PH_PERF_SEL_SC3_PA7_EOPG_WE = 0x000001de,
20849PH_PERF_SEL_SC3_PA7_DEALLOC_4_0_RD = 0x000001df,
20850PH_PERF_SEL_SC4_SRPS_WINDOW_VALID = 0x000001e0,
20851PH_PERF_SEL_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000001e1,
20852PH_PERF_SEL_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 0x000001e2,
20853PH_PERF_SEL_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000001e3,
20854PH_PERF_SEL_SC4_ARB_STALLED_FROM_BELOW = 0x000001e4,
20855PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE = 0x000001e5,
20856PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000001e6,
20857PH_PERF_SEL_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000001e7,
20858PH_PERF_SEL_SC4_ARB_BUSY = 0x000001e8,
20859PH_PERF_SEL_SC4_ARB_PA_BUSY_SOP = 0x000001e9,
20860PH_PERF_SEL_SC4_ARB_EOP_POP_SYNC_POP = 0x000001ea,
20861PH_PERF_SEL_SC4_ARB_EVENT_SYNC_POP = 0x000001eb,
20862PH_PERF_SEL_SC4_PS_ENG_MULTICYCLE_BUBBLE = 0x000001ec,
20863PH_PERF_SEL_SC4_EOP_SYNC_WINDOW = 0x000001ed,
20864PH_PERF_SEL_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000001ee,
20865PH_PERF_SEL_SC4_BUSY_CNT_NOT_ZERO = 0x000001ef,
20866PH_PERF_SEL_SC4_SEND = 0x000001f0,
20867PH_PERF_SEL_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001f1,
20868PH_PERF_SEL_SC4_CREDIT_AT_MAX = 0x000001f2,
20869PH_PERF_SEL_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001f3,
20870PH_PERF_SEL_SC4_GFX_PIPE0_TO_1_TRANSITION = 0x000001f4,
20871PH_PERF_SEL_SC4_GFX_PIPE1_TO_0_TRANSITION = 0x000001f5,
20872PH_PERF_SEL_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000001f6,
20873PH_PERF_SEL_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000001f7,
20874PH_PERF_SEL_SC4_PA0_DATA_FIFO_RD = 0x000001f8,
20875PH_PERF_SEL_SC4_PA0_DATA_FIFO_WE = 0x000001f9,
20876PH_PERF_SEL_SC4_PA0_FIFO_EMPTY = 0x000001fa,
20877PH_PERF_SEL_SC4_PA0_FIFO_FULL = 0x000001fb,
20878PH_PERF_SEL_SC4_PA0_NULL_WE = 0x000001fc,
20879PH_PERF_SEL_SC4_PA0_EVENT_WE = 0x000001fd,
20880PH_PERF_SEL_SC4_PA0_FPOV_WE = 0x000001fe,
20881PH_PERF_SEL_SC4_PA0_LPOV_WE = 0x000001ff,
20882PH_PERF_SEL_SC4_PA0_EOP_WE = 0x00000200,
20883PH_PERF_SEL_SC4_PA0_DATA_FIFO_EOP_RD = 0x00000201,
20884PH_PERF_SEL_SC4_PA0_EOPG_WE = 0x00000202,
20885PH_PERF_SEL_SC4_PA0_DEALLOC_4_0_RD = 0x00000203,
20886PH_PERF_SEL_SC4_PA1_DATA_FIFO_RD = 0x00000204,
20887PH_PERF_SEL_SC4_PA1_DATA_FIFO_WE = 0x00000205,
20888PH_PERF_SEL_SC4_PA1_FIFO_EMPTY = 0x00000206,
20889PH_PERF_SEL_SC4_PA1_FIFO_FULL = 0x00000207,
20890PH_PERF_SEL_SC4_PA1_NULL_WE = 0x00000208,
20891PH_PERF_SEL_SC4_PA1_EVENT_WE = 0x00000209,
20892PH_PERF_SEL_SC4_PA1_FPOV_WE = 0x0000020a,
20893PH_PERF_SEL_SC4_PA1_LPOV_WE = 0x0000020b,
20894PH_PERF_SEL_SC4_PA1_EOP_WE = 0x0000020c,
20895PH_PERF_SEL_SC4_PA1_DATA_FIFO_EOP_RD = 0x0000020d,
20896PH_PERF_SEL_SC4_PA1_EOPG_WE = 0x0000020e,
20897PH_PERF_SEL_SC4_PA1_DEALLOC_4_0_RD = 0x0000020f,
20898PH_PERF_SEL_SC4_PA2_DATA_FIFO_RD = 0x00000210,
20899PH_PERF_SEL_SC4_PA2_DATA_FIFO_WE = 0x00000211,
20900PH_PERF_SEL_SC4_PA2_FIFO_EMPTY = 0x00000212,
20901PH_PERF_SEL_SC4_PA2_FIFO_FULL = 0x00000213,
20902PH_PERF_SEL_SC4_PA2_NULL_WE = 0x00000214,
20903PH_PERF_SEL_SC4_PA2_EVENT_WE = 0x00000215,
20904PH_PERF_SEL_SC4_PA2_FPOV_WE = 0x00000216,
20905PH_PERF_SEL_SC4_PA2_LPOV_WE = 0x00000217,
20906PH_PERF_SEL_SC4_PA2_EOP_WE = 0x00000218,
20907PH_PERF_SEL_SC4_PA2_DATA_FIFO_EOP_RD = 0x00000219,
20908PH_PERF_SEL_SC4_PA2_EOPG_WE = 0x0000021a,
20909PH_PERF_SEL_SC4_PA2_DEALLOC_4_0_RD = 0x0000021b,
20910PH_PERF_SEL_SC4_PA3_DATA_FIFO_RD = 0x0000021c,
20911PH_PERF_SEL_SC4_PA3_DATA_FIFO_WE = 0x0000021d,
20912PH_PERF_SEL_SC4_PA3_FIFO_EMPTY = 0x0000021e,
20913PH_PERF_SEL_SC4_PA3_FIFO_FULL = 0x0000021f,
20914PH_PERF_SEL_SC4_PA3_NULL_WE = 0x00000220,
20915PH_PERF_SEL_SC4_PA3_EVENT_WE = 0x00000221,
20916PH_PERF_SEL_SC4_PA3_FPOV_WE = 0x00000222,
20917PH_PERF_SEL_SC4_PA3_LPOV_WE = 0x00000223,
20918PH_PERF_SEL_SC4_PA3_EOP_WE = 0x00000224,
20919PH_PERF_SEL_SC4_PA3_DATA_FIFO_EOP_RD = 0x00000225,
20920PH_PERF_SEL_SC4_PA3_EOPG_WE = 0x00000226,
20921PH_PERF_SEL_SC4_PA3_DEALLOC_4_0_RD = 0x00000227,
20922PH_PERF_SEL_SC4_PA4_DATA_FIFO_RD = 0x00000228,
20923PH_PERF_SEL_SC4_PA4_DATA_FIFO_WE = 0x00000229,
20924PH_PERF_SEL_SC4_PA4_FIFO_EMPTY = 0x0000022a,
20925PH_PERF_SEL_SC4_PA4_FIFO_FULL = 0x0000022b,
20926PH_PERF_SEL_SC4_PA4_NULL_WE = 0x0000022c,
20927PH_PERF_SEL_SC4_PA4_EVENT_WE = 0x0000022d,
20928PH_PERF_SEL_SC4_PA4_FPOV_WE = 0x0000022e,
20929PH_PERF_SEL_SC4_PA4_LPOV_WE = 0x0000022f,
20930PH_PERF_SEL_SC4_PA4_EOP_WE = 0x00000230,
20931PH_PERF_SEL_SC4_PA4_DATA_FIFO_EOP_RD = 0x00000231,
20932PH_PERF_SEL_SC4_PA4_EOPG_WE = 0x00000232,
20933PH_PERF_SEL_SC4_PA4_DEALLOC_4_0_RD = 0x00000233,
20934PH_PERF_SEL_SC4_PA5_DATA_FIFO_RD = 0x00000234,
20935PH_PERF_SEL_SC4_PA5_DATA_FIFO_WE = 0x00000235,
20936PH_PERF_SEL_SC4_PA5_FIFO_EMPTY = 0x00000236,
20937PH_PERF_SEL_SC4_PA5_FIFO_FULL = 0x00000237,
20938PH_PERF_SEL_SC4_PA5_NULL_WE = 0x00000238,
20939PH_PERF_SEL_SC4_PA5_EVENT_WE = 0x00000239,
20940PH_PERF_SEL_SC4_PA5_FPOV_WE = 0x0000023a,
20941PH_PERF_SEL_SC4_PA5_LPOV_WE = 0x0000023b,
20942PH_PERF_SEL_SC4_PA5_EOP_WE = 0x0000023c,
20943PH_PERF_SEL_SC4_PA5_DATA_FIFO_EOP_RD = 0x0000023d,
20944PH_PERF_SEL_SC4_PA5_EOPG_WE = 0x0000023e,
20945PH_PERF_SEL_SC4_PA5_DEALLOC_4_0_RD = 0x0000023f,
20946PH_PERF_SEL_SC4_PA6_DATA_FIFO_RD = 0x00000240,
20947PH_PERF_SEL_SC4_PA6_DATA_FIFO_WE = 0x00000241,
20948PH_PERF_SEL_SC4_PA6_FIFO_EMPTY = 0x00000242,
20949PH_PERF_SEL_SC4_PA6_FIFO_FULL = 0x00000243,
20950PH_PERF_SEL_SC4_PA6_NULL_WE = 0x00000244,
20951PH_PERF_SEL_SC4_PA6_EVENT_WE = 0x00000245,
20952PH_PERF_SEL_SC4_PA6_FPOV_WE = 0x00000246,
20953PH_PERF_SEL_SC4_PA6_LPOV_WE = 0x00000247,
20954PH_PERF_SEL_SC4_PA6_EOP_WE = 0x00000248,
20955PH_PERF_SEL_SC4_PA6_DATA_FIFO_EOP_RD = 0x00000249,
20956PH_PERF_SEL_SC4_PA6_EOPG_WE = 0x0000024a,
20957PH_PERF_SEL_SC4_PA6_DEALLOC_4_0_RD = 0x0000024b,
20958PH_PERF_SEL_SC4_PA7_DATA_FIFO_RD = 0x0000024c,
20959PH_PERF_SEL_SC4_PA7_DATA_FIFO_WE = 0x0000024d,
20960PH_PERF_SEL_SC4_PA7_FIFO_EMPTY = 0x0000024e,
20961PH_PERF_SEL_SC4_PA7_FIFO_FULL = 0x0000024f,
20962PH_PERF_SEL_SC4_PA7_NULL_WE = 0x00000250,
20963PH_PERF_SEL_SC4_PA7_EVENT_WE = 0x00000251,
20964PH_PERF_SEL_SC4_PA7_FPOV_WE = 0x00000252,
20965PH_PERF_SEL_SC4_PA7_LPOV_WE = 0x00000253,
20966PH_PERF_SEL_SC4_PA7_EOP_WE = 0x00000254,
20967PH_PERF_SEL_SC4_PA7_DATA_FIFO_EOP_RD = 0x00000255,
20968PH_PERF_SEL_SC4_PA7_EOPG_WE = 0x00000256,
20969PH_PERF_SEL_SC4_PA7_DEALLOC_4_0_RD = 0x00000257,
20970PH_PERF_SEL_SC5_SRPS_WINDOW_VALID = 0x00000258,
20971PH_PERF_SEL_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000259,
20972PH_PERF_SEL_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000025a,
20973PH_PERF_SEL_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000025b,
20974PH_PERF_SEL_SC5_ARB_STALLED_FROM_BELOW = 0x0000025c,
20975PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE = 0x0000025d,
20976PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000025e,
20977PH_PERF_SEL_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000025f,
20978PH_PERF_SEL_SC5_ARB_BUSY = 0x00000260,
20979PH_PERF_SEL_SC5_ARB_PA_BUSY_SOP = 0x00000261,
20980PH_PERF_SEL_SC5_ARB_EOP_POP_SYNC_POP = 0x00000262,
20981PH_PERF_SEL_SC5_ARB_EVENT_SYNC_POP = 0x00000263,
20982PH_PERF_SEL_SC5_PS_ENG_MULTICYCLE_BUBBLE = 0x00000264,
20983PH_PERF_SEL_SC5_EOP_SYNC_WINDOW = 0x00000265,
20984PH_PERF_SEL_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000266,
20985PH_PERF_SEL_SC5_BUSY_CNT_NOT_ZERO = 0x00000267,
20986PH_PERF_SEL_SC5_SEND = 0x00000268,
20987PH_PERF_SEL_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000269,
20988PH_PERF_SEL_SC5_CREDIT_AT_MAX = 0x0000026a,
20989PH_PERF_SEL_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000026b,
20990PH_PERF_SEL_SC5_GFX_PIPE0_TO_1_TRANSITION = 0x0000026c,
20991PH_PERF_SEL_SC5_GFX_PIPE1_TO_0_TRANSITION = 0x0000026d,
20992PH_PERF_SEL_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000026e,
20993PH_PERF_SEL_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000026f,
20994PH_PERF_SEL_SC5_PA0_DATA_FIFO_RD = 0x00000270,
20995PH_PERF_SEL_SC5_PA0_DATA_FIFO_WE = 0x00000271,
20996PH_PERF_SEL_SC5_PA0_FIFO_EMPTY = 0x00000272,
20997PH_PERF_SEL_SC5_PA0_FIFO_FULL = 0x00000273,
20998PH_PERF_SEL_SC5_PA0_NULL_WE = 0x00000274,
20999PH_PERF_SEL_SC5_PA0_EVENT_WE = 0x00000275,
21000PH_PERF_SEL_SC5_PA0_FPOV_WE = 0x00000276,
21001PH_PERF_SEL_SC5_PA0_LPOV_WE = 0x00000277,
21002PH_PERF_SEL_SC5_PA0_EOP_WE = 0x00000278,
21003PH_PERF_SEL_SC5_PA0_DATA_FIFO_EOP_RD = 0x00000279,
21004PH_PERF_SEL_SC5_PA0_EOPG_WE = 0x0000027a,
21005PH_PERF_SEL_SC5_PA0_DEALLOC_4_0_RD = 0x0000027b,
21006PH_PERF_SEL_SC5_PA1_DATA_FIFO_RD = 0x0000027c,
21007PH_PERF_SEL_SC5_PA1_DATA_FIFO_WE = 0x0000027d,
21008PH_PERF_SEL_SC5_PA1_FIFO_EMPTY = 0x0000027e,
21009PH_PERF_SEL_SC5_PA1_FIFO_FULL = 0x0000027f,
21010PH_PERF_SEL_SC5_PA1_NULL_WE = 0x00000280,
21011PH_PERF_SEL_SC5_PA1_EVENT_WE = 0x00000281,
21012PH_PERF_SEL_SC5_PA1_FPOV_WE = 0x00000282,
21013PH_PERF_SEL_SC5_PA1_LPOV_WE = 0x00000283,
21014PH_PERF_SEL_SC5_PA1_EOP_WE = 0x00000284,
21015PH_PERF_SEL_SC5_PA1_DATA_FIFO_EOP_RD = 0x00000285,
21016PH_PERF_SEL_SC5_PA1_EOPG_WE = 0x00000286,
21017PH_PERF_SEL_SC5_PA1_DEALLOC_4_0_RD = 0x00000287,
21018PH_PERF_SEL_SC5_PA2_DATA_FIFO_RD = 0x00000288,
21019PH_PERF_SEL_SC5_PA2_DATA_FIFO_WE = 0x00000289,
21020PH_PERF_SEL_SC5_PA2_FIFO_EMPTY = 0x0000028a,
21021PH_PERF_SEL_SC5_PA2_FIFO_FULL = 0x0000028b,
21022PH_PERF_SEL_SC5_PA2_NULL_WE = 0x0000028c,
21023PH_PERF_SEL_SC5_PA2_EVENT_WE = 0x0000028d,
21024PH_PERF_SEL_SC5_PA2_FPOV_WE = 0x0000028e,
21025PH_PERF_SEL_SC5_PA2_LPOV_WE = 0x0000028f,
21026PH_PERF_SEL_SC5_PA2_EOP_WE = 0x00000290,
21027PH_PERF_SEL_SC5_PA2_DATA_FIFO_EOP_RD = 0x00000291,
21028PH_PERF_SEL_SC5_PA2_EOPG_WE = 0x00000292,
21029PH_PERF_SEL_SC5_PA2_DEALLOC_4_0_RD = 0x00000293,
21030PH_PERF_SEL_SC5_PA3_DATA_FIFO_RD = 0x00000294,
21031PH_PERF_SEL_SC5_PA3_DATA_FIFO_WE = 0x00000295,
21032PH_PERF_SEL_SC5_PA3_FIFO_EMPTY = 0x00000296,
21033PH_PERF_SEL_SC5_PA3_FIFO_FULL = 0x00000297,
21034PH_PERF_SEL_SC5_PA3_NULL_WE = 0x00000298,
21035PH_PERF_SEL_SC5_PA3_EVENT_WE = 0x00000299,
21036PH_PERF_SEL_SC5_PA3_FPOV_WE = 0x0000029a,
21037PH_PERF_SEL_SC5_PA3_LPOV_WE = 0x0000029b,
21038PH_PERF_SEL_SC5_PA3_EOP_WE = 0x0000029c,
21039PH_PERF_SEL_SC5_PA3_DATA_FIFO_EOP_RD = 0x0000029d,
21040PH_PERF_SEL_SC5_PA3_EOPG_WE = 0x0000029e,
21041PH_PERF_SEL_SC5_PA3_DEALLOC_4_0_RD = 0x0000029f,
21042PH_PERF_SEL_SC5_PA4_DATA_FIFO_RD = 0x000002a0,
21043PH_PERF_SEL_SC5_PA4_DATA_FIFO_WE = 0x000002a1,
21044PH_PERF_SEL_SC5_PA4_FIFO_EMPTY = 0x000002a2,
21045PH_PERF_SEL_SC5_PA4_FIFO_FULL = 0x000002a3,
21046PH_PERF_SEL_SC5_PA4_NULL_WE = 0x000002a4,
21047PH_PERF_SEL_SC5_PA4_EVENT_WE = 0x000002a5,
21048PH_PERF_SEL_SC5_PA4_FPOV_WE = 0x000002a6,
21049PH_PERF_SEL_SC5_PA4_LPOV_WE = 0x000002a7,
21050PH_PERF_SEL_SC5_PA4_EOP_WE = 0x000002a8,
21051PH_PERF_SEL_SC5_PA4_DATA_FIFO_EOP_RD = 0x000002a9,
21052PH_PERF_SEL_SC5_PA4_EOPG_WE = 0x000002aa,
21053PH_PERF_SEL_SC5_PA4_DEALLOC_4_0_RD = 0x000002ab,
21054PH_PERF_SEL_SC5_PA5_DATA_FIFO_RD = 0x000002ac,
21055PH_PERF_SEL_SC5_PA5_DATA_FIFO_WE = 0x000002ad,
21056PH_PERF_SEL_SC5_PA5_FIFO_EMPTY = 0x000002ae,
21057PH_PERF_SEL_SC5_PA5_FIFO_FULL = 0x000002af,
21058PH_PERF_SEL_SC5_PA5_NULL_WE = 0x000002b0,
21059PH_PERF_SEL_SC5_PA5_EVENT_WE = 0x000002b1,
21060PH_PERF_SEL_SC5_PA5_FPOV_WE = 0x000002b2,
21061PH_PERF_SEL_SC5_PA5_LPOV_WE = 0x000002b3,
21062PH_PERF_SEL_SC5_PA5_EOP_WE = 0x000002b4,
21063PH_PERF_SEL_SC5_PA5_DATA_FIFO_EOP_RD = 0x000002b5,
21064PH_PERF_SEL_SC5_PA5_EOPG_WE = 0x000002b6,
21065PH_PERF_SEL_SC5_PA5_DEALLOC_4_0_RD = 0x000002b7,
21066PH_PERF_SEL_SC5_PA6_DATA_FIFO_RD = 0x000002b8,
21067PH_PERF_SEL_SC5_PA6_DATA_FIFO_WE = 0x000002b9,
21068PH_PERF_SEL_SC5_PA6_FIFO_EMPTY = 0x000002ba,
21069PH_PERF_SEL_SC5_PA6_FIFO_FULL = 0x000002bb,
21070PH_PERF_SEL_SC5_PA6_NULL_WE = 0x000002bc,
21071PH_PERF_SEL_SC5_PA6_EVENT_WE = 0x000002bd,
21072PH_PERF_SEL_SC5_PA6_FPOV_WE = 0x000002be,
21073PH_PERF_SEL_SC5_PA6_LPOV_WE = 0x000002bf,
21074PH_PERF_SEL_SC5_PA6_EOP_WE = 0x000002c0,
21075PH_PERF_SEL_SC5_PA6_DATA_FIFO_EOP_RD = 0x000002c1,
21076PH_PERF_SEL_SC5_PA6_EOPG_WE = 0x000002c2,
21077PH_PERF_SEL_SC5_PA6_DEALLOC_4_0_RD = 0x000002c3,
21078PH_PERF_SEL_SC5_PA7_DATA_FIFO_RD = 0x000002c4,
21079PH_PERF_SEL_SC5_PA7_DATA_FIFO_WE = 0x000002c5,
21080PH_PERF_SEL_SC5_PA7_FIFO_EMPTY = 0x000002c6,
21081PH_PERF_SEL_SC5_PA7_FIFO_FULL = 0x000002c7,
21082PH_PERF_SEL_SC5_PA7_NULL_WE = 0x000002c8,
21083PH_PERF_SEL_SC5_PA7_EVENT_WE = 0x000002c9,
21084PH_PERF_SEL_SC5_PA7_FPOV_WE = 0x000002ca,
21085PH_PERF_SEL_SC5_PA7_LPOV_WE = 0x000002cb,
21086PH_PERF_SEL_SC5_PA7_EOP_WE = 0x000002cc,
21087PH_PERF_SEL_SC5_PA7_DATA_FIFO_EOP_RD = 0x000002cd,
21088PH_PERF_SEL_SC5_PA7_EOPG_WE = 0x000002ce,
21089PH_PERF_SEL_SC5_PA7_DEALLOC_4_0_RD = 0x000002cf,
21090PH_PERF_SEL_SC6_SRPS_WINDOW_VALID = 0x000002d0,
21091PH_PERF_SEL_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000002d1,
21092PH_PERF_SEL_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 0x000002d2,
21093PH_PERF_SEL_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000002d3,
21094PH_PERF_SEL_SC6_ARB_STALLED_FROM_BELOW = 0x000002d4,
21095PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE = 0x000002d5,
21096PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000002d6,
21097PH_PERF_SEL_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000002d7,
21098PH_PERF_SEL_SC6_ARB_BUSY = 0x000002d8,
21099PH_PERF_SEL_SC6_ARB_PA_BUSY_SOP = 0x000002d9,
21100PH_PERF_SEL_SC6_ARB_EOP_POP_SYNC_POP = 0x000002da,
21101PH_PERF_SEL_SC6_ARB_EVENT_SYNC_POP = 0x000002db,
21102PH_PERF_SEL_SC6_PS_ENG_MULTICYCLE_BUBBLE = 0x000002dc,
21103PH_PERF_SEL_SC6_EOP_SYNC_WINDOW = 0x000002dd,
21104PH_PERF_SEL_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000002de,
21105PH_PERF_SEL_SC6_BUSY_CNT_NOT_ZERO = 0x000002df,
21106PH_PERF_SEL_SC6_SEND = 0x000002e0,
21107PH_PERF_SEL_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000002e1,
21108PH_PERF_SEL_SC6_CREDIT_AT_MAX = 0x000002e2,
21109PH_PERF_SEL_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000002e3,
21110PH_PERF_SEL_SC6_GFX_PIPE0_TO_1_TRANSITION = 0x000002e4,
21111PH_PERF_SEL_SC6_GFX_PIPE1_TO_0_TRANSITION = 0x000002e5,
21112PH_PERF_SEL_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000002e6,
21113PH_PERF_SEL_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000002e7,
21114PH_PERF_SEL_SC6_PA0_DATA_FIFO_RD = 0x000002e8,
21115PH_PERF_SEL_SC6_PA0_DATA_FIFO_WE = 0x000002e9,
21116PH_PERF_SEL_SC6_PA0_FIFO_EMPTY = 0x000002ea,
21117PH_PERF_SEL_SC6_PA0_FIFO_FULL = 0x000002eb,
21118PH_PERF_SEL_SC6_PA0_NULL_WE = 0x000002ec,
21119PH_PERF_SEL_SC6_PA0_EVENT_WE = 0x000002ed,
21120PH_PERF_SEL_SC6_PA0_FPOV_WE = 0x000002ee,
21121PH_PERF_SEL_SC6_PA0_LPOV_WE = 0x000002ef,
21122PH_PERF_SEL_SC6_PA0_EOP_WE = 0x000002f0,
21123PH_PERF_SEL_SC6_PA0_DATA_FIFO_EOP_RD = 0x000002f1,
21124PH_PERF_SEL_SC6_PA0_EOPG_WE = 0x000002f2,
21125PH_PERF_SEL_SC6_PA0_DEALLOC_4_0_RD = 0x000002f3,
21126PH_PERF_SEL_SC6_PA1_DATA_FIFO_RD = 0x000002f4,
21127PH_PERF_SEL_SC6_PA1_DATA_FIFO_WE = 0x000002f5,
21128PH_PERF_SEL_SC6_PA1_FIFO_EMPTY = 0x000002f6,
21129PH_PERF_SEL_SC6_PA1_FIFO_FULL = 0x000002f7,
21130PH_PERF_SEL_SC6_PA1_NULL_WE = 0x000002f8,
21131PH_PERF_SEL_SC6_PA1_EVENT_WE = 0x000002f9,
21132PH_PERF_SEL_SC6_PA1_FPOV_WE = 0x000002fa,
21133PH_PERF_SEL_SC6_PA1_LPOV_WE = 0x000002fb,
21134PH_PERF_SEL_SC6_PA1_EOP_WE = 0x000002fc,
21135PH_PERF_SEL_SC6_PA1_DATA_FIFO_EOP_RD = 0x000002fd,
21136PH_PERF_SEL_SC6_PA1_EOPG_WE = 0x000002fe,
21137PH_PERF_SEL_SC6_PA1_DEALLOC_4_0_RD = 0x000002ff,
21138PH_PERF_SEL_SC6_PA2_DATA_FIFO_RD = 0x00000300,
21139PH_PERF_SEL_SC6_PA2_DATA_FIFO_WE = 0x00000301,
21140PH_PERF_SEL_SC6_PA2_FIFO_EMPTY = 0x00000302,
21141PH_PERF_SEL_SC6_PA2_FIFO_FULL = 0x00000303,
21142PH_PERF_SEL_SC6_PA2_NULL_WE = 0x00000304,
21143PH_PERF_SEL_SC6_PA2_EVENT_WE = 0x00000305,
21144PH_PERF_SEL_SC6_PA2_FPOV_WE = 0x00000306,
21145PH_PERF_SEL_SC6_PA2_LPOV_WE = 0x00000307,
21146PH_PERF_SEL_SC6_PA2_EOP_WE = 0x00000308,
21147PH_PERF_SEL_SC6_PA2_DATA_FIFO_EOP_RD = 0x00000309,
21148PH_PERF_SEL_SC6_PA2_EOPG_WE = 0x0000030a,
21149PH_PERF_SEL_SC6_PA2_DEALLOC_4_0_RD = 0x0000030b,
21150PH_PERF_SEL_SC6_PA3_DATA_FIFO_RD = 0x0000030c,
21151PH_PERF_SEL_SC6_PA3_DATA_FIFO_WE = 0x0000030d,
21152PH_PERF_SEL_SC6_PA3_FIFO_EMPTY = 0x0000030e,
21153PH_PERF_SEL_SC6_PA3_FIFO_FULL = 0x0000030f,
21154PH_PERF_SEL_SC6_PA3_NULL_WE = 0x00000310,
21155PH_PERF_SEL_SC6_PA3_EVENT_WE = 0x00000311,
21156PH_PERF_SEL_SC6_PA3_FPOV_WE = 0x00000312,
21157PH_PERF_SEL_SC6_PA3_LPOV_WE = 0x00000313,
21158PH_PERF_SEL_SC6_PA3_EOP_WE = 0x00000314,
21159PH_PERF_SEL_SC6_PA3_DATA_FIFO_EOP_RD = 0x00000315,
21160PH_PERF_SEL_SC6_PA3_EOPG_WE = 0x00000316,
21161PH_PERF_SEL_SC6_PA3_DEALLOC_4_0_RD = 0x00000317,
21162PH_PERF_SEL_SC6_PA4_DATA_FIFO_RD = 0x00000318,
21163PH_PERF_SEL_SC6_PA4_DATA_FIFO_WE = 0x00000319,
21164PH_PERF_SEL_SC6_PA4_FIFO_EMPTY = 0x0000031a,
21165PH_PERF_SEL_SC6_PA4_FIFO_FULL = 0x0000031b,
21166PH_PERF_SEL_SC6_PA4_NULL_WE = 0x0000031c,
21167PH_PERF_SEL_SC6_PA4_EVENT_WE = 0x0000031d,
21168PH_PERF_SEL_SC6_PA4_FPOV_WE = 0x0000031e,
21169PH_PERF_SEL_SC6_PA4_LPOV_WE = 0x0000031f,
21170PH_PERF_SEL_SC6_PA4_EOP_WE = 0x00000320,
21171PH_PERF_SEL_SC6_PA4_DATA_FIFO_EOP_RD = 0x00000321,
21172PH_PERF_SEL_SC6_PA4_EOPG_WE = 0x00000322,
21173PH_PERF_SEL_SC6_PA4_DEALLOC_4_0_RD = 0x00000323,
21174PH_PERF_SEL_SC6_PA5_DATA_FIFO_RD = 0x00000324,
21175PH_PERF_SEL_SC6_PA5_DATA_FIFO_WE = 0x00000325,
21176PH_PERF_SEL_SC6_PA5_FIFO_EMPTY = 0x00000326,
21177PH_PERF_SEL_SC6_PA5_FIFO_FULL = 0x00000327,
21178PH_PERF_SEL_SC6_PA5_NULL_WE = 0x00000328,
21179PH_PERF_SEL_SC6_PA5_EVENT_WE = 0x00000329,
21180PH_PERF_SEL_SC6_PA5_FPOV_WE = 0x0000032a,
21181PH_PERF_SEL_SC6_PA5_LPOV_WE = 0x0000032b,
21182PH_PERF_SEL_SC6_PA5_EOP_WE = 0x0000032c,
21183PH_PERF_SEL_SC6_PA5_DATA_FIFO_EOP_RD = 0x0000032d,
21184PH_PERF_SEL_SC6_PA5_EOPG_WE = 0x0000032e,
21185PH_PERF_SEL_SC6_PA5_DEALLOC_4_0_RD = 0x0000032f,
21186PH_PERF_SEL_SC6_PA6_DATA_FIFO_RD = 0x00000330,
21187PH_PERF_SEL_SC6_PA6_DATA_FIFO_WE = 0x00000331,
21188PH_PERF_SEL_SC6_PA6_FIFO_EMPTY = 0x00000332,
21189PH_PERF_SEL_SC6_PA6_FIFO_FULL = 0x00000333,
21190PH_PERF_SEL_SC6_PA6_NULL_WE = 0x00000334,
21191PH_PERF_SEL_SC6_PA6_EVENT_WE = 0x00000335,
21192PH_PERF_SEL_SC6_PA6_FPOV_WE = 0x00000336,
21193PH_PERF_SEL_SC6_PA6_LPOV_WE = 0x00000337,
21194PH_PERF_SEL_SC6_PA6_EOP_WE = 0x00000338,
21195PH_PERF_SEL_SC6_PA6_DATA_FIFO_EOP_RD = 0x00000339,
21196PH_PERF_SEL_SC6_PA6_EOPG_WE = 0x0000033a,
21197PH_PERF_SEL_SC6_PA6_DEALLOC_4_0_RD = 0x0000033b,
21198PH_PERF_SEL_SC6_PA7_DATA_FIFO_RD = 0x0000033c,
21199PH_PERF_SEL_SC6_PA7_DATA_FIFO_WE = 0x0000033d,
21200PH_PERF_SEL_SC6_PA7_FIFO_EMPTY = 0x0000033e,
21201PH_PERF_SEL_SC6_PA7_FIFO_FULL = 0x0000033f,
21202PH_PERF_SEL_SC6_PA7_NULL_WE = 0x00000340,
21203PH_PERF_SEL_SC6_PA7_EVENT_WE = 0x00000341,
21204PH_PERF_SEL_SC6_PA7_FPOV_WE = 0x00000342,
21205PH_PERF_SEL_SC6_PA7_LPOV_WE = 0x00000343,
21206PH_PERF_SEL_SC6_PA7_EOP_WE = 0x00000344,
21207PH_PERF_SEL_SC6_PA7_DATA_FIFO_EOP_RD = 0x00000345,
21208PH_PERF_SEL_SC6_PA7_EOPG_WE = 0x00000346,
21209PH_PERF_SEL_SC6_PA7_DEALLOC_4_0_RD = 0x00000347,
21210PH_PERF_SEL_SC7_SRPS_WINDOW_VALID = 0x00000348,
21211PH_PERF_SEL_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000349,
21212PH_PERF_SEL_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000034a,
21213PH_PERF_SEL_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000034b,
21214PH_PERF_SEL_SC7_ARB_STALLED_FROM_BELOW = 0x0000034c,
21215PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE = 0x0000034d,
21216PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000034e,
21217PH_PERF_SEL_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000034f,
21218PH_PERF_SEL_SC7_ARB_BUSY = 0x00000350,
21219PH_PERF_SEL_SC7_ARB_PA_BUSY_SOP = 0x00000351,
21220PH_PERF_SEL_SC7_ARB_EOP_POP_SYNC_POP = 0x00000352,
21221PH_PERF_SEL_SC7_ARB_EVENT_SYNC_POP = 0x00000353,
21222PH_PERF_SEL_SC7_PS_ENG_MULTICYCLE_BUBBLE = 0x00000354,
21223PH_PERF_SEL_SC7_EOP_SYNC_WINDOW = 0x00000355,
21224PH_PERF_SEL_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000356,
21225PH_PERF_SEL_SC7_BUSY_CNT_NOT_ZERO = 0x00000357,
21226PH_PERF_SEL_SC7_SEND = 0x00000358,
21227PH_PERF_SEL_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000359,
21228PH_PERF_SEL_SC7_CREDIT_AT_MAX = 0x0000035a,
21229PH_PERF_SEL_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000035b,
21230PH_PERF_SEL_SC7_GFX_PIPE0_TO_1_TRANSITION = 0x0000035c,
21231PH_PERF_SEL_SC7_GFX_PIPE1_TO_0_TRANSITION = 0x0000035d,
21232PH_PERF_SEL_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000035e,
21233PH_PERF_SEL_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000035f,
21234PH_PERF_SEL_SC7_PA0_DATA_FIFO_RD = 0x00000360,
21235PH_PERF_SEL_SC7_PA0_DATA_FIFO_WE = 0x00000361,
21236PH_PERF_SEL_SC7_PA0_FIFO_EMPTY = 0x00000362,
21237PH_PERF_SEL_SC7_PA0_FIFO_FULL = 0x00000363,
21238PH_PERF_SEL_SC7_PA0_NULL_WE = 0x00000364,
21239PH_PERF_SEL_SC7_PA0_EVENT_WE = 0x00000365,
21240PH_PERF_SEL_SC7_PA0_FPOV_WE = 0x00000366,
21241PH_PERF_SEL_SC7_PA0_LPOV_WE = 0x00000367,
21242PH_PERF_SEL_SC7_PA0_EOP_WE = 0x00000368,
21243PH_PERF_SEL_SC7_PA0_DATA_FIFO_EOP_RD = 0x00000369,
21244PH_PERF_SEL_SC7_PA0_EOPG_WE = 0x0000036a,
21245PH_PERF_SEL_SC7_PA0_DEALLOC_4_0_RD = 0x0000036b,
21246PH_PERF_SEL_SC7_PA1_DATA_FIFO_RD = 0x0000036c,
21247PH_PERF_SEL_SC7_PA1_DATA_FIFO_WE = 0x0000036d,
21248PH_PERF_SEL_SC7_PA1_FIFO_EMPTY = 0x0000036e,
21249PH_PERF_SEL_SC7_PA1_FIFO_FULL = 0x0000036f,
21250PH_PERF_SEL_SC7_PA1_NULL_WE = 0x00000370,
21251PH_PERF_SEL_SC7_PA1_EVENT_WE = 0x00000371,
21252PH_PERF_SEL_SC7_PA1_FPOV_WE = 0x00000372,
21253PH_PERF_SEL_SC7_PA1_LPOV_WE = 0x00000373,
21254PH_PERF_SEL_SC7_PA1_EOP_WE = 0x00000374,
21255PH_PERF_SEL_SC7_PA1_DATA_FIFO_EOP_RD = 0x00000375,
21256PH_PERF_SEL_SC7_PA1_EOPG_WE = 0x00000376,
21257PH_PERF_SEL_SC7_PA1_DEALLOC_4_0_RD = 0x00000377,
21258PH_PERF_SEL_SC7_PA2_DATA_FIFO_RD = 0x00000378,
21259PH_PERF_SEL_SC7_PA2_DATA_FIFO_WE = 0x00000379,
21260PH_PERF_SEL_SC7_PA2_FIFO_EMPTY = 0x0000037a,
21261PH_PERF_SEL_SC7_PA2_FIFO_FULL = 0x0000037b,
21262PH_PERF_SEL_SC7_PA2_NULL_WE = 0x0000037c,
21263PH_PERF_SEL_SC7_PA2_EVENT_WE = 0x0000037d,
21264PH_PERF_SEL_SC7_PA2_FPOV_WE = 0x0000037e,
21265PH_PERF_SEL_SC7_PA2_LPOV_WE = 0x0000037f,
21266PH_PERF_SEL_SC7_PA2_EOP_WE = 0x00000380,
21267PH_PERF_SEL_SC7_PA2_DATA_FIFO_EOP_RD = 0x00000381,
21268PH_PERF_SEL_SC7_PA2_EOPG_WE = 0x00000382,
21269PH_PERF_SEL_SC7_PA2_DEALLOC_4_0_RD = 0x00000383,
21270PH_PERF_SEL_SC7_PA3_DATA_FIFO_RD = 0x00000384,
21271PH_PERF_SEL_SC7_PA3_DATA_FIFO_WE = 0x00000385,
21272PH_PERF_SEL_SC7_PA3_FIFO_EMPTY = 0x00000386,
21273PH_PERF_SEL_SC7_PA3_FIFO_FULL = 0x00000387,
21274PH_PERF_SEL_SC7_PA3_NULL_WE = 0x00000388,
21275PH_PERF_SEL_SC7_PA3_EVENT_WE = 0x00000389,
21276PH_PERF_SEL_SC7_PA3_FPOV_WE = 0x0000038a,
21277PH_PERF_SEL_SC7_PA3_LPOV_WE = 0x0000038b,
21278PH_PERF_SEL_SC7_PA3_EOP_WE = 0x0000038c,
21279PH_PERF_SEL_SC7_PA3_DATA_FIFO_EOP_RD = 0x0000038d,
21280PH_PERF_SEL_SC7_PA3_EOPG_WE = 0x0000038e,
21281PH_PERF_SEL_SC7_PA3_DEALLOC_4_0_RD = 0x0000038f,
21282PH_PERF_SEL_SC7_PA4_DATA_FIFO_RD = 0x00000390,
21283PH_PERF_SEL_SC7_PA4_DATA_FIFO_WE = 0x00000391,
21284PH_PERF_SEL_SC7_PA4_FIFO_EMPTY = 0x00000392,
21285PH_PERF_SEL_SC7_PA4_FIFO_FULL = 0x00000393,
21286PH_PERF_SEL_SC7_PA4_NULL_WE = 0x00000394,
21287PH_PERF_SEL_SC7_PA4_EVENT_WE = 0x00000395,
21288PH_PERF_SEL_SC7_PA4_FPOV_WE = 0x00000396,
21289PH_PERF_SEL_SC7_PA4_LPOV_WE = 0x00000397,
21290PH_PERF_SEL_SC7_PA4_EOP_WE = 0x00000398,
21291PH_PERF_SEL_SC7_PA4_DATA_FIFO_EOP_RD = 0x00000399,
21292PH_PERF_SEL_SC7_PA4_EOPG_WE = 0x0000039a,
21293PH_PERF_SEL_SC7_PA4_DEALLOC_4_0_RD = 0x0000039b,
21294PH_PERF_SEL_SC7_PA5_DATA_FIFO_RD = 0x0000039c,
21295PH_PERF_SEL_SC7_PA5_DATA_FIFO_WE = 0x0000039d,
21296PH_PERF_SEL_SC7_PA5_FIFO_EMPTY = 0x0000039e,
21297PH_PERF_SEL_SC7_PA5_FIFO_FULL = 0x0000039f,
21298PH_PERF_SEL_SC7_PA5_NULL_WE = 0x000003a0,
21299PH_PERF_SEL_SC7_PA5_EVENT_WE = 0x000003a1,
21300PH_PERF_SEL_SC7_PA5_FPOV_WE = 0x000003a2,
21301PH_PERF_SEL_SC7_PA5_LPOV_WE = 0x000003a3,
21302PH_PERF_SEL_SC7_PA5_EOP_WE = 0x000003a4,
21303PH_PERF_SEL_SC7_PA5_DATA_FIFO_EOP_RD = 0x000003a5,
21304PH_PERF_SEL_SC7_PA5_EOPG_WE = 0x000003a6,
21305PH_PERF_SEL_SC7_PA5_DEALLOC_4_0_RD = 0x000003a7,
21306PH_PERF_SEL_SC7_PA6_DATA_FIFO_RD = 0x000003a8,
21307PH_PERF_SEL_SC7_PA6_DATA_FIFO_WE = 0x000003a9,
21308PH_PERF_SEL_SC7_PA6_FIFO_EMPTY = 0x000003aa,
21309PH_PERF_SEL_SC7_PA6_FIFO_FULL = 0x000003ab,
21310PH_PERF_SEL_SC7_PA6_NULL_WE = 0x000003ac,
21311PH_PERF_SEL_SC7_PA6_EVENT_WE = 0x000003ad,
21312PH_PERF_SEL_SC7_PA6_FPOV_WE = 0x000003ae,
21313PH_PERF_SEL_SC7_PA6_LPOV_WE = 0x000003af,
21314PH_PERF_SEL_SC7_PA6_EOP_WE = 0x000003b0,
21315PH_PERF_SEL_SC7_PA6_DATA_FIFO_EOP_RD = 0x000003b1,
21316PH_PERF_SEL_SC7_PA6_EOPG_WE = 0x000003b2,
21317PH_PERF_SEL_SC7_PA6_DEALLOC_4_0_RD = 0x000003b3,
21318PH_PERF_SEL_SC7_PA7_DATA_FIFO_RD = 0x000003b4,
21319PH_PERF_SEL_SC7_PA7_DATA_FIFO_WE = 0x000003b5,
21320PH_PERF_SEL_SC7_PA7_FIFO_EMPTY = 0x000003b6,
21321PH_PERF_SEL_SC7_PA7_FIFO_FULL = 0x000003b7,
21322PH_PERF_SEL_SC7_PA7_NULL_WE = 0x000003b8,
21323PH_PERF_SEL_SC7_PA7_EVENT_WE = 0x000003b9,
21324PH_PERF_SEL_SC7_PA7_FPOV_WE = 0x000003ba,
21325PH_PERF_SEL_SC7_PA7_LPOV_WE = 0x000003bb,
21326PH_PERF_SEL_SC7_PA7_EOP_WE = 0x000003bc,
21327PH_PERF_SEL_SC7_PA7_DATA_FIFO_EOP_RD = 0x000003bd,
21328PH_PERF_SEL_SC7_PA7_EOPG_WE = 0x000003be,
21329PH_PERF_SEL_SC7_PA7_DEALLOC_4_0_RD = 0x000003bf,
21330PH_PERF_SEL_1_SC_ARB_STALLED_FROM_BELOW = 0x000003c0,
21331PH_PERF_SEL_2_SC_ARB_STALLED_FROM_BELOW = 0x000003c1,
21332PH_PERF_SEL_3_SC_ARB_STALLED_FROM_BELOW = 0x000003c2,
21333PH_PERF_SEL_4_SC_ARB_STALLED_FROM_BELOW = 0x000003c3,
21334PH_PERF_SEL_5_SC_ARB_STALLED_FROM_BELOW = 0x000003c4,
21335PH_PERF_SEL_6_SC_ARB_STALLED_FROM_BELOW = 0x000003c5,
21336PH_PERF_SEL_7_SC_ARB_STALLED_FROM_BELOW = 0x000003c6,
21337PH_PERF_SEL_8_SC_ARB_STALLED_FROM_BELOW = 0x000003c7,
21338PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE = 0x000003c8,
21339PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE = 0x000003c9,
21340PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE = 0x000003ca,
21341PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE = 0x000003cb,
21342PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE = 0x000003cc,
21343PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE = 0x000003cd,
21344PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE = 0x000003ce,
21345PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE = 0x000003cf,
21346PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d0,
21347PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d1,
21348PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d2,
21349PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d3,
21350PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d4,
21351PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d5,
21352PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d6,
21353PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000003d7,
21354PH_PERF_SEL_1_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003d8,
21355PH_PERF_SEL_2_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003d9,
21356PH_PERF_SEL_3_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003da,
21357PH_PERF_SEL_4_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003db,
21358PH_PERF_SEL_5_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003dc,
21359PH_PERF_SEL_6_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003dd,
21360PH_PERF_SEL_7_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003de,
21361PH_PERF_SEL_8_SC_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000003df,
21362PH_PERF_SC0_FIFO_STATUS_0 = 0x000003e0,
21363PH_PERF_SC0_FIFO_STATUS_1 = 0x000003e1,
21364PH_PERF_SC0_FIFO_STATUS_2 = 0x000003e2,
21365PH_PERF_SC0_FIFO_STATUS_3 = 0x000003e3,
21366PH_PERF_SC1_FIFO_STATUS_0 = 0x000003e4,
21367PH_PERF_SC1_FIFO_STATUS_1 = 0x000003e5,
21368PH_PERF_SC1_FIFO_STATUS_2 = 0x000003e6,
21369PH_PERF_SC1_FIFO_STATUS_3 = 0x000003e7,
21370PH_PERF_SC2_FIFO_STATUS_0 = 0x000003e8,
21371PH_PERF_SC2_FIFO_STATUS_1 = 0x000003e9,
21372PH_PERF_SC2_FIFO_STATUS_2 = 0x000003ea,
21373PH_PERF_SC2_FIFO_STATUS_3 = 0x000003eb,
21374PH_PERF_SC3_FIFO_STATUS_0 = 0x000003ec,
21375PH_PERF_SC3_FIFO_STATUS_1 = 0x000003ed,
21376PH_PERF_SC3_FIFO_STATUS_2 = 0x000003ee,
21377PH_PERF_SC3_FIFO_STATUS_3 = 0x000003ef,
21378PH_PERF_SC4_FIFO_STATUS_0 = 0x000003f0,
21379PH_PERF_SC4_FIFO_STATUS_1 = 0x000003f1,
21380PH_PERF_SC4_FIFO_STATUS_2 = 0x000003f2,
21381PH_PERF_SC4_FIFO_STATUS_3 = 0x000003f3,
21382PH_PERF_SC5_FIFO_STATUS_0 = 0x000003f4,
21383PH_PERF_SC5_FIFO_STATUS_1 = 0x000003f5,
21384PH_PERF_SC5_FIFO_STATUS_2 = 0x000003f6,
21385PH_PERF_SC5_FIFO_STATUS_3 = 0x000003f7,
21386PH_PERF_SC6_FIFO_STATUS_0 = 0x000003f8,
21387PH_PERF_SC6_FIFO_STATUS_1 = 0x000003f9,
21388PH_PERF_SC6_FIFO_STATUS_2 = 0x000003fa,
21389PH_PERF_SC6_FIFO_STATUS_3 = 0x000003fb,
21390PH_PERF_SC7_FIFO_STATUS_0 = 0x000003fc,
21391PH_PERF_SC7_FIFO_STATUS_1 = 0x000003fd,
21392PH_PERF_SC7_FIFO_STATUS_2 = 0x000003fe,
21393PH_PERF_SC7_FIFO_STATUS_3 = 0x000003ff,
21394} PH_PERFCNT_SEL;
21395
21396/*
21397 * PhSPIstatusMode enum
21398 */
21399
21400typedef enum PhSPIstatusMode {
21401PH_SPI_MODE_LARGEST_PA_PH_FIFO_COUNT = 0x00000000,
21402PH_SPI_MODE_ARBITER_SELECTED_PA_PH_FIFO_COUNT = 0x00000001,
21403PH_SPI_MODE_DISABLED = 0x00000002,
21404} PhSPIstatusMode;
21405
21406/*******************************************************
21407 * RMI Enums
21408 *******************************************************/
21409
21410/*
21411 * RMIPerfSel enum
21412 */
21413
21414typedef enum RMIPerfSel {
21415RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0x00000000,
21416RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 0x00000001,
21417} RMIPerfSel;
21418
21419/*******************************************************
21420 * PMM Enums
21421 *******************************************************/
21422
21423/*
21424 * GCRPerfSel enum
21425 */
21426
21427typedef enum GCRPerfSel {
21428GCR_PERF_SEL_NONE = 0x00000000,
21429GCR_PERF_SEL_SDMA0_ALL_REQ = 0x00000001,
21430GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 0x00000002,
21431GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 0x00000003,
21432GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 0x00000004,
21433GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 0x00000005,
21434GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 0x00000006,
21435GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 0x00000007,
21436GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 0x00000008,
21437GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 0x00000009,
21438GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 0x0000000a,
21439GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 0x0000000b,
21440GCR_PERF_SEL_SDMA0_METADATA_REQ = 0x0000000c,
21441GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 0x0000000d,
21442GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 0x0000000e,
21443GCR_PERF_SEL_SDMA0_TCP_REQ = 0x0000000f,
21444GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 0x00000010,
21445GCR_PERF_SEL_SDMA1_ALL_REQ = 0x00000011,
21446GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 0x00000012,
21447GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 0x00000013,
21448GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 0x00000014,
21449GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 0x00000015,
21450GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 0x00000016,
21451GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 0x00000017,
21452GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 0x00000018,
21453GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 0x00000019,
21454GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 0x0000001a,
21455GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 0x0000001b,
21456GCR_PERF_SEL_SDMA1_METADATA_REQ = 0x0000001c,
21457GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 0x0000001d,
21458GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 0x0000001e,
21459GCR_PERF_SEL_SDMA1_TCP_REQ = 0x0000001f,
21460GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 0x00000020,
21461GCR_PERF_SEL_CPC_ALL_REQ = 0x00000021,
21462GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 0x00000022,
21463GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 0x00000023,
21464GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 0x00000024,
21465GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 0x00000025,
21466GCR_PERF_SEL_CPC_GL2_ALL_REQ = 0x00000026,
21467GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 0x00000027,
21468GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 0x00000028,
21469GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 0x00000029,
21470GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 0x0000002a,
21471GCR_PERF_SEL_CPC_GL1_ALL_REQ = 0x0000002b,
21472GCR_PERF_SEL_CPC_METADATA_REQ = 0x0000002c,
21473GCR_PERF_SEL_CPC_SQC_DATA_REQ = 0x0000002d,
21474GCR_PERF_SEL_CPC_SQC_INST_REQ = 0x0000002e,
21475GCR_PERF_SEL_CPC_TCP_REQ = 0x0000002f,
21476GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 0x00000030,
21477GCR_PERF_SEL_CPG_ALL_REQ = 0x00000031,
21478GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 0x00000032,
21479GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 0x00000033,
21480GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 0x00000034,
21481GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 0x00000035,
21482GCR_PERF_SEL_CPG_GL2_ALL_REQ = 0x00000036,
21483GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 0x00000037,
21484GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 0x00000038,
21485GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 0x00000039,
21486GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 0x0000003a,
21487GCR_PERF_SEL_CPG_GL1_ALL_REQ = 0x0000003b,
21488GCR_PERF_SEL_CPG_METADATA_REQ = 0x0000003c,
21489GCR_PERF_SEL_CPG_SQC_DATA_REQ = 0x0000003d,
21490GCR_PERF_SEL_CPG_SQC_INST_REQ = 0x0000003e,
21491GCR_PERF_SEL_CPG_TCP_REQ = 0x0000003f,
21492GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 0x00000040,
21493GCR_PERF_SEL_CPF_ALL_REQ = 0x00000041,
21494GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 0x00000042,
21495GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 0x00000043,
21496GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 0x00000044,
21497GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 0x00000045,
21498GCR_PERF_SEL_CPF_GL2_ALL_REQ = 0x00000046,
21499GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 0x00000047,
21500GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 0x00000048,
21501GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 0x00000049,
21502GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 0x0000004a,
21503GCR_PERF_SEL_CPF_GL1_ALL_REQ = 0x0000004b,
21504GCR_PERF_SEL_CPF_METADATA_REQ = 0x0000004c,
21505GCR_PERF_SEL_CPF_SQC_DATA_REQ = 0x0000004d,
21506GCR_PERF_SEL_CPF_SQC_INST_REQ = 0x0000004e,
21507GCR_PERF_SEL_CPF_TCP_REQ = 0x0000004f,
21508GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 0x00000050,
21509GCR_PERF_SEL_VIRT_REQ = 0x00000051,
21510GCR_PERF_SEL_PHY_REQ = 0x00000052,
21511GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 0x00000053,
21512GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 0x00000054,
21513GCR_PERF_SEL_ALL_REQ = 0x00000055,
21514GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 0x00000056,
21515GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 0x00000057,
21516GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 0x00000058,
21517GCR_PERF_SEL_UTCL2_REQ = 0x00000059,
21518GCR_PERF_SEL_UTCL2_RET = 0x0000005a,
21519GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 0x0000005b,
21520GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 0x0000005c,
21521GCR_PERF_SEL_UTCL2_FILTERED_RET = 0x0000005d,
21522GCR_PERF_SEL_RLC_ALL_REQ = 0x0000005e,
21523GCR_PERF_SEL_RLC_GL2_RANGE_REQ = 0x0000005f,
21524GCR_PERF_SEL_RLC_GL2_RANGE_LT16K_REQ = 0x00000060,
21525GCR_PERF_SEL_RLC_GL2_RANGE_16K_REQ = 0x00000061,
21526GCR_PERF_SEL_RLC_GL2_RANGE_GT16K_REQ = 0x00000062,
21527GCR_PERF_SEL_RLC_GL2_ALL_REQ = 0x00000063,
21528GCR_PERF_SEL_RLC_GL1_RANGE_REQ = 0x00000064,
21529GCR_PERF_SEL_RLC_GL1_RANGE_LT16K_REQ = 0x00000065,
21530GCR_PERF_SEL_RLC_GL1_RANGE_16K_REQ = 0x00000066,
21531GCR_PERF_SEL_RLC_GL1_RANGE_GT16K_REQ = 0x00000067,
21532GCR_PERF_SEL_RLC_GL1_ALL_REQ = 0x00000068,
21533GCR_PERF_SEL_RLC_METADATA_REQ = 0x00000069,
21534GCR_PERF_SEL_RLC_SQC_DATA_REQ = 0x0000006a,
21535GCR_PERF_SEL_RLC_SQC_INST_REQ = 0x0000006b,
21536GCR_PERF_SEL_RLC_TCP_REQ = 0x0000006c,
21537GCR_PERF_SEL_RLC_TCP_TLB_SHOOTDOWN_REQ = 0x0000006d,
21538GCR_PERF_SEL_PM_ALL_REQ = 0x0000006e,
21539GCR_PERF_SEL_PM_GL2_RANGE_REQ = 0x0000006f,
21540GCR_PERF_SEL_PM_GL2_RANGE_LT16K_REQ = 0x00000070,
21541GCR_PERF_SEL_PM_GL2_RANGE_16K_REQ = 0x00000071,
21542GCR_PERF_SEL_PM_GL2_RANGE_GT16K_REQ = 0x00000072,
21543GCR_PERF_SEL_PM_GL2_ALL_REQ = 0x00000073,
21544GCR_PERF_SEL_PM_GL1_RANGE_REQ = 0x00000074,
21545GCR_PERF_SEL_PM_GL1_RANGE_LT16K_REQ = 0x00000075,
21546GCR_PERF_SEL_PM_GL1_RANGE_16K_REQ = 0x00000076,
21547GCR_PERF_SEL_PM_GL1_RANGE_GT16K_REQ = 0x00000077,
21548GCR_PERF_SEL_PM_GL1_ALL_REQ = 0x00000078,
21549GCR_PERF_SEL_PM_METADATA_REQ = 0x00000079,
21550GCR_PERF_SEL_PM_SQC_DATA_REQ = 0x0000007a,
21551GCR_PERF_SEL_PM_SQC_INST_REQ = 0x0000007b,
21552GCR_PERF_SEL_PM_TCP_REQ = 0x0000007c,
21553GCR_PERF_SEL_PM_TCP_TLB_SHOOTDOWN_REQ = 0x0000007d,
21554GCR_PERF_SEL_PIO_ALL_REQ = 0x0000007e,
21555GCR_PERF_SEL_PIO_GL2_RANGE_REQ = 0x0000007f,
21556GCR_PERF_SEL_PIO_GL2_RANGE_LT16K_REQ = 0x00000080,
21557GCR_PERF_SEL_PIO_GL2_RANGE_16K_REQ = 0x00000081,
21558GCR_PERF_SEL_PIO_GL2_RANGE_GT16K_REQ = 0x00000082,
21559GCR_PERF_SEL_PIO_GL2_ALL_REQ = 0x00000083,
21560GCR_PERF_SEL_PIO_GL1_RANGE_REQ = 0x00000084,
21561GCR_PERF_SEL_PIO_GL1_RANGE_LT16K_REQ = 0x00000085,
21562GCR_PERF_SEL_PIO_GL1_RANGE_16K_REQ = 0x00000086,
21563GCR_PERF_SEL_PIO_GL1_RANGE_GT16K_REQ = 0x00000087,
21564GCR_PERF_SEL_PIO_GL1_ALL_REQ = 0x00000088,
21565GCR_PERF_SEL_PIO_METADATA_REQ = 0x00000089,
21566GCR_PERF_SEL_PIO_SQC_DATA_REQ = 0x0000008a,
21567GCR_PERF_SEL_PIO_SQC_INST_REQ = 0x0000008b,
21568GCR_PERF_SEL_PIO_TCP_REQ = 0x0000008c,
21569GCR_PERF_SEL_PIO_TCP_TLB_SHOOTDOWN_REQ = 0x0000008d,
21570} GCRPerfSel;
21571
21572/*******************************************************
21573 * UTCL1 Enums
21574 *******************************************************/
21575
21576/*
21577 * UTCL1PerfSel enum
21578 */
21579
21580typedef enum UTCL1PerfSel {
21581UTCL1_PERF_SEL_NONE = 0x00000000,
21582UTCL1_PERF_SEL_REQS = 0x00000001,
21583UTCL1_PERF_SEL_HITS = 0x00000002,
21584UTCL1_PERF_SEL_MISSES = 0x00000003,
21585UTCL1_PERF_SEL_MH_RECENT_BUF_HIT = 0x00000004,
21586UTCL1_PERF_SEL_MH_DUPLICATE_DETECT = 0x00000005,
21587UTCL1_PERF_SEL_UTCL2_REQS = 0x00000006,
21588UTCL1_PERF_SEL_UTCL2_RET_XNACK_RETRY = 0x00000007,
21589UTCL1_PERF_SEL_UTCL2_RET_FAULT = 0x00000008,
21590UTCL1_PERF_SEL_STALL_UTCL2_CREDITS = 0x00000009,
21591UTCL1_PERF_SEL_STALL_MH_FULL = 0x0000000a,
21592UTCL1_PERF_SEL_UTCL2_REQS_OUTSTANDING_ACCUM = 0x0000000b,
21593UTCL1_PERF_SEL_UTCL2_RET_CNT = 0x0000000c,
21594UTCL1_PERF_SEL_RTNS = 0x0000000d,
21595UTCL1_PERF_SEL_XLAT_REQ_BUSY = 0x0000000e,
21596UTCL1_PERF_SEL_BYPASS_REQS = 0x0000000f,
21597UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 0x00000010,
21598UTCL1_PERF_SEL_UTCL2_RET_PERM_FAULT = 0x00000011,
21599UTCL1_PERF_SEL_UTCL2_RET_PRT_FAULT = 0x00000012,
21600UTCL1_PERF_SEL_CP_INVREQS = 0x00000013,
21601UTCL1_PERF_SEL_UTCL2_UTCL1_INVREQS = 0x00000014,
21602UTCL1_PERF_SEL_RANGE_INVREQS = 0x00000015,
21603UTCL1_PERF_SEL_INV_ALL_VMID_INVREQS = 0x00000016,
21604} UTCL1PerfSel;
21605
21606/*******************************************************
21607 * IH Enums
21608 *******************************************************/
21609
21610/*
21611 * IH_CLIENT_TYPE enum
21612 */
21613
21614typedef enum IH_CLIENT_TYPE {
21615IH_GFX_VMID_CLIENT = 0x00000000,
21616IH_MM_VMID_CLIENT = 0x00000001,
21617IH_MULTI_VMID_CLIENT = 0x00000002,
21618IH_CLIENT_TYPE_RESERVED = 0x00000003,
21619} IH_CLIENT_TYPE;
21620
21621/*
21622 * IH_INTERFACE_TYPE enum
21623 */
21624
21625typedef enum IH_INTERFACE_TYPE {
21626IH_LEGACY_INTERFACE = 0x00000000,
21627IH_REGISTER_WRITE_INTERFACE = 0x00000001,
21628} IH_INTERFACE_TYPE;
21629
21630/*
21631 * IH_PERF_SEL enum
21632 */
21633
21634typedef enum IH_PERF_SEL {
21635IH_PERF_SEL_CYCLE = 0x00000000,
21636IH_PERF_SEL_IDLE = 0x00000001,
21637IH_PERF_SEL_INPUT_IDLE = 0x00000002,
21638IH_PERF_SEL_BUFFER_IDLE = 0x00000003,
21639IH_PERF_SEL_RB0_FULL = 0x00000004,
21640IH_PERF_SEL_RB0_OVERFLOW = 0x00000005,
21641IH_PERF_SEL_RB0_WPTR_WRITEBACK = 0x00000006,
21642IH_PERF_SEL_RB0_WPTR_WRAP = 0x00000007,
21643IH_PERF_SEL_RB0_RPTR_WRAP = 0x00000008,
21644IH_PERF_SEL_MC_WR_IDLE = 0x00000009,
21645IH_PERF_SEL_MC_WR_COUNT = 0x0000000a,
21646IH_PERF_SEL_MC_WR_STALL = 0x0000000b,
21647IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x0000000c,
21648IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x0000000d,
21649IH_PERF_SEL_BIF_LINE0_RISING = 0x0000000e,
21650IH_PERF_SEL_BIF_LINE0_FALLING = 0x0000000f,
21651IH_PERF_SEL_RB1_FULL = 0x00000010,
21652IH_PERF_SEL_RB1_OVERFLOW = 0x00000011,
21653IH_PERF_SEL_COOKIE_REC_ERROR = 0x00000012,
21654IH_PERF_SEL_RB1_WPTR_WRAP = 0x00000013,
21655IH_PERF_SEL_RB1_RPTR_WRAP = 0x00000014,
21656IH_PERF_SEL_RB2_FULL = 0x00000015,
21657IH_PERF_SEL_RB2_OVERFLOW = 0x00000016,
21658IH_PERF_SEL_CLIENT_CREDIT_ERROR = 0x00000017,
21659IH_PERF_SEL_RB2_WPTR_WRAP = 0x00000018,
21660IH_PERF_SEL_RB2_RPTR_WRAP = 0x00000019,
21661IH_PERF_SEL_STORM_CLIENT_INT_DROP = 0x0000001a,
21662IH_PERF_SEL_SELF_IV_VALID = 0x0000001b,
21663IH_PERF_SEL_BUFFER_FIFO_FULL = 0x0000001c,
21664IH_PERF_SEL_RB0_FULL_VF0 = 0x0000001d,
21665IH_PERF_SEL_RB0_FULL_VF1 = 0x0000001e,
21666IH_PERF_SEL_RB0_FULL_VF2 = 0x0000001f,
21667IH_PERF_SEL_RB0_FULL_VF3 = 0x00000020,
21668IH_PERF_SEL_RB0_FULL_VF4 = 0x00000021,
21669IH_PERF_SEL_RB0_FULL_VF5 = 0x00000022,
21670IH_PERF_SEL_RB0_FULL_VF6 = 0x00000023,
21671IH_PERF_SEL_RB0_FULL_VF7 = 0x00000024,
21672IH_PERF_SEL_RB0_FULL_VF8 = 0x00000025,
21673IH_PERF_SEL_RB0_FULL_VF9 = 0x00000026,
21674IH_PERF_SEL_RB0_FULL_VF10 = 0x00000027,
21675IH_PERF_SEL_RB0_FULL_VF11 = 0x00000028,
21676IH_PERF_SEL_RB0_FULL_VF12 = 0x00000029,
21677IH_PERF_SEL_RB0_FULL_VF13 = 0x0000002a,
21678IH_PERF_SEL_RB0_FULL_VF14 = 0x0000002b,
21679IH_PERF_SEL_RB0_FULL_VF15 = 0x0000002c,
21680IH_PERF_SEL_RB0_OVERFLOW_VF0 = 0x0000002d,
21681IH_PERF_SEL_RB0_OVERFLOW_VF1 = 0x0000002e,
21682IH_PERF_SEL_RB0_OVERFLOW_VF2 = 0x0000002f,
21683IH_PERF_SEL_RB0_OVERFLOW_VF3 = 0x00000030,
21684IH_PERF_SEL_RB0_OVERFLOW_VF4 = 0x00000031,
21685IH_PERF_SEL_RB0_OVERFLOW_VF5 = 0x00000032,
21686IH_PERF_SEL_RB0_OVERFLOW_VF6 = 0x00000033,
21687IH_PERF_SEL_RB0_OVERFLOW_VF7 = 0x00000034,
21688IH_PERF_SEL_RB0_OVERFLOW_VF8 = 0x00000035,
21689IH_PERF_SEL_RB0_OVERFLOW_VF9 = 0x00000036,
21690IH_PERF_SEL_RB0_OVERFLOW_VF10 = 0x00000037,
21691IH_PERF_SEL_RB0_OVERFLOW_VF11 = 0x00000038,
21692IH_PERF_SEL_RB0_OVERFLOW_VF12 = 0x00000039,
21693IH_PERF_SEL_RB0_OVERFLOW_VF13 = 0x0000003a,
21694IH_PERF_SEL_RB0_OVERFLOW_VF14 = 0x0000003b,
21695IH_PERF_SEL_RB0_OVERFLOW_VF15 = 0x0000003c,
21696IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 0x0000003d,
21697IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 0x0000003e,
21698IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 0x0000003f,
21699IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 0x00000040,
21700IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 0x00000041,
21701IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 0x00000042,
21702IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 0x00000043,
21703IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 0x00000044,
21704IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 0x00000045,
21705IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 0x00000046,
21706IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 0x00000047,
21707IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 0x00000048,
21708IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 0x00000049,
21709IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 0x0000004a,
21710IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 0x0000004b,
21711IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 0x0000004c,
21712IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 0x0000004d,
21713IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 0x0000004e,
21714IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 0x0000004f,
21715IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 0x00000050,
21716IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 0x00000051,
21717IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 0x00000052,
21718IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 0x00000053,
21719IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 0x00000054,
21720IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 0x00000055,
21721IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 0x00000056,
21722IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 0x00000057,
21723IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 0x00000058,
21724IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 0x00000059,
21725IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 0x0000005a,
21726IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 0x0000005b,
21727IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 0x0000005c,
21728IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 0x0000005d,
21729IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 0x0000005e,
21730IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 0x0000005f,
21731IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 0x00000060,
21732IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 0x00000061,
21733IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 0x00000062,
21734IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 0x00000063,
21735IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 0x00000064,
21736IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 0x00000065,
21737IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 0x00000066,
21738IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 0x00000067,
21739IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 0x00000068,
21740IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 0x00000069,
21741IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 0x0000006a,
21742IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 0x0000006b,
21743IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 0x0000006c,
21744IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 0x0000006d,
21745IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 0x0000006e,
21746IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 0x0000006f,
21747IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 0x00000070,
21748IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 0x00000071,
21749IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 0x00000072,
21750IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 0x00000073,
21751IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 0x00000074,
21752IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 0x00000075,
21753IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 0x00000076,
21754IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 0x00000077,
21755IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 0x00000078,
21756IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 0x00000079,
21757IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 0x0000007a,
21758IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 0x0000007b,
21759IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 0x0000007c,
21760IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 0x0000007d,
21761IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 0x0000007e,
21762IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 0x0000007f,
21763IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 0x00000080,
21764IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 0x00000081,
21765IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 0x00000082,
21766IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 0x00000083,
21767IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 0x00000084,
21768IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 0x00000085,
21769IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 0x00000086,
21770IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 0x00000087,
21771IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 0x00000088,
21772IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 0x00000089,
21773IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 0x0000008a,
21774IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 0x0000008b,
21775IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 0x0000008c,
21776IH_PERF_SEL_CLIENT0_INT = 0x0000008d,
21777IH_PERF_SEL_CLIENT1_INT = 0x0000008e,
21778IH_PERF_SEL_CLIENT2_INT = 0x0000008f,
21779IH_PERF_SEL_CLIENT3_INT = 0x00000090,
21780IH_PERF_SEL_CLIENT4_INT = 0x00000091,
21781IH_PERF_SEL_CLIENT5_INT = 0x00000092,
21782IH_PERF_SEL_CLIENT6_INT = 0x00000093,
21783IH_PERF_SEL_CLIENT7_INT = 0x00000094,
21784IH_PERF_SEL_CLIENT8_INT = 0x00000095,
21785IH_PERF_SEL_CLIENT9_INT = 0x00000096,
21786IH_PERF_SEL_CLIENT10_INT = 0x00000097,
21787IH_PERF_SEL_CLIENT11_INT = 0x00000098,
21788IH_PERF_SEL_CLIENT12_INT = 0x00000099,
21789IH_PERF_SEL_CLIENT13_INT = 0x0000009a,
21790IH_PERF_SEL_CLIENT14_INT = 0x0000009b,
21791IH_PERF_SEL_CLIENT15_INT = 0x0000009c,
21792IH_PERF_SEL_CLIENT16_INT = 0x0000009d,
21793IH_PERF_SEL_CLIENT17_INT = 0x0000009e,
21794IH_PERF_SEL_CLIENT18_INT = 0x0000009f,
21795IH_PERF_SEL_CLIENT19_INT = 0x000000a0,
21796IH_PERF_SEL_CLIENT20_INT = 0x000000a1,
21797IH_PERF_SEL_CLIENT21_INT = 0x000000a2,
21798IH_PERF_SEL_CLIENT22_INT = 0x000000a3,
21799IH_PERF_SEL_CLIENT23_INT = 0x000000a4,
21800IH_PERF_SEL_CLIENT24_INT = 0x000000a5,
21801IH_PERF_SEL_CLIENT25_INT = 0x000000a6,
21802IH_PERF_SEL_CLIENT26_INT = 0x000000a7,
21803IH_PERF_SEL_CLIENT27_INT = 0x000000a8,
21804IH_PERF_SEL_CLIENT28_INT = 0x000000a9,
21805IH_PERF_SEL_CLIENT29_INT = 0x000000aa,
21806IH_PERF_SEL_CLIENT30_INT = 0x000000ab,
21807IH_PERF_SEL_CLIENT31_INT = 0x000000ac,
21808IH_PERF_SEL_RB1_FULL_VF0 = 0x000000ad,
21809IH_PERF_SEL_RB1_FULL_VF1 = 0x000000ae,
21810IH_PERF_SEL_RB1_FULL_VF2 = 0x000000af,
21811IH_PERF_SEL_RB1_FULL_VF3 = 0x000000b0,
21812IH_PERF_SEL_RB1_FULL_VF4 = 0x000000b1,
21813IH_PERF_SEL_RB1_FULL_VF5 = 0x000000b2,
21814IH_PERF_SEL_RB1_FULL_VF6 = 0x000000b3,
21815IH_PERF_SEL_RB1_FULL_VF7 = 0x000000b4,
21816IH_PERF_SEL_RB1_FULL_VF8 = 0x000000b5,
21817IH_PERF_SEL_RB1_FULL_VF9 = 0x000000b6,
21818IH_PERF_SEL_RB1_FULL_VF10 = 0x000000b7,
21819IH_PERF_SEL_RB1_FULL_VF11 = 0x000000b8,
21820IH_PERF_SEL_RB1_FULL_VF12 = 0x000000b9,
21821IH_PERF_SEL_RB1_FULL_VF13 = 0x000000ba,
21822IH_PERF_SEL_RB1_FULL_VF14 = 0x000000bb,
21823IH_PERF_SEL_RB1_FULL_VF15 = 0x000000bc,
21824IH_PERF_SEL_RB1_OVERFLOW_VF0 = 0x000000bd,
21825IH_PERF_SEL_RB1_OVERFLOW_VF1 = 0x000000be,
21826IH_PERF_SEL_RB1_OVERFLOW_VF2 = 0x000000bf,
21827IH_PERF_SEL_RB1_OVERFLOW_VF3 = 0x000000c0,
21828IH_PERF_SEL_RB1_OVERFLOW_VF4 = 0x000000c1,
21829IH_PERF_SEL_RB1_OVERFLOW_VF5 = 0x000000c2,
21830IH_PERF_SEL_RB1_OVERFLOW_VF6 = 0x000000c3,
21831IH_PERF_SEL_RB1_OVERFLOW_VF7 = 0x000000c4,
21832IH_PERF_SEL_RB1_OVERFLOW_VF8 = 0x000000c5,
21833IH_PERF_SEL_RB1_OVERFLOW_VF9 = 0x000000c6,
21834IH_PERF_SEL_RB1_OVERFLOW_VF10 = 0x000000c7,
21835IH_PERF_SEL_RB1_OVERFLOW_VF11 = 0x000000c8,
21836IH_PERF_SEL_RB1_OVERFLOW_VF12 = 0x000000c9,
21837IH_PERF_SEL_RB1_OVERFLOW_VF13 = 0x000000ca,
21838IH_PERF_SEL_RB1_OVERFLOW_VF14 = 0x000000cb,
21839IH_PERF_SEL_RB1_OVERFLOW_VF15 = 0x000000cc,
21840IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 0x000000cd,
21841IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 0x000000ce,
21842IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 0x000000cf,
21843IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 0x000000d0,
21844IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 0x000000d1,
21845IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 0x000000d2,
21846IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 0x000000d3,
21847IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 0x000000d4,
21848IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 0x000000d5,
21849IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 0x000000d6,
21850IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 0x000000d7,
21851IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 0x000000d8,
21852IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 0x000000d9,
21853IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 0x000000da,
21854IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 0x000000db,
21855IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 0x000000dc,
21856IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 0x000000dd,
21857IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 0x000000de,
21858IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 0x000000df,
21859IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 0x000000e0,
21860IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 0x000000e1,
21861IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 0x000000e2,
21862IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 0x000000e3,
21863IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 0x000000e4,
21864IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 0x000000e5,
21865IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 0x000000e6,
21866IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 0x000000e7,
21867IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 0x000000e8,
21868IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 0x000000e9,
21869IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 0x000000ea,
21870IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 0x000000eb,
21871IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 0x000000ec,
21872IH_PERF_SEL_RB2_FULL_VF0 = 0x000000ed,
21873IH_PERF_SEL_RB2_FULL_VF1 = 0x000000ee,
21874IH_PERF_SEL_RB2_FULL_VF2 = 0x000000ef,
21875IH_PERF_SEL_RB2_FULL_VF3 = 0x000000f0,
21876IH_PERF_SEL_RB2_FULL_VF4 = 0x000000f1,
21877IH_PERF_SEL_RB2_FULL_VF5 = 0x000000f2,
21878IH_PERF_SEL_RB2_FULL_VF6 = 0x000000f3,
21879IH_PERF_SEL_RB2_FULL_VF7 = 0x000000f4,
21880IH_PERF_SEL_RB2_FULL_VF8 = 0x000000f5,
21881IH_PERF_SEL_RB2_FULL_VF9 = 0x000000f6,
21882IH_PERF_SEL_RB2_FULL_VF10 = 0x000000f7,
21883IH_PERF_SEL_RB2_FULL_VF11 = 0x000000f8,
21884IH_PERF_SEL_RB2_FULL_VF12 = 0x000000f9,
21885IH_PERF_SEL_RB2_FULL_VF13 = 0x000000fa,
21886IH_PERF_SEL_RB2_FULL_VF14 = 0x000000fb,
21887IH_PERF_SEL_RB2_FULL_VF15 = 0x000000fc,
21888IH_PERF_SEL_RB2_OVERFLOW_VF0 = 0x000000fd,
21889IH_PERF_SEL_RB2_OVERFLOW_VF1 = 0x000000fe,
21890IH_PERF_SEL_RB2_OVERFLOW_VF2 = 0x000000ff,
21891IH_PERF_SEL_RB2_OVERFLOW_VF3 = 0x00000100,
21892IH_PERF_SEL_RB2_OVERFLOW_VF4 = 0x00000101,
21893IH_PERF_SEL_RB2_OVERFLOW_VF5 = 0x00000102,
21894IH_PERF_SEL_RB2_OVERFLOW_VF6 = 0x00000103,
21895IH_PERF_SEL_RB2_OVERFLOW_VF7 = 0x00000104,
21896IH_PERF_SEL_RB2_OVERFLOW_VF8 = 0x00000105,
21897IH_PERF_SEL_RB2_OVERFLOW_VF9 = 0x00000106,
21898IH_PERF_SEL_RB2_OVERFLOW_VF10 = 0x00000107,
21899IH_PERF_SEL_RB2_OVERFLOW_VF11 = 0x00000108,
21900IH_PERF_SEL_RB2_OVERFLOW_VF12 = 0x00000109,
21901IH_PERF_SEL_RB2_OVERFLOW_VF13 = 0x0000010a,
21902IH_PERF_SEL_RB2_OVERFLOW_VF14 = 0x0000010b,
21903IH_PERF_SEL_RB2_OVERFLOW_VF15 = 0x0000010c,
21904IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 0x0000010d,
21905IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 0x0000010e,
21906IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 0x0000010f,
21907IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 0x00000110,
21908IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 0x00000111,
21909IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 0x00000112,
21910IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 0x00000113,
21911IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 0x00000114,
21912IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 0x00000115,
21913IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 0x00000116,
21914IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 0x00000117,
21915IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 0x00000118,
21916IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 0x00000119,
21917IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 0x0000011a,
21918IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 0x0000011b,
21919IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 0x0000011c,
21920IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 0x0000011d,
21921IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 0x0000011e,
21922IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 0x0000011f,
21923IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 0x00000120,
21924IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 0x00000121,
21925IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 0x00000122,
21926IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 0x00000123,
21927IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 0x00000124,
21928IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 0x00000125,
21929IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 0x00000126,
21930IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 0x00000127,
21931IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 0x00000128,
21932IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 0x00000129,
21933IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 0x0000012a,
21934IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 0x0000012b,
21935IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 0x0000012c,
21936IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 0x0000012d,
21937IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 0x0000012e,
21938IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 0x0000012f,
21939IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 0x00000130,
21940IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 0x00000131,
21941IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 0x00000132,
21942IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 0x00000133,
21943IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 0x00000134,
21944IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 0x00000135,
21945IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 0x00000136,
21946IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 0x00000137,
21947IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 0x00000138,
21948IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 0x00000139,
21949IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 0x0000013a,
21950IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 0x0000013b,
21951IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 0x0000013c,
21952IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 0x0000013d,
21953IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 0x0000013e,
21954IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 0x0000013f,
21955IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 0x00000140,
21956IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 0x00000141,
21957IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 0x00000142,
21958IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 0x00000143,
21959IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 0x00000144,
21960IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 0x00000145,
21961IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 0x00000146,
21962IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 0x00000147,
21963IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 0x00000148,
21964IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 0x00000149,
21965IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 0x0000014a,
21966IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 0x0000014b,
21967IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 0x0000014c,
21968IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 0x0000014d,
21969IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 0x0000014e,
21970IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 0x0000014f,
21971IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 0x00000150,
21972IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 0x00000151,
21973IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 0x00000152,
21974IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 0x00000153,
21975IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 0x00000154,
21976IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 0x00000155,
21977IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 0x00000156,
21978IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 0x00000157,
21979IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 0x00000158,
21980IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 0x00000159,
21981IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 0x0000015a,
21982IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 0x0000015b,
21983IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 0x0000015c,
21984IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 0x0000015d,
21985IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 0x0000015e,
21986IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 0x0000015f,
21987IH_PERF_SEL_RB0_LOAD_RPTR = 0x00000160,
21988IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 0x00000161,
21989IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 0x00000162,
21990IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 0x00000163,
21991IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 0x00000164,
21992IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 0x00000165,
21993IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 0x00000166,
21994IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 0x00000167,
21995IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 0x00000168,
21996IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 0x00000169,
21997IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 0x0000016a,
21998IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 0x0000016b,
21999IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 0x0000016c,
22000IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 0x0000016d,
22001IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 0x0000016e,
22002IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 0x0000016f,
22003IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 0x00000170,
22004IH_PERF_SEL_RB1_LOAD_RPTR = 0x00000171,
22005IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 0x00000172,
22006IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 0x00000173,
22007IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 0x00000174,
22008IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 0x00000175,
22009IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 0x00000176,
22010IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 0x00000177,
22011IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 0x00000178,
22012IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 0x00000179,
22013IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 0x0000017a,
22014IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 0x0000017b,
22015IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 0x0000017c,
22016IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 0x0000017d,
22017IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 0x0000017e,
22018IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 0x0000017f,
22019IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 0x00000180,
22020IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 0x00000181,
22021IH_PERF_SEL_RB2_LOAD_RPTR = 0x00000182,
22022IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 0x00000183,
22023IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 0x00000184,
22024IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 0x00000185,
22025IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 0x00000186,
22026IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 0x00000187,
22027IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 0x00000188,
22028IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 0x00000189,
22029IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 0x0000018a,
22030IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 0x0000018b,
22031IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 0x0000018c,
22032IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 0x0000018d,
22033IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 0x0000018e,
22034IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 0x0000018f,
22035IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 0x00000190,
22036IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 0x00000191,
22037IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 0x00000192,
22038} IH_PERF_SEL;
22039
22040/*
22041 * IH_RING_ID enum
22042 */
22043
22044typedef enum IH_RING_ID {
22045IH_RING_ID_INTERRUPT = 0x00000000,
22046IH_RING_ID_REQUEST = 0x00000001,
22047IH_RING_ID_TRANSLATION = 0x00000002,
22048IH_RING_ID_RESERVED = 0x00000003,
22049} IH_RING_ID;
22050
22051/*
22052 * IH_VF_RB_SELECT enum
22053 */
22054
22055typedef enum IH_VF_RB_SELECT {
22056IH_VF_RB_SELECT_CLIENT_FCN_ID = 0x00000000,
22057IH_VF_RB_SELECT_IH_FCN_ID = 0x00000001,
22058IH_VF_RB_SELECT_PF = 0x00000002,
22059IH_VF_RB_SELECT_RESERVED = 0x00000003,
22060} IH_VF_RB_SELECT;
22061
22062/*******************************************************
22063 * SEM Enums
22064 *******************************************************/
22065
22066/*
22067 * SEM_PERF_SEL enum
22068 */
22069
22070typedef enum SEM_PERF_SEL {
22071SEM_PERF_SEL_CYCLE = 0x00000000,
22072SEM_PERF_SEL_IDLE = 0x00000001,
22073SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x00000002,
22074SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x00000003,
22075SEM_PERF_SEL_SDMA2_REQ_SIGNAL = 0x00000004,
22076SEM_PERF_SEL_SDMA3_REQ_SIGNAL = 0x00000005,
22077SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x00000006,
22078SEM_PERF_SEL_UVD1_REQ_SIGNAL = 0x00000007,
22079SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x00000008,
22080SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x00000009,
22081SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x0000000a,
22082SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x0000000b,
22083SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x0000000c,
22084SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0x0000000d,
22085SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0x0000000e,
22086SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0x0000000f,
22087SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0x00000010,
22088SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0x00000011,
22089SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0x00000012,
22090SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x00000013,
22091SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x00000014,
22092SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x00000015,
22093SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x00000016,
22094SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x00000017,
22095SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x00000018,
22096SEM_PERF_SEL_SDMA2_REQ_WAIT = 0x00000019,
22097SEM_PERF_SEL_SDMA3_REQ_WAIT = 0x0000001a,
22098SEM_PERF_SEL_UVD_REQ_WAIT = 0x0000001b,
22099SEM_PERF_SEL_UVD1_REQ_WAIT = 0x0000001c,
22100SEM_PERF_SEL_VCE0_REQ_WAIT = 0x0000001d,
22101SEM_PERF_SEL_ACP_REQ_WAIT = 0x0000001e,
22102SEM_PERF_SEL_ISP_REQ_WAIT = 0x0000001f,
22103SEM_PERF_SEL_VCE1_REQ_WAIT = 0x00000020,
22104SEM_PERF_SEL_VP8_REQ_WAIT = 0x00000021,
22105SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x00000022,
22106SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x00000023,
22107SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x00000024,
22108SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x00000025,
22109SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x00000026,
22110SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x00000027,
22111SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x00000028,
22112SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x00000029,
22113SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x0000002a,
22114SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x0000002b,
22115SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x0000002c,
22116SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x0000002d,
22117SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x0000002e,
22118SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x0000002f,
22119SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x00000030,
22120SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x00000031,
22121SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x00000032,
22122SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x00000033,
22123SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x00000034,
22124SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x00000035,
22125SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x00000036,
22126SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x00000037,
22127SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x00000038,
22128SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x00000039,
22129SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x0000003a,
22130SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x0000003b,
22131SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x0000003c,
22132SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x0000003d,
22133SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x0000003e,
22134SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x0000003f,
22135SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x00000040,
22136SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x00000041,
22137SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x00000042,
22138SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x00000043,
22139SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x00000044,
22140SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x00000045,
22141SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x00000046,
22142SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x00000047,
22143SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x00000048,
22144SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x00000049,
22145SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x0000004a,
22146SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x0000004b,
22147SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x0000004c,
22148SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x0000004d,
22149SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x0000004e,
22150SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x0000004f,
22151SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x00000050,
22152SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x00000051,
22153SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x00000052,
22154SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x00000053,
22155SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x00000054,
22156SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x00000055,
22157SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x00000056,
22158SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x00000057,
22159SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x00000058,
22160SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x00000059,
22161SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x0000005a,
22162SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x0000005b,
22163SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x0000005c,
22164SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x0000005d,
22165SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x0000005e,
22166SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x0000005f,
22167SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x00000060,
22168SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x00000061,
22169SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x00000062,
22170SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x00000063,
22171SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x00000064,
22172SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x00000065,
22173SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x00000066,
22174SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x00000067,
22175SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x00000068,
22176SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x00000069,
22177SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x0000006a,
22178SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x0000006b,
22179SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x0000006c,
22180SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x0000006d,
22181SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x0000006e,
22182SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x0000006f,
22183SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x00000070,
22184SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x00000071,
22185SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x00000072,
22186SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x00000073,
22187SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x00000074,
22188SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x00000075,
22189SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x00000076,
22190SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x00000077,
22191SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x00000078,
22192SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x00000079,
22193SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x0000007a,
22194SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x0000007b,
22195SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x0000007c,
22196SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x0000007d,
22197SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x0000007e,
22198SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x0000007f,
22199SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x00000080,
22200SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x00000081,
22201SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x00000082,
22202SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x00000083,
22203SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x00000084,
22204SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x00000085,
22205SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x00000086,
22206SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x00000087,
22207SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x00000088,
22208SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x00000089,
22209SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x0000008a,
22210SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x0000008b,
22211SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x0000008c,
22212SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x0000008d,
22213SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x0000008e,
22214SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x0000008f,
22215SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x00000090,
22216SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x00000091,
22217SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x00000092,
22218SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x00000093,
22219SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x00000094,
22220SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x00000095,
22221SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x00000096,
22222SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x00000097,
22223SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x00000098,
22224SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x00000099,
22225SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x0000009a,
22226SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x0000009b,
22227SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x0000009c,
22228SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x0000009d,
22229SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x0000009e,
22230SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x0000009f,
22231SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x000000a0,
22232SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x000000a1,
22233SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x000000a2,
22234SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x000000a3,
22235SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x000000a4,
22236SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x000000a5,
22237SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0x000000a6,
22238SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0x000000a7,
22239SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0x000000a8,
22240SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0x000000a9,
22241SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0x000000aa,
22242SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0x000000ab,
22243SEM_PERF_SEL_MC_RD_REQ = 0x000000ac,
22244SEM_PERF_SEL_MC_RD_RET = 0x000000ad,
22245SEM_PERF_SEL_MC_WR_REQ = 0x000000ae,
22246SEM_PERF_SEL_MC_WR_RET = 0x000000af,
22247SEM_PERF_SEL_ATC_REQ = 0x000000b0,
22248SEM_PERF_SEL_ATC_RET = 0x000000b1,
22249SEM_PERF_SEL_ATC_XNACK = 0x000000b2,
22250SEM_PERF_SEL_ATC_INVALIDATION = 0x000000b3,
22251SEM_PERF_SEL_ATC_VM_INVALIDATION = 0x000000b4,
22252} SEM_PERF_SEL;
22253
22254/*******************************************************
22255 * LSDMA Enums
22256 *******************************************************/
22257
22258/*
22259 * LSDMA_PERF_SEL enum
22260 */
22261
22262typedef enum LSDMA_PERF_SEL {
22263LSDMA_PERF_SEL_CYCLE = 0x00000000,
22264LSDMA_PERF_SEL_IDLE = 0x00000001,
22265LSDMA_PERF_SEL_REG_IDLE = 0x00000002,
22266LSDMA_PERF_SEL_RB_EMPTY = 0x00000003,
22267LSDMA_PERF_SEL_RB_FULL = 0x00000004,
22268LSDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005,
22269LSDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006,
22270LSDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007,
22271LSDMA_PERF_SEL_RB_RPTR_WB = 0x00000008,
22272LSDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009,
22273LSDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a,
22274LSDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b,
22275LSDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c,
22276LSDMA_PERF_SEL_EX_IDLE = 0x0000000d,
22277LSDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e,
22278LSDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
22279LSDMA_PERF_SEL_MC_WR_IDLE = 0x00000010,
22280LSDMA_PERF_SEL_MC_WR_COUNT = 0x00000011,
22281LSDMA_PERF_SEL_MC_RD_IDLE = 0x00000012,
22282LSDMA_PERF_SEL_MC_RD_COUNT = 0x00000013,
22283LSDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014,
22284LSDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015,
22285LSDMA_PERF_SEL_SEM_IDLE = 0x00000018,
22286LSDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019,
22287LSDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a,
22288LSDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b,
22289LSDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c,
22290LSDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d,
22291LSDMA_PERF_SEL_INT_IDLE = 0x0000001e,
22292LSDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f,
22293LSDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020,
22294LSDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021,
22295LSDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022,
22296LSDMA_PERF_SEL_NUM_PACKET = 0x00000023,
22297LSDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025,
22298LSDMA_PERF_SEL_CE_WR_IDLE = 0x00000026,
22299LSDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027,
22300LSDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028,
22301LSDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029,
22302LSDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a,
22303LSDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b,
22304LSDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e,
22305LSDMA_PERF_SEL_CE_INFO_FULL = 0x00000031,
22306LSDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032,
22307LSDMA_PERF_SEL_CE_RD_STALL = 0x00000033,
22308LSDMA_PERF_SEL_CE_WR_STALL = 0x00000034,
22309LSDMA_PERF_SEL_GFX_SELECT = 0x00000035,
22310LSDMA_PERF_SEL_RLC0_SELECT = 0x00000036,
22311LSDMA_PERF_SEL_RLC1_SELECT = 0x00000037,
22312LSDMA_PERF_SEL_PAGE_SELECT = 0x00000038,
22313LSDMA_PERF_SEL_CTX_CHANGE = 0x00000039,
22314LSDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a,
22315LSDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b,
22316LSDMA_PERF_SEL_DOORBELL = 0x0000003c,
22317LSDMA_PERF_SEL_RD_BA_RTR = 0x0000003d,
22318LSDMA_PERF_SEL_WR_BA_RTR = 0x0000003e,
22319LSDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f,
22320LSDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040,
22321LSDMA_PERF_SEL_CE_L1_STALL = 0x00000041,
22322LSDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x00000042,
22323LSDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x00000043,
22324LSDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x00000044,
22325LSDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x00000045,
22326LSDMA_PERF_SEL_ATCL2_RET_XNACK = 0x00000046,
22327LSDMA_PERF_SEL_ATCL2_RET_ACK = 0x00000047,
22328LSDMA_PERF_SEL_ATCL2_FREE = 0x00000048,
22329LSDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x00000049,
22330LSDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004a,
22331LSDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004b,
22332LSDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004c,
22333LSDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004d,
22334LSDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x0000004e,
22335LSDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x0000004f,
22336LSDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000050,
22337LSDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000051,
22338LSDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000052,
22339LSDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000053,
22340LSDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000054,
22341LSDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000055,
22342LSDMA_PERF_SEL_L1_WR_INV_EN = 0x00000056,
22343LSDMA_PERF_SEL_L1_RD_INV_EN = 0x00000057,
22344LSDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x00000058,
22345LSDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x00000059,
22346LSDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x0000005a,
22347LSDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x0000005b,
22348LSDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x0000005c,
22349LSDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x0000005d,
22350LSDMA_PERF_SEL_L1_INV_MIDDLE = 0x0000005e,
22351LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_REQ = 0x0000005f,
22352LSDMA_PERF_SEL_CE_OR_F32_MMHUB_WR_RET = 0x00000060,
22353LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_REQ = 0x00000061,
22354LSDMA_PERF_SEL_ATOMIC_MMHUB_WR_RET = 0x00000062,
22355LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_REQ = 0x00000063,
22356LSDMA_PERF_SEL_CE_OR_F32_MMHUB_RD_RET = 0x00000064,
22357LSDMA_PERF_SEL_RB_MMHUB_RD_REQ = 0x00000065,
22358LSDMA_PERF_SEL_RB_MMHUB_RD_RET = 0x00000066,
22359LSDMA_PERF_SEL_IB_MMHUB_RD_REQ = 0x00000067,
22360LSDMA_PERF_SEL_IB_MMHUB_RD_RET = 0x00000068,
22361LSDMA_PERF_SEL_WPTR_MMHUB_RD_REQ = 0x00000069,
22362LSDMA_PERF_SEL_WPTR_MMHUB_RD_RET = 0x0000006a,
22363LSDMA_PERF_SEL_UTCL1_UTCL2_REQ = 0x0000006b,
22364LSDMA_PERF_SEL_UTCL1_UTCL2_RET = 0x0000006c,
22365LSDMA_PERF_SEL_CMD_OP_MATCH = 0x0000006d,
22366LSDMA_PERF_SEL_CMD_OP_START = 0x0000006e,
22367LSDMA_PERF_SEL_CMD_OP_END = 0x0000006f,
22368LSDMA_PERF_SEL_CE_BUSY = 0x00000070,
22369LSDMA_PERF_SEL_CE_BUSY_START = 0x00000071,
22370LSDMA_PERF_SEL_CE_BUSY_END = 0x00000072,
22371LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 0x00000073,
22372LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 0x00000074,
22373LSDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 0x00000075,
22374LSDMA_PERF_SEL_CE_MMHUB_WRREQ_SEND = 0x00000076,
22375LSDMA_PERF_SEL_MMHUB_CE_WRRET_VALID = 0x00000077,
22376LSDMA_PERF_SEL_CE_MMHUB_RDREQ_SEND = 0x00000078,
22377LSDMA_PERF_SEL_MMHUB_CE_RDRET_VALID = 0x00000079,
22378LSDMA_PERF_SEL_DRAM_ECC = 0x0000007a,
22379LSDMA_PERF_SEL_NACK_GEN_ERR = 0x0000007b,
22380} LSDMA_PERF_SEL;
22381
22382/*******************************************************
22383 * SMUIO_ROM Enums
22384 *******************************************************/
22385
22386/*
22387 * ROM_SIGNATURE value
22388 */
22389
22390#define ROM_SIGNATURE 0x0000aa55
22391
22392/*******************************************************
22393 * UVD_EFC Enums
22394 *******************************************************/
22395
22396/*
22397 * EFC_SURFACE_PIXEL_FORMAT enum
22398 */
22399
22400typedef enum EFC_SURFACE_PIXEL_FORMAT {
22401EFC_ARGB1555 = 0x00000001,
22402EFC_RGBA5551 = 0x00000002,
22403EFC_RGB565 = 0x00000003,
22404EFC_BGR565 = 0x00000004,
22405EFC_ARGB4444 = 0x00000005,
22406EFC_RGBA4444 = 0x00000006,
22407EFC_ARGB8888 = 0x00000008,
22408EFC_RGBA8888 = 0x00000009,
22409EFC_ARGB2101010 = 0x0000000a,
22410EFC_RGBA1010102 = 0x0000000b,
22411EFC_AYCrCb8888 = 0x0000000c,
22412EFC_YCrCbA8888 = 0x0000000d,
22413EFC_ACrYCb8888 = 0x0000000e,
22414EFC_CrYCbA8888 = 0x0000000f,
22415EFC_ARGB16161616_10MSB = 0x00000010,
22416EFC_RGBA16161616_10MSB = 0x00000011,
22417EFC_ARGB16161616_10LSB = 0x00000012,
22418EFC_RGBA16161616_10LSB = 0x00000013,
22419EFC_ARGB16161616_12MSB = 0x00000014,
22420EFC_RGBA16161616_12MSB = 0x00000015,
22421EFC_ARGB16161616_12LSB = 0x00000016,
22422EFC_RGBA16161616_12LSB = 0x00000017,
22423EFC_ARGB16161616_FLOAT = 0x00000018,
22424EFC_RGBA16161616_FLOAT = 0x00000019,
22425EFC_ARGB16161616_UNORM = 0x0000001a,
22426EFC_RGBA16161616_UNORM = 0x0000001b,
22427EFC_ARGB16161616_SNORM = 0x0000001c,
22428EFC_RGBA16161616_SNORM = 0x0000001d,
22429EFC_AYCrCb16161616_10MSB = 0x00000020,
22430EFC_AYCrCb16161616_10LSB = 0x00000021,
22431EFC_YCrCbA16161616_10MSB = 0x00000022,
22432EFC_YCrCbA16161616_10LSB = 0x00000023,
22433EFC_ACrYCb16161616_10MSB = 0x00000024,
22434EFC_ACrYCb16161616_10LSB = 0x00000025,
22435EFC_CrYCbA16161616_10MSB = 0x00000026,
22436EFC_CrYCbA16161616_10LSB = 0x00000027,
22437EFC_AYCrCb16161616_12MSB = 0x00000028,
22438EFC_AYCrCb16161616_12LSB = 0x00000029,
22439EFC_YCrCbA16161616_12MSB = 0x0000002a,
22440EFC_YCrCbA16161616_12LSB = 0x0000002b,
22441EFC_ACrYCb16161616_12MSB = 0x0000002c,
22442EFC_ACrYCb16161616_12LSB = 0x0000002d,
22443EFC_CrYCbA16161616_12MSB = 0x0000002e,
22444EFC_CrYCbA16161616_12LSB = 0x0000002f,
22445EFC_Y8_CrCb88_420_PLANAR = 0x00000040,
22446EFC_Y8_CbCr88_420_PLANAR = 0x00000041,
22447EFC_Y10_CrCb1010_420_PLANAR = 0x00000042,
22448EFC_Y10_CbCr1010_420_PLANAR = 0x00000043,
22449EFC_Y12_CrCb1212_420_PLANAR = 0x00000044,
22450EFC_Y12_CbCr1212_420_PLANAR = 0x00000045,
22451EFC_YCrYCb8888_422_PACKED = 0x00000048,
22452EFC_YCbYCr8888_422_PACKED = 0x00000049,
22453EFC_CrYCbY8888_422_PACKED = 0x0000004a,
22454EFC_CbYCrY8888_422_PACKED = 0x0000004b,
22455EFC_YCrYCb10101010_422_PACKED = 0x0000004c,
22456EFC_YCbYCr10101010_422_PACKED = 0x0000004d,
22457EFC_CrYCbY10101010_422_PACKED = 0x0000004e,
22458EFC_CbYCrY10101010_422_PACKED = 0x0000004f,
22459EFC_YCrYCb12121212_422_PACKED = 0x00000050,
22460EFC_YCbYCr12121212_422_PACKED = 0x00000051,
22461EFC_CrYCbY12121212_422_PACKED = 0x00000052,
22462EFC_CbYCrY12121212_422_PACKED = 0x00000053,
22463EFC_RGB111110_FIX = 0x00000070,
22464EFC_BGR101111_FIX = 0x00000071,
22465EFC_ACrYCb2101010 = 0x00000072,
22466EFC_CrYCbA1010102 = 0x00000073,
22467EFC_RGB111110_FLOAT = 0x00000076,
22468EFC_BGR101111_FLOAT = 0x00000077,
22469EFC_MONO_8 = 0x00000078,
22470EFC_MONO_10MSB = 0x00000079,
22471EFC_MONO_10LSB = 0x0000007a,
22472EFC_MONO_12MSB = 0x0000007b,
22473EFC_MONO_12LSB = 0x0000007c,
22474EFC_MONO_16 = 0x0000007d,
22475} EFC_SURFACE_PIXEL_FORMAT;
22476
22477#endif /*_soc21_ENUM_HEADER*/