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1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 * Authors: Christian König <christian.koenig@amd.com>
26 */
27
28#include <linux/firmware.h>
29
30#include "amdgpu.h"
31#include "amdgpu_vce.h"
32#include "cikd.h"
33#include "vce/vce_2_0_d.h"
34#include "vce/vce_2_0_sh_mask.h"
35#include "smu/smu_7_0_1_d.h"
36#include "smu/smu_7_0_1_sh_mask.h"
37#include "oss/oss_2_0_d.h"
38#include "oss/oss_2_0_sh_mask.h"
39
40#define VCE_V2_0_FW_SIZE (256 * 1024)
41#define VCE_V2_0_STACK_SIZE (64 * 1024)
42#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES)
43#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
44
45static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
46static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
47
48/**
49 * vce_v2_0_ring_get_rptr - get read pointer
50 *
51 * @ring: amdgpu_ring pointer
52 *
53 * Returns the current hardware read pointer
54 */
55static uint64_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
56{
57 struct amdgpu_device *adev = ring->adev;
58
59 if (ring->me == 0)
60 return RREG32(mmVCE_RB_RPTR);
61 else
62 return RREG32(mmVCE_RB_RPTR2);
63}
64
65/**
66 * vce_v2_0_ring_get_wptr - get write pointer
67 *
68 * @ring: amdgpu_ring pointer
69 *
70 * Returns the current hardware write pointer
71 */
72static uint64_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
73{
74 struct amdgpu_device *adev = ring->adev;
75
76 if (ring->me == 0)
77 return RREG32(mmVCE_RB_WPTR);
78 else
79 return RREG32(mmVCE_RB_WPTR2);
80}
81
82/**
83 * vce_v2_0_ring_set_wptr - set write pointer
84 *
85 * @ring: amdgpu_ring pointer
86 *
87 * Commits the write pointer to the hardware
88 */
89static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
90{
91 struct amdgpu_device *adev = ring->adev;
92
93 if (ring->me == 0)
94 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
95 else
96 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
97}
98
99static int vce_v2_0_lmi_clean(struct amdgpu_device *adev)
100{
101 int i, j;
102
103 for (i = 0; i < 10; ++i) {
104 for (j = 0; j < 100; ++j) {
105 uint32_t status = RREG32(mmVCE_LMI_STATUS);
106
107 if (status & 0x337f)
108 return 0;
109 mdelay(10);
110 }
111 }
112
113 return -ETIMEDOUT;
114}
115
116static int vce_v2_0_firmware_loaded(struct amdgpu_device *adev)
117{
118 int i, j;
119
120 for (i = 0; i < 10; ++i) {
121 for (j = 0; j < 100; ++j) {
122 uint32_t status = RREG32(mmVCE_STATUS);
123
124 if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
125 return 0;
126 mdelay(10);
127 }
128
129 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
130 WREG32_P(mmVCE_SOFT_RESET,
131 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
132 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
133 mdelay(10);
134 WREG32_P(mmVCE_SOFT_RESET, 0,
135 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
136 mdelay(10);
137 }
138
139 return -ETIMEDOUT;
140}
141
142static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
143{
144 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
145}
146
147static void vce_v2_0_init_cg(struct amdgpu_device *adev)
148{
149 u32 tmp;
150
151 tmp = RREG32(mmVCE_CLOCK_GATING_A);
152 tmp &= ~0xfff;
153 tmp |= ((0 << 0) | (4 << 4));
154 tmp |= 0x40000;
155 WREG32(mmVCE_CLOCK_GATING_A, tmp);
156
157 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
158 tmp &= ~0xfff;
159 tmp |= ((0 << 0) | (4 << 4));
160 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
161
162 tmp = RREG32(mmVCE_CLOCK_GATING_B);
163 tmp |= 0x10;
164 tmp &= ~0x100000;
165 WREG32(mmVCE_CLOCK_GATING_B, tmp);
166}
167
168static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
169{
170 uint32_t size, offset;
171
172 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
173 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
174 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
175 WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
176
177 WREG32(mmVCE_LMI_CTRL, 0x00398000);
178 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
179 WREG32(mmVCE_LMI_SWAP_CNTL, 0);
180 WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
181 WREG32(mmVCE_LMI_VM_CTRL, 0);
182
183 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
184
185 offset = AMDGPU_VCE_FIRMWARE_OFFSET;
186 size = VCE_V2_0_FW_SIZE;
187 WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
188 WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
189
190 offset += size;
191 size = VCE_V2_0_STACK_SIZE;
192 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
193 WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
194
195 offset += size;
196 size = VCE_V2_0_DATA_SIZE;
197 WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);
198 WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
199
200 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
201 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1);
202}
203
204static bool vce_v2_0_is_idle(void *handle)
205{
206 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
207
208 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
209}
210
211static int vce_v2_0_wait_for_idle(void *handle)
212{
213 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
214 unsigned i;
215
216 for (i = 0; i < adev->usec_timeout; i++) {
217 if (vce_v2_0_is_idle(handle))
218 return 0;
219 }
220 return -ETIMEDOUT;
221}
222
223/**
224 * vce_v2_0_start - start VCE block
225 *
226 * @adev: amdgpu_device pointer
227 *
228 * Setup and start the VCE block
229 */
230static int vce_v2_0_start(struct amdgpu_device *adev)
231{
232 struct amdgpu_ring *ring;
233 int r;
234
235 /* set BUSY flag */
236 WREG32_P(mmVCE_STATUS, 1, ~1);
237
238 vce_v2_0_init_cg(adev);
239 vce_v2_0_disable_cg(adev);
240
241 vce_v2_0_mc_resume(adev);
242
243 ring = &adev->vce.ring[0];
244 WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
245 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
246 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
247 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
248 WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
249
250 ring = &adev->vce.ring[1];
251 WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
252 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
253 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
254 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
255 WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
256
257 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1);
258 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
259 mdelay(100);
260 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0);
261
262 r = vce_v2_0_firmware_loaded(adev);
263
264 /* clear BUSY flag */
265 WREG32_P(mmVCE_STATUS, 0, ~1);
266
267 if (r) {
268 DRM_ERROR("VCE not responding, giving up!!!\n");
269 return r;
270 }
271
272 return 0;
273}
274
275static int vce_v2_0_stop(struct amdgpu_device *adev)
276{
277 int i;
278 int status;
279
280 if (vce_v2_0_lmi_clean(adev)) {
281 DRM_INFO("vce is not idle \n");
282 return 0;
283 }
284
285 if (vce_v2_0_wait_for_idle(adev)) {
286 DRM_INFO("VCE is busy, Can't set clock gating");
287 return 0;
288 }
289
290 /* Stall UMC and register bus before resetting VCPU */
291 WREG32_P(mmVCE_LMI_CTRL2, 1 << 8, ~(1 << 8));
292
293 for (i = 0; i < 100; ++i) {
294 status = RREG32(mmVCE_LMI_STATUS);
295 if (status & 0x240)
296 break;
297 mdelay(1);
298 }
299
300 WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x80001);
301
302 /* put LMI, VCPU, RBC etc... into reset */
303 WREG32_P(mmVCE_SOFT_RESET, 1, ~0x1);
304
305 WREG32(mmVCE_STATUS, 0);
306
307 return 0;
308}
309
310static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
311{
312 u32 tmp;
313
314 if (gated) {
315 tmp = RREG32(mmVCE_CLOCK_GATING_B);
316 tmp |= 0xe70000;
317 WREG32(mmVCE_CLOCK_GATING_B, tmp);
318
319 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
320 tmp |= 0xff000000;
321 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
322
323 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
324 tmp &= ~0x3fc;
325 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
326
327 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
328 } else {
329 tmp = RREG32(mmVCE_CLOCK_GATING_B);
330 tmp |= 0xe7;
331 tmp &= ~0xe70000;
332 WREG32(mmVCE_CLOCK_GATING_B, tmp);
333
334 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
335 tmp |= 0x1fe000;
336 tmp &= ~0xff000000;
337 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
338
339 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
340 tmp |= 0x3fc;
341 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
342 }
343}
344
345static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
346{
347 u32 orig, tmp;
348
349/* LMI_MC/LMI_UMC always set in dynamic,
350 * set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {0, 0}
351 */
352 tmp = RREG32(mmVCE_CLOCK_GATING_B);
353 tmp &= ~0x00060006;
354
355/* Exception for ECPU, IH, SEM, SYS blocks needs to be turned on/off by SW */
356 if (gated) {
357 tmp |= 0xe10000;
358 WREG32(mmVCE_CLOCK_GATING_B, tmp);
359 } else {
360 tmp |= 0xe1;
361 tmp &= ~0xe10000;
362 WREG32(mmVCE_CLOCK_GATING_B, tmp);
363 }
364
365 orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
366 tmp &= ~0x1fe000;
367 tmp &= ~0xff000000;
368 if (tmp != orig)
369 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
370
371 orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
372 tmp &= ~0x3fc;
373 if (tmp != orig)
374 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
375
376 /* set VCE_UENC_REG_CLOCK_GATING always in dynamic mode */
377 WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
378
379 if(gated)
380 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
381}
382
383static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable,
384 bool sw_cg)
385{
386 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
387 if (sw_cg)
388 vce_v2_0_set_sw_cg(adev, true);
389 else
390 vce_v2_0_set_dyn_cg(adev, true);
391 } else {
392 vce_v2_0_disable_cg(adev);
393
394 if (sw_cg)
395 vce_v2_0_set_sw_cg(adev, false);
396 else
397 vce_v2_0_set_dyn_cg(adev, false);
398 }
399}
400
401static int vce_v2_0_early_init(void *handle)
402{
403 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
404
405 adev->vce.num_rings = 2;
406
407 vce_v2_0_set_ring_funcs(adev);
408 vce_v2_0_set_irq_funcs(adev);
409
410 return 0;
411}
412
413static int vce_v2_0_sw_init(void *handle)
414{
415 struct amdgpu_ring *ring;
416 int r, i;
417 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
418
419 /* VCE */
420 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq);
421 if (r)
422 return r;
423
424 r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE +
425 VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE);
426 if (r)
427 return r;
428
429 r = amdgpu_vce_resume(adev);
430 if (r)
431 return r;
432
433 for (i = 0; i < adev->vce.num_rings; i++) {
434 enum amdgpu_ring_priority_level hw_prio = amdgpu_vce_get_ring_prio(i);
435
436 ring = &adev->vce.ring[i];
437 sprintf(ring->name, "vce%d", i);
438 r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0,
439 hw_prio, NULL);
440 if (r)
441 return r;
442 }
443
444 return r;
445}
446
447static int vce_v2_0_sw_fini(void *handle)
448{
449 int r;
450 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
451
452 r = amdgpu_vce_suspend(adev);
453 if (r)
454 return r;
455
456 return amdgpu_vce_sw_fini(adev);
457}
458
459static int vce_v2_0_hw_init(void *handle)
460{
461 int r, i;
462 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
463
464 amdgpu_asic_set_vce_clocks(adev, 10000, 10000);
465 vce_v2_0_enable_mgcg(adev, true, false);
466
467 for (i = 0; i < adev->vce.num_rings; i++) {
468 r = amdgpu_ring_test_helper(&adev->vce.ring[i]);
469 if (r)
470 return r;
471 }
472
473 DRM_INFO("VCE initialized successfully.\n");
474
475 return 0;
476}
477
478static int vce_v2_0_hw_fini(void *handle)
479{
480 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
481
482 cancel_delayed_work_sync(&adev->vce.idle_work);
483
484 return 0;
485}
486
487static int vce_v2_0_suspend(void *handle)
488{
489 int r;
490 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
491
492
493 /*
494 * Proper cleanups before halting the HW engine:
495 * - cancel the delayed idle work
496 * - enable powergating
497 * - enable clockgating
498 * - disable dpm
499 *
500 * TODO: to align with the VCN implementation, move the
501 * jobs for clockgating/powergating/dpm setting to
502 * ->set_powergating_state().
503 */
504 cancel_delayed_work_sync(&adev->vce.idle_work);
505
506 if (adev->pm.dpm_enabled) {
507 amdgpu_dpm_enable_vce(adev, false);
508 } else {
509 amdgpu_asic_set_vce_clocks(adev, 0, 0);
510 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
511 AMD_PG_STATE_GATE);
512 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
513 AMD_CG_STATE_GATE);
514 }
515
516 r = vce_v2_0_hw_fini(adev);
517 if (r)
518 return r;
519
520 return amdgpu_vce_suspend(adev);
521}
522
523static int vce_v2_0_resume(void *handle)
524{
525 int r;
526 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
527
528 r = amdgpu_vce_resume(adev);
529 if (r)
530 return r;
531
532 return vce_v2_0_hw_init(adev);
533}
534
535static int vce_v2_0_soft_reset(void *handle)
536{
537 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
538
539 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1);
540 mdelay(5);
541
542 return vce_v2_0_start(adev);
543}
544
545static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
546 struct amdgpu_irq_src *source,
547 unsigned type,
548 enum amdgpu_interrupt_state state)
549{
550 uint32_t val = 0;
551
552 if (state == AMDGPU_IRQ_STATE_ENABLE)
553 val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
554
555 WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
556 return 0;
557}
558
559static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
560 struct amdgpu_irq_src *source,
561 struct amdgpu_iv_entry *entry)
562{
563 DRM_DEBUG("IH: VCE\n");
564 switch (entry->src_data[0]) {
565 case 0:
566 case 1:
567 amdgpu_fence_process(&adev->vce.ring[entry->src_data[0]]);
568 break;
569 default:
570 DRM_ERROR("Unhandled interrupt: %d %d\n",
571 entry->src_id, entry->src_data[0]);
572 break;
573 }
574
575 return 0;
576}
577
578static int vce_v2_0_set_clockgating_state(void *handle,
579 enum amd_clockgating_state state)
580{
581 bool gate = false;
582 bool sw_cg = false;
583
584 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
585
586 if (state == AMD_CG_STATE_GATE) {
587 gate = true;
588 sw_cg = true;
589 }
590
591 vce_v2_0_enable_mgcg(adev, gate, sw_cg);
592
593 return 0;
594}
595
596static int vce_v2_0_set_powergating_state(void *handle,
597 enum amd_powergating_state state)
598{
599 /* This doesn't actually powergate the VCE block.
600 * That's done in the dpm code via the SMC. This
601 * just re-inits the block as necessary. The actual
602 * gating still happens in the dpm code. We should
603 * revisit this when there is a cleaner line between
604 * the smc and the hw blocks
605 */
606 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
607
608 if (state == AMD_PG_STATE_GATE)
609 return vce_v2_0_stop(adev);
610 else
611 return vce_v2_0_start(adev);
612}
613
614static const struct amd_ip_funcs vce_v2_0_ip_funcs = {
615 .name = "vce_v2_0",
616 .early_init = vce_v2_0_early_init,
617 .late_init = NULL,
618 .sw_init = vce_v2_0_sw_init,
619 .sw_fini = vce_v2_0_sw_fini,
620 .hw_init = vce_v2_0_hw_init,
621 .hw_fini = vce_v2_0_hw_fini,
622 .suspend = vce_v2_0_suspend,
623 .resume = vce_v2_0_resume,
624 .is_idle = vce_v2_0_is_idle,
625 .wait_for_idle = vce_v2_0_wait_for_idle,
626 .soft_reset = vce_v2_0_soft_reset,
627 .set_clockgating_state = vce_v2_0_set_clockgating_state,
628 .set_powergating_state = vce_v2_0_set_powergating_state,
629};
630
631static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
632 .type = AMDGPU_RING_TYPE_VCE,
633 .align_mask = 0xf,
634 .nop = VCE_CMD_NO_OP,
635 .support_64bit_ptrs = false,
636 .no_user_fence = true,
637 .get_rptr = vce_v2_0_ring_get_rptr,
638 .get_wptr = vce_v2_0_ring_get_wptr,
639 .set_wptr = vce_v2_0_ring_set_wptr,
640 .parse_cs = amdgpu_vce_ring_parse_cs,
641 .emit_frame_size = 6, /* amdgpu_vce_ring_emit_fence x1 no user fence */
642 .emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */
643 .emit_ib = amdgpu_vce_ring_emit_ib,
644 .emit_fence = amdgpu_vce_ring_emit_fence,
645 .test_ring = amdgpu_vce_ring_test_ring,
646 .test_ib = amdgpu_vce_ring_test_ib,
647 .insert_nop = amdgpu_ring_insert_nop,
648 .pad_ib = amdgpu_ring_generic_pad_ib,
649 .begin_use = amdgpu_vce_ring_begin_use,
650 .end_use = amdgpu_vce_ring_end_use,
651};
652
653static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
654{
655 int i;
656
657 for (i = 0; i < adev->vce.num_rings; i++) {
658 adev->vce.ring[i].funcs = &vce_v2_0_ring_funcs;
659 adev->vce.ring[i].me = i;
660 }
661}
662
663static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
664 .set = vce_v2_0_set_interrupt_state,
665 .process = vce_v2_0_process_interrupt,
666};
667
668static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
669{
670 adev->vce.irq.num_types = 1;
671 adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
672};
673
674const struct amdgpu_ip_block_version vce_v2_0_ip_block =
675{
676 .type = AMD_IP_BLOCK_TYPE_VCE,
677 .major = 2,
678 .minor = 0,
679 .rev = 0,
680 .funcs = &vce_v2_0_ip_funcs,
681};
1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 * Authors: Christian König <christian.koenig@amd.com>
26 */
27
28#include <linux/firmware.h>
29#include <drm/drmP.h>
30#include "amdgpu.h"
31#include "amdgpu_vce.h"
32#include "cikd.h"
33
34#include "vce/vce_2_0_d.h"
35#include "vce/vce_2_0_sh_mask.h"
36
37#include "oss/oss_2_0_d.h"
38#include "oss/oss_2_0_sh_mask.h"
39
40#define VCE_V2_0_FW_SIZE (256 * 1024)
41#define VCE_V2_0_STACK_SIZE (64 * 1024)
42#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES)
43
44static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
45static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
46static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
47
48/**
49 * vce_v2_0_ring_get_rptr - get read pointer
50 *
51 * @ring: amdgpu_ring pointer
52 *
53 * Returns the current hardware read pointer
54 */
55static uint32_t vce_v2_0_ring_get_rptr(struct amdgpu_ring *ring)
56{
57 struct amdgpu_device *adev = ring->adev;
58
59 if (ring == &adev->vce.ring[0])
60 return RREG32(mmVCE_RB_RPTR);
61 else
62 return RREG32(mmVCE_RB_RPTR2);
63}
64
65/**
66 * vce_v2_0_ring_get_wptr - get write pointer
67 *
68 * @ring: amdgpu_ring pointer
69 *
70 * Returns the current hardware write pointer
71 */
72static uint32_t vce_v2_0_ring_get_wptr(struct amdgpu_ring *ring)
73{
74 struct amdgpu_device *adev = ring->adev;
75
76 if (ring == &adev->vce.ring[0])
77 return RREG32(mmVCE_RB_WPTR);
78 else
79 return RREG32(mmVCE_RB_WPTR2);
80}
81
82/**
83 * vce_v2_0_ring_set_wptr - set write pointer
84 *
85 * @ring: amdgpu_ring pointer
86 *
87 * Commits the write pointer to the hardware
88 */
89static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
90{
91 struct amdgpu_device *adev = ring->adev;
92
93 if (ring == &adev->vce.ring[0])
94 WREG32(mmVCE_RB_WPTR, ring->wptr);
95 else
96 WREG32(mmVCE_RB_WPTR2, ring->wptr);
97}
98
99/**
100 * vce_v2_0_start - start VCE block
101 *
102 * @adev: amdgpu_device pointer
103 *
104 * Setup and start the VCE block
105 */
106static int vce_v2_0_start(struct amdgpu_device *adev)
107{
108 struct amdgpu_ring *ring;
109 int i, j, r;
110
111 vce_v2_0_mc_resume(adev);
112
113 /* set BUSY flag */
114 WREG32_P(mmVCE_STATUS, 1, ~1);
115
116 ring = &adev->vce.ring[0];
117 WREG32(mmVCE_RB_RPTR, ring->wptr);
118 WREG32(mmVCE_RB_WPTR, ring->wptr);
119 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
120 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
121 WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
122
123 ring = &adev->vce.ring[1];
124 WREG32(mmVCE_RB_RPTR2, ring->wptr);
125 WREG32(mmVCE_RB_WPTR2, ring->wptr);
126 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
127 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
128 WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
129
130 WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
131
132 WREG32_P(mmVCE_SOFT_RESET,
133 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
134 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
135
136 mdelay(100);
137
138 WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
139
140 for (i = 0; i < 10; ++i) {
141 uint32_t status;
142 for (j = 0; j < 100; ++j) {
143 status = RREG32(mmVCE_STATUS);
144 if (status & 2)
145 break;
146 mdelay(10);
147 }
148 r = 0;
149 if (status & 2)
150 break;
151
152 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
153 WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
154 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
155 mdelay(10);
156 WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
157 mdelay(10);
158 r = -1;
159 }
160
161 /* clear BUSY flag */
162 WREG32_P(mmVCE_STATUS, 0, ~1);
163
164 if (r) {
165 DRM_ERROR("VCE not responding, giving up!!!\n");
166 return r;
167 }
168
169 return 0;
170}
171
172static int vce_v2_0_early_init(void *handle)
173{
174 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
175
176 vce_v2_0_set_ring_funcs(adev);
177 vce_v2_0_set_irq_funcs(adev);
178
179 return 0;
180}
181
182static int vce_v2_0_sw_init(void *handle)
183{
184 struct amdgpu_ring *ring;
185 int r;
186 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
187
188 /* VCE */
189 r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
190 if (r)
191 return r;
192
193 r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE +
194 VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE);
195 if (r)
196 return r;
197
198 r = amdgpu_vce_resume(adev);
199 if (r)
200 return r;
201
202 ring = &adev->vce.ring[0];
203 sprintf(ring->name, "vce0");
204 r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
205 &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
206 if (r)
207 return r;
208
209 ring = &adev->vce.ring[1];
210 sprintf(ring->name, "vce1");
211 r = amdgpu_ring_init(adev, ring, 4096, VCE_CMD_NO_OP, 0xf,
212 &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE);
213 if (r)
214 return r;
215
216 return r;
217}
218
219static int vce_v2_0_sw_fini(void *handle)
220{
221 int r;
222 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
223
224 r = amdgpu_vce_suspend(adev);
225 if (r)
226 return r;
227
228 r = amdgpu_vce_sw_fini(adev);
229 if (r)
230 return r;
231
232 return r;
233}
234
235static int vce_v2_0_hw_init(void *handle)
236{
237 struct amdgpu_ring *ring;
238 int r;
239 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
240
241 r = vce_v2_0_start(adev);
242 if (r)
243 return r;
244
245 ring = &adev->vce.ring[0];
246 ring->ready = true;
247 r = amdgpu_ring_test_ring(ring);
248 if (r) {
249 ring->ready = false;
250 return r;
251 }
252
253 ring = &adev->vce.ring[1];
254 ring->ready = true;
255 r = amdgpu_ring_test_ring(ring);
256 if (r) {
257 ring->ready = false;
258 return r;
259 }
260
261 DRM_INFO("VCE initialized successfully.\n");
262
263 return 0;
264}
265
266static int vce_v2_0_hw_fini(void *handle)
267{
268 return 0;
269}
270
271static int vce_v2_0_suspend(void *handle)
272{
273 int r;
274 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
275
276 r = vce_v2_0_hw_fini(adev);
277 if (r)
278 return r;
279
280 r = amdgpu_vce_suspend(adev);
281 if (r)
282 return r;
283
284 return r;
285}
286
287static int vce_v2_0_resume(void *handle)
288{
289 int r;
290 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
291
292 r = amdgpu_vce_resume(adev);
293 if (r)
294 return r;
295
296 r = vce_v2_0_hw_init(adev);
297 if (r)
298 return r;
299
300 return r;
301}
302
303static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
304{
305 u32 tmp;
306
307 if (gated) {
308 tmp = RREG32(mmVCE_CLOCK_GATING_B);
309 tmp |= 0xe70000;
310 WREG32(mmVCE_CLOCK_GATING_B, tmp);
311
312 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
313 tmp |= 0xff000000;
314 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
315
316 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
317 tmp &= ~0x3fc;
318 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
319
320 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
321 } else {
322 tmp = RREG32(mmVCE_CLOCK_GATING_B);
323 tmp |= 0xe7;
324 tmp &= ~0xe70000;
325 WREG32(mmVCE_CLOCK_GATING_B, tmp);
326
327 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
328 tmp |= 0x1fe000;
329 tmp &= ~0xff000000;
330 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
331
332 tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
333 tmp |= 0x3fc;
334 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
335 }
336}
337
338static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
339{
340 u32 orig, tmp;
341
342 tmp = RREG32(mmVCE_CLOCK_GATING_B);
343 tmp &= ~0x00060006;
344 if (gated) {
345 tmp |= 0xe10000;
346 } else {
347 tmp |= 0xe1;
348 tmp &= ~0xe10000;
349 }
350 WREG32(mmVCE_CLOCK_GATING_B, tmp);
351
352 orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
353 tmp &= ~0x1fe000;
354 tmp &= ~0xff000000;
355 if (tmp != orig)
356 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
357
358 orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
359 tmp &= ~0x3fc;
360 if (tmp != orig)
361 WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
362
363 if (gated)
364 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
365}
366
367static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
368{
369 WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);
370}
371
372static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
373{
374 bool sw_cg = false;
375
376 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) {
377 if (sw_cg)
378 vce_v2_0_set_sw_cg(adev, true);
379 else
380 vce_v2_0_set_dyn_cg(adev, true);
381 } else {
382 vce_v2_0_disable_cg(adev);
383
384 if (sw_cg)
385 vce_v2_0_set_sw_cg(adev, false);
386 else
387 vce_v2_0_set_dyn_cg(adev, false);
388 }
389}
390
391static void vce_v2_0_init_cg(struct amdgpu_device *adev)
392{
393 u32 tmp;
394
395 tmp = RREG32(mmVCE_CLOCK_GATING_A);
396 tmp &= ~0xfff;
397 tmp |= ((0 << 0) | (4 << 4));
398 tmp |= 0x40000;
399 WREG32(mmVCE_CLOCK_GATING_A, tmp);
400
401 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
402 tmp &= ~0xfff;
403 tmp |= ((0 << 0) | (4 << 4));
404 WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
405
406 tmp = RREG32(mmVCE_CLOCK_GATING_B);
407 tmp |= 0x10;
408 tmp &= ~0x100000;
409 WREG32(mmVCE_CLOCK_GATING_B, tmp);
410}
411
412static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
413{
414 uint64_t addr = adev->vce.gpu_addr;
415 uint32_t size;
416
417 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16));
418 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
419 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
420 WREG32(mmVCE_CLOCK_GATING_B, 0xf7);
421
422 WREG32(mmVCE_LMI_CTRL, 0x00398000);
423 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1);
424 WREG32(mmVCE_LMI_SWAP_CNTL, 0);
425 WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
426 WREG32(mmVCE_LMI_VM_CTRL, 0);
427
428 addr += AMDGPU_VCE_FIRMWARE_OFFSET;
429 size = VCE_V2_0_FW_SIZE;
430 WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
431 WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
432
433 addr += size;
434 size = VCE_V2_0_STACK_SIZE;
435 WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
436 WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
437
438 addr += size;
439 size = VCE_V2_0_DATA_SIZE;
440 WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
441 WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
442
443 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
444
445 WREG32_P(mmVCE_SYS_INT_EN, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK,
446 ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
447
448 vce_v2_0_init_cg(adev);
449}
450
451static bool vce_v2_0_is_idle(void *handle)
452{
453 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
454
455 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
456}
457
458static int vce_v2_0_wait_for_idle(void *handle)
459{
460 unsigned i;
461 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
462
463 for (i = 0; i < adev->usec_timeout; i++) {
464 if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))
465 return 0;
466 }
467 return -ETIMEDOUT;
468}
469
470static int vce_v2_0_soft_reset(void *handle)
471{
472 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
473
474 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK,
475 ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK);
476 mdelay(5);
477
478 return vce_v2_0_start(adev);
479}
480
481static void vce_v2_0_print_status(void *handle)
482{
483 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
484
485 dev_info(adev->dev, "VCE 2.0 registers\n");
486 dev_info(adev->dev, " VCE_STATUS=0x%08X\n",
487 RREG32(mmVCE_STATUS));
488 dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n",
489 RREG32(mmVCE_VCPU_CNTL));
490 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
491 RREG32(mmVCE_VCPU_CACHE_OFFSET0));
492 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n",
493 RREG32(mmVCE_VCPU_CACHE_SIZE0));
494 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
495 RREG32(mmVCE_VCPU_CACHE_OFFSET1));
496 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n",
497 RREG32(mmVCE_VCPU_CACHE_SIZE1));
498 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
499 RREG32(mmVCE_VCPU_CACHE_OFFSET2));
500 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n",
501 RREG32(mmVCE_VCPU_CACHE_SIZE2));
502 dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n",
503 RREG32(mmVCE_SOFT_RESET));
504 dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n",
505 RREG32(mmVCE_RB_BASE_LO2));
506 dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n",
507 RREG32(mmVCE_RB_BASE_HI2));
508 dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n",
509 RREG32(mmVCE_RB_SIZE2));
510 dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n",
511 RREG32(mmVCE_RB_RPTR2));
512 dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n",
513 RREG32(mmVCE_RB_WPTR2));
514 dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n",
515 RREG32(mmVCE_RB_BASE_LO));
516 dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n",
517 RREG32(mmVCE_RB_BASE_HI));
518 dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n",
519 RREG32(mmVCE_RB_SIZE));
520 dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n",
521 RREG32(mmVCE_RB_RPTR));
522 dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n",
523 RREG32(mmVCE_RB_WPTR));
524 dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n",
525 RREG32(mmVCE_CLOCK_GATING_A));
526 dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n",
527 RREG32(mmVCE_CLOCK_GATING_B));
528 dev_info(adev->dev, " VCE_CGTT_CLK_OVERRIDE=0x%08X\n",
529 RREG32(mmVCE_CGTT_CLK_OVERRIDE));
530 dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n",
531 RREG32(mmVCE_UENC_CLOCK_GATING));
532 dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
533 RREG32(mmVCE_UENC_REG_CLOCK_GATING));
534 dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n",
535 RREG32(mmVCE_SYS_INT_EN));
536 dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n",
537 RREG32(mmVCE_LMI_CTRL2));
538 dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n",
539 RREG32(mmVCE_LMI_CTRL));
540 dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n",
541 RREG32(mmVCE_LMI_VM_CTRL));
542 dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n",
543 RREG32(mmVCE_LMI_SWAP_CNTL));
544 dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n",
545 RREG32(mmVCE_LMI_SWAP_CNTL1));
546 dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n",
547 RREG32(mmVCE_LMI_CACHE_CTRL));
548}
549
550static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
551 struct amdgpu_irq_src *source,
552 unsigned type,
553 enum amdgpu_interrupt_state state)
554{
555 uint32_t val = 0;
556
557 if (state == AMDGPU_IRQ_STATE_ENABLE)
558 val |= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK;
559
560 WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);
561 return 0;
562}
563
564static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
565 struct amdgpu_irq_src *source,
566 struct amdgpu_iv_entry *entry)
567{
568 DRM_DEBUG("IH: VCE\n");
569 switch (entry->src_data) {
570 case 0:
571 amdgpu_fence_process(&adev->vce.ring[0]);
572 break;
573 case 1:
574 amdgpu_fence_process(&adev->vce.ring[1]);
575 break;
576 default:
577 DRM_ERROR("Unhandled interrupt: %d %d\n",
578 entry->src_id, entry->src_data);
579 break;
580 }
581
582 return 0;
583}
584
585static int vce_v2_0_set_clockgating_state(void *handle,
586 enum amd_clockgating_state state)
587{
588 bool gate = false;
589 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
590
591 if (state == AMD_CG_STATE_GATE)
592 gate = true;
593
594 vce_v2_0_enable_mgcg(adev, gate);
595
596 return 0;
597}
598
599static int vce_v2_0_set_powergating_state(void *handle,
600 enum amd_powergating_state state)
601{
602 /* This doesn't actually powergate the VCE block.
603 * That's done in the dpm code via the SMC. This
604 * just re-inits the block as necessary. The actual
605 * gating still happens in the dpm code. We should
606 * revisit this when there is a cleaner line between
607 * the smc and the hw blocks
608 */
609 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
610
611 if (!(adev->pg_flags & AMD_PG_SUPPORT_VCE))
612 return 0;
613
614 if (state == AMD_PG_STATE_GATE)
615 /* XXX do we need a vce_v2_0_stop()? */
616 return 0;
617 else
618 return vce_v2_0_start(adev);
619}
620
621const struct amd_ip_funcs vce_v2_0_ip_funcs = {
622 .early_init = vce_v2_0_early_init,
623 .late_init = NULL,
624 .sw_init = vce_v2_0_sw_init,
625 .sw_fini = vce_v2_0_sw_fini,
626 .hw_init = vce_v2_0_hw_init,
627 .hw_fini = vce_v2_0_hw_fini,
628 .suspend = vce_v2_0_suspend,
629 .resume = vce_v2_0_resume,
630 .is_idle = vce_v2_0_is_idle,
631 .wait_for_idle = vce_v2_0_wait_for_idle,
632 .soft_reset = vce_v2_0_soft_reset,
633 .print_status = vce_v2_0_print_status,
634 .set_clockgating_state = vce_v2_0_set_clockgating_state,
635 .set_powergating_state = vce_v2_0_set_powergating_state,
636};
637
638static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
639 .get_rptr = vce_v2_0_ring_get_rptr,
640 .get_wptr = vce_v2_0_ring_get_wptr,
641 .set_wptr = vce_v2_0_ring_set_wptr,
642 .parse_cs = amdgpu_vce_ring_parse_cs,
643 .emit_ib = amdgpu_vce_ring_emit_ib,
644 .emit_fence = amdgpu_vce_ring_emit_fence,
645 .test_ring = amdgpu_vce_ring_test_ring,
646 .test_ib = amdgpu_vce_ring_test_ib,
647 .insert_nop = amdgpu_ring_insert_nop,
648 .pad_ib = amdgpu_ring_generic_pad_ib,
649};
650
651static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev)
652{
653 adev->vce.ring[0].funcs = &vce_v2_0_ring_funcs;
654 adev->vce.ring[1].funcs = &vce_v2_0_ring_funcs;
655}
656
657static const struct amdgpu_irq_src_funcs vce_v2_0_irq_funcs = {
658 .set = vce_v2_0_set_interrupt_state,
659 .process = vce_v2_0_process_interrupt,
660};
661
662static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev)
663{
664 adev->vce.irq.num_types = 1;
665 adev->vce.irq.funcs = &vce_v2_0_irq_funcs;
666};