Loading...
Note: File does not exist in v4.6.
1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26/**
27 * DOC: overview
28 *
29 * The Output Plane Processor (OPP) block groups have functions that format
30 * pixel streams such that they are suitable for display at the display device.
31 * The key functions contained in the OPP are:
32 *
33 * - Adaptive Backlight Modulation (ABM)
34 * - Formatter (FMT) which provide pixel-by-pixel operations for format the
35 * incoming pixel stream.
36 * - Output Buffer that provide pixel replication, and overlapping.
37 * - Interface between MPC and OPTC.
38 * - Clock and reset generation.
39 * - CRC generation.
40 */
41
42#ifndef __DAL_OPP_H__
43#define __DAL_OPP_H__
44
45#include "hw_shared.h"
46#include "dc_hw_types.h"
47#include "transform.h"
48#include "mpc.h"
49
50struct fixed31_32;
51
52/* TODO: Need cleanup */
53enum clamping_range {
54 CLAMPING_FULL_RANGE = 0, /* No Clamping */
55 CLAMPING_LIMITED_RANGE_8BPC, /* 8 bpc: Clamping 1 to FE */
56 CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4 to 3FB */
57 CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */
58 /* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */
59 CLAMPING_LIMITED_RANGE_PROGRAMMABLE
60};
61
62struct clamping_and_pixel_encoding_params {
63 enum dc_pixel_encoding pixel_encoding; /* Pixel Encoding */
64 enum clamping_range clamping_level; /* Clamping identifier */
65 enum dc_color_depth c_depth; /* Deep color use. */
66};
67
68struct bit_depth_reduction_params {
69 struct {
70 /* truncate/round */
71 /* trunc/round enabled*/
72 uint32_t TRUNCATE_ENABLED:1;
73 /* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/
74 uint32_t TRUNCATE_DEPTH:2;
75 /* truncate or round*/
76 uint32_t TRUNCATE_MODE:1;
77
78 /* spatial dither */
79 /* Spatial Bit Depth Reduction enabled*/
80 uint32_t SPATIAL_DITHER_ENABLED:1;
81 /* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/
82 uint32_t SPATIAL_DITHER_DEPTH:2;
83 /* 0-3 to select patterns*/
84 uint32_t SPATIAL_DITHER_MODE:2;
85 /* Enable RGB random dithering*/
86 uint32_t RGB_RANDOM:1;
87 /* Enable Frame random dithering*/
88 uint32_t FRAME_RANDOM:1;
89 /* Enable HighPass random dithering*/
90 uint32_t HIGHPASS_RANDOM:1;
91
92 /* temporal dither*/
93 /* frame modulation enabled*/
94 uint32_t FRAME_MODULATION_ENABLED:1;
95 /* same as for trunc/spatial*/
96 uint32_t FRAME_MODULATION_DEPTH:2;
97 /* 2/4 gray levels*/
98 uint32_t TEMPORAL_LEVEL:1;
99 uint32_t FRC25:2;
100 uint32_t FRC50:2;
101 uint32_t FRC75:2;
102 } flags;
103
104 uint32_t r_seed_value;
105 uint32_t b_seed_value;
106 uint32_t g_seed_value;
107 enum dc_pixel_encoding pixel_encoding;
108};
109
110enum wide_gamut_regamma_mode {
111 /* 0x0 - BITS2:0 Bypass */
112 WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS,
113 /* 0x1 - Fixed curve sRGB 2.4 */
114 WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_SRGB24,
115 /* 0x2 - Fixed curve xvYCC 2.22 */
116 WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_XYYCC22,
117 /* 0x3 - Programmable control A */
118 WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A,
119 /* 0x4 - Programmable control B */
120 WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_B,
121 /* 0x0 - BITS6:4 Bypass */
122 WIDE_GAMUT_REGAMMA_MODE_OVL_BYPASS,
123 /* 0x1 - Fixed curve sRGB 2.4 */
124 WIDE_GAMUT_REGAMMA_MODE_OVL_SRGB24,
125 /* 0x2 - Fixed curve xvYCC 2.22 */
126 WIDE_GAMUT_REGAMMA_MODE_OVL_XYYCC22,
127 /* 0x3 - Programmable control A */
128 WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_A,
129 /* 0x4 - Programmable control B */
130 WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_B
131};
132
133struct gamma_pixel {
134 struct fixed31_32 r;
135 struct fixed31_32 g;
136 struct fixed31_32 b;
137};
138
139enum channel_name {
140 CHANNEL_NAME_RED,
141 CHANNEL_NAME_GREEN,
142 CHANNEL_NAME_BLUE
143};
144
145struct custom_float_format {
146 uint32_t mantissa_bits;
147 uint32_t exponenta_bits;
148 bool sign;
149};
150
151struct custom_float_value {
152 uint32_t mantissa;
153 uint32_t exponenta;
154 uint32_t value;
155 bool negative;
156};
157
158struct hw_x_point {
159 uint32_t custom_float_x;
160 struct fixed31_32 x;
161 struct fixed31_32 regamma_y_red;
162 struct fixed31_32 regamma_y_green;
163 struct fixed31_32 regamma_y_blue;
164
165};
166
167struct pwl_float_data_ex {
168 struct fixed31_32 r;
169 struct fixed31_32 g;
170 struct fixed31_32 b;
171 struct fixed31_32 delta_r;
172 struct fixed31_32 delta_g;
173 struct fixed31_32 delta_b;
174};
175
176enum hw_point_position {
177 /* hw point sits between left and right sw points */
178 HW_POINT_POSITION_MIDDLE,
179 /* hw point lays left from left (smaller) sw point */
180 HW_POINT_POSITION_LEFT,
181 /* hw point lays stays from right (bigger) sw point */
182 HW_POINT_POSITION_RIGHT
183};
184
185struct gamma_point {
186 int32_t left_index;
187 int32_t right_index;
188 enum hw_point_position pos;
189 struct fixed31_32 coeff;
190};
191
192struct pixel_gamma_point {
193 struct gamma_point r;
194 struct gamma_point g;
195 struct gamma_point b;
196};
197
198struct gamma_coefficients {
199 struct fixed31_32 a0[3];
200 struct fixed31_32 a1[3];
201 struct fixed31_32 a2[3];
202 struct fixed31_32 a3[3];
203 struct fixed31_32 user_gamma[3];
204 struct fixed31_32 user_contrast;
205 struct fixed31_32 user_brightness;
206};
207
208struct pwl_float_data {
209 struct fixed31_32 r;
210 struct fixed31_32 g;
211 struct fixed31_32 b;
212};
213
214struct mpc_tree_cfg {
215 int num_pipes;
216 int dpp[MAX_PIPES];
217 int mpcc[MAX_PIPES];
218};
219
220struct output_pixel_processor {
221 struct dc_context *ctx;
222 uint32_t inst;
223 struct pwl_params regamma_params;
224 struct mpc_tree mpc_tree_params;
225 bool mpcc_disconnect_pending[MAX_PIPES];
226 const struct opp_funcs *funcs;
227 uint32_t dyn_expansion;
228};
229
230enum fmt_stereo_action {
231 FMT_STEREO_ACTION_ENABLE = 0,
232 FMT_STEREO_ACTION_DISABLE,
233 FMT_STEREO_ACTION_UPDATE_POLARITY
234};
235
236struct opp_grph_csc_adjustment {
237 //enum grph_color_adjust_option color_adjust_option;
238 enum dc_color_space c_space;
239 enum dc_color_depth color_depth; /* clean up to uint32_t */
240 enum graphics_csc_adjust_type csc_adjust_type;
241 int32_t adjust_divider;
242 int32_t grph_cont;
243 int32_t grph_sat;
244 int32_t grph_bright;
245 int32_t grph_hue;
246};
247
248/* Underlay related types */
249
250struct hw_adjustment_range {
251 int32_t hw_default;
252 int32_t min;
253 int32_t max;
254 int32_t step;
255 uint32_t divider; /* (actually HW range is min/divider; divider !=0) */
256};
257
258enum ovl_csc_adjust_item {
259 OVERLAY_BRIGHTNESS = 0,
260 OVERLAY_GAMMA,
261 OVERLAY_CONTRAST,
262 OVERLAY_SATURATION,
263 OVERLAY_HUE,
264 OVERLAY_ALPHA,
265 OVERLAY_ALPHA_PER_PIX,
266 OVERLAY_COLOR_TEMPERATURE
267};
268
269enum oppbuf_display_segmentation {
270 OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0,
271 OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1,
272 OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2,
273 OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3,
274 OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4
275};
276
277struct oppbuf_params {
278 uint32_t active_width;
279 enum oppbuf_display_segmentation mso_segmentation;
280 uint32_t mso_overlap_pixel_num;
281 uint32_t pixel_repetition;
282 uint32_t num_segment_padded_pixels;
283};
284
285struct opp_funcs {
286
287
288 /* FORMATTER RELATED */
289
290 void (*opp_program_fmt)(
291 struct output_pixel_processor *opp,
292 struct bit_depth_reduction_params *fmt_bit_depth,
293 struct clamping_and_pixel_encoding_params *clamping);
294
295 void (*opp_set_dyn_expansion)(
296 struct output_pixel_processor *opp,
297 enum dc_color_space color_sp,
298 enum dc_color_depth color_dpth,
299 enum signal_type signal);
300
301 void (*opp_program_bit_depth_reduction)(
302 struct output_pixel_processor *opp,
303 const struct bit_depth_reduction_params *params);
304
305 /* underlay related */
306 void (*opp_get_underlay_adjustment_range)(
307 struct output_pixel_processor *opp,
308 enum ovl_csc_adjust_item overlay_adjust_item,
309 struct hw_adjustment_range *range);
310
311 void (*opp_destroy)(struct output_pixel_processor **opp);
312
313 void (*opp_program_stereo)(
314 struct output_pixel_processor *opp,
315 bool enable,
316 const struct dc_crtc_timing *timing);
317
318 void (*opp_pipe_clock_control)(
319 struct output_pixel_processor *opp,
320 bool enable);
321
322 void (*opp_set_disp_pattern_generator)(
323 struct output_pixel_processor *opp,
324 enum controller_dp_test_pattern test_pattern,
325 enum controller_dp_color_space color_space,
326 enum dc_color_depth color_depth,
327 const struct tg_color *solid_color,
328 int width,
329 int height,
330 int offset);
331
332 void (*opp_program_dpg_dimensions)(
333 struct output_pixel_processor *opp,
334 int width,
335 int height);
336
337 bool (*dpg_is_blanked)(
338 struct output_pixel_processor *opp);
339
340 bool (*dpg_is_pending)(struct output_pixel_processor *opp);
341
342
343 void (*opp_dpg_set_blank_color)(
344 struct output_pixel_processor *opp,
345 const struct tg_color *color);
346
347 void (*opp_program_left_edge_extra_pixel)(
348 struct output_pixel_processor *opp,
349 bool count);
350
351};
352
353#endif