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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2009 - 2018 Intel Corporation. */
3
4#ifndef _E1000_REGS_H_
5#define _E1000_REGS_H_
6
7#define E1000_CTRL 0x00000 /* Device Control - RW */
8#define E1000_STATUS 0x00008 /* Device Status - RO */
9#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
10#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
11#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
12#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
13#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
14#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
15#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
16#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
17#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
18#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
19
20/* Convenience macros
21 *
22 * Note: "_n" is the queue number of the register to be written to.
23 *
24 * Example usage:
25 * E1000_RDBAL_REG(current_rx_queue)
26 */
27#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
28 (0x0C000 + ((_n) * 0x40)))
29#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
30 (0x0C004 + ((_n) * 0x40)))
31#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
32 (0x0C008 + ((_n) * 0x40)))
33#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
34 (0x0C00C + ((_n) * 0x40)))
35#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
36 (0x0C010 + ((_n) * 0x40)))
37#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
38 (0x0C018 + ((_n) * 0x40)))
39#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
40 (0x0C028 + ((_n) * 0x40)))
41#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
42 (0x0E000 + ((_n) * 0x40)))
43#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
44 (0x0E004 + ((_n) * 0x40)))
45#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
46 (0x0E008 + ((_n) * 0x40)))
47#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
48 (0x0E010 + ((_n) * 0x40)))
49#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
50 (0x0E018 + ((_n) * 0x40)))
51#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
52 (0x0E028 + ((_n) * 0x40)))
53#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
54#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
55#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
56 (0x054E0 + ((_i - 16) * 8)))
57#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
58 (0x054E4 + ((_i - 16) * 8)))
59
60/* Statistics registers */
61#define E1000_VFGPRC 0x00F10
62#define E1000_VFGORC 0x00F18
63#define E1000_VFMPRC 0x00F3C
64#define E1000_VFGPTC 0x00F14
65#define E1000_VFGOTC 0x00F34
66#define E1000_VFGOTLBC 0x00F50
67#define E1000_VFGPTLBC 0x00F44
68#define E1000_VFGORLBC 0x00F48
69#define E1000_VFGPRLBC 0x00F40
70
71/* These act per VF so an array friendly macro is used */
72#define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n)))
73#define E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))
74
75/* Define macros for handling registers */
76#define er32(reg) readl(hw->hw_addr + E1000_##reg)
77#define ew32(reg, val) writel((val), hw->hw_addr + E1000_##reg)
78#define array_er32(reg, offset) \
79 readl(hw->hw_addr + E1000_##reg + (offset << 2))
80#define array_ew32(reg, offset, val) \
81 writel((val), hw->hw_addr + E1000_##reg + (offset << 2))
82#define e1e_flush() er32(STATUS)
83
84#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*******************************************************************************
3
4 Intel(R) 82576 Virtual Function Linux driver
5 Copyright(c) 2009 - 2012 Intel Corporation.
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, see <http://www.gnu.org/licenses/>.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _E1000_REGS_H_
29#define _E1000_REGS_H_
30
31#define E1000_CTRL 0x00000 /* Device Control - RW */
32#define E1000_STATUS 0x00008 /* Device Status - RO */
33#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
34#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
35#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
36#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
37#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
38#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
39#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
40#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
41#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
42#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
43
44/* Convenience macros
45 *
46 * Note: "_n" is the queue number of the register to be written to.
47 *
48 * Example usage:
49 * E1000_RDBAL_REG(current_rx_queue)
50 */
51#define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
52 (0x0C000 + ((_n) * 0x40)))
53#define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
54 (0x0C004 + ((_n) * 0x40)))
55#define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
56 (0x0C008 + ((_n) * 0x40)))
57#define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
58 (0x0C00C + ((_n) * 0x40)))
59#define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
60 (0x0C010 + ((_n) * 0x40)))
61#define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
62 (0x0C018 + ((_n) * 0x40)))
63#define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
64 (0x0C028 + ((_n) * 0x40)))
65#define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
66 (0x0E000 + ((_n) * 0x40)))
67#define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
68 (0x0E004 + ((_n) * 0x40)))
69#define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
70 (0x0E008 + ((_n) * 0x40)))
71#define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
72 (0x0E010 + ((_n) * 0x40)))
73#define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
74 (0x0E018 + ((_n) * 0x40)))
75#define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
76 (0x0E028 + ((_n) * 0x40)))
77#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
78#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
79#define E1000_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
80 (0x054E0 + ((_i - 16) * 8)))
81#define E1000_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
82 (0x054E4 + ((_i - 16) * 8)))
83
84/* Statistics registers */
85#define E1000_VFGPRC 0x00F10
86#define E1000_VFGORC 0x00F18
87#define E1000_VFMPRC 0x00F3C
88#define E1000_VFGPTC 0x00F14
89#define E1000_VFGOTC 0x00F34
90#define E1000_VFGOTLBC 0x00F50
91#define E1000_VFGPTLBC 0x00F44
92#define E1000_VFGORLBC 0x00F48
93#define E1000_VFGPRLBC 0x00F40
94
95/* These act per VF so an array friendly macro is used */
96#define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n)))
97#define E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))
98
99/* Define macros for handling registers */
100#define er32(reg) readl(hw->hw_addr + E1000_##reg)
101#define ew32(reg, val) writel((val), hw->hw_addr + E1000_##reg)
102#define array_er32(reg, offset) \
103 readl(hw->hw_addr + E1000_##reg + (offset << 2))
104#define array_ew32(reg, offset, val) \
105 writel((val), hw->hw_addr + E1000_##reg + (offset << 2))
106#define e1e_flush() er32(STATUS)
107
108#endif