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1/* SPDX-License-Identifier: GPL-2.0 */
2/*******************************************************************************
3 *
4 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
5 * Copyright(c) 2013 - 2017 Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#ifndef _I40E_ADMINQ_CMD_H_
29#define _I40E_ADMINQ_CMD_H_
30
31/* This header file defines the i40e Admin Queue commands and is shared between
32 * i40e Firmware and Software.
33 *
34 * This file needs to comply with the Linux Kernel coding style.
35 */
36
37#define I40E_FW_API_VERSION_MAJOR 0x0001
38#define I40E_FW_API_VERSION_MINOR_X722 0x0005
39#define I40E_FW_API_VERSION_MINOR_X710 0x0007
40
41#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
42 I40E_FW_API_VERSION_MINOR_X710 : \
43 I40E_FW_API_VERSION_MINOR_X722)
44
45/* API version 1.7 implements additional link and PHY-specific APIs */
46#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
47
48struct i40e_aq_desc {
49 __le16 flags;
50 __le16 opcode;
51 __le16 datalen;
52 __le16 retval;
53 __le32 cookie_high;
54 __le32 cookie_low;
55 union {
56 struct {
57 __le32 param0;
58 __le32 param1;
59 __le32 param2;
60 __le32 param3;
61 } internal;
62 struct {
63 __le32 param0;
64 __le32 param1;
65 __le32 addr_high;
66 __le32 addr_low;
67 } external;
68 u8 raw[16];
69 } params;
70};
71
72/* Flags sub-structure
73 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
74 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
75 */
76
77/* command flags and offsets*/
78#define I40E_AQ_FLAG_DD_SHIFT 0
79#define I40E_AQ_FLAG_CMP_SHIFT 1
80#define I40E_AQ_FLAG_ERR_SHIFT 2
81#define I40E_AQ_FLAG_VFE_SHIFT 3
82#define I40E_AQ_FLAG_LB_SHIFT 9
83#define I40E_AQ_FLAG_RD_SHIFT 10
84#define I40E_AQ_FLAG_VFC_SHIFT 11
85#define I40E_AQ_FLAG_BUF_SHIFT 12
86#define I40E_AQ_FLAG_SI_SHIFT 13
87#define I40E_AQ_FLAG_EI_SHIFT 14
88#define I40E_AQ_FLAG_FE_SHIFT 15
89
90#define I40E_AQ_FLAG_DD BIT(I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
91#define I40E_AQ_FLAG_CMP BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
92#define I40E_AQ_FLAG_ERR BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
93#define I40E_AQ_FLAG_VFE BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
94#define I40E_AQ_FLAG_LB BIT(I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
95#define I40E_AQ_FLAG_RD BIT(I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
96#define I40E_AQ_FLAG_VFC BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
97#define I40E_AQ_FLAG_BUF BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
98#define I40E_AQ_FLAG_SI BIT(I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
99#define I40E_AQ_FLAG_EI BIT(I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
100#define I40E_AQ_FLAG_FE BIT(I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
101
102/* error codes */
103enum i40e_admin_queue_err {
104 I40E_AQ_RC_OK = 0, /* success */
105 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
106 I40E_AQ_RC_ENOENT = 2, /* No such element */
107 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
108 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
109 I40E_AQ_RC_EIO = 5, /* I/O error */
110 I40E_AQ_RC_ENXIO = 6, /* No such resource */
111 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
112 I40E_AQ_RC_EAGAIN = 8, /* Try again */
113 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
114 I40E_AQ_RC_EACCES = 10, /* Permission denied */
115 I40E_AQ_RC_EFAULT = 11, /* Bad address */
116 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
117 I40E_AQ_RC_EEXIST = 13, /* object already exists */
118 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
119 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
120 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
121 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
122 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
123 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
124 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
125 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
126 I40E_AQ_RC_EFBIG = 22, /* File too large */
127};
128
129/* Admin Queue command opcodes */
130enum i40e_admin_queue_opc {
131 /* aq commands */
132 i40e_aqc_opc_get_version = 0x0001,
133 i40e_aqc_opc_driver_version = 0x0002,
134 i40e_aqc_opc_queue_shutdown = 0x0003,
135 i40e_aqc_opc_set_pf_context = 0x0004,
136
137 /* resource ownership */
138 i40e_aqc_opc_request_resource = 0x0008,
139 i40e_aqc_opc_release_resource = 0x0009,
140
141 i40e_aqc_opc_list_func_capabilities = 0x000A,
142 i40e_aqc_opc_list_dev_capabilities = 0x000B,
143
144 /* Proxy commands */
145 i40e_aqc_opc_set_proxy_config = 0x0104,
146 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
147
148 /* LAA */
149 i40e_aqc_opc_mac_address_read = 0x0107,
150 i40e_aqc_opc_mac_address_write = 0x0108,
151
152 /* PXE */
153 i40e_aqc_opc_clear_pxe_mode = 0x0110,
154
155 /* WoL commands */
156 i40e_aqc_opc_set_wol_filter = 0x0120,
157 i40e_aqc_opc_get_wake_reason = 0x0121,
158
159 /* internal switch commands */
160 i40e_aqc_opc_get_switch_config = 0x0200,
161 i40e_aqc_opc_add_statistics = 0x0201,
162 i40e_aqc_opc_remove_statistics = 0x0202,
163 i40e_aqc_opc_set_port_parameters = 0x0203,
164 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
165 i40e_aqc_opc_set_switch_config = 0x0205,
166 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
167 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
168
169 i40e_aqc_opc_add_vsi = 0x0210,
170 i40e_aqc_opc_update_vsi_parameters = 0x0211,
171 i40e_aqc_opc_get_vsi_parameters = 0x0212,
172
173 i40e_aqc_opc_add_pv = 0x0220,
174 i40e_aqc_opc_update_pv_parameters = 0x0221,
175 i40e_aqc_opc_get_pv_parameters = 0x0222,
176
177 i40e_aqc_opc_add_veb = 0x0230,
178 i40e_aqc_opc_update_veb_parameters = 0x0231,
179 i40e_aqc_opc_get_veb_parameters = 0x0232,
180
181 i40e_aqc_opc_delete_element = 0x0243,
182
183 i40e_aqc_opc_add_macvlan = 0x0250,
184 i40e_aqc_opc_remove_macvlan = 0x0251,
185 i40e_aqc_opc_add_vlan = 0x0252,
186 i40e_aqc_opc_remove_vlan = 0x0253,
187 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
188 i40e_aqc_opc_add_tag = 0x0255,
189 i40e_aqc_opc_remove_tag = 0x0256,
190 i40e_aqc_opc_add_multicast_etag = 0x0257,
191 i40e_aqc_opc_remove_multicast_etag = 0x0258,
192 i40e_aqc_opc_update_tag = 0x0259,
193 i40e_aqc_opc_add_control_packet_filter = 0x025A,
194 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
195 i40e_aqc_opc_add_cloud_filters = 0x025C,
196 i40e_aqc_opc_remove_cloud_filters = 0x025D,
197 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
198
199 i40e_aqc_opc_add_mirror_rule = 0x0260,
200 i40e_aqc_opc_delete_mirror_rule = 0x0261,
201
202 /* Dynamic Device Personalization */
203 i40e_aqc_opc_write_personalization_profile = 0x0270,
204 i40e_aqc_opc_get_personalization_profile_list = 0x0271,
205
206 /* DCB commands */
207 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
208 i40e_aqc_opc_dcb_updated = 0x0302,
209 i40e_aqc_opc_set_dcb_parameters = 0x0303,
210
211 /* TX scheduler */
212 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
213 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
214 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
215 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
216 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
217 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
218
219 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
220 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
221 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
222 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
223 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
224 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
225 i40e_aqc_opc_query_port_ets_config = 0x0419,
226 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
227 i40e_aqc_opc_suspend_port_tx = 0x041B,
228 i40e_aqc_opc_resume_port_tx = 0x041C,
229 i40e_aqc_opc_configure_partition_bw = 0x041D,
230 /* hmc */
231 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
232 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
233
234 /* phy commands*/
235 i40e_aqc_opc_get_phy_abilities = 0x0600,
236 i40e_aqc_opc_set_phy_config = 0x0601,
237 i40e_aqc_opc_set_mac_config = 0x0603,
238 i40e_aqc_opc_set_link_restart_an = 0x0605,
239 i40e_aqc_opc_get_link_status = 0x0607,
240 i40e_aqc_opc_set_phy_int_mask = 0x0613,
241 i40e_aqc_opc_get_local_advt_reg = 0x0614,
242 i40e_aqc_opc_set_local_advt_reg = 0x0615,
243 i40e_aqc_opc_get_partner_advt = 0x0616,
244 i40e_aqc_opc_set_lb_modes = 0x0618,
245 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
246 i40e_aqc_opc_set_phy_debug = 0x0622,
247 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
248 i40e_aqc_opc_run_phy_activity = 0x0626,
249 i40e_aqc_opc_set_phy_register = 0x0628,
250 i40e_aqc_opc_get_phy_register = 0x0629,
251
252 /* NVM commands */
253 i40e_aqc_opc_nvm_read = 0x0701,
254 i40e_aqc_opc_nvm_erase = 0x0702,
255 i40e_aqc_opc_nvm_update = 0x0703,
256 i40e_aqc_opc_nvm_config_read = 0x0704,
257 i40e_aqc_opc_nvm_config_write = 0x0705,
258 i40e_aqc_opc_oem_post_update = 0x0720,
259 i40e_aqc_opc_thermal_sensor = 0x0721,
260
261 /* virtualization commands */
262 i40e_aqc_opc_send_msg_to_pf = 0x0801,
263 i40e_aqc_opc_send_msg_to_vf = 0x0802,
264 i40e_aqc_opc_send_msg_to_peer = 0x0803,
265
266 /* alternate structure */
267 i40e_aqc_opc_alternate_write = 0x0900,
268 i40e_aqc_opc_alternate_write_indirect = 0x0901,
269 i40e_aqc_opc_alternate_read = 0x0902,
270 i40e_aqc_opc_alternate_read_indirect = 0x0903,
271 i40e_aqc_opc_alternate_write_done = 0x0904,
272 i40e_aqc_opc_alternate_set_mode = 0x0905,
273 i40e_aqc_opc_alternate_clear_port = 0x0906,
274
275 /* LLDP commands */
276 i40e_aqc_opc_lldp_get_mib = 0x0A00,
277 i40e_aqc_opc_lldp_update_mib = 0x0A01,
278 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
279 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
280 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
281 i40e_aqc_opc_lldp_stop = 0x0A05,
282 i40e_aqc_opc_lldp_start = 0x0A06,
283
284 /* Tunnel commands */
285 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
286 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
287 i40e_aqc_opc_set_rss_key = 0x0B02,
288 i40e_aqc_opc_set_rss_lut = 0x0B03,
289 i40e_aqc_opc_get_rss_key = 0x0B04,
290 i40e_aqc_opc_get_rss_lut = 0x0B05,
291
292 /* Async Events */
293 i40e_aqc_opc_event_lan_overflow = 0x1001,
294
295 /* OEM commands */
296 i40e_aqc_opc_oem_parameter_change = 0xFE00,
297 i40e_aqc_opc_oem_device_status_change = 0xFE01,
298 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
299 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
300
301 /* debug commands */
302 i40e_aqc_opc_debug_read_reg = 0xFF03,
303 i40e_aqc_opc_debug_write_reg = 0xFF04,
304 i40e_aqc_opc_debug_modify_reg = 0xFF07,
305 i40e_aqc_opc_debug_dump_internals = 0xFF08,
306};
307
308/* command structures and indirect data structures */
309
310/* Structure naming conventions:
311 * - no suffix for direct command descriptor structures
312 * - _data for indirect sent data
313 * - _resp for indirect return data (data which is both will use _data)
314 * - _completion for direct return data
315 * - _element_ for repeated elements (may also be _data or _resp)
316 *
317 * Command structures are expected to overlay the params.raw member of the basic
318 * descriptor, and as such cannot exceed 16 bytes in length.
319 */
320
321/* This macro is used to generate a compilation error if a structure
322 * is not exactly the correct length. It gives a divide by zero error if the
323 * structure is not of the correct size, otherwise it creates an enum that is
324 * never used.
325 */
326#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
327 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
328
329/* This macro is used extensively to ensure that command structures are 16
330 * bytes in length as they have to map to the raw array of that size.
331 */
332#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
333
334/* internal (0x00XX) commands */
335
336/* Get version (direct 0x0001) */
337struct i40e_aqc_get_version {
338 __le32 rom_ver;
339 __le32 fw_build;
340 __le16 fw_major;
341 __le16 fw_minor;
342 __le16 api_major;
343 __le16 api_minor;
344};
345
346I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
347
348/* Send driver version (indirect 0x0002) */
349struct i40e_aqc_driver_version {
350 u8 driver_major_ver;
351 u8 driver_minor_ver;
352 u8 driver_build_ver;
353 u8 driver_subbuild_ver;
354 u8 reserved[4];
355 __le32 address_high;
356 __le32 address_low;
357};
358
359I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
360
361/* Queue Shutdown (direct 0x0003) */
362struct i40e_aqc_queue_shutdown {
363 __le32 driver_unloading;
364#define I40E_AQ_DRIVER_UNLOADING 0x1
365 u8 reserved[12];
366};
367
368I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
369
370/* Set PF context (0x0004, direct) */
371struct i40e_aqc_set_pf_context {
372 u8 pf_id;
373 u8 reserved[15];
374};
375
376I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
377
378/* Request resource ownership (direct 0x0008)
379 * Release resource ownership (direct 0x0009)
380 */
381#define I40E_AQ_RESOURCE_NVM 1
382#define I40E_AQ_RESOURCE_SDP 2
383#define I40E_AQ_RESOURCE_ACCESS_READ 1
384#define I40E_AQ_RESOURCE_ACCESS_WRITE 2
385#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
386#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
387
388struct i40e_aqc_request_resource {
389 __le16 resource_id;
390 __le16 access_type;
391 __le32 timeout;
392 __le32 resource_number;
393 u8 reserved[4];
394};
395
396I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
397
398/* Get function capabilities (indirect 0x000A)
399 * Get device capabilities (indirect 0x000B)
400 */
401struct i40e_aqc_list_capabilites {
402 u8 command_flags;
403#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
404 u8 pf_index;
405 u8 reserved[2];
406 __le32 count;
407 __le32 addr_high;
408 __le32 addr_low;
409};
410
411I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
412
413struct i40e_aqc_list_capabilities_element_resp {
414 __le16 id;
415 u8 major_rev;
416 u8 minor_rev;
417 __le32 number;
418 __le32 logical_id;
419 __le32 phys_id;
420 u8 reserved[16];
421};
422
423/* list of caps */
424
425#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
426#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
427#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
428#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
429#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
430#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
431#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
432#define I40E_AQ_CAP_ID_SRIOV 0x0012
433#define I40E_AQ_CAP_ID_VF 0x0013
434#define I40E_AQ_CAP_ID_VMDQ 0x0014
435#define I40E_AQ_CAP_ID_8021QBG 0x0015
436#define I40E_AQ_CAP_ID_8021QBR 0x0016
437#define I40E_AQ_CAP_ID_VSI 0x0017
438#define I40E_AQ_CAP_ID_DCB 0x0018
439#define I40E_AQ_CAP_ID_FCOE 0x0021
440#define I40E_AQ_CAP_ID_ISCSI 0x0022
441#define I40E_AQ_CAP_ID_RSS 0x0040
442#define I40E_AQ_CAP_ID_RXQ 0x0041
443#define I40E_AQ_CAP_ID_TXQ 0x0042
444#define I40E_AQ_CAP_ID_MSIX 0x0043
445#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
446#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
447#define I40E_AQ_CAP_ID_1588 0x0046
448#define I40E_AQ_CAP_ID_IWARP 0x0051
449#define I40E_AQ_CAP_ID_LED 0x0061
450#define I40E_AQ_CAP_ID_SDP 0x0062
451#define I40E_AQ_CAP_ID_MDIO 0x0063
452#define I40E_AQ_CAP_ID_WSR_PROT 0x0064
453#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
454#define I40E_AQ_CAP_ID_FLEX10 0x00F1
455#define I40E_AQ_CAP_ID_CEM 0x00F2
456
457/* Set CPPM Configuration (direct 0x0103) */
458struct i40e_aqc_cppm_configuration {
459 __le16 command_flags;
460#define I40E_AQ_CPPM_EN_LTRC 0x0800
461#define I40E_AQ_CPPM_EN_DMCTH 0x1000
462#define I40E_AQ_CPPM_EN_DMCTLX 0x2000
463#define I40E_AQ_CPPM_EN_HPTC 0x4000
464#define I40E_AQ_CPPM_EN_DMARC 0x8000
465 __le16 ttlx;
466 __le32 dmacr;
467 __le16 dmcth;
468 u8 hptc;
469 u8 reserved;
470 __le32 pfltrc;
471};
472
473I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
474
475/* Set ARP Proxy command / response (indirect 0x0104) */
476struct i40e_aqc_arp_proxy_data {
477 __le16 command_flags;
478#define I40E_AQ_ARP_INIT_IPV4 0x0800
479#define I40E_AQ_ARP_UNSUP_CTL 0x1000
480#define I40E_AQ_ARP_ENA 0x2000
481#define I40E_AQ_ARP_ADD_IPV4 0x4000
482#define I40E_AQ_ARP_DEL_IPV4 0x8000
483 __le16 table_id;
484 __le32 enabled_offloads;
485#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
486#define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
487 __le32 ip_addr;
488 u8 mac_addr[6];
489 u8 reserved[2];
490};
491
492I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
493
494/* Set NS Proxy Table Entry Command (indirect 0x0105) */
495struct i40e_aqc_ns_proxy_data {
496 __le16 table_idx_mac_addr_0;
497 __le16 table_idx_mac_addr_1;
498 __le16 table_idx_ipv6_0;
499 __le16 table_idx_ipv6_1;
500 __le16 control;
501#define I40E_AQ_NS_PROXY_ADD_0 0x0001
502#define I40E_AQ_NS_PROXY_DEL_0 0x0002
503#define I40E_AQ_NS_PROXY_ADD_1 0x0004
504#define I40E_AQ_NS_PROXY_DEL_1 0x0008
505#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
506#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
507#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
508#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
509#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
510#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
511#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
512#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
513#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
514 u8 mac_addr_0[6];
515 u8 mac_addr_1[6];
516 u8 local_mac_addr[6];
517 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
518 u8 ipv6_addr_1[16];
519};
520
521I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
522
523/* Manage LAA Command (0x0106) - obsolete */
524struct i40e_aqc_mng_laa {
525 __le16 command_flags;
526#define I40E_AQ_LAA_FLAG_WR 0x8000
527 u8 reserved[2];
528 __le32 sal;
529 __le16 sah;
530 u8 reserved2[6];
531};
532
533I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
534
535/* Manage MAC Address Read Command (indirect 0x0107) */
536struct i40e_aqc_mac_address_read {
537 __le16 command_flags;
538#define I40E_AQC_LAN_ADDR_VALID 0x10
539#define I40E_AQC_SAN_ADDR_VALID 0x20
540#define I40E_AQC_PORT_ADDR_VALID 0x40
541#define I40E_AQC_WOL_ADDR_VALID 0x80
542#define I40E_AQC_MC_MAG_EN_VALID 0x100
543#define I40E_AQC_ADDR_VALID_MASK 0x3F0
544 u8 reserved[6];
545 __le32 addr_high;
546 __le32 addr_low;
547};
548
549I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
550
551struct i40e_aqc_mac_address_read_data {
552 u8 pf_lan_mac[6];
553 u8 pf_san_mac[6];
554 u8 port_mac[6];
555 u8 pf_wol_mac[6];
556};
557
558I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
559
560/* Manage MAC Address Write Command (0x0108) */
561struct i40e_aqc_mac_address_write {
562 __le16 command_flags;
563#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
564#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
565#define I40E_AQC_WRITE_TYPE_PORT 0x8000
566#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
567#define I40E_AQC_WRITE_TYPE_MASK 0xC000
568
569 __le16 mac_sah;
570 __le32 mac_sal;
571 u8 reserved[8];
572};
573
574I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
575
576/* PXE commands (0x011x) */
577
578/* Clear PXE Command and response (direct 0x0110) */
579struct i40e_aqc_clear_pxe {
580 u8 rx_cnt;
581 u8 reserved[15];
582};
583
584I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
585
586/* Set WoL Filter (0x0120) */
587
588struct i40e_aqc_set_wol_filter {
589 __le16 filter_index;
590#define I40E_AQC_MAX_NUM_WOL_FILTERS 8
591#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
592#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
593 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
594
595#define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
596#define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
597 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
598 __le16 cmd_flags;
599#define I40E_AQC_SET_WOL_FILTER 0x8000
600#define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
601#define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
602#define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
603#define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
604 __le16 valid_flags;
605#define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
606#define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
607 u8 reserved[2];
608 __le32 address_high;
609 __le32 address_low;
610};
611
612I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter);
613
614struct i40e_aqc_set_wol_filter_data {
615 u8 filter[128];
616 u8 mask[16];
617};
618
619I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
620
621/* Get Wake Reason (0x0121) */
622
623struct i40e_aqc_get_wake_reason_completion {
624 u8 reserved_1[2];
625 __le16 wake_reason;
626#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
627#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
628 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
629#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
630#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
631 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
632 u8 reserved_2[12];
633};
634
635I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion);
636
637/* Switch configuration commands (0x02xx) */
638
639/* Used by many indirect commands that only pass an seid and a buffer in the
640 * command
641 */
642struct i40e_aqc_switch_seid {
643 __le16 seid;
644 u8 reserved[6];
645 __le32 addr_high;
646 __le32 addr_low;
647};
648
649I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
650
651/* Get Switch Configuration command (indirect 0x0200)
652 * uses i40e_aqc_switch_seid for the descriptor
653 */
654struct i40e_aqc_get_switch_config_header_resp {
655 __le16 num_reported;
656 __le16 num_total;
657 u8 reserved[12];
658};
659
660I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
661
662struct i40e_aqc_switch_config_element_resp {
663 u8 element_type;
664#define I40E_AQ_SW_ELEM_TYPE_MAC 1
665#define I40E_AQ_SW_ELEM_TYPE_PF 2
666#define I40E_AQ_SW_ELEM_TYPE_VF 3
667#define I40E_AQ_SW_ELEM_TYPE_EMP 4
668#define I40E_AQ_SW_ELEM_TYPE_BMC 5
669#define I40E_AQ_SW_ELEM_TYPE_PV 16
670#define I40E_AQ_SW_ELEM_TYPE_VEB 17
671#define I40E_AQ_SW_ELEM_TYPE_PA 18
672#define I40E_AQ_SW_ELEM_TYPE_VSI 19
673 u8 revision;
674#define I40E_AQ_SW_ELEM_REV_1 1
675 __le16 seid;
676 __le16 uplink_seid;
677 __le16 downlink_seid;
678 u8 reserved[3];
679 u8 connection_type;
680#define I40E_AQ_CONN_TYPE_REGULAR 0x1
681#define I40E_AQ_CONN_TYPE_DEFAULT 0x2
682#define I40E_AQ_CONN_TYPE_CASCADED 0x3
683 __le16 scheduler_id;
684 __le16 element_info;
685};
686
687I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
688
689/* Get Switch Configuration (indirect 0x0200)
690 * an array of elements are returned in the response buffer
691 * the first in the array is the header, remainder are elements
692 */
693struct i40e_aqc_get_switch_config_resp {
694 struct i40e_aqc_get_switch_config_header_resp header;
695 struct i40e_aqc_switch_config_element_resp element[1];
696};
697
698I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
699
700/* Add Statistics (direct 0x0201)
701 * Remove Statistics (direct 0x0202)
702 */
703struct i40e_aqc_add_remove_statistics {
704 __le16 seid;
705 __le16 vlan;
706 __le16 stat_index;
707 u8 reserved[10];
708};
709
710I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
711
712/* Set Port Parameters command (direct 0x0203) */
713struct i40e_aqc_set_port_parameters {
714 __le16 command_flags;
715#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
716#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
717#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
718 __le16 bad_frame_vsi;
719#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
720#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
721 __le16 default_seid; /* reserved for command */
722 u8 reserved[10];
723};
724
725I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
726
727/* Get Switch Resource Allocation (indirect 0x0204) */
728struct i40e_aqc_get_switch_resource_alloc {
729 u8 num_entries; /* reserved for command */
730 u8 reserved[7];
731 __le32 addr_high;
732 __le32 addr_low;
733};
734
735I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
736
737/* expect an array of these structs in the response buffer */
738struct i40e_aqc_switch_resource_alloc_element_resp {
739 u8 resource_type;
740#define I40E_AQ_RESOURCE_TYPE_VEB 0x0
741#define I40E_AQ_RESOURCE_TYPE_VSI 0x1
742#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
743#define I40E_AQ_RESOURCE_TYPE_STAG 0x3
744#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
745#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
746#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
747#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
748#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
749#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
750#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
751#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
752#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
753#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
754#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
755#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
756#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
757#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
758#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
759 u8 reserved1;
760 __le16 guaranteed;
761 __le16 total;
762 __le16 used;
763 __le16 total_unalloced;
764 u8 reserved2[6];
765};
766
767I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
768
769/* Set Switch Configuration (direct 0x0205) */
770struct i40e_aqc_set_switch_config {
771 __le16 flags;
772/* flags used for both fields below */
773#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
774#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
775 __le16 valid_flags;
776 /* The ethertype in switch_tag is dropped on ingress and used
777 * internally by the switch. Set this to zero for the default
778 * of 0x88a8 (802.1ad). Should be zero for firmware API
779 * versions lower than 1.7.
780 */
781 __le16 switch_tag;
782 /* The ethertypes in first_tag and second_tag are used to
783 * match the outer and inner VLAN tags (respectively) when HW
784 * double VLAN tagging is enabled via the set port parameters
785 * AQ command. Otherwise these are both ignored. Set them to
786 * zero for their defaults of 0x8100 (802.1Q). Should be zero
787 * for firmware API versions lower than 1.7.
788 */
789 __le16 first_tag;
790 __le16 second_tag;
791 u8 reserved[6];
792};
793
794I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
795
796/* Read Receive control registers (direct 0x0206)
797 * Write Receive control registers (direct 0x0207)
798 * used for accessing Rx control registers that can be
799 * slow and need special handling when under high Rx load
800 */
801struct i40e_aqc_rx_ctl_reg_read_write {
802 __le32 reserved1;
803 __le32 address;
804 __le32 reserved2;
805 __le32 value;
806};
807
808I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
809
810/* Add VSI (indirect 0x0210)
811 * this indirect command uses struct i40e_aqc_vsi_properties_data
812 * as the indirect buffer (128 bytes)
813 *
814 * Update VSI (indirect 0x211)
815 * uses the same data structure as Add VSI
816 *
817 * Get VSI (indirect 0x0212)
818 * uses the same completion and data structure as Add VSI
819 */
820struct i40e_aqc_add_get_update_vsi {
821 __le16 uplink_seid;
822 u8 connection_type;
823#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
824#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
825#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
826 u8 reserved1;
827 u8 vf_id;
828 u8 reserved2;
829 __le16 vsi_flags;
830#define I40E_AQ_VSI_TYPE_SHIFT 0x0
831#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
832#define I40E_AQ_VSI_TYPE_VF 0x0
833#define I40E_AQ_VSI_TYPE_VMDQ2 0x1
834#define I40E_AQ_VSI_TYPE_PF 0x2
835#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
836#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
837 __le32 addr_high;
838 __le32 addr_low;
839};
840
841I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
842
843struct i40e_aqc_add_get_update_vsi_completion {
844 __le16 seid;
845 __le16 vsi_number;
846 __le16 vsi_used;
847 __le16 vsi_free;
848 __le32 addr_high;
849 __le32 addr_low;
850};
851
852I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
853
854struct i40e_aqc_vsi_properties_data {
855 /* first 96 byte are written by SW */
856 __le16 valid_sections;
857#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
858#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
859#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
860#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
861#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
862#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
863#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
864#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
865#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
866#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
867 /* switch section */
868 __le16 switch_id; /* 12bit id combined with flags below */
869#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
870#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
871#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
872#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
873#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
874 u8 sw_reserved[2];
875 /* security section */
876 u8 sec_flags;
877#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
878#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
879#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
880 u8 sec_reserved;
881 /* VLAN section */
882 __le16 pvid; /* VLANS include priority bits */
883 __le16 fcoe_pvid;
884 u8 port_vlan_flags;
885#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
886#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
887 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
888#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
889#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
890#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
891#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
892#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
893#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
894 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
895#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
896#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
897#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
898#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
899 u8 pvlan_reserved[3];
900 /* ingress egress up sections */
901 __le32 ingress_table; /* bitmap, 3 bits per up */
902#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
903#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
904 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
905#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
906#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
907 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
908#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
909#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
910 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
911#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
912#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
913 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
914#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
915#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
916 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
917#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
918#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
919 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
920#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
921#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
922 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
923#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
924#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
925 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
926 __le32 egress_table; /* same defines as for ingress table */
927 /* cascaded PV section */
928 __le16 cas_pv_tag;
929 u8 cas_pv_flags;
930#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
931#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
932 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
933#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
934#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
935#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
936#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
937#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
938#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
939 u8 cas_pv_reserved;
940 /* queue mapping section */
941 __le16 mapping_flags;
942#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
943#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
944 __le16 queue_mapping[16];
945#define I40E_AQ_VSI_QUEUE_SHIFT 0x0
946#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
947 __le16 tc_mapping[8];
948#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
949#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
950 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
951#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
952#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
953 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
954 /* queueing option section */
955 u8 queueing_opt_flags;
956#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
957#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
958#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
959#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
960#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
961#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
962 u8 queueing_opt_reserved[3];
963 /* scheduler section */
964 u8 up_enable_bits;
965 u8 sched_reserved;
966 /* outer up section */
967 __le32 outer_up_table; /* same structure and defines as ingress tbl */
968 u8 cmd_reserved[8];
969 /* last 32 bytes are written by FW */
970 __le16 qs_handle[8];
971#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
972 __le16 stat_counter_idx;
973 __le16 sched_id;
974 u8 resp_reserved[12];
975};
976
977I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
978
979/* Add Port Virtualizer (direct 0x0220)
980 * also used for update PV (direct 0x0221) but only flags are used
981 * (IS_CTRL_PORT only works on add PV)
982 */
983struct i40e_aqc_add_update_pv {
984 __le16 command_flags;
985#define I40E_AQC_PV_FLAG_PV_TYPE 0x1
986#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
987#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
988#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
989 __le16 uplink_seid;
990 __le16 connected_seid;
991 u8 reserved[10];
992};
993
994I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
995
996struct i40e_aqc_add_update_pv_completion {
997 /* reserved for update; for add also encodes error if rc == ENOSPC */
998 __le16 pv_seid;
999#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
1000#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
1001#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
1002#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
1003 u8 reserved[14];
1004};
1005
1006I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
1007
1008/* Get PV Params (direct 0x0222)
1009 * uses i40e_aqc_switch_seid for the descriptor
1010 */
1011
1012struct i40e_aqc_get_pv_params_completion {
1013 __le16 seid;
1014 __le16 default_stag;
1015 __le16 pv_flags; /* same flags as add_pv */
1016#define I40E_AQC_GET_PV_PV_TYPE 0x1
1017#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1018#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1019 u8 reserved[8];
1020 __le16 default_port_seid;
1021};
1022
1023I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
1024
1025/* Add VEB (direct 0x0230) */
1026struct i40e_aqc_add_veb {
1027 __le16 uplink_seid;
1028 __le16 downlink_seid;
1029 __le16 veb_flags;
1030#define I40E_AQC_ADD_VEB_FLOATING 0x1
1031#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
1032#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1033 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1034#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1035#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1036#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1037#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1038 u8 enable_tcs;
1039 u8 reserved[9];
1040};
1041
1042I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
1043
1044struct i40e_aqc_add_veb_completion {
1045 u8 reserved[6];
1046 __le16 switch_seid;
1047 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1048 __le16 veb_seid;
1049#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1050#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1051#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1052#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1053 __le16 statistic_index;
1054 __le16 vebs_used;
1055 __le16 vebs_free;
1056};
1057
1058I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
1059
1060/* Get VEB Parameters (direct 0x0232)
1061 * uses i40e_aqc_switch_seid for the descriptor
1062 */
1063struct i40e_aqc_get_veb_parameters_completion {
1064 __le16 seid;
1065 __le16 switch_id;
1066 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1067 __le16 statistic_index;
1068 __le16 vebs_used;
1069 __le16 vebs_free;
1070 u8 reserved[4];
1071};
1072
1073I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
1074
1075/* Delete Element (direct 0x0243)
1076 * uses the generic i40e_aqc_switch_seid
1077 */
1078
1079/* Add MAC-VLAN (indirect 0x0250) */
1080
1081/* used for the command for most vlan commands */
1082struct i40e_aqc_macvlan {
1083 __le16 num_addresses;
1084 __le16 seid[3];
1085#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1086#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1087 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1088#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1089 __le32 addr_high;
1090 __le32 addr_low;
1091};
1092
1093I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
1094
1095/* indirect data for command and response */
1096struct i40e_aqc_add_macvlan_element_data {
1097 u8 mac_addr[6];
1098 __le16 vlan_tag;
1099 __le16 flags;
1100#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1101#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1102#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1103#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1104#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1105 __le16 queue_number;
1106#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1107#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1108 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1109 /* response section */
1110 u8 match_method;
1111#define I40E_AQC_MM_PERFECT_MATCH 0x01
1112#define I40E_AQC_MM_HASH_MATCH 0x02
1113#define I40E_AQC_MM_ERR_NO_RES 0xFF
1114 u8 reserved1[3];
1115};
1116
1117struct i40e_aqc_add_remove_macvlan_completion {
1118 __le16 perfect_mac_used;
1119 __le16 perfect_mac_free;
1120 __le16 unicast_hash_free;
1121 __le16 multicast_hash_free;
1122 __le32 addr_high;
1123 __le32 addr_low;
1124};
1125
1126I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1127
1128/* Remove MAC-VLAN (indirect 0x0251)
1129 * uses i40e_aqc_macvlan for the descriptor
1130 * data points to an array of num_addresses of elements
1131 */
1132
1133struct i40e_aqc_remove_macvlan_element_data {
1134 u8 mac_addr[6];
1135 __le16 vlan_tag;
1136 u8 flags;
1137#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1138#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1139#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1140#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1141 u8 reserved[3];
1142 /* reply section */
1143 u8 error_code;
1144#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1145#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1146 u8 reply_reserved[3];
1147};
1148
1149/* Add VLAN (indirect 0x0252)
1150 * Remove VLAN (indirect 0x0253)
1151 * use the generic i40e_aqc_macvlan for the command
1152 */
1153struct i40e_aqc_add_remove_vlan_element_data {
1154 __le16 vlan_tag;
1155 u8 vlan_flags;
1156/* flags for add VLAN */
1157#define I40E_AQC_ADD_VLAN_LOCAL 0x1
1158#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1159#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1160#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1161#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1162#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1163#define I40E_AQC_VLAN_PTYPE_SHIFT 3
1164#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1165#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1166#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1167#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1168#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1169/* flags for remove VLAN */
1170#define I40E_AQC_REMOVE_VLAN_ALL 0x1
1171 u8 reserved;
1172 u8 result;
1173/* flags for add VLAN */
1174#define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1175#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1176#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1177/* flags for remove VLAN */
1178#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1179#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1180 u8 reserved1[3];
1181};
1182
1183struct i40e_aqc_add_remove_vlan_completion {
1184 u8 reserved[4];
1185 __le16 vlans_used;
1186 __le16 vlans_free;
1187 __le32 addr_high;
1188 __le32 addr_low;
1189};
1190
1191/* Set VSI Promiscuous Modes (direct 0x0254) */
1192struct i40e_aqc_set_vsi_promiscuous_modes {
1193 __le16 promiscuous_flags;
1194 __le16 valid_flags;
1195/* flags used for both fields above */
1196#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1197#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1198#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1199#define I40E_AQC_SET_VSI_DEFAULT 0x08
1200#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1201#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1202 __le16 seid;
1203#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1204 __le16 vlan_tag;
1205#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1206#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1207 u8 reserved[8];
1208};
1209
1210I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1211
1212/* Add S/E-tag command (direct 0x0255)
1213 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1214 */
1215struct i40e_aqc_add_tag {
1216 __le16 flags;
1217#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1218 __le16 seid;
1219#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1220#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1221 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1222 __le16 tag;
1223 __le16 queue_number;
1224 u8 reserved[8];
1225};
1226
1227I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1228
1229struct i40e_aqc_add_remove_tag_completion {
1230 u8 reserved[12];
1231 __le16 tags_used;
1232 __le16 tags_free;
1233};
1234
1235I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1236
1237/* Remove S/E-tag command (direct 0x0256)
1238 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1239 */
1240struct i40e_aqc_remove_tag {
1241 __le16 seid;
1242#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1243#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1244 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1245 __le16 tag;
1246 u8 reserved[12];
1247};
1248
1249I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1250
1251/* Add multicast E-Tag (direct 0x0257)
1252 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1253 * and no external data
1254 */
1255struct i40e_aqc_add_remove_mcast_etag {
1256 __le16 pv_seid;
1257 __le16 etag;
1258 u8 num_unicast_etags;
1259 u8 reserved[3];
1260 __le32 addr_high; /* address of array of 2-byte s-tags */
1261 __le32 addr_low;
1262};
1263
1264I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1265
1266struct i40e_aqc_add_remove_mcast_etag_completion {
1267 u8 reserved[4];
1268 __le16 mcast_etags_used;
1269 __le16 mcast_etags_free;
1270 __le32 addr_high;
1271 __le32 addr_low;
1272
1273};
1274
1275I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1276
1277/* Update S/E-Tag (direct 0x0259) */
1278struct i40e_aqc_update_tag {
1279 __le16 seid;
1280#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1281#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1282 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1283 __le16 old_tag;
1284 __le16 new_tag;
1285 u8 reserved[10];
1286};
1287
1288I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1289
1290struct i40e_aqc_update_tag_completion {
1291 u8 reserved[12];
1292 __le16 tags_used;
1293 __le16 tags_free;
1294};
1295
1296I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1297
1298/* Add Control Packet filter (direct 0x025A)
1299 * Remove Control Packet filter (direct 0x025B)
1300 * uses the i40e_aqc_add_oveb_cloud,
1301 * and the generic direct completion structure
1302 */
1303struct i40e_aqc_add_remove_control_packet_filter {
1304 u8 mac[6];
1305 __le16 etype;
1306 __le16 flags;
1307#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1308#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1309#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1310#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1311#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1312 __le16 seid;
1313#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1314#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1315 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1316 __le16 queue;
1317 u8 reserved[2];
1318};
1319
1320I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1321
1322struct i40e_aqc_add_remove_control_packet_filter_completion {
1323 __le16 mac_etype_used;
1324 __le16 etype_used;
1325 __le16 mac_etype_free;
1326 __le16 etype_free;
1327 u8 reserved[8];
1328};
1329
1330I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1331
1332/* Add Cloud filters (indirect 0x025C)
1333 * Remove Cloud filters (indirect 0x025D)
1334 * uses the i40e_aqc_add_remove_cloud_filters,
1335 * and the generic indirect completion structure
1336 */
1337struct i40e_aqc_add_remove_cloud_filters {
1338 u8 num_filters;
1339 u8 reserved;
1340 __le16 seid;
1341#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1342#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1343 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1344 u8 big_buffer_flag;
1345#define I40E_AQC_ADD_CLOUD_CMD_BB 1
1346 u8 reserved2[3];
1347 __le32 addr_high;
1348 __le32 addr_low;
1349};
1350
1351I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1352
1353struct i40e_aqc_cloud_filters_element_data {
1354 u8 outer_mac[6];
1355 u8 inner_mac[6];
1356 __le16 inner_vlan;
1357 union {
1358 struct {
1359 u8 reserved[12];
1360 u8 data[4];
1361 } v4;
1362 struct {
1363 u8 data[16];
1364 } v6;
1365 struct {
1366 __le16 data[8];
1367 } raw_v6;
1368 } ipaddr;
1369 __le16 flags;
1370#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1371#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1372 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1373/* 0x0000 reserved */
1374#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1375/* 0x0002 reserved */
1376#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1377#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1378/* 0x0005 reserved */
1379#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1380/* 0x0007 reserved */
1381/* 0x0008 reserved */
1382#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1383#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1384#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1385#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1386/* 0x0010 to 0x0017 is for custom filters */
1387#define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */
1388#define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */
1389#define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */
1390
1391#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1392#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1393#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1394#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1395#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1396
1397#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1398#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1399#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1400#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1401#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1402#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1403#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1404#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1405
1406#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1407#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1408#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1409
1410 __le32 tenant_id;
1411 u8 reserved[4];
1412 __le16 queue_number;
1413#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1414#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1415 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1416 u8 reserved2[14];
1417 /* response section */
1418 u8 allocation_result;
1419#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1420#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1421 u8 response_reserved[7];
1422};
1423
1424I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1425
1426/* i40e_aqc_cloud_filters_element_bb is used when
1427 * I40E_AQC_ADD_CLOUD_CMD_BB flag is set.
1428 */
1429struct i40e_aqc_cloud_filters_element_bb {
1430 struct i40e_aqc_cloud_filters_element_data element;
1431 u16 general_fields[32];
1432#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1433#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
1434#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
1435#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
1436#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
1437#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
1438#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
1439#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
1440#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
1441#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
1442#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
1443#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
1444#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
1445#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
1446#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
1447#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
1448#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
1449#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
1450#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
1451#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
1452#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
1453#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
1454#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
1455#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
1456#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
1457#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
1458#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
1459#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
1460#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
1461#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
1462#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
1463};
1464
1465I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1466
1467struct i40e_aqc_remove_cloud_filters_completion {
1468 __le16 perfect_ovlan_used;
1469 __le16 perfect_ovlan_free;
1470 __le16 vlan_used;
1471 __le16 vlan_free;
1472 __le32 addr_high;
1473 __le32 addr_low;
1474};
1475
1476I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1477
1478/* Replace filter Command 0x025F
1479 * uses the i40e_aqc_replace_cloud_filters,
1480 * and the generic indirect completion structure
1481 */
1482struct i40e_filter_data {
1483 u8 filter_type;
1484 u8 input[3];
1485};
1486
1487I40E_CHECK_STRUCT_LEN(4, i40e_filter_data);
1488
1489struct i40e_aqc_replace_cloud_filters_cmd {
1490 u8 valid_flags;
1491#define I40E_AQC_REPLACE_L1_FILTER 0x0
1492#define I40E_AQC_REPLACE_CLOUD_FILTER 0x1
1493#define I40E_AQC_GET_CLOUD_FILTERS 0x2
1494#define I40E_AQC_MIRROR_CLOUD_FILTER 0x4
1495#define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8
1496 u8 old_filter_type;
1497 u8 new_filter_type;
1498 u8 tr_bit;
1499 u8 reserved[4];
1500 __le32 addr_high;
1501 __le32 addr_low;
1502};
1503
1504I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd);
1505
1506struct i40e_aqc_replace_cloud_filters_cmd_buf {
1507 u8 data[32];
1508/* Filter type INPUT codes*/
1509#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3
1510#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED BIT(7)
1511
1512/* Field Vector offsets */
1513#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0
1514#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6
1515#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7
1516#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8
1517#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9
1518#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10
1519#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11
1520#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12
1521/* big FLU */
1522#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14
1523/* big FLU */
1524#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15
1525
1526#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37
1527 struct i40e_filter_data filters[8];
1528};
1529
1530I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1531
1532/* Add Mirror Rule (indirect or direct 0x0260)
1533 * Delete Mirror Rule (indirect or direct 0x0261)
1534 * note: some rule types (4,5) do not use an external buffer.
1535 * take care to set the flags correctly.
1536 */
1537struct i40e_aqc_add_delete_mirror_rule {
1538 __le16 seid;
1539 __le16 rule_type;
1540#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1541#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1542 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1543#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1544#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1545#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1546#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1547#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1548 __le16 num_entries;
1549 __le16 destination; /* VSI for add, rule id for delete */
1550 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1551 __le32 addr_low;
1552};
1553
1554I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1555
1556struct i40e_aqc_add_delete_mirror_rule_completion {
1557 u8 reserved[2];
1558 __le16 rule_id; /* only used on add */
1559 __le16 mirror_rules_used;
1560 __le16 mirror_rules_free;
1561 __le32 addr_high;
1562 __le32 addr_low;
1563};
1564
1565I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1566
1567/* Dynamic Device Personalization */
1568struct i40e_aqc_write_personalization_profile {
1569 u8 flags;
1570 u8 reserved[3];
1571 __le32 profile_track_id;
1572 __le32 addr_high;
1573 __le32 addr_low;
1574};
1575
1576I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile);
1577
1578struct i40e_aqc_write_ddp_resp {
1579 __le32 error_offset;
1580 __le32 error_info;
1581 __le32 addr_high;
1582 __le32 addr_low;
1583};
1584
1585struct i40e_aqc_get_applied_profiles {
1586 u8 flags;
1587#define I40E_AQC_GET_DDP_GET_CONF 0x1
1588#define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2
1589 u8 rsv[3];
1590 __le32 reserved;
1591 __le32 addr_high;
1592 __le32 addr_low;
1593};
1594
1595I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles);
1596
1597/* DCB 0x03xx*/
1598
1599/* PFC Ignore (direct 0x0301)
1600 * the command and response use the same descriptor structure
1601 */
1602struct i40e_aqc_pfc_ignore {
1603 u8 tc_bitmap;
1604 u8 command_flags; /* unused on response */
1605#define I40E_AQC_PFC_IGNORE_SET 0x80
1606#define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1607 u8 reserved[14];
1608};
1609
1610I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1611
1612/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1613 * with no parameters
1614 */
1615
1616/* TX scheduler 0x04xx */
1617
1618/* Almost all the indirect commands use
1619 * this generic struct to pass the SEID in param0
1620 */
1621struct i40e_aqc_tx_sched_ind {
1622 __le16 vsi_seid;
1623 u8 reserved[6];
1624 __le32 addr_high;
1625 __le32 addr_low;
1626};
1627
1628I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1629
1630/* Several commands respond with a set of queue set handles */
1631struct i40e_aqc_qs_handles_resp {
1632 __le16 qs_handles[8];
1633};
1634
1635/* Configure VSI BW limits (direct 0x0400) */
1636struct i40e_aqc_configure_vsi_bw_limit {
1637 __le16 vsi_seid;
1638 u8 reserved[2];
1639 __le16 credit;
1640 u8 reserved1[2];
1641 u8 max_credit; /* 0-3, limit = 2^max */
1642 u8 reserved2[7];
1643};
1644
1645I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1646
1647/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1648 * responds with i40e_aqc_qs_handles_resp
1649 */
1650struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1651 u8 tc_valid_bits;
1652 u8 reserved[15];
1653 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1654
1655 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1656 __le16 tc_bw_max[2];
1657 u8 reserved1[28];
1658};
1659
1660I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1661
1662/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1663 * responds with i40e_aqc_qs_handles_resp
1664 */
1665struct i40e_aqc_configure_vsi_tc_bw_data {
1666 u8 tc_valid_bits;
1667 u8 reserved[3];
1668 u8 tc_bw_credits[8];
1669 u8 reserved1[4];
1670 __le16 qs_handles[8];
1671};
1672
1673I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1674
1675/* Query vsi bw configuration (indirect 0x0408) */
1676struct i40e_aqc_query_vsi_bw_config_resp {
1677 u8 tc_valid_bits;
1678 u8 tc_suspended_bits;
1679 u8 reserved[14];
1680 __le16 qs_handles[8];
1681 u8 reserved1[4];
1682 __le16 port_bw_limit;
1683 u8 reserved2[2];
1684 u8 max_bw; /* 0-3, limit = 2^max */
1685 u8 reserved3[23];
1686};
1687
1688I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1689
1690/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1691struct i40e_aqc_query_vsi_ets_sla_config_resp {
1692 u8 tc_valid_bits;
1693 u8 reserved[3];
1694 u8 share_credits[8];
1695 __le16 credits[8];
1696
1697 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1698 __le16 tc_bw_max[2];
1699};
1700
1701I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1702
1703/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1704struct i40e_aqc_configure_switching_comp_bw_limit {
1705 __le16 seid;
1706 u8 reserved[2];
1707 __le16 credit;
1708 u8 reserved1[2];
1709 u8 max_bw; /* 0-3, limit = 2^max */
1710 u8 reserved2[7];
1711};
1712
1713I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1714
1715/* Enable Physical Port ETS (indirect 0x0413)
1716 * Modify Physical Port ETS (indirect 0x0414)
1717 * Disable Physical Port ETS (indirect 0x0415)
1718 */
1719struct i40e_aqc_configure_switching_comp_ets_data {
1720 u8 reserved[4];
1721 u8 tc_valid_bits;
1722 u8 seepage;
1723#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1724 u8 tc_strict_priority_flags;
1725 u8 reserved1[17];
1726 u8 tc_bw_share_credits[8];
1727 u8 reserved2[96];
1728};
1729
1730I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1731
1732/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1733struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1734 u8 tc_valid_bits;
1735 u8 reserved[15];
1736 __le16 tc_bw_credit[8];
1737
1738 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1739 __le16 tc_bw_max[2];
1740 u8 reserved1[28];
1741};
1742
1743I40E_CHECK_STRUCT_LEN(0x40,
1744 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1745
1746/* Configure Switching Component Bandwidth Allocation per Tc
1747 * (indirect 0x0417)
1748 */
1749struct i40e_aqc_configure_switching_comp_bw_config_data {
1750 u8 tc_valid_bits;
1751 u8 reserved[2];
1752 u8 absolute_credits; /* bool */
1753 u8 tc_bw_share_credits[8];
1754 u8 reserved1[20];
1755};
1756
1757I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1758
1759/* Query Switching Component Configuration (indirect 0x0418) */
1760struct i40e_aqc_query_switching_comp_ets_config_resp {
1761 u8 tc_valid_bits;
1762 u8 reserved[35];
1763 __le16 port_bw_limit;
1764 u8 reserved1[2];
1765 u8 tc_bw_max; /* 0-3, limit = 2^max */
1766 u8 reserved2[23];
1767};
1768
1769I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1770
1771/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1772struct i40e_aqc_query_port_ets_config_resp {
1773 u8 reserved[4];
1774 u8 tc_valid_bits;
1775 u8 reserved1;
1776 u8 tc_strict_priority_bits;
1777 u8 reserved2;
1778 u8 tc_bw_share_credits[8];
1779 __le16 tc_bw_limits[8];
1780
1781 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1782 __le16 tc_bw_max[2];
1783 u8 reserved3[32];
1784};
1785
1786I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1787
1788/* Query Switching Component Bandwidth Allocation per Traffic Type
1789 * (indirect 0x041A)
1790 */
1791struct i40e_aqc_query_switching_comp_bw_config_resp {
1792 u8 tc_valid_bits;
1793 u8 reserved[2];
1794 u8 absolute_credits_enable; /* bool */
1795 u8 tc_bw_share_credits[8];
1796 __le16 tc_bw_limits[8];
1797
1798 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1799 __le16 tc_bw_max[2];
1800};
1801
1802I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1803
1804/* Suspend/resume port TX traffic
1805 * (direct 0x041B and 0x041C) uses the generic SEID struct
1806 */
1807
1808/* Configure partition BW
1809 * (indirect 0x041D)
1810 */
1811struct i40e_aqc_configure_partition_bw_data {
1812 __le16 pf_valid_bits;
1813 u8 min_bw[16]; /* guaranteed bandwidth */
1814 u8 max_bw[16]; /* bandwidth limit */
1815};
1816
1817I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1818
1819/* Get and set the active HMC resource profile and status.
1820 * (direct 0x0500) and (direct 0x0501)
1821 */
1822struct i40e_aq_get_set_hmc_resource_profile {
1823 u8 pm_profile;
1824 u8 pe_vf_enabled;
1825 u8 reserved[14];
1826};
1827
1828I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1829
1830enum i40e_aq_hmc_profile {
1831 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1832 I40E_HMC_PROFILE_DEFAULT = 1,
1833 I40E_HMC_PROFILE_FAVOR_VF = 2,
1834 I40E_HMC_PROFILE_EQUAL = 3,
1835};
1836
1837/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1838
1839/* set in param0 for get phy abilities to report qualified modules */
1840#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1841#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1842
1843enum i40e_aq_phy_type {
1844 I40E_PHY_TYPE_SGMII = 0x0,
1845 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1846 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1847 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1848 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1849 I40E_PHY_TYPE_XAUI = 0x5,
1850 I40E_PHY_TYPE_XFI = 0x6,
1851 I40E_PHY_TYPE_SFI = 0x7,
1852 I40E_PHY_TYPE_XLAUI = 0x8,
1853 I40E_PHY_TYPE_XLPPI = 0x9,
1854 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1855 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1856 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1857 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1858 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1859 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1860 I40E_PHY_TYPE_100BASE_TX = 0x11,
1861 I40E_PHY_TYPE_1000BASE_T = 0x12,
1862 I40E_PHY_TYPE_10GBASE_T = 0x13,
1863 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1864 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1865 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1866 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1867 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1868 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1869 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1870 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1871 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1872 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1873 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1874 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1875 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1876 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1877 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1878 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1879 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1880 I40E_PHY_TYPE_MAX,
1881 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1882 I40E_PHY_TYPE_EMPTY = 0xFE,
1883 I40E_PHY_TYPE_DEFAULT = 0xFF,
1884};
1885
1886#define I40E_LINK_SPEED_100MB_SHIFT 0x1
1887#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1888#define I40E_LINK_SPEED_10GB_SHIFT 0x3
1889#define I40E_LINK_SPEED_40GB_SHIFT 0x4
1890#define I40E_LINK_SPEED_20GB_SHIFT 0x5
1891#define I40E_LINK_SPEED_25GB_SHIFT 0x6
1892
1893enum i40e_aq_link_speed {
1894 I40E_LINK_SPEED_UNKNOWN = 0,
1895 I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT),
1896 I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
1897 I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT),
1898 I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT),
1899 I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT),
1900 I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT),
1901};
1902
1903struct i40e_aqc_module_desc {
1904 u8 oui[3];
1905 u8 reserved1;
1906 u8 part_number[16];
1907 u8 revision[4];
1908 u8 reserved2[8];
1909};
1910
1911I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1912
1913struct i40e_aq_get_phy_abilities_resp {
1914 __le32 phy_type; /* bitmap using the above enum for offsets */
1915 u8 link_speed; /* bitmap using the above enum bit patterns */
1916 u8 abilities;
1917#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1918#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1919#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1920#define I40E_AQ_PHY_LINK_ENABLED 0x08
1921#define I40E_AQ_PHY_AN_ENABLED 0x10
1922#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1923#define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
1924#define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
1925 __le16 eee_capability;
1926#define I40E_AQ_EEE_100BASE_TX 0x0002
1927#define I40E_AQ_EEE_1000BASE_T 0x0004
1928#define I40E_AQ_EEE_10GBASE_T 0x0008
1929#define I40E_AQ_EEE_1000BASE_KX 0x0010
1930#define I40E_AQ_EEE_10GBASE_KX4 0x0020
1931#define I40E_AQ_EEE_10GBASE_KR 0x0040
1932 __le32 eeer_val;
1933 u8 d3_lpan;
1934#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1935 u8 phy_type_ext;
1936#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1937#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1938#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1939#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1940#define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10
1941#define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20
1942 u8 fec_cfg_curr_mod_ext_info;
1943#define I40E_AQ_ENABLE_FEC_KR 0x01
1944#define I40E_AQ_ENABLE_FEC_RS 0x02
1945#define I40E_AQ_REQUEST_FEC_KR 0x04
1946#define I40E_AQ_REQUEST_FEC_RS 0x08
1947#define I40E_AQ_ENABLE_FEC_AUTO 0x10
1948#define I40E_AQ_FEC
1949#define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
1950#define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5
1951
1952 u8 ext_comp_code;
1953 u8 phy_id[4];
1954 u8 module_type[3];
1955 u8 qualified_module_count;
1956#define I40E_AQ_PHY_MAX_QMS 16
1957 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1958};
1959
1960I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1961
1962/* Set PHY Config (direct 0x0601) */
1963struct i40e_aq_set_phy_config { /* same bits as above in all */
1964 __le32 phy_type;
1965 u8 link_speed;
1966 u8 abilities;
1967/* bits 0-2 use the values from get_phy_abilities_resp */
1968#define I40E_AQ_PHY_ENABLE_LINK 0x08
1969#define I40E_AQ_PHY_ENABLE_AN 0x10
1970#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1971 __le16 eee_capability;
1972 __le32 eeer;
1973 u8 low_power_ctrl;
1974 u8 phy_type_ext;
1975#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01
1976#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02
1977#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
1978#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
1979 u8 fec_config;
1980#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
1981#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1)
1982#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2)
1983#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3)
1984#define I40E_AQ_SET_FEC_AUTO BIT(4)
1985#define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
1986#define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
1987 u8 reserved;
1988};
1989
1990I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1991
1992/* Set MAC Config command data structure (direct 0x0603) */
1993struct i40e_aq_set_mac_config {
1994 __le16 max_frame_size;
1995 u8 params;
1996#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1997#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1998#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1999#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
2000#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
2001#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
2002#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
2003#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
2004#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
2005#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
2006#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
2007#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
2008#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
2009#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
2010 u8 tx_timer_priority; /* bitmap */
2011 __le16 tx_timer_value;
2012 __le16 fc_refresh_threshold;
2013 u8 reserved[8];
2014};
2015
2016I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
2017
2018/* Restart Auto-Negotiation (direct 0x605) */
2019struct i40e_aqc_set_link_restart_an {
2020 u8 command;
2021#define I40E_AQ_PHY_RESTART_AN 0x02
2022#define I40E_AQ_PHY_LINK_ENABLE 0x04
2023 u8 reserved[15];
2024};
2025
2026I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
2027
2028/* Get Link Status cmd & response data structure (direct 0x0607) */
2029struct i40e_aqc_get_link_status {
2030 __le16 command_flags; /* only field set on command */
2031#define I40E_AQ_LSE_MASK 0x3
2032#define I40E_AQ_LSE_NOP 0x0
2033#define I40E_AQ_LSE_DISABLE 0x2
2034#define I40E_AQ_LSE_ENABLE 0x3
2035/* only response uses this flag */
2036#define I40E_AQ_LSE_IS_ENABLED 0x1
2037 u8 phy_type; /* i40e_aq_phy_type */
2038 u8 link_speed; /* i40e_aq_link_speed */
2039 u8 link_info;
2040#define I40E_AQ_LINK_UP 0x01 /* obsolete */
2041#define I40E_AQ_LINK_UP_FUNCTION 0x01
2042#define I40E_AQ_LINK_FAULT 0x02
2043#define I40E_AQ_LINK_FAULT_TX 0x04
2044#define I40E_AQ_LINK_FAULT_RX 0x08
2045#define I40E_AQ_LINK_FAULT_REMOTE 0x10
2046#define I40E_AQ_LINK_UP_PORT 0x20
2047#define I40E_AQ_MEDIA_AVAILABLE 0x40
2048#define I40E_AQ_SIGNAL_DETECT 0x80
2049 u8 an_info;
2050#define I40E_AQ_AN_COMPLETED 0x01
2051#define I40E_AQ_LP_AN_ABILITY 0x02
2052#define I40E_AQ_PD_FAULT 0x04
2053#define I40E_AQ_FEC_EN 0x08
2054#define I40E_AQ_PHY_LOW_POWER 0x10
2055#define I40E_AQ_LINK_PAUSE_TX 0x20
2056#define I40E_AQ_LINK_PAUSE_RX 0x40
2057#define I40E_AQ_QUALIFIED_MODULE 0x80
2058 u8 ext_info;
2059#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
2060#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
2061#define I40E_AQ_LINK_TX_SHIFT 0x02
2062#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
2063#define I40E_AQ_LINK_TX_ACTIVE 0x00
2064#define I40E_AQ_LINK_TX_DRAINED 0x01
2065#define I40E_AQ_LINK_TX_FLUSHED 0x03
2066#define I40E_AQ_LINK_FORCED_40G 0x10
2067/* 25G Error Codes */
2068#define I40E_AQ_25G_NO_ERR 0X00
2069#define I40E_AQ_25G_NOT_PRESENT 0X01
2070#define I40E_AQ_25G_NVM_CRC_ERR 0X02
2071#define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
2072#define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
2073#define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
2074 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
2075/* Since firmware API 1.7 loopback field keeps power class info as well */
2076#define I40E_AQ_LOOPBACK_MASK 0x07
2077#define I40E_AQ_PWR_CLASS_SHIFT_LB 6
2078#define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
2079 __le16 max_frame_size;
2080 u8 config;
2081#define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
2082#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
2083#define I40E_AQ_CONFIG_CRC_ENA 0x04
2084#define I40E_AQ_CONFIG_PACING_MASK 0x78
2085 union {
2086 struct {
2087 u8 power_desc;
2088#define I40E_AQ_LINK_POWER_CLASS_1 0x00
2089#define I40E_AQ_LINK_POWER_CLASS_2 0x01
2090#define I40E_AQ_LINK_POWER_CLASS_3 0x02
2091#define I40E_AQ_LINK_POWER_CLASS_4 0x03
2092#define I40E_AQ_PWR_CLASS_MASK 0x03
2093 u8 reserved[4];
2094 };
2095 struct {
2096 u8 link_type[4];
2097 u8 link_type_ext;
2098 };
2099 };
2100};
2101
2102I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
2103
2104/* Set event mask command (direct 0x613) */
2105struct i40e_aqc_set_phy_int_mask {
2106 u8 reserved[8];
2107 __le16 event_mask;
2108#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
2109#define I40E_AQ_EVENT_MEDIA_NA 0x0004
2110#define I40E_AQ_EVENT_LINK_FAULT 0x0008
2111#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
2112#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
2113#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
2114#define I40E_AQ_EVENT_AN_COMPLETED 0x0080
2115#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
2116#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2117 u8 reserved1[6];
2118};
2119
2120I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
2121
2122/* Get Local AN advt register (direct 0x0614)
2123 * Set Local AN advt register (direct 0x0615)
2124 * Get Link Partner AN advt register (direct 0x0616)
2125 */
2126struct i40e_aqc_an_advt_reg {
2127 __le32 local_an_reg0;
2128 __le16 local_an_reg1;
2129 u8 reserved[10];
2130};
2131
2132I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
2133
2134/* Set Loopback mode (0x0618) */
2135struct i40e_aqc_set_lb_mode {
2136 __le16 lb_mode;
2137#define I40E_AQ_LB_PHY_LOCAL 0x01
2138#define I40E_AQ_LB_PHY_REMOTE 0x02
2139#define I40E_AQ_LB_MAC_LOCAL 0x04
2140 u8 reserved[14];
2141};
2142
2143I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
2144
2145/* Set PHY Debug command (0x0622) */
2146struct i40e_aqc_set_phy_debug {
2147 u8 command_flags;
2148#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
2149#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
2150#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
2151 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2152#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
2153#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2154#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2155#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2156 u8 reserved[15];
2157};
2158
2159I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
2160
2161enum i40e_aq_phy_reg_type {
2162 I40E_AQC_PHY_REG_INTERNAL = 0x1,
2163 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
2164 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2165};
2166
2167/* Run PHY Activity (0x0626) */
2168struct i40e_aqc_run_phy_activity {
2169 __le16 activity_id;
2170 u8 flags;
2171 u8 reserved1;
2172 __le32 control;
2173 __le32 data;
2174 u8 reserved2[4];
2175};
2176
2177I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
2178
2179/* Set PHY Register command (0x0628) */
2180/* Get PHY Register command (0x0629) */
2181struct i40e_aqc_phy_register_access {
2182 u8 phy_interface;
2183#define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
2184#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1
2185#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
2186 u8 dev_address;
2187 u8 reserved1[2];
2188 __le32 reg_address;
2189 __le32 reg_value;
2190 u8 reserved2[4];
2191};
2192
2193I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access);
2194
2195/* NVM Read command (indirect 0x0701)
2196 * NVM Erase commands (direct 0x0702)
2197 * NVM Update commands (indirect 0x0703)
2198 */
2199struct i40e_aqc_nvm_update {
2200 u8 command_flags;
2201#define I40E_AQ_NVM_LAST_CMD 0x01
2202#define I40E_AQ_NVM_FLASH_ONLY 0x80
2203#define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
2204#define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
2205#define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2206#define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
2207 u8 module_pointer;
2208 __le16 length;
2209 __le32 offset;
2210 __le32 addr_high;
2211 __le32 addr_low;
2212};
2213
2214I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
2215
2216/* NVM Config Read (indirect 0x0704) */
2217struct i40e_aqc_nvm_config_read {
2218 __le16 cmd_flags;
2219#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
2220#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2221#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
2222 __le16 element_count;
2223 __le16 element_id; /* Feature/field ID */
2224 __le16 element_id_msw; /* MSWord of field ID */
2225 __le32 address_high;
2226 __le32 address_low;
2227};
2228
2229I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
2230
2231/* NVM Config Write (indirect 0x0705) */
2232struct i40e_aqc_nvm_config_write {
2233 __le16 cmd_flags;
2234 __le16 element_count;
2235 u8 reserved[4];
2236 __le32 address_high;
2237 __le32 address_low;
2238};
2239
2240I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
2241
2242/* Used for 0x0704 as well as for 0x0705 commands */
2243#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
2244#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2245 BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2246#define I40E_AQ_ANVM_FEATURE 0
2247#define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT)
2248struct i40e_aqc_nvm_config_data_feature {
2249 __le16 feature_id;
2250#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2251#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2252#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2253 __le16 feature_options;
2254 __le16 feature_selection;
2255};
2256
2257I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2258
2259struct i40e_aqc_nvm_config_data_immediate_field {
2260 __le32 field_id;
2261 __le32 field_value;
2262 __le16 field_options;
2263 __le16 reserved;
2264};
2265
2266I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2267
2268/* OEM Post Update (indirect 0x0720)
2269 * no command data struct used
2270 */
2271 struct i40e_aqc_nvm_oem_post_update {
2272#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2273 u8 sel_data;
2274 u8 reserved[7];
2275};
2276
2277I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2278
2279struct i40e_aqc_nvm_oem_post_update_buffer {
2280 u8 str_len;
2281 u8 dev_addr;
2282 __le16 eeprom_addr;
2283 u8 data[36];
2284};
2285
2286I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2287
2288/* Thermal Sensor (indirect 0x0721)
2289 * read or set thermal sensor configs and values
2290 * takes a sensor and command specific data buffer, not detailed here
2291 */
2292struct i40e_aqc_thermal_sensor {
2293 u8 sensor_action;
2294#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2295#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
2296#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
2297 u8 reserved[7];
2298 __le32 addr_high;
2299 __le32 addr_low;
2300};
2301
2302I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
2303
2304/* Send to PF command (indirect 0x0801) id is only used by PF
2305 * Send to VF command (indirect 0x0802) id is only used by PF
2306 * Send to Peer PF command (indirect 0x0803)
2307 */
2308struct i40e_aqc_pf_vf_message {
2309 __le32 id;
2310 u8 reserved[4];
2311 __le32 addr_high;
2312 __le32 addr_low;
2313};
2314
2315I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
2316
2317/* Alternate structure */
2318
2319/* Direct write (direct 0x0900)
2320 * Direct read (direct 0x0902)
2321 */
2322struct i40e_aqc_alternate_write {
2323 __le32 address0;
2324 __le32 data0;
2325 __le32 address1;
2326 __le32 data1;
2327};
2328
2329I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2330
2331/* Indirect write (indirect 0x0901)
2332 * Indirect read (indirect 0x0903)
2333 */
2334
2335struct i40e_aqc_alternate_ind_write {
2336 __le32 address;
2337 __le32 length;
2338 __le32 addr_high;
2339 __le32 addr_low;
2340};
2341
2342I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2343
2344/* Done alternate write (direct 0x0904)
2345 * uses i40e_aq_desc
2346 */
2347struct i40e_aqc_alternate_write_done {
2348 __le16 cmd_flags;
2349#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2350#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2351#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2352#define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2353 u8 reserved[14];
2354};
2355
2356I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2357
2358/* Set OEM mode (direct 0x0905) */
2359struct i40e_aqc_alternate_set_mode {
2360 __le32 mode;
2361#define I40E_AQ_ALTERNATE_MODE_NONE 0
2362#define I40E_AQ_ALTERNATE_MODE_OEM 1
2363 u8 reserved[12];
2364};
2365
2366I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2367
2368/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2369
2370/* async events 0x10xx */
2371
2372/* Lan Queue Overflow Event (direct, 0x1001) */
2373struct i40e_aqc_lan_overflow {
2374 __le32 prtdcb_rupto;
2375 __le32 otx_ctl;
2376 u8 reserved[8];
2377};
2378
2379I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2380
2381/* Get LLDP MIB (indirect 0x0A00) */
2382struct i40e_aqc_lldp_get_mib {
2383 u8 type;
2384 u8 reserved1;
2385#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2386#define I40E_AQ_LLDP_MIB_LOCAL 0x0
2387#define I40E_AQ_LLDP_MIB_REMOTE 0x1
2388#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2389#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2390#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2391#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2392#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2393#define I40E_AQ_LLDP_TX_SHIFT 0x4
2394#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2395/* TX pause flags use I40E_AQ_LINK_TX_* above */
2396 __le16 local_len;
2397 __le16 remote_len;
2398 u8 reserved2[2];
2399 __le32 addr_high;
2400 __le32 addr_low;
2401};
2402
2403I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2404
2405/* Configure LLDP MIB Change Event (direct 0x0A01)
2406 * also used for the event (with type in the command field)
2407 */
2408struct i40e_aqc_lldp_update_mib {
2409 u8 command;
2410#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2411#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2412 u8 reserved[7];
2413 __le32 addr_high;
2414 __le32 addr_low;
2415};
2416
2417I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2418
2419/* Add LLDP TLV (indirect 0x0A02)
2420 * Delete LLDP TLV (indirect 0x0A04)
2421 */
2422struct i40e_aqc_lldp_add_tlv {
2423 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2424 u8 reserved1[1];
2425 __le16 len;
2426 u8 reserved2[4];
2427 __le32 addr_high;
2428 __le32 addr_low;
2429};
2430
2431I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2432
2433/* Update LLDP TLV (indirect 0x0A03) */
2434struct i40e_aqc_lldp_update_tlv {
2435 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2436 u8 reserved;
2437 __le16 old_len;
2438 __le16 new_offset;
2439 __le16 new_len;
2440 __le32 addr_high;
2441 __le32 addr_low;
2442};
2443
2444I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2445
2446/* Stop LLDP (direct 0x0A05) */
2447struct i40e_aqc_lldp_stop {
2448 u8 command;
2449#define I40E_AQ_LLDP_AGENT_STOP 0x0
2450#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2451 u8 reserved[15];
2452};
2453
2454I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2455
2456/* Start LLDP (direct 0x0A06) */
2457
2458struct i40e_aqc_lldp_start {
2459 u8 command;
2460#define I40E_AQ_LLDP_AGENT_START 0x1
2461 u8 reserved[15];
2462};
2463
2464I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2465
2466/* Set DCB (direct 0x0303) */
2467struct i40e_aqc_set_dcb_parameters {
2468 u8 command;
2469#define I40E_AQ_DCB_SET_AGENT 0x1
2470#define I40E_DCB_VALID 0x1
2471 u8 valid_flags;
2472 u8 reserved[14];
2473};
2474
2475I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters);
2476
2477/* Apply MIB changes (0x0A07)
2478 * uses the generic struc as it contains no data
2479 */
2480
2481/* Add Udp Tunnel command and completion (direct 0x0B00) */
2482struct i40e_aqc_add_udp_tunnel {
2483 __le16 udp_port;
2484 u8 reserved0[3];
2485 u8 protocol_type;
2486#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2487#define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2488#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2489#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2490 u8 reserved1[10];
2491};
2492
2493I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2494
2495struct i40e_aqc_add_udp_tunnel_completion {
2496 __le16 udp_port;
2497 u8 filter_entry_index;
2498 u8 multiple_pfs;
2499#define I40E_AQC_SINGLE_PF 0x0
2500#define I40E_AQC_MULTIPLE_PFS 0x1
2501 u8 total_filters;
2502 u8 reserved[11];
2503};
2504
2505I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2506
2507/* remove UDP Tunnel command (0x0B01) */
2508struct i40e_aqc_remove_udp_tunnel {
2509 u8 reserved[2];
2510 u8 index; /* 0 to 15 */
2511 u8 reserved2[13];
2512};
2513
2514I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2515
2516struct i40e_aqc_del_udp_tunnel_completion {
2517 __le16 udp_port;
2518 u8 index; /* 0 to 15 */
2519 u8 multiple_pfs;
2520 u8 total_filters_used;
2521 u8 reserved1[11];
2522};
2523
2524I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2525
2526struct i40e_aqc_get_set_rss_key {
2527#define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15)
2528#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2529#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2530 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2531 __le16 vsi_id;
2532 u8 reserved[6];
2533 __le32 addr_high;
2534 __le32 addr_low;
2535};
2536
2537I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2538
2539struct i40e_aqc_get_set_rss_key_data {
2540 u8 standard_rss_key[0x28];
2541 u8 extended_hash_key[0xc];
2542};
2543
2544I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2545
2546struct i40e_aqc_get_set_rss_lut {
2547#define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15)
2548#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2549#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2550 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2551 __le16 vsi_id;
2552#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2553#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \
2554 BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2555
2556#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2557#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2558 __le16 flags;
2559 u8 reserved[4];
2560 __le32 addr_high;
2561 __le32 addr_low;
2562};
2563
2564I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2565
2566/* tunnel key structure 0x0B10 */
2567
2568struct i40e_aqc_tunnel_key_structure_A0 {
2569 __le16 key1_off;
2570 __le16 key1_len;
2571 __le16 key2_off;
2572 __le16 key2_len;
2573 __le16 flags;
2574#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2575/* response flags */
2576#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2577#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2578#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2579 u8 resreved[6];
2580};
2581
2582I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
2583
2584struct i40e_aqc_tunnel_key_structure {
2585 u8 key1_off;
2586 u8 key2_off;
2587 u8 key1_len; /* 0 to 15 */
2588 u8 key2_len; /* 0 to 15 */
2589 u8 flags;
2590#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2591/* response flags */
2592#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2593#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2594#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2595 u8 network_key_index;
2596#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2597#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2598#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2599#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2600 u8 reserved[10];
2601};
2602
2603I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2604
2605/* OEM mode commands (direct 0xFE0x) */
2606struct i40e_aqc_oem_param_change {
2607 __le32 param_type;
2608#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2609#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2610#define I40E_AQ_OEM_PARAM_MAC 2
2611 __le32 param_value1;
2612 __le16 param_value2;
2613 u8 reserved[6];
2614};
2615
2616I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2617
2618struct i40e_aqc_oem_state_change {
2619 __le32 state;
2620#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2621#define I40E_AQ_OEM_STATE_LINK_UP 0x1
2622 u8 reserved[12];
2623};
2624
2625I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2626
2627/* Initialize OCSD (0xFE02, direct) */
2628struct i40e_aqc_opc_oem_ocsd_initialize {
2629 u8 type_status;
2630 u8 reserved1[3];
2631 __le32 ocsd_memory_block_addr_high;
2632 __le32 ocsd_memory_block_addr_low;
2633 __le32 requested_update_interval;
2634};
2635
2636I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2637
2638/* Initialize OCBB (0xFE03, direct) */
2639struct i40e_aqc_opc_oem_ocbb_initialize {
2640 u8 type_status;
2641 u8 reserved1[3];
2642 __le32 ocbb_memory_block_addr_high;
2643 __le32 ocbb_memory_block_addr_low;
2644 u8 reserved2[4];
2645};
2646
2647I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2648
2649/* debug commands */
2650
2651/* get device id (0xFF00) uses the generic structure */
2652
2653/* set test more (0xFF01, internal) */
2654
2655struct i40e_acq_set_test_mode {
2656 u8 mode;
2657#define I40E_AQ_TEST_PARTIAL 0
2658#define I40E_AQ_TEST_FULL 1
2659#define I40E_AQ_TEST_NVM 2
2660 u8 reserved[3];
2661 u8 command;
2662#define I40E_AQ_TEST_OPEN 0
2663#define I40E_AQ_TEST_CLOSE 1
2664#define I40E_AQ_TEST_INC 2
2665 u8 reserved2[3];
2666 __le32 address_high;
2667 __le32 address_low;
2668};
2669
2670I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2671
2672/* Debug Read Register command (0xFF03)
2673 * Debug Write Register command (0xFF04)
2674 */
2675struct i40e_aqc_debug_reg_read_write {
2676 __le32 reserved;
2677 __le32 address;
2678 __le32 value_high;
2679 __le32 value_low;
2680};
2681
2682I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2683
2684/* Scatter/gather Reg Read (indirect 0xFF05)
2685 * Scatter/gather Reg Write (indirect 0xFF06)
2686 */
2687
2688/* i40e_aq_desc is used for the command */
2689struct i40e_aqc_debug_reg_sg_element_data {
2690 __le32 address;
2691 __le32 value;
2692};
2693
2694/* Debug Modify register (direct 0xFF07) */
2695struct i40e_aqc_debug_modify_reg {
2696 __le32 address;
2697 __le32 value;
2698 __le32 clear_mask;
2699 __le32 set_mask;
2700};
2701
2702I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2703
2704/* dump internal data (0xFF08, indirect) */
2705
2706#define I40E_AQ_CLUSTER_ID_AUX 0
2707#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2708#define I40E_AQ_CLUSTER_ID_TXSCHED 2
2709#define I40E_AQ_CLUSTER_ID_HMC 3
2710#define I40E_AQ_CLUSTER_ID_MAC0 4
2711#define I40E_AQ_CLUSTER_ID_MAC1 5
2712#define I40E_AQ_CLUSTER_ID_MAC2 6
2713#define I40E_AQ_CLUSTER_ID_MAC3 7
2714#define I40E_AQ_CLUSTER_ID_DCB 8
2715#define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2716#define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2717#define I40E_AQ_CLUSTER_ID_ALTRAM 11
2718
2719struct i40e_aqc_debug_dump_internals {
2720 u8 cluster_id;
2721 u8 table_id;
2722 __le16 data_size;
2723 __le32 idx;
2724 __le32 address_high;
2725 __le32 address_low;
2726};
2727
2728I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2729
2730struct i40e_aqc_debug_modify_internals {
2731 u8 cluster_id;
2732 u8 cluster_specific_params[7];
2733 __le32 address_high;
2734 __le32 address_low;
2735};
2736
2737I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2738
2739#endif /* _I40E_ADMINQ_CMD_H_ */