Loading...
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4/* 80003ES2LAN Gigabit Ethernet Controller (Copper)
5 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
6 */
7
8#include "e1000.h"
9
10/* A table for the GG82563 cable length where the range is defined
11 * with a lower bound at "index" and the upper bound at
12 * "index + 5".
13 */
14static const u16 e1000_gg82563_cable_length_table[] = {
15 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF
16};
17
18#define GG82563_CABLE_LENGTH_TABLE_SIZE \
19 ARRAY_SIZE(e1000_gg82563_cable_length_table)
20
21static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
22static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
23static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
24static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
25static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
26static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
27static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
28static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
29 u16 *data);
30static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
31 u16 data);
32static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
33
34/**
35 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
36 * @hw: pointer to the HW structure
37 **/
38static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
39{
40 struct e1000_phy_info *phy = &hw->phy;
41 s32 ret_val;
42
43 if (hw->phy.media_type != e1000_media_type_copper) {
44 phy->type = e1000_phy_none;
45 return 0;
46 } else {
47 phy->ops.power_up = e1000_power_up_phy_copper;
48 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
49 }
50
51 phy->addr = 1;
52 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
53 phy->reset_delay_us = 100;
54 phy->type = e1000_phy_gg82563;
55
56 /* This can only be done after all function pointers are setup. */
57 ret_val = e1000e_get_phy_id(hw);
58
59 /* Verify phy id */
60 if (phy->id != GG82563_E_PHY_ID)
61 return -E1000_ERR_PHY;
62
63 return ret_val;
64}
65
66/**
67 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
68 * @hw: pointer to the HW structure
69 **/
70static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
71{
72 struct e1000_nvm_info *nvm = &hw->nvm;
73 u32 eecd = er32(EECD);
74 u16 size;
75
76 nvm->opcode_bits = 8;
77 nvm->delay_usec = 1;
78 switch (nvm->override) {
79 case e1000_nvm_override_spi_large:
80 nvm->page_size = 32;
81 nvm->address_bits = 16;
82 break;
83 case e1000_nvm_override_spi_small:
84 nvm->page_size = 8;
85 nvm->address_bits = 8;
86 break;
87 default:
88 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
89 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
90 break;
91 }
92
93 nvm->type = e1000_nvm_eeprom_spi;
94
95 size = (u16)FIELD_GET(E1000_EECD_SIZE_EX_MASK, eecd);
96
97 /* Added to a constant, "size" becomes the left-shift value
98 * for setting word_size.
99 */
100 size += NVM_WORD_SIZE_BASE_SHIFT;
101
102 /* EEPROM access above 16k is unsupported */
103 if (size > 14)
104 size = 14;
105 nvm->word_size = BIT(size);
106
107 return 0;
108}
109
110/**
111 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
112 * @hw: pointer to the HW structure
113 **/
114static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
115{
116 struct e1000_mac_info *mac = &hw->mac;
117
118 /* Set media type and media-dependent function pointers */
119 switch (hw->adapter->pdev->device) {
120 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
121 hw->phy.media_type = e1000_media_type_internal_serdes;
122 mac->ops.check_for_link = e1000e_check_for_serdes_link;
123 mac->ops.setup_physical_interface =
124 e1000e_setup_fiber_serdes_link;
125 break;
126 default:
127 hw->phy.media_type = e1000_media_type_copper;
128 mac->ops.check_for_link = e1000e_check_for_copper_link;
129 mac->ops.setup_physical_interface =
130 e1000_setup_copper_link_80003es2lan;
131 break;
132 }
133
134 /* Set mta register count */
135 mac->mta_reg_count = 128;
136 /* Set rar entry count */
137 mac->rar_entry_count = E1000_RAR_ENTRIES;
138 /* FWSM register */
139 mac->has_fwsm = true;
140 /* ARC supported; valid only if manageability features are enabled. */
141 mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
142 /* Adaptive IFS not supported */
143 mac->adaptive_ifs = false;
144
145 /* set lan id for port to determine which phy lock to use */
146 hw->mac.ops.set_lan_id(hw);
147
148 return 0;
149}
150
151static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
152{
153 struct e1000_hw *hw = &adapter->hw;
154 s32 rc;
155
156 rc = e1000_init_mac_params_80003es2lan(hw);
157 if (rc)
158 return rc;
159
160 rc = e1000_init_nvm_params_80003es2lan(hw);
161 if (rc)
162 return rc;
163
164 rc = e1000_init_phy_params_80003es2lan(hw);
165 if (rc)
166 return rc;
167
168 return 0;
169}
170
171/**
172 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
173 * @hw: pointer to the HW structure
174 *
175 * A wrapper to acquire access rights to the correct PHY.
176 **/
177static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
178{
179 u16 mask;
180
181 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
182 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
183}
184
185/**
186 * e1000_release_phy_80003es2lan - Release rights to access PHY
187 * @hw: pointer to the HW structure
188 *
189 * A wrapper to release access rights to the correct PHY.
190 **/
191static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
192{
193 u16 mask;
194
195 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
196 e1000_release_swfw_sync_80003es2lan(hw, mask);
197}
198
199/**
200 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
201 * @hw: pointer to the HW structure
202 *
203 * Acquire the semaphore to access the Kumeran interface.
204 *
205 **/
206static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
207{
208 u16 mask;
209
210 mask = E1000_SWFW_CSR_SM;
211
212 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
213}
214
215/**
216 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
217 * @hw: pointer to the HW structure
218 *
219 * Release the semaphore used to access the Kumeran interface
220 **/
221static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
222{
223 u16 mask;
224
225 mask = E1000_SWFW_CSR_SM;
226
227 e1000_release_swfw_sync_80003es2lan(hw, mask);
228}
229
230/**
231 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
232 * @hw: pointer to the HW structure
233 *
234 * Acquire the semaphore to access the EEPROM.
235 **/
236static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
237{
238 s32 ret_val;
239
240 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
241 if (ret_val)
242 return ret_val;
243
244 ret_val = e1000e_acquire_nvm(hw);
245
246 if (ret_val)
247 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
248
249 return ret_val;
250}
251
252/**
253 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
254 * @hw: pointer to the HW structure
255 *
256 * Release the semaphore used to access the EEPROM.
257 **/
258static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
259{
260 e1000e_release_nvm(hw);
261 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
262}
263
264/**
265 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
266 * @hw: pointer to the HW structure
267 * @mask: specifies which semaphore to acquire
268 *
269 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
270 * will also specify which port we're acquiring the lock for.
271 **/
272static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
273{
274 u32 swfw_sync;
275 u32 swmask = mask;
276 u32 fwmask = mask << 16;
277 s32 i = 0;
278 s32 timeout = 50;
279
280 while (i < timeout) {
281 if (e1000e_get_hw_semaphore(hw))
282 return -E1000_ERR_SWFW_SYNC;
283
284 swfw_sync = er32(SW_FW_SYNC);
285 if (!(swfw_sync & (fwmask | swmask)))
286 break;
287
288 /* Firmware currently using resource (fwmask)
289 * or other software thread using resource (swmask)
290 */
291 e1000e_put_hw_semaphore(hw);
292 mdelay(5);
293 i++;
294 }
295
296 if (i == timeout) {
297 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
298 return -E1000_ERR_SWFW_SYNC;
299 }
300
301 swfw_sync |= swmask;
302 ew32(SW_FW_SYNC, swfw_sync);
303
304 e1000e_put_hw_semaphore(hw);
305
306 return 0;
307}
308
309/**
310 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
311 * @hw: pointer to the HW structure
312 * @mask: specifies which semaphore to acquire
313 *
314 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
315 * will also specify which port we're releasing the lock for.
316 **/
317static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
318{
319 u32 swfw_sync;
320
321 while (e1000e_get_hw_semaphore(hw) != 0)
322 ; /* Empty */
323
324 swfw_sync = er32(SW_FW_SYNC);
325 swfw_sync &= ~mask;
326 ew32(SW_FW_SYNC, swfw_sync);
327
328 e1000e_put_hw_semaphore(hw);
329}
330
331/**
332 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
333 * @hw: pointer to the HW structure
334 * @offset: offset of the register to read
335 * @data: pointer to the data returned from the operation
336 *
337 * Read the GG82563 PHY register.
338 **/
339static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
340 u32 offset, u16 *data)
341{
342 s32 ret_val;
343 u32 page_select;
344 u16 temp;
345
346 ret_val = e1000_acquire_phy_80003es2lan(hw);
347 if (ret_val)
348 return ret_val;
349
350 /* Select Configuration Page */
351 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
352 page_select = GG82563_PHY_PAGE_SELECT;
353 } else {
354 /* Use Alternative Page Select register to access
355 * registers 30 and 31
356 */
357 page_select = GG82563_PHY_PAGE_SELECT_ALT;
358 }
359
360 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
361 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
362 if (ret_val) {
363 e1000_release_phy_80003es2lan(hw);
364 return ret_val;
365 }
366
367 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
368 /* The "ready" bit in the MDIC register may be incorrectly set
369 * before the device has completed the "Page Select" MDI
370 * transaction. So we wait 200us after each MDI command...
371 */
372 usleep_range(200, 400);
373
374 /* ...and verify the command was successful. */
375 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
376
377 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
378 e1000_release_phy_80003es2lan(hw);
379 return -E1000_ERR_PHY;
380 }
381
382 usleep_range(200, 400);
383
384 ret_val = e1000e_read_phy_reg_mdic(hw,
385 MAX_PHY_REG_ADDRESS & offset,
386 data);
387
388 usleep_range(200, 400);
389 } else {
390 ret_val = e1000e_read_phy_reg_mdic(hw,
391 MAX_PHY_REG_ADDRESS & offset,
392 data);
393 }
394
395 e1000_release_phy_80003es2lan(hw);
396
397 return ret_val;
398}
399
400/**
401 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
402 * @hw: pointer to the HW structure
403 * @offset: offset of the register to read
404 * @data: value to write to the register
405 *
406 * Write to the GG82563 PHY register.
407 **/
408static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
409 u32 offset, u16 data)
410{
411 s32 ret_val;
412 u32 page_select;
413 u16 temp;
414
415 ret_val = e1000_acquire_phy_80003es2lan(hw);
416 if (ret_val)
417 return ret_val;
418
419 /* Select Configuration Page */
420 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
421 page_select = GG82563_PHY_PAGE_SELECT;
422 } else {
423 /* Use Alternative Page Select register to access
424 * registers 30 and 31
425 */
426 page_select = GG82563_PHY_PAGE_SELECT_ALT;
427 }
428
429 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
430 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
431 if (ret_val) {
432 e1000_release_phy_80003es2lan(hw);
433 return ret_val;
434 }
435
436 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
437 /* The "ready" bit in the MDIC register may be incorrectly set
438 * before the device has completed the "Page Select" MDI
439 * transaction. So we wait 200us after each MDI command...
440 */
441 usleep_range(200, 400);
442
443 /* ...and verify the command was successful. */
444 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
445
446 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
447 e1000_release_phy_80003es2lan(hw);
448 return -E1000_ERR_PHY;
449 }
450
451 usleep_range(200, 400);
452
453 ret_val = e1000e_write_phy_reg_mdic(hw,
454 MAX_PHY_REG_ADDRESS &
455 offset, data);
456
457 usleep_range(200, 400);
458 } else {
459 ret_val = e1000e_write_phy_reg_mdic(hw,
460 MAX_PHY_REG_ADDRESS &
461 offset, data);
462 }
463
464 e1000_release_phy_80003es2lan(hw);
465
466 return ret_val;
467}
468
469/**
470 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
471 * @hw: pointer to the HW structure
472 * @offset: offset of the register to read
473 * @words: number of words to write
474 * @data: buffer of data to write to the NVM
475 *
476 * Write "words" of data to the ESB2 NVM.
477 **/
478static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
479 u16 words, u16 *data)
480{
481 return e1000e_write_nvm_spi(hw, offset, words, data);
482}
483
484/**
485 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
486 * @hw: pointer to the HW structure
487 *
488 * Wait a specific amount of time for manageability processes to complete.
489 * This is a function pointer entry point called by the phy module.
490 **/
491static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
492{
493 s32 timeout = PHY_CFG_TIMEOUT;
494 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
495
496 if (hw->bus.func == 1)
497 mask = E1000_NVM_CFG_DONE_PORT_1;
498
499 while (timeout) {
500 if (er32(EEMNGCTL) & mask)
501 break;
502 usleep_range(1000, 2000);
503 timeout--;
504 }
505 if (!timeout) {
506 e_dbg("MNG configuration cycle has not completed.\n");
507 return -E1000_ERR_RESET;
508 }
509
510 return 0;
511}
512
513/**
514 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
515 * @hw: pointer to the HW structure
516 *
517 * Force the speed and duplex settings onto the PHY. This is a
518 * function pointer entry point called by the phy module.
519 **/
520static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
521{
522 s32 ret_val;
523 u16 phy_data;
524 bool link;
525
526 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
527 * forced whenever speed and duplex are forced.
528 */
529 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
530 if (ret_val)
531 return ret_val;
532
533 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
534 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
535 if (ret_val)
536 return ret_val;
537
538 e_dbg("GG82563 PSCR: %X\n", phy_data);
539
540 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
541 if (ret_val)
542 return ret_val;
543
544 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
545
546 /* Reset the phy to commit changes. */
547 phy_data |= BMCR_RESET;
548
549 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
550 if (ret_val)
551 return ret_val;
552
553 udelay(1);
554
555 if (hw->phy.autoneg_wait_to_complete) {
556 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
557
558 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
559 100000, &link);
560 if (ret_val)
561 return ret_val;
562
563 if (!link) {
564 /* We didn't get link.
565 * Reset the DSP and cross our fingers.
566 */
567 ret_val = e1000e_phy_reset_dsp(hw);
568 if (ret_val)
569 return ret_val;
570 }
571
572 /* Try once more */
573 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
574 100000, &link);
575 if (ret_val)
576 return ret_val;
577 }
578
579 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
580 if (ret_val)
581 return ret_val;
582
583 /* Resetting the phy means we need to verify the TX_CLK corresponds
584 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
585 */
586 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
587 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
588 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
589 else
590 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
591
592 /* In addition, we must re-enable CRS on Tx for both half and full
593 * duplex.
594 */
595 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
596 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
597
598 return ret_val;
599}
600
601/**
602 * e1000_get_cable_length_80003es2lan - Set approximate cable length
603 * @hw: pointer to the HW structure
604 *
605 * Find the approximate cable length as measured by the GG82563 PHY.
606 * This is a function pointer entry point called by the phy module.
607 **/
608static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
609{
610 struct e1000_phy_info *phy = &hw->phy;
611 s32 ret_val;
612 u16 phy_data, index;
613
614 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
615 if (ret_val)
616 return ret_val;
617
618 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
619
620 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
621 return -E1000_ERR_PHY;
622
623 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
624 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
625
626 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
627
628 return 0;
629}
630
631/**
632 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
633 * @hw: pointer to the HW structure
634 * @speed: pointer to speed buffer
635 * @duplex: pointer to duplex buffer
636 *
637 * Retrieve the current speed and duplex configuration.
638 **/
639static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
640 u16 *duplex)
641{
642 s32 ret_val;
643
644 if (hw->phy.media_type == e1000_media_type_copper) {
645 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
646 hw->phy.ops.cfg_on_link_up(hw);
647 } else {
648 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
649 speed,
650 duplex);
651 }
652
653 return ret_val;
654}
655
656/**
657 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
658 * @hw: pointer to the HW structure
659 *
660 * Perform a global reset to the ESB2 controller.
661 **/
662static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
663{
664 u32 ctrl;
665 s32 ret_val;
666 u16 kum_reg_data;
667
668 /* Prevent the PCI-E bus from sticking if there is no TLP connection
669 * on the last TLP read/write transaction when MAC is reset.
670 */
671 ret_val = e1000e_disable_pcie_master(hw);
672 if (ret_val)
673 e_dbg("PCI-E Master disable polling has failed.\n");
674
675 e_dbg("Masking off all interrupts\n");
676 ew32(IMC, 0xffffffff);
677
678 ew32(RCTL, 0);
679 ew32(TCTL, E1000_TCTL_PSP);
680 e1e_flush();
681
682 usleep_range(10000, 11000);
683
684 ctrl = er32(CTRL);
685
686 ret_val = e1000_acquire_phy_80003es2lan(hw);
687 if (ret_val)
688 return ret_val;
689
690 e_dbg("Issuing a global reset to MAC\n");
691 ew32(CTRL, ctrl | E1000_CTRL_RST);
692 e1000_release_phy_80003es2lan(hw);
693
694 /* Disable IBIST slave mode (far-end loopback) */
695 ret_val =
696 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
697 &kum_reg_data);
698 if (!ret_val) {
699 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
700 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
701 E1000_KMRNCTRLSTA_INBAND_PARAM,
702 kum_reg_data);
703 if (ret_val)
704 e_dbg("Error disabling far-end loopback\n");
705 } else {
706 e_dbg("Error disabling far-end loopback\n");
707 }
708
709 ret_val = e1000e_get_auto_rd_done(hw);
710 if (ret_val)
711 /* We don't want to continue accessing MAC registers. */
712 return ret_val;
713
714 /* Clear any pending interrupt events. */
715 ew32(IMC, 0xffffffff);
716 er32(ICR);
717
718 return e1000_check_alt_mac_addr_generic(hw);
719}
720
721/**
722 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
723 * @hw: pointer to the HW structure
724 *
725 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
726 **/
727static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
728{
729 struct e1000_mac_info *mac = &hw->mac;
730 u32 reg_data;
731 s32 ret_val;
732 u16 kum_reg_data;
733 u16 i;
734
735 e1000_initialize_hw_bits_80003es2lan(hw);
736
737 /* Initialize identification LED */
738 ret_val = mac->ops.id_led_init(hw);
739 /* An error is not fatal and we should not stop init due to this */
740 if (ret_val)
741 e_dbg("Error initializing identification LED\n");
742
743 /* Disabling VLAN filtering */
744 e_dbg("Initializing the IEEE VLAN\n");
745 mac->ops.clear_vfta(hw);
746
747 /* Setup the receive address. */
748 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
749
750 /* Zero out the Multicast HASH table */
751 e_dbg("Zeroing the MTA\n");
752 for (i = 0; i < mac->mta_reg_count; i++)
753 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
754
755 /* Setup link and flow control */
756 ret_val = mac->ops.setup_link(hw);
757 if (ret_val)
758 return ret_val;
759
760 /* Disable IBIST slave mode (far-end loopback) */
761 ret_val =
762 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
763 &kum_reg_data);
764 if (!ret_val) {
765 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
766 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
767 E1000_KMRNCTRLSTA_INBAND_PARAM,
768 kum_reg_data);
769 if (ret_val)
770 e_dbg("Error disabling far-end loopback\n");
771 } else {
772 e_dbg("Error disabling far-end loopback\n");
773 }
774
775 /* Set the transmit descriptor write-back policy */
776 reg_data = er32(TXDCTL(0));
777 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
778 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
779 ew32(TXDCTL(0), reg_data);
780
781 /* ...for both queues. */
782 reg_data = er32(TXDCTL(1));
783 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
784 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
785 ew32(TXDCTL(1), reg_data);
786
787 /* Enable retransmit on late collisions */
788 reg_data = er32(TCTL);
789 reg_data |= E1000_TCTL_RTLC;
790 ew32(TCTL, reg_data);
791
792 /* Configure Gigabit Carry Extend Padding */
793 reg_data = er32(TCTL_EXT);
794 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
795 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
796 ew32(TCTL_EXT, reg_data);
797
798 /* Configure Transmit Inter-Packet Gap */
799 reg_data = er32(TIPG);
800 reg_data &= ~E1000_TIPG_IPGT_MASK;
801 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
802 ew32(TIPG, reg_data);
803
804 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
805 reg_data &= ~0x00100000;
806 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
807
808 /* default to true to enable the MDIC W/A */
809 hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
810
811 ret_val =
812 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
813 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
814 if (!ret_val) {
815 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
816 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
817 hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
818 }
819
820 /* Clear all of the statistics registers (clear on read). It is
821 * important that we do this after we have tried to establish link
822 * because the symbol error count will increment wildly if there
823 * is no link.
824 */
825 e1000_clear_hw_cntrs_80003es2lan(hw);
826
827 return ret_val;
828}
829
830/**
831 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
832 * @hw: pointer to the HW structure
833 *
834 * Initializes required hardware-dependent bits needed for normal operation.
835 **/
836static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
837{
838 u32 reg;
839
840 /* Transmit Descriptor Control 0 */
841 reg = er32(TXDCTL(0));
842 reg |= BIT(22);
843 ew32(TXDCTL(0), reg);
844
845 /* Transmit Descriptor Control 1 */
846 reg = er32(TXDCTL(1));
847 reg |= BIT(22);
848 ew32(TXDCTL(1), reg);
849
850 /* Transmit Arbitration Control 0 */
851 reg = er32(TARC(0));
852 reg &= ~(0xF << 27); /* 30:27 */
853 if (hw->phy.media_type != e1000_media_type_copper)
854 reg &= ~BIT(20);
855 ew32(TARC(0), reg);
856
857 /* Transmit Arbitration Control 1 */
858 reg = er32(TARC(1));
859 if (er32(TCTL) & E1000_TCTL_MULR)
860 reg &= ~BIT(28);
861 else
862 reg |= BIT(28);
863 ew32(TARC(1), reg);
864
865 /* Disable IPv6 extension header parsing because some malformed
866 * IPv6 headers can hang the Rx.
867 */
868 reg = er32(RFCTL);
869 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
870 ew32(RFCTL, reg);
871}
872
873/**
874 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
875 * @hw: pointer to the HW structure
876 *
877 * Setup some GG82563 PHY registers for obtaining link
878 **/
879static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
880{
881 struct e1000_phy_info *phy = &hw->phy;
882 s32 ret_val;
883 u32 reg;
884 u16 data;
885
886 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
887 if (ret_val)
888 return ret_val;
889
890 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
891 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
892 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
893
894 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
895 if (ret_val)
896 return ret_val;
897
898 /* Options:
899 * MDI/MDI-X = 0 (default)
900 * 0 - Auto for all speeds
901 * 1 - MDI mode
902 * 2 - MDI-X mode
903 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
904 */
905 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
906 if (ret_val)
907 return ret_val;
908
909 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
910
911 switch (phy->mdix) {
912 case 1:
913 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
914 break;
915 case 2:
916 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
917 break;
918 case 0:
919 default:
920 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
921 break;
922 }
923
924 /* Options:
925 * disable_polarity_correction = 0 (default)
926 * Automatic Correction for Reversed Cable Polarity
927 * 0 - Disabled
928 * 1 - Enabled
929 */
930 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
931 if (phy->disable_polarity_correction)
932 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
933
934 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
935 if (ret_val)
936 return ret_val;
937
938 /* SW Reset the PHY so all changes take effect */
939 ret_val = hw->phy.ops.commit(hw);
940 if (ret_val) {
941 e_dbg("Error Resetting the PHY\n");
942 return ret_val;
943 }
944
945 /* Bypass Rx and Tx FIFO's */
946 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
947 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
948 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
949 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
950 if (ret_val)
951 return ret_val;
952
953 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
954 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
955 if (ret_val)
956 return ret_val;
957 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
958 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
959 if (ret_val)
960 return ret_val;
961
962 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
963 if (ret_val)
964 return ret_val;
965
966 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
967 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
968 if (ret_val)
969 return ret_val;
970
971 reg = er32(CTRL_EXT);
972 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
973 ew32(CTRL_EXT, reg);
974
975 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
976 if (ret_val)
977 return ret_val;
978
979 /* Do not init these registers when the HW is in IAMT mode, since the
980 * firmware will have already initialized them. We only initialize
981 * them if the HW is not in IAMT mode.
982 */
983 if (!hw->mac.ops.check_mng_mode(hw)) {
984 /* Enable Electrical Idle on the PHY */
985 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
986 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
987 if (ret_val)
988 return ret_val;
989
990 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
991 if (ret_val)
992 return ret_val;
993
994 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
995 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
996 if (ret_val)
997 return ret_val;
998 }
999
1000 /* Workaround: Disable padding in Kumeran interface in the MAC
1001 * and in the PHY to avoid CRC errors.
1002 */
1003 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1004 if (ret_val)
1005 return ret_val;
1006
1007 data |= GG82563_ICR_DIS_PADDING;
1008 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1009 if (ret_val)
1010 return ret_val;
1011
1012 return 0;
1013}
1014
1015/**
1016 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1017 * @hw: pointer to the HW structure
1018 *
1019 * Essentially a wrapper for setting up all things "copper" related.
1020 * This is a function pointer entry point called by the mac module.
1021 **/
1022static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1023{
1024 u32 ctrl;
1025 s32 ret_val;
1026 u16 reg_data;
1027
1028 ctrl = er32(CTRL);
1029 ctrl |= E1000_CTRL_SLU;
1030 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1031 ew32(CTRL, ctrl);
1032
1033 /* Set the mac to wait the maximum time between each
1034 * iteration and increase the max iterations when
1035 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1036 */
1037 /* these next three accesses were always meant to use page 0x34 using
1038 * GG82563_REG(0x34, N) but never did, so we've just corrected the call
1039 * to not drop bits
1040 */
1041 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 4, 0xFFFF);
1042 if (ret_val)
1043 return ret_val;
1044 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 9, ®_data);
1045 if (ret_val)
1046 return ret_val;
1047 reg_data |= 0x3F;
1048 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 9, reg_data);
1049 if (ret_val)
1050 return ret_val;
1051 ret_val =
1052 e1000_read_kmrn_reg_80003es2lan(hw,
1053 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1054 ®_data);
1055 if (ret_val)
1056 return ret_val;
1057 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1058 ret_val =
1059 e1000_write_kmrn_reg_80003es2lan(hw,
1060 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1061 reg_data);
1062 if (ret_val)
1063 return ret_val;
1064
1065 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1066 if (ret_val)
1067 return ret_val;
1068
1069 return e1000e_setup_copper_link(hw);
1070}
1071
1072/**
1073 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1074 * @hw: pointer to the HW structure
1075 *
1076 * Configure the KMRN interface by applying last minute quirks for
1077 * 10/100 operation.
1078 **/
1079static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1080{
1081 s32 ret_val = 0;
1082 u16 speed;
1083 u16 duplex;
1084
1085 if (hw->phy.media_type == e1000_media_type_copper) {
1086 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1087 &duplex);
1088 if (ret_val)
1089 return ret_val;
1090
1091 if (speed == SPEED_1000)
1092 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1093 else
1094 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1095 }
1096
1097 return ret_val;
1098}
1099
1100/**
1101 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1102 * @hw: pointer to the HW structure
1103 * @duplex: current duplex setting
1104 *
1105 * Configure the KMRN interface by applying last minute quirks for
1106 * 10/100 operation.
1107 **/
1108static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1109{
1110 s32 ret_val;
1111 u32 tipg;
1112 u32 i = 0;
1113 u16 reg_data, reg_data2;
1114
1115 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1116 ret_val =
1117 e1000_write_kmrn_reg_80003es2lan(hw,
1118 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1119 reg_data);
1120 if (ret_val)
1121 return ret_val;
1122
1123 /* Configure Transmit Inter-Packet Gap */
1124 tipg = er32(TIPG);
1125 tipg &= ~E1000_TIPG_IPGT_MASK;
1126 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1127 ew32(TIPG, tipg);
1128
1129 do {
1130 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1131 if (ret_val)
1132 return ret_val;
1133
1134 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1135 if (ret_val)
1136 return ret_val;
1137 i++;
1138 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1139
1140 if (duplex == HALF_DUPLEX)
1141 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1142 else
1143 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1144
1145 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1146}
1147
1148/**
1149 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1150 * @hw: pointer to the HW structure
1151 *
1152 * Configure the KMRN interface by applying last minute quirks for
1153 * gigabit operation.
1154 **/
1155static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1156{
1157 s32 ret_val;
1158 u16 reg_data, reg_data2;
1159 u32 tipg;
1160 u32 i = 0;
1161
1162 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1163 ret_val =
1164 e1000_write_kmrn_reg_80003es2lan(hw,
1165 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1166 reg_data);
1167 if (ret_val)
1168 return ret_val;
1169
1170 /* Configure Transmit Inter-Packet Gap */
1171 tipg = er32(TIPG);
1172 tipg &= ~E1000_TIPG_IPGT_MASK;
1173 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1174 ew32(TIPG, tipg);
1175
1176 do {
1177 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1178 if (ret_val)
1179 return ret_val;
1180
1181 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1182 if (ret_val)
1183 return ret_val;
1184 i++;
1185 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1186
1187 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1188
1189 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1190}
1191
1192/**
1193 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1194 * @hw: pointer to the HW structure
1195 * @offset: register offset to be read
1196 * @data: pointer to the read data
1197 *
1198 * Acquire semaphore, then read the PHY register at offset
1199 * using the kumeran interface. The information retrieved is stored in data.
1200 * Release the semaphore before exiting.
1201 **/
1202static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1203 u16 *data)
1204{
1205 u32 kmrnctrlsta;
1206 s32 ret_val;
1207
1208 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1209 if (ret_val)
1210 return ret_val;
1211
1212 kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) |
1213 E1000_KMRNCTRLSTA_REN;
1214 ew32(KMRNCTRLSTA, kmrnctrlsta);
1215 e1e_flush();
1216
1217 udelay(2);
1218
1219 kmrnctrlsta = er32(KMRNCTRLSTA);
1220 *data = (u16)kmrnctrlsta;
1221
1222 e1000_release_mac_csr_80003es2lan(hw);
1223
1224 return ret_val;
1225}
1226
1227/**
1228 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1229 * @hw: pointer to the HW structure
1230 * @offset: register offset to write to
1231 * @data: data to write at register offset
1232 *
1233 * Acquire semaphore, then write the data to PHY register
1234 * at the offset using the kumeran interface. Release semaphore
1235 * before exiting.
1236 **/
1237static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1238 u16 data)
1239{
1240 u32 kmrnctrlsta;
1241 s32 ret_val;
1242
1243 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1244 if (ret_val)
1245 return ret_val;
1246
1247 kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) | data;
1248 ew32(KMRNCTRLSTA, kmrnctrlsta);
1249 e1e_flush();
1250
1251 udelay(2);
1252
1253 e1000_release_mac_csr_80003es2lan(hw);
1254
1255 return ret_val;
1256}
1257
1258/**
1259 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1260 * @hw: pointer to the HW structure
1261 **/
1262static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1263{
1264 s32 ret_val;
1265
1266 /* If there's an alternate MAC address place it in RAR0
1267 * so that it will override the Si installed default perm
1268 * address.
1269 */
1270 ret_val = e1000_check_alt_mac_addr_generic(hw);
1271 if (ret_val)
1272 return ret_val;
1273
1274 return e1000_read_mac_addr_generic(hw);
1275}
1276
1277/**
1278 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1279 * @hw: pointer to the HW structure
1280 *
1281 * In the case of a PHY power down to save power, or to turn off link during a
1282 * driver unload, or wake on lan is not enabled, remove the link.
1283 **/
1284static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1285{
1286 /* If the management interface is not enabled, then power down */
1287 if (!(hw->mac.ops.check_mng_mode(hw) ||
1288 hw->phy.ops.check_reset_block(hw)))
1289 e1000_power_down_phy_copper(hw);
1290}
1291
1292/**
1293 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1294 * @hw: pointer to the HW structure
1295 *
1296 * Clears the hardware counters by reading the counter registers.
1297 **/
1298static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1299{
1300 e1000e_clear_hw_cntrs_base(hw);
1301
1302 er32(PRC64);
1303 er32(PRC127);
1304 er32(PRC255);
1305 er32(PRC511);
1306 er32(PRC1023);
1307 er32(PRC1522);
1308 er32(PTC64);
1309 er32(PTC127);
1310 er32(PTC255);
1311 er32(PTC511);
1312 er32(PTC1023);
1313 er32(PTC1522);
1314
1315 er32(ALGNERRC);
1316 er32(RXERRC);
1317 er32(TNCRS);
1318 er32(CEXTERR);
1319 er32(TSCTC);
1320 er32(TSCTFC);
1321
1322 er32(MGTPRC);
1323 er32(MGTPDC);
1324 er32(MGTPTC);
1325
1326 er32(IAC);
1327 er32(ICRXOC);
1328
1329 er32(ICRXPTC);
1330 er32(ICRXATC);
1331 er32(ICTXPTC);
1332 er32(ICTXATC);
1333 er32(ICTXQEC);
1334 er32(ICTXQMTC);
1335 er32(ICRXDMTC);
1336}
1337
1338static const struct e1000_mac_operations es2_mac_ops = {
1339 .read_mac_addr = e1000_read_mac_addr_80003es2lan,
1340 .id_led_init = e1000e_id_led_init_generic,
1341 .blink_led = e1000e_blink_led_generic,
1342 .check_mng_mode = e1000e_check_mng_mode_generic,
1343 /* check_for_link dependent on media type */
1344 .cleanup_led = e1000e_cleanup_led_generic,
1345 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
1346 .get_bus_info = e1000e_get_bus_info_pcie,
1347 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1348 .get_link_up_info = e1000_get_link_up_info_80003es2lan,
1349 .led_on = e1000e_led_on_generic,
1350 .led_off = e1000e_led_off_generic,
1351 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1352 .write_vfta = e1000_write_vfta_generic,
1353 .clear_vfta = e1000_clear_vfta_generic,
1354 .reset_hw = e1000_reset_hw_80003es2lan,
1355 .init_hw = e1000_init_hw_80003es2lan,
1356 .setup_link = e1000e_setup_link_generic,
1357 /* setup_physical_interface dependent on media type */
1358 .setup_led = e1000e_setup_led_generic,
1359 .config_collision_dist = e1000e_config_collision_dist_generic,
1360 .rar_set = e1000e_rar_set_generic,
1361 .rar_get_count = e1000e_rar_get_count_generic,
1362};
1363
1364static const struct e1000_phy_operations es2_phy_ops = {
1365 .acquire = e1000_acquire_phy_80003es2lan,
1366 .check_polarity = e1000_check_polarity_m88,
1367 .check_reset_block = e1000e_check_reset_block_generic,
1368 .commit = e1000e_phy_sw_reset,
1369 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1370 .get_cfg_done = e1000_get_cfg_done_80003es2lan,
1371 .get_cable_length = e1000_get_cable_length_80003es2lan,
1372 .get_info = e1000e_get_phy_info_m88,
1373 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
1374 .release = e1000_release_phy_80003es2lan,
1375 .reset = e1000e_phy_hw_reset_generic,
1376 .set_d0_lplu_state = NULL,
1377 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1378 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1379 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
1380};
1381
1382static const struct e1000_nvm_operations es2_nvm_ops = {
1383 .acquire = e1000_acquire_nvm_80003es2lan,
1384 .read = e1000e_read_nvm_eerd,
1385 .release = e1000_release_nvm_80003es2lan,
1386 .reload = e1000e_reload_nvm_generic,
1387 .update = e1000e_update_nvm_checksum_generic,
1388 .valid_led_default = e1000e_valid_led_default,
1389 .validate = e1000e_validate_nvm_checksum_generic,
1390 .write = e1000_write_nvm_80003es2lan,
1391};
1392
1393const struct e1000_info e1000_es2_info = {
1394 .mac = e1000_80003es2lan,
1395 .flags = FLAG_HAS_HW_VLAN_FILTER
1396 | FLAG_HAS_JUMBO_FRAMES
1397 | FLAG_HAS_WOL
1398 | FLAG_APME_IN_CTRL3
1399 | FLAG_HAS_CTRLEXT_ON_LOAD
1400 | FLAG_RX_NEEDS_RESTART /* errata */
1401 | FLAG_TARC_SET_BIT_ZERO /* errata */
1402 | FLAG_APME_CHECK_PORT_B
1403 | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1404 .flags2 = FLAG2_DMA_BURST,
1405 .pba = 38,
1406 .max_hw_frame_size = DEFAULT_JUMBO,
1407 .get_variants = e1000_get_variants_80003es2lan,
1408 .mac_ops = &es2_mac_ops,
1409 .phy_ops = &es2_phy_ops,
1410 .nvm_ops = &es2_nvm_ops,
1411};
1// SPDX-License-Identifier: GPL-2.0
2/* Intel PRO/1000 Linux driver
3 * Copyright(c) 1999 - 2015 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in
15 * the file called "COPYING".
16 *
17 * Contact Information:
18 * Linux NICS <linux.nics@intel.com>
19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21 */
22
23/* 80003ES2LAN Gigabit Ethernet Controller (Copper)
24 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
25 */
26
27#include "e1000.h"
28
29/* A table for the GG82563 cable length where the range is defined
30 * with a lower bound at "index" and the upper bound at
31 * "index + 5".
32 */
33static const u16 e1000_gg82563_cable_length_table[] = {
34 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF
35};
36
37#define GG82563_CABLE_LENGTH_TABLE_SIZE \
38 ARRAY_SIZE(e1000_gg82563_cable_length_table)
39
40static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
41static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
42static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
43static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
44static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
45static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
46static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
47static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
48 u16 *data);
49static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
50 u16 data);
51static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
52
53/**
54 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
55 * @hw: pointer to the HW structure
56 **/
57static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
58{
59 struct e1000_phy_info *phy = &hw->phy;
60 s32 ret_val;
61
62 if (hw->phy.media_type != e1000_media_type_copper) {
63 phy->type = e1000_phy_none;
64 return 0;
65 } else {
66 phy->ops.power_up = e1000_power_up_phy_copper;
67 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
68 }
69
70 phy->addr = 1;
71 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
72 phy->reset_delay_us = 100;
73 phy->type = e1000_phy_gg82563;
74
75 /* This can only be done after all function pointers are setup. */
76 ret_val = e1000e_get_phy_id(hw);
77
78 /* Verify phy id */
79 if (phy->id != GG82563_E_PHY_ID)
80 return -E1000_ERR_PHY;
81
82 return ret_val;
83}
84
85/**
86 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
87 * @hw: pointer to the HW structure
88 **/
89static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
90{
91 struct e1000_nvm_info *nvm = &hw->nvm;
92 u32 eecd = er32(EECD);
93 u16 size;
94
95 nvm->opcode_bits = 8;
96 nvm->delay_usec = 1;
97 switch (nvm->override) {
98 case e1000_nvm_override_spi_large:
99 nvm->page_size = 32;
100 nvm->address_bits = 16;
101 break;
102 case e1000_nvm_override_spi_small:
103 nvm->page_size = 8;
104 nvm->address_bits = 8;
105 break;
106 default:
107 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
108 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
109 break;
110 }
111
112 nvm->type = e1000_nvm_eeprom_spi;
113
114 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
115 E1000_EECD_SIZE_EX_SHIFT);
116
117 /* Added to a constant, "size" becomes the left-shift value
118 * for setting word_size.
119 */
120 size += NVM_WORD_SIZE_BASE_SHIFT;
121
122 /* EEPROM access above 16k is unsupported */
123 if (size > 14)
124 size = 14;
125 nvm->word_size = BIT(size);
126
127 return 0;
128}
129
130/**
131 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
132 * @hw: pointer to the HW structure
133 **/
134static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
135{
136 struct e1000_mac_info *mac = &hw->mac;
137
138 /* Set media type and media-dependent function pointers */
139 switch (hw->adapter->pdev->device) {
140 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
141 hw->phy.media_type = e1000_media_type_internal_serdes;
142 mac->ops.check_for_link = e1000e_check_for_serdes_link;
143 mac->ops.setup_physical_interface =
144 e1000e_setup_fiber_serdes_link;
145 break;
146 default:
147 hw->phy.media_type = e1000_media_type_copper;
148 mac->ops.check_for_link = e1000e_check_for_copper_link;
149 mac->ops.setup_physical_interface =
150 e1000_setup_copper_link_80003es2lan;
151 break;
152 }
153
154 /* Set mta register count */
155 mac->mta_reg_count = 128;
156 /* Set rar entry count */
157 mac->rar_entry_count = E1000_RAR_ENTRIES;
158 /* FWSM register */
159 mac->has_fwsm = true;
160 /* ARC supported; valid only if manageability features are enabled. */
161 mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
162 /* Adaptive IFS not supported */
163 mac->adaptive_ifs = false;
164
165 /* set lan id for port to determine which phy lock to use */
166 hw->mac.ops.set_lan_id(hw);
167
168 return 0;
169}
170
171static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
172{
173 struct e1000_hw *hw = &adapter->hw;
174 s32 rc;
175
176 rc = e1000_init_mac_params_80003es2lan(hw);
177 if (rc)
178 return rc;
179
180 rc = e1000_init_nvm_params_80003es2lan(hw);
181 if (rc)
182 return rc;
183
184 rc = e1000_init_phy_params_80003es2lan(hw);
185 if (rc)
186 return rc;
187
188 return 0;
189}
190
191/**
192 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
193 * @hw: pointer to the HW structure
194 *
195 * A wrapper to acquire access rights to the correct PHY.
196 **/
197static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
198{
199 u16 mask;
200
201 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
202 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
203}
204
205/**
206 * e1000_release_phy_80003es2lan - Release rights to access PHY
207 * @hw: pointer to the HW structure
208 *
209 * A wrapper to release access rights to the correct PHY.
210 **/
211static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
212{
213 u16 mask;
214
215 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
216 e1000_release_swfw_sync_80003es2lan(hw, mask);
217}
218
219/**
220 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
221 * @hw: pointer to the HW structure
222 *
223 * Acquire the semaphore to access the Kumeran interface.
224 *
225 **/
226static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
227{
228 u16 mask;
229
230 mask = E1000_SWFW_CSR_SM;
231
232 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
233}
234
235/**
236 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
237 * @hw: pointer to the HW structure
238 *
239 * Release the semaphore used to access the Kumeran interface
240 **/
241static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
242{
243 u16 mask;
244
245 mask = E1000_SWFW_CSR_SM;
246
247 e1000_release_swfw_sync_80003es2lan(hw, mask);
248}
249
250/**
251 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
252 * @hw: pointer to the HW structure
253 *
254 * Acquire the semaphore to access the EEPROM.
255 **/
256static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
257{
258 s32 ret_val;
259
260 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
261 if (ret_val)
262 return ret_val;
263
264 ret_val = e1000e_acquire_nvm(hw);
265
266 if (ret_val)
267 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
268
269 return ret_val;
270}
271
272/**
273 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
274 * @hw: pointer to the HW structure
275 *
276 * Release the semaphore used to access the EEPROM.
277 **/
278static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
279{
280 e1000e_release_nvm(hw);
281 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
282}
283
284/**
285 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
286 * @hw: pointer to the HW structure
287 * @mask: specifies which semaphore to acquire
288 *
289 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
290 * will also specify which port we're acquiring the lock for.
291 **/
292static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
293{
294 u32 swfw_sync;
295 u32 swmask = mask;
296 u32 fwmask = mask << 16;
297 s32 i = 0;
298 s32 timeout = 50;
299
300 while (i < timeout) {
301 if (e1000e_get_hw_semaphore(hw))
302 return -E1000_ERR_SWFW_SYNC;
303
304 swfw_sync = er32(SW_FW_SYNC);
305 if (!(swfw_sync & (fwmask | swmask)))
306 break;
307
308 /* Firmware currently using resource (fwmask)
309 * or other software thread using resource (swmask)
310 */
311 e1000e_put_hw_semaphore(hw);
312 mdelay(5);
313 i++;
314 }
315
316 if (i == timeout) {
317 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
318 return -E1000_ERR_SWFW_SYNC;
319 }
320
321 swfw_sync |= swmask;
322 ew32(SW_FW_SYNC, swfw_sync);
323
324 e1000e_put_hw_semaphore(hw);
325
326 return 0;
327}
328
329/**
330 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
331 * @hw: pointer to the HW structure
332 * @mask: specifies which semaphore to acquire
333 *
334 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
335 * will also specify which port we're releasing the lock for.
336 **/
337static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
338{
339 u32 swfw_sync;
340
341 while (e1000e_get_hw_semaphore(hw) != 0)
342 ; /* Empty */
343
344 swfw_sync = er32(SW_FW_SYNC);
345 swfw_sync &= ~mask;
346 ew32(SW_FW_SYNC, swfw_sync);
347
348 e1000e_put_hw_semaphore(hw);
349}
350
351/**
352 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
353 * @hw: pointer to the HW structure
354 * @offset: offset of the register to read
355 * @data: pointer to the data returned from the operation
356 *
357 * Read the GG82563 PHY register.
358 **/
359static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
360 u32 offset, u16 *data)
361{
362 s32 ret_val;
363 u32 page_select;
364 u16 temp;
365
366 ret_val = e1000_acquire_phy_80003es2lan(hw);
367 if (ret_val)
368 return ret_val;
369
370 /* Select Configuration Page */
371 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
372 page_select = GG82563_PHY_PAGE_SELECT;
373 } else {
374 /* Use Alternative Page Select register to access
375 * registers 30 and 31
376 */
377 page_select = GG82563_PHY_PAGE_SELECT_ALT;
378 }
379
380 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
381 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
382 if (ret_val) {
383 e1000_release_phy_80003es2lan(hw);
384 return ret_val;
385 }
386
387 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
388 /* The "ready" bit in the MDIC register may be incorrectly set
389 * before the device has completed the "Page Select" MDI
390 * transaction. So we wait 200us after each MDI command...
391 */
392 usleep_range(200, 400);
393
394 /* ...and verify the command was successful. */
395 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
396
397 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
398 e1000_release_phy_80003es2lan(hw);
399 return -E1000_ERR_PHY;
400 }
401
402 usleep_range(200, 400);
403
404 ret_val = e1000e_read_phy_reg_mdic(hw,
405 MAX_PHY_REG_ADDRESS & offset,
406 data);
407
408 usleep_range(200, 400);
409 } else {
410 ret_val = e1000e_read_phy_reg_mdic(hw,
411 MAX_PHY_REG_ADDRESS & offset,
412 data);
413 }
414
415 e1000_release_phy_80003es2lan(hw);
416
417 return ret_val;
418}
419
420/**
421 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
422 * @hw: pointer to the HW structure
423 * @offset: offset of the register to read
424 * @data: value to write to the register
425 *
426 * Write to the GG82563 PHY register.
427 **/
428static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
429 u32 offset, u16 data)
430{
431 s32 ret_val;
432 u32 page_select;
433 u16 temp;
434
435 ret_val = e1000_acquire_phy_80003es2lan(hw);
436 if (ret_val)
437 return ret_val;
438
439 /* Select Configuration Page */
440 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
441 page_select = GG82563_PHY_PAGE_SELECT;
442 } else {
443 /* Use Alternative Page Select register to access
444 * registers 30 and 31
445 */
446 page_select = GG82563_PHY_PAGE_SELECT_ALT;
447 }
448
449 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
450 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
451 if (ret_val) {
452 e1000_release_phy_80003es2lan(hw);
453 return ret_val;
454 }
455
456 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
457 /* The "ready" bit in the MDIC register may be incorrectly set
458 * before the device has completed the "Page Select" MDI
459 * transaction. So we wait 200us after each MDI command...
460 */
461 usleep_range(200, 400);
462
463 /* ...and verify the command was successful. */
464 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
465
466 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
467 e1000_release_phy_80003es2lan(hw);
468 return -E1000_ERR_PHY;
469 }
470
471 usleep_range(200, 400);
472
473 ret_val = e1000e_write_phy_reg_mdic(hw,
474 MAX_PHY_REG_ADDRESS &
475 offset, data);
476
477 usleep_range(200, 400);
478 } else {
479 ret_val = e1000e_write_phy_reg_mdic(hw,
480 MAX_PHY_REG_ADDRESS &
481 offset, data);
482 }
483
484 e1000_release_phy_80003es2lan(hw);
485
486 return ret_val;
487}
488
489/**
490 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
491 * @hw: pointer to the HW structure
492 * @offset: offset of the register to read
493 * @words: number of words to write
494 * @data: buffer of data to write to the NVM
495 *
496 * Write "words" of data to the ESB2 NVM.
497 **/
498static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
499 u16 words, u16 *data)
500{
501 return e1000e_write_nvm_spi(hw, offset, words, data);
502}
503
504/**
505 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
506 * @hw: pointer to the HW structure
507 *
508 * Wait a specific amount of time for manageability processes to complete.
509 * This is a function pointer entry point called by the phy module.
510 **/
511static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
512{
513 s32 timeout = PHY_CFG_TIMEOUT;
514 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
515
516 if (hw->bus.func == 1)
517 mask = E1000_NVM_CFG_DONE_PORT_1;
518
519 while (timeout) {
520 if (er32(EEMNGCTL) & mask)
521 break;
522 usleep_range(1000, 2000);
523 timeout--;
524 }
525 if (!timeout) {
526 e_dbg("MNG configuration cycle has not completed.\n");
527 return -E1000_ERR_RESET;
528 }
529
530 return 0;
531}
532
533/**
534 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
535 * @hw: pointer to the HW structure
536 *
537 * Force the speed and duplex settings onto the PHY. This is a
538 * function pointer entry point called by the phy module.
539 **/
540static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
541{
542 s32 ret_val;
543 u16 phy_data;
544 bool link;
545
546 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
547 * forced whenever speed and duplex are forced.
548 */
549 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
550 if (ret_val)
551 return ret_val;
552
553 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
554 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
555 if (ret_val)
556 return ret_val;
557
558 e_dbg("GG82563 PSCR: %X\n", phy_data);
559
560 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
561 if (ret_val)
562 return ret_val;
563
564 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
565
566 /* Reset the phy to commit changes. */
567 phy_data |= BMCR_RESET;
568
569 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
570 if (ret_val)
571 return ret_val;
572
573 udelay(1);
574
575 if (hw->phy.autoneg_wait_to_complete) {
576 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
577
578 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
579 100000, &link);
580 if (ret_val)
581 return ret_val;
582
583 if (!link) {
584 /* We didn't get link.
585 * Reset the DSP and cross our fingers.
586 */
587 ret_val = e1000e_phy_reset_dsp(hw);
588 if (ret_val)
589 return ret_val;
590 }
591
592 /* Try once more */
593 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
594 100000, &link);
595 if (ret_val)
596 return ret_val;
597 }
598
599 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
600 if (ret_val)
601 return ret_val;
602
603 /* Resetting the phy means we need to verify the TX_CLK corresponds
604 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
605 */
606 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
607 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
608 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
609 else
610 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
611
612 /* In addition, we must re-enable CRS on Tx for both half and full
613 * duplex.
614 */
615 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
616 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
617
618 return ret_val;
619}
620
621/**
622 * e1000_get_cable_length_80003es2lan - Set approximate cable length
623 * @hw: pointer to the HW structure
624 *
625 * Find the approximate cable length as measured by the GG82563 PHY.
626 * This is a function pointer entry point called by the phy module.
627 **/
628static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
629{
630 struct e1000_phy_info *phy = &hw->phy;
631 s32 ret_val;
632 u16 phy_data, index;
633
634 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
635 if (ret_val)
636 return ret_val;
637
638 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
639
640 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
641 return -E1000_ERR_PHY;
642
643 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
644 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
645
646 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
647
648 return 0;
649}
650
651/**
652 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
653 * @hw: pointer to the HW structure
654 * @speed: pointer to speed buffer
655 * @duplex: pointer to duplex buffer
656 *
657 * Retrieve the current speed and duplex configuration.
658 **/
659static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
660 u16 *duplex)
661{
662 s32 ret_val;
663
664 if (hw->phy.media_type == e1000_media_type_copper) {
665 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
666 hw->phy.ops.cfg_on_link_up(hw);
667 } else {
668 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
669 speed,
670 duplex);
671 }
672
673 return ret_val;
674}
675
676/**
677 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
678 * @hw: pointer to the HW structure
679 *
680 * Perform a global reset to the ESB2 controller.
681 **/
682static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
683{
684 u32 ctrl;
685 s32 ret_val;
686 u16 kum_reg_data;
687
688 /* Prevent the PCI-E bus from sticking if there is no TLP connection
689 * on the last TLP read/write transaction when MAC is reset.
690 */
691 ret_val = e1000e_disable_pcie_master(hw);
692 if (ret_val)
693 e_dbg("PCI-E Master disable polling has failed.\n");
694
695 e_dbg("Masking off all interrupts\n");
696 ew32(IMC, 0xffffffff);
697
698 ew32(RCTL, 0);
699 ew32(TCTL, E1000_TCTL_PSP);
700 e1e_flush();
701
702 usleep_range(10000, 20000);
703
704 ctrl = er32(CTRL);
705
706 ret_val = e1000_acquire_phy_80003es2lan(hw);
707 if (ret_val)
708 return ret_val;
709
710 e_dbg("Issuing a global reset to MAC\n");
711 ew32(CTRL, ctrl | E1000_CTRL_RST);
712 e1000_release_phy_80003es2lan(hw);
713
714 /* Disable IBIST slave mode (far-end loopback) */
715 ret_val =
716 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
717 &kum_reg_data);
718 if (ret_val)
719 return ret_val;
720 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
721 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
722 kum_reg_data);
723
724 ret_val = e1000e_get_auto_rd_done(hw);
725 if (ret_val)
726 /* We don't want to continue accessing MAC registers. */
727 return ret_val;
728
729 /* Clear any pending interrupt events. */
730 ew32(IMC, 0xffffffff);
731 er32(ICR);
732
733 return e1000_check_alt_mac_addr_generic(hw);
734}
735
736/**
737 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
738 * @hw: pointer to the HW structure
739 *
740 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
741 **/
742static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
743{
744 struct e1000_mac_info *mac = &hw->mac;
745 u32 reg_data;
746 s32 ret_val;
747 u16 kum_reg_data;
748 u16 i;
749
750 e1000_initialize_hw_bits_80003es2lan(hw);
751
752 /* Initialize identification LED */
753 ret_val = mac->ops.id_led_init(hw);
754 /* An error is not fatal and we should not stop init due to this */
755 if (ret_val)
756 e_dbg("Error initializing identification LED\n");
757
758 /* Disabling VLAN filtering */
759 e_dbg("Initializing the IEEE VLAN\n");
760 mac->ops.clear_vfta(hw);
761
762 /* Setup the receive address. */
763 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
764
765 /* Zero out the Multicast HASH table */
766 e_dbg("Zeroing the MTA\n");
767 for (i = 0; i < mac->mta_reg_count; i++)
768 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
769
770 /* Setup link and flow control */
771 ret_val = mac->ops.setup_link(hw);
772 if (ret_val)
773 return ret_val;
774
775 /* Disable IBIST slave mode (far-end loopback) */
776 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
777 &kum_reg_data);
778 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
779 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
780 kum_reg_data);
781
782 /* Set the transmit descriptor write-back policy */
783 reg_data = er32(TXDCTL(0));
784 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
785 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
786 ew32(TXDCTL(0), reg_data);
787
788 /* ...for both queues. */
789 reg_data = er32(TXDCTL(1));
790 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
791 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
792 ew32(TXDCTL(1), reg_data);
793
794 /* Enable retransmit on late collisions */
795 reg_data = er32(TCTL);
796 reg_data |= E1000_TCTL_RTLC;
797 ew32(TCTL, reg_data);
798
799 /* Configure Gigabit Carry Extend Padding */
800 reg_data = er32(TCTL_EXT);
801 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
802 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
803 ew32(TCTL_EXT, reg_data);
804
805 /* Configure Transmit Inter-Packet Gap */
806 reg_data = er32(TIPG);
807 reg_data &= ~E1000_TIPG_IPGT_MASK;
808 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
809 ew32(TIPG, reg_data);
810
811 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
812 reg_data &= ~0x00100000;
813 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
814
815 /* default to true to enable the MDIC W/A */
816 hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
817
818 ret_val =
819 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
820 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
821 if (!ret_val) {
822 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
823 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
824 hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
825 }
826
827 /* Clear all of the statistics registers (clear on read). It is
828 * important that we do this after we have tried to establish link
829 * because the symbol error count will increment wildly if there
830 * is no link.
831 */
832 e1000_clear_hw_cntrs_80003es2lan(hw);
833
834 return ret_val;
835}
836
837/**
838 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
839 * @hw: pointer to the HW structure
840 *
841 * Initializes required hardware-dependent bits needed for normal operation.
842 **/
843static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
844{
845 u32 reg;
846
847 /* Transmit Descriptor Control 0 */
848 reg = er32(TXDCTL(0));
849 reg |= BIT(22);
850 ew32(TXDCTL(0), reg);
851
852 /* Transmit Descriptor Control 1 */
853 reg = er32(TXDCTL(1));
854 reg |= BIT(22);
855 ew32(TXDCTL(1), reg);
856
857 /* Transmit Arbitration Control 0 */
858 reg = er32(TARC(0));
859 reg &= ~(0xF << 27); /* 30:27 */
860 if (hw->phy.media_type != e1000_media_type_copper)
861 reg &= ~BIT(20);
862 ew32(TARC(0), reg);
863
864 /* Transmit Arbitration Control 1 */
865 reg = er32(TARC(1));
866 if (er32(TCTL) & E1000_TCTL_MULR)
867 reg &= ~BIT(28);
868 else
869 reg |= BIT(28);
870 ew32(TARC(1), reg);
871
872 /* Disable IPv6 extension header parsing because some malformed
873 * IPv6 headers can hang the Rx.
874 */
875 reg = er32(RFCTL);
876 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
877 ew32(RFCTL, reg);
878}
879
880/**
881 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
882 * @hw: pointer to the HW structure
883 *
884 * Setup some GG82563 PHY registers for obtaining link
885 **/
886static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
887{
888 struct e1000_phy_info *phy = &hw->phy;
889 s32 ret_val;
890 u32 reg;
891 u16 data;
892
893 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
894 if (ret_val)
895 return ret_val;
896
897 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
898 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
899 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
900
901 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
902 if (ret_val)
903 return ret_val;
904
905 /* Options:
906 * MDI/MDI-X = 0 (default)
907 * 0 - Auto for all speeds
908 * 1 - MDI mode
909 * 2 - MDI-X mode
910 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
911 */
912 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
913 if (ret_val)
914 return ret_val;
915
916 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
917
918 switch (phy->mdix) {
919 case 1:
920 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
921 break;
922 case 2:
923 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
924 break;
925 case 0:
926 default:
927 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
928 break;
929 }
930
931 /* Options:
932 * disable_polarity_correction = 0 (default)
933 * Automatic Correction for Reversed Cable Polarity
934 * 0 - Disabled
935 * 1 - Enabled
936 */
937 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
938 if (phy->disable_polarity_correction)
939 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
940
941 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
942 if (ret_val)
943 return ret_val;
944
945 /* SW Reset the PHY so all changes take effect */
946 ret_val = hw->phy.ops.commit(hw);
947 if (ret_val) {
948 e_dbg("Error Resetting the PHY\n");
949 return ret_val;
950 }
951
952 /* Bypass Rx and Tx FIFO's */
953 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
954 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
955 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
956 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
957 if (ret_val)
958 return ret_val;
959
960 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
961 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
962 if (ret_val)
963 return ret_val;
964 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
965 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
966 if (ret_val)
967 return ret_val;
968
969 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
970 if (ret_val)
971 return ret_val;
972
973 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
974 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
975 if (ret_val)
976 return ret_val;
977
978 reg = er32(CTRL_EXT);
979 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
980 ew32(CTRL_EXT, reg);
981
982 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
983 if (ret_val)
984 return ret_val;
985
986 /* Do not init these registers when the HW is in IAMT mode, since the
987 * firmware will have already initialized them. We only initialize
988 * them if the HW is not in IAMT mode.
989 */
990 if (!hw->mac.ops.check_mng_mode(hw)) {
991 /* Enable Electrical Idle on the PHY */
992 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
993 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
994 if (ret_val)
995 return ret_val;
996
997 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
998 if (ret_val)
999 return ret_val;
1000
1001 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1002 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1003 if (ret_val)
1004 return ret_val;
1005 }
1006
1007 /* Workaround: Disable padding in Kumeran interface in the MAC
1008 * and in the PHY to avoid CRC errors.
1009 */
1010 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1011 if (ret_val)
1012 return ret_val;
1013
1014 data |= GG82563_ICR_DIS_PADDING;
1015 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1016 if (ret_val)
1017 return ret_val;
1018
1019 return 0;
1020}
1021
1022/**
1023 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1024 * @hw: pointer to the HW structure
1025 *
1026 * Essentially a wrapper for setting up all things "copper" related.
1027 * This is a function pointer entry point called by the mac module.
1028 **/
1029static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1030{
1031 u32 ctrl;
1032 s32 ret_val;
1033 u16 reg_data;
1034
1035 ctrl = er32(CTRL);
1036 ctrl |= E1000_CTRL_SLU;
1037 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1038 ew32(CTRL, ctrl);
1039
1040 /* Set the mac to wait the maximum time between each
1041 * iteration and increase the max iterations when
1042 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1043 */
1044 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1045 0xFFFF);
1046 if (ret_val)
1047 return ret_val;
1048 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1049 ®_data);
1050 if (ret_val)
1051 return ret_val;
1052 reg_data |= 0x3F;
1053 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1054 reg_data);
1055 if (ret_val)
1056 return ret_val;
1057 ret_val =
1058 e1000_read_kmrn_reg_80003es2lan(hw,
1059 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1060 ®_data);
1061 if (ret_val)
1062 return ret_val;
1063 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1064 ret_val =
1065 e1000_write_kmrn_reg_80003es2lan(hw,
1066 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1067 reg_data);
1068 if (ret_val)
1069 return ret_val;
1070
1071 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1072 if (ret_val)
1073 return ret_val;
1074
1075 return e1000e_setup_copper_link(hw);
1076}
1077
1078/**
1079 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1080 * @hw: pointer to the HW structure
1081 * @duplex: current duplex setting
1082 *
1083 * Configure the KMRN interface by applying last minute quirks for
1084 * 10/100 operation.
1085 **/
1086static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1087{
1088 s32 ret_val = 0;
1089 u16 speed;
1090 u16 duplex;
1091
1092 if (hw->phy.media_type == e1000_media_type_copper) {
1093 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1094 &duplex);
1095 if (ret_val)
1096 return ret_val;
1097
1098 if (speed == SPEED_1000)
1099 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1100 else
1101 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1102 }
1103
1104 return ret_val;
1105}
1106
1107/**
1108 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1109 * @hw: pointer to the HW structure
1110 * @duplex: current duplex setting
1111 *
1112 * Configure the KMRN interface by applying last minute quirks for
1113 * 10/100 operation.
1114 **/
1115static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1116{
1117 s32 ret_val;
1118 u32 tipg;
1119 u32 i = 0;
1120 u16 reg_data, reg_data2;
1121
1122 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1123 ret_val =
1124 e1000_write_kmrn_reg_80003es2lan(hw,
1125 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1126 reg_data);
1127 if (ret_val)
1128 return ret_val;
1129
1130 /* Configure Transmit Inter-Packet Gap */
1131 tipg = er32(TIPG);
1132 tipg &= ~E1000_TIPG_IPGT_MASK;
1133 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1134 ew32(TIPG, tipg);
1135
1136 do {
1137 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1138 if (ret_val)
1139 return ret_val;
1140
1141 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1142 if (ret_val)
1143 return ret_val;
1144 i++;
1145 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1146
1147 if (duplex == HALF_DUPLEX)
1148 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1149 else
1150 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1151
1152 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1153}
1154
1155/**
1156 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1157 * @hw: pointer to the HW structure
1158 *
1159 * Configure the KMRN interface by applying last minute quirks for
1160 * gigabit operation.
1161 **/
1162static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1163{
1164 s32 ret_val;
1165 u16 reg_data, reg_data2;
1166 u32 tipg;
1167 u32 i = 0;
1168
1169 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1170 ret_val =
1171 e1000_write_kmrn_reg_80003es2lan(hw,
1172 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1173 reg_data);
1174 if (ret_val)
1175 return ret_val;
1176
1177 /* Configure Transmit Inter-Packet Gap */
1178 tipg = er32(TIPG);
1179 tipg &= ~E1000_TIPG_IPGT_MASK;
1180 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1181 ew32(TIPG, tipg);
1182
1183 do {
1184 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1185 if (ret_val)
1186 return ret_val;
1187
1188 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1189 if (ret_val)
1190 return ret_val;
1191 i++;
1192 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1193
1194 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1195
1196 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1197}
1198
1199/**
1200 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1201 * @hw: pointer to the HW structure
1202 * @offset: register offset to be read
1203 * @data: pointer to the read data
1204 *
1205 * Acquire semaphore, then read the PHY register at offset
1206 * using the kumeran interface. The information retrieved is stored in data.
1207 * Release the semaphore before exiting.
1208 **/
1209static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1210 u16 *data)
1211{
1212 u32 kmrnctrlsta;
1213 s32 ret_val;
1214
1215 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1216 if (ret_val)
1217 return ret_val;
1218
1219 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1220 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1221 ew32(KMRNCTRLSTA, kmrnctrlsta);
1222 e1e_flush();
1223
1224 udelay(2);
1225
1226 kmrnctrlsta = er32(KMRNCTRLSTA);
1227 *data = (u16)kmrnctrlsta;
1228
1229 e1000_release_mac_csr_80003es2lan(hw);
1230
1231 return ret_val;
1232}
1233
1234/**
1235 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1236 * @hw: pointer to the HW structure
1237 * @offset: register offset to write to
1238 * @data: data to write at register offset
1239 *
1240 * Acquire semaphore, then write the data to PHY register
1241 * at the offset using the kumeran interface. Release semaphore
1242 * before exiting.
1243 **/
1244static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1245 u16 data)
1246{
1247 u32 kmrnctrlsta;
1248 s32 ret_val;
1249
1250 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1251 if (ret_val)
1252 return ret_val;
1253
1254 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1255 E1000_KMRNCTRLSTA_OFFSET) | data;
1256 ew32(KMRNCTRLSTA, kmrnctrlsta);
1257 e1e_flush();
1258
1259 udelay(2);
1260
1261 e1000_release_mac_csr_80003es2lan(hw);
1262
1263 return ret_val;
1264}
1265
1266/**
1267 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1268 * @hw: pointer to the HW structure
1269 **/
1270static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1271{
1272 s32 ret_val;
1273
1274 /* If there's an alternate MAC address place it in RAR0
1275 * so that it will override the Si installed default perm
1276 * address.
1277 */
1278 ret_val = e1000_check_alt_mac_addr_generic(hw);
1279 if (ret_val)
1280 return ret_val;
1281
1282 return e1000_read_mac_addr_generic(hw);
1283}
1284
1285/**
1286 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1287 * @hw: pointer to the HW structure
1288 *
1289 * In the case of a PHY power down to save power, or to turn off link during a
1290 * driver unload, or wake on lan is not enabled, remove the link.
1291 **/
1292static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1293{
1294 /* If the management interface is not enabled, then power down */
1295 if (!(hw->mac.ops.check_mng_mode(hw) ||
1296 hw->phy.ops.check_reset_block(hw)))
1297 e1000_power_down_phy_copper(hw);
1298}
1299
1300/**
1301 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1302 * @hw: pointer to the HW structure
1303 *
1304 * Clears the hardware counters by reading the counter registers.
1305 **/
1306static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1307{
1308 e1000e_clear_hw_cntrs_base(hw);
1309
1310 er32(PRC64);
1311 er32(PRC127);
1312 er32(PRC255);
1313 er32(PRC511);
1314 er32(PRC1023);
1315 er32(PRC1522);
1316 er32(PTC64);
1317 er32(PTC127);
1318 er32(PTC255);
1319 er32(PTC511);
1320 er32(PTC1023);
1321 er32(PTC1522);
1322
1323 er32(ALGNERRC);
1324 er32(RXERRC);
1325 er32(TNCRS);
1326 er32(CEXTERR);
1327 er32(TSCTC);
1328 er32(TSCTFC);
1329
1330 er32(MGTPRC);
1331 er32(MGTPDC);
1332 er32(MGTPTC);
1333
1334 er32(IAC);
1335 er32(ICRXOC);
1336
1337 er32(ICRXPTC);
1338 er32(ICRXATC);
1339 er32(ICTXPTC);
1340 er32(ICTXATC);
1341 er32(ICTXQEC);
1342 er32(ICTXQMTC);
1343 er32(ICRXDMTC);
1344}
1345
1346static const struct e1000_mac_operations es2_mac_ops = {
1347 .read_mac_addr = e1000_read_mac_addr_80003es2lan,
1348 .id_led_init = e1000e_id_led_init_generic,
1349 .blink_led = e1000e_blink_led_generic,
1350 .check_mng_mode = e1000e_check_mng_mode_generic,
1351 /* check_for_link dependent on media type */
1352 .cleanup_led = e1000e_cleanup_led_generic,
1353 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
1354 .get_bus_info = e1000e_get_bus_info_pcie,
1355 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1356 .get_link_up_info = e1000_get_link_up_info_80003es2lan,
1357 .led_on = e1000e_led_on_generic,
1358 .led_off = e1000e_led_off_generic,
1359 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1360 .write_vfta = e1000_write_vfta_generic,
1361 .clear_vfta = e1000_clear_vfta_generic,
1362 .reset_hw = e1000_reset_hw_80003es2lan,
1363 .init_hw = e1000_init_hw_80003es2lan,
1364 .setup_link = e1000e_setup_link_generic,
1365 /* setup_physical_interface dependent on media type */
1366 .setup_led = e1000e_setup_led_generic,
1367 .config_collision_dist = e1000e_config_collision_dist_generic,
1368 .rar_set = e1000e_rar_set_generic,
1369 .rar_get_count = e1000e_rar_get_count_generic,
1370};
1371
1372static const struct e1000_phy_operations es2_phy_ops = {
1373 .acquire = e1000_acquire_phy_80003es2lan,
1374 .check_polarity = e1000_check_polarity_m88,
1375 .check_reset_block = e1000e_check_reset_block_generic,
1376 .commit = e1000e_phy_sw_reset,
1377 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1378 .get_cfg_done = e1000_get_cfg_done_80003es2lan,
1379 .get_cable_length = e1000_get_cable_length_80003es2lan,
1380 .get_info = e1000e_get_phy_info_m88,
1381 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
1382 .release = e1000_release_phy_80003es2lan,
1383 .reset = e1000e_phy_hw_reset_generic,
1384 .set_d0_lplu_state = NULL,
1385 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1386 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1387 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
1388};
1389
1390static const struct e1000_nvm_operations es2_nvm_ops = {
1391 .acquire = e1000_acquire_nvm_80003es2lan,
1392 .read = e1000e_read_nvm_eerd,
1393 .release = e1000_release_nvm_80003es2lan,
1394 .reload = e1000e_reload_nvm_generic,
1395 .update = e1000e_update_nvm_checksum_generic,
1396 .valid_led_default = e1000e_valid_led_default,
1397 .validate = e1000e_validate_nvm_checksum_generic,
1398 .write = e1000_write_nvm_80003es2lan,
1399};
1400
1401const struct e1000_info e1000_es2_info = {
1402 .mac = e1000_80003es2lan,
1403 .flags = FLAG_HAS_HW_VLAN_FILTER
1404 | FLAG_HAS_JUMBO_FRAMES
1405 | FLAG_HAS_WOL
1406 | FLAG_APME_IN_CTRL3
1407 | FLAG_HAS_CTRLEXT_ON_LOAD
1408 | FLAG_RX_NEEDS_RESTART /* errata */
1409 | FLAG_TARC_SET_BIT_ZERO /* errata */
1410 | FLAG_APME_CHECK_PORT_B
1411 | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1412 .flags2 = FLAG2_DMA_BURST,
1413 .pba = 38,
1414 .max_hw_frame_size = DEFAULT_JUMBO,
1415 .get_variants = e1000_get_variants_80003es2lan,
1416 .mac_ops = &es2_mac_ops,
1417 .phy_ops = &es2_phy_ops,
1418 .nvm_ops = &es2_nvm_ops,
1419};