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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27
28#include "dm_services.h"
29#include "dc.h"
30
31#include "dcn31/dcn31_init.h"
32#include "dcn314/dcn314_init.h"
33
34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn314_resource.h"
37
38#include "dcn20/dcn20_resource.h"
39#include "dcn30/dcn30_resource.h"
40#include "dcn31/dcn31_resource.h"
41
42#include "dcn10/dcn10_ipp.h"
43#include "dcn30/dcn30_hubbub.h"
44#include "dcn31/dcn31_hubbub.h"
45#include "dcn30/dcn30_mpc.h"
46#include "dcn31/dcn31_hubp.h"
47#include "irq/dcn31/irq_service_dcn31.h"
48#include "irq/dcn314/irq_service_dcn314.h"
49#include "dcn30/dcn30_dpp.h"
50#include "dcn314/dcn314_optc.h"
51#include "dcn20/dcn20_hwseq.h"
52#include "dcn30/dcn30_hwseq.h"
53#include "dce110/dce110_hwseq.h"
54#include "dcn30/dcn30_opp.h"
55#include "dcn20/dcn20_dsc.h"
56#include "dcn30/dcn30_vpg.h"
57#include "dcn30/dcn30_afmt.h"
58#include "dcn31/dcn31_dio_link_encoder.h"
59#include "dcn314/dcn314_dio_stream_encoder.h"
60#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
61#include "dcn31/dcn31_hpo_dp_link_encoder.h"
62#include "dcn31/dcn31_apg.h"
63#include "dcn31/dcn31_vpg.h"
64#include "dcn31/dcn31_afmt.h"
65#include "dce/dce_clock_source.h"
66#include "dce/dce_audio.h"
67#include "dce/dce_hwseq.h"
68#include "clk_mgr.h"
69#include "virtual/virtual_stream_encoder.h"
70#include "dce110/dce110_resource.h"
71#include "dml/display_mode_vba.h"
72#include "dml/dcn31/dcn31_fpu.h"
73#include "dml/dcn314/dcn314_fpu.h"
74#include "dcn314/dcn314_dccg.h"
75#include "dcn10/dcn10_resource.h"
76#include "dcn31/dcn31_panel_cntl.h"
77#include "dcn314/dcn314_hwseq.h"
78
79#include "dcn30/dcn30_dwb.h"
80#include "dcn30/dcn30_mmhubbub.h"
81
82#include "dcn/dcn_3_1_4_offset.h"
83#include "dcn/dcn_3_1_4_sh_mask.h"
84#include "dpcs/dpcs_3_1_4_offset.h"
85#include "dpcs/dpcs_3_1_4_sh_mask.h"
86
87#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
88#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
89
90#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
91#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
92
93#include "reg_helper.h"
94#include "dce/dmub_abm.h"
95#include "dce/dmub_psr.h"
96#include "dce/dmub_replay.h"
97#include "dce/dce_aux.h"
98#include "dce/dce_i2c.h"
99#include "dml/dcn314/display_mode_vba_314.h"
100#include "vm_helper.h"
101#include "dcn20/dcn20_vmid.h"
102
103#include "link_enc_cfg.h"
104
105#define DCN_BASE__INST0_SEG1 0x000000C0
106#define DCN_BASE__INST0_SEG2 0x000034C0
107#define DCN_BASE__INST0_SEG3 0x00009000
108
109#define NBIO_BASE__INST0_SEG1 0x00000014
110
111#define MAX_INSTANCE 7
112#define MAX_SEGMENT 8
113
114#define regBIF_BX2_BIOS_SCRATCH_2 0x003a
115#define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1
116#define regBIF_BX2_BIOS_SCRATCH_3 0x003b
117#define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1
118#define regBIF_BX2_BIOS_SCRATCH_6 0x003e
119#define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1
120
121#define DC_LOGGER \
122 dc->ctx->logger
123#define DC_LOGGER_INIT(logger)
124
125enum dcn31_clk_src_array_id {
126 DCN31_CLK_SRC_PLL0,
127 DCN31_CLK_SRC_PLL1,
128 DCN31_CLK_SRC_PLL2,
129 DCN31_CLK_SRC_PLL3,
130 DCN31_CLK_SRC_PLL4,
131 DCN30_CLK_SRC_TOTAL
132};
133
134/* begin *********************
135 * macros to expend register list macro defined in HW object header file
136 */
137
138/* DCN */
139/* TODO awful hack. fixup dcn20_dwb.h */
140#undef BASE_INNER
141#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
142
143#define BASE(seg) BASE_INNER(seg)
144
145#define SR(reg_name)\
146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
147 reg ## reg_name
148
149#define SRI(reg_name, block, id)\
150 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 reg ## block ## id ## _ ## reg_name
152
153#define SRI2(reg_name, block, id)\
154 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
155 reg ## reg_name
156
157#define SRIR(var_name, reg_name, block, id)\
158 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
159 reg ## block ## id ## _ ## reg_name
160
161#define SRII(reg_name, block, id)\
162 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
163 reg ## block ## id ## _ ## reg_name
164
165#define SRII_MPC_RMU(reg_name, block, id)\
166 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
167 reg ## block ## id ## _ ## reg_name
168
169#define SRII_DWB(reg_name, temp_name, block, id)\
170 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
171 reg ## block ## id ## _ ## temp_name
172
173#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
174 .field_name = reg_name ## __ ## field_name ## post_fix
175
176#define DCCG_SRII(reg_name, block, id)\
177 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
178 reg ## block ## id ## _ ## reg_name
179
180#define VUPDATE_SRII(reg_name, block, id)\
181 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
182 reg ## reg_name ## _ ## block ## id
183
184/* NBIO */
185#define NBIO_BASE_INNER(seg) \
186 NBIO_BASE__INST0_SEG ## seg
187
188#define NBIO_BASE(seg) \
189 NBIO_BASE_INNER(seg)
190
191#define NBIO_SR(reg_name)\
192 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
193 regBIF_BX2_ ## reg_name
194
195/* MMHUB */
196#define MMHUB_BASE_INNER(seg) \
197 MMHUB_BASE__INST0_SEG ## seg
198
199#define MMHUB_BASE(seg) \
200 MMHUB_BASE_INNER(seg)
201
202#define MMHUB_SR(reg_name)\
203 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \
204 reg ## reg_name
205
206/* CLOCK */
207#define CLK_BASE_INNER(seg) \
208 CLK_BASE__INST0_SEG ## seg
209
210#define CLK_BASE(seg) \
211 CLK_BASE_INNER(seg)
212
213#define CLK_SRI(reg_name, block, inst)\
214 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
215 reg ## block ## _ ## inst ## _ ## reg_name
216
217
218static const struct bios_registers bios_regs = {
219 NBIO_SR(BIOS_SCRATCH_3),
220 NBIO_SR(BIOS_SCRATCH_6)
221};
222
223#define clk_src_regs(index, pllid)\
224[index] = {\
225 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
226}
227
228static const struct dce110_clk_src_regs clk_src_regs[] = {
229 clk_src_regs(0, A),
230 clk_src_regs(1, B),
231 clk_src_regs(2, C),
232 clk_src_regs(3, D),
233 clk_src_regs(4, E)
234};
235
236static const struct dce110_clk_src_shift cs_shift = {
237 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
238};
239
240static const struct dce110_clk_src_mask cs_mask = {
241 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
242};
243
244#define abm_regs(id)\
245[id] = {\
246 ABM_DCN302_REG_LIST(id)\
247}
248
249static const struct dce_abm_registers abm_regs[] = {
250 abm_regs(0),
251 abm_regs(1),
252 abm_regs(2),
253 abm_regs(3),
254};
255
256static const struct dce_abm_shift abm_shift = {
257 ABM_MASK_SH_LIST_DCN30(__SHIFT)
258};
259
260static const struct dce_abm_mask abm_mask = {
261 ABM_MASK_SH_LIST_DCN30(_MASK)
262};
263
264#define audio_regs(id)\
265[id] = {\
266 AUD_COMMON_REG_LIST(id)\
267}
268
269static const struct dce_audio_registers audio_regs[] = {
270 audio_regs(0),
271 audio_regs(1),
272 audio_regs(2),
273 audio_regs(3),
274 audio_regs(4),
275 audio_regs(5),
276 audio_regs(6)
277};
278
279#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
280 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
281 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
282 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
283
284static const struct dce_audio_shift audio_shift = {
285 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
286};
287
288static const struct dce_audio_mask audio_mask = {
289 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
290};
291
292#define vpg_regs(id)\
293[id] = {\
294 VPG_DCN31_REG_LIST(id)\
295}
296
297static const struct dcn31_vpg_registers vpg_regs[] = {
298 vpg_regs(0),
299 vpg_regs(1),
300 vpg_regs(2),
301 vpg_regs(3),
302 vpg_regs(4),
303 vpg_regs(5),
304 vpg_regs(6),
305 vpg_regs(7),
306 vpg_regs(8),
307 vpg_regs(9),
308};
309
310static const struct dcn31_vpg_shift vpg_shift = {
311 DCN31_VPG_MASK_SH_LIST(__SHIFT)
312};
313
314static const struct dcn31_vpg_mask vpg_mask = {
315 DCN31_VPG_MASK_SH_LIST(_MASK)
316};
317
318#define afmt_regs(id)\
319[id] = {\
320 AFMT_DCN31_REG_LIST(id)\
321}
322
323static const struct dcn31_afmt_registers afmt_regs[] = {
324 afmt_regs(0),
325 afmt_regs(1),
326 afmt_regs(2),
327 afmt_regs(3),
328 afmt_regs(4),
329 afmt_regs(5)
330};
331
332static const struct dcn31_afmt_shift afmt_shift = {
333 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
334};
335
336static const struct dcn31_afmt_mask afmt_mask = {
337 DCN31_AFMT_MASK_SH_LIST(_MASK)
338};
339
340#define apg_regs(id)\
341[id] = {\
342 APG_DCN31_REG_LIST(id)\
343}
344
345static const struct dcn31_apg_registers apg_regs[] = {
346 apg_regs(0),
347 apg_regs(1),
348 apg_regs(2),
349 apg_regs(3)
350};
351
352static const struct dcn31_apg_shift apg_shift = {
353 DCN31_APG_MASK_SH_LIST(__SHIFT)
354};
355
356static const struct dcn31_apg_mask apg_mask = {
357 DCN31_APG_MASK_SH_LIST(_MASK)
358};
359
360#define stream_enc_regs(id)\
361[id] = {\
362 SE_DCN314_REG_LIST(id)\
363}
364
365static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
366 stream_enc_regs(0),
367 stream_enc_regs(1),
368 stream_enc_regs(2),
369 stream_enc_regs(3),
370 stream_enc_regs(4)
371};
372
373static const struct dcn10_stream_encoder_shift se_shift = {
374 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT)
375};
376
377static const struct dcn10_stream_encoder_mask se_mask = {
378 SE_COMMON_MASK_SH_LIST_DCN314(_MASK)
379};
380
381
382#define aux_regs(id)\
383[id] = {\
384 DCN2_AUX_REG_LIST(id)\
385}
386
387static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
388 aux_regs(0),
389 aux_regs(1),
390 aux_regs(2),
391 aux_regs(3),
392 aux_regs(4)
393};
394
395#define hpd_regs(id)\
396[id] = {\
397 HPD_REG_LIST(id)\
398}
399
400static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
401 hpd_regs(0),
402 hpd_regs(1),
403 hpd_regs(2),
404 hpd_regs(3),
405 hpd_regs(4)
406};
407
408#define link_regs(id, phyid)\
409[id] = {\
410 LE_DCN31_REG_LIST(id), \
411 UNIPHY_DCN2_REG_LIST(phyid), \
412}
413
414static const struct dce110_aux_registers_shift aux_shift = {
415 DCN_AUX_MASK_SH_LIST(__SHIFT)
416};
417
418static const struct dce110_aux_registers_mask aux_mask = {
419 DCN_AUX_MASK_SH_LIST(_MASK)
420};
421
422static const struct dcn10_link_enc_registers link_enc_regs[] = {
423 link_regs(0, A),
424 link_regs(1, B),
425 link_regs(2, C),
426 link_regs(3, D),
427 link_regs(4, E)
428};
429
430static const struct dcn10_link_enc_shift le_shift = {
431 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT),
432 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
433};
434
435static const struct dcn10_link_enc_mask le_mask = {
436 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK),
437 DPCS_DCN31_MASK_SH_LIST(_MASK)
438};
439
440#define hpo_dp_stream_encoder_reg_list(id)\
441[id] = {\
442 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
443}
444
445static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
446 hpo_dp_stream_encoder_reg_list(0),
447 hpo_dp_stream_encoder_reg_list(1),
448 hpo_dp_stream_encoder_reg_list(2),
449 hpo_dp_stream_encoder_reg_list(3)
450};
451
452static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
453 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
454};
455
456static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
457 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
458};
459
460
461#define hpo_dp_link_encoder_reg_list(id)\
462[id] = {\
463 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
464 DCN3_1_RDPCSTX_REG_LIST(0),\
465 DCN3_1_RDPCSTX_REG_LIST(1),\
466 DCN3_1_RDPCSTX_REG_LIST(2),\
467}
468
469static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
470 hpo_dp_link_encoder_reg_list(0),
471 hpo_dp_link_encoder_reg_list(1),
472};
473
474static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
475 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
476};
477
478static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
479 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
480};
481
482#define dpp_regs(id)\
483[id] = {\
484 DPP_REG_LIST_DCN30(id),\
485}
486
487static const struct dcn3_dpp_registers dpp_regs[] = {
488 dpp_regs(0),
489 dpp_regs(1),
490 dpp_regs(2),
491 dpp_regs(3)
492};
493
494static const struct dcn3_dpp_shift tf_shift = {
495 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
496};
497
498static const struct dcn3_dpp_mask tf_mask = {
499 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
500};
501
502#define opp_regs(id)\
503[id] = {\
504 OPP_REG_LIST_DCN30(id),\
505}
506
507static const struct dcn20_opp_registers opp_regs[] = {
508 opp_regs(0),
509 opp_regs(1),
510 opp_regs(2),
511 opp_regs(3)
512};
513
514static const struct dcn20_opp_shift opp_shift = {
515 OPP_MASK_SH_LIST_DCN20(__SHIFT)
516};
517
518static const struct dcn20_opp_mask opp_mask = {
519 OPP_MASK_SH_LIST_DCN20(_MASK)
520};
521
522#define aux_engine_regs(id)\
523[id] = {\
524 AUX_COMMON_REG_LIST0(id), \
525 .AUXN_IMPCAL = 0, \
526 .AUXP_IMPCAL = 0, \
527 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
528}
529
530static const struct dce110_aux_registers aux_engine_regs[] = {
531 aux_engine_regs(0),
532 aux_engine_regs(1),
533 aux_engine_regs(2),
534 aux_engine_regs(3),
535 aux_engine_regs(4)
536};
537
538#define dwbc_regs_dcn3(id)\
539[id] = {\
540 DWBC_COMMON_REG_LIST_DCN30(id),\
541}
542
543static const struct dcn30_dwbc_registers dwbc30_regs[] = {
544 dwbc_regs_dcn3(0),
545};
546
547static const struct dcn30_dwbc_shift dwbc30_shift = {
548 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
549};
550
551static const struct dcn30_dwbc_mask dwbc30_mask = {
552 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
553};
554
555#define mcif_wb_regs_dcn3(id)\
556[id] = {\
557 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
558}
559
560static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
561 mcif_wb_regs_dcn3(0)
562};
563
564static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
565 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
566};
567
568static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
569 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
570};
571
572#define dsc_regsDCN314(id)\
573[id] = {\
574 DSC_REG_LIST_DCN20(id)\
575}
576
577static const struct dcn20_dsc_registers dsc_regs[] = {
578 dsc_regsDCN314(0),
579 dsc_regsDCN314(1),
580 dsc_regsDCN314(2),
581 dsc_regsDCN314(3)
582};
583
584static const struct dcn20_dsc_shift dsc_shift = {
585 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
586};
587
588static const struct dcn20_dsc_mask dsc_mask = {
589 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
590};
591
592static const struct dcn30_mpc_registers mpc_regs = {
593 MPC_REG_LIST_DCN3_0(0),
594 MPC_REG_LIST_DCN3_0(1),
595 MPC_REG_LIST_DCN3_0(2),
596 MPC_REG_LIST_DCN3_0(3),
597 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
598 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
599 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
600 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
601 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
602 MPC_RMU_REG_LIST_DCN3AG(0),
603 MPC_RMU_REG_LIST_DCN3AG(1),
604 //MPC_RMU_REG_LIST_DCN3AG(2),
605 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
606};
607
608static const struct dcn30_mpc_shift mpc_shift = {
609 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
610};
611
612static const struct dcn30_mpc_mask mpc_mask = {
613 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
614};
615
616#define optc_regs(id)\
617[id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)}
618
619static const struct dcn_optc_registers optc_regs[] = {
620 optc_regs(0),
621 optc_regs(1),
622 optc_regs(2),
623 optc_regs(3)
624};
625
626static const struct dcn_optc_shift optc_shift = {
627 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT)
628};
629
630static const struct dcn_optc_mask optc_mask = {
631 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK)
632};
633
634#define hubp_regs(id)\
635[id] = {\
636 HUBP_REG_LIST_DCN30(id)\
637}
638
639static const struct dcn_hubp2_registers hubp_regs[] = {
640 hubp_regs(0),
641 hubp_regs(1),
642 hubp_regs(2),
643 hubp_regs(3)
644};
645
646
647static const struct dcn_hubp2_shift hubp_shift = {
648 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
649};
650
651static const struct dcn_hubp2_mask hubp_mask = {
652 HUBP_MASK_SH_LIST_DCN31(_MASK)
653};
654static const struct dcn_hubbub_registers hubbub_reg = {
655 HUBBUB_REG_LIST_DCN31(0)
656};
657
658static const struct dcn_hubbub_shift hubbub_shift = {
659 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
660};
661
662static const struct dcn_hubbub_mask hubbub_mask = {
663 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
664};
665
666static const struct dccg_registers dccg_regs = {
667 DCCG_REG_LIST_DCN314()
668};
669
670static const struct dccg_shift dccg_shift = {
671 DCCG_MASK_SH_LIST_DCN314(__SHIFT)
672};
673
674static const struct dccg_mask dccg_mask = {
675 DCCG_MASK_SH_LIST_DCN314(_MASK)
676};
677
678
679#define SRII2(reg_name_pre, reg_name_post, id)\
680 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
681 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
682 reg ## reg_name_pre ## id ## _ ## reg_name_post
683
684
685#define HWSEQ_DCN31_REG_LIST()\
686 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
687 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
688 SR(DIO_MEM_PWR_CTRL), \
689 SR(ODM_MEM_PWR_CTRL3), \
690 SR(DMU_MEM_PWR_CNTL), \
691 SR(MMHUBBUB_MEM_PWR_CNTL), \
692 SR(DCCG_GATE_DISABLE_CNTL), \
693 SR(DCCG_GATE_DISABLE_CNTL2), \
694 SR(DCFCLK_CNTL),\
695 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
696 SRII(PIXEL_RATE_CNTL, OTG, 0), \
697 SRII(PIXEL_RATE_CNTL, OTG, 1),\
698 SRII(PIXEL_RATE_CNTL, OTG, 2),\
699 SRII(PIXEL_RATE_CNTL, OTG, 3),\
700 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
701 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
702 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
703 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
704 SR(MICROSECOND_TIME_BASE_DIV), \
705 SR(MILLISECOND_TIME_BASE_DIV), \
706 SR(DISPCLK_FREQ_CHANGE_CNTL), \
707 SR(RBBMIF_TIMEOUT_DIS), \
708 SR(RBBMIF_TIMEOUT_DIS_2), \
709 SR(DCHUBBUB_CRC_CTRL), \
710 SR(DPP_TOP0_DPP_CRC_CTRL), \
711 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
712 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
713 SR(MPC_CRC_CTRL), \
714 SR(MPC_CRC_RESULT_GB), \
715 SR(MPC_CRC_RESULT_C), \
716 SR(MPC_CRC_RESULT_AR), \
717 SR(DOMAIN0_PG_CONFIG), \
718 SR(DOMAIN1_PG_CONFIG), \
719 SR(DOMAIN2_PG_CONFIG), \
720 SR(DOMAIN3_PG_CONFIG), \
721 SR(DOMAIN16_PG_CONFIG), \
722 SR(DOMAIN17_PG_CONFIG), \
723 SR(DOMAIN18_PG_CONFIG), \
724 SR(DOMAIN19_PG_CONFIG), \
725 SR(DOMAIN0_PG_STATUS), \
726 SR(DOMAIN1_PG_STATUS), \
727 SR(DOMAIN2_PG_STATUS), \
728 SR(DOMAIN3_PG_STATUS), \
729 SR(DOMAIN16_PG_STATUS), \
730 SR(DOMAIN17_PG_STATUS), \
731 SR(DOMAIN18_PG_STATUS), \
732 SR(DOMAIN19_PG_STATUS), \
733 SR(D1VGA_CONTROL), \
734 SR(D2VGA_CONTROL), \
735 SR(D3VGA_CONTROL), \
736 SR(D4VGA_CONTROL), \
737 SR(D5VGA_CONTROL), \
738 SR(D6VGA_CONTROL), \
739 SR(DC_IP_REQUEST_CNTL), \
740 SR(AZALIA_AUDIO_DTO), \
741 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
742 SR(HPO_TOP_HW_CONTROL)
743
744static const struct dce_hwseq_registers hwseq_reg = {
745 HWSEQ_DCN31_REG_LIST()
746};
747
748#define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
749 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
750 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
751 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
752 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
753 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
754 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
755 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
756 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
757 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
758 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
759 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
760 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
761 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
762 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
763 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
764 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
765 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
766 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
767 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
768 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
769 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
770 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
771 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
772 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
773 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
774 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
775 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
776 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
777 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
778 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
779 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
780 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
781 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
782 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
783 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
784 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
785
786static const struct dce_hwseq_shift hwseq_shift = {
787 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
788};
789
790static const struct dce_hwseq_mask hwseq_mask = {
791 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
792};
793#define vmid_regs(id)\
794[id] = {\
795 DCN20_VMID_REG_LIST(id)\
796}
797
798static const struct dcn_vmid_registers vmid_regs[] = {
799 vmid_regs(0),
800 vmid_regs(1),
801 vmid_regs(2),
802 vmid_regs(3),
803 vmid_regs(4),
804 vmid_regs(5),
805 vmid_regs(6),
806 vmid_regs(7),
807 vmid_regs(8),
808 vmid_regs(9),
809 vmid_regs(10),
810 vmid_regs(11),
811 vmid_regs(12),
812 vmid_regs(13),
813 vmid_regs(14),
814 vmid_regs(15)
815};
816
817static const struct dcn20_vmid_shift vmid_shifts = {
818 DCN20_VMID_MASK_SH_LIST(__SHIFT)
819};
820
821static const struct dcn20_vmid_mask vmid_masks = {
822 DCN20_VMID_MASK_SH_LIST(_MASK)
823};
824
825static const struct resource_caps res_cap_dcn314 = {
826 .num_timing_generator = 4,
827 .num_opp = 4,
828 .num_video_plane = 4,
829 .num_audio = 5,
830 .num_stream_encoder = 5,
831 .num_dig_link_enc = 5,
832 .num_hpo_dp_stream_encoder = 4,
833 .num_hpo_dp_link_encoder = 2,
834 .num_pll = 5,
835 .num_dwb = 1,
836 .num_ddc = 5,
837 .num_vmid = 16,
838 .num_mpc_3dlut = 2,
839 .num_dsc = 4,
840};
841
842static const struct dc_plane_cap plane_cap = {
843 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
844 .per_pixel_alpha = true,
845
846 .pixel_format_support = {
847 .argb8888 = true,
848 .nv12 = true,
849 .fp16 = true,
850 .p010 = true,
851 .ayuv = false,
852 },
853
854 .max_upscale_factor = {
855 .argb8888 = 16000,
856 .nv12 = 16000,
857 .fp16 = 16000
858 },
859
860 // 6:1 downscaling ratio: 1000/6 = 166.666
861 // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250
862 .max_downscale_factor = {
863 .argb8888 = 250,
864 .nv12 = 167,
865 .fp16 = 167
866 },
867 64,
868 64
869};
870
871static const struct dc_debug_options debug_defaults_drv = {
872 .disable_z10 = false,
873 .enable_z9_disable_interface = true,
874 .minimum_z8_residency_time = 2100,
875 .psr_skip_crtc_disable = true,
876 .replay_skip_crtc_disabled = true,
877 .disable_dmcu = true,
878 .force_abm_enable = false,
879 .timing_trace = false,
880 .clock_trace = true,
881 .disable_dpp_power_gate = false,
882 .disable_hubp_power_gate = false,
883 .disable_pplib_clock_request = false,
884 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
885 .force_single_disp_pipe_split = false,
886 .disable_dcc = DCC_ENABLE,
887 .vsr_support = true,
888 .performance_trace = false,
889 .max_downscale_src_width = 4096,/*upto true 4k*/
890 .disable_pplib_wm_range = false,
891 .scl_reset_length10 = true,
892 .sanity_checks = true,
893 .underflow_assert_delay_us = 0xFFFFFFFF,
894 .dwb_fi_phase = -1, // -1 = disable,
895 .dmub_command_table = true,
896 .pstate_enabled = true,
897 .use_max_lb = true,
898 .enable_mem_low_power = {
899 .bits = {
900 .vga = true,
901 .i2c = true,
902 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
903 .dscl = true,
904 .cm = true,
905 .mpc = true,
906 .optc = true,
907 .vpg = true,
908 .afmt = true,
909 }
910 },
911
912 .root_clock_optimization = {
913 .bits = {
914 .dpp = true,
915 .dsc = true,
916 .hdmistream = true,
917 .hdmichar = true,
918 .dpstream = true,
919 .symclk32_se = false,
920 .symclk32_le = true,
921 .symclk_fe = true,
922 .physymclk = true,
923 .dpiasymclk = true,
924 }
925 },
926
927 .seamless_boot_odm_combine = true,
928 .using_dml2 = false,
929};
930
931static const struct dc_debug_options debug_defaults_diags = {
932 .disable_dmcu = true,
933 .force_abm_enable = false,
934 .timing_trace = true,
935 .clock_trace = true,
936 .disable_dpp_power_gate = true,
937 .disable_hubp_power_gate = true,
938 .disable_clock_gate = true,
939 .disable_pplib_clock_request = true,
940 .disable_pplib_wm_range = true,
941 .disable_stutter = false,
942 .scl_reset_length10 = true,
943 .dwb_fi_phase = -1, // -1 = disable
944 .dmub_command_table = true,
945 .enable_tri_buf = true,
946 .use_max_lb = true
947};
948
949static const struct dc_panel_config panel_config_defaults = {
950 .psr = {
951 .disable_psr = false,
952 .disallow_psrsu = false,
953 .disallow_replay = false,
954 },
955 .ilr = {
956 .optimize_edp_link_rate = true,
957 },
958};
959
960static void dcn31_dpp_destroy(struct dpp **dpp)
961{
962 kfree(TO_DCN20_DPP(*dpp));
963 *dpp = NULL;
964}
965
966static struct dpp *dcn31_dpp_create(
967 struct dc_context *ctx,
968 uint32_t inst)
969{
970 struct dcn3_dpp *dpp =
971 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
972
973 if (!dpp)
974 return NULL;
975
976 if (dpp3_construct(dpp, ctx, inst,
977 &dpp_regs[inst], &tf_shift, &tf_mask))
978 return &dpp->base;
979
980 BREAK_TO_DEBUGGER();
981 kfree(dpp);
982 return NULL;
983}
984
985static struct output_pixel_processor *dcn31_opp_create(
986 struct dc_context *ctx, uint32_t inst)
987{
988 struct dcn20_opp *opp =
989 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
990
991 if (!opp) {
992 BREAK_TO_DEBUGGER();
993 return NULL;
994 }
995
996 dcn20_opp_construct(opp, ctx, inst,
997 &opp_regs[inst], &opp_shift, &opp_mask);
998 return &opp->base;
999}
1000
1001static struct dce_aux *dcn31_aux_engine_create(
1002 struct dc_context *ctx,
1003 uint32_t inst)
1004{
1005 struct aux_engine_dce110 *aux_engine =
1006 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1007
1008 if (!aux_engine)
1009 return NULL;
1010
1011 dce110_aux_engine_construct(aux_engine, ctx, inst,
1012 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1013 &aux_engine_regs[inst],
1014 &aux_mask,
1015 &aux_shift,
1016 ctx->dc->caps.extended_aux_timeout_support);
1017
1018 return &aux_engine->base;
1019}
1020#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1021
1022static const struct dce_i2c_registers i2c_hw_regs[] = {
1023 i2c_inst_regs(1),
1024 i2c_inst_regs(2),
1025 i2c_inst_regs(3),
1026 i2c_inst_regs(4),
1027 i2c_inst_regs(5),
1028};
1029
1030static const struct dce_i2c_shift i2c_shifts = {
1031 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1032};
1033
1034static const struct dce_i2c_mask i2c_masks = {
1035 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1036};
1037
1038/* ========================================================== */
1039
1040/*
1041 * DPIA index | Preferred Encoder | Host Router
1042 * 0 | C | 0
1043 * 1 | First Available | 0
1044 * 2 | D | 1
1045 * 3 | First Available | 1
1046 */
1047/* ========================================================== */
1048static const enum engine_id dpia_to_preferred_enc_id_table[] = {
1049 ENGINE_ID_DIGC,
1050 ENGINE_ID_DIGC,
1051 ENGINE_ID_DIGD,
1052 ENGINE_ID_DIGD
1053};
1054
1055static enum engine_id dcn314_get_preferred_eng_id_dpia(unsigned int dpia_index)
1056{
1057 return dpia_to_preferred_enc_id_table[dpia_index];
1058}
1059
1060static struct dce_i2c_hw *dcn31_i2c_hw_create(
1061 struct dc_context *ctx,
1062 uint32_t inst)
1063{
1064 struct dce_i2c_hw *dce_i2c_hw =
1065 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1066
1067 if (!dce_i2c_hw)
1068 return NULL;
1069
1070 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1071 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1072
1073 return dce_i2c_hw;
1074}
1075static struct mpc *dcn31_mpc_create(
1076 struct dc_context *ctx,
1077 int num_mpcc,
1078 int num_rmu)
1079{
1080 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1081 GFP_KERNEL);
1082
1083 if (!mpc30)
1084 return NULL;
1085
1086 dcn30_mpc_construct(mpc30, ctx,
1087 &mpc_regs,
1088 &mpc_shift,
1089 &mpc_mask,
1090 num_mpcc,
1091 num_rmu);
1092
1093 return &mpc30->base;
1094}
1095
1096static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1097{
1098 int i;
1099
1100 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1101 GFP_KERNEL);
1102
1103 if (!hubbub3)
1104 return NULL;
1105
1106 hubbub31_construct(hubbub3, ctx,
1107 &hubbub_reg,
1108 &hubbub_shift,
1109 &hubbub_mask,
1110 dcn3_14_ip.det_buffer_size_kbytes,
1111 dcn3_14_ip.pixel_chunk_size_kbytes,
1112 dcn3_14_ip.config_return_buffer_size_in_kbytes);
1113
1114
1115 for (i = 0; i < res_cap_dcn314.num_vmid; i++) {
1116 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1117
1118 vmid->ctx = ctx;
1119
1120 vmid->regs = &vmid_regs[i];
1121 vmid->shifts = &vmid_shifts;
1122 vmid->masks = &vmid_masks;
1123 }
1124
1125 return &hubbub3->base;
1126}
1127
1128static struct timing_generator *dcn31_timing_generator_create(
1129 struct dc_context *ctx,
1130 uint32_t instance)
1131{
1132 struct optc *tgn10 =
1133 kzalloc(sizeof(struct optc), GFP_KERNEL);
1134
1135 if (!tgn10)
1136 return NULL;
1137
1138 tgn10->base.inst = instance;
1139 tgn10->base.ctx = ctx;
1140
1141 tgn10->tg_regs = &optc_regs[instance];
1142 tgn10->tg_shift = &optc_shift;
1143 tgn10->tg_mask = &optc_mask;
1144
1145 dcn314_timing_generator_init(tgn10);
1146
1147 return &tgn10->base;
1148}
1149
1150static const struct encoder_feature_support link_enc_feature = {
1151 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1152 .max_hdmi_pixel_clock = 600000,
1153 .hdmi_ycbcr420_supported = true,
1154 .dp_ycbcr420_supported = true,
1155 .fec_supported = true,
1156 .flags.bits.IS_HBR2_CAPABLE = true,
1157 .flags.bits.IS_HBR3_CAPABLE = true,
1158 .flags.bits.IS_TPS3_CAPABLE = true,
1159 .flags.bits.IS_TPS4_CAPABLE = true
1160};
1161
1162static struct link_encoder *dcn31_link_encoder_create(
1163 struct dc_context *ctx,
1164 const struct encoder_init_data *enc_init_data)
1165{
1166 struct dcn20_link_encoder *enc20 =
1167 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1168
1169 if (!enc20)
1170 return NULL;
1171
1172 dcn31_link_encoder_construct(enc20,
1173 enc_init_data,
1174 &link_enc_feature,
1175 &link_enc_regs[enc_init_data->transmitter],
1176 &link_enc_aux_regs[enc_init_data->channel - 1],
1177 &link_enc_hpd_regs[enc_init_data->hpd_source],
1178 &le_shift,
1179 &le_mask);
1180
1181 return &enc20->enc10.base;
1182}
1183
1184/* Create a minimal link encoder object not associated with a particular
1185 * physical connector.
1186 * resource_funcs.link_enc_create_minimal
1187 */
1188static struct link_encoder *dcn31_link_enc_create_minimal(
1189 struct dc_context *ctx, enum engine_id eng_id)
1190{
1191 struct dcn20_link_encoder *enc20;
1192
1193 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1194 return NULL;
1195
1196 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1197 if (!enc20)
1198 return NULL;
1199
1200 dcn31_link_encoder_construct_minimal(
1201 enc20,
1202 ctx,
1203 &link_enc_feature,
1204 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1205 eng_id);
1206
1207 return &enc20->enc10.base;
1208}
1209
1210static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1211{
1212 struct dcn31_panel_cntl *panel_cntl =
1213 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1214
1215 if (!panel_cntl)
1216 return NULL;
1217
1218 dcn31_panel_cntl_construct(panel_cntl, init_data);
1219
1220 return &panel_cntl->base;
1221}
1222
1223static void read_dce_straps(
1224 struct dc_context *ctx,
1225 struct resource_straps *straps)
1226{
1227 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1228 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1229
1230}
1231
1232static struct audio *dcn31_create_audio(
1233 struct dc_context *ctx, unsigned int inst)
1234{
1235 return dce_audio_create(ctx, inst,
1236 &audio_regs[inst], &audio_shift, &audio_mask);
1237}
1238
1239static struct vpg *dcn31_vpg_create(
1240 struct dc_context *ctx,
1241 uint32_t inst)
1242{
1243 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1244
1245 if (!vpg31)
1246 return NULL;
1247
1248 vpg31_construct(vpg31, ctx, inst,
1249 &vpg_regs[inst],
1250 &vpg_shift,
1251 &vpg_mask);
1252
1253 return &vpg31->base;
1254}
1255
1256static struct afmt *dcn31_afmt_create(
1257 struct dc_context *ctx,
1258 uint32_t inst)
1259{
1260 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1261
1262 if (!afmt31)
1263 return NULL;
1264
1265 afmt31_construct(afmt31, ctx, inst,
1266 &afmt_regs[inst],
1267 &afmt_shift,
1268 &afmt_mask);
1269
1270 // Light sleep by default, no need to power down here
1271
1272 return &afmt31->base;
1273}
1274
1275static struct apg *dcn31_apg_create(
1276 struct dc_context *ctx,
1277 uint32_t inst)
1278{
1279 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1280
1281 if (!apg31)
1282 return NULL;
1283
1284 apg31_construct(apg31, ctx, inst,
1285 &apg_regs[inst],
1286 &apg_shift,
1287 &apg_mask);
1288
1289 return &apg31->base;
1290}
1291
1292static struct stream_encoder *dcn314_stream_encoder_create(
1293 enum engine_id eng_id,
1294 struct dc_context *ctx)
1295{
1296 struct dcn10_stream_encoder *enc1;
1297 struct vpg *vpg;
1298 struct afmt *afmt;
1299 int vpg_inst;
1300 int afmt_inst;
1301
1302 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1303 if (eng_id < ENGINE_ID_DIGF) {
1304 vpg_inst = eng_id;
1305 afmt_inst = eng_id;
1306 } else
1307 return NULL;
1308
1309 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1310 vpg = dcn31_vpg_create(ctx, vpg_inst);
1311 afmt = dcn31_afmt_create(ctx, afmt_inst);
1312
1313 if (!enc1 || !vpg || !afmt) {
1314 kfree(enc1);
1315 kfree(vpg);
1316 kfree(afmt);
1317 return NULL;
1318 }
1319
1320 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1321 eng_id, vpg, afmt,
1322 &stream_enc_regs[eng_id],
1323 &se_shift, &se_mask);
1324
1325 return &enc1->base;
1326}
1327
1328static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1329 enum engine_id eng_id,
1330 struct dc_context *ctx)
1331{
1332 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1333 struct vpg *vpg;
1334 struct apg *apg;
1335 uint32_t hpo_dp_inst;
1336 uint32_t vpg_inst;
1337 uint32_t apg_inst;
1338
1339 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1340 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1341
1342 /* Mapping of VPG register blocks to HPO DP block instance:
1343 * VPG[6] -> HPO_DP[0]
1344 * VPG[7] -> HPO_DP[1]
1345 * VPG[8] -> HPO_DP[2]
1346 * VPG[9] -> HPO_DP[3]
1347 */
1348 //Uses offset index 5-8, but actually maps to vpg_inst 6-9
1349 vpg_inst = hpo_dp_inst + 5;
1350
1351 /* Mapping of APG register blocks to HPO DP block instance:
1352 * APG[0] -> HPO_DP[0]
1353 * APG[1] -> HPO_DP[1]
1354 * APG[2] -> HPO_DP[2]
1355 * APG[3] -> HPO_DP[3]
1356 */
1357 apg_inst = hpo_dp_inst;
1358
1359 /* allocate HPO stream encoder and create VPG sub-block */
1360 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1361 vpg = dcn31_vpg_create(ctx, vpg_inst);
1362 apg = dcn31_apg_create(ctx, apg_inst);
1363
1364 if (!hpo_dp_enc31 || !vpg || !apg) {
1365 kfree(hpo_dp_enc31);
1366 kfree(vpg);
1367 kfree(apg);
1368 return NULL;
1369 }
1370
1371 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1372 hpo_dp_inst, eng_id, vpg, apg,
1373 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1374 &hpo_dp_se_shift, &hpo_dp_se_mask);
1375
1376 return &hpo_dp_enc31->base;
1377}
1378
1379static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1380 uint8_t inst,
1381 struct dc_context *ctx)
1382{
1383 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1384
1385 /* allocate HPO link encoder */
1386 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1387
1388 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1389 &hpo_dp_link_enc_regs[inst],
1390 &hpo_dp_le_shift, &hpo_dp_le_mask);
1391
1392 return &hpo_dp_enc31->base;
1393}
1394
1395static struct dce_hwseq *dcn314_hwseq_create(
1396 struct dc_context *ctx)
1397{
1398 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1399
1400 if (hws) {
1401 hws->ctx = ctx;
1402 hws->regs = &hwseq_reg;
1403 hws->shifts = &hwseq_shift;
1404 hws->masks = &hwseq_mask;
1405 }
1406 return hws;
1407}
1408static const struct resource_create_funcs res_create_funcs = {
1409 .read_dce_straps = read_dce_straps,
1410 .create_audio = dcn31_create_audio,
1411 .create_stream_encoder = dcn314_stream_encoder_create,
1412 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1413 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1414 .create_hwseq = dcn314_hwseq_create,
1415};
1416
1417static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
1418{
1419 unsigned int i;
1420
1421 for (i = 0; i < pool->base.stream_enc_count; i++) {
1422 if (pool->base.stream_enc[i] != NULL) {
1423 if (pool->base.stream_enc[i]->vpg != NULL) {
1424 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1425 pool->base.stream_enc[i]->vpg = NULL;
1426 }
1427 if (pool->base.stream_enc[i]->afmt != NULL) {
1428 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1429 pool->base.stream_enc[i]->afmt = NULL;
1430 }
1431 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1432 pool->base.stream_enc[i] = NULL;
1433 }
1434 }
1435
1436 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1437 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1438 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1439 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1440 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1441 }
1442 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1443 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1444 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1445 }
1446 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1447 pool->base.hpo_dp_stream_enc[i] = NULL;
1448 }
1449 }
1450
1451 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1452 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1453 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1454 pool->base.hpo_dp_link_enc[i] = NULL;
1455 }
1456 }
1457
1458 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1459 if (pool->base.dscs[i] != NULL)
1460 dcn20_dsc_destroy(&pool->base.dscs[i]);
1461 }
1462
1463 if (pool->base.mpc != NULL) {
1464 kfree(TO_DCN20_MPC(pool->base.mpc));
1465 pool->base.mpc = NULL;
1466 }
1467 if (pool->base.hubbub != NULL) {
1468 kfree(pool->base.hubbub);
1469 pool->base.hubbub = NULL;
1470 }
1471 for (i = 0; i < pool->base.pipe_count; i++) {
1472 if (pool->base.dpps[i] != NULL)
1473 dcn31_dpp_destroy(&pool->base.dpps[i]);
1474
1475 if (pool->base.ipps[i] != NULL)
1476 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1477
1478 if (pool->base.hubps[i] != NULL) {
1479 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1480 pool->base.hubps[i] = NULL;
1481 }
1482
1483 if (pool->base.irqs != NULL)
1484 dal_irq_service_destroy(&pool->base.irqs);
1485 }
1486
1487 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1488 if (pool->base.engines[i] != NULL)
1489 dce110_engine_destroy(&pool->base.engines[i]);
1490 if (pool->base.hw_i2cs[i] != NULL) {
1491 kfree(pool->base.hw_i2cs[i]);
1492 pool->base.hw_i2cs[i] = NULL;
1493 }
1494 if (pool->base.sw_i2cs[i] != NULL) {
1495 kfree(pool->base.sw_i2cs[i]);
1496 pool->base.sw_i2cs[i] = NULL;
1497 }
1498 }
1499
1500 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1501 if (pool->base.opps[i] != NULL)
1502 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1503 }
1504
1505 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1506 if (pool->base.timing_generators[i] != NULL) {
1507 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1508 pool->base.timing_generators[i] = NULL;
1509 }
1510 }
1511
1512 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1513 if (pool->base.dwbc[i] != NULL) {
1514 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1515 pool->base.dwbc[i] = NULL;
1516 }
1517 if (pool->base.mcif_wb[i] != NULL) {
1518 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1519 pool->base.mcif_wb[i] = NULL;
1520 }
1521 }
1522
1523 for (i = 0; i < pool->base.audio_count; i++) {
1524 if (pool->base.audios[i])
1525 dce_aud_destroy(&pool->base.audios[i]);
1526 }
1527
1528 for (i = 0; i < pool->base.clk_src_count; i++) {
1529 if (pool->base.clock_sources[i] != NULL) {
1530 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1531 pool->base.clock_sources[i] = NULL;
1532 }
1533 }
1534
1535 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1536 if (pool->base.mpc_lut[i] != NULL) {
1537 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1538 pool->base.mpc_lut[i] = NULL;
1539 }
1540 if (pool->base.mpc_shaper[i] != NULL) {
1541 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1542 pool->base.mpc_shaper[i] = NULL;
1543 }
1544 }
1545
1546 if (pool->base.dp_clock_source != NULL) {
1547 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1548 pool->base.dp_clock_source = NULL;
1549 }
1550
1551 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1552 if (pool->base.multiple_abms[i] != NULL)
1553 dce_abm_destroy(&pool->base.multiple_abms[i]);
1554 }
1555
1556 if (pool->base.psr != NULL)
1557 dmub_psr_destroy(&pool->base.psr);
1558
1559 if (pool->base.replay != NULL)
1560 dmub_replay_destroy(&pool->base.replay);
1561
1562 if (pool->base.dccg != NULL)
1563 dcn_dccg_destroy(&pool->base.dccg);
1564}
1565
1566static struct hubp *dcn31_hubp_create(
1567 struct dc_context *ctx,
1568 uint32_t inst)
1569{
1570 struct dcn20_hubp *hubp2 =
1571 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1572
1573 if (!hubp2)
1574 return NULL;
1575
1576 if (hubp31_construct(hubp2, ctx, inst,
1577 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1578 return &hubp2->base;
1579
1580 BREAK_TO_DEBUGGER();
1581 kfree(hubp2);
1582 return NULL;
1583}
1584
1585static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1586{
1587 int i;
1588 uint32_t pipe_count = pool->res_cap->num_dwb;
1589
1590 for (i = 0; i < pipe_count; i++) {
1591 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1592 GFP_KERNEL);
1593
1594 if (!dwbc30) {
1595 dm_error("DC: failed to create dwbc30!\n");
1596 return false;
1597 }
1598
1599 dcn30_dwbc_construct(dwbc30, ctx,
1600 &dwbc30_regs[i],
1601 &dwbc30_shift,
1602 &dwbc30_mask,
1603 i);
1604
1605 pool->dwbc[i] = &dwbc30->base;
1606 }
1607 return true;
1608}
1609
1610static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1611{
1612 int i;
1613 uint32_t pipe_count = pool->res_cap->num_dwb;
1614
1615 for (i = 0; i < pipe_count; i++) {
1616 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1617 GFP_KERNEL);
1618
1619 if (!mcif_wb30) {
1620 dm_error("DC: failed to create mcif_wb30!\n");
1621 return false;
1622 }
1623
1624 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1625 &mcif_wb30_regs[i],
1626 &mcif_wb30_shift,
1627 &mcif_wb30_mask,
1628 i);
1629
1630 pool->mcif_wb[i] = &mcif_wb30->base;
1631 }
1632 return true;
1633}
1634
1635static struct display_stream_compressor *dcn314_dsc_create(
1636 struct dc_context *ctx, uint32_t inst)
1637{
1638 struct dcn20_dsc *dsc =
1639 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1640
1641 if (!dsc) {
1642 BREAK_TO_DEBUGGER();
1643 return NULL;
1644 }
1645
1646 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1647 return &dsc->base;
1648}
1649
1650static void dcn314_destroy_resource_pool(struct resource_pool **pool)
1651{
1652 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool);
1653
1654 dcn314_resource_destruct(dcn314_pool);
1655 kfree(dcn314_pool);
1656 *pool = NULL;
1657}
1658
1659static struct clock_source *dcn31_clock_source_create(
1660 struct dc_context *ctx,
1661 struct dc_bios *bios,
1662 enum clock_source_id id,
1663 const struct dce110_clk_src_regs *regs,
1664 bool dp_clk_src)
1665{
1666 struct dce110_clk_src *clk_src =
1667 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1668
1669 if (!clk_src)
1670 return NULL;
1671
1672 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1673 regs, &cs_shift, &cs_mask)) {
1674 clk_src->base.dp_clk_src = dp_clk_src;
1675 return &clk_src->base;
1676 }
1677
1678 BREAK_TO_DEBUGGER();
1679 kfree(clk_src);
1680 return NULL;
1681}
1682
1683static int dcn314_populate_dml_pipes_from_context(
1684 struct dc *dc, struct dc_state *context,
1685 display_e2e_pipe_params_st *pipes,
1686 bool fast_validate)
1687{
1688 int pipe_cnt;
1689
1690 DC_FP_START();
1691 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate);
1692 DC_FP_END();
1693
1694 return pipe_cnt;
1695}
1696
1697static struct dc_cap_funcs cap_funcs = {
1698 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1699};
1700
1701static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1702{
1703 DC_FP_START();
1704 dcn314_update_bw_bounding_box_fpu(dc, bw_params);
1705 DC_FP_END();
1706}
1707
1708static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config)
1709{
1710 *panel_config = panel_config_defaults;
1711}
1712
1713static bool filter_modes_for_single_channel_workaround(struct dc *dc,
1714 struct dc_state *context)
1715{
1716 // Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR
1717 if (dc->clk_mgr->bw_params->vram_type == 34 &&
1718 dc->clk_mgr->bw_params->num_channels < 2 &&
1719 context->stream_count > 1) {
1720 int total_phy_pix_clk = 0;
1721
1722 for (int i = 0; i < context->stream_count; i++)
1723 if (context->res_ctx.pipe_ctx[i].stream)
1724 total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
1725
1726 if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps
1727 return true;
1728 }
1729 return false;
1730}
1731
1732bool dcn314_validate_bandwidth(struct dc *dc,
1733 struct dc_state *context,
1734 bool fast_validate)
1735{
1736 bool out = false;
1737
1738 BW_VAL_TRACE_SETUP();
1739
1740 int vlevel = 0;
1741 int pipe_cnt = 0;
1742 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1743 DC_LOGGER_INIT(dc->ctx->logger);
1744
1745 BW_VAL_TRACE_COUNT();
1746
1747 if (filter_modes_for_single_channel_workaround(dc, context))
1748 goto validate_fail;
1749
1750 DC_FP_START();
1751 // do not support self refresh only
1752 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);
1753 DC_FP_END();
1754
1755 // Disable fast_validate to set min dcfclk in calculate_wm_and_dlg
1756 if (pipe_cnt == 0)
1757 fast_validate = false;
1758
1759 if (!out)
1760 goto validate_fail;
1761
1762 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1763
1764 if (fast_validate) {
1765 BW_VAL_TRACE_SKIP(fast);
1766 goto validate_out;
1767 }
1768 if (dc->res_pool->funcs->calculate_wm_and_dlg)
1769 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1770
1771 BW_VAL_TRACE_END_WATERMARKS();
1772
1773 goto validate_out;
1774
1775validate_fail:
1776 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1777 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1778
1779 BW_VAL_TRACE_SKIP(fail);
1780 out = false;
1781
1782validate_out:
1783 kfree(pipes);
1784
1785 BW_VAL_TRACE_FINISH();
1786
1787 return out;
1788}
1789
1790static struct resource_funcs dcn314_res_pool_funcs = {
1791 .destroy = dcn314_destroy_resource_pool,
1792 .link_enc_create = dcn31_link_encoder_create,
1793 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1794 .link_encs_assign = link_enc_cfg_link_encs_assign,
1795 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1796 .panel_cntl_create = dcn31_panel_cntl_create,
1797 .validate_bandwidth = dcn314_validate_bandwidth,
1798 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1799 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1800 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context,
1801 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1802 .release_pipe = dcn20_release_pipe,
1803 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1804 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1805 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1806 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1807 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1808 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1809 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1810 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1811 .update_bw_bounding_box = dcn314_update_bw_bounding_box,
1812 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1813 .get_panel_config_defaults = dcn314_get_panel_config_defaults,
1814 .get_preferred_eng_id_dpia = dcn314_get_preferred_eng_id_dpia,
1815};
1816
1817static struct clock_source *dcn30_clock_source_create(
1818 struct dc_context *ctx,
1819 struct dc_bios *bios,
1820 enum clock_source_id id,
1821 const struct dce110_clk_src_regs *regs,
1822 bool dp_clk_src)
1823{
1824 struct dce110_clk_src *clk_src =
1825 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1826
1827 if (!clk_src)
1828 return NULL;
1829
1830 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1831 regs, &cs_shift, &cs_mask)) {
1832 clk_src->base.dp_clk_src = dp_clk_src;
1833 return &clk_src->base;
1834 }
1835
1836 BREAK_TO_DEBUGGER();
1837 kfree(clk_src);
1838 return NULL;
1839}
1840
1841static bool dcn314_resource_construct(
1842 uint8_t num_virtual_links,
1843 struct dc *dc,
1844 struct dcn314_resource_pool *pool)
1845{
1846 int i;
1847 struct dc_context *ctx = dc->ctx;
1848 struct irq_service_init_data init_data;
1849
1850 ctx->dc_bios->regs = &bios_regs;
1851
1852 pool->base.res_cap = &res_cap_dcn314;
1853 pool->base.funcs = &dcn314_res_pool_funcs;
1854
1855 /*************************************************
1856 * Resource + asic cap harcoding *
1857 *************************************************/
1858 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1859 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1860 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1861 dc->caps.max_downscale_ratio = 400;
1862 dc->caps.i2c_speed_in_khz = 100;
1863 dc->caps.i2c_speed_in_khz_hdcp = 100;
1864 dc->caps.max_cursor_size = 256;
1865 dc->caps.min_horizontal_blanking_period = 80;
1866 dc->caps.dmdata_alloc_size = 2048;
1867 dc->caps.max_slave_planes = 2;
1868 dc->caps.max_slave_yuv_planes = 2;
1869 dc->caps.max_slave_rgb_planes = 2;
1870 dc->caps.post_blend_color_processing = true;
1871 dc->caps.force_dp_tps4_for_cp2520 = true;
1872 if (dc->config.forceHBR2CP2520)
1873 dc->caps.force_dp_tps4_for_cp2520 = false;
1874 dc->caps.dp_hpo = true;
1875 dc->caps.dp_hdmi21_pcon_support = true;
1876 dc->caps.edp_dsc_support = true;
1877 dc->caps.extended_aux_timeout_support = true;
1878 dc->caps.dmcub_support = true;
1879 dc->caps.is_apu = true;
1880 dc->caps.seamless_odm = true;
1881
1882 dc->caps.zstate_support = true;
1883
1884 /* Color pipeline capabilities */
1885 dc->caps.color.dpp.dcn_arch = 1;
1886 dc->caps.color.dpp.input_lut_shared = 0;
1887 dc->caps.color.dpp.icsc = 1;
1888 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1889 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1890 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1891 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1892 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1893 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1894 dc->caps.color.dpp.post_csc = 1;
1895 dc->caps.color.dpp.gamma_corr = 1;
1896 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1897
1898 dc->caps.color.dpp.hw_3d_lut = 1;
1899 dc->caps.color.dpp.ogam_ram = 1;
1900 // no OGAM ROM on DCN301
1901 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1902 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1903 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1904 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1905 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1906 dc->caps.color.dpp.ocsc = 0;
1907
1908 dc->caps.color.mpc.gamut_remap = 1;
1909 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1910 dc->caps.color.mpc.ogam_ram = 1;
1911 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1912 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1913 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1914 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1915 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1916 dc->caps.color.mpc.ocsc = 1;
1917
1918 dc->caps.max_disp_clock_khz_at_vmin = 650000;
1919
1920 /* Use pipe context based otg sync logic */
1921 dc->config.use_pipe_ctx_sync_logic = true;
1922
1923 /* read VBIOS LTTPR caps */
1924 {
1925 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1926 enum bp_result bp_query_result;
1927 uint8_t is_vbios_lttpr_enable = 0;
1928
1929 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1930 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1931 }
1932
1933 /* interop bit is implicit */
1934 {
1935 dc->caps.vbios_lttpr_aware = true;
1936 }
1937 }
1938
1939 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1940 dc->debug = debug_defaults_drv;
1941 else
1942 dc->debug = debug_defaults_diags;
1943
1944 /* Disable pipe power gating */
1945 dc->debug.disable_dpp_power_gate = true;
1946 dc->debug.disable_hubp_power_gate = true;
1947
1948 /* Disable root clock optimization */
1949 dc->debug.root_clock_optimization.u32All = 0;
1950
1951 // Init the vm_helper
1952 if (dc->vm_helper)
1953 vm_helper_init(dc->vm_helper, 16);
1954
1955 /*************************************************
1956 * Create resources *
1957 *************************************************/
1958
1959 /* Clock Sources for Pixel Clock*/
1960 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1961 dcn30_clock_source_create(ctx, ctx->dc_bios,
1962 CLOCK_SOURCE_COMBO_PHY_PLL0,
1963 &clk_src_regs[0], false);
1964 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1965 dcn30_clock_source_create(ctx, ctx->dc_bios,
1966 CLOCK_SOURCE_COMBO_PHY_PLL1,
1967 &clk_src_regs[1], false);
1968 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1969 dcn30_clock_source_create(ctx, ctx->dc_bios,
1970 CLOCK_SOURCE_COMBO_PHY_PLL2,
1971 &clk_src_regs[2], false);
1972 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1973 dcn30_clock_source_create(ctx, ctx->dc_bios,
1974 CLOCK_SOURCE_COMBO_PHY_PLL3,
1975 &clk_src_regs[3], false);
1976 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1977 dcn30_clock_source_create(ctx, ctx->dc_bios,
1978 CLOCK_SOURCE_COMBO_PHY_PLL4,
1979 &clk_src_regs[4], false);
1980
1981 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1982
1983 /* todo: not reuse phy_pll registers */
1984 pool->base.dp_clock_source =
1985 dcn31_clock_source_create(ctx, ctx->dc_bios,
1986 CLOCK_SOURCE_ID_DP_DTO,
1987 &clk_src_regs[0], true);
1988
1989 for (i = 0; i < pool->base.clk_src_count; i++) {
1990 if (pool->base.clock_sources[i] == NULL) {
1991 dm_error("DC: failed to create clock sources!\n");
1992 BREAK_TO_DEBUGGER();
1993 goto create_fail;
1994 }
1995 }
1996
1997 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1998 if (pool->base.dccg == NULL) {
1999 dm_error("DC: failed to create dccg!\n");
2000 BREAK_TO_DEBUGGER();
2001 goto create_fail;
2002 }
2003
2004 init_data.ctx = dc->ctx;
2005 pool->base.irqs = dal_irq_service_dcn314_create(&init_data);
2006 if (!pool->base.irqs)
2007 goto create_fail;
2008
2009 /* HUBBUB */
2010 pool->base.hubbub = dcn31_hubbub_create(ctx);
2011 if (pool->base.hubbub == NULL) {
2012 BREAK_TO_DEBUGGER();
2013 dm_error("DC: failed to create hubbub!\n");
2014 goto create_fail;
2015 }
2016
2017 /* HUBPs, DPPs, OPPs and TGs */
2018 for (i = 0; i < pool->base.pipe_count; i++) {
2019 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2020 if (pool->base.hubps[i] == NULL) {
2021 BREAK_TO_DEBUGGER();
2022 dm_error(
2023 "DC: failed to create hubps!\n");
2024 goto create_fail;
2025 }
2026
2027 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2028 if (pool->base.dpps[i] == NULL) {
2029 BREAK_TO_DEBUGGER();
2030 dm_error(
2031 "DC: failed to create dpps!\n");
2032 goto create_fail;
2033 }
2034 }
2035
2036 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2037 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2038 if (pool->base.opps[i] == NULL) {
2039 BREAK_TO_DEBUGGER();
2040 dm_error(
2041 "DC: failed to create output pixel processor!\n");
2042 goto create_fail;
2043 }
2044 }
2045
2046 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2047 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2048 ctx, i);
2049 if (pool->base.timing_generators[i] == NULL) {
2050 BREAK_TO_DEBUGGER();
2051 dm_error("DC: failed to create tg!\n");
2052 goto create_fail;
2053 }
2054 }
2055 pool->base.timing_generator_count = i;
2056
2057 /* PSR */
2058 pool->base.psr = dmub_psr_create(ctx);
2059 if (pool->base.psr == NULL) {
2060 dm_error("DC: failed to create psr obj!\n");
2061 BREAK_TO_DEBUGGER();
2062 goto create_fail;
2063 }
2064
2065 /* Replay */
2066 pool->base.replay = dmub_replay_create(ctx);
2067 if (pool->base.replay == NULL) {
2068 dm_error("DC: failed to create replay obj!\n");
2069 BREAK_TO_DEBUGGER();
2070 goto create_fail;
2071 }
2072
2073 /* ABM */
2074 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2075 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2076 &abm_regs[i],
2077 &abm_shift,
2078 &abm_mask);
2079 if (pool->base.multiple_abms[i] == NULL) {
2080 dm_error("DC: failed to create abm for pipe %d!\n", i);
2081 BREAK_TO_DEBUGGER();
2082 goto create_fail;
2083 }
2084 }
2085
2086 /* MPC and DSC */
2087 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2088 if (pool->base.mpc == NULL) {
2089 BREAK_TO_DEBUGGER();
2090 dm_error("DC: failed to create mpc!\n");
2091 goto create_fail;
2092 }
2093
2094 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2095 pool->base.dscs[i] = dcn314_dsc_create(ctx, i);
2096 if (pool->base.dscs[i] == NULL) {
2097 BREAK_TO_DEBUGGER();
2098 dm_error("DC: failed to create display stream compressor %d!\n", i);
2099 goto create_fail;
2100 }
2101 }
2102
2103 /* DWB and MMHUBBUB */
2104 if (!dcn31_dwbc_create(ctx, &pool->base)) {
2105 BREAK_TO_DEBUGGER();
2106 dm_error("DC: failed to create dwbc!\n");
2107 goto create_fail;
2108 }
2109
2110 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2111 BREAK_TO_DEBUGGER();
2112 dm_error("DC: failed to create mcif_wb!\n");
2113 goto create_fail;
2114 }
2115
2116 /* AUX and I2C */
2117 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2118 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2119 if (pool->base.engines[i] == NULL) {
2120 BREAK_TO_DEBUGGER();
2121 dm_error(
2122 "DC:failed to create aux engine!!\n");
2123 goto create_fail;
2124 }
2125 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2126 if (pool->base.hw_i2cs[i] == NULL) {
2127 BREAK_TO_DEBUGGER();
2128 dm_error(
2129 "DC:failed to create hw i2c!!\n");
2130 goto create_fail;
2131 }
2132 pool->base.sw_i2cs[i] = NULL;
2133 }
2134
2135 /* DCN314 has 4 DPIA */
2136 pool->base.usb4_dpia_count = 4;
2137
2138 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2139 if (!resource_construct(num_virtual_links, dc, &pool->base,
2140 &res_create_funcs))
2141 goto create_fail;
2142
2143 /* HW Sequencer and Plane caps */
2144 dcn314_hw_sequencer_construct(dc);
2145
2146 dc->caps.max_planes = pool->base.pipe_count;
2147
2148 for (i = 0; i < dc->caps.max_planes; ++i)
2149 dc->caps.planes[i] = plane_cap;
2150
2151 dc->cap_funcs = cap_funcs;
2152
2153 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp;
2154
2155 return true;
2156
2157create_fail:
2158
2159 dcn314_resource_destruct(pool);
2160
2161 return false;
2162}
2163
2164struct resource_pool *dcn314_create_resource_pool(
2165 const struct dc_init_data *init_data,
2166 struct dc *dc)
2167{
2168 struct dcn314_resource_pool *pool =
2169 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL);
2170
2171 if (!pool)
2172 return NULL;
2173
2174 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))
2175 return &pool->base;
2176
2177 BREAK_TO_DEBUGGER();
2178 kfree(pool);
2179 return NULL;
2180}