1/*
 2 * Copyright 2017 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "soc_bounding_box.h"
26#include "display_mode_lib.h"
27#include "dc_features.h"
28
29#include "dml_inline_defs.h"
30
31/*
32 * NOTE:
33 *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
34 *
35 * It doesn't adhere to Linux kernel style and sometimes will do things in odd
36 * ways. Unless there is something clearly wrong with it the code should
37 * remain as-is as it provides us with a guarantee from HW that it is correct.
38 */
39
40void dml_socbb_set_latencies(soc_bounding_box_st *to_box, soc_bounding_box_st *from_box)
41{
42	to_box->dram_clock_change_latency_us = from_box->dram_clock_change_latency_us;
43	to_box->sr_exit_time_us = from_box->sr_exit_time_us;
44	to_box->sr_enter_plus_exit_time_us = from_box->sr_enter_plus_exit_time_us;
45	to_box->urgent_latency_us = from_box->urgent_latency_us;
46	to_box->writeback_latency_us = from_box->writeback_latency_us;
47}
48
49voltage_scaling_st dml_socbb_voltage_scaling(
50		const soc_bounding_box_st *soc,
51		enum voltage_state voltage)
52{
53	const voltage_scaling_st *voltage_state;
54	const voltage_scaling_st * const voltage_end = soc->clock_limits + DC__VOLTAGE_STATES;
55
56	for (voltage_state = soc->clock_limits;
57			voltage_state < voltage_end && voltage_state->state != voltage;
58			voltage_state++) {
59	}
60
61	if (voltage_state < voltage_end)
62		return *voltage_state;
63	return soc->clock_limits[DC__VOLTAGE_STATES - 1];
64}
65
66double dml_socbb_return_bw_mhz(soc_bounding_box_st *box, enum voltage_state voltage)
67{
68	double return_bw;
69
70	voltage_scaling_st state = dml_socbb_voltage_scaling(box, voltage);
71
72	return_bw = dml_min((double) box->return_bus_width_bytes * state.dcfclk_mhz,
73			state.dram_bw_per_chan_gbps * 1000.0 * (double) box->num_chans
74					* box->ideal_dram_bw_after_urgent_percent / 100.0);
75
76	return_bw = dml_min((double) box->return_bus_width_bytes * state.fabricclk_mhz, return_bw);
77
78	return return_bw;
79}