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1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25#include <linux/ratelimit.h>
26#include <linux/printk.h>
27#include <linux/slab.h>
28#include <linux/list.h>
29#include <linux/types.h>
30#include <linux/bitops.h>
31#include <linux/sched.h>
32#include "kfd_priv.h"
33#include "kfd_device_queue_manager.h"
34#include "kfd_mqd_manager.h"
35#include "cik_regs.h"
36#include "kfd_kernel_queue.h"
37#include "amdgpu_amdkfd.h"
38#include "mes_api_def.h"
39#include "kfd_debug.h"
40
41/* Size of the per-pipe EOP queue */
42#define CIK_HPD_EOP_BYTES_LOG2 11
43#define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
44
45static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
46 u32 pasid, unsigned int vmid);
47
48static int execute_queues_cpsch(struct device_queue_manager *dqm,
49 enum kfd_unmap_queues_filter filter,
50 uint32_t filter_param,
51 uint32_t grace_period);
52static int unmap_queues_cpsch(struct device_queue_manager *dqm,
53 enum kfd_unmap_queues_filter filter,
54 uint32_t filter_param,
55 uint32_t grace_period,
56 bool reset);
57
58static int map_queues_cpsch(struct device_queue_manager *dqm);
59
60static void deallocate_sdma_queue(struct device_queue_manager *dqm,
61 struct queue *q);
62
63static inline void deallocate_hqd(struct device_queue_manager *dqm,
64 struct queue *q);
65static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q);
66static int allocate_sdma_queue(struct device_queue_manager *dqm,
67 struct queue *q, const uint32_t *restore_sdma_id);
68static void kfd_process_hw_exception(struct work_struct *work);
69
70static inline
71enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
72{
73 if (type == KFD_QUEUE_TYPE_SDMA || type == KFD_QUEUE_TYPE_SDMA_XGMI)
74 return KFD_MQD_TYPE_SDMA;
75 return KFD_MQD_TYPE_CP;
76}
77
78static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
79{
80 int i;
81 int pipe_offset = (mec * dqm->dev->kfd->shared_resources.num_pipe_per_mec
82 + pipe) * dqm->dev->kfd->shared_resources.num_queue_per_pipe;
83
84 /* queue is available for KFD usage if bit is 1 */
85 for (i = 0; i < dqm->dev->kfd->shared_resources.num_queue_per_pipe; ++i)
86 if (test_bit(pipe_offset + i,
87 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
88 return true;
89 return false;
90}
91
92unsigned int get_cp_queues_num(struct device_queue_manager *dqm)
93{
94 return bitmap_weight(dqm->dev->kfd->shared_resources.cp_queue_bitmap,
95 AMDGPU_MAX_QUEUES);
96}
97
98unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
99{
100 return dqm->dev->kfd->shared_resources.num_queue_per_pipe;
101}
102
103unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
104{
105 return dqm->dev->kfd->shared_resources.num_pipe_per_mec;
106}
107
108static unsigned int get_num_all_sdma_engines(struct device_queue_manager *dqm)
109{
110 return kfd_get_num_sdma_engines(dqm->dev) +
111 kfd_get_num_xgmi_sdma_engines(dqm->dev);
112}
113
114unsigned int get_num_sdma_queues(struct device_queue_manager *dqm)
115{
116 return kfd_get_num_sdma_engines(dqm->dev) *
117 dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
118}
119
120unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm)
121{
122 return kfd_get_num_xgmi_sdma_engines(dqm->dev) *
123 dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
124}
125
126static void init_sdma_bitmaps(struct device_queue_manager *dqm)
127{
128 bitmap_zero(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES);
129 bitmap_set(dqm->sdma_bitmap, 0, get_num_sdma_queues(dqm));
130
131 bitmap_zero(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES);
132 bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm));
133
134 /* Mask out the reserved queues */
135 bitmap_andnot(dqm->sdma_bitmap, dqm->sdma_bitmap,
136 dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap,
137 KFD_MAX_SDMA_QUEUES);
138}
139
140void program_sh_mem_settings(struct device_queue_manager *dqm,
141 struct qcm_process_device *qpd)
142{
143 uint32_t xcc_mask = dqm->dev->xcc_mask;
144 int xcc_id;
145
146 for_each_inst(xcc_id, xcc_mask)
147 dqm->dev->kfd2kgd->program_sh_mem_settings(
148 dqm->dev->adev, qpd->vmid, qpd->sh_mem_config,
149 qpd->sh_mem_ape1_base, qpd->sh_mem_ape1_limit,
150 qpd->sh_mem_bases, xcc_id);
151}
152
153static void kfd_hws_hang(struct device_queue_manager *dqm)
154{
155 /*
156 * Issue a GPU reset if HWS is unresponsive
157 */
158 dqm->is_hws_hang = true;
159
160 /* It's possible we're detecting a HWS hang in the
161 * middle of a GPU reset. No need to schedule another
162 * reset in this case.
163 */
164 if (!dqm->is_resetting)
165 schedule_work(&dqm->hw_exception_work);
166}
167
168static int convert_to_mes_queue_type(int queue_type)
169{
170 int mes_queue_type;
171
172 switch (queue_type) {
173 case KFD_QUEUE_TYPE_COMPUTE:
174 mes_queue_type = MES_QUEUE_TYPE_COMPUTE;
175 break;
176 case KFD_QUEUE_TYPE_SDMA:
177 mes_queue_type = MES_QUEUE_TYPE_SDMA;
178 break;
179 default:
180 WARN(1, "Invalid queue type %d", queue_type);
181 mes_queue_type = -EINVAL;
182 break;
183 }
184
185 return mes_queue_type;
186}
187
188static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
189 struct qcm_process_device *qpd)
190{
191 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev;
192 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
193 struct mes_add_queue_input queue_input;
194 int r, queue_type;
195 uint64_t wptr_addr_off;
196
197 if (dqm->is_hws_hang)
198 return -EIO;
199
200 memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input));
201 queue_input.process_id = qpd->pqm->process->pasid;
202 queue_input.page_table_base_addr = qpd->page_table_base;
203 queue_input.process_va_start = 0;
204 queue_input.process_va_end = adev->vm_manager.max_pfn - 1;
205 /* MES unit for quantum is 100ns */
206 queue_input.process_quantum = KFD_MES_PROCESS_QUANTUM; /* Equivalent to 10ms. */
207 queue_input.process_context_addr = pdd->proc_ctx_gpu_addr;
208 queue_input.gang_quantum = KFD_MES_GANG_QUANTUM; /* Equivalent to 1ms */
209 queue_input.gang_context_addr = q->gang_ctx_gpu_addr;
210 queue_input.inprocess_gang_priority = q->properties.priority;
211 queue_input.gang_global_priority_level =
212 AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
213 queue_input.doorbell_offset = q->properties.doorbell_off;
214 queue_input.mqd_addr = q->gart_mqd_addr;
215 queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
216
217 if (q->wptr_bo) {
218 wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1);
219 queue_input.wptr_mc_addr = amdgpu_bo_gpu_offset(q->wptr_bo) + wptr_addr_off;
220 }
221
222 queue_input.is_kfd_process = 1;
223 queue_input.is_aql_queue = (q->properties.format == KFD_QUEUE_FORMAT_AQL);
224 queue_input.queue_size = q->properties.queue_size >> 2;
225
226 queue_input.paging = false;
227 queue_input.tba_addr = qpd->tba_addr;
228 queue_input.tma_addr = qpd->tma_addr;
229 queue_input.trap_en = !kfd_dbg_has_cwsr_workaround(q->device);
230 queue_input.skip_process_ctx_clear =
231 qpd->pqm->process->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED &&
232 (qpd->pqm->process->debug_trap_enabled ||
233 kfd_dbg_has_ttmps_always_setup(q->device));
234
235 queue_type = convert_to_mes_queue_type(q->properties.type);
236 if (queue_type < 0) {
237 dev_err(adev->dev, "Queue type not supported with MES, queue:%d\n",
238 q->properties.type);
239 return -EINVAL;
240 }
241 queue_input.queue_type = (uint32_t)queue_type;
242
243 queue_input.exclusively_scheduled = q->properties.is_gws;
244
245 amdgpu_mes_lock(&adev->mes);
246 r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);
247 amdgpu_mes_unlock(&adev->mes);
248 if (r) {
249 dev_err(adev->dev, "failed to add hardware queue to MES, doorbell=0x%x\n",
250 q->properties.doorbell_off);
251 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n");
252 kfd_hws_hang(dqm);
253 }
254
255 return r;
256}
257
258static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q,
259 struct qcm_process_device *qpd)
260{
261 struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev;
262 int r;
263 struct mes_remove_queue_input queue_input;
264
265 if (dqm->is_hws_hang)
266 return -EIO;
267
268 memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input));
269 queue_input.doorbell_offset = q->properties.doorbell_off;
270 queue_input.gang_context_addr = q->gang_ctx_gpu_addr;
271
272 amdgpu_mes_lock(&adev->mes);
273 r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);
274 amdgpu_mes_unlock(&adev->mes);
275
276 if (r) {
277 dev_err(adev->dev, "failed to remove hardware queue from MES, doorbell=0x%x\n",
278 q->properties.doorbell_off);
279 dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n");
280 kfd_hws_hang(dqm);
281 }
282
283 return r;
284}
285
286static int remove_all_queues_mes(struct device_queue_manager *dqm)
287{
288 struct device_process_node *cur;
289 struct device *dev = dqm->dev->adev->dev;
290 struct qcm_process_device *qpd;
291 struct queue *q;
292 int retval = 0;
293
294 list_for_each_entry(cur, &dqm->queues, list) {
295 qpd = cur->qpd;
296 list_for_each_entry(q, &qpd->queues_list, list) {
297 if (q->properties.is_active) {
298 retval = remove_queue_mes(dqm, q, qpd);
299 if (retval) {
300 dev_err(dev, "%s: Failed to remove queue %d for dev %d",
301 __func__,
302 q->properties.queue_id,
303 dqm->dev->id);
304 return retval;
305 }
306 }
307 }
308 }
309
310 return retval;
311}
312
313static void increment_queue_count(struct device_queue_manager *dqm,
314 struct qcm_process_device *qpd,
315 struct queue *q)
316{
317 dqm->active_queue_count++;
318 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
319 q->properties.type == KFD_QUEUE_TYPE_DIQ)
320 dqm->active_cp_queue_count++;
321
322 if (q->properties.is_gws) {
323 dqm->gws_queue_count++;
324 qpd->mapped_gws_queue = true;
325 }
326}
327
328static void decrement_queue_count(struct device_queue_manager *dqm,
329 struct qcm_process_device *qpd,
330 struct queue *q)
331{
332 dqm->active_queue_count--;
333 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
334 q->properties.type == KFD_QUEUE_TYPE_DIQ)
335 dqm->active_cp_queue_count--;
336
337 if (q->properties.is_gws) {
338 dqm->gws_queue_count--;
339 qpd->mapped_gws_queue = false;
340 }
341}
342
343/*
344 * Allocate a doorbell ID to this queue.
345 * If doorbell_id is passed in, make sure requested ID is valid then allocate it.
346 */
347static int allocate_doorbell(struct qcm_process_device *qpd,
348 struct queue *q,
349 uint32_t const *restore_id)
350{
351 struct kfd_node *dev = qpd->dqm->dev;
352
353 if (!KFD_IS_SOC15(dev)) {
354 /* On pre-SOC15 chips we need to use the queue ID to
355 * preserve the user mode ABI.
356 */
357
358 if (restore_id && *restore_id != q->properties.queue_id)
359 return -EINVAL;
360
361 q->doorbell_id = q->properties.queue_id;
362 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
363 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
364 /* For SDMA queues on SOC15 with 8-byte doorbell, use static
365 * doorbell assignments based on the engine and queue id.
366 * The doobell index distance between RLC (2*i) and (2*i+1)
367 * for a SDMA engine is 512.
368 */
369
370 uint32_t *idx_offset = dev->kfd->shared_resources.sdma_doorbell_idx;
371
372 /*
373 * q->properties.sdma_engine_id corresponds to the virtual
374 * sdma engine number. However, for doorbell allocation,
375 * we need the physical sdma engine id in order to get the
376 * correct doorbell offset.
377 */
378 uint32_t valid_id = idx_offset[qpd->dqm->dev->node_id *
379 get_num_all_sdma_engines(qpd->dqm) +
380 q->properties.sdma_engine_id]
381 + (q->properties.sdma_queue_id & 1)
382 * KFD_QUEUE_DOORBELL_MIRROR_OFFSET
383 + (q->properties.sdma_queue_id >> 1);
384
385 if (restore_id && *restore_id != valid_id)
386 return -EINVAL;
387 q->doorbell_id = valid_id;
388 } else {
389 /* For CP queues on SOC15 */
390 if (restore_id) {
391 /* make sure that ID is free */
392 if (__test_and_set_bit(*restore_id, qpd->doorbell_bitmap))
393 return -EINVAL;
394
395 q->doorbell_id = *restore_id;
396 } else {
397 /* or reserve a free doorbell ID */
398 unsigned int found;
399
400 found = find_first_zero_bit(qpd->doorbell_bitmap,
401 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
402 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
403 pr_debug("No doorbells available");
404 return -EBUSY;
405 }
406 set_bit(found, qpd->doorbell_bitmap);
407 q->doorbell_id = found;
408 }
409 }
410
411 q->properties.doorbell_off = amdgpu_doorbell_index_on_bar(dev->adev,
412 qpd->proc_doorbells,
413 q->doorbell_id,
414 dev->kfd->device_info.doorbell_size);
415 return 0;
416}
417
418static void deallocate_doorbell(struct qcm_process_device *qpd,
419 struct queue *q)
420{
421 unsigned int old;
422 struct kfd_node *dev = qpd->dqm->dev;
423
424 if (!KFD_IS_SOC15(dev) ||
425 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
426 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
427 return;
428
429 old = test_and_clear_bit(q->doorbell_id, qpd->doorbell_bitmap);
430 WARN_ON(!old);
431}
432
433static void program_trap_handler_settings(struct device_queue_manager *dqm,
434 struct qcm_process_device *qpd)
435{
436 uint32_t xcc_mask = dqm->dev->xcc_mask;
437 int xcc_id;
438
439 if (dqm->dev->kfd2kgd->program_trap_handler_settings)
440 for_each_inst(xcc_id, xcc_mask)
441 dqm->dev->kfd2kgd->program_trap_handler_settings(
442 dqm->dev->adev, qpd->vmid, qpd->tba_addr,
443 qpd->tma_addr, xcc_id);
444}
445
446static int allocate_vmid(struct device_queue_manager *dqm,
447 struct qcm_process_device *qpd,
448 struct queue *q)
449{
450 struct device *dev = dqm->dev->adev->dev;
451 int allocated_vmid = -1, i;
452
453 for (i = dqm->dev->vm_info.first_vmid_kfd;
454 i <= dqm->dev->vm_info.last_vmid_kfd; i++) {
455 if (!dqm->vmid_pasid[i]) {
456 allocated_vmid = i;
457 break;
458 }
459 }
460
461 if (allocated_vmid < 0) {
462 dev_err(dev, "no more vmid to allocate\n");
463 return -ENOSPC;
464 }
465
466 pr_debug("vmid allocated: %d\n", allocated_vmid);
467
468 dqm->vmid_pasid[allocated_vmid] = q->process->pasid;
469
470 set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid);
471
472 qpd->vmid = allocated_vmid;
473 q->properties.vmid = allocated_vmid;
474
475 program_sh_mem_settings(dqm, qpd);
476
477 if (KFD_IS_SOC15(dqm->dev) && dqm->dev->kfd->cwsr_enabled)
478 program_trap_handler_settings(dqm, qpd);
479
480 /* qpd->page_table_base is set earlier when register_process()
481 * is called, i.e. when the first queue is created.
482 */
483 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->adev,
484 qpd->vmid,
485 qpd->page_table_base);
486 /* invalidate the VM context after pasid and vmid mapping is set up */
487 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
488
489 if (dqm->dev->kfd2kgd->set_scratch_backing_va)
490 dqm->dev->kfd2kgd->set_scratch_backing_va(dqm->dev->adev,
491 qpd->sh_hidden_private_base, qpd->vmid);
492
493 return 0;
494}
495
496static int flush_texture_cache_nocpsch(struct kfd_node *kdev,
497 struct qcm_process_device *qpd)
498{
499 const struct packet_manager_funcs *pmf = qpd->dqm->packet_mgr.pmf;
500 int ret;
501
502 if (!qpd->ib_kaddr)
503 return -ENOMEM;
504
505 ret = pmf->release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
506 if (ret)
507 return ret;
508
509 return amdgpu_amdkfd_submit_ib(kdev->adev, KGD_ENGINE_MEC1, qpd->vmid,
510 qpd->ib_base, (uint32_t *)qpd->ib_kaddr,
511 pmf->release_mem_size / sizeof(uint32_t));
512}
513
514static void deallocate_vmid(struct device_queue_manager *dqm,
515 struct qcm_process_device *qpd,
516 struct queue *q)
517{
518 struct device *dev = dqm->dev->adev->dev;
519
520 /* On GFX v7, CP doesn't flush TC at dequeue */
521 if (q->device->adev->asic_type == CHIP_HAWAII)
522 if (flush_texture_cache_nocpsch(q->device, qpd))
523 dev_err(dev, "Failed to flush TC\n");
524
525 kfd_flush_tlb(qpd_to_pdd(qpd), TLB_FLUSH_LEGACY);
526
527 /* Release the vmid mapping */
528 set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
529 dqm->vmid_pasid[qpd->vmid] = 0;
530
531 qpd->vmid = 0;
532 q->properties.vmid = 0;
533}
534
535static int create_queue_nocpsch(struct device_queue_manager *dqm,
536 struct queue *q,
537 struct qcm_process_device *qpd,
538 const struct kfd_criu_queue_priv_data *qd,
539 const void *restore_mqd, const void *restore_ctl_stack)
540{
541 struct mqd_manager *mqd_mgr;
542 int retval;
543
544 dqm_lock(dqm);
545
546 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
547 pr_warn("Can't create new usermode queue because %d queues were already created\n",
548 dqm->total_queue_count);
549 retval = -EPERM;
550 goto out_unlock;
551 }
552
553 if (list_empty(&qpd->queues_list)) {
554 retval = allocate_vmid(dqm, qpd, q);
555 if (retval)
556 goto out_unlock;
557 }
558 q->properties.vmid = qpd->vmid;
559 /*
560 * Eviction state logic: mark all queues as evicted, even ones
561 * not currently active. Restoring inactive queues later only
562 * updates the is_evicted flag but is a no-op otherwise.
563 */
564 q->properties.is_evicted = !!qpd->evicted;
565
566 q->properties.tba_addr = qpd->tba_addr;
567 q->properties.tma_addr = qpd->tma_addr;
568
569 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
570 q->properties.type)];
571 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
572 retval = allocate_hqd(dqm, q);
573 if (retval)
574 goto deallocate_vmid;
575 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
576 q->pipe, q->queue);
577 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
578 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
579 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL);
580 if (retval)
581 goto deallocate_vmid;
582 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
583 }
584
585 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL);
586 if (retval)
587 goto out_deallocate_hqd;
588
589 /* Temporarily release dqm lock to avoid a circular lock dependency */
590 dqm_unlock(dqm);
591 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
592 dqm_lock(dqm);
593
594 if (!q->mqd_mem_obj) {
595 retval = -ENOMEM;
596 goto out_deallocate_doorbell;
597 }
598
599 if (qd)
600 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr,
601 &q->properties, restore_mqd, restore_ctl_stack,
602 qd->ctl_stack_size);
603 else
604 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
605 &q->gart_mqd_addr, &q->properties);
606
607 if (q->properties.is_active) {
608 if (!dqm->sched_running) {
609 WARN_ONCE(1, "Load non-HWS mqd while stopped\n");
610 goto add_queue_to_list;
611 }
612
613 if (WARN(q->process->mm != current->mm,
614 "should only run in user thread"))
615 retval = -EFAULT;
616 else
617 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
618 q->queue, &q->properties, current->mm);
619 if (retval)
620 goto out_free_mqd;
621 }
622
623add_queue_to_list:
624 list_add(&q->list, &qpd->queues_list);
625 qpd->queue_count++;
626 if (q->properties.is_active)
627 increment_queue_count(dqm, qpd, q);
628
629 /*
630 * Unconditionally increment this counter, regardless of the queue's
631 * type or whether the queue is active.
632 */
633 dqm->total_queue_count++;
634 pr_debug("Total of %d queues are accountable so far\n",
635 dqm->total_queue_count);
636 goto out_unlock;
637
638out_free_mqd:
639 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
640out_deallocate_doorbell:
641 deallocate_doorbell(qpd, q);
642out_deallocate_hqd:
643 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
644 deallocate_hqd(dqm, q);
645 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
646 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
647 deallocate_sdma_queue(dqm, q);
648deallocate_vmid:
649 if (list_empty(&qpd->queues_list))
650 deallocate_vmid(dqm, qpd, q);
651out_unlock:
652 dqm_unlock(dqm);
653 return retval;
654}
655
656static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
657{
658 bool set;
659 int pipe, bit, i;
660
661 set = false;
662
663 for (pipe = dqm->next_pipe_to_allocate, i = 0;
664 i < get_pipes_per_mec(dqm);
665 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
666
667 if (!is_pipe_enabled(dqm, 0, pipe))
668 continue;
669
670 if (dqm->allocated_queues[pipe] != 0) {
671 bit = ffs(dqm->allocated_queues[pipe]) - 1;
672 dqm->allocated_queues[pipe] &= ~(1 << bit);
673 q->pipe = pipe;
674 q->queue = bit;
675 set = true;
676 break;
677 }
678 }
679
680 if (!set)
681 return -EBUSY;
682
683 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
684 /* horizontal hqd allocation */
685 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
686
687 return 0;
688}
689
690static inline void deallocate_hqd(struct device_queue_manager *dqm,
691 struct queue *q)
692{
693 dqm->allocated_queues[q->pipe] |= (1 << q->queue);
694}
695
696#define SQ_IND_CMD_CMD_KILL 0x00000003
697#define SQ_IND_CMD_MODE_BROADCAST 0x00000001
698
699static int dbgdev_wave_reset_wavefronts(struct kfd_node *dev, struct kfd_process *p)
700{
701 int status = 0;
702 unsigned int vmid;
703 uint16_t queried_pasid;
704 union SQ_CMD_BITS reg_sq_cmd;
705 union GRBM_GFX_INDEX_BITS reg_gfx_index;
706 struct kfd_process_device *pdd;
707 int first_vmid_to_scan = dev->vm_info.first_vmid_kfd;
708 int last_vmid_to_scan = dev->vm_info.last_vmid_kfd;
709 uint32_t xcc_mask = dev->xcc_mask;
710 int xcc_id;
711
712 reg_sq_cmd.u32All = 0;
713 reg_gfx_index.u32All = 0;
714
715 pr_debug("Killing all process wavefronts\n");
716
717 if (!dev->kfd2kgd->get_atc_vmid_pasid_mapping_info) {
718 dev_err(dev->adev->dev, "no vmid pasid mapping supported\n");
719 return -EOPNOTSUPP;
720 }
721
722 /* Scan all registers in the range ATC_VMID8_PASID_MAPPING ..
723 * ATC_VMID15_PASID_MAPPING
724 * to check which VMID the current process is mapped to.
725 */
726
727 for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) {
728 status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info
729 (dev->adev, vmid, &queried_pasid);
730
731 if (status && queried_pasid == p->pasid) {
732 pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",
733 vmid, p->pasid);
734 break;
735 }
736 }
737
738 if (vmid > last_vmid_to_scan) {
739 dev_err(dev->adev->dev, "Didn't find vmid for pasid 0x%x\n", p->pasid);
740 return -EFAULT;
741 }
742
743 /* taking the VMID for that process on the safe way using PDD */
744 pdd = kfd_get_process_device_data(dev, p);
745 if (!pdd)
746 return -EFAULT;
747
748 reg_gfx_index.bits.sh_broadcast_writes = 1;
749 reg_gfx_index.bits.se_broadcast_writes = 1;
750 reg_gfx_index.bits.instance_broadcast_writes = 1;
751 reg_sq_cmd.bits.mode = SQ_IND_CMD_MODE_BROADCAST;
752 reg_sq_cmd.bits.cmd = SQ_IND_CMD_CMD_KILL;
753 reg_sq_cmd.bits.vm_id = vmid;
754
755 for_each_inst(xcc_id, xcc_mask)
756 dev->kfd2kgd->wave_control_execute(
757 dev->adev, reg_gfx_index.u32All,
758 reg_sq_cmd.u32All, xcc_id);
759
760 return 0;
761}
762
763/* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
764 * to avoid asynchronized access
765 */
766static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
767 struct qcm_process_device *qpd,
768 struct queue *q)
769{
770 int retval;
771 struct mqd_manager *mqd_mgr;
772
773 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
774 q->properties.type)];
775
776 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
777 deallocate_hqd(dqm, q);
778 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
779 deallocate_sdma_queue(dqm, q);
780 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
781 deallocate_sdma_queue(dqm, q);
782 else {
783 pr_debug("q->properties.type %d is invalid\n",
784 q->properties.type);
785 return -EINVAL;
786 }
787 dqm->total_queue_count--;
788
789 deallocate_doorbell(qpd, q);
790
791 if (!dqm->sched_running) {
792 WARN_ONCE(1, "Destroy non-HWS queue while stopped\n");
793 return 0;
794 }
795
796 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
797 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
798 KFD_UNMAP_LATENCY_MS,
799 q->pipe, q->queue);
800 if (retval == -ETIME)
801 qpd->reset_wavefronts = true;
802
803 list_del(&q->list);
804 if (list_empty(&qpd->queues_list)) {
805 if (qpd->reset_wavefronts) {
806 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
807 dqm->dev);
808 /* dbgdev_wave_reset_wavefronts has to be called before
809 * deallocate_vmid(), i.e. when vmid is still in use.
810 */
811 dbgdev_wave_reset_wavefronts(dqm->dev,
812 qpd->pqm->process);
813 qpd->reset_wavefronts = false;
814 }
815
816 deallocate_vmid(dqm, qpd, q);
817 }
818 qpd->queue_count--;
819 if (q->properties.is_active)
820 decrement_queue_count(dqm, qpd, q);
821
822 return retval;
823}
824
825static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
826 struct qcm_process_device *qpd,
827 struct queue *q)
828{
829 int retval;
830 uint64_t sdma_val = 0;
831 struct device *dev = dqm->dev->adev->dev;
832 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
833 struct mqd_manager *mqd_mgr =
834 dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)];
835
836 /* Get the SDMA queue stats */
837 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
838 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
839 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr,
840 &sdma_val);
841 if (retval)
842 dev_err(dev, "Failed to read SDMA queue counter for queue: %d\n",
843 q->properties.queue_id);
844 }
845
846 dqm_lock(dqm);
847 retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
848 if (!retval)
849 pdd->sdma_past_activity_counter += sdma_val;
850 dqm_unlock(dqm);
851
852 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
853
854 return retval;
855}
856
857static int update_queue(struct device_queue_manager *dqm, struct queue *q,
858 struct mqd_update_info *minfo)
859{
860 int retval = 0;
861 struct device *dev = dqm->dev->adev->dev;
862 struct mqd_manager *mqd_mgr;
863 struct kfd_process_device *pdd;
864 bool prev_active = false;
865
866 dqm_lock(dqm);
867 pdd = kfd_get_process_device_data(q->device, q->process);
868 if (!pdd) {
869 retval = -ENODEV;
870 goto out_unlock;
871 }
872 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
873 q->properties.type)];
874
875 /* Save previous activity state for counters */
876 prev_active = q->properties.is_active;
877
878 /* Make sure the queue is unmapped before updating the MQD */
879 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
880 if (!dqm->dev->kfd->shared_resources.enable_mes)
881 retval = unmap_queues_cpsch(dqm,
882 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false);
883 else if (prev_active)
884 retval = remove_queue_mes(dqm, q, &pdd->qpd);
885
886 if (retval) {
887 dev_err(dev, "unmap queue failed\n");
888 goto out_unlock;
889 }
890 } else if (prev_active &&
891 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
892 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
893 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
894
895 if (!dqm->sched_running) {
896 WARN_ONCE(1, "Update non-HWS queue while stopped\n");
897 goto out_unlock;
898 }
899
900 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
901 (dqm->dev->kfd->cwsr_enabled ?
902 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE :
903 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
904 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
905 if (retval) {
906 dev_err(dev, "destroy mqd failed\n");
907 goto out_unlock;
908 }
909 }
910
911 mqd_mgr->update_mqd(mqd_mgr, q->mqd, &q->properties, minfo);
912
913 /*
914 * check active state vs. the previous state and modify
915 * counter accordingly. map_queues_cpsch uses the
916 * dqm->active_queue_count to determine whether a new runlist must be
917 * uploaded.
918 */
919 if (q->properties.is_active && !prev_active) {
920 increment_queue_count(dqm, &pdd->qpd, q);
921 } else if (!q->properties.is_active && prev_active) {
922 decrement_queue_count(dqm, &pdd->qpd, q);
923 } else if (q->gws && !q->properties.is_gws) {
924 if (q->properties.is_active) {
925 dqm->gws_queue_count++;
926 pdd->qpd.mapped_gws_queue = true;
927 }
928 q->properties.is_gws = true;
929 } else if (!q->gws && q->properties.is_gws) {
930 if (q->properties.is_active) {
931 dqm->gws_queue_count--;
932 pdd->qpd.mapped_gws_queue = false;
933 }
934 q->properties.is_gws = false;
935 }
936
937 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
938 if (!dqm->dev->kfd->shared_resources.enable_mes)
939 retval = map_queues_cpsch(dqm);
940 else if (q->properties.is_active)
941 retval = add_queue_mes(dqm, q, &pdd->qpd);
942 } else if (q->properties.is_active &&
943 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
944 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
945 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
946 if (WARN(q->process->mm != current->mm,
947 "should only run in user thread"))
948 retval = -EFAULT;
949 else
950 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd,
951 q->pipe, q->queue,
952 &q->properties, current->mm);
953 }
954
955out_unlock:
956 dqm_unlock(dqm);
957 return retval;
958}
959
960/* suspend_single_queue does not lock the dqm like the
961 * evict_process_queues_cpsch or evict_process_queues_nocpsch. You should
962 * lock the dqm before calling, and unlock after calling.
963 *
964 * The reason we don't lock the dqm is because this function may be
965 * called on multiple queues in a loop, so rather than locking/unlocking
966 * multiple times, we will just keep the dqm locked for all of the calls.
967 */
968static int suspend_single_queue(struct device_queue_manager *dqm,
969 struct kfd_process_device *pdd,
970 struct queue *q)
971{
972 bool is_new;
973
974 if (q->properties.is_suspended)
975 return 0;
976
977 pr_debug("Suspending PASID %u queue [%i]\n",
978 pdd->process->pasid,
979 q->properties.queue_id);
980
981 is_new = q->properties.exception_status & KFD_EC_MASK(EC_QUEUE_NEW);
982
983 if (is_new || q->properties.is_being_destroyed) {
984 pr_debug("Suspend: skip %s queue id %i\n",
985 is_new ? "new" : "destroyed",
986 q->properties.queue_id);
987 return -EBUSY;
988 }
989
990 q->properties.is_suspended = true;
991 if (q->properties.is_active) {
992 if (dqm->dev->kfd->shared_resources.enable_mes) {
993 int r = remove_queue_mes(dqm, q, &pdd->qpd);
994
995 if (r)
996 return r;
997 }
998
999 decrement_queue_count(dqm, &pdd->qpd, q);
1000 q->properties.is_active = false;
1001 }
1002
1003 return 0;
1004}
1005
1006/* resume_single_queue does not lock the dqm like the functions
1007 * restore_process_queues_cpsch or restore_process_queues_nocpsch. You should
1008 * lock the dqm before calling, and unlock after calling.
1009 *
1010 * The reason we don't lock the dqm is because this function may be
1011 * called on multiple queues in a loop, so rather than locking/unlocking
1012 * multiple times, we will just keep the dqm locked for all of the calls.
1013 */
1014static int resume_single_queue(struct device_queue_manager *dqm,
1015 struct qcm_process_device *qpd,
1016 struct queue *q)
1017{
1018 struct kfd_process_device *pdd;
1019
1020 if (!q->properties.is_suspended)
1021 return 0;
1022
1023 pdd = qpd_to_pdd(qpd);
1024
1025 pr_debug("Restoring from suspend PASID %u queue [%i]\n",
1026 pdd->process->pasid,
1027 q->properties.queue_id);
1028
1029 q->properties.is_suspended = false;
1030
1031 if (QUEUE_IS_ACTIVE(q->properties)) {
1032 if (dqm->dev->kfd->shared_resources.enable_mes) {
1033 int r = add_queue_mes(dqm, q, &pdd->qpd);
1034
1035 if (r)
1036 return r;
1037 }
1038
1039 q->properties.is_active = true;
1040 increment_queue_count(dqm, qpd, q);
1041 }
1042
1043 return 0;
1044}
1045
1046static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
1047 struct qcm_process_device *qpd)
1048{
1049 struct queue *q;
1050 struct mqd_manager *mqd_mgr;
1051 struct kfd_process_device *pdd;
1052 int retval, ret = 0;
1053
1054 dqm_lock(dqm);
1055 if (qpd->evicted++ > 0) /* already evicted, do nothing */
1056 goto out;
1057
1058 pdd = qpd_to_pdd(qpd);
1059 pr_debug_ratelimited("Evicting PASID 0x%x queues\n",
1060 pdd->process->pasid);
1061
1062 pdd->last_evict_timestamp = get_jiffies_64();
1063 /* Mark all queues as evicted. Deactivate all active queues on
1064 * the qpd.
1065 */
1066 list_for_each_entry(q, &qpd->queues_list, list) {
1067 q->properties.is_evicted = true;
1068 if (!q->properties.is_active)
1069 continue;
1070
1071 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1072 q->properties.type)];
1073 q->properties.is_active = false;
1074 decrement_queue_count(dqm, qpd, q);
1075
1076 if (WARN_ONCE(!dqm->sched_running, "Evict when stopped\n"))
1077 continue;
1078
1079 retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
1080 (dqm->dev->kfd->cwsr_enabled ?
1081 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE :
1082 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
1083 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
1084 if (retval && !ret)
1085 /* Return the first error, but keep going to
1086 * maintain a consistent eviction state
1087 */
1088 ret = retval;
1089 }
1090
1091out:
1092 dqm_unlock(dqm);
1093 return ret;
1094}
1095
1096static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
1097 struct qcm_process_device *qpd)
1098{
1099 struct queue *q;
1100 struct device *dev = dqm->dev->adev->dev;
1101 struct kfd_process_device *pdd;
1102 int retval = 0;
1103
1104 dqm_lock(dqm);
1105 if (qpd->evicted++ > 0) /* already evicted, do nothing */
1106 goto out;
1107
1108 pdd = qpd_to_pdd(qpd);
1109
1110 /* The debugger creates processes that temporarily have not acquired
1111 * all VMs for all devices and has no VMs itself.
1112 * Skip queue eviction on process eviction.
1113 */
1114 if (!pdd->drm_priv)
1115 goto out;
1116
1117 pr_debug_ratelimited("Evicting PASID 0x%x queues\n",
1118 pdd->process->pasid);
1119
1120 /* Mark all queues as evicted. Deactivate all active queues on
1121 * the qpd.
1122 */
1123 list_for_each_entry(q, &qpd->queues_list, list) {
1124 q->properties.is_evicted = true;
1125 if (!q->properties.is_active)
1126 continue;
1127
1128 q->properties.is_active = false;
1129 decrement_queue_count(dqm, qpd, q);
1130
1131 if (dqm->dev->kfd->shared_resources.enable_mes) {
1132 retval = remove_queue_mes(dqm, q, qpd);
1133 if (retval) {
1134 dev_err(dev, "Failed to evict queue %d\n",
1135 q->properties.queue_id);
1136 goto out;
1137 }
1138 }
1139 }
1140 pdd->last_evict_timestamp = get_jiffies_64();
1141 if (!dqm->dev->kfd->shared_resources.enable_mes)
1142 retval = execute_queues_cpsch(dqm,
1143 qpd->is_debug ?
1144 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
1145 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
1146 USE_DEFAULT_GRACE_PERIOD);
1147
1148out:
1149 dqm_unlock(dqm);
1150 return retval;
1151}
1152
1153static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
1154 struct qcm_process_device *qpd)
1155{
1156 struct mm_struct *mm = NULL;
1157 struct queue *q;
1158 struct mqd_manager *mqd_mgr;
1159 struct kfd_process_device *pdd;
1160 uint64_t pd_base;
1161 uint64_t eviction_duration;
1162 int retval, ret = 0;
1163
1164 pdd = qpd_to_pdd(qpd);
1165 /* Retrieve PD base */
1166 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1167
1168 dqm_lock(dqm);
1169 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
1170 goto out;
1171 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
1172 qpd->evicted--;
1173 goto out;
1174 }
1175
1176 pr_debug_ratelimited("Restoring PASID 0x%x queues\n",
1177 pdd->process->pasid);
1178
1179 /* Update PD Base in QPD */
1180 qpd->page_table_base = pd_base;
1181 pr_debug("Updated PD address to 0x%llx\n", pd_base);
1182
1183 if (!list_empty(&qpd->queues_list)) {
1184 dqm->dev->kfd2kgd->set_vm_context_page_table_base(
1185 dqm->dev->adev,
1186 qpd->vmid,
1187 qpd->page_table_base);
1188 kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY);
1189 }
1190
1191 /* Take a safe reference to the mm_struct, which may otherwise
1192 * disappear even while the kfd_process is still referenced.
1193 */
1194 mm = get_task_mm(pdd->process->lead_thread);
1195 if (!mm) {
1196 ret = -EFAULT;
1197 goto out;
1198 }
1199
1200 /* Remove the eviction flags. Activate queues that are not
1201 * inactive for other reasons.
1202 */
1203 list_for_each_entry(q, &qpd->queues_list, list) {
1204 q->properties.is_evicted = false;
1205 if (!QUEUE_IS_ACTIVE(q->properties))
1206 continue;
1207
1208 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1209 q->properties.type)];
1210 q->properties.is_active = true;
1211 increment_queue_count(dqm, qpd, q);
1212
1213 if (WARN_ONCE(!dqm->sched_running, "Restore when stopped\n"))
1214 continue;
1215
1216 retval = mqd_mgr->load_mqd(mqd_mgr, q->mqd, q->pipe,
1217 q->queue, &q->properties, mm);
1218 if (retval && !ret)
1219 /* Return the first error, but keep going to
1220 * maintain a consistent eviction state
1221 */
1222 ret = retval;
1223 }
1224 qpd->evicted = 0;
1225 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
1226 atomic64_add(eviction_duration, &pdd->evict_duration_counter);
1227out:
1228 if (mm)
1229 mmput(mm);
1230 dqm_unlock(dqm);
1231 return ret;
1232}
1233
1234static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
1235 struct qcm_process_device *qpd)
1236{
1237 struct queue *q;
1238 struct device *dev = dqm->dev->adev->dev;
1239 struct kfd_process_device *pdd;
1240 uint64_t eviction_duration;
1241 int retval = 0;
1242
1243 pdd = qpd_to_pdd(qpd);
1244
1245 dqm_lock(dqm);
1246 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
1247 goto out;
1248 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
1249 qpd->evicted--;
1250 goto out;
1251 }
1252
1253 /* The debugger creates processes that temporarily have not acquired
1254 * all VMs for all devices and has no VMs itself.
1255 * Skip queue restore on process restore.
1256 */
1257 if (!pdd->drm_priv)
1258 goto vm_not_acquired;
1259
1260 pr_debug_ratelimited("Restoring PASID 0x%x queues\n",
1261 pdd->process->pasid);
1262
1263 /* Update PD Base in QPD */
1264 qpd->page_table_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1265 pr_debug("Updated PD address to 0x%llx\n", qpd->page_table_base);
1266
1267 /* activate all active queues on the qpd */
1268 list_for_each_entry(q, &qpd->queues_list, list) {
1269 q->properties.is_evicted = false;
1270 if (!QUEUE_IS_ACTIVE(q->properties))
1271 continue;
1272
1273 q->properties.is_active = true;
1274 increment_queue_count(dqm, &pdd->qpd, q);
1275
1276 if (dqm->dev->kfd->shared_resources.enable_mes) {
1277 retval = add_queue_mes(dqm, q, qpd);
1278 if (retval) {
1279 dev_err(dev, "Failed to restore queue %d\n",
1280 q->properties.queue_id);
1281 goto out;
1282 }
1283 }
1284 }
1285 if (!dqm->dev->kfd->shared_resources.enable_mes)
1286 retval = execute_queues_cpsch(dqm,
1287 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1288 eviction_duration = get_jiffies_64() - pdd->last_evict_timestamp;
1289 atomic64_add(eviction_duration, &pdd->evict_duration_counter);
1290vm_not_acquired:
1291 qpd->evicted = 0;
1292out:
1293 dqm_unlock(dqm);
1294 return retval;
1295}
1296
1297static int register_process(struct device_queue_manager *dqm,
1298 struct qcm_process_device *qpd)
1299{
1300 struct device_process_node *n;
1301 struct kfd_process_device *pdd;
1302 uint64_t pd_base;
1303 int retval;
1304
1305 n = kzalloc(sizeof(*n), GFP_KERNEL);
1306 if (!n)
1307 return -ENOMEM;
1308
1309 n->qpd = qpd;
1310
1311 pdd = qpd_to_pdd(qpd);
1312 /* Retrieve PD base */
1313 pd_base = amdgpu_amdkfd_gpuvm_get_process_page_dir(pdd->drm_priv);
1314
1315 dqm_lock(dqm);
1316 list_add(&n->list, &dqm->queues);
1317
1318 /* Update PD Base in QPD */
1319 qpd->page_table_base = pd_base;
1320 pr_debug("Updated PD address to 0x%llx\n", pd_base);
1321
1322 retval = dqm->asic_ops.update_qpd(dqm, qpd);
1323
1324 dqm->processes_count++;
1325
1326 dqm_unlock(dqm);
1327
1328 /* Outside the DQM lock because under the DQM lock we can't do
1329 * reclaim or take other locks that others hold while reclaiming.
1330 */
1331 kfd_inc_compute_active(dqm->dev);
1332
1333 return retval;
1334}
1335
1336static int unregister_process(struct device_queue_manager *dqm,
1337 struct qcm_process_device *qpd)
1338{
1339 int retval;
1340 struct device_process_node *cur, *next;
1341
1342 pr_debug("qpd->queues_list is %s\n",
1343 list_empty(&qpd->queues_list) ? "empty" : "not empty");
1344
1345 retval = 0;
1346 dqm_lock(dqm);
1347
1348 list_for_each_entry_safe(cur, next, &dqm->queues, list) {
1349 if (qpd == cur->qpd) {
1350 list_del(&cur->list);
1351 kfree(cur);
1352 dqm->processes_count--;
1353 goto out;
1354 }
1355 }
1356 /* qpd not found in dqm list */
1357 retval = 1;
1358out:
1359 dqm_unlock(dqm);
1360
1361 /* Outside the DQM lock because under the DQM lock we can't do
1362 * reclaim or take other locks that others hold while reclaiming.
1363 */
1364 if (!retval)
1365 kfd_dec_compute_active(dqm->dev);
1366
1367 return retval;
1368}
1369
1370static int
1371set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid,
1372 unsigned int vmid)
1373{
1374 uint32_t xcc_mask = dqm->dev->xcc_mask;
1375 int xcc_id, ret;
1376
1377 for_each_inst(xcc_id, xcc_mask) {
1378 ret = dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
1379 dqm->dev->adev, pasid, vmid, xcc_id);
1380 if (ret)
1381 break;
1382 }
1383
1384 return ret;
1385}
1386
1387static void init_interrupts(struct device_queue_manager *dqm)
1388{
1389 uint32_t xcc_mask = dqm->dev->xcc_mask;
1390 unsigned int i, xcc_id;
1391
1392 for_each_inst(xcc_id, xcc_mask) {
1393 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++) {
1394 if (is_pipe_enabled(dqm, 0, i)) {
1395 dqm->dev->kfd2kgd->init_interrupts(
1396 dqm->dev->adev, i, xcc_id);
1397 }
1398 }
1399 }
1400}
1401
1402static int initialize_nocpsch(struct device_queue_manager *dqm)
1403{
1404 int pipe, queue;
1405
1406 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1407
1408 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
1409 sizeof(unsigned int), GFP_KERNEL);
1410 if (!dqm->allocated_queues)
1411 return -ENOMEM;
1412
1413 mutex_init(&dqm->lock_hidden);
1414 INIT_LIST_HEAD(&dqm->queues);
1415 dqm->active_queue_count = dqm->next_pipe_to_allocate = 0;
1416 dqm->active_cp_queue_count = 0;
1417 dqm->gws_queue_count = 0;
1418
1419 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
1420 int pipe_offset = pipe * get_queues_per_pipe(dqm);
1421
1422 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
1423 if (test_bit(pipe_offset + queue,
1424 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
1425 dqm->allocated_queues[pipe] |= 1 << queue;
1426 }
1427
1428 memset(dqm->vmid_pasid, 0, sizeof(dqm->vmid_pasid));
1429
1430 init_sdma_bitmaps(dqm);
1431
1432 return 0;
1433}
1434
1435static void uninitialize(struct device_queue_manager *dqm)
1436{
1437 int i;
1438
1439 WARN_ON(dqm->active_queue_count > 0 || dqm->processes_count > 0);
1440
1441 kfree(dqm->allocated_queues);
1442 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
1443 kfree(dqm->mqd_mgrs[i]);
1444 mutex_destroy(&dqm->lock_hidden);
1445}
1446
1447static int start_nocpsch(struct device_queue_manager *dqm)
1448{
1449 int r = 0;
1450
1451 pr_info("SW scheduler is used");
1452 init_interrupts(dqm);
1453
1454 if (dqm->dev->adev->asic_type == CHIP_HAWAII)
1455 r = pm_init(&dqm->packet_mgr, dqm);
1456 if (!r)
1457 dqm->sched_running = true;
1458
1459 return r;
1460}
1461
1462static int stop_nocpsch(struct device_queue_manager *dqm)
1463{
1464 dqm_lock(dqm);
1465 if (!dqm->sched_running) {
1466 dqm_unlock(dqm);
1467 return 0;
1468 }
1469
1470 if (dqm->dev->adev->asic_type == CHIP_HAWAII)
1471 pm_uninit(&dqm->packet_mgr, false);
1472 dqm->sched_running = false;
1473 dqm_unlock(dqm);
1474
1475 return 0;
1476}
1477
1478static void pre_reset(struct device_queue_manager *dqm)
1479{
1480 dqm_lock(dqm);
1481 dqm->is_resetting = true;
1482 dqm_unlock(dqm);
1483}
1484
1485static int allocate_sdma_queue(struct device_queue_manager *dqm,
1486 struct queue *q, const uint32_t *restore_sdma_id)
1487{
1488 struct device *dev = dqm->dev->adev->dev;
1489 int bit;
1490
1491 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1492 if (bitmap_empty(dqm->sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {
1493 dev_err(dev, "No more SDMA queue to allocate\n");
1494 return -ENOMEM;
1495 }
1496
1497 if (restore_sdma_id) {
1498 /* Re-use existing sdma_id */
1499 if (!test_bit(*restore_sdma_id, dqm->sdma_bitmap)) {
1500 dev_err(dev, "SDMA queue already in use\n");
1501 return -EBUSY;
1502 }
1503 clear_bit(*restore_sdma_id, dqm->sdma_bitmap);
1504 q->sdma_id = *restore_sdma_id;
1505 } else {
1506 /* Find first available sdma_id */
1507 bit = find_first_bit(dqm->sdma_bitmap,
1508 get_num_sdma_queues(dqm));
1509 clear_bit(bit, dqm->sdma_bitmap);
1510 q->sdma_id = bit;
1511 }
1512
1513 q->properties.sdma_engine_id =
1514 q->sdma_id % kfd_get_num_sdma_engines(dqm->dev);
1515 q->properties.sdma_queue_id = q->sdma_id /
1516 kfd_get_num_sdma_engines(dqm->dev);
1517 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1518 if (bitmap_empty(dqm->xgmi_sdma_bitmap, KFD_MAX_SDMA_QUEUES)) {
1519 dev_err(dev, "No more XGMI SDMA queue to allocate\n");
1520 return -ENOMEM;
1521 }
1522 if (restore_sdma_id) {
1523 /* Re-use existing sdma_id */
1524 if (!test_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap)) {
1525 dev_err(dev, "SDMA queue already in use\n");
1526 return -EBUSY;
1527 }
1528 clear_bit(*restore_sdma_id, dqm->xgmi_sdma_bitmap);
1529 q->sdma_id = *restore_sdma_id;
1530 } else {
1531 bit = find_first_bit(dqm->xgmi_sdma_bitmap,
1532 get_num_xgmi_sdma_queues(dqm));
1533 clear_bit(bit, dqm->xgmi_sdma_bitmap);
1534 q->sdma_id = bit;
1535 }
1536 /* sdma_engine_id is sdma id including
1537 * both PCIe-optimized SDMAs and XGMI-
1538 * optimized SDMAs. The calculation below
1539 * assumes the first N engines are always
1540 * PCIe-optimized ones
1541 */
1542 q->properties.sdma_engine_id =
1543 kfd_get_num_sdma_engines(dqm->dev) +
1544 q->sdma_id % kfd_get_num_xgmi_sdma_engines(dqm->dev);
1545 q->properties.sdma_queue_id = q->sdma_id /
1546 kfd_get_num_xgmi_sdma_engines(dqm->dev);
1547 }
1548
1549 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
1550 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
1551
1552 return 0;
1553}
1554
1555static void deallocate_sdma_queue(struct device_queue_manager *dqm,
1556 struct queue *q)
1557{
1558 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1559 if (q->sdma_id >= get_num_sdma_queues(dqm))
1560 return;
1561 set_bit(q->sdma_id, dqm->sdma_bitmap);
1562 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1563 if (q->sdma_id >= get_num_xgmi_sdma_queues(dqm))
1564 return;
1565 set_bit(q->sdma_id, dqm->xgmi_sdma_bitmap);
1566 }
1567}
1568
1569/*
1570 * Device Queue Manager implementation for cp scheduler
1571 */
1572
1573static int set_sched_resources(struct device_queue_manager *dqm)
1574{
1575 int i, mec;
1576 struct scheduling_resources res;
1577 struct device *dev = dqm->dev->adev->dev;
1578
1579 res.vmid_mask = dqm->dev->compute_vmid_bitmap;
1580
1581 res.queue_mask = 0;
1582 for (i = 0; i < AMDGPU_MAX_QUEUES; ++i) {
1583 mec = (i / dqm->dev->kfd->shared_resources.num_queue_per_pipe)
1584 / dqm->dev->kfd->shared_resources.num_pipe_per_mec;
1585
1586 if (!test_bit(i, dqm->dev->kfd->shared_resources.cp_queue_bitmap))
1587 continue;
1588
1589 /* only acquire queues from the first MEC */
1590 if (mec > 0)
1591 continue;
1592
1593 /* This situation may be hit in the future if a new HW
1594 * generation exposes more than 64 queues. If so, the
1595 * definition of res.queue_mask needs updating
1596 */
1597 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
1598 dev_err(dev, "Invalid queue enabled by amdgpu: %d\n", i);
1599 break;
1600 }
1601
1602 res.queue_mask |= 1ull
1603 << amdgpu_queue_mask_bit_to_set_resource_bit(
1604 dqm->dev->adev, i);
1605 }
1606 res.gws_mask = ~0ull;
1607 res.oac_mask = res.gds_heap_base = res.gds_heap_size = 0;
1608
1609 pr_debug("Scheduling resources:\n"
1610 "vmid mask: 0x%8X\n"
1611 "queue mask: 0x%8llX\n",
1612 res.vmid_mask, res.queue_mask);
1613
1614 return pm_send_set_resources(&dqm->packet_mgr, &res);
1615}
1616
1617static int initialize_cpsch(struct device_queue_manager *dqm)
1618{
1619 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
1620
1621 mutex_init(&dqm->lock_hidden);
1622 INIT_LIST_HEAD(&dqm->queues);
1623 dqm->active_queue_count = dqm->processes_count = 0;
1624 dqm->active_cp_queue_count = 0;
1625 dqm->gws_queue_count = 0;
1626 dqm->active_runlist = false;
1627 INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception);
1628 dqm->trap_debug_vmid = 0;
1629
1630 init_sdma_bitmaps(dqm);
1631
1632 if (dqm->dev->kfd2kgd->get_iq_wait_times)
1633 dqm->dev->kfd2kgd->get_iq_wait_times(dqm->dev->adev,
1634 &dqm->wait_times,
1635 ffs(dqm->dev->xcc_mask) - 1);
1636 return 0;
1637}
1638
1639static int start_cpsch(struct device_queue_manager *dqm)
1640{
1641 struct device *dev = dqm->dev->adev->dev;
1642 int retval;
1643
1644 retval = 0;
1645
1646 dqm_lock(dqm);
1647
1648 if (!dqm->dev->kfd->shared_resources.enable_mes) {
1649 retval = pm_init(&dqm->packet_mgr, dqm);
1650 if (retval)
1651 goto fail_packet_manager_init;
1652
1653 retval = set_sched_resources(dqm);
1654 if (retval)
1655 goto fail_set_sched_resources;
1656 }
1657 pr_debug("Allocating fence memory\n");
1658
1659 /* allocate fence memory on the gart */
1660 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
1661 &dqm->fence_mem);
1662
1663 if (retval)
1664 goto fail_allocate_vidmem;
1665
1666 dqm->fence_addr = (uint64_t *)dqm->fence_mem->cpu_ptr;
1667 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
1668
1669 init_interrupts(dqm);
1670
1671 /* clear hang status when driver try to start the hw scheduler */
1672 dqm->is_hws_hang = false;
1673 dqm->is_resetting = false;
1674 dqm->sched_running = true;
1675
1676 if (!dqm->dev->kfd->shared_resources.enable_mes)
1677 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1678
1679 /* Set CWSR grace period to 1x1000 cycle for GFX9.4.3 APU */
1680 if (amdgpu_emu_mode == 0 && dqm->dev->adev->gmc.is_app_apu &&
1681 (KFD_GC_VERSION(dqm->dev) == IP_VERSION(9, 4, 3))) {
1682 uint32_t reg_offset = 0;
1683 uint32_t grace_period = 1;
1684
1685 retval = pm_update_grace_period(&dqm->packet_mgr,
1686 grace_period);
1687 if (retval)
1688 dev_err(dev, "Setting grace timeout failed\n");
1689 else if (dqm->dev->kfd2kgd->build_grace_period_packet_info)
1690 /* Update dqm->wait_times maintained in software */
1691 dqm->dev->kfd2kgd->build_grace_period_packet_info(
1692 dqm->dev->adev, dqm->wait_times,
1693 grace_period, ®_offset,
1694 &dqm->wait_times);
1695 }
1696
1697 dqm_unlock(dqm);
1698
1699 return 0;
1700fail_allocate_vidmem:
1701fail_set_sched_resources:
1702 if (!dqm->dev->kfd->shared_resources.enable_mes)
1703 pm_uninit(&dqm->packet_mgr, false);
1704fail_packet_manager_init:
1705 dqm_unlock(dqm);
1706 return retval;
1707}
1708
1709static int stop_cpsch(struct device_queue_manager *dqm)
1710{
1711 bool hanging;
1712
1713 dqm_lock(dqm);
1714 if (!dqm->sched_running) {
1715 dqm_unlock(dqm);
1716 return 0;
1717 }
1718
1719 if (!dqm->is_hws_hang) {
1720 if (!dqm->dev->kfd->shared_resources.enable_mes)
1721 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD, false);
1722 else
1723 remove_all_queues_mes(dqm);
1724 }
1725
1726 hanging = dqm->is_hws_hang || dqm->is_resetting;
1727 dqm->sched_running = false;
1728
1729 if (!dqm->dev->kfd->shared_resources.enable_mes)
1730 pm_release_ib(&dqm->packet_mgr);
1731
1732 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
1733 if (!dqm->dev->kfd->shared_resources.enable_mes)
1734 pm_uninit(&dqm->packet_mgr, hanging);
1735 dqm_unlock(dqm);
1736
1737 return 0;
1738}
1739
1740static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
1741 struct kernel_queue *kq,
1742 struct qcm_process_device *qpd)
1743{
1744 dqm_lock(dqm);
1745 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1746 pr_warn("Can't create new kernel queue because %d queues were already created\n",
1747 dqm->total_queue_count);
1748 dqm_unlock(dqm);
1749 return -EPERM;
1750 }
1751
1752 /*
1753 * Unconditionally increment this counter, regardless of the queue's
1754 * type or whether the queue is active.
1755 */
1756 dqm->total_queue_count++;
1757 pr_debug("Total of %d queues are accountable so far\n",
1758 dqm->total_queue_count);
1759
1760 list_add(&kq->list, &qpd->priv_queue_list);
1761 increment_queue_count(dqm, qpd, kq->queue);
1762 qpd->is_debug = true;
1763 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
1764 USE_DEFAULT_GRACE_PERIOD);
1765 dqm_unlock(dqm);
1766
1767 return 0;
1768}
1769
1770static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
1771 struct kernel_queue *kq,
1772 struct qcm_process_device *qpd)
1773{
1774 dqm_lock(dqm);
1775 list_del(&kq->list);
1776 decrement_queue_count(dqm, qpd, kq->queue);
1777 qpd->is_debug = false;
1778 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
1779 USE_DEFAULT_GRACE_PERIOD);
1780 /*
1781 * Unconditionally decrement this counter, regardless of the queue's
1782 * type.
1783 */
1784 dqm->total_queue_count--;
1785 pr_debug("Total of %d queues are accountable so far\n",
1786 dqm->total_queue_count);
1787 dqm_unlock(dqm);
1788}
1789
1790static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
1791 struct qcm_process_device *qpd,
1792 const struct kfd_criu_queue_priv_data *qd,
1793 const void *restore_mqd, const void *restore_ctl_stack)
1794{
1795 int retval;
1796 struct mqd_manager *mqd_mgr;
1797
1798 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1799 pr_warn("Can't create new usermode queue because %d queues were already created\n",
1800 dqm->total_queue_count);
1801 retval = -EPERM;
1802 goto out;
1803 }
1804
1805 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1806 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1807 dqm_lock(dqm);
1808 retval = allocate_sdma_queue(dqm, q, qd ? &qd->sdma_id : NULL);
1809 dqm_unlock(dqm);
1810 if (retval)
1811 goto out;
1812 }
1813
1814 retval = allocate_doorbell(qpd, q, qd ? &qd->doorbell_id : NULL);
1815 if (retval)
1816 goto out_deallocate_sdma_queue;
1817
1818 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
1819 q->properties.type)];
1820
1821 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1822 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
1823 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
1824 q->properties.tba_addr = qpd->tba_addr;
1825 q->properties.tma_addr = qpd->tma_addr;
1826 q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties);
1827 if (!q->mqd_mem_obj) {
1828 retval = -ENOMEM;
1829 goto out_deallocate_doorbell;
1830 }
1831
1832 dqm_lock(dqm);
1833 /*
1834 * Eviction state logic: mark all queues as evicted, even ones
1835 * not currently active. Restoring inactive queues later only
1836 * updates the is_evicted flag but is a no-op otherwise.
1837 */
1838 q->properties.is_evicted = !!qpd->evicted;
1839 q->properties.is_dbg_wa = qpd->pqm->process->debug_trap_enabled &&
1840 kfd_dbg_has_cwsr_workaround(q->device);
1841
1842 if (qd)
1843 mqd_mgr->restore_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj, &q->gart_mqd_addr,
1844 &q->properties, restore_mqd, restore_ctl_stack,
1845 qd->ctl_stack_size);
1846 else
1847 mqd_mgr->init_mqd(mqd_mgr, &q->mqd, q->mqd_mem_obj,
1848 &q->gart_mqd_addr, &q->properties);
1849
1850 list_add(&q->list, &qpd->queues_list);
1851 qpd->queue_count++;
1852
1853 if (q->properties.is_active) {
1854 increment_queue_count(dqm, qpd, q);
1855
1856 if (!dqm->dev->kfd->shared_resources.enable_mes)
1857 retval = execute_queues_cpsch(dqm,
1858 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD);
1859 else
1860 retval = add_queue_mes(dqm, q, qpd);
1861 if (retval)
1862 goto cleanup_queue;
1863 }
1864
1865 /*
1866 * Unconditionally increment this counter, regardless of the queue's
1867 * type or whether the queue is active.
1868 */
1869 dqm->total_queue_count++;
1870
1871 pr_debug("Total of %d queues are accountable so far\n",
1872 dqm->total_queue_count);
1873
1874 dqm_unlock(dqm);
1875 return retval;
1876
1877cleanup_queue:
1878 qpd->queue_count--;
1879 list_del(&q->list);
1880 if (q->properties.is_active)
1881 decrement_queue_count(dqm, qpd, q);
1882 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
1883 dqm_unlock(dqm);
1884out_deallocate_doorbell:
1885 deallocate_doorbell(qpd, q);
1886out_deallocate_sdma_queue:
1887 if (q->properties.type == KFD_QUEUE_TYPE_SDMA ||
1888 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
1889 dqm_lock(dqm);
1890 deallocate_sdma_queue(dqm, q);
1891 dqm_unlock(dqm);
1892 }
1893out:
1894 return retval;
1895}
1896
1897int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm,
1898 uint64_t fence_value,
1899 unsigned int timeout_ms)
1900{
1901 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
1902 struct device *dev = dqm->dev->adev->dev;
1903 uint64_t *fence_addr = dqm->fence_addr;
1904
1905 while (*fence_addr != fence_value) {
1906 /* Fatal err detected, this response won't come */
1907 if (amdgpu_amdkfd_is_fed(dqm->dev->adev))
1908 return -EIO;
1909
1910 if (time_after(jiffies, end_jiffies)) {
1911 dev_err(dev, "qcm fence wait loop timeout expired\n");
1912 /* In HWS case, this is used to halt the driver thread
1913 * in order not to mess up CP states before doing
1914 * scandumps for FW debugging.
1915 */
1916 while (halt_if_hws_hang)
1917 schedule();
1918
1919 return -ETIME;
1920 }
1921 schedule();
1922 }
1923
1924 return 0;
1925}
1926
1927/* dqm->lock mutex has to be locked before calling this function */
1928static int map_queues_cpsch(struct device_queue_manager *dqm)
1929{
1930 struct device *dev = dqm->dev->adev->dev;
1931 int retval;
1932
1933 if (!dqm->sched_running)
1934 return 0;
1935 if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0)
1936 return 0;
1937 if (dqm->active_runlist)
1938 return 0;
1939
1940 retval = pm_send_runlist(&dqm->packet_mgr, &dqm->queues);
1941 pr_debug("%s sent runlist\n", __func__);
1942 if (retval) {
1943 dev_err(dev, "failed to execute runlist\n");
1944 return retval;
1945 }
1946 dqm->active_runlist = true;
1947
1948 return retval;
1949}
1950
1951/* dqm->lock mutex has to be locked before calling this function */
1952static int unmap_queues_cpsch(struct device_queue_manager *dqm,
1953 enum kfd_unmap_queues_filter filter,
1954 uint32_t filter_param,
1955 uint32_t grace_period,
1956 bool reset)
1957{
1958 struct device *dev = dqm->dev->adev->dev;
1959 struct mqd_manager *mqd_mgr;
1960 int retval = 0;
1961
1962 if (!dqm->sched_running)
1963 return 0;
1964 if (dqm->is_hws_hang || dqm->is_resetting)
1965 return -EIO;
1966 if (!dqm->active_runlist)
1967 return retval;
1968
1969 if (grace_period != USE_DEFAULT_GRACE_PERIOD) {
1970 retval = pm_update_grace_period(&dqm->packet_mgr, grace_period);
1971 if (retval)
1972 return retval;
1973 }
1974
1975 retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset);
1976 if (retval)
1977 return retval;
1978
1979 *dqm->fence_addr = KFD_FENCE_INIT;
1980 pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr,
1981 KFD_FENCE_COMPLETED);
1982 /* should be timed out */
1983 retval = amdkfd_fence_wait_timeout(dqm, KFD_FENCE_COMPLETED,
1984 queue_preemption_timeout_ms);
1985 if (retval) {
1986 dev_err(dev, "The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
1987 kfd_hws_hang(dqm);
1988 return retval;
1989 }
1990
1991 /* In the current MEC firmware implementation, if compute queue
1992 * doesn't response to the preemption request in time, HIQ will
1993 * abandon the unmap request without returning any timeout error
1994 * to driver. Instead, MEC firmware will log the doorbell of the
1995 * unresponding compute queue to HIQ.MQD.queue_doorbell_id fields.
1996 * To make sure the queue unmap was successful, driver need to
1997 * check those fields
1998 */
1999 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ];
2000 if (mqd_mgr->read_doorbell_id(dqm->packet_mgr.priv_queue->queue->mqd)) {
2001 dev_err(dev, "HIQ MQD's queue_doorbell_id0 is not 0, Queue preemption time out\n");
2002 while (halt_if_hws_hang)
2003 schedule();
2004 kfd_hws_hang(dqm);
2005 return -ETIME;
2006 }
2007
2008 /* We need to reset the grace period value for this device */
2009 if (grace_period != USE_DEFAULT_GRACE_PERIOD) {
2010 if (pm_update_grace_period(&dqm->packet_mgr,
2011 USE_DEFAULT_GRACE_PERIOD))
2012 dev_err(dev, "Failed to reset grace period\n");
2013 }
2014
2015 pm_release_ib(&dqm->packet_mgr);
2016 dqm->active_runlist = false;
2017
2018 return retval;
2019}
2020
2021/* only for compute queue */
2022static int reset_queues_cpsch(struct device_queue_manager *dqm,
2023 uint16_t pasid)
2024{
2025 int retval;
2026
2027 dqm_lock(dqm);
2028
2029 retval = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_BY_PASID,
2030 pasid, USE_DEFAULT_GRACE_PERIOD, true);
2031
2032 dqm_unlock(dqm);
2033 return retval;
2034}
2035
2036/* dqm->lock mutex has to be locked before calling this function */
2037static int execute_queues_cpsch(struct device_queue_manager *dqm,
2038 enum kfd_unmap_queues_filter filter,
2039 uint32_t filter_param,
2040 uint32_t grace_period)
2041{
2042 int retval;
2043
2044 if (dqm->is_hws_hang)
2045 return -EIO;
2046 retval = unmap_queues_cpsch(dqm, filter, filter_param, grace_period, false);
2047 if (retval)
2048 return retval;
2049
2050 return map_queues_cpsch(dqm);
2051}
2052
2053static int wait_on_destroy_queue(struct device_queue_manager *dqm,
2054 struct queue *q)
2055{
2056 struct kfd_process_device *pdd = kfd_get_process_device_data(q->device,
2057 q->process);
2058 int ret = 0;
2059
2060 if (pdd->qpd.is_debug)
2061 return ret;
2062
2063 q->properties.is_being_destroyed = true;
2064
2065 if (pdd->process->debug_trap_enabled && q->properties.is_suspended) {
2066 dqm_unlock(dqm);
2067 mutex_unlock(&q->process->mutex);
2068 ret = wait_event_interruptible(dqm->destroy_wait,
2069 !q->properties.is_suspended);
2070
2071 mutex_lock(&q->process->mutex);
2072 dqm_lock(dqm);
2073 }
2074
2075 return ret;
2076}
2077
2078static int destroy_queue_cpsch(struct device_queue_manager *dqm,
2079 struct qcm_process_device *qpd,
2080 struct queue *q)
2081{
2082 int retval;
2083 struct mqd_manager *mqd_mgr;
2084 uint64_t sdma_val = 0;
2085 struct kfd_process_device *pdd = qpd_to_pdd(qpd);
2086 struct device *dev = dqm->dev->adev->dev;
2087
2088 /* Get the SDMA queue stats */
2089 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
2090 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
2091 retval = read_sdma_queue_counter((uint64_t __user *)q->properties.read_ptr,
2092 &sdma_val);
2093 if (retval)
2094 dev_err(dev, "Failed to read SDMA queue counter for queue: %d\n",
2095 q->properties.queue_id);
2096 }
2097
2098 /* remove queue from list to prevent rescheduling after preemption */
2099 dqm_lock(dqm);
2100
2101 retval = wait_on_destroy_queue(dqm, q);
2102
2103 if (retval) {
2104 dqm_unlock(dqm);
2105 return retval;
2106 }
2107
2108 if (qpd->is_debug) {
2109 /*
2110 * error, currently we do not allow to destroy a queue
2111 * of a currently debugged process
2112 */
2113 retval = -EBUSY;
2114 goto failed_try_destroy_debugged_queue;
2115
2116 }
2117
2118 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2119 q->properties.type)];
2120
2121 deallocate_doorbell(qpd, q);
2122
2123 if ((q->properties.type == KFD_QUEUE_TYPE_SDMA) ||
2124 (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)) {
2125 deallocate_sdma_queue(dqm, q);
2126 pdd->sdma_past_activity_counter += sdma_val;
2127 }
2128
2129 list_del(&q->list);
2130 qpd->queue_count--;
2131 if (q->properties.is_active) {
2132 decrement_queue_count(dqm, qpd, q);
2133 if (!dqm->dev->kfd->shared_resources.enable_mes) {
2134 retval = execute_queues_cpsch(dqm,
2135 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
2136 USE_DEFAULT_GRACE_PERIOD);
2137 if (retval == -ETIME)
2138 qpd->reset_wavefronts = true;
2139 } else {
2140 retval = remove_queue_mes(dqm, q, qpd);
2141 }
2142 }
2143
2144 /*
2145 * Unconditionally decrement this counter, regardless of the queue's
2146 * type
2147 */
2148 dqm->total_queue_count--;
2149 pr_debug("Total of %d queues are accountable so far\n",
2150 dqm->total_queue_count);
2151
2152 dqm_unlock(dqm);
2153
2154 /*
2155 * Do free_mqd and raise delete event after dqm_unlock(dqm) to avoid
2156 * circular locking
2157 */
2158 kfd_dbg_ev_raise(KFD_EC_MASK(EC_DEVICE_QUEUE_DELETE),
2159 qpd->pqm->process, q->device,
2160 -1, false, NULL, 0);
2161
2162 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2163
2164 return retval;
2165
2166failed_try_destroy_debugged_queue:
2167
2168 dqm_unlock(dqm);
2169 return retval;
2170}
2171
2172/*
2173 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
2174 * stay in user mode.
2175 */
2176#define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
2177/* APE1 limit is inclusive and 64K aligned. */
2178#define APE1_LIMIT_ALIGNMENT 0xFFFF
2179
2180static bool set_cache_memory_policy(struct device_queue_manager *dqm,
2181 struct qcm_process_device *qpd,
2182 enum cache_policy default_policy,
2183 enum cache_policy alternate_policy,
2184 void __user *alternate_aperture_base,
2185 uint64_t alternate_aperture_size)
2186{
2187 bool retval = true;
2188
2189 if (!dqm->asic_ops.set_cache_memory_policy)
2190 return retval;
2191
2192 dqm_lock(dqm);
2193
2194 if (alternate_aperture_size == 0) {
2195 /* base > limit disables APE1 */
2196 qpd->sh_mem_ape1_base = 1;
2197 qpd->sh_mem_ape1_limit = 0;
2198 } else {
2199 /*
2200 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
2201 * SH_MEM_APE1_BASE[31:0], 0x0000 }
2202 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
2203 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
2204 * Verify that the base and size parameters can be
2205 * represented in this format and convert them.
2206 * Additionally restrict APE1 to user-mode addresses.
2207 */
2208
2209 uint64_t base = (uintptr_t)alternate_aperture_base;
2210 uint64_t limit = base + alternate_aperture_size - 1;
2211
2212 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
2213 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
2214 retval = false;
2215 goto out;
2216 }
2217
2218 qpd->sh_mem_ape1_base = base >> 16;
2219 qpd->sh_mem_ape1_limit = limit >> 16;
2220 }
2221
2222 retval = dqm->asic_ops.set_cache_memory_policy(
2223 dqm,
2224 qpd,
2225 default_policy,
2226 alternate_policy,
2227 alternate_aperture_base,
2228 alternate_aperture_size);
2229
2230 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
2231 program_sh_mem_settings(dqm, qpd);
2232
2233 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
2234 qpd->sh_mem_config, qpd->sh_mem_ape1_base,
2235 qpd->sh_mem_ape1_limit);
2236
2237out:
2238 dqm_unlock(dqm);
2239 return retval;
2240}
2241
2242static int process_termination_nocpsch(struct device_queue_manager *dqm,
2243 struct qcm_process_device *qpd)
2244{
2245 struct queue *q;
2246 struct device_process_node *cur, *next_dpn;
2247 int retval = 0;
2248 bool found = false;
2249
2250 dqm_lock(dqm);
2251
2252 /* Clear all user mode queues */
2253 while (!list_empty(&qpd->queues_list)) {
2254 struct mqd_manager *mqd_mgr;
2255 int ret;
2256
2257 q = list_first_entry(&qpd->queues_list, struct queue, list);
2258 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2259 q->properties.type)];
2260 ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
2261 if (ret)
2262 retval = ret;
2263 dqm_unlock(dqm);
2264 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2265 dqm_lock(dqm);
2266 }
2267
2268 /* Unregister process */
2269 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
2270 if (qpd == cur->qpd) {
2271 list_del(&cur->list);
2272 kfree(cur);
2273 dqm->processes_count--;
2274 found = true;
2275 break;
2276 }
2277 }
2278
2279 dqm_unlock(dqm);
2280
2281 /* Outside the DQM lock because under the DQM lock we can't do
2282 * reclaim or take other locks that others hold while reclaiming.
2283 */
2284 if (found)
2285 kfd_dec_compute_active(dqm->dev);
2286
2287 return retval;
2288}
2289
2290static int get_wave_state(struct device_queue_manager *dqm,
2291 struct queue *q,
2292 void __user *ctl_stack,
2293 u32 *ctl_stack_used_size,
2294 u32 *save_area_used_size)
2295{
2296 struct mqd_manager *mqd_mgr;
2297
2298 dqm_lock(dqm);
2299
2300 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
2301
2302 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE ||
2303 q->properties.is_active || !q->device->kfd->cwsr_enabled ||
2304 !mqd_mgr->get_wave_state) {
2305 dqm_unlock(dqm);
2306 return -EINVAL;
2307 }
2308
2309 dqm_unlock(dqm);
2310
2311 /*
2312 * get_wave_state is outside the dqm lock to prevent circular locking
2313 * and the queue should be protected against destruction by the process
2314 * lock.
2315 */
2316 return mqd_mgr->get_wave_state(mqd_mgr, q->mqd, &q->properties,
2317 ctl_stack, ctl_stack_used_size, save_area_used_size);
2318}
2319
2320static void get_queue_checkpoint_info(struct device_queue_manager *dqm,
2321 const struct queue *q,
2322 u32 *mqd_size,
2323 u32 *ctl_stack_size)
2324{
2325 struct mqd_manager *mqd_mgr;
2326 enum KFD_MQD_TYPE mqd_type =
2327 get_mqd_type_from_queue_type(q->properties.type);
2328
2329 dqm_lock(dqm);
2330 mqd_mgr = dqm->mqd_mgrs[mqd_type];
2331 *mqd_size = mqd_mgr->mqd_size;
2332 *ctl_stack_size = 0;
2333
2334 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info)
2335 mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size);
2336
2337 dqm_unlock(dqm);
2338}
2339
2340static int checkpoint_mqd(struct device_queue_manager *dqm,
2341 const struct queue *q,
2342 void *mqd,
2343 void *ctl_stack)
2344{
2345 struct mqd_manager *mqd_mgr;
2346 int r = 0;
2347 enum KFD_MQD_TYPE mqd_type =
2348 get_mqd_type_from_queue_type(q->properties.type);
2349
2350 dqm_lock(dqm);
2351
2352 if (q->properties.is_active || !q->device->kfd->cwsr_enabled) {
2353 r = -EINVAL;
2354 goto dqm_unlock;
2355 }
2356
2357 mqd_mgr = dqm->mqd_mgrs[mqd_type];
2358 if (!mqd_mgr->checkpoint_mqd) {
2359 r = -EOPNOTSUPP;
2360 goto dqm_unlock;
2361 }
2362
2363 mqd_mgr->checkpoint_mqd(mqd_mgr, q->mqd, mqd, ctl_stack);
2364
2365dqm_unlock:
2366 dqm_unlock(dqm);
2367 return r;
2368}
2369
2370static int process_termination_cpsch(struct device_queue_manager *dqm,
2371 struct qcm_process_device *qpd)
2372{
2373 int retval;
2374 struct queue *q;
2375 struct device *dev = dqm->dev->adev->dev;
2376 struct kernel_queue *kq, *kq_next;
2377 struct mqd_manager *mqd_mgr;
2378 struct device_process_node *cur, *next_dpn;
2379 enum kfd_unmap_queues_filter filter =
2380 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
2381 bool found = false;
2382
2383 retval = 0;
2384
2385 dqm_lock(dqm);
2386
2387 /* Clean all kernel queues */
2388 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
2389 list_del(&kq->list);
2390 decrement_queue_count(dqm, qpd, kq->queue);
2391 qpd->is_debug = false;
2392 dqm->total_queue_count--;
2393 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
2394 }
2395
2396 /* Clear all user mode queues */
2397 list_for_each_entry(q, &qpd->queues_list, list) {
2398 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
2399 deallocate_sdma_queue(dqm, q);
2400 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI)
2401 deallocate_sdma_queue(dqm, q);
2402
2403 if (q->properties.is_active) {
2404 decrement_queue_count(dqm, qpd, q);
2405
2406 if (dqm->dev->kfd->shared_resources.enable_mes) {
2407 retval = remove_queue_mes(dqm, q, qpd);
2408 if (retval)
2409 dev_err(dev, "Failed to remove queue %d\n",
2410 q->properties.queue_id);
2411 }
2412 }
2413
2414 dqm->total_queue_count--;
2415 }
2416
2417 /* Unregister process */
2418 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
2419 if (qpd == cur->qpd) {
2420 list_del(&cur->list);
2421 kfree(cur);
2422 dqm->processes_count--;
2423 found = true;
2424 break;
2425 }
2426 }
2427
2428 if (!dqm->dev->kfd->shared_resources.enable_mes)
2429 retval = execute_queues_cpsch(dqm, filter, 0, USE_DEFAULT_GRACE_PERIOD);
2430
2431 if ((!dqm->is_hws_hang) && (retval || qpd->reset_wavefronts)) {
2432 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
2433 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
2434 qpd->reset_wavefronts = false;
2435 }
2436
2437 /* Lastly, free mqd resources.
2438 * Do free_mqd() after dqm_unlock to avoid circular locking.
2439 */
2440 while (!list_empty(&qpd->queues_list)) {
2441 q = list_first_entry(&qpd->queues_list, struct queue, list);
2442 mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(
2443 q->properties.type)];
2444 list_del(&q->list);
2445 qpd->queue_count--;
2446 dqm_unlock(dqm);
2447 mqd_mgr->free_mqd(mqd_mgr, q->mqd, q->mqd_mem_obj);
2448 dqm_lock(dqm);
2449 }
2450 dqm_unlock(dqm);
2451
2452 /* Outside the DQM lock because under the DQM lock we can't do
2453 * reclaim or take other locks that others hold while reclaiming.
2454 */
2455 if (found)
2456 kfd_dec_compute_active(dqm->dev);
2457
2458 return retval;
2459}
2460
2461static int init_mqd_managers(struct device_queue_manager *dqm)
2462{
2463 int i, j;
2464 struct device *dev = dqm->dev->adev->dev;
2465 struct mqd_manager *mqd_mgr;
2466
2467 for (i = 0; i < KFD_MQD_TYPE_MAX; i++) {
2468 mqd_mgr = dqm->asic_ops.mqd_manager_init(i, dqm->dev);
2469 if (!mqd_mgr) {
2470 dev_err(dev, "mqd manager [%d] initialization failed\n", i);
2471 goto out_free;
2472 }
2473 dqm->mqd_mgrs[i] = mqd_mgr;
2474 }
2475
2476 return 0;
2477
2478out_free:
2479 for (j = 0; j < i; j++) {
2480 kfree(dqm->mqd_mgrs[j]);
2481 dqm->mqd_mgrs[j] = NULL;
2482 }
2483
2484 return -ENOMEM;
2485}
2486
2487/* Allocate one hiq mqd (HWS) and all SDMA mqd in a continuous trunk*/
2488static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm)
2489{
2490 int retval;
2491 struct kfd_node *dev = dqm->dev;
2492 struct kfd_mem_obj *mem_obj = &dqm->hiq_sdma_mqd;
2493 uint32_t size = dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size *
2494 get_num_all_sdma_engines(dqm) *
2495 dev->kfd->device_info.num_sdma_queues_per_engine +
2496 (dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size *
2497 NUM_XCC(dqm->dev->xcc_mask));
2498
2499 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size,
2500 &(mem_obj->gtt_mem), &(mem_obj->gpu_addr),
2501 (void *)&(mem_obj->cpu_ptr), false);
2502
2503 return retval;
2504}
2505
2506struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev)
2507{
2508 struct device_queue_manager *dqm;
2509
2510 pr_debug("Loading device queue manager\n");
2511
2512 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
2513 if (!dqm)
2514 return NULL;
2515
2516 switch (dev->adev->asic_type) {
2517 /* HWS is not available on Hawaii. */
2518 case CHIP_HAWAII:
2519 /* HWS depends on CWSR for timely dequeue. CWSR is not
2520 * available on Tonga.
2521 *
2522 * FIXME: This argument also applies to Kaveri.
2523 */
2524 case CHIP_TONGA:
2525 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS;
2526 break;
2527 default:
2528 dqm->sched_policy = sched_policy;
2529 break;
2530 }
2531
2532 dqm->dev = dev;
2533 switch (dqm->sched_policy) {
2534 case KFD_SCHED_POLICY_HWS:
2535 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
2536 /* initialize dqm for cp scheduling */
2537 dqm->ops.create_queue = create_queue_cpsch;
2538 dqm->ops.initialize = initialize_cpsch;
2539 dqm->ops.start = start_cpsch;
2540 dqm->ops.stop = stop_cpsch;
2541 dqm->ops.pre_reset = pre_reset;
2542 dqm->ops.destroy_queue = destroy_queue_cpsch;
2543 dqm->ops.update_queue = update_queue;
2544 dqm->ops.register_process = register_process;
2545 dqm->ops.unregister_process = unregister_process;
2546 dqm->ops.uninitialize = uninitialize;
2547 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
2548 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
2549 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
2550 dqm->ops.process_termination = process_termination_cpsch;
2551 dqm->ops.evict_process_queues = evict_process_queues_cpsch;
2552 dqm->ops.restore_process_queues = restore_process_queues_cpsch;
2553 dqm->ops.get_wave_state = get_wave_state;
2554 dqm->ops.reset_queues = reset_queues_cpsch;
2555 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info;
2556 dqm->ops.checkpoint_mqd = checkpoint_mqd;
2557 break;
2558 case KFD_SCHED_POLICY_NO_HWS:
2559 /* initialize dqm for no cp scheduling */
2560 dqm->ops.start = start_nocpsch;
2561 dqm->ops.stop = stop_nocpsch;
2562 dqm->ops.pre_reset = pre_reset;
2563 dqm->ops.create_queue = create_queue_nocpsch;
2564 dqm->ops.destroy_queue = destroy_queue_nocpsch;
2565 dqm->ops.update_queue = update_queue;
2566 dqm->ops.register_process = register_process;
2567 dqm->ops.unregister_process = unregister_process;
2568 dqm->ops.initialize = initialize_nocpsch;
2569 dqm->ops.uninitialize = uninitialize;
2570 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
2571 dqm->ops.process_termination = process_termination_nocpsch;
2572 dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
2573 dqm->ops.restore_process_queues =
2574 restore_process_queues_nocpsch;
2575 dqm->ops.get_wave_state = get_wave_state;
2576 dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info;
2577 dqm->ops.checkpoint_mqd = checkpoint_mqd;
2578 break;
2579 default:
2580 dev_err(dev->adev->dev, "Invalid scheduling policy %d\n", dqm->sched_policy);
2581 goto out_free;
2582 }
2583
2584 switch (dev->adev->asic_type) {
2585 case CHIP_KAVERI:
2586 case CHIP_HAWAII:
2587 device_queue_manager_init_cik(&dqm->asic_ops);
2588 break;
2589
2590 case CHIP_CARRIZO:
2591 case CHIP_TONGA:
2592 case CHIP_FIJI:
2593 case CHIP_POLARIS10:
2594 case CHIP_POLARIS11:
2595 case CHIP_POLARIS12:
2596 case CHIP_VEGAM:
2597 device_queue_manager_init_vi(&dqm->asic_ops);
2598 break;
2599
2600 default:
2601 if (KFD_GC_VERSION(dev) >= IP_VERSION(11, 0, 0))
2602 device_queue_manager_init_v11(&dqm->asic_ops);
2603 else if (KFD_GC_VERSION(dev) >= IP_VERSION(10, 1, 1))
2604 device_queue_manager_init_v10(&dqm->asic_ops);
2605 else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1))
2606 device_queue_manager_init_v9(&dqm->asic_ops);
2607 else {
2608 WARN(1, "Unexpected ASIC family %u",
2609 dev->adev->asic_type);
2610 goto out_free;
2611 }
2612 }
2613
2614 if (init_mqd_managers(dqm))
2615 goto out_free;
2616
2617 if (!dev->kfd->shared_resources.enable_mes && allocate_hiq_sdma_mqd(dqm)) {
2618 dev_err(dev->adev->dev, "Failed to allocate hiq sdma mqd trunk buffer\n");
2619 goto out_free;
2620 }
2621
2622 if (!dqm->ops.initialize(dqm)) {
2623 init_waitqueue_head(&dqm->destroy_wait);
2624 return dqm;
2625 }
2626
2627out_free:
2628 kfree(dqm);
2629 return NULL;
2630}
2631
2632static void deallocate_hiq_sdma_mqd(struct kfd_node *dev,
2633 struct kfd_mem_obj *mqd)
2634{
2635 WARN(!mqd, "No hiq sdma mqd trunk to free");
2636
2637 amdgpu_amdkfd_free_gtt_mem(dev->adev, mqd->gtt_mem);
2638}
2639
2640void device_queue_manager_uninit(struct device_queue_manager *dqm)
2641{
2642 dqm->ops.stop(dqm);
2643 dqm->ops.uninitialize(dqm);
2644 if (!dqm->dev->kfd->shared_resources.enable_mes)
2645 deallocate_hiq_sdma_mqd(dqm->dev, &dqm->hiq_sdma_mqd);
2646 kfree(dqm);
2647}
2648
2649int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid)
2650{
2651 struct kfd_process_device *pdd;
2652 struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
2653 int ret = 0;
2654
2655 if (!p)
2656 return -EINVAL;
2657 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
2658 pdd = kfd_get_process_device_data(dqm->dev, p);
2659 if (pdd)
2660 ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd);
2661 kfd_unref_process(p);
2662
2663 return ret;
2664}
2665
2666static void kfd_process_hw_exception(struct work_struct *work)
2667{
2668 struct device_queue_manager *dqm = container_of(work,
2669 struct device_queue_manager, hw_exception_work);
2670 amdgpu_amdkfd_gpu_reset(dqm->dev->adev);
2671}
2672
2673int reserve_debug_trap_vmid(struct device_queue_manager *dqm,
2674 struct qcm_process_device *qpd)
2675{
2676 int r;
2677 struct device *dev = dqm->dev->adev->dev;
2678 int updated_vmid_mask;
2679
2680 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
2681 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy);
2682 return -EINVAL;
2683 }
2684
2685 dqm_lock(dqm);
2686
2687 if (dqm->trap_debug_vmid != 0) {
2688 dev_err(dev, "Trap debug id already reserved\n");
2689 r = -EBUSY;
2690 goto out_unlock;
2691 }
2692
2693 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
2694 USE_DEFAULT_GRACE_PERIOD, false);
2695 if (r)
2696 goto out_unlock;
2697
2698 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap;
2699 updated_vmid_mask &= ~(1 << dqm->dev->vm_info.last_vmid_kfd);
2700
2701 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask;
2702 dqm->trap_debug_vmid = dqm->dev->vm_info.last_vmid_kfd;
2703 r = set_sched_resources(dqm);
2704 if (r)
2705 goto out_unlock;
2706
2707 r = map_queues_cpsch(dqm);
2708 if (r)
2709 goto out_unlock;
2710
2711 pr_debug("Reserved VMID for trap debug: %i\n", dqm->trap_debug_vmid);
2712
2713out_unlock:
2714 dqm_unlock(dqm);
2715 return r;
2716}
2717
2718/*
2719 * Releases vmid for the trap debugger
2720 */
2721int release_debug_trap_vmid(struct device_queue_manager *dqm,
2722 struct qcm_process_device *qpd)
2723{
2724 struct device *dev = dqm->dev->adev->dev;
2725 int r;
2726 int updated_vmid_mask;
2727 uint32_t trap_debug_vmid;
2728
2729 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
2730 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy);
2731 return -EINVAL;
2732 }
2733
2734 dqm_lock(dqm);
2735 trap_debug_vmid = dqm->trap_debug_vmid;
2736 if (dqm->trap_debug_vmid == 0) {
2737 dev_err(dev, "Trap debug id is not reserved\n");
2738 r = -EINVAL;
2739 goto out_unlock;
2740 }
2741
2742 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0,
2743 USE_DEFAULT_GRACE_PERIOD, false);
2744 if (r)
2745 goto out_unlock;
2746
2747 updated_vmid_mask = dqm->dev->kfd->shared_resources.compute_vmid_bitmap;
2748 updated_vmid_mask |= (1 << dqm->dev->vm_info.last_vmid_kfd);
2749
2750 dqm->dev->kfd->shared_resources.compute_vmid_bitmap = updated_vmid_mask;
2751 dqm->trap_debug_vmid = 0;
2752 r = set_sched_resources(dqm);
2753 if (r)
2754 goto out_unlock;
2755
2756 r = map_queues_cpsch(dqm);
2757 if (r)
2758 goto out_unlock;
2759
2760 pr_debug("Released VMID for trap debug: %i\n", trap_debug_vmid);
2761
2762out_unlock:
2763 dqm_unlock(dqm);
2764 return r;
2765}
2766
2767#define QUEUE_NOT_FOUND -1
2768/* invalidate queue operation in array */
2769static void q_array_invalidate(uint32_t num_queues, uint32_t *queue_ids)
2770{
2771 int i;
2772
2773 for (i = 0; i < num_queues; i++)
2774 queue_ids[i] |= KFD_DBG_QUEUE_INVALID_MASK;
2775}
2776
2777/* find queue index in array */
2778static int q_array_get_index(unsigned int queue_id,
2779 uint32_t num_queues,
2780 uint32_t *queue_ids)
2781{
2782 int i;
2783
2784 for (i = 0; i < num_queues; i++)
2785 if (queue_id == (queue_ids[i] & ~KFD_DBG_QUEUE_INVALID_MASK))
2786 return i;
2787
2788 return QUEUE_NOT_FOUND;
2789}
2790
2791struct copy_context_work_handler_workarea {
2792 struct work_struct copy_context_work;
2793 struct kfd_process *p;
2794};
2795
2796static void copy_context_work_handler (struct work_struct *work)
2797{
2798 struct copy_context_work_handler_workarea *workarea;
2799 struct mqd_manager *mqd_mgr;
2800 struct queue *q;
2801 struct mm_struct *mm;
2802 struct kfd_process *p;
2803 uint32_t tmp_ctl_stack_used_size, tmp_save_area_used_size;
2804 int i;
2805
2806 workarea = container_of(work,
2807 struct copy_context_work_handler_workarea,
2808 copy_context_work);
2809
2810 p = workarea->p;
2811 mm = get_task_mm(p->lead_thread);
2812
2813 if (!mm)
2814 return;
2815
2816 kthread_use_mm(mm);
2817 for (i = 0; i < p->n_pdds; i++) {
2818 struct kfd_process_device *pdd = p->pdds[i];
2819 struct device_queue_manager *dqm = pdd->dev->dqm;
2820 struct qcm_process_device *qpd = &pdd->qpd;
2821
2822 list_for_each_entry(q, &qpd->queues_list, list) {
2823 mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP];
2824
2825 /* We ignore the return value from get_wave_state
2826 * because
2827 * i) right now, it always returns 0, and
2828 * ii) if we hit an error, we would continue to the
2829 * next queue anyway.
2830 */
2831 mqd_mgr->get_wave_state(mqd_mgr,
2832 q->mqd,
2833 &q->properties,
2834 (void __user *) q->properties.ctx_save_restore_area_address,
2835 &tmp_ctl_stack_used_size,
2836 &tmp_save_area_used_size);
2837 }
2838 }
2839 kthread_unuse_mm(mm);
2840 mmput(mm);
2841}
2842
2843static uint32_t *get_queue_ids(uint32_t num_queues, uint32_t *usr_queue_id_array)
2844{
2845 size_t array_size = num_queues * sizeof(uint32_t);
2846
2847 if (!usr_queue_id_array)
2848 return NULL;
2849
2850 return memdup_user(usr_queue_id_array, array_size);
2851}
2852
2853int resume_queues(struct kfd_process *p,
2854 uint32_t num_queues,
2855 uint32_t *usr_queue_id_array)
2856{
2857 uint32_t *queue_ids = NULL;
2858 int total_resumed = 0;
2859 int i;
2860
2861 if (usr_queue_id_array) {
2862 queue_ids = get_queue_ids(num_queues, usr_queue_id_array);
2863
2864 if (IS_ERR(queue_ids))
2865 return PTR_ERR(queue_ids);
2866
2867 /* mask all queues as invalid. unmask per successful request */
2868 q_array_invalidate(num_queues, queue_ids);
2869 }
2870
2871 for (i = 0; i < p->n_pdds; i++) {
2872 struct kfd_process_device *pdd = p->pdds[i];
2873 struct device_queue_manager *dqm = pdd->dev->dqm;
2874 struct device *dev = dqm->dev->adev->dev;
2875 struct qcm_process_device *qpd = &pdd->qpd;
2876 struct queue *q;
2877 int r, per_device_resumed = 0;
2878
2879 dqm_lock(dqm);
2880
2881 /* unmask queues that resume or already resumed as valid */
2882 list_for_each_entry(q, &qpd->queues_list, list) {
2883 int q_idx = QUEUE_NOT_FOUND;
2884
2885 if (queue_ids)
2886 q_idx = q_array_get_index(
2887 q->properties.queue_id,
2888 num_queues,
2889 queue_ids);
2890
2891 if (!queue_ids || q_idx != QUEUE_NOT_FOUND) {
2892 int err = resume_single_queue(dqm, &pdd->qpd, q);
2893
2894 if (queue_ids) {
2895 if (!err) {
2896 queue_ids[q_idx] &=
2897 ~KFD_DBG_QUEUE_INVALID_MASK;
2898 } else {
2899 queue_ids[q_idx] |=
2900 KFD_DBG_QUEUE_ERROR_MASK;
2901 break;
2902 }
2903 }
2904
2905 if (dqm->dev->kfd->shared_resources.enable_mes) {
2906 wake_up_all(&dqm->destroy_wait);
2907 if (!err)
2908 total_resumed++;
2909 } else {
2910 per_device_resumed++;
2911 }
2912 }
2913 }
2914
2915 if (!per_device_resumed) {
2916 dqm_unlock(dqm);
2917 continue;
2918 }
2919
2920 r = execute_queues_cpsch(dqm,
2921 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES,
2922 0,
2923 USE_DEFAULT_GRACE_PERIOD);
2924 if (r) {
2925 dev_err(dev, "Failed to resume process queues\n");
2926 if (queue_ids) {
2927 list_for_each_entry(q, &qpd->queues_list, list) {
2928 int q_idx = q_array_get_index(
2929 q->properties.queue_id,
2930 num_queues,
2931 queue_ids);
2932
2933 /* mask queue as error on resume fail */
2934 if (q_idx != QUEUE_NOT_FOUND)
2935 queue_ids[q_idx] |=
2936 KFD_DBG_QUEUE_ERROR_MASK;
2937 }
2938 }
2939 } else {
2940 wake_up_all(&dqm->destroy_wait);
2941 total_resumed += per_device_resumed;
2942 }
2943
2944 dqm_unlock(dqm);
2945 }
2946
2947 if (queue_ids) {
2948 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids,
2949 num_queues * sizeof(uint32_t)))
2950 pr_err("copy_to_user failed on queue resume\n");
2951
2952 kfree(queue_ids);
2953 }
2954
2955 return total_resumed;
2956}
2957
2958int suspend_queues(struct kfd_process *p,
2959 uint32_t num_queues,
2960 uint32_t grace_period,
2961 uint64_t exception_clear_mask,
2962 uint32_t *usr_queue_id_array)
2963{
2964 uint32_t *queue_ids = get_queue_ids(num_queues, usr_queue_id_array);
2965 int total_suspended = 0;
2966 int i;
2967
2968 if (IS_ERR(queue_ids))
2969 return PTR_ERR(queue_ids);
2970
2971 /* mask all queues as invalid. umask on successful request */
2972 q_array_invalidate(num_queues, queue_ids);
2973
2974 for (i = 0; i < p->n_pdds; i++) {
2975 struct kfd_process_device *pdd = p->pdds[i];
2976 struct device_queue_manager *dqm = pdd->dev->dqm;
2977 struct device *dev = dqm->dev->adev->dev;
2978 struct qcm_process_device *qpd = &pdd->qpd;
2979 struct queue *q;
2980 int r, per_device_suspended = 0;
2981
2982 mutex_lock(&p->event_mutex);
2983 dqm_lock(dqm);
2984
2985 /* unmask queues that suspend or already suspended */
2986 list_for_each_entry(q, &qpd->queues_list, list) {
2987 int q_idx = q_array_get_index(q->properties.queue_id,
2988 num_queues,
2989 queue_ids);
2990
2991 if (q_idx != QUEUE_NOT_FOUND) {
2992 int err = suspend_single_queue(dqm, pdd, q);
2993 bool is_mes = dqm->dev->kfd->shared_resources.enable_mes;
2994
2995 if (!err) {
2996 queue_ids[q_idx] &= ~KFD_DBG_QUEUE_INVALID_MASK;
2997 if (exception_clear_mask && is_mes)
2998 q->properties.exception_status &=
2999 ~exception_clear_mask;
3000
3001 if (is_mes)
3002 total_suspended++;
3003 else
3004 per_device_suspended++;
3005 } else if (err != -EBUSY) {
3006 r = err;
3007 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK;
3008 break;
3009 }
3010 }
3011 }
3012
3013 if (!per_device_suspended) {
3014 dqm_unlock(dqm);
3015 mutex_unlock(&p->event_mutex);
3016 if (total_suspended)
3017 amdgpu_amdkfd_debug_mem_fence(dqm->dev->adev);
3018 continue;
3019 }
3020
3021 r = execute_queues_cpsch(dqm,
3022 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0,
3023 grace_period);
3024
3025 if (r)
3026 dev_err(dev, "Failed to suspend process queues.\n");
3027 else
3028 total_suspended += per_device_suspended;
3029
3030 list_for_each_entry(q, &qpd->queues_list, list) {
3031 int q_idx = q_array_get_index(q->properties.queue_id,
3032 num_queues, queue_ids);
3033
3034 if (q_idx == QUEUE_NOT_FOUND)
3035 continue;
3036
3037 /* mask queue as error on suspend fail */
3038 if (r)
3039 queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK;
3040 else if (exception_clear_mask)
3041 q->properties.exception_status &=
3042 ~exception_clear_mask;
3043 }
3044
3045 dqm_unlock(dqm);
3046 mutex_unlock(&p->event_mutex);
3047 amdgpu_device_flush_hdp(dqm->dev->adev, NULL);
3048 }
3049
3050 if (total_suspended) {
3051 struct copy_context_work_handler_workarea copy_context_worker;
3052
3053 INIT_WORK_ONSTACK(
3054 ©_context_worker.copy_context_work,
3055 copy_context_work_handler);
3056
3057 copy_context_worker.p = p;
3058
3059 schedule_work(©_context_worker.copy_context_work);
3060
3061
3062 flush_work(©_context_worker.copy_context_work);
3063 destroy_work_on_stack(©_context_worker.copy_context_work);
3064 }
3065
3066 if (copy_to_user((void __user *)usr_queue_id_array, queue_ids,
3067 num_queues * sizeof(uint32_t)))
3068 pr_err("copy_to_user failed on queue suspend\n");
3069
3070 kfree(queue_ids);
3071
3072 return total_suspended;
3073}
3074
3075static uint32_t set_queue_type_for_user(struct queue_properties *q_props)
3076{
3077 switch (q_props->type) {
3078 case KFD_QUEUE_TYPE_COMPUTE:
3079 return q_props->format == KFD_QUEUE_FORMAT_PM4
3080 ? KFD_IOC_QUEUE_TYPE_COMPUTE
3081 : KFD_IOC_QUEUE_TYPE_COMPUTE_AQL;
3082 case KFD_QUEUE_TYPE_SDMA:
3083 return KFD_IOC_QUEUE_TYPE_SDMA;
3084 case KFD_QUEUE_TYPE_SDMA_XGMI:
3085 return KFD_IOC_QUEUE_TYPE_SDMA_XGMI;
3086 default:
3087 WARN_ONCE(true, "queue type not recognized!");
3088 return 0xffffffff;
3089 };
3090}
3091
3092void set_queue_snapshot_entry(struct queue *q,
3093 uint64_t exception_clear_mask,
3094 struct kfd_queue_snapshot_entry *qss_entry)
3095{
3096 qss_entry->ring_base_address = q->properties.queue_address;
3097 qss_entry->write_pointer_address = (uint64_t)q->properties.write_ptr;
3098 qss_entry->read_pointer_address = (uint64_t)q->properties.read_ptr;
3099 qss_entry->ctx_save_restore_address =
3100 q->properties.ctx_save_restore_area_address;
3101 qss_entry->ctx_save_restore_area_size =
3102 q->properties.ctx_save_restore_area_size;
3103 qss_entry->exception_status = q->properties.exception_status;
3104 qss_entry->queue_id = q->properties.queue_id;
3105 qss_entry->gpu_id = q->device->id;
3106 qss_entry->ring_size = (uint32_t)q->properties.queue_size;
3107 qss_entry->queue_type = set_queue_type_for_user(&q->properties);
3108 q->properties.exception_status &= ~exception_clear_mask;
3109}
3110
3111int debug_lock_and_unmap(struct device_queue_manager *dqm)
3112{
3113 struct device *dev = dqm->dev->adev->dev;
3114 int r;
3115
3116 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
3117 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy);
3118 return -EINVAL;
3119 }
3120
3121 if (!kfd_dbg_is_per_vmid_supported(dqm->dev))
3122 return 0;
3123
3124 dqm_lock(dqm);
3125
3126 r = unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, 0, false);
3127 if (r)
3128 dqm_unlock(dqm);
3129
3130 return r;
3131}
3132
3133int debug_map_and_unlock(struct device_queue_manager *dqm)
3134{
3135 struct device *dev = dqm->dev->adev->dev;
3136 int r;
3137
3138 if (dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
3139 dev_err(dev, "Unsupported on sched_policy: %i\n", dqm->sched_policy);
3140 return -EINVAL;
3141 }
3142
3143 if (!kfd_dbg_is_per_vmid_supported(dqm->dev))
3144 return 0;
3145
3146 r = map_queues_cpsch(dqm);
3147
3148 dqm_unlock(dqm);
3149
3150 return r;
3151}
3152
3153int debug_refresh_runlist(struct device_queue_manager *dqm)
3154{
3155 int r = debug_lock_and_unmap(dqm);
3156
3157 if (r)
3158 return r;
3159
3160 return debug_map_and_unlock(dqm);
3161}
3162
3163#if defined(CONFIG_DEBUG_FS)
3164
3165static void seq_reg_dump(struct seq_file *m,
3166 uint32_t (*dump)[2], uint32_t n_regs)
3167{
3168 uint32_t i, count;
3169
3170 for (i = 0, count = 0; i < n_regs; i++) {
3171 if (count == 0 ||
3172 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
3173 seq_printf(m, "%s %08x: %08x",
3174 i ? "\n" : "",
3175 dump[i][0], dump[i][1]);
3176 count = 7;
3177 } else {
3178 seq_printf(m, " %08x", dump[i][1]);
3179 count--;
3180 }
3181 }
3182
3183 seq_puts(m, "\n");
3184}
3185
3186int dqm_debugfs_hqds(struct seq_file *m, void *data)
3187{
3188 struct device_queue_manager *dqm = data;
3189 uint32_t xcc_mask = dqm->dev->xcc_mask;
3190 uint32_t (*dump)[2], n_regs;
3191 int pipe, queue;
3192 int r = 0, xcc_id;
3193 uint32_t sdma_engine_start;
3194
3195 if (!dqm->sched_running) {
3196 seq_puts(m, " Device is stopped\n");
3197 return 0;
3198 }
3199
3200 for_each_inst(xcc_id, xcc_mask) {
3201 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev,
3202 KFD_CIK_HIQ_PIPE,
3203 KFD_CIK_HIQ_QUEUE, &dump,
3204 &n_regs, xcc_id);
3205 if (!r) {
3206 seq_printf(
3207 m,
3208 " Inst %d, HIQ on MEC %d Pipe %d Queue %d\n",
3209 xcc_id,
3210 KFD_CIK_HIQ_PIPE / get_pipes_per_mec(dqm) + 1,
3211 KFD_CIK_HIQ_PIPE % get_pipes_per_mec(dqm),
3212 KFD_CIK_HIQ_QUEUE);
3213 seq_reg_dump(m, dump, n_regs);
3214
3215 kfree(dump);
3216 }
3217
3218 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
3219 int pipe_offset = pipe * get_queues_per_pipe(dqm);
3220
3221 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
3222 if (!test_bit(pipe_offset + queue,
3223 dqm->dev->kfd->shared_resources.cp_queue_bitmap))
3224 continue;
3225
3226 r = dqm->dev->kfd2kgd->hqd_dump(dqm->dev->adev,
3227 pipe, queue,
3228 &dump, &n_regs,
3229 xcc_id);
3230 if (r)
3231 break;
3232
3233 seq_printf(m,
3234 " Inst %d, CP Pipe %d, Queue %d\n",
3235 xcc_id, pipe, queue);
3236 seq_reg_dump(m, dump, n_regs);
3237
3238 kfree(dump);
3239 }
3240 }
3241 }
3242
3243 sdma_engine_start = dqm->dev->node_id * get_num_all_sdma_engines(dqm);
3244 for (pipe = sdma_engine_start;
3245 pipe < (sdma_engine_start + get_num_all_sdma_engines(dqm));
3246 pipe++) {
3247 for (queue = 0;
3248 queue < dqm->dev->kfd->device_info.num_sdma_queues_per_engine;
3249 queue++) {
3250 r = dqm->dev->kfd2kgd->hqd_sdma_dump(
3251 dqm->dev->adev, pipe, queue, &dump, &n_regs);
3252 if (r)
3253 break;
3254
3255 seq_printf(m, " SDMA Engine %d, RLC %d\n",
3256 pipe, queue);
3257 seq_reg_dump(m, dump, n_regs);
3258
3259 kfree(dump);
3260 }
3261 }
3262
3263 return r;
3264}
3265
3266int dqm_debugfs_hang_hws(struct device_queue_manager *dqm)
3267{
3268 int r = 0;
3269
3270 dqm_lock(dqm);
3271 r = pm_debugfs_hang_hws(&dqm->packet_mgr);
3272 if (r) {
3273 dqm_unlock(dqm);
3274 return r;
3275 }
3276 dqm->active_runlist = true;
3277 r = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES,
3278 0, USE_DEFAULT_GRACE_PERIOD);
3279 dqm_unlock(dqm);
3280
3281 return r;
3282}
3283
3284#endif
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/ratelimit.h>
25#include <linux/printk.h>
26#include <linux/slab.h>
27#include <linux/list.h>
28#include <linux/types.h>
29#include <linux/bitops.h>
30#include <linux/sched.h>
31#include "kfd_priv.h"
32#include "kfd_device_queue_manager.h"
33#include "kfd_mqd_manager.h"
34#include "cik_regs.h"
35#include "kfd_kernel_queue.h"
36
37/* Size of the per-pipe EOP queue */
38#define CIK_HPD_EOP_BYTES_LOG2 11
39#define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
40
41static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
42 unsigned int pasid, unsigned int vmid);
43
44static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
45 struct queue *q,
46 struct qcm_process_device *qpd);
47
48static int execute_queues_cpsch(struct device_queue_manager *dqm,
49 enum kfd_unmap_queues_filter filter,
50 uint32_t filter_param);
51static int unmap_queues_cpsch(struct device_queue_manager *dqm,
52 enum kfd_unmap_queues_filter filter,
53 uint32_t filter_param);
54
55static int map_queues_cpsch(struct device_queue_manager *dqm);
56
57static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
58 struct queue *q,
59 struct qcm_process_device *qpd);
60
61static void deallocate_sdma_queue(struct device_queue_manager *dqm,
62 unsigned int sdma_queue_id);
63
64static inline
65enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
66{
67 if (type == KFD_QUEUE_TYPE_SDMA)
68 return KFD_MQD_TYPE_SDMA;
69 return KFD_MQD_TYPE_CP;
70}
71
72static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
73{
74 int i;
75 int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
76 + pipe * dqm->dev->shared_resources.num_queue_per_pipe;
77
78 /* queue is available for KFD usage if bit is 1 */
79 for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i)
80 if (test_bit(pipe_offset + i,
81 dqm->dev->shared_resources.queue_bitmap))
82 return true;
83 return false;
84}
85
86unsigned int get_queues_num(struct device_queue_manager *dqm)
87{
88 return bitmap_weight(dqm->dev->shared_resources.queue_bitmap,
89 KGD_MAX_QUEUES);
90}
91
92unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
93{
94 return dqm->dev->shared_resources.num_queue_per_pipe;
95}
96
97unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
98{
99 return dqm->dev->shared_resources.num_pipe_per_mec;
100}
101
102void program_sh_mem_settings(struct device_queue_manager *dqm,
103 struct qcm_process_device *qpd)
104{
105 return dqm->dev->kfd2kgd->program_sh_mem_settings(
106 dqm->dev->kgd, qpd->vmid,
107 qpd->sh_mem_config,
108 qpd->sh_mem_ape1_base,
109 qpd->sh_mem_ape1_limit,
110 qpd->sh_mem_bases);
111}
112
113static int allocate_vmid(struct device_queue_manager *dqm,
114 struct qcm_process_device *qpd,
115 struct queue *q)
116{
117 int bit, allocated_vmid;
118
119 if (dqm->vmid_bitmap == 0)
120 return -ENOMEM;
121
122 bit = ffs(dqm->vmid_bitmap) - 1;
123 dqm->vmid_bitmap &= ~(1 << bit);
124
125 allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
126 pr_debug("vmid allocation %d\n", allocated_vmid);
127 qpd->vmid = allocated_vmid;
128 q->properties.vmid = allocated_vmid;
129
130 set_pasid_vmid_mapping(dqm, q->process->pasid, q->properties.vmid);
131 program_sh_mem_settings(dqm, qpd);
132
133 /* qpd->page_table_base is set earlier when register_process()
134 * is called, i.e. when the first queue is created.
135 */
136 dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->kgd,
137 qpd->vmid,
138 qpd->page_table_base);
139 /* invalidate the VM context after pasid and vmid mapping is set up */
140 kfd_flush_tlb(qpd_to_pdd(qpd));
141
142 return 0;
143}
144
145static int flush_texture_cache_nocpsch(struct kfd_dev *kdev,
146 struct qcm_process_device *qpd)
147{
148 uint32_t len;
149
150 if (!qpd->ib_kaddr)
151 return -ENOMEM;
152
153 len = pm_create_release_mem(qpd->ib_base, (uint32_t *)qpd->ib_kaddr);
154
155 return kdev->kfd2kgd->submit_ib(kdev->kgd, KGD_ENGINE_MEC1, qpd->vmid,
156 qpd->ib_base, (uint32_t *)qpd->ib_kaddr, len);
157}
158
159static void deallocate_vmid(struct device_queue_manager *dqm,
160 struct qcm_process_device *qpd,
161 struct queue *q)
162{
163 int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
164
165 /* On GFX v7, CP doesn't flush TC at dequeue */
166 if (q->device->device_info->asic_family == CHIP_HAWAII)
167 if (flush_texture_cache_nocpsch(q->device, qpd))
168 pr_err("Failed to flush TC\n");
169
170 kfd_flush_tlb(qpd_to_pdd(qpd));
171
172 /* Release the vmid mapping */
173 set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
174
175 dqm->vmid_bitmap |= (1 << bit);
176 qpd->vmid = 0;
177 q->properties.vmid = 0;
178}
179
180static int create_queue_nocpsch(struct device_queue_manager *dqm,
181 struct queue *q,
182 struct qcm_process_device *qpd)
183{
184 int retval;
185
186 print_queue(q);
187
188 mutex_lock(&dqm->lock);
189
190 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
191 pr_warn("Can't create new usermode queue because %d queues were already created\n",
192 dqm->total_queue_count);
193 retval = -EPERM;
194 goto out_unlock;
195 }
196
197 if (list_empty(&qpd->queues_list)) {
198 retval = allocate_vmid(dqm, qpd, q);
199 if (retval)
200 goto out_unlock;
201 }
202 q->properties.vmid = qpd->vmid;
203 /*
204 * Eviction state logic: we only mark active queues as evicted
205 * to avoid the overhead of restoring inactive queues later
206 */
207 if (qpd->evicted)
208 q->properties.is_evicted = (q->properties.queue_size > 0 &&
209 q->properties.queue_percent > 0 &&
210 q->properties.queue_address != 0);
211
212 q->properties.tba_addr = qpd->tba_addr;
213 q->properties.tma_addr = qpd->tma_addr;
214
215 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
216 retval = create_compute_queue_nocpsch(dqm, q, qpd);
217 else if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
218 retval = create_sdma_queue_nocpsch(dqm, q, qpd);
219 else
220 retval = -EINVAL;
221
222 if (retval) {
223 if (list_empty(&qpd->queues_list))
224 deallocate_vmid(dqm, qpd, q);
225 goto out_unlock;
226 }
227
228 list_add(&q->list, &qpd->queues_list);
229 qpd->queue_count++;
230 if (q->properties.is_active)
231 dqm->queue_count++;
232
233 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
234 dqm->sdma_queue_count++;
235
236 /*
237 * Unconditionally increment this counter, regardless of the queue's
238 * type or whether the queue is active.
239 */
240 dqm->total_queue_count++;
241 pr_debug("Total of %d queues are accountable so far\n",
242 dqm->total_queue_count);
243
244out_unlock:
245 mutex_unlock(&dqm->lock);
246 return retval;
247}
248
249static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
250{
251 bool set;
252 int pipe, bit, i;
253
254 set = false;
255
256 for (pipe = dqm->next_pipe_to_allocate, i = 0;
257 i < get_pipes_per_mec(dqm);
258 pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
259
260 if (!is_pipe_enabled(dqm, 0, pipe))
261 continue;
262
263 if (dqm->allocated_queues[pipe] != 0) {
264 bit = ffs(dqm->allocated_queues[pipe]) - 1;
265 dqm->allocated_queues[pipe] &= ~(1 << bit);
266 q->pipe = pipe;
267 q->queue = bit;
268 set = true;
269 break;
270 }
271 }
272
273 if (!set)
274 return -EBUSY;
275
276 pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
277 /* horizontal hqd allocation */
278 dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
279
280 return 0;
281}
282
283static inline void deallocate_hqd(struct device_queue_manager *dqm,
284 struct queue *q)
285{
286 dqm->allocated_queues[q->pipe] |= (1 << q->queue);
287}
288
289static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
290 struct queue *q,
291 struct qcm_process_device *qpd)
292{
293 int retval;
294 struct mqd_manager *mqd;
295
296 mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE);
297 if (!mqd)
298 return -ENOMEM;
299
300 retval = allocate_hqd(dqm, q);
301 if (retval)
302 return retval;
303
304 retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
305 &q->gart_mqd_addr, &q->properties);
306 if (retval)
307 goto out_deallocate_hqd;
308
309 pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
310 q->pipe, q->queue);
311
312 dqm->dev->kfd2kgd->set_scratch_backing_va(
313 dqm->dev->kgd, qpd->sh_hidden_private_base, qpd->vmid);
314
315 if (!q->properties.is_active)
316 return 0;
317
318 retval = mqd->load_mqd(mqd, q->mqd, q->pipe, q->queue, &q->properties,
319 q->process->mm);
320 if (retval)
321 goto out_uninit_mqd;
322
323 return 0;
324
325out_uninit_mqd:
326 mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
327out_deallocate_hqd:
328 deallocate_hqd(dqm, q);
329
330 return retval;
331}
332
333/* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
334 * to avoid asynchronized access
335 */
336static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
337 struct qcm_process_device *qpd,
338 struct queue *q)
339{
340 int retval;
341 struct mqd_manager *mqd;
342
343 mqd = dqm->ops.get_mqd_manager(dqm,
344 get_mqd_type_from_queue_type(q->properties.type));
345 if (!mqd)
346 return -ENOMEM;
347
348 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
349 deallocate_hqd(dqm, q);
350 } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
351 dqm->sdma_queue_count--;
352 deallocate_sdma_queue(dqm, q->sdma_id);
353 } else {
354 pr_debug("q->properties.type %d is invalid\n",
355 q->properties.type);
356 return -EINVAL;
357 }
358 dqm->total_queue_count--;
359
360 retval = mqd->destroy_mqd(mqd, q->mqd,
361 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
362 KFD_UNMAP_LATENCY_MS,
363 q->pipe, q->queue);
364 if (retval == -ETIME)
365 qpd->reset_wavefronts = true;
366
367 mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
368
369 list_del(&q->list);
370 if (list_empty(&qpd->queues_list)) {
371 if (qpd->reset_wavefronts) {
372 pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
373 dqm->dev);
374 /* dbgdev_wave_reset_wavefronts has to be called before
375 * deallocate_vmid(), i.e. when vmid is still in use.
376 */
377 dbgdev_wave_reset_wavefronts(dqm->dev,
378 qpd->pqm->process);
379 qpd->reset_wavefronts = false;
380 }
381
382 deallocate_vmid(dqm, qpd, q);
383 }
384 qpd->queue_count--;
385 if (q->properties.is_active)
386 dqm->queue_count--;
387
388 return retval;
389}
390
391static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
392 struct qcm_process_device *qpd,
393 struct queue *q)
394{
395 int retval;
396
397 mutex_lock(&dqm->lock);
398 retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
399 mutex_unlock(&dqm->lock);
400
401 return retval;
402}
403
404static int update_queue(struct device_queue_manager *dqm, struct queue *q)
405{
406 int retval;
407 struct mqd_manager *mqd;
408 struct kfd_process_device *pdd;
409 bool prev_active = false;
410
411 mutex_lock(&dqm->lock);
412 pdd = kfd_get_process_device_data(q->device, q->process);
413 if (!pdd) {
414 retval = -ENODEV;
415 goto out_unlock;
416 }
417 mqd = dqm->ops.get_mqd_manager(dqm,
418 get_mqd_type_from_queue_type(q->properties.type));
419 if (!mqd) {
420 retval = -ENOMEM;
421 goto out_unlock;
422 }
423 /*
424 * Eviction state logic: we only mark active queues as evicted
425 * to avoid the overhead of restoring inactive queues later
426 */
427 if (pdd->qpd.evicted)
428 q->properties.is_evicted = (q->properties.queue_size > 0 &&
429 q->properties.queue_percent > 0 &&
430 q->properties.queue_address != 0);
431
432 /* Save previous activity state for counters */
433 prev_active = q->properties.is_active;
434
435 /* Make sure the queue is unmapped before updating the MQD */
436 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
437 retval = unmap_queues_cpsch(dqm,
438 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
439 if (retval) {
440 pr_err("unmap queue failed\n");
441 goto out_unlock;
442 }
443 } else if (prev_active &&
444 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
445 q->properties.type == KFD_QUEUE_TYPE_SDMA)) {
446 retval = mqd->destroy_mqd(mqd, q->mqd,
447 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
448 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
449 if (retval) {
450 pr_err("destroy mqd failed\n");
451 goto out_unlock;
452 }
453 }
454
455 retval = mqd->update_mqd(mqd, q->mqd, &q->properties);
456
457 /*
458 * check active state vs. the previous state and modify
459 * counter accordingly. map_queues_cpsch uses the
460 * dqm->queue_count to determine whether a new runlist must be
461 * uploaded.
462 */
463 if (q->properties.is_active && !prev_active)
464 dqm->queue_count++;
465 else if (!q->properties.is_active && prev_active)
466 dqm->queue_count--;
467
468 if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS)
469 retval = map_queues_cpsch(dqm);
470 else if (q->properties.is_active &&
471 (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
472 q->properties.type == KFD_QUEUE_TYPE_SDMA))
473 retval = mqd->load_mqd(mqd, q->mqd, q->pipe, q->queue,
474 &q->properties, q->process->mm);
475
476out_unlock:
477 mutex_unlock(&dqm->lock);
478 return retval;
479}
480
481static struct mqd_manager *get_mqd_manager(
482 struct device_queue_manager *dqm, enum KFD_MQD_TYPE type)
483{
484 struct mqd_manager *mqd;
485
486 if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
487 return NULL;
488
489 pr_debug("mqd type %d\n", type);
490
491 mqd = dqm->mqds[type];
492 if (!mqd) {
493 mqd = mqd_manager_init(type, dqm->dev);
494 if (!mqd)
495 pr_err("mqd manager is NULL");
496 dqm->mqds[type] = mqd;
497 }
498
499 return mqd;
500}
501
502static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
503 struct qcm_process_device *qpd)
504{
505 struct queue *q;
506 struct mqd_manager *mqd;
507 struct kfd_process_device *pdd;
508 int retval = 0;
509
510 mutex_lock(&dqm->lock);
511 if (qpd->evicted++ > 0) /* already evicted, do nothing */
512 goto out;
513
514 pdd = qpd_to_pdd(qpd);
515 pr_info_ratelimited("Evicting PASID %u queues\n",
516 pdd->process->pasid);
517
518 /* unactivate all active queues on the qpd */
519 list_for_each_entry(q, &qpd->queues_list, list) {
520 if (!q->properties.is_active)
521 continue;
522 mqd = dqm->ops.get_mqd_manager(dqm,
523 get_mqd_type_from_queue_type(q->properties.type));
524 if (!mqd) { /* should not be here */
525 pr_err("Cannot evict queue, mqd mgr is NULL\n");
526 retval = -ENOMEM;
527 goto out;
528 }
529 q->properties.is_evicted = true;
530 q->properties.is_active = false;
531 retval = mqd->destroy_mqd(mqd, q->mqd,
532 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
533 KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
534 if (retval)
535 goto out;
536 dqm->queue_count--;
537 }
538
539out:
540 mutex_unlock(&dqm->lock);
541 return retval;
542}
543
544static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
545 struct qcm_process_device *qpd)
546{
547 struct queue *q;
548 struct kfd_process_device *pdd;
549 int retval = 0;
550
551 mutex_lock(&dqm->lock);
552 if (qpd->evicted++ > 0) /* already evicted, do nothing */
553 goto out;
554
555 pdd = qpd_to_pdd(qpd);
556 pr_info_ratelimited("Evicting PASID %u queues\n",
557 pdd->process->pasid);
558
559 /* unactivate all active queues on the qpd */
560 list_for_each_entry(q, &qpd->queues_list, list) {
561 if (!q->properties.is_active)
562 continue;
563 q->properties.is_evicted = true;
564 q->properties.is_active = false;
565 dqm->queue_count--;
566 }
567 retval = execute_queues_cpsch(dqm,
568 qpd->is_debug ?
569 KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
570 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
571
572out:
573 mutex_unlock(&dqm->lock);
574 return retval;
575}
576
577static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
578 struct qcm_process_device *qpd)
579{
580 struct queue *q;
581 struct mqd_manager *mqd;
582 struct kfd_process_device *pdd;
583 uint32_t pd_base;
584 int retval = 0;
585
586 pdd = qpd_to_pdd(qpd);
587 /* Retrieve PD base */
588 pd_base = dqm->dev->kfd2kgd->get_process_page_dir(pdd->vm);
589
590 mutex_lock(&dqm->lock);
591 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
592 goto out;
593 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
594 qpd->evicted--;
595 goto out;
596 }
597
598 pr_info_ratelimited("Restoring PASID %u queues\n",
599 pdd->process->pasid);
600
601 /* Update PD Base in QPD */
602 qpd->page_table_base = pd_base;
603 pr_debug("Updated PD address to 0x%08x\n", pd_base);
604
605 if (!list_empty(&qpd->queues_list)) {
606 dqm->dev->kfd2kgd->set_vm_context_page_table_base(
607 dqm->dev->kgd,
608 qpd->vmid,
609 qpd->page_table_base);
610 kfd_flush_tlb(pdd);
611 }
612
613 /* activate all active queues on the qpd */
614 list_for_each_entry(q, &qpd->queues_list, list) {
615 if (!q->properties.is_evicted)
616 continue;
617 mqd = dqm->ops.get_mqd_manager(dqm,
618 get_mqd_type_from_queue_type(q->properties.type));
619 if (!mqd) { /* should not be here */
620 pr_err("Cannot restore queue, mqd mgr is NULL\n");
621 retval = -ENOMEM;
622 goto out;
623 }
624 q->properties.is_evicted = false;
625 q->properties.is_active = true;
626 retval = mqd->load_mqd(mqd, q->mqd, q->pipe,
627 q->queue, &q->properties,
628 q->process->mm);
629 if (retval)
630 goto out;
631 dqm->queue_count++;
632 }
633 qpd->evicted = 0;
634out:
635 mutex_unlock(&dqm->lock);
636 return retval;
637}
638
639static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
640 struct qcm_process_device *qpd)
641{
642 struct queue *q;
643 struct kfd_process_device *pdd;
644 uint32_t pd_base;
645 int retval = 0;
646
647 pdd = qpd_to_pdd(qpd);
648 /* Retrieve PD base */
649 pd_base = dqm->dev->kfd2kgd->get_process_page_dir(pdd->vm);
650
651 mutex_lock(&dqm->lock);
652 if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
653 goto out;
654 if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
655 qpd->evicted--;
656 goto out;
657 }
658
659 pr_info_ratelimited("Restoring PASID %u queues\n",
660 pdd->process->pasid);
661
662 /* Update PD Base in QPD */
663 qpd->page_table_base = pd_base;
664 pr_debug("Updated PD address to 0x%08x\n", pd_base);
665
666 /* activate all active queues on the qpd */
667 list_for_each_entry(q, &qpd->queues_list, list) {
668 if (!q->properties.is_evicted)
669 continue;
670 q->properties.is_evicted = false;
671 q->properties.is_active = true;
672 dqm->queue_count++;
673 }
674 retval = execute_queues_cpsch(dqm,
675 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
676 if (!retval)
677 qpd->evicted = 0;
678out:
679 mutex_unlock(&dqm->lock);
680 return retval;
681}
682
683static int register_process(struct device_queue_manager *dqm,
684 struct qcm_process_device *qpd)
685{
686 struct device_process_node *n;
687 struct kfd_process_device *pdd;
688 uint32_t pd_base;
689 int retval;
690
691 n = kzalloc(sizeof(*n), GFP_KERNEL);
692 if (!n)
693 return -ENOMEM;
694
695 n->qpd = qpd;
696
697 pdd = qpd_to_pdd(qpd);
698 /* Retrieve PD base */
699 pd_base = dqm->dev->kfd2kgd->get_process_page_dir(pdd->vm);
700
701 mutex_lock(&dqm->lock);
702 list_add(&n->list, &dqm->queues);
703
704 /* Update PD Base in QPD */
705 qpd->page_table_base = pd_base;
706
707 retval = dqm->asic_ops.update_qpd(dqm, qpd);
708
709 dqm->processes_count++;
710
711 mutex_unlock(&dqm->lock);
712
713 return retval;
714}
715
716static int unregister_process(struct device_queue_manager *dqm,
717 struct qcm_process_device *qpd)
718{
719 int retval;
720 struct device_process_node *cur, *next;
721
722 pr_debug("qpd->queues_list is %s\n",
723 list_empty(&qpd->queues_list) ? "empty" : "not empty");
724
725 retval = 0;
726 mutex_lock(&dqm->lock);
727
728 list_for_each_entry_safe(cur, next, &dqm->queues, list) {
729 if (qpd == cur->qpd) {
730 list_del(&cur->list);
731 kfree(cur);
732 dqm->processes_count--;
733 goto out;
734 }
735 }
736 /* qpd not found in dqm list */
737 retval = 1;
738out:
739 mutex_unlock(&dqm->lock);
740 return retval;
741}
742
743static int
744set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid,
745 unsigned int vmid)
746{
747 uint32_t pasid_mapping;
748
749 pasid_mapping = (pasid == 0) ? 0 :
750 (uint32_t)pasid |
751 ATC_VMID_PASID_MAPPING_VALID;
752
753 return dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
754 dqm->dev->kgd, pasid_mapping,
755 vmid);
756}
757
758static void init_interrupts(struct device_queue_manager *dqm)
759{
760 unsigned int i;
761
762 for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++)
763 if (is_pipe_enabled(dqm, 0, i))
764 dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i);
765}
766
767static int initialize_nocpsch(struct device_queue_manager *dqm)
768{
769 int pipe, queue;
770
771 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
772
773 dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
774 sizeof(unsigned int), GFP_KERNEL);
775 if (!dqm->allocated_queues)
776 return -ENOMEM;
777
778 mutex_init(&dqm->lock);
779 INIT_LIST_HEAD(&dqm->queues);
780 dqm->queue_count = dqm->next_pipe_to_allocate = 0;
781 dqm->sdma_queue_count = 0;
782
783 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
784 int pipe_offset = pipe * get_queues_per_pipe(dqm);
785
786 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
787 if (test_bit(pipe_offset + queue,
788 dqm->dev->shared_resources.queue_bitmap))
789 dqm->allocated_queues[pipe] |= 1 << queue;
790 }
791
792 dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
793 dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
794
795 return 0;
796}
797
798static void uninitialize(struct device_queue_manager *dqm)
799{
800 int i;
801
802 WARN_ON(dqm->queue_count > 0 || dqm->processes_count > 0);
803
804 kfree(dqm->allocated_queues);
805 for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
806 kfree(dqm->mqds[i]);
807 mutex_destroy(&dqm->lock);
808 kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem);
809}
810
811static int start_nocpsch(struct device_queue_manager *dqm)
812{
813 init_interrupts(dqm);
814 return pm_init(&dqm->packets, dqm);
815}
816
817static int stop_nocpsch(struct device_queue_manager *dqm)
818{
819 pm_uninit(&dqm->packets);
820 return 0;
821}
822
823static int allocate_sdma_queue(struct device_queue_manager *dqm,
824 unsigned int *sdma_queue_id)
825{
826 int bit;
827
828 if (dqm->sdma_bitmap == 0)
829 return -ENOMEM;
830
831 bit = ffs(dqm->sdma_bitmap) - 1;
832 dqm->sdma_bitmap &= ~(1 << bit);
833 *sdma_queue_id = bit;
834
835 return 0;
836}
837
838static void deallocate_sdma_queue(struct device_queue_manager *dqm,
839 unsigned int sdma_queue_id)
840{
841 if (sdma_queue_id >= CIK_SDMA_QUEUES)
842 return;
843 dqm->sdma_bitmap |= (1 << sdma_queue_id);
844}
845
846static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
847 struct queue *q,
848 struct qcm_process_device *qpd)
849{
850 struct mqd_manager *mqd;
851 int retval;
852
853 mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_SDMA);
854 if (!mqd)
855 return -ENOMEM;
856
857 retval = allocate_sdma_queue(dqm, &q->sdma_id);
858 if (retval)
859 return retval;
860
861 q->properties.sdma_queue_id = q->sdma_id / CIK_SDMA_QUEUES_PER_ENGINE;
862 q->properties.sdma_engine_id = q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE;
863
864 pr_debug("SDMA id is: %d\n", q->sdma_id);
865 pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
866 pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
867
868 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
869 retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
870 &q->gart_mqd_addr, &q->properties);
871 if (retval)
872 goto out_deallocate_sdma_queue;
873
874 retval = mqd->load_mqd(mqd, q->mqd, 0, 0, &q->properties, NULL);
875 if (retval)
876 goto out_uninit_mqd;
877
878 return 0;
879
880out_uninit_mqd:
881 mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
882out_deallocate_sdma_queue:
883 deallocate_sdma_queue(dqm, q->sdma_id);
884
885 return retval;
886}
887
888/*
889 * Device Queue Manager implementation for cp scheduler
890 */
891
892static int set_sched_resources(struct device_queue_manager *dqm)
893{
894 int i, mec;
895 struct scheduling_resources res;
896
897 res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
898
899 res.queue_mask = 0;
900 for (i = 0; i < KGD_MAX_QUEUES; ++i) {
901 mec = (i / dqm->dev->shared_resources.num_queue_per_pipe)
902 / dqm->dev->shared_resources.num_pipe_per_mec;
903
904 if (!test_bit(i, dqm->dev->shared_resources.queue_bitmap))
905 continue;
906
907 /* only acquire queues from the first MEC */
908 if (mec > 0)
909 continue;
910
911 /* This situation may be hit in the future if a new HW
912 * generation exposes more than 64 queues. If so, the
913 * definition of res.queue_mask needs updating
914 */
915 if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
916 pr_err("Invalid queue enabled by amdgpu: %d\n", i);
917 break;
918 }
919
920 res.queue_mask |= (1ull << i);
921 }
922 res.gws_mask = res.oac_mask = res.gds_heap_base =
923 res.gds_heap_size = 0;
924
925 pr_debug("Scheduling resources:\n"
926 "vmid mask: 0x%8X\n"
927 "queue mask: 0x%8llX\n",
928 res.vmid_mask, res.queue_mask);
929
930 return pm_send_set_resources(&dqm->packets, &res);
931}
932
933static int initialize_cpsch(struct device_queue_manager *dqm)
934{
935 pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
936
937 mutex_init(&dqm->lock);
938 INIT_LIST_HEAD(&dqm->queues);
939 dqm->queue_count = dqm->processes_count = 0;
940 dqm->sdma_queue_count = 0;
941 dqm->active_runlist = false;
942 dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
943
944 return 0;
945}
946
947static int start_cpsch(struct device_queue_manager *dqm)
948{
949 int retval;
950
951 retval = 0;
952
953 retval = pm_init(&dqm->packets, dqm);
954 if (retval)
955 goto fail_packet_manager_init;
956
957 retval = set_sched_resources(dqm);
958 if (retval)
959 goto fail_set_sched_resources;
960
961 pr_debug("Allocating fence memory\n");
962
963 /* allocate fence memory on the gart */
964 retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
965 &dqm->fence_mem);
966
967 if (retval)
968 goto fail_allocate_vidmem;
969
970 dqm->fence_addr = dqm->fence_mem->cpu_ptr;
971 dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
972
973 init_interrupts(dqm);
974
975 mutex_lock(&dqm->lock);
976 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
977 mutex_unlock(&dqm->lock);
978
979 return 0;
980fail_allocate_vidmem:
981fail_set_sched_resources:
982 pm_uninit(&dqm->packets);
983fail_packet_manager_init:
984 return retval;
985}
986
987static int stop_cpsch(struct device_queue_manager *dqm)
988{
989 mutex_lock(&dqm->lock);
990 unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
991 mutex_unlock(&dqm->lock);
992
993 kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
994 pm_uninit(&dqm->packets);
995
996 return 0;
997}
998
999static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
1000 struct kernel_queue *kq,
1001 struct qcm_process_device *qpd)
1002{
1003 mutex_lock(&dqm->lock);
1004 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1005 pr_warn("Can't create new kernel queue because %d queues were already created\n",
1006 dqm->total_queue_count);
1007 mutex_unlock(&dqm->lock);
1008 return -EPERM;
1009 }
1010
1011 /*
1012 * Unconditionally increment this counter, regardless of the queue's
1013 * type or whether the queue is active.
1014 */
1015 dqm->total_queue_count++;
1016 pr_debug("Total of %d queues are accountable so far\n",
1017 dqm->total_queue_count);
1018
1019 list_add(&kq->list, &qpd->priv_queue_list);
1020 dqm->queue_count++;
1021 qpd->is_debug = true;
1022 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1023 mutex_unlock(&dqm->lock);
1024
1025 return 0;
1026}
1027
1028static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
1029 struct kernel_queue *kq,
1030 struct qcm_process_device *qpd)
1031{
1032 mutex_lock(&dqm->lock);
1033 list_del(&kq->list);
1034 dqm->queue_count--;
1035 qpd->is_debug = false;
1036 execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
1037 /*
1038 * Unconditionally decrement this counter, regardless of the queue's
1039 * type.
1040 */
1041 dqm->total_queue_count--;
1042 pr_debug("Total of %d queues are accountable so far\n",
1043 dqm->total_queue_count);
1044 mutex_unlock(&dqm->lock);
1045}
1046
1047static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
1048 struct qcm_process_device *qpd)
1049{
1050 int retval;
1051 struct mqd_manager *mqd;
1052
1053 retval = 0;
1054
1055 mutex_lock(&dqm->lock);
1056
1057 if (dqm->total_queue_count >= max_num_of_queues_per_device) {
1058 pr_warn("Can't create new usermode queue because %d queues were already created\n",
1059 dqm->total_queue_count);
1060 retval = -EPERM;
1061 goto out_unlock;
1062 }
1063
1064 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1065 retval = allocate_sdma_queue(dqm, &q->sdma_id);
1066 if (retval)
1067 goto out_unlock;
1068 q->properties.sdma_queue_id =
1069 q->sdma_id / CIK_SDMA_QUEUES_PER_ENGINE;
1070 q->properties.sdma_engine_id =
1071 q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE;
1072 }
1073 mqd = dqm->ops.get_mqd_manager(dqm,
1074 get_mqd_type_from_queue_type(q->properties.type));
1075
1076 if (!mqd) {
1077 retval = -ENOMEM;
1078 goto out_deallocate_sdma_queue;
1079 }
1080 /*
1081 * Eviction state logic: we only mark active queues as evicted
1082 * to avoid the overhead of restoring inactive queues later
1083 */
1084 if (qpd->evicted)
1085 q->properties.is_evicted = (q->properties.queue_size > 0 &&
1086 q->properties.queue_percent > 0 &&
1087 q->properties.queue_address != 0);
1088
1089 dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
1090
1091 q->properties.tba_addr = qpd->tba_addr;
1092 q->properties.tma_addr = qpd->tma_addr;
1093 retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
1094 &q->gart_mqd_addr, &q->properties);
1095 if (retval)
1096 goto out_deallocate_sdma_queue;
1097
1098 list_add(&q->list, &qpd->queues_list);
1099 qpd->queue_count++;
1100 if (q->properties.is_active) {
1101 dqm->queue_count++;
1102 retval = execute_queues_cpsch(dqm,
1103 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1104 }
1105
1106 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
1107 dqm->sdma_queue_count++;
1108 /*
1109 * Unconditionally increment this counter, regardless of the queue's
1110 * type or whether the queue is active.
1111 */
1112 dqm->total_queue_count++;
1113
1114 pr_debug("Total of %d queues are accountable so far\n",
1115 dqm->total_queue_count);
1116
1117 mutex_unlock(&dqm->lock);
1118 return retval;
1119
1120out_deallocate_sdma_queue:
1121 if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
1122 deallocate_sdma_queue(dqm, q->sdma_id);
1123out_unlock:
1124 mutex_unlock(&dqm->lock);
1125 return retval;
1126}
1127
1128int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
1129 unsigned int fence_value,
1130 unsigned int timeout_ms)
1131{
1132 unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
1133
1134 while (*fence_addr != fence_value) {
1135 if (time_after(jiffies, end_jiffies)) {
1136 pr_err("qcm fence wait loop timeout expired\n");
1137 return -ETIME;
1138 }
1139 schedule();
1140 }
1141
1142 return 0;
1143}
1144
1145static int unmap_sdma_queues(struct device_queue_manager *dqm,
1146 unsigned int sdma_engine)
1147{
1148 return pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_SDMA,
1149 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false,
1150 sdma_engine);
1151}
1152
1153/* dqm->lock mutex has to be locked before calling this function */
1154static int map_queues_cpsch(struct device_queue_manager *dqm)
1155{
1156 int retval;
1157
1158 if (dqm->queue_count <= 0 || dqm->processes_count <= 0)
1159 return 0;
1160
1161 if (dqm->active_runlist)
1162 return 0;
1163
1164 retval = pm_send_runlist(&dqm->packets, &dqm->queues);
1165 if (retval) {
1166 pr_err("failed to execute runlist\n");
1167 return retval;
1168 }
1169 dqm->active_runlist = true;
1170
1171 return retval;
1172}
1173
1174/* dqm->lock mutex has to be locked before calling this function */
1175static int unmap_queues_cpsch(struct device_queue_manager *dqm,
1176 enum kfd_unmap_queues_filter filter,
1177 uint32_t filter_param)
1178{
1179 int retval = 0;
1180
1181 if (!dqm->active_runlist)
1182 return retval;
1183
1184 pr_debug("Before destroying queues, sdma queue count is : %u\n",
1185 dqm->sdma_queue_count);
1186
1187 if (dqm->sdma_queue_count > 0) {
1188 unmap_sdma_queues(dqm, 0);
1189 unmap_sdma_queues(dqm, 1);
1190 }
1191
1192 retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE,
1193 filter, filter_param, false, 0);
1194 if (retval)
1195 return retval;
1196
1197 *dqm->fence_addr = KFD_FENCE_INIT;
1198 pm_send_query_status(&dqm->packets, dqm->fence_gpu_addr,
1199 KFD_FENCE_COMPLETED);
1200 /* should be timed out */
1201 retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
1202 QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS);
1203 if (retval)
1204 return retval;
1205
1206 pm_release_ib(&dqm->packets);
1207 dqm->active_runlist = false;
1208
1209 return retval;
1210}
1211
1212/* dqm->lock mutex has to be locked before calling this function */
1213static int execute_queues_cpsch(struct device_queue_manager *dqm,
1214 enum kfd_unmap_queues_filter filter,
1215 uint32_t filter_param)
1216{
1217 int retval;
1218
1219 retval = unmap_queues_cpsch(dqm, filter, filter_param);
1220 if (retval) {
1221 pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
1222 return retval;
1223 }
1224
1225 return map_queues_cpsch(dqm);
1226}
1227
1228static int destroy_queue_cpsch(struct device_queue_manager *dqm,
1229 struct qcm_process_device *qpd,
1230 struct queue *q)
1231{
1232 int retval;
1233 struct mqd_manager *mqd;
1234 bool preempt_all_queues;
1235
1236 preempt_all_queues = false;
1237
1238 retval = 0;
1239
1240 /* remove queue from list to prevent rescheduling after preemption */
1241 mutex_lock(&dqm->lock);
1242
1243 if (qpd->is_debug) {
1244 /*
1245 * error, currently we do not allow to destroy a queue
1246 * of a currently debugged process
1247 */
1248 retval = -EBUSY;
1249 goto failed_try_destroy_debugged_queue;
1250
1251 }
1252
1253 mqd = dqm->ops.get_mqd_manager(dqm,
1254 get_mqd_type_from_queue_type(q->properties.type));
1255 if (!mqd) {
1256 retval = -ENOMEM;
1257 goto failed;
1258 }
1259
1260 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1261 dqm->sdma_queue_count--;
1262 deallocate_sdma_queue(dqm, q->sdma_id);
1263 }
1264
1265 list_del(&q->list);
1266 qpd->queue_count--;
1267 if (q->properties.is_active) {
1268 dqm->queue_count--;
1269 retval = execute_queues_cpsch(dqm,
1270 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
1271 if (retval == -ETIME)
1272 qpd->reset_wavefronts = true;
1273 }
1274
1275 mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
1276
1277 /*
1278 * Unconditionally decrement this counter, regardless of the queue's
1279 * type
1280 */
1281 dqm->total_queue_count--;
1282 pr_debug("Total of %d queues are accountable so far\n",
1283 dqm->total_queue_count);
1284
1285 mutex_unlock(&dqm->lock);
1286
1287 return retval;
1288
1289failed:
1290failed_try_destroy_debugged_queue:
1291
1292 mutex_unlock(&dqm->lock);
1293 return retval;
1294}
1295
1296/*
1297 * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
1298 * stay in user mode.
1299 */
1300#define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
1301/* APE1 limit is inclusive and 64K aligned. */
1302#define APE1_LIMIT_ALIGNMENT 0xFFFF
1303
1304static bool set_cache_memory_policy(struct device_queue_manager *dqm,
1305 struct qcm_process_device *qpd,
1306 enum cache_policy default_policy,
1307 enum cache_policy alternate_policy,
1308 void __user *alternate_aperture_base,
1309 uint64_t alternate_aperture_size)
1310{
1311 bool retval;
1312
1313 mutex_lock(&dqm->lock);
1314
1315 if (alternate_aperture_size == 0) {
1316 /* base > limit disables APE1 */
1317 qpd->sh_mem_ape1_base = 1;
1318 qpd->sh_mem_ape1_limit = 0;
1319 } else {
1320 /*
1321 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
1322 * SH_MEM_APE1_BASE[31:0], 0x0000 }
1323 * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
1324 * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
1325 * Verify that the base and size parameters can be
1326 * represented in this format and convert them.
1327 * Additionally restrict APE1 to user-mode addresses.
1328 */
1329
1330 uint64_t base = (uintptr_t)alternate_aperture_base;
1331 uint64_t limit = base + alternate_aperture_size - 1;
1332
1333 if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
1334 (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
1335 retval = false;
1336 goto out;
1337 }
1338
1339 qpd->sh_mem_ape1_base = base >> 16;
1340 qpd->sh_mem_ape1_limit = limit >> 16;
1341 }
1342
1343 retval = dqm->asic_ops.set_cache_memory_policy(
1344 dqm,
1345 qpd,
1346 default_policy,
1347 alternate_policy,
1348 alternate_aperture_base,
1349 alternate_aperture_size);
1350
1351 if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
1352 program_sh_mem_settings(dqm, qpd);
1353
1354 pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
1355 qpd->sh_mem_config, qpd->sh_mem_ape1_base,
1356 qpd->sh_mem_ape1_limit);
1357
1358out:
1359 mutex_unlock(&dqm->lock);
1360 return retval;
1361}
1362
1363static int set_trap_handler(struct device_queue_manager *dqm,
1364 struct qcm_process_device *qpd,
1365 uint64_t tba_addr,
1366 uint64_t tma_addr)
1367{
1368 uint64_t *tma;
1369
1370 if (dqm->dev->cwsr_enabled) {
1371 /* Jump from CWSR trap handler to user trap */
1372 tma = (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET);
1373 tma[0] = tba_addr;
1374 tma[1] = tma_addr;
1375 } else {
1376 qpd->tba_addr = tba_addr;
1377 qpd->tma_addr = tma_addr;
1378 }
1379
1380 return 0;
1381}
1382
1383static int process_termination_nocpsch(struct device_queue_manager *dqm,
1384 struct qcm_process_device *qpd)
1385{
1386 struct queue *q, *next;
1387 struct device_process_node *cur, *next_dpn;
1388 int retval = 0;
1389
1390 mutex_lock(&dqm->lock);
1391
1392 /* Clear all user mode queues */
1393 list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
1394 int ret;
1395
1396 ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
1397 if (ret)
1398 retval = ret;
1399 }
1400
1401 /* Unregister process */
1402 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
1403 if (qpd == cur->qpd) {
1404 list_del(&cur->list);
1405 kfree(cur);
1406 dqm->processes_count--;
1407 break;
1408 }
1409 }
1410
1411 mutex_unlock(&dqm->lock);
1412 return retval;
1413}
1414
1415
1416static int process_termination_cpsch(struct device_queue_manager *dqm,
1417 struct qcm_process_device *qpd)
1418{
1419 int retval;
1420 struct queue *q, *next;
1421 struct kernel_queue *kq, *kq_next;
1422 struct mqd_manager *mqd;
1423 struct device_process_node *cur, *next_dpn;
1424 enum kfd_unmap_queues_filter filter =
1425 KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
1426
1427 retval = 0;
1428
1429 mutex_lock(&dqm->lock);
1430
1431 /* Clean all kernel queues */
1432 list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
1433 list_del(&kq->list);
1434 dqm->queue_count--;
1435 qpd->is_debug = false;
1436 dqm->total_queue_count--;
1437 filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
1438 }
1439
1440 /* Clear all user mode queues */
1441 list_for_each_entry(q, &qpd->queues_list, list) {
1442 if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
1443 dqm->sdma_queue_count--;
1444 deallocate_sdma_queue(dqm, q->sdma_id);
1445 }
1446
1447 if (q->properties.is_active)
1448 dqm->queue_count--;
1449
1450 dqm->total_queue_count--;
1451 }
1452
1453 /* Unregister process */
1454 list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
1455 if (qpd == cur->qpd) {
1456 list_del(&cur->list);
1457 kfree(cur);
1458 dqm->processes_count--;
1459 break;
1460 }
1461 }
1462
1463 retval = execute_queues_cpsch(dqm, filter, 0);
1464 if (retval || qpd->reset_wavefronts) {
1465 pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
1466 dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
1467 qpd->reset_wavefronts = false;
1468 }
1469
1470 /* lastly, free mqd resources */
1471 list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
1472 mqd = dqm->ops.get_mqd_manager(dqm,
1473 get_mqd_type_from_queue_type(q->properties.type));
1474 if (!mqd) {
1475 retval = -ENOMEM;
1476 goto out;
1477 }
1478 list_del(&q->list);
1479 qpd->queue_count--;
1480 mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
1481 }
1482
1483out:
1484 mutex_unlock(&dqm->lock);
1485 return retval;
1486}
1487
1488struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
1489{
1490 struct device_queue_manager *dqm;
1491
1492 pr_debug("Loading device queue manager\n");
1493
1494 dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
1495 if (!dqm)
1496 return NULL;
1497
1498 switch (dev->device_info->asic_family) {
1499 /* HWS is not available on Hawaii. */
1500 case CHIP_HAWAII:
1501 /* HWS depends on CWSR for timely dequeue. CWSR is not
1502 * available on Tonga.
1503 *
1504 * FIXME: This argument also applies to Kaveri.
1505 */
1506 case CHIP_TONGA:
1507 dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS;
1508 break;
1509 default:
1510 dqm->sched_policy = sched_policy;
1511 break;
1512 }
1513
1514 dqm->dev = dev;
1515 switch (dqm->sched_policy) {
1516 case KFD_SCHED_POLICY_HWS:
1517 case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
1518 /* initialize dqm for cp scheduling */
1519 dqm->ops.create_queue = create_queue_cpsch;
1520 dqm->ops.initialize = initialize_cpsch;
1521 dqm->ops.start = start_cpsch;
1522 dqm->ops.stop = stop_cpsch;
1523 dqm->ops.destroy_queue = destroy_queue_cpsch;
1524 dqm->ops.update_queue = update_queue;
1525 dqm->ops.get_mqd_manager = get_mqd_manager;
1526 dqm->ops.register_process = register_process;
1527 dqm->ops.unregister_process = unregister_process;
1528 dqm->ops.uninitialize = uninitialize;
1529 dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
1530 dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
1531 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
1532 dqm->ops.set_trap_handler = set_trap_handler;
1533 dqm->ops.process_termination = process_termination_cpsch;
1534 dqm->ops.evict_process_queues = evict_process_queues_cpsch;
1535 dqm->ops.restore_process_queues = restore_process_queues_cpsch;
1536 break;
1537 case KFD_SCHED_POLICY_NO_HWS:
1538 /* initialize dqm for no cp scheduling */
1539 dqm->ops.start = start_nocpsch;
1540 dqm->ops.stop = stop_nocpsch;
1541 dqm->ops.create_queue = create_queue_nocpsch;
1542 dqm->ops.destroy_queue = destroy_queue_nocpsch;
1543 dqm->ops.update_queue = update_queue;
1544 dqm->ops.get_mqd_manager = get_mqd_manager;
1545 dqm->ops.register_process = register_process;
1546 dqm->ops.unregister_process = unregister_process;
1547 dqm->ops.initialize = initialize_nocpsch;
1548 dqm->ops.uninitialize = uninitialize;
1549 dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
1550 dqm->ops.set_trap_handler = set_trap_handler;
1551 dqm->ops.process_termination = process_termination_nocpsch;
1552 dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
1553 dqm->ops.restore_process_queues =
1554 restore_process_queues_nocpsch;
1555 break;
1556 default:
1557 pr_err("Invalid scheduling policy %d\n", dqm->sched_policy);
1558 goto out_free;
1559 }
1560
1561 switch (dev->device_info->asic_family) {
1562 case CHIP_CARRIZO:
1563 device_queue_manager_init_vi(&dqm->asic_ops);
1564 break;
1565
1566 case CHIP_KAVERI:
1567 device_queue_manager_init_cik(&dqm->asic_ops);
1568 break;
1569
1570 case CHIP_HAWAII:
1571 device_queue_manager_init_cik_hawaii(&dqm->asic_ops);
1572 break;
1573
1574 case CHIP_TONGA:
1575 case CHIP_FIJI:
1576 case CHIP_POLARIS10:
1577 case CHIP_POLARIS11:
1578 device_queue_manager_init_vi_tonga(&dqm->asic_ops);
1579 break;
1580 default:
1581 WARN(1, "Unexpected ASIC family %u",
1582 dev->device_info->asic_family);
1583 goto out_free;
1584 }
1585
1586 if (!dqm->ops.initialize(dqm))
1587 return dqm;
1588
1589out_free:
1590 kfree(dqm);
1591 return NULL;
1592}
1593
1594void device_queue_manager_uninit(struct device_queue_manager *dqm)
1595{
1596 dqm->ops.uninitialize(dqm);
1597 kfree(dqm);
1598}
1599
1600#if defined(CONFIG_DEBUG_FS)
1601
1602static void seq_reg_dump(struct seq_file *m,
1603 uint32_t (*dump)[2], uint32_t n_regs)
1604{
1605 uint32_t i, count;
1606
1607 for (i = 0, count = 0; i < n_regs; i++) {
1608 if (count == 0 ||
1609 dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
1610 seq_printf(m, "%s %08x: %08x",
1611 i ? "\n" : "",
1612 dump[i][0], dump[i][1]);
1613 count = 7;
1614 } else {
1615 seq_printf(m, " %08x", dump[i][1]);
1616 count--;
1617 }
1618 }
1619
1620 seq_puts(m, "\n");
1621}
1622
1623int dqm_debugfs_hqds(struct seq_file *m, void *data)
1624{
1625 struct device_queue_manager *dqm = data;
1626 uint32_t (*dump)[2], n_regs;
1627 int pipe, queue;
1628 int r = 0;
1629
1630 for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
1631 int pipe_offset = pipe * get_queues_per_pipe(dqm);
1632
1633 for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
1634 if (!test_bit(pipe_offset + queue,
1635 dqm->dev->shared_resources.queue_bitmap))
1636 continue;
1637
1638 r = dqm->dev->kfd2kgd->hqd_dump(
1639 dqm->dev->kgd, pipe, queue, &dump, &n_regs);
1640 if (r)
1641 break;
1642
1643 seq_printf(m, " CP Pipe %d, Queue %d\n",
1644 pipe, queue);
1645 seq_reg_dump(m, dump, n_regs);
1646
1647 kfree(dump);
1648 }
1649 }
1650
1651 for (pipe = 0; pipe < CIK_SDMA_ENGINE_NUM; pipe++) {
1652 for (queue = 0; queue < CIK_SDMA_QUEUES_PER_ENGINE; queue++) {
1653 r = dqm->dev->kfd2kgd->hqd_sdma_dump(
1654 dqm->dev->kgd, pipe, queue, &dump, &n_regs);
1655 if (r)
1656 break;
1657
1658 seq_printf(m, " SDMA Engine %d, RLC %d\n",
1659 pipe, queue);
1660 seq_reg_dump(m, dump, n_regs);
1661
1662 kfree(dump);
1663 }
1664 }
1665
1666 return r;
1667}
1668
1669#endif