1/*
  2 * Copyright 2012 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * based on nouveau_prime.c
 23 *
 24 * Authors: Alex Deucher
 25 */
 26#include <drm/drmP.h>
 27
 28#include "amdgpu.h"
 29#include "amdgpu_display.h"
 30#include <drm/amdgpu_drm.h>
 31#include <linux/dma-buf.h>
 32
 33static const struct dma_buf_ops amdgpu_dmabuf_ops;
 34
 35struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj)
 36{
 37	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 38	int npages = bo->tbo.num_pages;
 39
 40	return drm_prime_pages_to_sg(bo->tbo.ttm->pages, npages);
 41}
 42
 43void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj)
 44{
 45	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 46	int ret;
 47
 48	ret = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages,
 49			  &bo->dma_buf_vmap);
 50	if (ret)
 51		return ERR_PTR(ret);
 52
 53	return bo->dma_buf_vmap.virtual;
 54}
 55
 56void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
 57{
 58	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 59
 60	ttm_bo_kunmap(&bo->dma_buf_vmap);
 61}
 62
 63int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma)
 64{
 65	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 66	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 67	unsigned asize = amdgpu_bo_size(bo);
 68	int ret;
 69
 70	if (!vma->vm_file)
 71		return -ENODEV;
 72
 73	if (adev == NULL)
 74		return -ENODEV;
 75
 76	/* Check for valid size. */
 77	if (asize < vma->vm_end - vma->vm_start)
 78		return -EINVAL;
 79
 80	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
 81	    (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
 82		return -EPERM;
 83	}
 84	vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;
 85
 86	/* prime mmap does not need to check access, so allow here */
 87	ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data);
 88	if (ret)
 89		return ret;
 90
 91	ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev);
 92	drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data);
 93
 94	return ret;
 95}
 96
 97struct drm_gem_object *
 98amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
 99				 struct dma_buf_attachment *attach,
100				 struct sg_table *sg)
101{
102	struct reservation_object *resv = attach->dmabuf->resv;
103	struct amdgpu_device *adev = dev->dev_private;
104	struct amdgpu_bo *bo;
105	int ret;
106
107	ww_mutex_lock(&resv->lock, NULL);
108	ret = amdgpu_bo_create(adev, attach->dmabuf->size, PAGE_SIZE,
109			       AMDGPU_GEM_DOMAIN_CPU, 0, ttm_bo_type_sg,
110			       resv, &bo);
111	if (ret)
112		goto error;
113
114	bo->tbo.sg = sg;
115	bo->tbo.ttm->sg = sg;
116	bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
117	bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
118	if (attach->dmabuf->ops != &amdgpu_dmabuf_ops)
119		bo->prime_shared_count = 1;
120
121	ww_mutex_unlock(&resv->lock);
122	return &bo->gem_base;
123
124error:
125	ww_mutex_unlock(&resv->lock);
126	return ERR_PTR(ret);
127}
128
129static int amdgpu_gem_map_attach(struct dma_buf *dma_buf,
130				 struct device *target_dev,
131				 struct dma_buf_attachment *attach)
132{
133	struct drm_gem_object *obj = dma_buf->priv;
134	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
135	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
136	long r;
137
138	r = drm_gem_map_attach(dma_buf, target_dev, attach);
139	if (r)
140		return r;
141
142	r = amdgpu_bo_reserve(bo, false);
143	if (unlikely(r != 0))
144		goto error_detach;
145
146
147	if (attach->dev->driver != adev->dev->driver) {
148		/*
149		 * Wait for all shared fences to complete before we switch to future
150		 * use of exclusive fence on this prime shared bo.
151		 */
152		r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
153							true, false,
154							MAX_SCHEDULE_TIMEOUT);
155		if (unlikely(r < 0)) {
156			DRM_DEBUG_PRIME("Fence wait failed: %li\n", r);
157			goto error_unreserve;
158		}
159	}
160
161	/* pin buffer into GTT */
162	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL);
163	if (r)
164		goto error_unreserve;
165
166	if (attach->dev->driver != adev->dev->driver)
167		bo->prime_shared_count++;
168
169error_unreserve:
170	amdgpu_bo_unreserve(bo);
171
172error_detach:
173	if (r)
174		drm_gem_map_detach(dma_buf, attach);
175	return r;
176}
177
178static void amdgpu_gem_map_detach(struct dma_buf *dma_buf,
179				  struct dma_buf_attachment *attach)
180{
181	struct drm_gem_object *obj = dma_buf->priv;
182	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
183	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
184	int ret = 0;
185
186	ret = amdgpu_bo_reserve(bo, true);
187	if (unlikely(ret != 0))
188		goto error;
189
190	amdgpu_bo_unpin(bo);
191	if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count)
192		bo->prime_shared_count--;
193	amdgpu_bo_unreserve(bo);
194
195error:
196	drm_gem_map_detach(dma_buf, attach);
197}
198
199struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj)
200{
201	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
202
203	return bo->tbo.resv;
204}
205
206static int amdgpu_gem_begin_cpu_access(struct dma_buf *dma_buf,
207				       enum dma_data_direction direction)
208{
209	struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
210	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
211	struct ttm_operation_ctx ctx = { true, false };
212	u32 domain = amdgpu_display_framebuffer_domains(adev);
213	int ret;
214	bool reads = (direction == DMA_BIDIRECTIONAL ||
215		      direction == DMA_FROM_DEVICE);
216
217	if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
218		return 0;
219
220	/* move to gtt */
221	ret = amdgpu_bo_reserve(bo, false);
222	if (unlikely(ret != 0))
223		return ret;
224
225	if (!bo->pin_count && (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
226		amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
227		ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
228	}
229
230	amdgpu_bo_unreserve(bo);
231	return ret;
232}
233
234static const struct dma_buf_ops amdgpu_dmabuf_ops = {
235	.attach = amdgpu_gem_map_attach,
236	.detach = amdgpu_gem_map_detach,
237	.map_dma_buf = drm_gem_map_dma_buf,
238	.unmap_dma_buf = drm_gem_unmap_dma_buf,
239	.release = drm_gem_dmabuf_release,
240	.begin_cpu_access = amdgpu_gem_begin_cpu_access,
241	.map = drm_gem_dmabuf_kmap,
242	.map_atomic = drm_gem_dmabuf_kmap_atomic,
243	.unmap = drm_gem_dmabuf_kunmap,
244	.unmap_atomic = drm_gem_dmabuf_kunmap_atomic,
245	.mmap = drm_gem_dmabuf_mmap,
246	.vmap = drm_gem_dmabuf_vmap,
247	.vunmap = drm_gem_dmabuf_vunmap,
248};
249
250struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
251					struct drm_gem_object *gobj,
252					int flags)
253{
254	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
255	struct dma_buf *buf;
256
257	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
258	    bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
259		return ERR_PTR(-EPERM);
260
261	buf = drm_gem_prime_export(dev, gobj, flags);
262	if (!IS_ERR(buf)) {
263		buf->file->f_mapping = dev->anon_inode->i_mapping;
264		buf->ops = &amdgpu_dmabuf_ops;
265	}
266
267	return buf;
268}
269
270struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
271					    struct dma_buf *dma_buf)
272{
273	struct drm_gem_object *obj;
274
275	if (dma_buf->ops == &amdgpu_dmabuf_ops) {
276		obj = dma_buf->priv;
277		if (obj->dev == dev) {
278			/*
279			 * Importing dmabuf exported from out own gem increases
280			 * refcount on gem itself instead of f_count of dmabuf.
281			 */
282			drm_gem_object_get(obj);
283			return obj;
284		}
285	}
286
287	return drm_gem_prime_import(dev, dma_buf);
288}