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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright 2009 Freescale Semiconductor, Inc.
4 *
5 * provides masks and opcode images for use by code generation, emulation
6 * and for instructions that older assemblers might not know about
7 */
8#ifndef _ASM_POWERPC_PPC_OPCODE_H
9#define _ASM_POWERPC_PPC_OPCODE_H
10
11#include <asm/asm-const.h>
12
13#define __REG_R0 0
14#define __REG_R1 1
15#define __REG_R2 2
16#define __REG_R3 3
17#define __REG_R4 4
18#define __REG_R5 5
19#define __REG_R6 6
20#define __REG_R7 7
21#define __REG_R8 8
22#define __REG_R9 9
23#define __REG_R10 10
24#define __REG_R11 11
25#define __REG_R12 12
26#define __REG_R13 13
27#define __REG_R14 14
28#define __REG_R15 15
29#define __REG_R16 16
30#define __REG_R17 17
31#define __REG_R18 18
32#define __REG_R19 19
33#define __REG_R20 20
34#define __REG_R21 21
35#define __REG_R22 22
36#define __REG_R23 23
37#define __REG_R24 24
38#define __REG_R25 25
39#define __REG_R26 26
40#define __REG_R27 27
41#define __REG_R28 28
42#define __REG_R29 29
43#define __REG_R30 30
44#define __REG_R31 31
45
46#define __REGA0_0 0
47#define __REGA0_R1 1
48#define __REGA0_R2 2
49#define __REGA0_R3 3
50#define __REGA0_R4 4
51#define __REGA0_R5 5
52#define __REGA0_R6 6
53#define __REGA0_R7 7
54#define __REGA0_R8 8
55#define __REGA0_R9 9
56#define __REGA0_R10 10
57#define __REGA0_R11 11
58#define __REGA0_R12 12
59#define __REGA0_R13 13
60#define __REGA0_R14 14
61#define __REGA0_R15 15
62#define __REGA0_R16 16
63#define __REGA0_R17 17
64#define __REGA0_R18 18
65#define __REGA0_R19 19
66#define __REGA0_R20 20
67#define __REGA0_R21 21
68#define __REGA0_R22 22
69#define __REGA0_R23 23
70#define __REGA0_R24 24
71#define __REGA0_R25 25
72#define __REGA0_R26 26
73#define __REGA0_R27 27
74#define __REGA0_R28 28
75#define __REGA0_R29 29
76#define __REGA0_R30 30
77#define __REGA0_R31 31
78
79/* For use with PPC_RAW_() macros */
80#define _R0 0
81#define _R1 1
82#define _R2 2
83#define _R3 3
84#define _R4 4
85#define _R5 5
86#define _R6 6
87#define _R7 7
88#define _R8 8
89#define _R9 9
90#define _R10 10
91#define _R11 11
92#define _R12 12
93#define _R13 13
94#define _R14 14
95#define _R15 15
96#define _R16 16
97#define _R17 17
98#define _R18 18
99#define _R19 19
100#define _R20 20
101#define _R21 21
102#define _R22 22
103#define _R23 23
104#define _R24 24
105#define _R25 25
106#define _R26 26
107#define _R27 27
108#define _R28 28
109#define _R29 29
110#define _R30 30
111#define _R31 31
112
113#define IMM_L(i) ((uintptr_t)(i) & 0xffff)
114#define IMM_DS(i) ((uintptr_t)(i) & 0xfffc)
115#define IMM_DQ(i) ((uintptr_t)(i) & 0xfff0)
116#define IMM_D0(i) (((uintptr_t)(i) >> 16) & 0x3ffff)
117#define IMM_D1(i) IMM_L(i)
118
119/*
120 * 16-bit immediate helper macros: HA() is for use with sign-extending instrs
121 * (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the
122 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
123 *
124 * XXX: should these mask out possible sign bits?
125 */
126#define IMM_H(i) ((uintptr_t)(i)>>16)
127#define IMM_HA(i) (((uintptr_t)(i)>>16) + \
128 (((uintptr_t)(i) & 0x8000) >> 15))
129
130/*
131 * 18-bit immediate helper for prefix 18-bit upper immediate si0 field.
132 */
133#define IMM_H18(i) (((uintptr_t)(i)>>16) & 0x3ffff)
134
135
136/* opcode and xopcode for instructions */
137#define OP_PREFIX 1
138#define OP_TRAP_64 2
139#define OP_TRAP 3
140#define OP_SC 17
141#define OP_19 19
142#define OP_31 31
143#define OP_LWZ 32
144#define OP_LWZU 33
145#define OP_LBZ 34
146#define OP_LBZU 35
147#define OP_STW 36
148#define OP_STWU 37
149#define OP_STB 38
150#define OP_STBU 39
151#define OP_LHZ 40
152#define OP_LHZU 41
153#define OP_LHA 42
154#define OP_LHAU 43
155#define OP_STH 44
156#define OP_STHU 45
157#define OP_LMW 46
158#define OP_STMW 47
159#define OP_LFS 48
160#define OP_LFSU 49
161#define OP_LFD 50
162#define OP_LFDU 51
163#define OP_STFS 52
164#define OP_STFSU 53
165#define OP_STFD 54
166#define OP_STFDU 55
167#define OP_LQ 56
168#define OP_LD 58
169#define OP_STD 62
170
171#define OP_19_XOP_RFID 18
172#define OP_19_XOP_RFMCI 38
173#define OP_19_XOP_RFDI 39
174#define OP_19_XOP_RFI 50
175#define OP_19_XOP_RFCI 51
176#define OP_19_XOP_RFSCV 82
177#define OP_19_XOP_HRFID 274
178#define OP_19_XOP_URFID 306
179#define OP_19_XOP_STOP 370
180#define OP_19_XOP_DOZE 402
181#define OP_19_XOP_NAP 434
182#define OP_19_XOP_SLEEP 466
183#define OP_19_XOP_RVWINKLE 498
184
185#define OP_31_XOP_TRAP 4
186#define OP_31_XOP_LDX 21
187#define OP_31_XOP_LWZX 23
188#define OP_31_XOP_LDUX 53
189#define OP_31_XOP_DCBST 54
190#define OP_31_XOP_LWZUX 55
191#define OP_31_XOP_TRAP_64 68
192#define OP_31_XOP_DCBF 86
193#define OP_31_XOP_LBZX 87
194#define OP_31_XOP_STDX 149
195#define OP_31_XOP_STWX 151
196#define OP_31_XOP_STDUX 181
197#define OP_31_XOP_STWUX 183
198#define OP_31_XOP_STBX 215
199#define OP_31_XOP_LBZUX 119
200#define OP_31_XOP_STBUX 247
201#define OP_31_XOP_LHZX 279
202#define OP_31_XOP_LHZUX 311
203#define OP_31_XOP_MSGSNDP 142
204#define OP_31_XOP_MSGCLRP 174
205#define OP_31_XOP_MTMSR 146
206#define OP_31_XOP_MTMSRD 178
207#define OP_31_XOP_TLBIE 306
208#define OP_31_XOP_MFSPR 339
209#define OP_31_XOP_LWAX 341
210#define OP_31_XOP_LHAX 343
211#define OP_31_XOP_LWAUX 373
212#define OP_31_XOP_LHAUX 375
213#define OP_31_XOP_STHX 407
214#define OP_31_XOP_STHUX 439
215#define OP_31_XOP_MTSPR 467
216#define OP_31_XOP_DCBI 470
217#define OP_31_XOP_LDBRX 532
218#define OP_31_XOP_LWBRX 534
219#define OP_31_XOP_TLBSYNC 566
220#define OP_31_XOP_STDBRX 660
221#define OP_31_XOP_STWBRX 662
222#define OP_31_XOP_STFSX 663
223#define OP_31_XOP_STFSUX 695
224#define OP_31_XOP_STFDX 727
225#define OP_31_XOP_HASHCHK 754
226#define OP_31_XOP_STFDUX 759
227#define OP_31_XOP_LHBRX 790
228#define OP_31_XOP_LFIWAX 855
229#define OP_31_XOP_LFIWZX 887
230#define OP_31_XOP_STHBRX 918
231#define OP_31_XOP_STFIWX 983
232
233/* VSX Scalar Load Instructions */
234#define OP_31_XOP_LXSDX 588
235#define OP_31_XOP_LXSSPX 524
236#define OP_31_XOP_LXSIWAX 76
237#define OP_31_XOP_LXSIWZX 12
238
239/* VSX Scalar Store Instructions */
240#define OP_31_XOP_STXSDX 716
241#define OP_31_XOP_STXSSPX 652
242#define OP_31_XOP_STXSIWX 140
243
244/* VSX Vector Load Instructions */
245#define OP_31_XOP_LXVD2X 844
246#define OP_31_XOP_LXVW4X 780
247
248/* VSX Vector Load and Splat Instruction */
249#define OP_31_XOP_LXVDSX 332
250
251/* VSX Vector Store Instructions */
252#define OP_31_XOP_STXVD2X 972
253#define OP_31_XOP_STXVW4X 908
254
255#define OP_31_XOP_LFSX 535
256#define OP_31_XOP_LFSUX 567
257#define OP_31_XOP_LFDX 599
258#define OP_31_XOP_LFDUX 631
259
260/* VMX Vector Load Instructions */
261#define OP_31_XOP_LVX 103
262
263/* VMX Vector Store Instructions */
264#define OP_31_XOP_STVX 231
265
266/* sorted alphabetically */
267#define PPC_INST_BCCTR_FLUSH 0x4c400420
268#define PPC_INST_COPY 0x7c20060c
269#define PPC_INST_DCBA 0x7c0005ec
270#define PPC_INST_DCBA_MASK 0xfc0007fe
271#define PPC_INST_DSSALL 0x7e00066c
272#define PPC_INST_ISEL 0x7c00001e
273#define PPC_INST_ISEL_MASK 0xfc00003e
274#define PPC_INST_LSWI 0x7c0004aa
275#define PPC_INST_LSWX 0x7c00042a
276#define PPC_INST_LWSYNC 0x7c2004ac
277#define PPC_INST_SYNC 0x7c0004ac
278#define PPC_INST_SYNC_MASK 0xfc0007fe
279#define PPC_INST_MCRXR 0x7c000400
280#define PPC_INST_MCRXR_MASK 0xfc0007fe
281#define PPC_INST_MFSPR_PVR 0x7c1f42a6
282#define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe
283#define PPC_INST_MTMSRD 0x7c000164
284#define PPC_INST_PASTE 0x7c20070d
285#define PPC_INST_PASTE_MASK 0xfc2007ff
286#define PPC_INST_POPCNTB 0x7c0000f4
287#define PPC_INST_POPCNTB_MASK 0xfc0007fe
288#define PPC_INST_RFEBB 0x4c000124
289#define PPC_INST_RFID 0x4c000024
290#define PPC_INST_MFSPR_DSCR 0x7c1102a6
291#define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe
292#define PPC_INST_MTSPR_DSCR 0x7c1103a6
293#define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe
294#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
295#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe
296#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
297#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe
298#define PPC_INST_STRING 0x7c00042a
299#define PPC_INST_STRING_MASK 0xfc0007fe
300#define PPC_INST_STRING_GEN_MASK 0xfc00067e
301#define PPC_INST_STSWI 0x7c0005aa
302#define PPC_INST_STSWX 0x7c00052a
303#define PPC_INST_TRECHKPT 0x7c0007dd
304#define PPC_INST_TRECLAIM 0x7c00075d
305#define PPC_INST_TSR 0x7c0005dd
306#define PPC_INST_BRANCH_COND 0x40800000
307
308/* Prefixes */
309#define PPC_INST_LFS 0xc0000000
310#define PPC_INST_STFS 0xd0000000
311#define PPC_INST_LFD 0xc8000000
312#define PPC_INST_STFD 0xd8000000
313#define PPC_PREFIX_MLS 0x06000000
314#define PPC_PREFIX_8LS 0x04000000
315
316/* Prefixed instructions */
317#define PPC_INST_PADDI 0x38000000
318#define PPC_INST_PLD 0xe4000000
319#define PPC_INST_PSTD 0xf4000000
320
321/* macros to insert fields into opcodes */
322#define ___PPC_RA(a) (((a) & 0x1f) << 16)
323#define ___PPC_RB(b) (((b) & 0x1f) << 11)
324#define ___PPC_RC(c) (((c) & 0x1f) << 6)
325#define ___PPC_RS(s) (((s) & 0x1f) << 21)
326#define ___PPC_RT(t) ___PPC_RS(t)
327#define ___PPC_R(r) (((r) & 0x1) << 16)
328#define ___PPC_PRS(prs) (((prs) & 0x1) << 17)
329#define ___PPC_RIC(ric) (((ric) & 0x3) << 18)
330#define __PPC_RA(a) ___PPC_RA(__REG_##a)
331#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
332#define __PPC_RB(b) ___PPC_RB(__REG_##b)
333#define __PPC_RS(s) ___PPC_RS(__REG_##s)
334#define __PPC_RT(t) ___PPC_RT(__REG_##t)
335#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
336#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
337#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
338#define __PPC_XT(s) __PPC_XS(s)
339#define __PPC_XSP(s) ((((s) & 0x1e) | (((s) >> 5) & 0x1)) << 21)
340#define __PPC_XTP(s) __PPC_XSP(s)
341#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
342#define __PPC_PL(p) (((p) & 0x3) << 16)
343#define __PPC_WC(w) (((w) & 0x3) << 21)
344#define __PPC_WS(w) (((w) & 0x1f) << 11)
345#define __PPC_SH(s) __PPC_WS(s)
346#define __PPC_SH64(s) (__PPC_SH(s) | (((s) & 0x20) >> 4))
347#define __PPC_MB(s) ___PPC_RC(s)
348#define __PPC_ME(s) (((s) & 0x1f) << 1)
349#define __PPC_MB64(s) (__PPC_MB(s) | ((s) & 0x20))
350#define __PPC_ME64(s) __PPC_MB64(s)
351#define __PPC_BI(s) (((s) & 0x1f) << 16)
352#define __PPC_CT(t) (((t) & 0x0f) << 21)
353#define __PPC_SPR(r) ((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11))
354#define __PPC_RC21 (0x1 << 10)
355#define __PPC_PRFX_R(r) (((r) & 0x1) << 20)
356#define __PPC_EH(eh) (((eh) & 0x1) << 0)
357
358/*
359 * Both low and high 16 bits are added as SIGNED additions, so if low 16 bits
360 * has high bit set, high 16 bits must be adjusted. These macros do that (stolen
361 * from binutils).
362 */
363#define PPC_LO(v) ((v) & 0xffff)
364#define PPC_HI(v) (((v) >> 16) & 0xffff)
365#define PPC_HA(v) PPC_HI((v) + 0x8000)
366#define PPC_HIGHER(v) (((v) >> 32) & 0xffff)
367#define PPC_HIGHEST(v) (((v) >> 48) & 0xffff)
368
369/* LI Field */
370#define PPC_LI_MASK 0x03fffffc
371#define PPC_LI(v) ((v) & PPC_LI_MASK)
372
373/* Base instruction encoding */
374#define PPC_RAW_CP_ABORT (0x7c00068c)
375#define PPC_RAW_COPY(a, b) (PPC_INST_COPY | ___PPC_RA(a) | ___PPC_RB(b))
376#define PPC_RAW_DARN(t, l) (0x7c0005e6 | ___PPC_RT(t) | (((l) & 0x3) << 16))
377#define PPC_RAW_DCBAL(a, b) (0x7c2005ec | __PPC_RA(a) | __PPC_RB(b))
378#define PPC_RAW_DCBZL(a, b) (0x7c2007ec | __PPC_RA(a) | __PPC_RB(b))
379#define PPC_RAW_LQARX(t, a, b, eh) (0x7c000228 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
380#define PPC_RAW_LDARX(t, a, b, eh) (0x7c0000a8 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
381#define PPC_RAW_LWARX(t, a, b, eh) (0x7c000028 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
382#define PPC_RAW_PHWSYNC (0x7c8004ac)
383#define PPC_RAW_PLWSYNC (0x7ca004ac)
384#define PPC_RAW_STQCX(t, a, b) (0x7c00016d | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
385#define PPC_RAW_MADDHD(t, a, b, c) (0x10000030 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
386#define PPC_RAW_MADDHDU(t, a, b, c) (0x10000031 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
387#define PPC_RAW_MADDLD(t, a, b, c) (0x10000033 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
388#define PPC_RAW_MSGSND(b) (0x7c00019c | ___PPC_RB(b))
389#define PPC_RAW_MSGSYNC (0x7c0006ec)
390#define PPC_RAW_MSGCLR(b) (0x7c0001dc | ___PPC_RB(b))
391#define PPC_RAW_MSGSNDP(b) (0x7c00011c | ___PPC_RB(b))
392#define PPC_RAW_MSGCLRP(b) (0x7c00015c | ___PPC_RB(b))
393#define PPC_RAW_PASTE(a, b) (0x7c20070d | ___PPC_RA(a) | ___PPC_RB(b))
394#define PPC_RAW_POPCNTB(a, s) (PPC_INST_POPCNTB | __PPC_RA(a) | __PPC_RS(s))
395#define PPC_RAW_POPCNTD(a, s) (0x7c0003f4 | __PPC_RA(a) | __PPC_RS(s))
396#define PPC_RAW_POPCNTW(a, s) (0x7c0002f4 | __PPC_RA(a) | __PPC_RS(s))
397#define PPC_RAW_RFCI (0x4c000066)
398#define PPC_RAW_RFDI (0x4c00004e)
399#define PPC_RAW_RFMCI (0x4c00004c)
400#define PPC_RAW_TLBILX_LPID (0x7c000024)
401#define PPC_RAW_TLBILX(t, a, b) (0x7c000024 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
402#define PPC_RAW_WAIT_v203 (0x7c00007c)
403#define PPC_RAW_WAIT(w, p) (0x7c00003c | __PPC_WC(w) | __PPC_PL(p))
404#define PPC_RAW_TLBIE(lp, a) (0x7c000264 | ___PPC_RB(a) | ___PPC_RS(lp))
405#define PPC_RAW_TLBIE_5(rb, rs, ric, prs, r) \
406 (0x7c000264 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
407#define PPC_RAW_TLBIEL(rb, rs, ric, prs, r) \
408 (0x7c000224 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
409#define PPC_RAW_TLBIEL_v205(rb, l) (0x7c000224 | ___PPC_RB(rb) | (l << 21))
410#define PPC_RAW_TLBSRX_DOT(a, b) (0x7c0006a5 | __PPC_RA0(a) | __PPC_RB(b))
411#define PPC_RAW_TLBIVAX(a, b) (0x7c000624 | __PPC_RA0(a) | __PPC_RB(b))
412#define PPC_RAW_ERATWE(s, a, w) (0x7c0001a6 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
413#define PPC_RAW_ERATRE(s, a, w) (0x7c000166 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
414#define PPC_RAW_ERATILX(t, a, b) (0x7c000066 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
415#define PPC_RAW_ERATIVAX(s, a, b) (0x7c000666 | __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
416#define PPC_RAW_ERATSX(t, a, w) (0x7c000126 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
417#define PPC_RAW_ERATSX_DOT(t, a, w) (0x7c000127 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
418#define PPC_RAW_SLBFEE_DOT(t, b) (0x7c0007a7 | __PPC_RT(t) | __PPC_RB(b))
419#define __PPC_RAW_SLBFEE_DOT(t, b) (0x7c0007a7 | ___PPC_RT(t) | ___PPC_RB(b))
420#define PPC_RAW_ICBT(c, a, b) (0x7c00002c | __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
421#define PPC_RAW_LBZCIX(t, a, b) (0x7c0006aa | __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
422#define PPC_RAW_STBCIX(s, a, b) (0x7c0007aa | __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
423#define PPC_RAW_DCBFPS(a, b) (0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (4 << 21))
424#define PPC_RAW_DCBSTPS(a, b) (0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (6 << 21))
425#define PPC_RAW_SC() (0x44000002)
426#define PPC_RAW_SYNC() (0x7c0004ac)
427#define PPC_RAW_ISYNC() (0x4c00012c)
428
429/*
430 * Define what the VSX XX1 form instructions will look like, then add
431 * the 128 bit load store instructions based on that.
432 */
433#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
434#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
435#define PPC_RAW_STXVD2X(s, a, b) (0x7c000798 | VSX_XX1((s), a, b))
436#define PPC_RAW_LXVD2X(s, a, b) (0x7c000698 | VSX_XX1((s), a, b))
437#define PPC_RAW_MFVRD(a, t) (0x7c000066 | VSX_XX1((t) + 32, a, R0))
438#define PPC_RAW_MTVRD(t, a) (0x7c000166 | VSX_XX1((t) + 32, a, R0))
439#define PPC_RAW_VPMSUMW(t, a, b) (0x10000488 | VSX_XX3((t), a, b))
440#define PPC_RAW_VPMSUMD(t, a, b) (0x100004c8 | VSX_XX3((t), a, b))
441#define PPC_RAW_XXLOR(t, a, b) (0xf0000490 | VSX_XX3((t), a, b))
442#define PPC_RAW_XXSWAPD(t, a) (0xf0000250 | VSX_XX3((t), a, a))
443#define PPC_RAW_XVCPSGNDP(t, a, b) ((0xf0000780 | VSX_XX3((t), (a), (b))))
444#define PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc) \
445 ((0x1000002d | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | (((vrc) & 0x1f) << 6)))
446#define PPC_RAW_LXVP(xtp, a, i) (0x18000000 | __PPC_XTP(xtp) | ___PPC_RA(a) | IMM_DQ(i))
447#define PPC_RAW_STXVP(xsp, a, i) (0x18000001 | __PPC_XSP(xsp) | ___PPC_RA(a) | IMM_DQ(i))
448#define PPC_RAW_LXVPX(xtp, a, b) (0x7c00029a | __PPC_XTP(xtp) | ___PPC_RA(a) | ___PPC_RB(b))
449#define PPC_RAW_STXVPX(xsp, a, b) (0x7c00039a | __PPC_XSP(xsp) | ___PPC_RA(a) | ___PPC_RB(b))
450#define PPC_RAW_PLXVP_P(xtp, i, a, pr) (PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i))
451#define PPC_RAW_PLXVP_S(xtp, i, a, pr) (0xe8000000 | __PPC_XTP(xtp) | ___PPC_RA(a) | IMM_D1(i))
452#define PPC_RAW_PSTXVP_P(xsp, i, a, pr) (PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i))
453#define PPC_RAW_PSTXVP_S(xsp, i, a, pr) (0xf8000000 | __PPC_XSP(xsp) | ___PPC_RA(a) | IMM_D1(i))
454#define PPC_RAW_NAP (0x4c000364)
455#define PPC_RAW_SLEEP (0x4c0003a4)
456#define PPC_RAW_WINKLE (0x4c0003e4)
457#define PPC_RAW_STOP (0x4c0002e4)
458#define PPC_RAW_CLRBHRB (0x7c00035c)
459#define PPC_RAW_MFBHRBE(r, n) (0x7c00025c | __PPC_RT(r) | (((n) & 0x3ff) << 11))
460#define PPC_RAW_TRECHKPT (PPC_INST_TRECHKPT)
461#define PPC_RAW_TRECLAIM(r) (PPC_INST_TRECLAIM | __PPC_RA(r))
462#define PPC_RAW_TABORT(r) (0x7c00071d | __PPC_RA(r))
463#define TMRN(x) ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
464#define PPC_RAW_MTTMR(tmr, r) (0x7c0003dc | TMRN(tmr) | ___PPC_RS(r))
465#define PPC_RAW_MFTMR(tmr, r) (0x7c0002dc | TMRN(tmr) | ___PPC_RT(r))
466#define PPC_RAW_ICSWX(s, a, b) (0x7c00032d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
467#define PPC_RAW_ICSWEPX(s, a, b) (0x7c00076d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
468#define PPC_RAW_SLBIA(IH) (0x7c0003e4 | (((IH) & 0x7) << 21))
469#define PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb) \
470 (0x100000c7 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
471#define PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb) \
472 (0x10000006 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
473#define PPC_RAW_LD(r, base, i) (0xe8000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_DS(i))
474#define PPC_RAW_LWZ(r, base, i) (0x80000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
475#define PPC_RAW_LWZX(t, a, b) (0x7c00002e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
476#define PPC_RAW_STD(r, base, i) (0xf8000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_DS(i))
477#define PPC_RAW_STDCX(s, a, b) (0x7c0001ad | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
478#define PPC_RAW_LFSX(t, a, b) (0x7c00042e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
479#define PPC_RAW_STFSX(s, a, b) (0x7c00052e | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
480#define PPC_RAW_LFDX(t, a, b) (0x7c0004ae | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
481#define PPC_RAW_STFDX(s, a, b) (0x7c0005ae | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
482#define PPC_RAW_LVX(t, a, b) (0x7c0000ce | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
483#define PPC_RAW_STVX(s, a, b) (0x7c0001ce | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
484#define PPC_RAW_ADDE(t, a, b) (0x7c000114 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
485#define PPC_RAW_ADDZE(t, a) (0x7c000194 | ___PPC_RT(t) | ___PPC_RA(a))
486#define PPC_RAW_ADDME(t, a) (0x7c0001d4 | ___PPC_RT(t) | ___PPC_RA(a))
487#define PPC_RAW_ADD(t, a, b) (0x7c000214 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
488#define PPC_RAW_ADD_DOT(t, a, b) (0x7c000214 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
489#define PPC_RAW_ADDC(t, a, b) (0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
490#define PPC_RAW_ADDC_DOT(t, a, b) (0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
491#define PPC_RAW_NOP() PPC_RAW_ORI(0, 0, 0)
492#define PPC_RAW_BLR() (0x4e800020)
493#define PPC_RAW_BLRL() (0x4e800021)
494#define PPC_RAW_MTLR(r) (0x7c0803a6 | ___PPC_RT(r))
495#define PPC_RAW_MFLR(t) (0x7c0802a6 | ___PPC_RT(t))
496#define PPC_RAW_BCTR() (0x4e800420)
497#define PPC_RAW_BCTRL() (0x4e800421)
498#define PPC_RAW_MTCTR(r) (0x7c0903a6 | ___PPC_RT(r))
499#define PPC_RAW_ADDI(d, a, i) (0x38000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
500#define PPC_RAW_LI(r, i) PPC_RAW_ADDI(r, 0, i)
501#define PPC_RAW_ADDIS(d, a, i) (0x3c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
502#define PPC_RAW_ADDIC(d, a, i) (0x30000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
503#define PPC_RAW_ADDIC_DOT(d, a, i) (0x34000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
504#define PPC_RAW_LIS(r, i) PPC_RAW_ADDIS(r, 0, i)
505#define PPC_RAW_STDX(r, base, b) (0x7c00012a | ___PPC_RS(r) | ___PPC_RA(base) | ___PPC_RB(b))
506#define PPC_RAW_STDU(r, base, i) (0xf8000001 | ___PPC_RS(r) | ___PPC_RA(base) | ((i) & 0xfffc))
507#define PPC_RAW_STW(r, base, i) (0x90000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
508#define PPC_RAW_STWU(r, base, i) (0x94000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
509#define PPC_RAW_STH(r, base, i) (0xb0000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
510#define PPC_RAW_STB(r, base, i) (0x98000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
511#define PPC_RAW_LBZ(r, base, i) (0x88000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
512#define PPC_RAW_LDX(r, base, b) (0x7c00002a | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
513#define PPC_RAW_LHA(r, base, i) (0xa8000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
514#define PPC_RAW_LHZ(r, base, i) (0xa0000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
515#define PPC_RAW_LHBRX(r, base, b) (0x7c00062c | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
516#define PPC_RAW_LWBRX(r, base, b) (0x7c00042c | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
517#define PPC_RAW_LDBRX(r, base, b) (0x7c000428 | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
518#define PPC_RAW_STWCX(s, a, b) (0x7c00012d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
519#define PPC_RAW_CMPWI(a, i) (0x2c000000 | ___PPC_RA(a) | IMM_L(i))
520#define PPC_RAW_CMPDI(a, i) (0x2c200000 | ___PPC_RA(a) | IMM_L(i))
521#define PPC_RAW_CMPW(a, b) (0x7c000000 | ___PPC_RA(a) | ___PPC_RB(b))
522#define PPC_RAW_CMPD(a, b) (0x7c200000 | ___PPC_RA(a) | ___PPC_RB(b))
523#define PPC_RAW_CMPLWI(a, i) (0x28000000 | ___PPC_RA(a) | IMM_L(i))
524#define PPC_RAW_CMPLDI(a, i) (0x28200000 | ___PPC_RA(a) | IMM_L(i))
525#define PPC_RAW_CMPLW(a, b) (0x7c000040 | ___PPC_RA(a) | ___PPC_RB(b))
526#define PPC_RAW_CMPLD(a, b) (0x7c200040 | ___PPC_RA(a) | ___PPC_RB(b))
527#define PPC_RAW_SUB(d, a, b) (0x7c000050 | ___PPC_RT(d) | ___PPC_RB(a) | ___PPC_RA(b))
528#define PPC_RAW_SUBFC(d, a, b) (0x7c000010 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
529#define PPC_RAW_SUBFE(d, a, b) (0x7c000110 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
530#define PPC_RAW_SUBFIC(d, a, i) (0x20000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
531#define PPC_RAW_SUBFZE(d, a) (0x7c000190 | ___PPC_RT(d) | ___PPC_RA(a))
532#define PPC_RAW_MULD(d, a, b) (0x7c0001d2 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
533#define PPC_RAW_MULW(d, a, b) (0x7c0001d6 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
534#define PPC_RAW_MULHWU(d, a, b) (0x7c000016 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
535#define PPC_RAW_MULI(d, a, i) (0x1c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
536#define PPC_RAW_DIVW(d, a, b) (0x7c0003d6 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
537#define PPC_RAW_DIVWU(d, a, b) (0x7c000396 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
538#define PPC_RAW_DIVDU(d, a, b) (0x7c000392 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
539#define PPC_RAW_DIVDE(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
540#define PPC_RAW_DIVDE_DOT(t, a, b) (0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
541#define PPC_RAW_DIVDEU(t, a, b) (0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
542#define PPC_RAW_DIVDEU_DOT(t, a, b) (0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
543#define PPC_RAW_AND(d, a, b) (0x7c000038 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
544#define PPC_RAW_ANDI(d, a, i) (0x70000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
545#define PPC_RAW_ANDIS(d, a, i) (0x74000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
546#define PPC_RAW_AND_DOT(d, a, b) (0x7c000039 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
547#define PPC_RAW_OR(d, a, b) (0x7c000378 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
548#define PPC_RAW_MR(d, a) PPC_RAW_OR(d, a, a)
549#define PPC_RAW_ORI(d, a, i) (0x60000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
550#define PPC_RAW_ORIS(d, a, i) (0x64000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
551#define PPC_RAW_NOR(d, a, b) (0x7c0000f8 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
552#define PPC_RAW_XOR(d, a, b) (0x7c000278 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
553#define PPC_RAW_XORI(d, a, i) (0x68000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
554#define PPC_RAW_XORIS(d, a, i) (0x6c000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
555#define PPC_RAW_EXTSB(d, a) (0x7c000774 | ___PPC_RA(d) | ___PPC_RS(a))
556#define PPC_RAW_EXTSH(d, a) (0x7c000734 | ___PPC_RA(d) | ___PPC_RS(a))
557#define PPC_RAW_EXTSW(d, a) (0x7c0007b4 | ___PPC_RA(d) | ___PPC_RS(a))
558#define PPC_RAW_SLW(d, a, s) (0x7c000030 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
559#define PPC_RAW_SLD(d, a, s) (0x7c000036 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
560#define PPC_RAW_SRW(d, a, s) (0x7c000430 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
561#define PPC_RAW_SRAW(d, a, s) (0x7c000630 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
562#define PPC_RAW_SRAWI(d, a, i) (0x7c000670 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i))
563#define PPC_RAW_SRD(d, a, s) (0x7c000436 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
564#define PPC_RAW_SRAD(d, a, s) (0x7c000634 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
565#define PPC_RAW_SRADI(d, a, i) (0x7c000674 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i))
566#define PPC_RAW_RLWINM(d, a, i, mb, me) (0x54000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
567#define PPC_RAW_RLWINM_DOT(d, a, i, mb, me) \
568 (0x54000001 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
569#define PPC_RAW_RLWIMI(d, a, i, mb, me) (0x50000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
570#define PPC_RAW_RLDICL(d, a, i, mb) (0x78000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_MB64(mb))
571#define PPC_RAW_RLDICR(d, a, i, me) (0x78000004 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_ME64(me))
572
573/* slwi = rlwinm Rx, Ry, n, 0, 31-n */
574#define PPC_RAW_SLWI(d, a, i) PPC_RAW_RLWINM(d, a, i, 0, 31-(i))
575/* srwi = rlwinm Rx, Ry, 32-n, n, 31 */
576#define PPC_RAW_SRWI(d, a, i) PPC_RAW_RLWINM(d, a, 32-(i), i, 31)
577/* sldi = rldicr Rx, Ry, n, 63-n */
578#define PPC_RAW_SLDI(d, a, i) PPC_RAW_RLDICR(d, a, i, 63-(i))
579/* sldi = rldicl Rx, Ry, 64-n, n */
580#define PPC_RAW_SRDI(d, a, i) PPC_RAW_RLDICL(d, a, 64-(i), i)
581
582#define PPC_RAW_NEG(d, a) (0x7c0000d0 | ___PPC_RT(d) | ___PPC_RA(a))
583
584#define PPC_RAW_MFSPR(d, spr) (0x7c0002a6 | ___PPC_RT(d) | __PPC_SPR(spr))
585#define PPC_RAW_MTSPR(spr, d) (0x7c0003a6 | ___PPC_RS(d) | __PPC_SPR(spr))
586#define PPC_RAW_EIEIO() (0x7c0006ac)
587
588#define PPC_RAW_BRANCH(offset) (0x48000000 | PPC_LI(offset))
589#define PPC_RAW_BL(offset) (0x48000001 | PPC_LI(offset))
590#define PPC_RAW_TW(t0, a, b) (0x7c000008 | ___PPC_RS(t0) | ___PPC_RA(a) | ___PPC_RB(b))
591#define PPC_RAW_TRAP() PPC_RAW_TW(31, 0, 0)
592#define PPC_RAW_SETB(t, bfa) (0x7c000100 | ___PPC_RT(t) | ___PPC_RA((bfa) << 2))
593
594/* Deal with instructions that older assemblers aren't aware of */
595#define PPC_BCCTR_FLUSH stringify_in_c(.long PPC_INST_BCCTR_FLUSH)
596#define PPC_CP_ABORT stringify_in_c(.long PPC_RAW_CP_ABORT)
597#define PPC_COPY(a, b) stringify_in_c(.long PPC_RAW_COPY(a, b))
598#define PPC_DARN(t, l) stringify_in_c(.long PPC_RAW_DARN(t, l))
599#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_RAW_DCBAL(a, b))
600#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_RAW_DCBZL(a, b))
601#define PPC_DIVDE(t, a, b) stringify_in_c(.long PPC_RAW_DIVDE(t, a, b))
602#define PPC_DIVDEU(t, a, b) stringify_in_c(.long PPC_RAW_DIVDEU(t, a, b))
603#define PPC_DSSALL stringify_in_c(.long PPC_INST_DSSALL)
604#define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh))
605#define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_RAW_STQCX(t, a, b))
606#define PPC_MADDHD(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHD(t, a, b, c))
607#define PPC_MADDHDU(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDHDU(t, a, b, c))
608#define PPC_MADDLD(t, a, b, c) stringify_in_c(.long PPC_RAW_MADDLD(t, a, b, c))
609#define PPC_MSGSND(b) stringify_in_c(.long PPC_RAW_MSGSND(b))
610#define PPC_MSGSYNC stringify_in_c(.long PPC_RAW_MSGSYNC)
611#define PPC_MSGCLR(b) stringify_in_c(.long PPC_RAW_MSGCLR(b))
612#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_RAW_MSGSNDP(b))
613#define PPC_MSGCLRP(b) stringify_in_c(.long PPC_RAW_MSGCLRP(b))
614#define PPC_PASTE(a, b) stringify_in_c(.long PPC_RAW_PASTE(a, b))
615#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_RAW_POPCNTB(a, s))
616#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_RAW_POPCNTD(a, s))
617#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_RAW_POPCNTW(a, s))
618#define PPC_RFCI stringify_in_c(.long PPC_RAW_RFCI)
619#define PPC_RFDI stringify_in_c(.long PPC_RAW_RFDI)
620#define PPC_RFMCI stringify_in_c(.long PPC_RAW_RFMCI)
621#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_RAW_TLBILX(t, a, b))
622#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
623#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
624#define PPC_TLBILX_LPID stringify_in_c(.long PPC_RAW_TLBILX_LPID)
625#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
626#define PPC_WAIT_v203 stringify_in_c(.long PPC_RAW_WAIT_v203)
627#define PPC_WAIT(w, p) stringify_in_c(.long PPC_RAW_WAIT(w, p))
628#define PPC_TLBIE(lp, a) stringify_in_c(.long PPC_RAW_TLBIE(lp, a))
629#define PPC_TLBIE_5(rb, rs, ric, prs, r) \
630 stringify_in_c(.long PPC_RAW_TLBIE_5(rb, rs, ric, prs, r))
631#define PPC_TLBIEL(rb,rs,ric,prs,r) \
632 stringify_in_c(.long PPC_RAW_TLBIEL(rb, rs, ric, prs, r))
633#define PPC_TLBIEL_v205(rb, l) stringify_in_c(.long PPC_RAW_TLBIEL_v205(rb, l))
634#define PPC_TLBSRX_DOT(a, b) stringify_in_c(.long PPC_RAW_TLBSRX_DOT(a, b))
635#define PPC_TLBIVAX(a, b) stringify_in_c(.long PPC_RAW_TLBIVAX(a, b))
636
637#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_RAW_ERATWE(s, a, w))
638#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_RAW_ERATRE(a, a, w))
639#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_RAW_ERATILX(t, a, b))
640#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_RAW_ERATIVAX(s, a, b))
641#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_RAW_ERATSX(t, a, w))
642#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_RAW_ERATSX_DOT(t, a, w))
643#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_RAW_SLBFEE_DOT(t, b))
644#define __PPC_SLBFEE_DOT(t, b) stringify_in_c(.long __PPC_RAW_SLBFEE_DOT(t, b))
645#define PPC_ICBT(c, a, b) stringify_in_c(.long PPC_RAW_ICBT(c, a, b))
646/* PASemi instructions */
647#define LBZCIX(t, a, b) stringify_in_c(.long PPC_RAW_LBZCIX(t, a, b))
648#define STBCIX(s, a, b) stringify_in_c(.long PPC_RAW_STBCIX(s, a, b))
649#define PPC_DCBFPS(a, b) stringify_in_c(.long PPC_RAW_DCBFPS(a, b))
650#define PPC_DCBSTPS(a, b) stringify_in_c(.long PPC_RAW_DCBSTPS(a, b))
651#define PPC_PHWSYNC stringify_in_c(.long PPC_RAW_PHWSYNC)
652#define PPC_PLWSYNC stringify_in_c(.long PPC_RAW_PLWSYNC)
653#define STXVD2X(s, a, b) stringify_in_c(.long PPC_RAW_STXVD2X(s, a, b))
654#define LXVD2X(s, a, b) stringify_in_c(.long PPC_RAW_LXVD2X(s, a, b))
655#define MFVRD(a, t) stringify_in_c(.long PPC_RAW_MFVRD(a, t))
656#define MTVRD(t, a) stringify_in_c(.long PPC_RAW_MTVRD(t, a))
657#define VPMSUMW(t, a, b) stringify_in_c(.long PPC_RAW_VPMSUMW(t, a, b))
658#define VPMSUMD(t, a, b) stringify_in_c(.long PPC_RAW_VPMSUMD(t, a, b))
659#define XXLOR(t, a, b) stringify_in_c(.long PPC_RAW_XXLOR(t, a, b))
660#define XXSWAPD(t, a) stringify_in_c(.long PPC_RAW_XXSWAPD(t, a))
661#define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_RAW_XVCPSGNDP(t, a, b)))
662
663#define VPERMXOR(vrt, vra, vrb, vrc) \
664 stringify_in_c(.long (PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc)))
665
666#define PPC_NAP stringify_in_c(.long PPC_RAW_NAP)
667#define PPC_SLEEP stringify_in_c(.long PPC_RAW_SLEEP)
668#define PPC_WINKLE stringify_in_c(.long PPC_RAW_WINKLE)
669
670#define PPC_STOP stringify_in_c(.long PPC_RAW_STOP)
671
672/* BHRB instructions */
673#define PPC_CLRBHRB stringify_in_c(.long PPC_RAW_CLRBHRB)
674#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_RAW_MFBHRBE(r, n))
675
676/* Transactional memory instructions */
677#define TRECHKPT stringify_in_c(.long PPC_RAW_TRECHKPT)
678#define TRECLAIM(r) stringify_in_c(.long PPC_RAW_TRECLAIM(r))
679#define TABORT(r) stringify_in_c(.long PPC_RAW_TABORT(r))
680
681/* book3e thread control instructions */
682#define MTTMR(tmr, r) stringify_in_c(.long PPC_RAW_MTTMR(tmr, r))
683#define MFTMR(tmr, r) stringify_in_c(.long PPC_RAW_MFTMR(tmr, r))
684
685/* Coprocessor instructions */
686#define PPC_ICSWX(s, a, b) stringify_in_c(.long PPC_RAW_ICSWX(s, a, b))
687#define PPC_ICSWEPX(s, a, b) stringify_in_c(.long PPC_RAW_ICSWEPX(s, a, b))
688
689#define PPC_SLBIA(IH) stringify_in_c(.long PPC_RAW_SLBIA(IH))
690
691/*
692 * These may only be used on ISA v3.0 or later (aka. CPU_FTR_ARCH_300, radix
693 * implies CPU_FTR_ARCH_300). USER/GUEST invalidates may only be used by radix
694 * mode (on HPT these would also invalidate various SLBEs which may not be
695 * desired).
696 */
697#define PPC_ISA_3_0_INVALIDATE_ERAT PPC_SLBIA(7)
698#define PPC_RADIX_INVALIDATE_ERAT_USER PPC_SLBIA(3)
699#define PPC_RADIX_INVALIDATE_ERAT_GUEST PPC_SLBIA(6)
700
701#define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb))
702
703#define VCMPEQUB_RC(vrt, vra, vrb) stringify_in_c(.long PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb))
704
705#endif /* _ASM_POWERPC_PPC_OPCODE_H */
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * provides masks and opcode images for use by code generation, emulation
10 * and for instructions that older assemblers might not know about
11 */
12#ifndef _ASM_POWERPC_PPC_OPCODE_H
13#define _ASM_POWERPC_PPC_OPCODE_H
14
15#include <linux/stringify.h>
16#include <asm/asm-compat.h>
17
18#define __REG_R0 0
19#define __REG_R1 1
20#define __REG_R2 2
21#define __REG_R3 3
22#define __REG_R4 4
23#define __REG_R5 5
24#define __REG_R6 6
25#define __REG_R7 7
26#define __REG_R8 8
27#define __REG_R9 9
28#define __REG_R10 10
29#define __REG_R11 11
30#define __REG_R12 12
31#define __REG_R13 13
32#define __REG_R14 14
33#define __REG_R15 15
34#define __REG_R16 16
35#define __REG_R17 17
36#define __REG_R18 18
37#define __REG_R19 19
38#define __REG_R20 20
39#define __REG_R21 21
40#define __REG_R22 22
41#define __REG_R23 23
42#define __REG_R24 24
43#define __REG_R25 25
44#define __REG_R26 26
45#define __REG_R27 27
46#define __REG_R28 28
47#define __REG_R29 29
48#define __REG_R30 30
49#define __REG_R31 31
50
51#define __REGA0_0 0
52#define __REGA0_R1 1
53#define __REGA0_R2 2
54#define __REGA0_R3 3
55#define __REGA0_R4 4
56#define __REGA0_R5 5
57#define __REGA0_R6 6
58#define __REGA0_R7 7
59#define __REGA0_R8 8
60#define __REGA0_R9 9
61#define __REGA0_R10 10
62#define __REGA0_R11 11
63#define __REGA0_R12 12
64#define __REGA0_R13 13
65#define __REGA0_R14 14
66#define __REGA0_R15 15
67#define __REGA0_R16 16
68#define __REGA0_R17 17
69#define __REGA0_R18 18
70#define __REGA0_R19 19
71#define __REGA0_R20 20
72#define __REGA0_R21 21
73#define __REGA0_R22 22
74#define __REGA0_R23 23
75#define __REGA0_R24 24
76#define __REGA0_R25 25
77#define __REGA0_R26 26
78#define __REGA0_R27 27
79#define __REGA0_R28 28
80#define __REGA0_R29 29
81#define __REGA0_R30 30
82#define __REGA0_R31 31
83
84/* opcode and xopcode for instructions */
85#define OP_TRAP 3
86#define OP_TRAP_64 2
87
88#define OP_31_XOP_TRAP 4
89#define OP_31_XOP_LDX 21
90#define OP_31_XOP_LWZX 23
91#define OP_31_XOP_LDUX 53
92#define OP_31_XOP_DCBST 54
93#define OP_31_XOP_LWZUX 55
94#define OP_31_XOP_TRAP_64 68
95#define OP_31_XOP_DCBF 86
96#define OP_31_XOP_LBZX 87
97#define OP_31_XOP_STDX 149
98#define OP_31_XOP_STWX 151
99#define OP_31_XOP_STDUX 181
100#define OP_31_XOP_STWUX 183
101#define OP_31_XOP_STBX 215
102#define OP_31_XOP_LBZUX 119
103#define OP_31_XOP_STBUX 247
104#define OP_31_XOP_LHZX 279
105#define OP_31_XOP_LHZUX 311
106#define OP_31_XOP_MSGSNDP 142
107#define OP_31_XOP_MSGCLRP 174
108#define OP_31_XOP_MFSPR 339
109#define OP_31_XOP_LWAX 341
110#define OP_31_XOP_LHAX 343
111#define OP_31_XOP_LWAUX 373
112#define OP_31_XOP_LHAUX 375
113#define OP_31_XOP_STHX 407
114#define OP_31_XOP_STHUX 439
115#define OP_31_XOP_MTSPR 467
116#define OP_31_XOP_DCBI 470
117#define OP_31_XOP_LDBRX 532
118#define OP_31_XOP_LWBRX 534
119#define OP_31_XOP_TLBSYNC 566
120#define OP_31_XOP_STDBRX 660
121#define OP_31_XOP_STWBRX 662
122#define OP_31_XOP_STFSX 663
123#define OP_31_XOP_STFSUX 695
124#define OP_31_XOP_STFDX 727
125#define OP_31_XOP_STFDUX 759
126#define OP_31_XOP_LHBRX 790
127#define OP_31_XOP_LFIWAX 855
128#define OP_31_XOP_LFIWZX 887
129#define OP_31_XOP_STHBRX 918
130#define OP_31_XOP_STFIWX 983
131
132/* VSX Scalar Load Instructions */
133#define OP_31_XOP_LXSDX 588
134#define OP_31_XOP_LXSSPX 524
135#define OP_31_XOP_LXSIWAX 76
136#define OP_31_XOP_LXSIWZX 12
137
138/* VSX Scalar Store Instructions */
139#define OP_31_XOP_STXSDX 716
140#define OP_31_XOP_STXSSPX 652
141#define OP_31_XOP_STXSIWX 140
142
143/* VSX Vector Load Instructions */
144#define OP_31_XOP_LXVD2X 844
145#define OP_31_XOP_LXVW4X 780
146
147/* VSX Vector Load and Splat Instruction */
148#define OP_31_XOP_LXVDSX 332
149
150/* VSX Vector Store Instructions */
151#define OP_31_XOP_STXVD2X 972
152#define OP_31_XOP_STXVW4X 908
153
154#define OP_31_XOP_LFSX 535
155#define OP_31_XOP_LFSUX 567
156#define OP_31_XOP_LFDX 599
157#define OP_31_XOP_LFDUX 631
158
159/* VMX Vector Load Instructions */
160#define OP_31_XOP_LVX 103
161
162/* VMX Vector Store Instructions */
163#define OP_31_XOP_STVX 231
164
165#define OP_LWZ 32
166#define OP_STFS 52
167#define OP_STFSU 53
168#define OP_STFD 54
169#define OP_STFDU 55
170#define OP_LD 58
171#define OP_LWZU 33
172#define OP_LBZ 34
173#define OP_LBZU 35
174#define OP_STW 36
175#define OP_STWU 37
176#define OP_STD 62
177#define OP_STB 38
178#define OP_STBU 39
179#define OP_LHZ 40
180#define OP_LHZU 41
181#define OP_LHA 42
182#define OP_LHAU 43
183#define OP_STH 44
184#define OP_STHU 45
185#define OP_LMW 46
186#define OP_STMW 47
187#define OP_LFS 48
188#define OP_LFSU 49
189#define OP_LFD 50
190#define OP_LFDU 51
191#define OP_STFS 52
192#define OP_STFSU 53
193#define OP_STFD 54
194#define OP_STFDU 55
195#define OP_LQ 56
196
197/* sorted alphabetically */
198#define PPC_INST_BHRBE 0x7c00025c
199#define PPC_INST_CLRBHRB 0x7c00035c
200#define PPC_INST_COPY 0x7c20060c
201#define PPC_INST_CP_ABORT 0x7c00068c
202#define PPC_INST_DARN 0x7c0005e6
203#define PPC_INST_DCBA 0x7c0005ec
204#define PPC_INST_DCBA_MASK 0xfc0007fe
205#define PPC_INST_DCBAL 0x7c2005ec
206#define PPC_INST_DCBZL 0x7c2007ec
207#define PPC_INST_ICBT 0x7c00002c
208#define PPC_INST_ICSWX 0x7c00032d
209#define PPC_INST_ICSWEPX 0x7c00076d
210#define PPC_INST_ISEL 0x7c00001e
211#define PPC_INST_ISEL_MASK 0xfc00003e
212#define PPC_INST_LDARX 0x7c0000a8
213#define PPC_INST_STDCX 0x7c0001ad
214#define PPC_INST_LQARX 0x7c000228
215#define PPC_INST_STQCX 0x7c00016d
216#define PPC_INST_LSWI 0x7c0004aa
217#define PPC_INST_LSWX 0x7c00042a
218#define PPC_INST_LWARX 0x7c000028
219#define PPC_INST_STWCX 0x7c00012d
220#define PPC_INST_LWSYNC 0x7c2004ac
221#define PPC_INST_SYNC 0x7c0004ac
222#define PPC_INST_SYNC_MASK 0xfc0007fe
223#define PPC_INST_ISYNC 0x4c00012c
224#define PPC_INST_LXVD2X 0x7c000698
225#define PPC_INST_MCRXR 0x7c000400
226#define PPC_INST_MCRXR_MASK 0xfc0007fe
227#define PPC_INST_MFSPR_PVR 0x7c1f42a6
228#define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe
229#define PPC_INST_MFTMR 0x7c0002dc
230#define PPC_INST_MSGSND 0x7c00019c
231#define PPC_INST_MSGCLR 0x7c0001dc
232#define PPC_INST_MSGSYNC 0x7c0006ec
233#define PPC_INST_MSGSNDP 0x7c00011c
234#define PPC_INST_MSGCLRP 0x7c00015c
235#define PPC_INST_MTMSRD 0x7c000164
236#define PPC_INST_MTTMR 0x7c0003dc
237#define PPC_INST_NOP 0x60000000
238#define PPC_INST_PASTE 0x7c20070d
239#define PPC_INST_POPCNTB 0x7c0000f4
240#define PPC_INST_POPCNTB_MASK 0xfc0007fe
241#define PPC_INST_POPCNTD 0x7c0003f4
242#define PPC_INST_POPCNTW 0x7c0002f4
243#define PPC_INST_RFEBB 0x4c000124
244#define PPC_INST_RFCI 0x4c000066
245#define PPC_INST_RFDI 0x4c00004e
246#define PPC_INST_RFID 0x4c000024
247#define PPC_INST_RFMCI 0x4c00004c
248#define PPC_INST_MFSPR 0x7c0002a6
249#define PPC_INST_MFSPR_DSCR 0x7c1102a6
250#define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe
251#define PPC_INST_MTSPR_DSCR 0x7c1103a6
252#define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe
253#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
254#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe
255#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
256#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe
257#define PPC_INST_MFVSRD 0x7c000066
258#define PPC_INST_MTVSRD 0x7c000166
259#define PPC_INST_SLBFEE 0x7c0007a7
260#define PPC_INST_SLBIA 0x7c0003e4
261
262#define PPC_INST_STRING 0x7c00042a
263#define PPC_INST_STRING_MASK 0xfc0007fe
264#define PPC_INST_STRING_GEN_MASK 0xfc00067e
265
266#define PPC_INST_STSWI 0x7c0005aa
267#define PPC_INST_STSWX 0x7c00052a
268#define PPC_INST_STXVD2X 0x7c000798
269#define PPC_INST_TLBIE 0x7c000264
270#define PPC_INST_TLBIEL 0x7c000224
271#define PPC_INST_TLBILX 0x7c000024
272#define PPC_INST_WAIT 0x7c00007c
273#define PPC_INST_TLBIVAX 0x7c000624
274#define PPC_INST_TLBSRX_DOT 0x7c0006a5
275#define PPC_INST_VPMSUMW 0x10000488
276#define PPC_INST_VPMSUMD 0x100004c8
277#define PPC_INST_VPERMXOR 0x1000002d
278#define PPC_INST_XXLOR 0xf0000490
279#define PPC_INST_XXSWAPD 0xf0000250
280#define PPC_INST_XVCPSGNDP 0xf0000780
281#define PPC_INST_TRECHKPT 0x7c0007dd
282#define PPC_INST_TRECLAIM 0x7c00075d
283#define PPC_INST_TABORT 0x7c00071d
284#define PPC_INST_TSR 0x7c0005dd
285
286#define PPC_INST_NAP 0x4c000364
287#define PPC_INST_SLEEP 0x4c0003a4
288#define PPC_INST_WINKLE 0x4c0003e4
289
290#define PPC_INST_STOP 0x4c0002e4
291
292/* A2 specific instructions */
293#define PPC_INST_ERATWE 0x7c0001a6
294#define PPC_INST_ERATRE 0x7c000166
295#define PPC_INST_ERATILX 0x7c000066
296#define PPC_INST_ERATIVAX 0x7c000666
297#define PPC_INST_ERATSX 0x7c000126
298#define PPC_INST_ERATSX_DOT 0x7c000127
299
300/* Misc instructions for BPF compiler */
301#define PPC_INST_LBZ 0x88000000
302#define PPC_INST_LD 0xe8000000
303#define PPC_INST_LHZ 0xa0000000
304#define PPC_INST_LWZ 0x80000000
305#define PPC_INST_LHBRX 0x7c00062c
306#define PPC_INST_LDBRX 0x7c000428
307#define PPC_INST_STB 0x98000000
308#define PPC_INST_STH 0xb0000000
309#define PPC_INST_STD 0xf8000000
310#define PPC_INST_STDU 0xf8000001
311#define PPC_INST_STW 0x90000000
312#define PPC_INST_STWU 0x94000000
313#define PPC_INST_MFLR 0x7c0802a6
314#define PPC_INST_MTLR 0x7c0803a6
315#define PPC_INST_MTCTR 0x7c0903a6
316#define PPC_INST_CMPWI 0x2c000000
317#define PPC_INST_CMPDI 0x2c200000
318#define PPC_INST_CMPW 0x7c000000
319#define PPC_INST_CMPD 0x7c200000
320#define PPC_INST_CMPLW 0x7c000040
321#define PPC_INST_CMPLD 0x7c200040
322#define PPC_INST_CMPLWI 0x28000000
323#define PPC_INST_CMPLDI 0x28200000
324#define PPC_INST_ADDI 0x38000000
325#define PPC_INST_ADDIS 0x3c000000
326#define PPC_INST_ADD 0x7c000214
327#define PPC_INST_SUB 0x7c000050
328#define PPC_INST_BLR 0x4e800020
329#define PPC_INST_BLRL 0x4e800021
330#define PPC_INST_BCTR 0x4e800420
331#define PPC_INST_MULLD 0x7c0001d2
332#define PPC_INST_MULLW 0x7c0001d6
333#define PPC_INST_MULHWU 0x7c000016
334#define PPC_INST_MULLI 0x1c000000
335#define PPC_INST_DIVWU 0x7c000396
336#define PPC_INST_DIVD 0x7c0003d2
337#define PPC_INST_RLWINM 0x54000000
338#define PPC_INST_RLWIMI 0x50000000
339#define PPC_INST_RLDICL 0x78000000
340#define PPC_INST_RLDICR 0x78000004
341#define PPC_INST_SLW 0x7c000030
342#define PPC_INST_SLD 0x7c000036
343#define PPC_INST_SRW 0x7c000430
344#define PPC_INST_SRD 0x7c000436
345#define PPC_INST_SRAD 0x7c000634
346#define PPC_INST_SRADI 0x7c000674
347#define PPC_INST_AND 0x7c000038
348#define PPC_INST_ANDDOT 0x7c000039
349#define PPC_INST_OR 0x7c000378
350#define PPC_INST_XOR 0x7c000278
351#define PPC_INST_ANDI 0x70000000
352#define PPC_INST_ORI 0x60000000
353#define PPC_INST_ORIS 0x64000000
354#define PPC_INST_XORI 0x68000000
355#define PPC_INST_XORIS 0x6c000000
356#define PPC_INST_NEG 0x7c0000d0
357#define PPC_INST_EXTSW 0x7c0007b4
358#define PPC_INST_BRANCH 0x48000000
359#define PPC_INST_BRANCH_COND 0x40800000
360#define PPC_INST_LBZCIX 0x7c0006aa
361#define PPC_INST_STBCIX 0x7c0007aa
362#define PPC_INST_LWZX 0x7c00002e
363#define PPC_INST_LFSX 0x7c00042e
364#define PPC_INST_STFSX 0x7c00052e
365#define PPC_INST_LFDX 0x7c0004ae
366#define PPC_INST_STFDX 0x7c0005ae
367#define PPC_INST_LVX 0x7c0000ce
368#define PPC_INST_STVX 0x7c0001ce
369
370/* macros to insert fields into opcodes */
371#define ___PPC_RA(a) (((a) & 0x1f) << 16)
372#define ___PPC_RB(b) (((b) & 0x1f) << 11)
373#define ___PPC_RS(s) (((s) & 0x1f) << 21)
374#define ___PPC_RT(t) ___PPC_RS(t)
375#define ___PPC_R(r) (((r) & 0x1) << 16)
376#define ___PPC_PRS(prs) (((prs) & 0x1) << 17)
377#define ___PPC_RIC(ric) (((ric) & 0x3) << 18)
378#define __PPC_RA(a) ___PPC_RA(__REG_##a)
379#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
380#define __PPC_RB(b) ___PPC_RB(__REG_##b)
381#define __PPC_RS(s) ___PPC_RS(__REG_##s)
382#define __PPC_RT(t) ___PPC_RT(__REG_##t)
383#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
384#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
385#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
386#define __PPC_XT(s) __PPC_XS(s)
387#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
388#define __PPC_WC(w) (((w) & 0x3) << 21)
389#define __PPC_WS(w) (((w) & 0x1f) << 11)
390#define __PPC_SH(s) __PPC_WS(s)
391#define __PPC_SH64(s) (__PPC_SH(s) | (((s) & 0x20) >> 4))
392#define __PPC_MB(s) (((s) & 0x1f) << 6)
393#define __PPC_ME(s) (((s) & 0x1f) << 1)
394#define __PPC_MB64(s) (__PPC_MB(s) | ((s) & 0x20))
395#define __PPC_ME64(s) __PPC_MB64(s)
396#define __PPC_BI(s) (((s) & 0x1f) << 16)
397#define __PPC_CT(t) (((t) & 0x0f) << 21)
398#define __PPC_SPR(r) ((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11))
399
400/*
401 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
402 * larx with EH set as an illegal instruction.
403 */
404#ifdef CONFIG_PPC64
405#define __PPC_EH(eh) (((eh) & 0x1) << 0)
406#else
407#define __PPC_EH(eh) 0
408#endif
409
410/* Deal with instructions that older assemblers aren't aware of */
411#define PPC_CP_ABORT stringify_in_c(.long PPC_INST_CP_ABORT)
412#define PPC_COPY(a, b) stringify_in_c(.long PPC_INST_COPY | \
413 ___PPC_RA(a) | ___PPC_RB(b))
414#define PPC_DARN(t, l) stringify_in_c(.long PPC_INST_DARN | \
415 ___PPC_RT(t) | \
416 (((l) & 0x3) << 16))
417#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \
418 __PPC_RA(a) | __PPC_RB(b))
419#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
420 __PPC_RA(a) | __PPC_RB(b))
421#define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LQARX | \
422 ___PPC_RT(t) | ___PPC_RA(a) | \
423 ___PPC_RB(b) | __PPC_EH(eh))
424#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
425 ___PPC_RT(t) | ___PPC_RA(a) | \
426 ___PPC_RB(b) | __PPC_EH(eh))
427#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
428 ___PPC_RT(t) | ___PPC_RA(a) | \
429 ___PPC_RB(b) | __PPC_EH(eh))
430#define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_INST_STQCX | \
431 ___PPC_RT(t) | ___PPC_RA(a) | \
432 ___PPC_RB(b))
433#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
434 ___PPC_RB(b))
435#define PPC_MSGSYNC stringify_in_c(.long PPC_INST_MSGSYNC)
436#define PPC_MSGCLR(b) stringify_in_c(.long PPC_INST_MSGCLR | \
437 ___PPC_RB(b))
438#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \
439 ___PPC_RB(b))
440#define PPC_MSGCLRP(b) stringify_in_c(.long PPC_INST_MSGCLRP | \
441 ___PPC_RB(b))
442#define PPC_PASTE(a, b) stringify_in_c(.long PPC_INST_PASTE | \
443 ___PPC_RA(a) | ___PPC_RB(b))
444#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
445 __PPC_RA(a) | __PPC_RS(s))
446#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
447 __PPC_RA(a) | __PPC_RS(s))
448#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \
449 __PPC_RA(a) | __PPC_RS(s))
450#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
451#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
452#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
453#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
454 __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
455#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
456#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
457#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
458#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
459 __PPC_WC(w))
460#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
461 ___PPC_RB(a) | ___PPC_RS(lp))
462#define PPC_TLBIE_5(rb,rs,ric,prs,r) \
463 stringify_in_c(.long PPC_INST_TLBIE | \
464 ___PPC_RB(rb) | ___PPC_RS(rs) | \
465 ___PPC_RIC(ric) | ___PPC_PRS(prs) | \
466 ___PPC_R(r))
467#define PPC_TLBIEL(rb,rs,ric,prs,r) \
468 stringify_in_c(.long PPC_INST_TLBIEL | \
469 ___PPC_RB(rb) | ___PPC_RS(rs) | \
470 ___PPC_RIC(ric) | ___PPC_PRS(prs) | \
471 ___PPC_R(r))
472#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
473 __PPC_RA0(a) | __PPC_RB(b))
474#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
475 __PPC_RA0(a) | __PPC_RB(b))
476
477#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
478 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
479#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
480 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
481#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
482 __PPC_T_TLB(t) | __PPC_RA0(a) | \
483 __PPC_RB(b))
484#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
485 __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
486#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
487 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
488#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
489 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
490#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
491 __PPC_RT(t) | __PPC_RB(b))
492#define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \
493 __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
494/* PASemi instructions */
495#define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \
496 __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
497#define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \
498 __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
499
500/*
501 * Define what the VSX XX1 form instructions will look like, then add
502 * the 128 bit load store instructions based on that.
503 */
504#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
505#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
506#define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \
507 VSX_XX1((s), a, b))
508#define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \
509 VSX_XX1((s), a, b))
510#define MFVRD(a, t) stringify_in_c(.long PPC_INST_MFVSRD | \
511 VSX_XX1((t)+32, a, R0))
512#define MTVRD(t, a) stringify_in_c(.long PPC_INST_MTVSRD | \
513 VSX_XX1((t)+32, a, R0))
514#define VPMSUMW(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMW | \
515 VSX_XX3((t), a, b))
516#define VPMSUMD(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMD | \
517 VSX_XX3((t), a, b))
518#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
519 VSX_XX3((t), a, b))
520#define XXSWAPD(t, a) stringify_in_c(.long PPC_INST_XXSWAPD | \
521 VSX_XX3((t), a, a))
522#define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
523 VSX_XX3((t), (a), (b))))
524
525#define VPERMXOR(vrt, vra, vrb, vrc) \
526 stringify_in_c(.long (PPC_INST_VPERMXOR | \
527 ___PPC_RT(vrt) | ___PPC_RA(vra) | \
528 ___PPC_RB(vrb) | (((vrc) & 0x1f) << 6)))
529
530#define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
531#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
532#define PPC_WINKLE stringify_in_c(.long PPC_INST_WINKLE)
533
534#define PPC_STOP stringify_in_c(.long PPC_INST_STOP)
535
536/* BHRB instructions */
537#define PPC_CLRBHRB stringify_in_c(.long PPC_INST_CLRBHRB)
538#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \
539 __PPC_RT(r) | \
540 (((n) & 0x3ff) << 11))
541
542/* Transactional memory instructions */
543#define TRECHKPT stringify_in_c(.long PPC_INST_TRECHKPT)
544#define TRECLAIM(r) stringify_in_c(.long PPC_INST_TRECLAIM \
545 | __PPC_RA(r))
546#define TABORT(r) stringify_in_c(.long PPC_INST_TABORT \
547 | __PPC_RA(r))
548
549/* book3e thread control instructions */
550#define TMRN(x) ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
551#define MTTMR(tmr, r) stringify_in_c(.long PPC_INST_MTTMR | \
552 TMRN(tmr) | ___PPC_RS(r))
553#define MFTMR(tmr, r) stringify_in_c(.long PPC_INST_MFTMR | \
554 TMRN(tmr) | ___PPC_RT(r))
555
556/* Coprocessor instructions */
557#define PPC_ICSWX(s, a, b) stringify_in_c(.long PPC_INST_ICSWX | \
558 ___PPC_RS(s) | \
559 ___PPC_RA(a) | \
560 ___PPC_RB(b))
561#define PPC_ICSWEPX(s, a, b) stringify_in_c(.long PPC_INST_ICSWEPX | \
562 ___PPC_RS(s) | \
563 ___PPC_RA(a) | \
564 ___PPC_RB(b))
565
566#define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA | \
567 ((IH & 0x7) << 21))
568#define PPC_INVALIDATE_ERAT PPC_SLBIA(7)
569
570#endif /* _ASM_POWERPC_PPC_OPCODE_H */