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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * arch/arm/include/asm/assembler.h
4 *
5 * Copyright (C) 1996-2000 Russell King
6 *
7 * This file contains arm architecture specific defines
8 * for the different processors.
9 *
10 * Do not include any C declarations in this file - it is included by
11 * assembler source.
12 */
13#ifndef __ASM_ASSEMBLER_H__
14#define __ASM_ASSEMBLER_H__
15
16#ifndef __ASSEMBLY__
17#error "Only include this from assembly code"
18#endif
19
20#include <asm/ptrace.h>
21#include <asm/opcodes-virt.h>
22#include <asm/asm-offsets.h>
23#include <asm/page.h>
24#include <asm/thread_info.h>
25#include <asm/uaccess-asm.h>
26
27#define IOMEM(x) (x)
28
29/*
30 * Endian independent macros for shifting bytes within registers.
31 */
32#ifndef __ARMEB__
33#define lspull lsr
34#define lspush lsl
35#define get_byte_0 lsl #0
36#define get_byte_1 lsr #8
37#define get_byte_2 lsr #16
38#define get_byte_3 lsr #24
39#define put_byte_0 lsl #0
40#define put_byte_1 lsl #8
41#define put_byte_2 lsl #16
42#define put_byte_3 lsl #24
43#else
44#define lspull lsl
45#define lspush lsr
46#define get_byte_0 lsr #24
47#define get_byte_1 lsr #16
48#define get_byte_2 lsr #8
49#define get_byte_3 lsl #0
50#define put_byte_0 lsl #24
51#define put_byte_1 lsl #16
52#define put_byte_2 lsl #8
53#define put_byte_3 lsl #0
54#endif
55
56/* Select code for any configuration running in BE8 mode */
57#ifdef CONFIG_CPU_ENDIAN_BE8
58#define ARM_BE8(code...) code
59#else
60#define ARM_BE8(code...)
61#endif
62
63/*
64 * Data preload for architectures that support it
65 */
66#if __LINUX_ARM_ARCH__ >= 5
67#define PLD(code...) code
68#else
69#define PLD(code...)
70#endif
71
72/*
73 * This can be used to enable code to cacheline align the destination
74 * pointer when bulk writing to memory. Experiments on StrongARM and
75 * XScale didn't show this a worthwhile thing to do when the cache is not
76 * set to write-allocate (this would need further testing on XScale when WA
77 * is used).
78 *
79 * On Feroceon there is much to gain however, regardless of cache mode.
80 */
81#ifdef CONFIG_CPU_FEROCEON
82#define CALGN(code...) code
83#else
84#define CALGN(code...)
85#endif
86
87#define IMM12_MASK 0xfff
88
89/* the frame pointer used for stack unwinding */
90ARM( fpreg .req r11 )
91THUMB( fpreg .req r7 )
92
93/*
94 * Enable and disable interrupts
95 */
96#if __LINUX_ARM_ARCH__ >= 6
97 .macro disable_irq_notrace
98 cpsid i
99 .endm
100
101 .macro enable_irq_notrace
102 cpsie i
103 .endm
104#else
105 .macro disable_irq_notrace
106 msr cpsr_c, #PSR_I_BIT | SVC_MODE
107 .endm
108
109 .macro enable_irq_notrace
110 msr cpsr_c, #SVC_MODE
111 .endm
112#endif
113
114#if __LINUX_ARM_ARCH__ < 7
115 .macro dsb, args
116 mcr p15, 0, r0, c7, c10, 4
117 .endm
118
119 .macro isb, args
120 mcr p15, 0, r0, c7, c5, 4
121 .endm
122#endif
123
124 .macro asm_trace_hardirqs_off, save=1
125#if defined(CONFIG_TRACE_IRQFLAGS)
126 .if \save
127 stmdb sp!, {r0-r3, ip, lr}
128 .endif
129 bl trace_hardirqs_off
130 .if \save
131 ldmia sp!, {r0-r3, ip, lr}
132 .endif
133#endif
134 .endm
135
136 .macro asm_trace_hardirqs_on, cond=al, save=1
137#if defined(CONFIG_TRACE_IRQFLAGS)
138 /*
139 * actually the registers should be pushed and pop'd conditionally, but
140 * after bl the flags are certainly clobbered
141 */
142 .if \save
143 stmdb sp!, {r0-r3, ip, lr}
144 .endif
145 bl\cond trace_hardirqs_on
146 .if \save
147 ldmia sp!, {r0-r3, ip, lr}
148 .endif
149#endif
150 .endm
151
152 .macro disable_irq, save=1
153 disable_irq_notrace
154 asm_trace_hardirqs_off \save
155 .endm
156
157 .macro enable_irq
158 asm_trace_hardirqs_on
159 enable_irq_notrace
160 .endm
161/*
162 * Save the current IRQ state and disable IRQs. Note that this macro
163 * assumes FIQs are enabled, and that the processor is in SVC mode.
164 */
165 .macro save_and_disable_irqs, oldcpsr
166#ifdef CONFIG_CPU_V7M
167 mrs \oldcpsr, primask
168#else
169 mrs \oldcpsr, cpsr
170#endif
171 disable_irq
172 .endm
173
174 .macro save_and_disable_irqs_notrace, oldcpsr
175#ifdef CONFIG_CPU_V7M
176 mrs \oldcpsr, primask
177#else
178 mrs \oldcpsr, cpsr
179#endif
180 disable_irq_notrace
181 .endm
182
183/*
184 * Restore interrupt state previously stored in a register. We don't
185 * guarantee that this will preserve the flags.
186 */
187 .macro restore_irqs_notrace, oldcpsr
188#ifdef CONFIG_CPU_V7M
189 msr primask, \oldcpsr
190#else
191 msr cpsr_c, \oldcpsr
192#endif
193 .endm
194
195 .macro restore_irqs, oldcpsr
196 tst \oldcpsr, #PSR_I_BIT
197 asm_trace_hardirqs_on cond=eq
198 restore_irqs_notrace \oldcpsr
199 .endm
200
201/*
202 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
203 * reference local symbols in the same assembly file which are to be
204 * resolved by the assembler. Other usage is undefined.
205 */
206 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
207 .macro badr\c, rd, sym
208#ifdef CONFIG_THUMB2_KERNEL
209 adr\c \rd, \sym + 1
210#else
211 adr\c \rd, \sym
212#endif
213 .endm
214 .endr
215
216/*
217 * Get current thread_info.
218 */
219 .macro get_thread_info, rd
220 /* thread_info is the first member of struct task_struct */
221 get_current \rd
222 .endm
223
224/*
225 * Increment/decrement the preempt count.
226 */
227#ifdef CONFIG_PREEMPT_COUNT
228 .macro inc_preempt_count, ti, tmp
229 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
230 add \tmp, \tmp, #1 @ increment it
231 str \tmp, [\ti, #TI_PREEMPT]
232 .endm
233
234 .macro dec_preempt_count, ti, tmp
235 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
236 sub \tmp, \tmp, #1 @ decrement it
237 str \tmp, [\ti, #TI_PREEMPT]
238 .endm
239#else
240 .macro inc_preempt_count, ti, tmp
241 .endm
242
243 .macro dec_preempt_count, ti, tmp
244 .endm
245#endif
246
247#define USERL(l, x...) \
2489999: x; \
249 .pushsection __ex_table,"a"; \
250 .align 3; \
251 .long 9999b,l; \
252 .popsection
253
254#define USER(x...) USERL(9001f, x)
255
256#ifdef CONFIG_SMP
257#define ALT_SMP(instr...) \
2589998: instr
259/*
260 * Note: if you get assembler errors from ALT_UP() when building with
261 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
262 * ALT_SMP( W(instr) ... )
263 */
264#define ALT_UP(instr...) \
265 .pushsection ".alt.smp.init", "a" ;\
266 .align 2 ;\
267 .long 9998b - . ;\
2689997: instr ;\
269 .if . - 9997b == 2 ;\
270 nop ;\
271 .endif ;\
272 .if . - 9997b != 4 ;\
273 .error "ALT_UP() content must assemble to exactly 4 bytes";\
274 .endif ;\
275 .popsection
276#define ALT_UP_B(label) \
277 .pushsection ".alt.smp.init", "a" ;\
278 .align 2 ;\
279 .long 9998b - . ;\
280 W(b) . + (label - 9998b) ;\
281 .popsection
282#else
283#define ALT_SMP(instr...)
284#define ALT_UP(instr...) instr
285#define ALT_UP_B(label) b label
286#endif
287
288 /*
289 * this_cpu_offset - load the per-CPU offset of this CPU into
290 * register 'rd'
291 */
292 .macro this_cpu_offset, rd:req
293#ifdef CONFIG_SMP
294ALT_SMP(mrc p15, 0, \rd, c13, c0, 4)
295#ifdef CONFIG_CPU_V6
296ALT_UP_B(.L1_\@)
297.L0_\@:
298 .subsection 1
299.L1_\@: ldr_va \rd, __per_cpu_offset
300 b .L0_\@
301 .previous
302#endif
303#else
304 mov \rd, #0
305#endif
306 .endm
307
308 /*
309 * set_current - store the task pointer of this CPU's current task
310 */
311 .macro set_current, rn:req, tmp:req
312#if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
3139998: mcr p15, 0, \rn, c13, c0, 3 @ set TPIDRURO register
314#ifdef CONFIG_CPU_V6
315ALT_UP_B(.L0_\@)
316 .subsection 1
317.L0_\@: str_va \rn, __current, \tmp
318 b .L1_\@
319 .previous
320.L1_\@:
321#endif
322#else
323 str_va \rn, __current, \tmp
324#endif
325 .endm
326
327 /*
328 * get_current - load the task pointer of this CPU's current task
329 */
330 .macro get_current, rd:req
331#if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
3329998: mrc p15, 0, \rd, c13, c0, 3 @ get TPIDRURO register
333#ifdef CONFIG_CPU_V6
334ALT_UP_B(.L0_\@)
335 .subsection 1
336.L0_\@: ldr_va \rd, __current
337 b .L1_\@
338 .previous
339.L1_\@:
340#endif
341#else
342 ldr_va \rd, __current
343#endif
344 .endm
345
346 /*
347 * reload_current - reload the task pointer of this CPU's current task
348 * into the TLS register
349 */
350 .macro reload_current, t1:req, t2:req
351#if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP)
352#ifdef CONFIG_CPU_V6
353ALT_SMP(nop)
354ALT_UP_B(.L0_\@)
355#endif
356 ldr_this_cpu \t1, __entry_task, \t1, \t2
357 mcr p15, 0, \t1, c13, c0, 3 @ store in TPIDRURO
358.L0_\@:
359#endif
360 .endm
361
362/*
363 * Instruction barrier
364 */
365 .macro instr_sync
366#if __LINUX_ARM_ARCH__ >= 7
367 isb
368#elif __LINUX_ARM_ARCH__ == 6
369 mcr p15, 0, r0, c7, c5, 4
370#endif
371 .endm
372
373/*
374 * SMP data memory barrier
375 */
376 .macro smp_dmb mode
377#ifdef CONFIG_SMP
378#if __LINUX_ARM_ARCH__ >= 7
379 .ifeqs "\mode","arm"
380 ALT_SMP(dmb ish)
381 .else
382 ALT_SMP(W(dmb) ish)
383 .endif
384#elif __LINUX_ARM_ARCH__ == 6
385 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
386#else
387#error Incompatible SMP platform
388#endif
389 .ifeqs "\mode","arm"
390 ALT_UP(nop)
391 .else
392 ALT_UP(W(nop))
393 .endif
394#endif
395 .endm
396
397/*
398 * Raw SMP data memory barrier
399 */
400 .macro __smp_dmb mode
401#if __LINUX_ARM_ARCH__ >= 7
402 .ifeqs "\mode","arm"
403 dmb ish
404 .else
405 W(dmb) ish
406 .endif
407#elif __LINUX_ARM_ARCH__ == 6
408 mcr p15, 0, r0, c7, c10, 5 @ dmb
409#else
410 .error "Incompatible SMP platform"
411#endif
412 .endm
413
414#if defined(CONFIG_CPU_V7M)
415 /*
416 * setmode is used to assert to be in svc mode during boot. For v7-M
417 * this is done in __v7m_setup, so setmode can be empty here.
418 */
419 .macro setmode, mode, reg
420 .endm
421#elif defined(CONFIG_THUMB2_KERNEL)
422 .macro setmode, mode, reg
423 mov \reg, #\mode
424 msr cpsr_c, \reg
425 .endm
426#else
427 .macro setmode, mode, reg
428 msr cpsr_c, #\mode
429 .endm
430#endif
431
432/*
433 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
434 * a scratch register for the macro to overwrite.
435 *
436 * This macro is intended for forcing the CPU into SVC mode at boot time.
437 * you cannot return to the original mode.
438 */
439.macro safe_svcmode_maskall reg:req
440#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
441 mrs \reg , cpsr
442 eor \reg, \reg, #HYP_MODE
443 tst \reg, #MODE_MASK
444 bic \reg , \reg , #MODE_MASK
445 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
446THUMB( orr \reg , \reg , #PSR_T_BIT )
447 bne 1f
448 orr \reg, \reg, #PSR_A_BIT
449 badr lr, 2f
450 msr spsr_cxsf, \reg
451 __MSR_ELR_HYP(14)
452 __ERET
4531: msr cpsr_c, \reg
4542:
455#else
456/*
457 * workaround for possibly broken pre-v6 hardware
458 * (akita, Sharp Zaurus C-1000, PXA270-based)
459 */
460 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
461#endif
462.endm
463
464/*
465 * STRT/LDRT access macros with ARM and Thumb-2 variants
466 */
467#ifdef CONFIG_THUMB2_KERNEL
468
469 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
4709999:
471 .if \inc == 1
472 \instr\()b\t\cond\().w \reg, [\ptr, #\off]
473 .elseif \inc == 4
474 \instr\t\cond\().w \reg, [\ptr, #\off]
475 .else
476 .error "Unsupported inc macro argument"
477 .endif
478
479 .pushsection __ex_table,"a"
480 .align 3
481 .long 9999b, \abort
482 .popsection
483 .endm
484
485 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
486 @ explicit IT instruction needed because of the label
487 @ introduced by the USER macro
488 .ifnc \cond,al
489 .if \rept == 1
490 itt \cond
491 .elseif \rept == 2
492 ittt \cond
493 .else
494 .error "Unsupported rept macro argument"
495 .endif
496 .endif
497
498 @ Slightly optimised to avoid incrementing the pointer twice
499 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
500 .if \rept == 2
501 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
502 .endif
503
504 add\cond \ptr, #\rept * \inc
505 .endm
506
507#else /* !CONFIG_THUMB2_KERNEL */
508
509 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
510 .rept \rept
5119999:
512 .if \inc == 1
513 \instr\()b\t\cond \reg, [\ptr], #\inc
514 .elseif \inc == 4
515 \instr\t\cond \reg, [\ptr], #\inc
516 .else
517 .error "Unsupported inc macro argument"
518 .endif
519
520 .pushsection __ex_table,"a"
521 .align 3
522 .long 9999b, \abort
523 .popsection
524 .endr
525 .endm
526
527#endif /* CONFIG_THUMB2_KERNEL */
528
529 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
530 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
531 .endm
532
533 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
534 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
535 .endm
536
537/* Utility macro for declaring string literals */
538 .macro string name:req, string
539 .type \name , #object
540\name:
541 .asciz "\string"
542 .size \name , . - \name
543 .endm
544
545 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
546 .macro ret\c, reg
547#if __LINUX_ARM_ARCH__ < 6
548 mov\c pc, \reg
549#else
550 .ifeqs "\reg", "lr"
551 bx\c \reg
552 .else
553 mov\c pc, \reg
554 .endif
555#endif
556 .endm
557 .endr
558
559 .macro ret.w, reg
560 ret \reg
561#ifdef CONFIG_THUMB2_KERNEL
562 nop
563#endif
564 .endm
565
566 .macro bug, msg, line
567#ifdef CONFIG_THUMB2_KERNEL
5681: .inst 0xde02
569#else
5701: .inst 0xe7f001f2
571#endif
572#ifdef CONFIG_DEBUG_BUGVERBOSE
573 .pushsection .rodata.str, "aMS", %progbits, 1
5742: .asciz "\msg"
575 .popsection
576 .pushsection __bug_table, "aw"
577 .align 2
578 .word 1b, 2b
579 .hword \line
580 .popsection
581#endif
582 .endm
583
584#ifdef CONFIG_KPROBES
585#define _ASM_NOKPROBE(entry) \
586 .pushsection "_kprobe_blacklist", "aw" ; \
587 .balign 4 ; \
588 .long entry; \
589 .popsection
590#else
591#define _ASM_NOKPROBE(entry)
592#endif
593
594 .macro __adldst_l, op, reg, sym, tmp, c
595 .if __LINUX_ARM_ARCH__ < 7
596 ldr\c \tmp, .La\@
597 .subsection 1
598 .align 2
599.La\@: .long \sym - .Lpc\@
600 .previous
601 .else
602 .ifnb \c
603 THUMB( ittt \c )
604 .endif
605 movw\c \tmp, #:lower16:\sym - .Lpc\@
606 movt\c \tmp, #:upper16:\sym - .Lpc\@
607 .endif
608
609#ifndef CONFIG_THUMB2_KERNEL
610 .set .Lpc\@, . + 8 // PC bias
611 .ifc \op, add
612 add\c \reg, \tmp, pc
613 .else
614 \op\c \reg, [pc, \tmp]
615 .endif
616#else
617.Lb\@: add\c \tmp, \tmp, pc
618 /*
619 * In Thumb-2 builds, the PC bias depends on whether we are currently
620 * emitting into a .arm or a .thumb section. The size of the add opcode
621 * above will be 2 bytes when emitting in Thumb mode and 4 bytes when
622 * emitting in ARM mode, so let's use this to account for the bias.
623 */
624 .set .Lpc\@, . + (. - .Lb\@)
625
626 .ifnc \op, add
627 \op\c \reg, [\tmp]
628 .endif
629#endif
630 .endm
631
632 /*
633 * mov_l - move a constant value or [relocated] address into a register
634 */
635 .macro mov_l, dst:req, imm:req, cond
636 .if __LINUX_ARM_ARCH__ < 7
637 ldr\cond \dst, =\imm
638 .else
639 movw\cond \dst, #:lower16:\imm
640 movt\cond \dst, #:upper16:\imm
641 .endif
642 .endm
643
644 /*
645 * adr_l - adr pseudo-op with unlimited range
646 *
647 * @dst: destination register
648 * @sym: name of the symbol
649 * @cond: conditional opcode suffix
650 */
651 .macro adr_l, dst:req, sym:req, cond
652 __adldst_l add, \dst, \sym, \dst, \cond
653 .endm
654
655 /*
656 * ldr_l - ldr <literal> pseudo-op with unlimited range
657 *
658 * @dst: destination register
659 * @sym: name of the symbol
660 * @cond: conditional opcode suffix
661 */
662 .macro ldr_l, dst:req, sym:req, cond
663 __adldst_l ldr, \dst, \sym, \dst, \cond
664 .endm
665
666 /*
667 * str_l - str <literal> pseudo-op with unlimited range
668 *
669 * @src: source register
670 * @sym: name of the symbol
671 * @tmp: mandatory scratch register
672 * @cond: conditional opcode suffix
673 */
674 .macro str_l, src:req, sym:req, tmp:req, cond
675 __adldst_l str, \src, \sym, \tmp, \cond
676 .endm
677
678 .macro __ldst_va, op, reg, tmp, sym, cond, offset
679#if __LINUX_ARM_ARCH__ >= 7 || \
680 !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
681 (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
682 mov_l \tmp, \sym, \cond
683#else
684 /*
685 * Avoid a literal load, by emitting a sequence of ADD/LDR instructions
686 * with the appropriate relocations. The combined sequence has a range
687 * of -/+ 256 MiB, which should be sufficient for the core kernel and
688 * for modules loaded into the module region.
689 */
690 .globl \sym
691 .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym
692 .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym
693 .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym
694.L0_\@: sub\cond \tmp, pc, #8 - \offset
695.L1_\@: sub\cond \tmp, \tmp, #4 - \offset
696.L2_\@:
697#endif
698 \op\cond \reg, [\tmp, #\offset]
699 .endm
700
701 /*
702 * ldr_va - load a 32-bit word from the virtual address of \sym
703 */
704 .macro ldr_va, rd:req, sym:req, cond, tmp, offset=0
705 .ifnb \tmp
706 __ldst_va ldr, \rd, \tmp, \sym, \cond, \offset
707 .else
708 __ldst_va ldr, \rd, \rd, \sym, \cond, \offset
709 .endif
710 .endm
711
712 /*
713 * str_va - store a 32-bit word to the virtual address of \sym
714 */
715 .macro str_va, rn:req, sym:req, tmp:req, cond
716 __ldst_va str, \rn, \tmp, \sym, \cond, 0
717 .endm
718
719 /*
720 * ldr_this_cpu_armv6 - Load a 32-bit word from the per-CPU variable 'sym',
721 * without using a temp register. Supported in ARM mode
722 * only.
723 */
724 .macro ldr_this_cpu_armv6, rd:req, sym:req
725 this_cpu_offset \rd
726 .globl \sym
727 .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym
728 .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym
729 .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym
730 add \rd, \rd, pc
731.L0_\@: sub \rd, \rd, #4
732.L1_\@: sub \rd, \rd, #0
733.L2_\@: ldr \rd, [\rd, #4]
734 .endm
735
736 /*
737 * ldr_this_cpu - Load a 32-bit word from the per-CPU variable 'sym'
738 * into register 'rd', which may be the stack pointer,
739 * using 't1' and 't2' as general temp registers. These
740 * are permitted to overlap with 'rd' if != sp
741 */
742 .macro ldr_this_cpu, rd:req, sym:req, t1:req, t2:req
743#ifndef CONFIG_SMP
744 ldr_va \rd, \sym, tmp=\t1
745#elif __LINUX_ARM_ARCH__ >= 7 || \
746 !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \
747 (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS))
748 this_cpu_offset \t1
749 mov_l \t2, \sym
750 ldr \rd, [\t1, \t2]
751#else
752 ldr_this_cpu_armv6 \rd, \sym
753#endif
754 .endm
755
756 /*
757 * rev_l - byte-swap a 32-bit value
758 *
759 * @val: source/destination register
760 * @tmp: scratch register
761 */
762 .macro rev_l, val:req, tmp:req
763 .if __LINUX_ARM_ARCH__ < 6
764 eor \tmp, \val, \val, ror #16
765 bic \tmp, \tmp, #0x00ff0000
766 mov \val, \val, ror #8
767 eor \val, \val, \tmp, lsr #8
768 .else
769 rev \val, \val
770 .endif
771 .endm
772
773 .if __LINUX_ARM_ARCH__ < 6
774 .set .Lrev_l_uses_tmp, 1
775 .else
776 .set .Lrev_l_uses_tmp, 0
777 .endif
778
779 /*
780 * bl_r - branch and link to register
781 *
782 * @dst: target to branch to
783 * @c: conditional opcode suffix
784 */
785 .macro bl_r, dst:req, c
786 .if __LINUX_ARM_ARCH__ < 6
787 mov\c lr, pc
788 mov\c pc, \dst
789 .else
790 blx\c \dst
791 .endif
792 .endm
793
794#endif /* __ASM_ASSEMBLER_H__ */
1/*
2 * arch/arm/include/asm/assembler.h
3 *
4 * Copyright (C) 1996-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This file contains arm architecture specific defines
11 * for the different processors.
12 *
13 * Do not include any C declarations in this file - it is included by
14 * assembler source.
15 */
16#ifndef __ASM_ASSEMBLER_H__
17#define __ASM_ASSEMBLER_H__
18
19#ifndef __ASSEMBLY__
20#error "Only include this from assembly code"
21#endif
22
23#include <asm/ptrace.h>
24#include <asm/domain.h>
25#include <asm/opcodes-virt.h>
26#include <asm/asm-offsets.h>
27#include <asm/page.h>
28#include <asm/thread_info.h>
29
30#define IOMEM(x) (x)
31
32/*
33 * Endian independent macros for shifting bytes within registers.
34 */
35#ifndef __ARMEB__
36#define lspull lsr
37#define lspush lsl
38#define get_byte_0 lsl #0
39#define get_byte_1 lsr #8
40#define get_byte_2 lsr #16
41#define get_byte_3 lsr #24
42#define put_byte_0 lsl #0
43#define put_byte_1 lsl #8
44#define put_byte_2 lsl #16
45#define put_byte_3 lsl #24
46#else
47#define lspull lsl
48#define lspush lsr
49#define get_byte_0 lsr #24
50#define get_byte_1 lsr #16
51#define get_byte_2 lsr #8
52#define get_byte_3 lsl #0
53#define put_byte_0 lsl #24
54#define put_byte_1 lsl #16
55#define put_byte_2 lsl #8
56#define put_byte_3 lsl #0
57#endif
58
59/* Select code for any configuration running in BE8 mode */
60#ifdef CONFIG_CPU_ENDIAN_BE8
61#define ARM_BE8(code...) code
62#else
63#define ARM_BE8(code...)
64#endif
65
66/*
67 * Data preload for architectures that support it
68 */
69#if __LINUX_ARM_ARCH__ >= 5
70#define PLD(code...) code
71#else
72#define PLD(code...)
73#endif
74
75/*
76 * This can be used to enable code to cacheline align the destination
77 * pointer when bulk writing to memory. Experiments on StrongARM and
78 * XScale didn't show this a worthwhile thing to do when the cache is not
79 * set to write-allocate (this would need further testing on XScale when WA
80 * is used).
81 *
82 * On Feroceon there is much to gain however, regardless of cache mode.
83 */
84#ifdef CONFIG_CPU_FEROCEON
85#define CALGN(code...) code
86#else
87#define CALGN(code...)
88#endif
89
90#define IMM12_MASK 0xfff
91
92/*
93 * Enable and disable interrupts
94 */
95#if __LINUX_ARM_ARCH__ >= 6
96 .macro disable_irq_notrace
97 cpsid i
98 .endm
99
100 .macro enable_irq_notrace
101 cpsie i
102 .endm
103#else
104 .macro disable_irq_notrace
105 msr cpsr_c, #PSR_I_BIT | SVC_MODE
106 .endm
107
108 .macro enable_irq_notrace
109 msr cpsr_c, #SVC_MODE
110 .endm
111#endif
112
113 .macro asm_trace_hardirqs_off, save=1
114#if defined(CONFIG_TRACE_IRQFLAGS)
115 .if \save
116 stmdb sp!, {r0-r3, ip, lr}
117 .endif
118 bl trace_hardirqs_off
119 .if \save
120 ldmia sp!, {r0-r3, ip, lr}
121 .endif
122#endif
123 .endm
124
125 .macro asm_trace_hardirqs_on, cond=al, save=1
126#if defined(CONFIG_TRACE_IRQFLAGS)
127 /*
128 * actually the registers should be pushed and pop'd conditionally, but
129 * after bl the flags are certainly clobbered
130 */
131 .if \save
132 stmdb sp!, {r0-r3, ip, lr}
133 .endif
134 bl\cond trace_hardirqs_on
135 .if \save
136 ldmia sp!, {r0-r3, ip, lr}
137 .endif
138#endif
139 .endm
140
141 .macro disable_irq, save=1
142 disable_irq_notrace
143 asm_trace_hardirqs_off \save
144 .endm
145
146 .macro enable_irq
147 asm_trace_hardirqs_on
148 enable_irq_notrace
149 .endm
150/*
151 * Save the current IRQ state and disable IRQs. Note that this macro
152 * assumes FIQs are enabled, and that the processor is in SVC mode.
153 */
154 .macro save_and_disable_irqs, oldcpsr
155#ifdef CONFIG_CPU_V7M
156 mrs \oldcpsr, primask
157#else
158 mrs \oldcpsr, cpsr
159#endif
160 disable_irq
161 .endm
162
163 .macro save_and_disable_irqs_notrace, oldcpsr
164#ifdef CONFIG_CPU_V7M
165 mrs \oldcpsr, primask
166#else
167 mrs \oldcpsr, cpsr
168#endif
169 disable_irq_notrace
170 .endm
171
172/*
173 * Restore interrupt state previously stored in a register. We don't
174 * guarantee that this will preserve the flags.
175 */
176 .macro restore_irqs_notrace, oldcpsr
177#ifdef CONFIG_CPU_V7M
178 msr primask, \oldcpsr
179#else
180 msr cpsr_c, \oldcpsr
181#endif
182 .endm
183
184 .macro restore_irqs, oldcpsr
185 tst \oldcpsr, #PSR_I_BIT
186 asm_trace_hardirqs_on cond=eq
187 restore_irqs_notrace \oldcpsr
188 .endm
189
190/*
191 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
192 * reference local symbols in the same assembly file which are to be
193 * resolved by the assembler. Other usage is undefined.
194 */
195 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
196 .macro badr\c, rd, sym
197#ifdef CONFIG_THUMB2_KERNEL
198 adr\c \rd, \sym + 1
199#else
200 adr\c \rd, \sym
201#endif
202 .endm
203 .endr
204
205/*
206 * Get current thread_info.
207 */
208 .macro get_thread_info, rd
209 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT )
210 THUMB( mov \rd, sp )
211 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT )
212 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
213 .endm
214
215/*
216 * Increment/decrement the preempt count.
217 */
218#ifdef CONFIG_PREEMPT_COUNT
219 .macro inc_preempt_count, ti, tmp
220 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
221 add \tmp, \tmp, #1 @ increment it
222 str \tmp, [\ti, #TI_PREEMPT]
223 .endm
224
225 .macro dec_preempt_count, ti, tmp
226 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
227 sub \tmp, \tmp, #1 @ decrement it
228 str \tmp, [\ti, #TI_PREEMPT]
229 .endm
230
231 .macro dec_preempt_count_ti, ti, tmp
232 get_thread_info \ti
233 dec_preempt_count \ti, \tmp
234 .endm
235#else
236 .macro inc_preempt_count, ti, tmp
237 .endm
238
239 .macro dec_preempt_count, ti, tmp
240 .endm
241
242 .macro dec_preempt_count_ti, ti, tmp
243 .endm
244#endif
245
246#define USER(x...) \
2479999: x; \
248 .pushsection __ex_table,"a"; \
249 .align 3; \
250 .long 9999b,9001f; \
251 .popsection
252
253#ifdef CONFIG_SMP
254#define ALT_SMP(instr...) \
2559998: instr
256/*
257 * Note: if you get assembler errors from ALT_UP() when building with
258 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
259 * ALT_SMP( W(instr) ... )
260 */
261#define ALT_UP(instr...) \
262 .pushsection ".alt.smp.init", "a" ;\
263 .long 9998b ;\
2649997: instr ;\
265 .if . - 9997b == 2 ;\
266 nop ;\
267 .endif ;\
268 .if . - 9997b != 4 ;\
269 .error "ALT_UP() content must assemble to exactly 4 bytes";\
270 .endif ;\
271 .popsection
272#define ALT_UP_B(label) \
273 .equ up_b_offset, label - 9998b ;\
274 .pushsection ".alt.smp.init", "a" ;\
275 .long 9998b ;\
276 W(b) . + up_b_offset ;\
277 .popsection
278#else
279#define ALT_SMP(instr...)
280#define ALT_UP(instr...) instr
281#define ALT_UP_B(label) b label
282#endif
283
284/*
285 * Instruction barrier
286 */
287 .macro instr_sync
288#if __LINUX_ARM_ARCH__ >= 7
289 isb
290#elif __LINUX_ARM_ARCH__ == 6
291 mcr p15, 0, r0, c7, c5, 4
292#endif
293 .endm
294
295/*
296 * SMP data memory barrier
297 */
298 .macro smp_dmb mode
299#ifdef CONFIG_SMP
300#if __LINUX_ARM_ARCH__ >= 7
301 .ifeqs "\mode","arm"
302 ALT_SMP(dmb ish)
303 .else
304 ALT_SMP(W(dmb) ish)
305 .endif
306#elif __LINUX_ARM_ARCH__ == 6
307 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
308#else
309#error Incompatible SMP platform
310#endif
311 .ifeqs "\mode","arm"
312 ALT_UP(nop)
313 .else
314 ALT_UP(W(nop))
315 .endif
316#endif
317 .endm
318
319#if defined(CONFIG_CPU_V7M)
320 /*
321 * setmode is used to assert to be in svc mode during boot. For v7-M
322 * this is done in __v7m_setup, so setmode can be empty here.
323 */
324 .macro setmode, mode, reg
325 .endm
326#elif defined(CONFIG_THUMB2_KERNEL)
327 .macro setmode, mode, reg
328 mov \reg, #\mode
329 msr cpsr_c, \reg
330 .endm
331#else
332 .macro setmode, mode, reg
333 msr cpsr_c, #\mode
334 .endm
335#endif
336
337/*
338 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
339 * a scratch register for the macro to overwrite.
340 *
341 * This macro is intended for forcing the CPU into SVC mode at boot time.
342 * you cannot return to the original mode.
343 */
344.macro safe_svcmode_maskall reg:req
345#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
346 mrs \reg , cpsr
347 eor \reg, \reg, #HYP_MODE
348 tst \reg, #MODE_MASK
349 bic \reg , \reg , #MODE_MASK
350 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
351THUMB( orr \reg , \reg , #PSR_T_BIT )
352 bne 1f
353 orr \reg, \reg, #PSR_A_BIT
354 badr lr, 2f
355 msr spsr_cxsf, \reg
356 __MSR_ELR_HYP(14)
357 __ERET
3581: msr cpsr_c, \reg
3592:
360#else
361/*
362 * workaround for possibly broken pre-v6 hardware
363 * (akita, Sharp Zaurus C-1000, PXA270-based)
364 */
365 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
366#endif
367.endm
368
369/*
370 * STRT/LDRT access macros with ARM and Thumb-2 variants
371 */
372#ifdef CONFIG_THUMB2_KERNEL
373
374 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
3759999:
376 .if \inc == 1
377 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
378 .elseif \inc == 4
379 \instr\cond\()\t\().w \reg, [\ptr, #\off]
380 .else
381 .error "Unsupported inc macro argument"
382 .endif
383
384 .pushsection __ex_table,"a"
385 .align 3
386 .long 9999b, \abort
387 .popsection
388 .endm
389
390 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
391 @ explicit IT instruction needed because of the label
392 @ introduced by the USER macro
393 .ifnc \cond,al
394 .if \rept == 1
395 itt \cond
396 .elseif \rept == 2
397 ittt \cond
398 .else
399 .error "Unsupported rept macro argument"
400 .endif
401 .endif
402
403 @ Slightly optimised to avoid incrementing the pointer twice
404 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
405 .if \rept == 2
406 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
407 .endif
408
409 add\cond \ptr, #\rept * \inc
410 .endm
411
412#else /* !CONFIG_THUMB2_KERNEL */
413
414 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
415 .rept \rept
4169999:
417 .if \inc == 1
418 \instr\cond\()b\()\t \reg, [\ptr], #\inc
419 .elseif \inc == 4
420 \instr\cond\()\t \reg, [\ptr], #\inc
421 .else
422 .error "Unsupported inc macro argument"
423 .endif
424
425 .pushsection __ex_table,"a"
426 .align 3
427 .long 9999b, \abort
428 .popsection
429 .endr
430 .endm
431
432#endif /* CONFIG_THUMB2_KERNEL */
433
434 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
435 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
436 .endm
437
438 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
439 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
440 .endm
441
442/* Utility macro for declaring string literals */
443 .macro string name:req, string
444 .type \name , #object
445\name:
446 .asciz "\string"
447 .size \name , . - \name
448 .endm
449
450 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
451#ifndef CONFIG_CPU_USE_DOMAINS
452 adds \tmp, \addr, #\size - 1
453 sbcccs \tmp, \tmp, \limit
454 bcs \bad
455#endif
456 .endm
457
458 .macro uaccess_disable, tmp, isb=1
459#ifdef CONFIG_CPU_SW_DOMAIN_PAN
460 /*
461 * Whenever we re-enter userspace, the domains should always be
462 * set appropriately.
463 */
464 mov \tmp, #DACR_UACCESS_DISABLE
465 mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register
466 .if \isb
467 instr_sync
468 .endif
469#endif
470 .endm
471
472 .macro uaccess_enable, tmp, isb=1
473#ifdef CONFIG_CPU_SW_DOMAIN_PAN
474 /*
475 * Whenever we re-enter userspace, the domains should always be
476 * set appropriately.
477 */
478 mov \tmp, #DACR_UACCESS_ENABLE
479 mcr p15, 0, \tmp, c3, c0, 0
480 .if \isb
481 instr_sync
482 .endif
483#endif
484 .endm
485
486 .macro uaccess_save, tmp
487#ifdef CONFIG_CPU_SW_DOMAIN_PAN
488 mrc p15, 0, \tmp, c3, c0, 0
489 str \tmp, [sp, #SVC_DACR]
490#endif
491 .endm
492
493 .macro uaccess_restore
494#ifdef CONFIG_CPU_SW_DOMAIN_PAN
495 ldr r0, [sp, #SVC_DACR]
496 mcr p15, 0, r0, c3, c0, 0
497#endif
498 .endm
499
500 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
501 .macro ret\c, reg
502#if __LINUX_ARM_ARCH__ < 6
503 mov\c pc, \reg
504#else
505 .ifeqs "\reg", "lr"
506 bx\c \reg
507 .else
508 mov\c pc, \reg
509 .endif
510#endif
511 .endm
512 .endr
513
514 .macro ret.w, reg
515 ret \reg
516#ifdef CONFIG_THUMB2_KERNEL
517 nop
518#endif
519 .endm
520
521 .macro bug, msg, line
522#ifdef CONFIG_THUMB2_KERNEL
5231: .inst 0xde02
524#else
5251: .inst 0xe7f001f2
526#endif
527#ifdef CONFIG_DEBUG_BUGVERBOSE
528 .pushsection .rodata.str, "aMS", %progbits, 1
5292: .asciz "\msg"
530 .popsection
531 .pushsection __bug_table, "aw"
532 .align 2
533 .word 1b, 2b
534 .hword \line
535 .popsection
536#endif
537 .endm
538
539#ifdef CONFIG_KPROBES
540#define _ASM_NOKPROBE(entry) \
541 .pushsection "_kprobe_blacklist", "aw" ; \
542 .balign 4 ; \
543 .long entry; \
544 .popsection
545#else
546#define _ASM_NOKPROBE(entry)
547#endif
548
549#endif /* __ASM_ASSEMBLER_H__ */