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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 */
4
5/*
6 Vortex core low level functions.
7
8 Author: Manuel Jander (mjander@users.sourceforge.cl)
9 These functions are mainly the result of translations made
10 from the original disassembly of the au88x0 binary drivers,
11 written by Aureal before they went down.
12 Many thanks to the Jeff Muizelaar, Kester Maddock, and whoever
13 contributed to the OpenVortex project.
14 The author of this file, put the few available pieces together
15 and translated the rest of the riddle (Mix, Src and connection stuff).
16 Some things are still to be discovered, and their meanings are unclear.
17
18 Some of these functions aren't intended to be really used, rather
19 to help to understand how does the AU88X0 chips work. Keep them in, because
20 they could be used somewhere in the future.
21
22 This code hasn't been tested or proof read thoroughly. If you wanna help,
23 take a look at the AU88X0 assembly and check if this matches.
24 Functions tested ok so far are (they show the desired effect
25 at least):
26 vortex_routes(); (1 bug fixed).
27 vortex_adb_addroute();
28 vortex_adb_addroutes();
29 vortex_connect_codecplay();
30 vortex_src_flushbuffers();
31 vortex_adbdma_setmode(); note: still some unknown arguments!
32 vortex_adbdma_startfifo();
33 vortex_adbdma_stopfifo();
34 vortex_fifo_setadbctrl(); note: still some unknown arguments!
35 vortex_mix_setinputvolumebyte();
36 vortex_mix_enableinput();
37 vortex_mixer_addWTD(); (fixed)
38 vortex_connection_adbdma_src_src();
39 vortex_connection_adbdma_src();
40 vortex_src_change_convratio();
41 vortex_src_addWTD(); (fixed)
42
43 History:
44
45 01-03-2003 First revision.
46 01-21-2003 Some bug fixes.
47 17-02-2003 many bugfixes after a big versioning mess.
48 18-02-2003 JAAAAAHHHUUUUUU!!!! The mixer works !! I'm just so happy !
49 (2 hours later...) I cant believe it! Im really lucky today.
50 Now the SRC is working too! Yeah! XMMS works !
51 20-02-2003 First steps into the ALSA world.
52 28-02-2003 As my birthday present, i discovered how the DMA buffer pages really
53 work :-). It was all wrong.
54 12-03-2003 ALSA driver starts working (2 channels).
55 16-03-2003 More srcblock_setupchannel discoveries.
56 12-04-2003 AU8830 playback support. Recording in the works.
57 17-04-2003 vortex_route() and vortex_routes() bug fixes. AU8830 recording
58 works now, but chipn' dale effect is still there.
59 16-05-2003 SrcSetupChannel cleanup. Moved the Src setup stuff entirely
60 into au88x0_pcm.c .
61 06-06-2003 Buffer shifter bugfix. Mixer volume fix.
62 07-12-2003 A3D routing finally fixed. Believed to be OK.
63 25-03-2004 Many thanks to Claudia, for such valuable bug reports.
64
65*/
66
67#include "au88x0.h"
68#include "au88x0_a3d.h"
69#include <linux/delay.h>
70
71/* MIXER (CAsp4Mix.s and CAsp4Mixer.s) */
72
73// FIXME: get rid of this.
74static int mchannels[NR_MIXIN];
75static int rampchs[NR_MIXIN];
76
77static void vortex_mixer_en_sr(vortex_t * vortex, int channel)
78{
79 hwwrite(vortex->mmio, VORTEX_MIXER_SR,
80 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel));
81}
82static void vortex_mixer_dis_sr(vortex_t * vortex, int channel)
83{
84 hwwrite(vortex->mmio, VORTEX_MIXER_SR,
85 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel));
86}
87
88#if 0
89static void
90vortex_mix_muteinputgain(vortex_t * vortex, unsigned char mix,
91 unsigned char channel)
92{
93 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel),
94 0x80);
95 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel),
96 0x80);
97}
98
99static int vortex_mix_getvolume(vortex_t * vortex, unsigned char mix)
100{
101 int a;
102 a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
103 //FP2LinearFrac(a);
104 return (a);
105}
106
107static int
108vortex_mix_getinputvolume(vortex_t * vortex, unsigned char mix,
109 int channel, int *vol)
110{
111 int a;
112 if (!(mchannels[mix] & (1 << channel)))
113 return 0;
114 a = hwread(vortex->mmio,
115 VORTEX_MIX_INVOL_A + (((mix << 5) + channel) << 2));
116 /*
117 if (rampchs[mix] == 0)
118 a = FP2LinearFrac(a);
119 else
120 a = FP2LinearFracWT(a);
121 */
122 *vol = a;
123 return (0);
124}
125
126static unsigned int vortex_mix_boost6db(unsigned char vol)
127{
128 return (vol + 8); /* WOW! what a complex function! */
129}
130
131static void vortex_mix_rampvolume(vortex_t * vortex, int mix)
132{
133 int ch;
134 char a;
135 // This function is intended for ramping down only (see vortex_disableinput()).
136 for (ch = 0; ch < 0x20; ch++) {
137 if (((1 << ch) & rampchs[mix]) == 0)
138 continue;
139 a = hwread(vortex->mmio,
140 VORTEX_MIX_INVOL_B + (((mix << 5) + ch) << 2));
141 if (a > -126) {
142 a -= 2;
143 hwwrite(vortex->mmio,
144 VORTEX_MIX_INVOL_A +
145 (((mix << 5) + ch) << 2), a);
146 hwwrite(vortex->mmio,
147 VORTEX_MIX_INVOL_B +
148 (((mix << 5) + ch) << 2), a);
149 } else
150 vortex_mix_killinput(vortex, mix, ch);
151 }
152}
153
154static int
155vortex_mix_getenablebit(vortex_t * vortex, unsigned char mix, int mixin)
156{
157 int addr, temp;
158 if (mixin >= 0)
159 addr = mixin;
160 else
161 addr = mixin + 3;
162 addr = ((mix << 3) + (addr >> 2)) << 2;
163 temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
164 return ((temp >> (mixin & 3)) & 1);
165}
166#endif
167static void
168vortex_mix_setvolumebyte(vortex_t * vortex, unsigned char mix,
169 unsigned char vol)
170{
171 int temp;
172 hwwrite(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2), vol);
173 if (1) { /*if (this_10) */
174 temp = hwread(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2));
175 if ((temp != 0x80) || (vol == 0x80))
176 return;
177 }
178 hwwrite(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2), vol);
179}
180
181static void
182vortex_mix_setinputvolumebyte(vortex_t * vortex, unsigned char mix,
183 int mixin, unsigned char vol)
184{
185 int temp;
186
187 hwwrite(vortex->mmio,
188 VORTEX_MIX_INVOL_A + (((mix << 5) + mixin) << 2), vol);
189 if (1) { /* this_10, initialized to 1. */
190 temp =
191 hwread(vortex->mmio,
192 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2));
193 if ((temp != 0x80) || (vol == 0x80))
194 return;
195 }
196 hwwrite(vortex->mmio,
197 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), vol);
198}
199
200static void
201vortex_mix_setenablebit(vortex_t * vortex, unsigned char mix, int mixin, int en)
202{
203 int temp, addr;
204
205 if (mixin < 0)
206 addr = (mixin + 3);
207 else
208 addr = mixin;
209 addr = ((mix << 3) + (addr >> 2)) << 2;
210 temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
211 if (en)
212 temp |= (1 << (mixin & 3));
213 else
214 temp &= ~(1 << (mixin & 3));
215 /* Mute input. Astatic void crackling? */
216 hwwrite(vortex->mmio,
217 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), 0x80);
218 /* Looks like clear buffer. */
219 hwwrite(vortex->mmio, VORTEX_MIX_SMP + (mixin << 2), 0x0);
220 hwwrite(vortex->mmio, VORTEX_MIX_SMP + 4 + (mixin << 2), 0x0);
221 /* Write enable bit. */
222 hwwrite(vortex->mmio, VORTEX_MIX_ENIN + addr, temp);
223}
224
225static void
226vortex_mix_killinput(vortex_t * vortex, unsigned char mix, int mixin)
227{
228 rampchs[mix] &= ~(1 << mixin);
229 vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80);
230 mchannels[mix] &= ~(1 << mixin);
231 vortex_mix_setenablebit(vortex, mix, mixin, 0);
232}
233
234static void
235vortex_mix_enableinput(vortex_t * vortex, unsigned char mix, int mixin)
236{
237 vortex_mix_killinput(vortex, mix, mixin);
238 if ((mchannels[mix] & (1 << mixin)) == 0) {
239 vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80); /*0x80 : mute */
240 mchannels[mix] |= (1 << mixin);
241 }
242 vortex_mix_setenablebit(vortex, mix, mixin, 1);
243}
244
245static void
246vortex_mix_disableinput(vortex_t * vortex, unsigned char mix, int channel,
247 int ramp)
248{
249 if (ramp) {
250 rampchs[mix] |= (1 << channel);
251 // Register callback.
252 //vortex_mix_startrampvolume(vortex);
253 vortex_mix_killinput(vortex, mix, channel);
254 } else
255 vortex_mix_killinput(vortex, mix, channel);
256}
257
258static int
259vortex_mixer_addWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
260{
261 int temp, lifeboat = 0, prev;
262
263 temp = hwread(vortex->mmio, VORTEX_MIXER_SR);
264 if ((temp & (1 << ch)) == 0) {
265 hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), mix);
266 vortex_mixer_en_sr(vortex, ch);
267 return 1;
268 }
269 prev = VORTEX_MIXER_CHNBASE + (ch << 2);
270 temp = hwread(vortex->mmio, prev);
271 while (temp & 0x10) {
272 prev = VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2);
273 temp = hwread(vortex->mmio, prev);
274 //printk(KERN_INFO "vortex: mixAddWTD: while addr=%x, val=%x\n", prev, temp);
275 if ((++lifeboat) > 0xf) {
276 dev_err(vortex->card->dev,
277 "vortex_mixer_addWTD: lifeboat overflow\n");
278 return 0;
279 }
280 }
281 hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2), mix);
282 hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
283 return 1;
284}
285
286static int
287vortex_mixer_delWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
288{
289 int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
290 //int esp1f=edi(while)=src, esp10=ch;
291
292 eax = hwread(vortex->mmio, VORTEX_MIXER_SR);
293 if (((1 << ch) & eax) == 0) {
294 dev_err(vortex->card->dev, "mix ALARM %x\n", eax);
295 return 0;
296 }
297 ebp = VORTEX_MIXER_CHNBASE + (ch << 2);
298 esp18 = hwread(vortex->mmio, ebp);
299 if (esp18 & 0x10) {
300 ebx = (esp18 & 0xf);
301 if (mix == ebx) {
302 ebx = VORTEX_MIXER_RTBASE + (mix << 2);
303 edx = hwread(vortex->mmio, ebx);
304 //7b60
305 hwwrite(vortex->mmio, ebp, edx);
306 hwwrite(vortex->mmio, ebx, 0);
307 } else {
308 //7ad3
309 edx =
310 hwread(vortex->mmio,
311 VORTEX_MIXER_RTBASE + (ebx << 2));
312 //printk(KERN_INFO "vortex: mixdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src);
313 while ((edx & 0xf) != mix) {
314 if ((esi) > 0xf) {
315 dev_err(vortex->card->dev,
316 "mixdelWTD: error lifeboat overflow\n");
317 return 0;
318 }
319 esp14 = ebx;
320 ebx = edx & 0xf;
321 ebp = ebx << 2;
322 edx =
323 hwread(vortex->mmio,
324 VORTEX_MIXER_RTBASE + ebp);
325 //printk(KERN_INFO "vortex: mixdelWTD: while addr=%x, val=%x\n", ebp, edx);
326 esi++;
327 }
328 //7b30
329 ebp = ebx << 2;
330 if (edx & 0x10) { /* Delete entry in between others */
331 ebx = VORTEX_MIXER_RTBASE + ((edx & 0xf) << 2);
332 edx = hwread(vortex->mmio, ebx);
333 //7b60
334 hwwrite(vortex->mmio,
335 VORTEX_MIXER_RTBASE + ebp, edx);
336 hwwrite(vortex->mmio, ebx, 0);
337 //printk(KERN_INFO "vortex mixdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx);
338 } else { /* Delete last entry */
339 //7b83
340 if (esp14 == -1)
341 hwwrite(vortex->mmio,
342 VORTEX_MIXER_CHNBASE +
343 (ch << 2), esp18 & 0xef);
344 else {
345 ebx = (0xffffffe0 & edx) | (0xf & ebx);
346 hwwrite(vortex->mmio,
347 VORTEX_MIXER_RTBASE +
348 (esp14 << 2), ebx);
349 //printk(KERN_INFO "vortex mixdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx);
350 }
351 hwwrite(vortex->mmio,
352 VORTEX_MIXER_RTBASE + ebp, 0);
353 return 1;
354 }
355 }
356 } else {
357 //printk(KERN_INFO "removed last mix\n");
358 //7be0
359 vortex_mixer_dis_sr(vortex, ch);
360 hwwrite(vortex->mmio, ebp, 0);
361 }
362 return 1;
363}
364
365static void vortex_mixer_init(vortex_t * vortex)
366{
367 u32 addr;
368 int x;
369
370 // FIXME: get rid of this crap.
371 memset(mchannels, 0, NR_MIXOUT * sizeof(int));
372 memset(rampchs, 0, NR_MIXOUT * sizeof(int));
373
374 addr = VORTEX_MIX_SMP + 0x17c;
375 for (x = 0x5f; x >= 0; x--) {
376 hwwrite(vortex->mmio, addr, 0);
377 addr -= 4;
378 }
379 addr = VORTEX_MIX_ENIN + 0x1fc;
380 for (x = 0x7f; x >= 0; x--) {
381 hwwrite(vortex->mmio, addr, 0);
382 addr -= 4;
383 }
384 addr = VORTEX_MIX_SMP + 0x17c;
385 for (x = 0x5f; x >= 0; x--) {
386 hwwrite(vortex->mmio, addr, 0);
387 addr -= 4;
388 }
389 addr = VORTEX_MIX_INVOL_A + 0x7fc;
390 for (x = 0x1ff; x >= 0; x--) {
391 hwwrite(vortex->mmio, addr, 0x80);
392 addr -= 4;
393 }
394 addr = VORTEX_MIX_VOL_A + 0x3c;
395 for (x = 0xf; x >= 0; x--) {
396 hwwrite(vortex->mmio, addr, 0x80);
397 addr -= 4;
398 }
399 addr = VORTEX_MIX_INVOL_B + 0x7fc;
400 for (x = 0x1ff; x >= 0; x--) {
401 hwwrite(vortex->mmio, addr, 0x80);
402 addr -= 4;
403 }
404 addr = VORTEX_MIX_VOL_B + 0x3c;
405 for (x = 0xf; x >= 0; x--) {
406 hwwrite(vortex->mmio, addr, 0x80);
407 addr -= 4;
408 }
409 addr = VORTEX_MIXER_RTBASE + (MIXER_RTBASE_SIZE - 1) * 4;
410 for (x = (MIXER_RTBASE_SIZE - 1); x >= 0; x--) {
411 hwwrite(vortex->mmio, addr, 0x0);
412 addr -= 4;
413 }
414 hwwrite(vortex->mmio, VORTEX_MIXER_SR, 0);
415
416 /* Set clipping ceiling (this may be all wrong). */
417 /*
418 for (x = 0; x < 0x80; x++) {
419 hwwrite(vortex->mmio, VORTEX_MIXER_CLIP + (x << 2), 0x3ffff);
420 }
421 */
422 /*
423 call CAsp4Mix__Initialize_CAsp4HwIO____CAsp4Mixer____
424 Register ISR callback for volume smooth fade out.
425 Maybe this avoids clicks when press "stop" ?
426 */
427}
428
429/* SRC (CAsp4Src.s and CAsp4SrcBlock) */
430
431static void vortex_src_en_sr(vortex_t * vortex, int channel)
432{
433 hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
434 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) | (0x1 << channel));
435}
436
437static void vortex_src_dis_sr(vortex_t * vortex, int channel)
438{
439 hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
440 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) & ~(0x1 << channel));
441}
442
443static void vortex_src_flushbuffers(vortex_t * vortex, unsigned char src)
444{
445 int i;
446
447 for (i = 0x1f; i >= 0; i--)
448 hwwrite(vortex->mmio,
449 VORTEX_SRC_DATA0 + (src << 7) + (i << 2), 0);
450 hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3), 0);
451 hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3) + 4, 0);
452}
453
454static void vortex_src_cleardrift(vortex_t * vortex, unsigned char src)
455{
456 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
457 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT1 + (src << 2), 0);
458 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
459}
460
461static void
462vortex_src_set_throttlesource(vortex_t * vortex, unsigned char src, int en)
463{
464 int temp;
465
466 temp = hwread(vortex->mmio, VORTEX_SRC_SOURCE);
467 if (en)
468 temp |= 1 << src;
469 else
470 temp &= ~(1 << src);
471 hwwrite(vortex->mmio, VORTEX_SRC_SOURCE, temp);
472}
473
474static int
475vortex_src_persist_convratio(vortex_t * vortex, unsigned char src, int ratio)
476{
477 int temp, lifeboat = 0;
478
479 do {
480 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), ratio);
481 temp = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
482 if ((++lifeboat) > 0x9) {
483 dev_err(vortex->card->dev, "Src cvr fail\n");
484 break;
485 }
486 }
487 while (temp != ratio);
488 return temp;
489}
490
491#if 0
492static void vortex_src_slowlock(vortex_t * vortex, unsigned char src)
493{
494 int temp;
495
496 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
497 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
498 temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
499 if (temp & 0x200)
500 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
501 temp & ~0x200L);
502}
503
504static void
505vortex_src_change_convratio(vortex_t * vortex, unsigned char src, int ratio)
506{
507 int temp, a;
508
509 if ((ratio & 0x10000) && (ratio != 0x10000)) {
510 if (ratio & 0x3fff)
511 a = (0x11 - ((ratio >> 0xe) & 0x3)) - 1;
512 else
513 a = (0x11 - ((ratio >> 0xe) & 0x3)) - 2;
514 } else
515 a = 0xc;
516 temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
517 if (((temp >> 4) & 0xf) != a)
518 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
519 (temp & 0xf) | ((a & 0xf) << 4));
520
521 vortex_src_persist_convratio(vortex, src, ratio);
522}
523
524static int
525vortex_src_checkratio(vortex_t * vortex, unsigned char src,
526 unsigned int desired_ratio)
527{
528 int hw_ratio, lifeboat = 0;
529
530 hw_ratio = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
531
532 while (hw_ratio != desired_ratio) {
533 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), desired_ratio);
534
535 if ((lifeboat++) > 15) {
536 pr_err( "Vortex: could not set src-%d from %d to %d\n",
537 src, hw_ratio, desired_ratio);
538 break;
539 }
540 }
541
542 return hw_ratio;
543}
544
545#endif
546/*
547 Objective: Set samplerate for given SRC module.
548 Arguments:
549 card: pointer to vortex_t strcut.
550 src: Integer index of the SRC module.
551 cr: Current sample rate conversion factor.
552 b: unknown 16 bit value.
553 sweep: Enable Samplerate fade from cr toward tr flag.
554 dirplay: 1: playback, 0: recording.
555 sl: Slow Lock flag.
556 tr: Target samplerate conversion.
557 thsource: Throttle source flag (no idea what that means).
558*/
559static void vortex_src_setupchannel(vortex_t * card, unsigned char src,
560 unsigned int cr, unsigned int b, int sweep, int d,
561 int dirplay, int sl, unsigned int tr, int thsource)
562{
563 // noplayback: d=2,4,7,0xa,0xb when using first 2 src's.
564 // c: enables pitch sweep.
565 // looks like g is c related. Maybe g is a sweep parameter ?
566 // g = cvr
567 // dirplay: 0 = recording, 1 = playback
568 // d = src hw index.
569
570 int esi, ebp = 0, esp10;
571
572 vortex_src_flushbuffers(card, src);
573
574 if (sweep) {
575 if ((tr & 0x10000) && (tr != 0x10000)) {
576 tr = 0;
577 esi = 0x7;
578 } else {
579 if ((((short)tr) < 0) && (tr != 0x8000)) {
580 tr = 0;
581 esi = 0x8;
582 } else {
583 tr = 1;
584 esi = 0xc;
585 }
586 }
587 } else {
588 if ((cr & 0x10000) && (cr != 0x10000)) {
589 tr = 0; /*ebx = 0 */
590 esi = 0x11 - ((cr >> 0xe) & 7);
591 if (cr & 0x3fff)
592 esi -= 1;
593 else
594 esi -= 2;
595 } else {
596 tr = 1;
597 esi = 0xc;
598 }
599 }
600 vortex_src_cleardrift(card, src);
601 vortex_src_set_throttlesource(card, src, thsource);
602
603 if ((dirplay == 0) && (sweep == 0)) {
604 if (tr)
605 esp10 = 0xf;
606 else
607 esp10 = 0xc;
608 ebp = 0;
609 } else {
610 if (tr)
611 ebp = 0xf;
612 else
613 ebp = 0xc;
614 esp10 = 0;
615 }
616 hwwrite(card->mmio, VORTEX_SRC_U0 + (src << 2),
617 (sl << 0x9) | (sweep << 0x8) | ((esi & 0xf) << 4) | d);
618 /* 0xc0 esi=0xc c=f=0 d=0 */
619 vortex_src_persist_convratio(card, src, cr);
620 hwwrite(card->mmio, VORTEX_SRC_U1 + (src << 2), b & 0xffff);
621 /* 0 b=0 */
622 hwwrite(card->mmio, VORTEX_SRC_U2 + (src << 2),
623 (tr << 0x11) | (dirplay << 0x10) | (ebp << 0x8) | esp10);
624 /* 0x30f00 e=g=1 esp10=0 ebp=f */
625 //printk(KERN_INFO "vortex: SRC %d, d=0x%x, esi=0x%x, esp10=0x%x, ebp=0x%x\n", src, d, esi, esp10, ebp);
626}
627
628static void vortex_srcblock_init(vortex_t * vortex)
629{
630 u32 addr;
631 int x;
632 hwwrite(vortex->mmio, VORTEX_SRC_SOURCESIZE, 0x1ff);
633 /*
634 for (x=0; x<0x10; x++) {
635 vortex_src_init(&vortex_src[x], x);
636 }
637 */
638 //addr = 0xcc3c;
639 //addr = 0x26c3c;
640 addr = VORTEX_SRC_RTBASE + 0x3c;
641 for (x = 0xf; x >= 0; x--) {
642 hwwrite(vortex->mmio, addr, 0);
643 addr -= 4;
644 }
645 //addr = 0xcc94;
646 //addr = 0x26c94;
647 addr = VORTEX_SRC_CHNBASE + 0x54;
648 for (x = 0x15; x >= 0; x--) {
649 hwwrite(vortex->mmio, addr, 0);
650 addr -= 4;
651 }
652}
653
654static int
655vortex_src_addWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
656{
657 int temp, lifeboat = 0, prev;
658 // esp13 = src
659
660 temp = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
661 if ((temp & (1 << ch)) == 0) {
662 hwwrite(vortex->mmio, VORTEX_SRC_CHNBASE + (ch << 2), src);
663 vortex_src_en_sr(vortex, ch);
664 return 1;
665 }
666 prev = VORTEX_SRC_CHNBASE + (ch << 2); /*ebp */
667 temp = hwread(vortex->mmio, prev);
668 //while (temp & NR_SRC) {
669 while (temp & 0x10) {
670 prev = VORTEX_SRC_RTBASE + ((temp & 0xf) << 2); /*esp12 */
671 //prev = VORTEX_SRC_RTBASE + ((temp & (NR_SRC-1)) << 2); /*esp12*/
672 temp = hwread(vortex->mmio, prev);
673 //printk(KERN_INFO "vortex: srcAddWTD: while addr=%x, val=%x\n", prev, temp);
674 if ((++lifeboat) > 0xf) {
675 dev_err(vortex->card->dev,
676 "vortex_src_addWTD: lifeboat overflow\n");
677 return 0;
678 }
679 }
680 hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ((temp & 0xf) << 2), src);
681 //hwwrite(vortex->mmio, prev, (temp & (NR_SRC-1)) | NR_SRC);
682 hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
683 return 1;
684}
685
686static int
687vortex_src_delWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
688{
689 int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
690 //int esp1f=edi(while)=src, esp10=ch;
691
692 eax = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
693 if (((1 << ch) & eax) == 0) {
694 dev_err(vortex->card->dev, "src alarm\n");
695 return 0;
696 }
697 ebp = VORTEX_SRC_CHNBASE + (ch << 2);
698 esp18 = hwread(vortex->mmio, ebp);
699 if (esp18 & 0x10) {
700 ebx = (esp18 & 0xf);
701 if (src == ebx) {
702 ebx = VORTEX_SRC_RTBASE + (src << 2);
703 edx = hwread(vortex->mmio, ebx);
704 //7b60
705 hwwrite(vortex->mmio, ebp, edx);
706 hwwrite(vortex->mmio, ebx, 0);
707 } else {
708 //7ad3
709 edx =
710 hwread(vortex->mmio,
711 VORTEX_SRC_RTBASE + (ebx << 2));
712 //printk(KERN_INFO "vortex: srcdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src);
713 while ((edx & 0xf) != src) {
714 if ((esi) > 0xf) {
715 dev_warn(vortex->card->dev,
716 "srcdelWTD: error, lifeboat overflow\n");
717 return 0;
718 }
719 esp14 = ebx;
720 ebx = edx & 0xf;
721 ebp = ebx << 2;
722 edx =
723 hwread(vortex->mmio,
724 VORTEX_SRC_RTBASE + ebp);
725 //printk(KERN_INFO "vortex: srcdelWTD: while addr=%x, val=%x\n", ebp, edx);
726 esi++;
727 }
728 //7b30
729 ebp = ebx << 2;
730 if (edx & 0x10) { /* Delete entry in between others */
731 ebx = VORTEX_SRC_RTBASE + ((edx & 0xf) << 2);
732 edx = hwread(vortex->mmio, ebx);
733 //7b60
734 hwwrite(vortex->mmio,
735 VORTEX_SRC_RTBASE + ebp, edx);
736 hwwrite(vortex->mmio, ebx, 0);
737 //printk(KERN_INFO "vortex srcdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx);
738 } else { /* Delete last entry */
739 //7b83
740 if (esp14 == -1)
741 hwwrite(vortex->mmio,
742 VORTEX_SRC_CHNBASE +
743 (ch << 2), esp18 & 0xef);
744 else {
745 ebx = (0xffffffe0 & edx) | (0xf & ebx);
746 hwwrite(vortex->mmio,
747 VORTEX_SRC_RTBASE +
748 (esp14 << 2), ebx);
749 //printk(KERN_INFO"vortex srcdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx);
750 }
751 hwwrite(vortex->mmio,
752 VORTEX_SRC_RTBASE + ebp, 0);
753 return 1;
754 }
755 }
756 } else {
757 //7be0
758 vortex_src_dis_sr(vortex, ch);
759 hwwrite(vortex->mmio, ebp, 0);
760 }
761 return 1;
762}
763
764 /*FIFO*/
765
766static void
767vortex_fifo_clearadbdata(vortex_t * vortex, int fifo, int x)
768{
769 for (x--; x >= 0; x--)
770 hwwrite(vortex->mmio,
771 VORTEX_FIFO_ADBDATA +
772 (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
773}
774
775#if 0
776static void vortex_fifo_adbinitialize(vortex_t * vortex, int fifo, int j)
777{
778 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
779#ifdef CHIP_AU8820
780 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
781 (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
782#else
783 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
784 (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
785#endif
786}
787#endif
788static void vortex_fifo_setadbvalid(vortex_t * vortex, int fifo, int en)
789{
790 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
791 (hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)) &
792 0xffffffef) | ((1 & en) << 4) | FIFO_U1);
793}
794
795static void
796vortex_fifo_setadbctrl(vortex_t * vortex, int fifo, int stereo, int priority,
797 int empty, int valid, int f)
798{
799 int temp, lifeboat = 0;
800 //int this_8[NR_ADB] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; /* position */
801 int this_4 = 0x2;
802 /* f seems priority related.
803 * CAsp4AdbDma::SetPriority is the only place that calls SetAdbCtrl with f set to 1
804 * every where else it is set to 0. It seems, however, that CAsp4AdbDma::SetPriority
805 * is never called, thus the f related bits remain a mystery for now.
806 */
807 do {
808 temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
809 if (lifeboat++ > 0xbb8) {
810 dev_err(vortex->card->dev,
811 "vortex_fifo_setadbctrl fail\n");
812 break;
813 }
814 }
815 while (temp & FIFO_RDONLY);
816
817 // AU8830 semes to take some special care about fifo content (data).
818 // But i'm just to lazy to translate that :)
819 if (valid) {
820 if ((temp & FIFO_VALID) == 0) {
821 //this_8[fifo] = 0;
822 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); // this_4
823#ifdef CHIP_AU8820
824 temp = (this_4 & 0x1f) << 0xb;
825#else
826 temp = (this_4 & 0x3f) << 0xc;
827#endif
828 temp = (temp & 0xfffffffd) | ((stereo & 1) << 1);
829 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
830 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
831 temp |= FIFO_U1;
832 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
833#ifdef CHIP_AU8820
834 temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
835#endif
836#ifdef CHIP_AU8830
837 temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
838 temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
839#endif
840#ifdef CHIP_AU8810
841 temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
842 temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
843#endif
844 }
845 } else {
846 if (temp & FIFO_VALID) {
847#ifdef CHIP_AU8820
848 temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
849#endif
850#ifdef CHIP_AU8830
851 temp =
852 ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
853#endif
854#ifdef CHIP_AU8810
855 temp =
856 ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
857#endif
858 } else
859 /*if (this_8[fifo]) */
860 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
861 }
862 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), temp);
863 hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
864}
865
866#ifndef CHIP_AU8810
867static void vortex_fifo_clearwtdata(vortex_t * vortex, int fifo, int x)
868{
869 if (x < 1)
870 return;
871 for (x--; x >= 0; x--)
872 hwwrite(vortex->mmio,
873 VORTEX_FIFO_WTDATA +
874 (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
875}
876
877static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j)
878{
879 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
880#ifdef CHIP_AU8820
881 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
882 (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
883#else
884 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
885 (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
886#endif
887}
888
889static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en)
890{
891 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
892 (hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)) &
893 0xffffffef) | ((en & 1) << 4) | FIFO_U1);
894}
895
896static void
897vortex_fifo_setwtctrl(vortex_t * vortex, int fifo, int ctrl, int priority,
898 int empty, int valid, int f)
899{
900 int temp = 0, lifeboat = 0;
901 int this_4 = 2;
902
903 do {
904 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
905 if (lifeboat++ > 0xbb8) {
906 dev_err(vortex->card->dev,
907 "vortex_fifo_setwtctrl fail\n");
908 break;
909 }
910 }
911 while (temp & FIFO_RDONLY);
912
913 if (valid) {
914 if ((temp & FIFO_VALID) == 0) {
915 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); // this_4
916#ifdef CHIP_AU8820
917 temp = (this_4 & 0x1f) << 0xb;
918#else
919 temp = (this_4 & 0x3f) << 0xc;
920#endif
921 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
922 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
923 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
924 temp |= FIFO_U1;
925 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
926#ifdef CHIP_AU8820
927 temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
928#endif
929#ifdef CHIP_AU8830
930 temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
931 temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
932#endif
933#ifdef CHIP_AU8810
934 temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
935 temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
936#endif
937 }
938 } else {
939 if (temp & FIFO_VALID) {
940#ifdef CHIP_AU8820
941 temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
942#endif
943#ifdef CHIP_AU8830
944 temp =
945 ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
946#endif
947#ifdef CHIP_AU8810
948 temp =
949 ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
950#endif
951 } else
952 /*if (this_8[fifo]) */
953 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
954 }
955 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
956 hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
957
958/*
959 do {
960 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
961 if (lifeboat++ > 0xbb8) {
962 pr_err( "Vortex: vortex_fifo_setwtctrl fail (hanging)\n");
963 break;
964 }
965 } while ((temp & FIFO_RDONLY)&&(temp & FIFO_VALID)&&(temp != 0xFFFFFFFF));
966
967
968 if (valid) {
969 if (temp & FIFO_VALID) {
970 temp = 0x40000;
971 //temp |= 0x08000000;
972 //temp |= 0x10000000;
973 //temp |= 0x04000000;
974 //temp |= 0x00400000;
975 temp |= 0x1c400000;
976 temp &= 0xFFFFFFF3;
977 temp &= 0xFFFFFFEF;
978 temp |= (valid & 1) << 4;
979 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
980 return;
981 } else {
982 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
983 return;
984 }
985 } else {
986 temp &= 0xffffffef;
987 temp |= 0x08000000;
988 temp |= 0x10000000;
989 temp |= 0x04000000;
990 temp |= 0x00400000;
991 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
992 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
993 //((temp >> 6) & 0x3f)
994
995 priority = 0;
996 if (((temp & 0x0fc0) ^ ((temp >> 6) & 0x0fc0)) & 0FFFFFFC0)
997 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
998 valid = 0xfb;
999 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
1000 temp = (temp & 0xfffdffff) | ((f & 1) << 0x11);
1001 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
1002 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
1003 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
1004 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1005 }
1006
1007 */
1008
1009 /*
1010 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
1011 temp = (temp & 0xfffdffff) | ((f & 1) << 0x11);
1012 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
1013 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
1014 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
1015 #ifdef FIFO_BITS
1016 temp = temp | FIFO_BITS | 40000;
1017 #endif
1018 // 0x1c440010, 0x1c400000
1019 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1020 */
1021}
1022
1023#endif
1024static void vortex_fifo_init(vortex_t * vortex)
1025{
1026 int x;
1027 u32 addr;
1028
1029 /* ADB DMA channels fifos. */
1030 addr = VORTEX_FIFO_ADBCTRL + ((NR_ADB - 1) * 4);
1031 for (x = NR_ADB - 1; x >= 0; x--) {
1032 hwwrite(vortex->mmio, addr, (FIFO_U0 | FIFO_U1));
1033 if (hwread(vortex->mmio, addr) != (FIFO_U0 | FIFO_U1))
1034 dev_err(vortex->card->dev, "bad adb fifo reset!\n");
1035 vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE);
1036 addr -= 4;
1037 }
1038
1039#ifndef CHIP_AU8810
1040 /* WT DMA channels fifos. */
1041 addr = VORTEX_FIFO_WTCTRL + ((NR_WT - 1) * 4);
1042 for (x = NR_WT - 1; x >= 0; x--) {
1043 hwwrite(vortex->mmio, addr, FIFO_U0);
1044 if (hwread(vortex->mmio, addr) != FIFO_U0)
1045 dev_err(vortex->card->dev,
1046 "bad wt fifo reset (0x%08x, 0x%08x)!\n",
1047 addr, hwread(vortex->mmio, addr));
1048 vortex_fifo_clearwtdata(vortex, x, FIFO_SIZE);
1049 addr -= 4;
1050 }
1051#endif
1052 /* trigger... */
1053#ifdef CHIP_AU8820
1054 hwwrite(vortex->mmio, 0xf8c0, 0xd03); //0x0843 0xd6b
1055#else
1056#ifdef CHIP_AU8830
1057 hwwrite(vortex->mmio, 0x17000, 0x61); /* wt a */
1058 hwwrite(vortex->mmio, 0x17004, 0x61); /* wt b */
1059#endif
1060 hwwrite(vortex->mmio, 0x17008, 0x61); /* adb */
1061#endif
1062}
1063
1064/* ADBDMA */
1065
1066static void vortex_adbdma_init(vortex_t * vortex)
1067{
1068}
1069
1070static void vortex_adbdma_setfirstbuffer(vortex_t * vortex, int adbdma)
1071{
1072 stream_t *dma = &vortex->dma_adb[adbdma];
1073
1074 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1075 dma->dma_ctrl);
1076}
1077
1078static void vortex_adbdma_setstartbuffer(vortex_t * vortex, int adbdma, int sb)
1079{
1080 stream_t *dma = &vortex->dma_adb[adbdma];
1081 //hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2), sb << (((NR_ADB-1)-((adbdma&0xf)*2))));
1082 hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2),
1083 sb << ((0xf - (adbdma & 0xf)) * 2));
1084 dma->period_real = dma->period_virt = sb;
1085}
1086
1087static void
1088vortex_adbdma_setbuffers(vortex_t * vortex, int adbdma,
1089 int psize, int count)
1090{
1091 stream_t *dma = &vortex->dma_adb[adbdma];
1092
1093 dma->period_bytes = psize;
1094 dma->nr_periods = count;
1095
1096 dma->cfg0 = 0;
1097 dma->cfg1 = 0;
1098 switch (count) {
1099 /* Four or more pages */
1100 default:
1101 case 4:
1102 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize - 1);
1103 hwwrite(vortex->mmio,
1104 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0xc,
1105 snd_pcm_sgbuf_get_addr(dma->substream, psize * 3));
1106 fallthrough;
1107 /* 3 pages */
1108 case 3:
1109 dma->cfg0 |= 0x12000000;
1110 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
1111 hwwrite(vortex->mmio,
1112 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x8,
1113 snd_pcm_sgbuf_get_addr(dma->substream, psize * 2));
1114 fallthrough;
1115 /* 2 pages */
1116 case 2:
1117 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize - 1);
1118 hwwrite(vortex->mmio,
1119 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x4,
1120 snd_pcm_sgbuf_get_addr(dma->substream, psize));
1121 fallthrough;
1122 /* 1 page */
1123 case 1:
1124 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
1125 hwwrite(vortex->mmio,
1126 VORTEX_ADBDMA_BUFBASE + (adbdma << 4),
1127 snd_pcm_sgbuf_get_addr(dma->substream, 0));
1128 break;
1129 }
1130 /*
1131 pr_debug( "vortex: cfg0 = 0x%x\nvortex: cfg1=0x%x\n",
1132 dma->cfg0, dma->cfg1);
1133 */
1134 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + (adbdma << 3), dma->cfg0);
1135 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG1 + (adbdma << 3), dma->cfg1);
1136
1137 vortex_adbdma_setfirstbuffer(vortex, adbdma);
1138 vortex_adbdma_setstartbuffer(vortex, adbdma, 0);
1139}
1140
1141static void
1142vortex_adbdma_setmode(vortex_t * vortex, int adbdma, int ie, int dir,
1143 int fmt, int stereo, u32 offset)
1144{
1145 stream_t *dma = &vortex->dma_adb[adbdma];
1146
1147 dma->dma_unknown = stereo;
1148 dma->dma_ctrl =
1149 ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1150 /* Enable PCMOUT interrupts. */
1151 dma->dma_ctrl =
1152 (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1153
1154 dma->dma_ctrl =
1155 (dma->dma_ctrl & ~DIR_MASK) | ((dir << DIR_SHIFT) & DIR_MASK);
1156 dma->dma_ctrl =
1157 (dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1158
1159 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1160 dma->dma_ctrl);
1161 hwread(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2));
1162}
1163
1164static int vortex_adbdma_bufshift(vortex_t * vortex, int adbdma)
1165{
1166 stream_t *dma = &vortex->dma_adb[adbdma];
1167 int page, p, pp, delta, i;
1168
1169 page =
1170 (hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)) &
1171 ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT;
1172 if (dma->nr_periods >= 4)
1173 delta = (page - dma->period_real) & 3;
1174 else {
1175 delta = (page - dma->period_real);
1176 if (delta < 0)
1177 delta += dma->nr_periods;
1178 }
1179 if (delta == 0)
1180 return 0;
1181
1182 /* refresh hw page table */
1183 if (dma->nr_periods > 4) {
1184 for (i = 0; i < delta; i++) {
1185 /* p: audio buffer page index */
1186 p = dma->period_virt + i + 4;
1187 if (p >= dma->nr_periods)
1188 p -= dma->nr_periods;
1189 /* pp: hardware DMA page index. */
1190 pp = dma->period_real + i;
1191 if (pp >= 4)
1192 pp -= 4;
1193 //hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE+(((adbdma << 2)+pp) << 2), dma->table[p].addr);
1194 hwwrite(vortex->mmio,
1195 VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2),
1196 snd_pcm_sgbuf_get_addr(dma->substream,
1197 dma->period_bytes * p));
1198 /* Force write through cache. */
1199 hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE +
1200 (((adbdma << 2) + pp) << 2));
1201 }
1202 }
1203 dma->period_virt += delta;
1204 dma->period_real = page;
1205 if (dma->period_virt >= dma->nr_periods)
1206 dma->period_virt -= dma->nr_periods;
1207 if (delta != 1)
1208 dev_info(vortex->card->dev,
1209 "%d virt=%d, real=%d, delta=%d\n",
1210 adbdma, dma->period_virt, dma->period_real, delta);
1211
1212 return delta;
1213}
1214
1215
1216static void vortex_adbdma_resetup(vortex_t *vortex, int adbdma) {
1217 stream_t *dma = &vortex->dma_adb[adbdma];
1218 int p, pp, i;
1219
1220 /* refresh hw page table */
1221 for (i=0 ; i < 4 && i < dma->nr_periods; i++) {
1222 /* p: audio buffer page index */
1223 p = dma->period_virt + i;
1224 if (p >= dma->nr_periods)
1225 p -= dma->nr_periods;
1226 /* pp: hardware DMA page index. */
1227 pp = dma->period_real + i;
1228 if (dma->nr_periods < 4) {
1229 if (pp >= dma->nr_periods)
1230 pp -= dma->nr_periods;
1231 }
1232 else {
1233 if (pp >= 4)
1234 pp -= 4;
1235 }
1236 hwwrite(vortex->mmio,
1237 VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2),
1238 snd_pcm_sgbuf_get_addr(dma->substream,
1239 dma->period_bytes * p));
1240 /* Force write through cache. */
1241 hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (((adbdma << 2)+pp) << 2));
1242 }
1243}
1244
1245static inline int vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma)
1246{
1247 stream_t *dma = &vortex->dma_adb[adbdma];
1248 int temp, page, delta;
1249
1250 temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2));
1251 page = (temp & ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT;
1252 if (dma->nr_periods >= 4)
1253 delta = (page - dma->period_real) & 3;
1254 else {
1255 delta = (page - dma->period_real);
1256 if (delta < 0)
1257 delta += dma->nr_periods;
1258 }
1259 return (dma->period_virt + delta) * dma->period_bytes
1260 + (temp & (dma->period_bytes - 1));
1261}
1262
1263static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma)
1264{
1265 int this_8 = 0 /*empty */ , this_4 = 0 /*priority */ ;
1266 stream_t *dma = &vortex->dma_adb[adbdma];
1267
1268 switch (dma->fifo_status) {
1269 case FIFO_START:
1270 vortex_fifo_setadbvalid(vortex, adbdma,
1271 dma->fifo_enabled ? 1 : 0);
1272 break;
1273 case FIFO_STOP:
1274 this_8 = 1;
1275 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1276 dma->dma_ctrl);
1277 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1278 this_4, this_8,
1279 dma->fifo_enabled ? 1 : 0, 0);
1280 break;
1281 case FIFO_PAUSE:
1282 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1283 this_4, this_8,
1284 dma->fifo_enabled ? 1 : 0, 0);
1285 break;
1286 }
1287 dma->fifo_status = FIFO_START;
1288}
1289
1290static void vortex_adbdma_resumefifo(vortex_t * vortex, int adbdma)
1291{
1292 stream_t *dma = &vortex->dma_adb[adbdma];
1293
1294 int this_8 = 1, this_4 = 0;
1295 switch (dma->fifo_status) {
1296 case FIFO_STOP:
1297 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1298 dma->dma_ctrl);
1299 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1300 this_4, this_8,
1301 dma->fifo_enabled ? 1 : 0, 0);
1302 break;
1303 case FIFO_PAUSE:
1304 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1305 this_4, this_8,
1306 dma->fifo_enabled ? 1 : 0, 0);
1307 break;
1308 }
1309 dma->fifo_status = FIFO_START;
1310}
1311
1312static void vortex_adbdma_pausefifo(vortex_t * vortex, int adbdma)
1313{
1314 stream_t *dma = &vortex->dma_adb[adbdma];
1315
1316 int this_8 = 0, this_4 = 0;
1317 switch (dma->fifo_status) {
1318 case FIFO_START:
1319 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1320 this_4, this_8, 0, 0);
1321 break;
1322 case FIFO_STOP:
1323 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1324 dma->dma_ctrl);
1325 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1326 this_4, this_8, 0, 0);
1327 break;
1328 }
1329 dma->fifo_status = FIFO_PAUSE;
1330}
1331
1332static void vortex_adbdma_stopfifo(vortex_t * vortex, int adbdma)
1333{
1334 stream_t *dma = &vortex->dma_adb[adbdma];
1335
1336 int this_4 = 0, this_8 = 0;
1337 if (dma->fifo_status == FIFO_START)
1338 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1339 this_4, this_8, 0, 0);
1340 else if (dma->fifo_status == FIFO_STOP)
1341 return;
1342 dma->fifo_status = FIFO_STOP;
1343 dma->fifo_enabled = 0;
1344}
1345
1346/* WTDMA */
1347
1348#ifndef CHIP_AU8810
1349static void vortex_wtdma_setfirstbuffer(vortex_t * vortex, int wtdma)
1350{
1351 //int this_7c=dma_ctrl;
1352 stream_t *dma = &vortex->dma_wt[wtdma];
1353
1354 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1355}
1356
1357static void vortex_wtdma_setstartbuffer(vortex_t * vortex, int wtdma, int sb)
1358{
1359 stream_t *dma = &vortex->dma_wt[wtdma];
1360 //hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2), sb << ((0x1f-(wtdma&0xf)*2)));
1361 hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2),
1362 sb << ((0xf - (wtdma & 0xf)) * 2));
1363 dma->period_real = dma->period_virt = sb;
1364}
1365
1366static void
1367vortex_wtdma_setbuffers(vortex_t * vortex, int wtdma,
1368 int psize, int count)
1369{
1370 stream_t *dma = &vortex->dma_wt[wtdma];
1371
1372 dma->period_bytes = psize;
1373 dma->nr_periods = count;
1374
1375 dma->cfg0 = 0;
1376 dma->cfg1 = 0;
1377 switch (count) {
1378 /* Four or more pages */
1379 default:
1380 case 4:
1381 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize-1);
1382 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0xc,
1383 snd_pcm_sgbuf_get_addr(dma->substream, psize * 3));
1384 fallthrough;
1385 /* 3 pages */
1386 case 3:
1387 dma->cfg0 |= 0x12000000;
1388 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
1389 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x8,
1390 snd_pcm_sgbuf_get_addr(dma->substream, psize * 2));
1391 fallthrough;
1392 /* 2 pages */
1393 case 2:
1394 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize-1);
1395 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x4,
1396 snd_pcm_sgbuf_get_addr(dma->substream, psize));
1397 fallthrough;
1398 /* 1 page */
1399 case 1:
1400 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
1401 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4),
1402 snd_pcm_sgbuf_get_addr(dma->substream, 0));
1403 break;
1404 }
1405 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0);
1406 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1);
1407
1408 vortex_wtdma_setfirstbuffer(vortex, wtdma);
1409 vortex_wtdma_setstartbuffer(vortex, wtdma, 0);
1410}
1411
1412static void
1413vortex_wtdma_setmode(vortex_t * vortex, int wtdma, int ie, int fmt, int d,
1414 /*int e, */ u32 offset)
1415{
1416 stream_t *dma = &vortex->dma_wt[wtdma];
1417
1418 //dma->this_08 = e;
1419 dma->dma_unknown = d;
1420 dma->dma_ctrl = 0;
1421 dma->dma_ctrl =
1422 ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1423 /* PCMOUT interrupt */
1424 dma->dma_ctrl =
1425 (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1426 /* Always playback. */
1427 dma->dma_ctrl |= (1 << DIR_SHIFT);
1428 /* Audio Format */
1429 dma->dma_ctrl =
1430 (dma->dma_ctrl & FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1431 /* Write into hardware */
1432 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1433}
1434
1435static int vortex_wtdma_bufshift(vortex_t * vortex, int wtdma)
1436{
1437 stream_t *dma = &vortex->dma_wt[wtdma];
1438 int page, p, pp, delta, i;
1439
1440 page =
1441 (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2))
1442 >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK;
1443 if (dma->nr_periods >= 4)
1444 delta = (page - dma->period_real) & 3;
1445 else {
1446 delta = (page - dma->period_real);
1447 if (delta < 0)
1448 delta += dma->nr_periods;
1449 }
1450 if (delta == 0)
1451 return 0;
1452
1453 /* refresh hw page table */
1454 if (dma->nr_periods > 4) {
1455 for (i = 0; i < delta; i++) {
1456 /* p: audio buffer page index */
1457 p = dma->period_virt + i + 4;
1458 if (p >= dma->nr_periods)
1459 p -= dma->nr_periods;
1460 /* pp: hardware DMA page index. */
1461 pp = dma->period_real + i;
1462 if (pp >= 4)
1463 pp -= 4;
1464 hwwrite(vortex->mmio,
1465 VORTEX_WTDMA_BUFBASE +
1466 (((wtdma << 2) + pp) << 2),
1467 snd_pcm_sgbuf_get_addr(dma->substream,
1468 dma->period_bytes * p));
1469 /* Force write through cache. */
1470 hwread(vortex->mmio, VORTEX_WTDMA_BUFBASE +
1471 (((wtdma << 2) + pp) << 2));
1472 }
1473 }
1474 dma->period_virt += delta;
1475 if (dma->period_virt >= dma->nr_periods)
1476 dma->period_virt -= dma->nr_periods;
1477 dma->period_real = page;
1478
1479 if (delta != 1)
1480 dev_warn(vortex->card->dev, "wt virt = %d, delta = %d\n",
1481 dma->period_virt, delta);
1482
1483 return delta;
1484}
1485
1486#if 0
1487static void
1488vortex_wtdma_getposition(vortex_t * vortex, int wtdma, int *subbuf, int *pos)
1489{
1490 int temp;
1491 temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
1492 *subbuf = (temp >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK;
1493 *pos = temp & POS_MASK;
1494}
1495
1496static int vortex_wtdma_getcursubuffer(vortex_t * vortex, int wtdma)
1497{
1498 return ((hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >>
1499 POS_SHIFT) & POS_MASK);
1500}
1501#endif
1502static inline int vortex_wtdma_getlinearpos(vortex_t * vortex, int wtdma)
1503{
1504 stream_t *dma = &vortex->dma_wt[wtdma];
1505 int temp;
1506
1507 temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
1508 temp = (dma->period_virt * dma->period_bytes) + (temp & (dma->period_bytes - 1));
1509 return temp;
1510}
1511
1512static void vortex_wtdma_startfifo(vortex_t * vortex, int wtdma)
1513{
1514 stream_t *dma = &vortex->dma_wt[wtdma];
1515 int this_8 = 0, this_4 = 0;
1516
1517 switch (dma->fifo_status) {
1518 case FIFO_START:
1519 vortex_fifo_setwtvalid(vortex, wtdma,
1520 dma->fifo_enabled ? 1 : 0);
1521 break;
1522 case FIFO_STOP:
1523 this_8 = 1;
1524 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1525 dma->dma_ctrl);
1526 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1527 this_4, this_8,
1528 dma->fifo_enabled ? 1 : 0, 0);
1529 break;
1530 case FIFO_PAUSE:
1531 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1532 this_4, this_8,
1533 dma->fifo_enabled ? 1 : 0, 0);
1534 break;
1535 }
1536 dma->fifo_status = FIFO_START;
1537}
1538
1539static void vortex_wtdma_resumefifo(vortex_t * vortex, int wtdma)
1540{
1541 stream_t *dma = &vortex->dma_wt[wtdma];
1542
1543 int this_8 = 0, this_4 = 0;
1544 switch (dma->fifo_status) {
1545 case FIFO_STOP:
1546 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1547 dma->dma_ctrl);
1548 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1549 this_4, this_8,
1550 dma->fifo_enabled ? 1 : 0, 0);
1551 break;
1552 case FIFO_PAUSE:
1553 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1554 this_4, this_8,
1555 dma->fifo_enabled ? 1 : 0, 0);
1556 break;
1557 }
1558 dma->fifo_status = FIFO_START;
1559}
1560
1561static void vortex_wtdma_pausefifo(vortex_t * vortex, int wtdma)
1562{
1563 stream_t *dma = &vortex->dma_wt[wtdma];
1564
1565 int this_8 = 0, this_4 = 0;
1566 switch (dma->fifo_status) {
1567 case FIFO_START:
1568 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1569 this_4, this_8, 0, 0);
1570 break;
1571 case FIFO_STOP:
1572 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1573 dma->dma_ctrl);
1574 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1575 this_4, this_8, 0, 0);
1576 break;
1577 }
1578 dma->fifo_status = FIFO_PAUSE;
1579}
1580
1581static void vortex_wtdma_stopfifo(vortex_t * vortex, int wtdma)
1582{
1583 stream_t *dma = &vortex->dma_wt[wtdma];
1584
1585 int this_4 = 0, this_8 = 0;
1586 if (dma->fifo_status == FIFO_START)
1587 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1588 this_4, this_8, 0, 0);
1589 else if (dma->fifo_status == FIFO_STOP)
1590 return;
1591 dma->fifo_status = FIFO_STOP;
1592 dma->fifo_enabled = 0;
1593}
1594
1595#endif
1596/* ADB Routes */
1597
1598typedef int ADBRamLink;
1599static void vortex_adb_init(vortex_t * vortex)
1600{
1601 int i;
1602 /* it looks like we are writing more than we need to...
1603 * if we write what we are supposed to it breaks things... */
1604 hwwrite(vortex->mmio, VORTEX_ADB_SR, 0);
1605 for (i = 0; i < VORTEX_ADB_RTBASE_COUNT; i++)
1606 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (i << 2),
1607 hwread(vortex->mmio,
1608 VORTEX_ADB_RTBASE + (i << 2)) | ROUTE_MASK);
1609 for (i = 0; i < VORTEX_ADB_CHNBASE_COUNT; i++) {
1610 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (i << 2),
1611 hwread(vortex->mmio,
1612 VORTEX_ADB_CHNBASE + (i << 2)) | ROUTE_MASK);
1613 }
1614}
1615
1616static void vortex_adb_en_sr(vortex_t * vortex, int channel)
1617{
1618 hwwrite(vortex->mmio, VORTEX_ADB_SR,
1619 hwread(vortex->mmio, VORTEX_ADB_SR) | (0x1 << channel));
1620}
1621
1622static void vortex_adb_dis_sr(vortex_t * vortex, int channel)
1623{
1624 hwwrite(vortex->mmio, VORTEX_ADB_SR,
1625 hwread(vortex->mmio, VORTEX_ADB_SR) & ~(0x1 << channel));
1626}
1627
1628static void
1629vortex_adb_addroutes(vortex_t * vortex, unsigned char channel,
1630 ADBRamLink * route, int rnum)
1631{
1632 int temp, prev, lifeboat = 0;
1633
1634 if ((rnum <= 0) || (route == NULL))
1635 return;
1636 /* Write last routes. */
1637 rnum--;
1638 hwwrite(vortex->mmio,
1639 VORTEX_ADB_RTBASE + ((route[rnum] & ADB_MASK) << 2),
1640 ROUTE_MASK);
1641 while (rnum > 0) {
1642 hwwrite(vortex->mmio,
1643 VORTEX_ADB_RTBASE +
1644 ((route[rnum - 1] & ADB_MASK) << 2), route[rnum]);
1645 rnum--;
1646 }
1647 /* Write first route. */
1648 temp =
1649 hwread(vortex->mmio,
1650 VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
1651 if (temp == ADB_MASK) {
1652 /* First entry on this channel. */
1653 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
1654 route[0]);
1655 vortex_adb_en_sr(vortex, channel);
1656 return;
1657 }
1658 /* Not first entry on this channel. Need to link. */
1659 do {
1660 prev = temp;
1661 temp =
1662 hwread(vortex->mmio,
1663 VORTEX_ADB_RTBASE + (temp << 2)) & ADB_MASK;
1664 if ((lifeboat++) > ADB_MASK) {
1665 dev_err(vortex->card->dev,
1666 "vortex_adb_addroutes: unending route! 0x%x\n",
1667 *route);
1668 return;
1669 }
1670 }
1671 while (temp != ADB_MASK);
1672 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), route[0]);
1673}
1674
1675static void
1676vortex_adb_delroutes(vortex_t * vortex, unsigned char channel,
1677 ADBRamLink route0, ADBRamLink route1)
1678{
1679 int temp, lifeboat = 0, prev;
1680
1681 /* Find route. */
1682 temp =
1683 hwread(vortex->mmio,
1684 VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
1685 if (temp == (route0 & ADB_MASK)) {
1686 temp =
1687 hwread(vortex->mmio,
1688 VORTEX_ADB_RTBASE + ((route1 & ADB_MASK) << 2));
1689 if ((temp & ADB_MASK) == ADB_MASK)
1690 vortex_adb_dis_sr(vortex, channel);
1691 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
1692 temp);
1693 return;
1694 }
1695 do {
1696 prev = temp;
1697 temp =
1698 hwread(vortex->mmio,
1699 VORTEX_ADB_RTBASE + (prev << 2)) & ADB_MASK;
1700 if (((lifeboat++) > ADB_MASK) || (temp == ADB_MASK)) {
1701 dev_err(vortex->card->dev,
1702 "vortex_adb_delroutes: route not found! 0x%x\n",
1703 route0);
1704 return;
1705 }
1706 }
1707 while (temp != (route0 & ADB_MASK));
1708 temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
1709 if ((temp & ADB_MASK) == route1)
1710 temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
1711 /* Make bridge over deleted route. */
1712 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), temp);
1713}
1714
1715static void
1716vortex_route(vortex_t * vortex, int en, unsigned char channel,
1717 unsigned char source, unsigned char dest)
1718{
1719 ADBRamLink route;
1720
1721 route = ((source & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1722 if (en) {
1723 vortex_adb_addroutes(vortex, channel, &route, 1);
1724 if ((source < (OFFSET_SRCOUT + NR_SRC))
1725 && (source >= OFFSET_SRCOUT))
1726 vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
1727 channel);
1728 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1729 && (source >= OFFSET_MIXOUT))
1730 vortex_mixer_addWTD(vortex,
1731 (source - OFFSET_MIXOUT), channel);
1732 } else {
1733 vortex_adb_delroutes(vortex, channel, route, route);
1734 if ((source < (OFFSET_SRCOUT + NR_SRC))
1735 && (source >= OFFSET_SRCOUT))
1736 vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
1737 channel);
1738 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1739 && (source >= OFFSET_MIXOUT))
1740 vortex_mixer_delWTD(vortex,
1741 (source - OFFSET_MIXOUT), channel);
1742 }
1743}
1744
1745#if 0
1746static void
1747vortex_routes(vortex_t * vortex, int en, unsigned char channel,
1748 unsigned char source, unsigned char dest0, unsigned char dest1)
1749{
1750 ADBRamLink route[2];
1751
1752 route[0] = ((source & ADB_MASK) << ADB_SHIFT) | (dest0 & ADB_MASK);
1753 route[1] = ((source & ADB_MASK) << ADB_SHIFT) | (dest1 & ADB_MASK);
1754
1755 if (en) {
1756 vortex_adb_addroutes(vortex, channel, route, 2);
1757 if ((source < (OFFSET_SRCOUT + NR_SRC))
1758 && (source >= (OFFSET_SRCOUT)))
1759 vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
1760 channel);
1761 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1762 && (source >= (OFFSET_MIXOUT)))
1763 vortex_mixer_addWTD(vortex,
1764 (source - OFFSET_MIXOUT), channel);
1765 } else {
1766 vortex_adb_delroutes(vortex, channel, route[0], route[1]);
1767 if ((source < (OFFSET_SRCOUT + NR_SRC))
1768 && (source >= (OFFSET_SRCOUT)))
1769 vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
1770 channel);
1771 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1772 && (source >= (OFFSET_MIXOUT)))
1773 vortex_mixer_delWTD(vortex,
1774 (source - OFFSET_MIXOUT), channel);
1775 }
1776}
1777
1778#endif
1779/* Route two sources to same target. Sources must be of same class !!! */
1780static void
1781vortex_routeLRT(vortex_t * vortex, int en, unsigned char ch,
1782 unsigned char source0, unsigned char source1,
1783 unsigned char dest)
1784{
1785 ADBRamLink route[2];
1786
1787 route[0] = ((source0 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1788 route[1] = ((source1 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1789
1790 if (dest < 0x10)
1791 route[1] = (route[1] & ~ADB_MASK) | (dest + 0x20); /* fifo A */
1792
1793 if (en) {
1794 vortex_adb_addroutes(vortex, ch, route, 2);
1795 if ((source0 < (OFFSET_SRCOUT + NR_SRC))
1796 && (source0 >= OFFSET_SRCOUT)) {
1797 vortex_src_addWTD(vortex,
1798 (source0 - OFFSET_SRCOUT), ch);
1799 vortex_src_addWTD(vortex,
1800 (source1 - OFFSET_SRCOUT), ch);
1801 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
1802 && (source0 >= OFFSET_MIXOUT)) {
1803 vortex_mixer_addWTD(vortex,
1804 (source0 - OFFSET_MIXOUT), ch);
1805 vortex_mixer_addWTD(vortex,
1806 (source1 - OFFSET_MIXOUT), ch);
1807 }
1808 } else {
1809 vortex_adb_delroutes(vortex, ch, route[0], route[1]);
1810 if ((source0 < (OFFSET_SRCOUT + NR_SRC))
1811 && (source0 >= OFFSET_SRCOUT)) {
1812 vortex_src_delWTD(vortex,
1813 (source0 - OFFSET_SRCOUT), ch);
1814 vortex_src_delWTD(vortex,
1815 (source1 - OFFSET_SRCOUT), ch);
1816 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
1817 && (source0 >= OFFSET_MIXOUT)) {
1818 vortex_mixer_delWTD(vortex,
1819 (source0 - OFFSET_MIXOUT), ch);
1820 vortex_mixer_delWTD(vortex,
1821 (source1 - OFFSET_MIXOUT), ch);
1822 }
1823 }
1824}
1825
1826/* Connection stuff */
1827
1828// Connect adbdma to src('s).
1829static void
1830vortex_connection_adbdma_src(vortex_t * vortex, int en, unsigned char ch,
1831 unsigned char adbdma, unsigned char src)
1832{
1833 vortex_route(vortex, en, ch, ADB_DMA(adbdma), ADB_SRCIN(src));
1834}
1835
1836// Connect SRC to mixin.
1837static void
1838vortex_connection_src_mixin(vortex_t * vortex, int en,
1839 unsigned char channel, unsigned char src,
1840 unsigned char mixin)
1841{
1842 vortex_route(vortex, en, channel, ADB_SRCOUT(src), ADB_MIXIN(mixin));
1843}
1844
1845// Connect mixin with mix output.
1846static void
1847vortex_connection_mixin_mix(vortex_t * vortex, int en, unsigned char mixin,
1848 unsigned char mix, int a)
1849{
1850 if (en) {
1851 vortex_mix_enableinput(vortex, mix, mixin);
1852 vortex_mix_setinputvolumebyte(vortex, mix, mixin, MIX_DEFIGAIN); // added to original code.
1853 } else
1854 vortex_mix_disableinput(vortex, mix, mixin, a);
1855}
1856
1857// Connect absolute address to mixin.
1858static void
1859vortex_connection_adb_mixin(vortex_t * vortex, int en,
1860 unsigned char channel, unsigned char source,
1861 unsigned char mixin)
1862{
1863 vortex_route(vortex, en, channel, source, ADB_MIXIN(mixin));
1864}
1865
1866static void
1867vortex_connection_src_adbdma(vortex_t * vortex, int en, unsigned char ch,
1868 unsigned char src, unsigned char adbdma)
1869{
1870 vortex_route(vortex, en, ch, ADB_SRCOUT(src), ADB_DMA(adbdma));
1871}
1872
1873static void
1874vortex_connection_src_src_adbdma(vortex_t * vortex, int en,
1875 unsigned char ch, unsigned char src0,
1876 unsigned char src1, unsigned char adbdma)
1877{
1878
1879 vortex_routeLRT(vortex, en, ch, ADB_SRCOUT(src0), ADB_SRCOUT(src1),
1880 ADB_DMA(adbdma));
1881}
1882
1883// mix to absolute address.
1884static void
1885vortex_connection_mix_adb(vortex_t * vortex, int en, unsigned char ch,
1886 unsigned char mix, unsigned char dest)
1887{
1888 vortex_route(vortex, en, ch, ADB_MIXOUT(mix), dest);
1889 vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code.
1890}
1891
1892// mixer to src.
1893static void
1894vortex_connection_mix_src(vortex_t * vortex, int en, unsigned char ch,
1895 unsigned char mix, unsigned char src)
1896{
1897 vortex_route(vortex, en, ch, ADB_MIXOUT(mix), ADB_SRCIN(src));
1898 vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code.
1899}
1900
1901#if 0
1902static void
1903vortex_connection_adbdma_src_src(vortex_t * vortex, int en,
1904 unsigned char channel,
1905 unsigned char adbdma, unsigned char src0,
1906 unsigned char src1)
1907{
1908 vortex_routes(vortex, en, channel, ADB_DMA(adbdma),
1909 ADB_SRCIN(src0), ADB_SRCIN(src1));
1910}
1911
1912// Connect two mix to AdbDma.
1913static void
1914vortex_connection_mix_mix_adbdma(vortex_t * vortex, int en,
1915 unsigned char ch, unsigned char mix0,
1916 unsigned char mix1, unsigned char adbdma)
1917{
1918
1919 ADBRamLink routes[2];
1920 routes[0] =
1921 (((mix0 +
1922 OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | (adbdma & ADB_MASK);
1923 routes[1] =
1924 (((mix1 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | ((adbdma +
1925 0x20) &
1926 ADB_MASK);
1927 if (en) {
1928 vortex_adb_addroutes(vortex, ch, routes, 0x2);
1929 vortex_mixer_addWTD(vortex, mix0, ch);
1930 vortex_mixer_addWTD(vortex, mix1, ch);
1931 } else {
1932 vortex_adb_delroutes(vortex, ch, routes[0], routes[1]);
1933 vortex_mixer_delWTD(vortex, mix0, ch);
1934 vortex_mixer_delWTD(vortex, mix1, ch);
1935 }
1936}
1937#endif
1938
1939/* CODEC connect. */
1940
1941static void
1942vortex_connect_codecplay(vortex_t * vortex, int en, unsigned char mixers[])
1943{
1944#ifdef CHIP_AU8820
1945 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
1946 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
1947#else
1948#if 1
1949 // Connect front channels through EQ.
1950 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_EQIN(0));
1951 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_EQIN(1));
1952 /* Lower volume, since EQ has some gain. */
1953 vortex_mix_setvolumebyte(vortex, mixers[0], 0);
1954 vortex_mix_setvolumebyte(vortex, mixers[1], 0);
1955 vortex_route(vortex, en, 0x11, ADB_EQOUT(0), ADB_CODECOUT(0));
1956 vortex_route(vortex, en, 0x11, ADB_EQOUT(1), ADB_CODECOUT(1));
1957
1958 /* Check if reg 0x28 has SDAC bit set. */
1959 if (VORTEX_IS_QUAD(vortex)) {
1960 /* Rear channel. Note: ADB_CODECOUT(0+2) and (1+2) is for AC97 modem */
1961 vortex_connection_mix_adb(vortex, en, 0x11, mixers[2],
1962 ADB_CODECOUT(0 + 4));
1963 vortex_connection_mix_adb(vortex, en, 0x11, mixers[3],
1964 ADB_CODECOUT(1 + 4));
1965 /* pr_debug( "SDAC detected "); */
1966 }
1967#else
1968 // Use plain direct output to codec.
1969 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
1970 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
1971#endif
1972#endif
1973}
1974
1975static void
1976vortex_connect_codecrec(vortex_t * vortex, int en, unsigned char mixin0,
1977 unsigned char mixin1)
1978{
1979 /*
1980 Enable: 0x1, 0x1
1981 Channel: 0x11, 0x11
1982 ADB Source address: 0x48, 0x49
1983 Destination Asp4Topology_0x9c,0x98
1984 */
1985 vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(0), mixin0);
1986 vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(1), mixin1);
1987}
1988
1989// Higher level ADB audio path (de)allocator.
1990
1991/* Resource manager */
1992static const int resnum[VORTEX_RESOURCE_LAST] =
1993 { NR_ADB, NR_SRC, NR_MIXIN, NR_MIXOUT, NR_A3D };
1994/*
1995 Checkout/Checkin resource of given type.
1996 resmap: resource map to be used. If NULL means that we want to allocate
1997 a DMA resource (root of all other resources of a dma channel).
1998 out: Mean checkout if != 0. Else mean Checkin resource.
1999 restype: Indicates type of resource to be checked in or out.
2000*/
2001static int
2002vortex_adb_checkinout(vortex_t * vortex, int resmap[], int out, int restype)
2003{
2004 int i, qty = resnum[restype], resinuse = 0;
2005
2006 if (out) {
2007 /* Gather used resources by all streams. */
2008 for (i = 0; i < NR_ADB; i++) {
2009 resinuse |= vortex->dma_adb[i].resources[restype];
2010 }
2011 resinuse |= vortex->fixed_res[restype];
2012 /* Find and take free resource. */
2013 for (i = 0; i < qty; i++) {
2014 if ((resinuse & (1 << i)) == 0) {
2015 if (resmap != NULL)
2016 resmap[restype] |= (1 << i);
2017 else
2018 vortex->dma_adb[i].resources[restype] |= (1 << i);
2019 /*
2020 pr_debug(
2021 "vortex: ResManager: type %d out %d\n",
2022 restype, i);
2023 */
2024 return i;
2025 }
2026 }
2027 } else {
2028 if (resmap == NULL)
2029 return -EINVAL;
2030 /* Checkin first resource of type restype. */
2031 for (i = 0; i < qty; i++) {
2032 if (resmap[restype] & (1 << i)) {
2033 resmap[restype] &= ~(1 << i);
2034 /*
2035 pr_debug(
2036 "vortex: ResManager: type %d in %d\n",
2037 restype, i);
2038 */
2039 return i;
2040 }
2041 }
2042 }
2043 dev_err(vortex->card->dev,
2044 "FATAL: ResManager: resource type %d exhausted.\n",
2045 restype);
2046 return -ENOMEM;
2047}
2048
2049/* Default Connections */
2050
2051static void vortex_connect_default(vortex_t * vortex, int en)
2052{
2053 // Connect AC97 codec.
2054 vortex->mixplayb[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2055 VORTEX_RESOURCE_MIXOUT);
2056 vortex->mixplayb[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2057 VORTEX_RESOURCE_MIXOUT);
2058 if (VORTEX_IS_QUAD(vortex)) {
2059 vortex->mixplayb[2] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2060 VORTEX_RESOURCE_MIXOUT);
2061 vortex->mixplayb[3] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2062 VORTEX_RESOURCE_MIXOUT);
2063 }
2064 vortex_connect_codecplay(vortex, en, vortex->mixplayb);
2065
2066 vortex->mixcapt[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2067 VORTEX_RESOURCE_MIXIN);
2068 vortex->mixcapt[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2069 VORTEX_RESOURCE_MIXIN);
2070 vortex_connect_codecrec(vortex, en, MIX_CAPT(0), MIX_CAPT(1));
2071
2072 // Connect SPDIF
2073#ifndef CHIP_AU8820
2074 vortex->mixspdif[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2075 VORTEX_RESOURCE_MIXOUT);
2076 vortex->mixspdif[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2077 VORTEX_RESOURCE_MIXOUT);
2078 vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[0],
2079 ADB_SPDIFOUT(0));
2080 vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[1],
2081 ADB_SPDIFOUT(1));
2082#endif
2083 // Connect WT
2084#ifndef CHIP_AU8810
2085 vortex_wt_connect(vortex, en);
2086#endif
2087 // A3D (crosstalk canceler and A3D slices). AU8810 disabled for now.
2088#ifndef CHIP_AU8820
2089 vortex_Vort3D_connect(vortex, en);
2090#endif
2091 // Connect I2S
2092
2093 // Connect DSP interface for SQ3500 turbo (not here i think...)
2094
2095 // Connect AC98 modem codec
2096
2097}
2098
2099/*
2100 Allocate nr_ch pcm audio routes if dma < 0. If dma >= 0, existing routes
2101 are deallocated.
2102 dma: DMA engine routes to be deallocated when dma >= 0.
2103 nr_ch: Number of channels to be de/allocated.
2104 dir: direction of stream. Uses same values as substream->stream.
2105 type: Type of audio output/source (codec, spdif, i2s, dsp, etc)
2106 Return: Return allocated DMA or same DMA passed as "dma" when dma >= 0.
2107*/
2108static int
2109vortex_adb_allocroute(vortex_t *vortex, int dma, int nr_ch, int dir,
2110 int type, int subdev)
2111{
2112 stream_t *stream;
2113 int i, en;
2114 struct pcm_vol *p;
2115
2116 if (dma >= 0) {
2117 en = 0;
2118 vortex_adb_checkinout(vortex,
2119 vortex->dma_adb[dma].resources, en,
2120 VORTEX_RESOURCE_DMA);
2121 } else {
2122 en = 1;
2123 dma = vortex_adb_checkinout(vortex, NULL, en,
2124 VORTEX_RESOURCE_DMA);
2125 if (dma < 0)
2126 return -EBUSY;
2127 }
2128
2129 stream = &vortex->dma_adb[dma];
2130 stream->dma = dma;
2131 stream->dir = dir;
2132 stream->type = type;
2133
2134 /* PLAYBACK ROUTES. */
2135 if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
2136 int src[4], mix[4], ch_top;
2137#ifndef CHIP_AU8820
2138 int a3d = 0;
2139#endif
2140 /* Get SRC and MIXER hardware resources. */
2141 if (stream->type != VORTEX_PCM_SPDIF) {
2142 for (i = 0; i < nr_ch; i++) {
2143 src[i] = vortex_adb_checkinout(vortex,
2144 stream->resources, en,
2145 VORTEX_RESOURCE_SRC);
2146 if (src[i] < 0) {
2147 memset(stream->resources, 0,
2148 sizeof(stream->resources));
2149 return -EBUSY;
2150 }
2151 if (stream->type != VORTEX_PCM_A3D) {
2152 mix[i] = vortex_adb_checkinout(vortex,
2153 stream->resources,
2154 en,
2155 VORTEX_RESOURCE_MIXIN);
2156 if (mix[i] < 0) {
2157 memset(stream->resources,
2158 0,
2159 sizeof(stream->resources));
2160 return -EBUSY;
2161 }
2162 }
2163 }
2164 }
2165#ifndef CHIP_AU8820
2166 if (stream->type == VORTEX_PCM_A3D) {
2167 a3d = vortex_adb_checkinout(vortex,
2168 stream->resources, en,
2169 VORTEX_RESOURCE_A3D);
2170 if (a3d < 0) {
2171 memset(stream->resources, 0,
2172 sizeof(stream->resources));
2173 dev_err(vortex->card->dev,
2174 "out of A3D sources. Sorry\n");
2175 return -EBUSY;
2176 }
2177 /* (De)Initialize A3D hardware source. */
2178 vortex_Vort3D_InitializeSource(&vortex->a3d[a3d], en,
2179 vortex);
2180 }
2181 /* Make SPDIF out exclusive to "spdif" device when in use. */
2182 if ((stream->type == VORTEX_PCM_SPDIF) && (en)) {
2183 vortex_route(vortex, 0, 0x14,
2184 ADB_MIXOUT(vortex->mixspdif[0]),
2185 ADB_SPDIFOUT(0));
2186 vortex_route(vortex, 0, 0x14,
2187 ADB_MIXOUT(vortex->mixspdif[1]),
2188 ADB_SPDIFOUT(1));
2189 }
2190#endif
2191 /* Make playback routes. */
2192 for (i = 0; i < nr_ch; i++) {
2193 if (stream->type == VORTEX_PCM_ADB) {
2194 vortex_connection_adbdma_src(vortex, en,
2195 src[nr_ch - 1],
2196 dma,
2197 src[i]);
2198 vortex_connection_src_mixin(vortex, en,
2199 0x11, src[i],
2200 mix[i]);
2201 vortex_connection_mixin_mix(vortex, en,
2202 mix[i],
2203 MIX_PLAYB(i), 0);
2204#ifndef CHIP_AU8820
2205 vortex_connection_mixin_mix(vortex, en,
2206 mix[i],
2207 MIX_SPDIF(i % 2), 0);
2208 vortex_mix_setinputvolumebyte(vortex,
2209 MIX_SPDIF(i % 2),
2210 mix[i],
2211 MIX_DEFIGAIN);
2212#endif
2213 }
2214#ifndef CHIP_AU8820
2215 if (stream->type == VORTEX_PCM_A3D) {
2216 vortex_connection_adbdma_src(vortex, en,
2217 src[nr_ch - 1],
2218 dma,
2219 src[i]);
2220 vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_A3DIN(a3d));
2221 /* XTalk test. */
2222 //vortex_route(vortex, en, 0x11, dma, ADB_XTALKIN(i?9:4));
2223 //vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_XTALKIN(i?4:9));
2224 }
2225 if (stream->type == VORTEX_PCM_SPDIF)
2226 vortex_route(vortex, en, 0x14,
2227 ADB_DMA(stream->dma),
2228 ADB_SPDIFOUT(i));
2229#endif
2230 }
2231 if (stream->type != VORTEX_PCM_SPDIF && stream->type != VORTEX_PCM_A3D) {
2232 ch_top = (VORTEX_IS_QUAD(vortex) ? 4 : 2);
2233 for (i = nr_ch; i < ch_top; i++) {
2234 vortex_connection_mixin_mix(vortex, en,
2235 mix[i % nr_ch],
2236 MIX_PLAYB(i), 0);
2237#ifndef CHIP_AU8820
2238 vortex_connection_mixin_mix(vortex, en,
2239 mix[i % nr_ch],
2240 MIX_SPDIF(i % 2),
2241 0);
2242 vortex_mix_setinputvolumebyte(vortex,
2243 MIX_SPDIF(i % 2),
2244 mix[i % nr_ch],
2245 MIX_DEFIGAIN);
2246#endif
2247 }
2248 if (stream->type == VORTEX_PCM_ADB && en) {
2249 p = &vortex->pcm_vol[subdev];
2250 p->dma = dma;
2251 for (i = 0; i < nr_ch; i++)
2252 p->mixin[i] = mix[i];
2253 for (i = 0; i < ch_top; i++)
2254 p->vol[i] = 0;
2255 }
2256 }
2257#ifndef CHIP_AU8820
2258 else {
2259 if (nr_ch == 1 && stream->type == VORTEX_PCM_SPDIF)
2260 vortex_route(vortex, en, 0x14,
2261 ADB_DMA(stream->dma),
2262 ADB_SPDIFOUT(1));
2263 }
2264 /* Reconnect SPDIF out when "spdif" device is down. */
2265 if ((stream->type == VORTEX_PCM_SPDIF) && (!en)) {
2266 vortex_route(vortex, 1, 0x14,
2267 ADB_MIXOUT(vortex->mixspdif[0]),
2268 ADB_SPDIFOUT(0));
2269 vortex_route(vortex, 1, 0x14,
2270 ADB_MIXOUT(vortex->mixspdif[1]),
2271 ADB_SPDIFOUT(1));
2272 }
2273#endif
2274 /* CAPTURE ROUTES. */
2275 } else {
2276 int src[2], mix[2];
2277
2278 if (nr_ch < 1)
2279 return -EINVAL;
2280
2281 /* Get SRC and MIXER hardware resources. */
2282 for (i = 0; i < nr_ch; i++) {
2283 mix[i] = vortex_adb_checkinout(vortex,
2284 stream->resources, en,
2285 VORTEX_RESOURCE_MIXOUT);
2286 if (mix[i] < 0) {
2287 memset(stream->resources, 0,
2288 sizeof(stream->resources));
2289 return -EBUSY;
2290 }
2291 src[i] = vortex_adb_checkinout(vortex,
2292 stream->resources, en,
2293 VORTEX_RESOURCE_SRC);
2294 if (src[i] < 0) {
2295 memset(stream->resources, 0,
2296 sizeof(stream->resources));
2297 return -EBUSY;
2298 }
2299 }
2300
2301 /* Make capture routes. */
2302 vortex_connection_mixin_mix(vortex, en, MIX_CAPT(0), mix[0], 0);
2303 vortex_connection_mix_src(vortex, en, 0x11, mix[0], src[0]);
2304 if (nr_ch == 1) {
2305 vortex_connection_mixin_mix(vortex, en,
2306 MIX_CAPT(1), mix[0], 0);
2307 vortex_connection_src_adbdma(vortex, en,
2308 src[0],
2309 src[0], dma);
2310 } else {
2311 vortex_connection_mixin_mix(vortex, en,
2312 MIX_CAPT(1), mix[1], 0);
2313 vortex_connection_mix_src(vortex, en, 0x11, mix[1],
2314 src[1]);
2315 vortex_connection_src_src_adbdma(vortex, en,
2316 src[1], src[0],
2317 src[1], dma);
2318 }
2319 }
2320 vortex->dma_adb[dma].nr_ch = nr_ch;
2321
2322#if 0
2323 /* AC97 Codec channel setup. FIXME: this has no effect on some cards !! */
2324 if (nr_ch < 4) {
2325 /* Copy stereo to rear channel (surround) */
2326 snd_ac97_write_cache(vortex->codec,
2327 AC97_SIGMATEL_DAC2INVERT,
2328 snd_ac97_read(vortex->codec,
2329 AC97_SIGMATEL_DAC2INVERT)
2330 | 4);
2331 } else {
2332 /* Allow separate front and rear channels. */
2333 snd_ac97_write_cache(vortex->codec,
2334 AC97_SIGMATEL_DAC2INVERT,
2335 snd_ac97_read(vortex->codec,
2336 AC97_SIGMATEL_DAC2INVERT)
2337 & ~((u32)
2338 4));
2339 }
2340#endif
2341 return dma;
2342}
2343
2344/*
2345 Set the SampleRate of the SRC's attached to the given DMA engine.
2346 */
2347static void
2348vortex_adb_setsrc(vortex_t * vortex, int adbdma, unsigned int rate, int dir)
2349{
2350 stream_t *stream = &(vortex->dma_adb[adbdma]);
2351 int i, cvrt;
2352
2353 /* dir=1:play ; dir=0:rec */
2354 if (dir)
2355 cvrt = SRC_RATIO(rate, 48000);
2356 else
2357 cvrt = SRC_RATIO(48000, rate);
2358
2359 /* Setup SRC's */
2360 for (i = 0; i < NR_SRC; i++) {
2361 if (stream->resources[VORTEX_RESOURCE_SRC] & (1 << i))
2362 vortex_src_setupchannel(vortex, i, cvrt, 0, 0, i, dir, 1, cvrt, dir);
2363 }
2364}
2365
2366// Timer and ISR functions.
2367
2368static void vortex_settimer(vortex_t * vortex, int period)
2369{
2370 //set the timer period to <period> 48000ths of a second.
2371 hwwrite(vortex->mmio, VORTEX_IRQ_STAT, period);
2372}
2373
2374#if 0
2375static void vortex_enable_timer_int(vortex_t * card)
2376{
2377 hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2378 hwread(card->mmio, VORTEX_IRQ_CTRL) | IRQ_TIMER | 0x60);
2379}
2380
2381static void vortex_disable_timer_int(vortex_t * card)
2382{
2383 hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2384 hwread(card->mmio, VORTEX_IRQ_CTRL) & ~IRQ_TIMER);
2385}
2386
2387#endif
2388static void vortex_enable_int(vortex_t * card)
2389{
2390 // CAsp4ISR__EnableVortexInt_void_
2391 hwwrite(card->mmio, VORTEX_CTRL,
2392 hwread(card->mmio, VORTEX_CTRL) | CTRL_IRQ_ENABLE);
2393 hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2394 (hwread(card->mmio, VORTEX_IRQ_CTRL) & 0xffffefc0) | 0x24);
2395}
2396
2397static void vortex_disable_int(vortex_t * card)
2398{
2399 hwwrite(card->mmio, VORTEX_CTRL,
2400 hwread(card->mmio, VORTEX_CTRL) & ~CTRL_IRQ_ENABLE);
2401}
2402
2403static irqreturn_t vortex_interrupt(int irq, void *dev_id)
2404{
2405 vortex_t *vortex = dev_id;
2406 int i, handled;
2407 u32 source;
2408
2409 //check if the interrupt is ours.
2410 if (!(hwread(vortex->mmio, VORTEX_STAT) & 0x1))
2411 return IRQ_NONE;
2412
2413 // This is the Interrupt Enable flag we set before (consistency check).
2414 if (!(hwread(vortex->mmio, VORTEX_CTRL) & CTRL_IRQ_ENABLE))
2415 return IRQ_NONE;
2416
2417 source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
2418 // Reset IRQ flags.
2419 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, source);
2420 hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
2421 // Is at least one IRQ flag set?
2422 if (source == 0) {
2423 dev_err(vortex->card->dev, "missing irq source\n");
2424 return IRQ_NONE;
2425 }
2426
2427 handled = 0;
2428 // Attend every interrupt source.
2429 if (unlikely(source & IRQ_ERR_MASK)) {
2430 if (source & IRQ_FATAL) {
2431 dev_err(vortex->card->dev, "IRQ fatal error\n");
2432 }
2433 if (source & IRQ_PARITY) {
2434 dev_err(vortex->card->dev, "IRQ parity error\n");
2435 }
2436 if (source & IRQ_REG) {
2437 dev_err(vortex->card->dev, "IRQ reg error\n");
2438 }
2439 if (source & IRQ_FIFO) {
2440 dev_err(vortex->card->dev, "IRQ fifo error\n");
2441 }
2442 if (source & IRQ_DMA) {
2443 dev_err(vortex->card->dev, "IRQ dma error\n");
2444 }
2445 handled = 1;
2446 }
2447 if (source & IRQ_PCMOUT) {
2448 /* ALSA period acknowledge. */
2449 spin_lock(&vortex->lock);
2450 for (i = 0; i < NR_ADB; i++) {
2451 if (vortex->dma_adb[i].fifo_status == FIFO_START) {
2452 if (!vortex_adbdma_bufshift(vortex, i))
2453 continue;
2454 spin_unlock(&vortex->lock);
2455 snd_pcm_period_elapsed(vortex->dma_adb[i].
2456 substream);
2457 spin_lock(&vortex->lock);
2458 }
2459 }
2460#ifndef CHIP_AU8810
2461 for (i = 0; i < NR_WT; i++) {
2462 if (vortex->dma_wt[i].fifo_status == FIFO_START) {
2463 /* FIXME: we ignore the return value from
2464 * vortex_wtdma_bufshift() below as the delta
2465 * calculation seems not working for wavetable
2466 * by some reason
2467 */
2468 vortex_wtdma_bufshift(vortex, i);
2469 spin_unlock(&vortex->lock);
2470 snd_pcm_period_elapsed(vortex->dma_wt[i].
2471 substream);
2472 spin_lock(&vortex->lock);
2473 }
2474 }
2475#endif
2476 spin_unlock(&vortex->lock);
2477 handled = 1;
2478 }
2479 //Acknowledge the Timer interrupt
2480 if (source & IRQ_TIMER) {
2481 hwread(vortex->mmio, VORTEX_IRQ_STAT);
2482 handled = 1;
2483 }
2484 if ((source & IRQ_MIDI) && vortex->rmidi) {
2485 snd_mpu401_uart_interrupt(vortex->irq,
2486 vortex->rmidi->private_data);
2487 handled = 1;
2488 }
2489
2490 if (!handled) {
2491 dev_err(vortex->card->dev, "unknown irq source %x\n", source);
2492 }
2493 return IRQ_RETVAL(handled);
2494}
2495
2496/* Codec */
2497
2498#define POLL_COUNT 1000
2499static void vortex_codec_init(vortex_t * vortex)
2500{
2501 int i;
2502
2503 for (i = 0; i < 32; i++) {
2504 /* the windows driver writes -i, so we write -i */
2505 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), -i);
2506 msleep(2);
2507 }
2508 if (0) {
2509 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x8068);
2510 msleep(1);
2511 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
2512 msleep(1);
2513 } else {
2514 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
2515 msleep(2);
2516 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
2517 msleep(2);
2518 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80e8);
2519 msleep(2);
2520 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
2521 msleep(2);
2522 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
2523 msleep(2);
2524 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
2525 }
2526 for (i = 0; i < 32; i++) {
2527 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), -i);
2528 msleep(5);
2529 }
2530 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0xe8);
2531 msleep(1);
2532 /* Enable codec channels 0 and 1. */
2533 hwwrite(vortex->mmio, VORTEX_CODEC_EN,
2534 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_CODEC);
2535}
2536
2537static void
2538vortex_codec_write(struct snd_ac97 * codec, unsigned short addr, unsigned short data)
2539{
2540
2541 vortex_t *card = (vortex_t *) codec->private_data;
2542 unsigned int lifeboat = 0;
2543
2544 /* wait for transactions to clear */
2545 while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
2546 udelay(100);
2547 if (lifeboat++ > POLL_COUNT) {
2548 dev_err(card->card->dev, "ac97 codec stuck busy\n");
2549 return;
2550 }
2551 }
2552 /* write register */
2553 hwwrite(card->mmio, VORTEX_CODEC_IO,
2554 ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) |
2555 ((data << VORTEX_CODEC_DATSHIFT) & VORTEX_CODEC_DATMASK) |
2556 VORTEX_CODEC_WRITE |
2557 (codec->num << VORTEX_CODEC_ID_SHIFT) );
2558
2559 /* Flush Caches. */
2560 hwread(card->mmio, VORTEX_CODEC_IO);
2561}
2562
2563static unsigned short vortex_codec_read(struct snd_ac97 * codec, unsigned short addr)
2564{
2565
2566 vortex_t *card = (vortex_t *) codec->private_data;
2567 u32 read_addr, data;
2568 unsigned lifeboat = 0;
2569
2570 /* wait for transactions to clear */
2571 while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
2572 udelay(100);
2573 if (lifeboat++ > POLL_COUNT) {
2574 dev_err(card->card->dev, "ac97 codec stuck busy\n");
2575 return 0xffff;
2576 }
2577 }
2578 /* set up read address */
2579 read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) |
2580 (codec->num << VORTEX_CODEC_ID_SHIFT) ;
2581 hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr);
2582
2583 /* wait for address */
2584 do {
2585 udelay(100);
2586 data = hwread(card->mmio, VORTEX_CODEC_IO);
2587 if (lifeboat++ > POLL_COUNT) {
2588 dev_err(card->card->dev,
2589 "ac97 address never arrived\n");
2590 return 0xffff;
2591 }
2592 } while ((data & VORTEX_CODEC_ADDMASK) !=
2593 (addr << VORTEX_CODEC_ADDSHIFT));
2594
2595 /* return data. */
2596 return (u16) (data & VORTEX_CODEC_DATMASK);
2597}
2598
2599/* SPDIF support */
2600
2601static void vortex_spdif_init(vortex_t * vortex, int spdif_sr, int spdif_mode)
2602{
2603 int i, this_38 = 0, this_04 = 0, this_08 = 0, this_0c = 0;
2604
2605 /* CAsp4Spdif::InitializeSpdifHardware(void) */
2606 hwwrite(vortex->mmio, VORTEX_SPDIF_FLAGS,
2607 hwread(vortex->mmio, VORTEX_SPDIF_FLAGS) & 0xfff3fffd);
2608 //for (i=0x291D4; i<0x29200; i+=4)
2609 for (i = 0; i < 11; i++)
2610 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1 + (i << 2), 0);
2611 //hwwrite(vortex->mmio, 0x29190, hwread(vortex->mmio, 0x29190) | 0xc0000);
2612 hwwrite(vortex->mmio, VORTEX_CODEC_EN,
2613 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_SPDIF);
2614
2615 /* CAsp4Spdif::ProgramSRCInHardware(enum SPDIF_SR,enum SPDIFMODE) */
2616 if (this_04 && this_08) {
2617 int edi;
2618
2619 i = (((0x5DC00000 / spdif_sr) + 1) >> 1);
2620 if (i > 0x800) {
2621 if (i < 0x1ffff)
2622 edi = (i >> 1);
2623 else
2624 edi = 0x1ffff;
2625 } else {
2626 edi = 0x800;
2627 }
2628 /* this_04 and this_08 are the CASp4Src's (samplerate converters) */
2629 vortex_src_setupchannel(vortex, this_04, edi, 0, 1,
2630 this_0c, 1, 0, edi, 1);
2631 vortex_src_setupchannel(vortex, this_08, edi, 0, 1,
2632 this_0c, 1, 0, edi, 1);
2633 }
2634
2635 i = spdif_sr;
2636 spdif_sr |= 0x8c;
2637 switch (i) {
2638 case 32000:
2639 this_38 &= 0xFFFFFFFE;
2640 this_38 &= 0xFFFFFFFD;
2641 this_38 &= 0xF3FFFFFF;
2642 this_38 |= 0x03000000; /* set 32khz samplerate */
2643 this_38 &= 0xFFFFFF3F;
2644 spdif_sr &= 0xFFFFFFFD;
2645 spdif_sr |= 1;
2646 break;
2647 case 44100:
2648 this_38 &= 0xFFFFFFFE;
2649 this_38 &= 0xFFFFFFFD;
2650 this_38 &= 0xF0FFFFFF;
2651 this_38 |= 0x03000000;
2652 this_38 &= 0xFFFFFF3F;
2653 spdif_sr &= 0xFFFFFFFC;
2654 break;
2655 case 48000:
2656 if (spdif_mode == 1) {
2657 this_38 &= 0xFFFFFFFE;
2658 this_38 &= 0xFFFFFFFD;
2659 this_38 &= 0xF2FFFFFF;
2660 this_38 |= 0x02000000; /* set 48khz samplerate */
2661 this_38 &= 0xFFFFFF3F;
2662 } else {
2663 /* J. Gordon Wolfe: I think this stuff is for AC3 */
2664 this_38 |= 0x00000003;
2665 this_38 &= 0xFFFFFFBF;
2666 this_38 |= 0x80;
2667 }
2668 spdif_sr |= 2;
2669 spdif_sr &= 0xFFFFFFFE;
2670 break;
2671
2672 }
2673 /* looks like the next 2 lines transfer a 16-bit value into 2 8-bit
2674 registers. seems to be for the standard IEC/SPDIF initialization
2675 stuff */
2676 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG0, this_38 & 0xffff);
2677 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1, this_38 >> 0x10);
2678 hwwrite(vortex->mmio, VORTEX_SPDIF_SMPRATE, spdif_sr);
2679}
2680
2681/* Initialization */
2682
2683static int vortex_core_init(vortex_t *vortex)
2684{
2685
2686 dev_info(vortex->card->dev, "init started\n");
2687 /* Hardware Init. */
2688 hwwrite(vortex->mmio, VORTEX_CTRL, 0xffffffff);
2689 msleep(5);
2690 hwwrite(vortex->mmio, VORTEX_CTRL,
2691 hwread(vortex->mmio, VORTEX_CTRL) & 0xffdfffff);
2692 msleep(5);
2693 /* Reset IRQ flags */
2694 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffffffff);
2695 hwread(vortex->mmio, VORTEX_IRQ_STAT);
2696
2697 vortex_codec_init(vortex);
2698
2699#ifdef CHIP_AU8830
2700 hwwrite(vortex->mmio, VORTEX_CTRL,
2701 hwread(vortex->mmio, VORTEX_CTRL) | 0x1000000);
2702#endif
2703
2704 /* Init audio engine. */
2705 vortex_adbdma_init(vortex);
2706 hwwrite(vortex->mmio, VORTEX_ENGINE_CTRL, 0x0); //, 0xc83c7e58, 0xc5f93e58
2707 vortex_adb_init(vortex);
2708 /* Init processing blocks. */
2709 vortex_fifo_init(vortex);
2710 vortex_mixer_init(vortex);
2711 vortex_srcblock_init(vortex);
2712#ifndef CHIP_AU8820
2713 vortex_eq_init(vortex);
2714 vortex_spdif_init(vortex, 48000, 1);
2715 vortex_Vort3D_enable(vortex);
2716#endif
2717#ifndef CHIP_AU8810
2718 vortex_wt_init(vortex);
2719#endif
2720 // Moved to au88x0.c
2721 //vortex_connect_default(vortex, 1);
2722
2723 vortex_settimer(vortex, 0x90);
2724 // Enable Interrupts.
2725 // vortex_enable_int() must be first !!
2726 // hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0);
2727 // vortex_enable_int(vortex);
2728 //vortex_enable_timer_int(vortex);
2729 //vortex_disable_timer_int(vortex);
2730
2731 dev_info(vortex->card->dev, "init.... done.\n");
2732 spin_lock_init(&vortex->lock);
2733
2734 return 0;
2735}
2736
2737static int vortex_core_shutdown(vortex_t * vortex)
2738{
2739
2740 dev_info(vortex->card->dev, "shutdown started\n");
2741#ifndef CHIP_AU8820
2742 vortex_eq_free(vortex);
2743 vortex_Vort3D_disable(vortex);
2744#endif
2745 //vortex_disable_timer_int(vortex);
2746 vortex_disable_int(vortex);
2747 vortex_connect_default(vortex, 0);
2748 /* Reset all DMA fifos. */
2749 vortex_fifo_init(vortex);
2750 /* Erase all audio routes. */
2751 vortex_adb_init(vortex);
2752
2753 /* Disable MPU401 */
2754 //hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, hwread(vortex->mmio, VORTEX_IRQ_CTRL) & ~IRQ_MIDI);
2755 //hwwrite(vortex->mmio, VORTEX_CTRL, hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_EN);
2756
2757 hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0);
2758 hwwrite(vortex->mmio, VORTEX_CTRL, 0);
2759 msleep(5);
2760 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffff);
2761
2762 dev_info(vortex->card->dev, "shutdown.... done.\n");
2763 return 0;
2764}
2765
2766/* Alsa support. */
2767
2768static int vortex_alsafmt_aspfmt(snd_pcm_format_t alsafmt, vortex_t *v)
2769{
2770 int fmt;
2771
2772 switch (alsafmt) {
2773 case SNDRV_PCM_FORMAT_U8:
2774 fmt = 0x1;
2775 break;
2776 case SNDRV_PCM_FORMAT_MU_LAW:
2777 fmt = 0x2;
2778 break;
2779 case SNDRV_PCM_FORMAT_A_LAW:
2780 fmt = 0x3;
2781 break;
2782 case SNDRV_PCM_FORMAT_SPECIAL:
2783 fmt = 0x4; /* guess. */
2784 break;
2785 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
2786 fmt = 0x5; /* guess. */
2787 break;
2788 case SNDRV_PCM_FORMAT_S16_LE:
2789 fmt = 0x8;
2790 break;
2791 case SNDRV_PCM_FORMAT_S16_BE:
2792 fmt = 0x9; /* check this... */
2793 break;
2794 default:
2795 fmt = 0x8;
2796 dev_err(v->card->dev,
2797 "format unsupported %d\n", alsafmt);
2798 break;
2799 }
2800 return fmt;
2801}
2802
2803/* Some not yet useful translations. */
2804#if 0
2805typedef enum {
2806 ASPFMTLINEAR16 = 0, /* 0x8 */
2807 ASPFMTLINEAR8, /* 0x1 */
2808 ASPFMTULAW, /* 0x2 */
2809 ASPFMTALAW, /* 0x3 */
2810 ASPFMTSPORT, /* ? */
2811 ASPFMTSPDIF, /* ? */
2812} ASPENCODING;
2813
2814static int
2815vortex_translateformat(vortex_t * vortex, char bits, char nch, int encod)
2816{
2817 int a, this_194;
2818
2819 if ((bits != 8) && (bits != 16))
2820 return -1;
2821
2822 switch (encod) {
2823 case 0:
2824 if (bits == 0x10)
2825 a = 8; // 16 bit
2826 break;
2827 case 1:
2828 if (bits == 8)
2829 a = 1; // 8 bit
2830 break;
2831 case 2:
2832 a = 2; // U_LAW
2833 break;
2834 case 3:
2835 a = 3; // A_LAW
2836 break;
2837 }
2838 switch (nch) {
2839 case 1:
2840 this_194 = 0;
2841 break;
2842 case 2:
2843 this_194 = 1;
2844 break;
2845 case 4:
2846 this_194 = 1;
2847 break;
2848 case 6:
2849 this_194 = 1;
2850 break;
2851 }
2852 return (a);
2853}
2854
2855static void vortex_cdmacore_setformat(vortex_t * vortex, int bits, int nch)
2856{
2857 short int d, this_148;
2858
2859 d = ((bits >> 3) * nch);
2860 this_148 = 0xbb80 / d;
2861}
2862#endif
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU Library General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 */
16
17/*
18 Vortex core low level functions.
19
20 Author: Manuel Jander (mjander@users.sourceforge.cl)
21 These functions are mainly the result of translations made
22 from the original disassembly of the au88x0 binary drivers,
23 written by Aureal before they went down.
24 Many thanks to the Jeff Muizelaar, Kester Maddock, and whoever
25 contributed to the OpenVortex project.
26 The author of this file, put the few available pieces together
27 and translated the rest of the riddle (Mix, Src and connection stuff).
28 Some things are still to be discovered, and their meanings are unclear.
29
30 Some of these functions aren't intended to be really used, rather
31 to help to understand how does the AU88X0 chips work. Keep them in, because
32 they could be used somewhere in the future.
33
34 This code hasn't been tested or proof read thoroughly. If you wanna help,
35 take a look at the AU88X0 assembly and check if this matches.
36 Functions tested ok so far are (they show the desired effect
37 at least):
38 vortex_routes(); (1 bug fixed).
39 vortex_adb_addroute();
40 vortex_adb_addroutes();
41 vortex_connect_codecplay();
42 vortex_src_flushbuffers();
43 vortex_adbdma_setmode(); note: still some unknown arguments!
44 vortex_adbdma_startfifo();
45 vortex_adbdma_stopfifo();
46 vortex_fifo_setadbctrl(); note: still some unknown arguments!
47 vortex_mix_setinputvolumebyte();
48 vortex_mix_enableinput();
49 vortex_mixer_addWTD(); (fixed)
50 vortex_connection_adbdma_src_src();
51 vortex_connection_adbdma_src();
52 vortex_src_change_convratio();
53 vortex_src_addWTD(); (fixed)
54
55 History:
56
57 01-03-2003 First revision.
58 01-21-2003 Some bug fixes.
59 17-02-2003 many bugfixes after a big versioning mess.
60 18-02-2003 JAAAAAHHHUUUUUU!!!! The mixer works !! I'm just so happy !
61 (2 hours later...) I cant believe it! Im really lucky today.
62 Now the SRC is working too! Yeah! XMMS works !
63 20-02-2003 First steps into the ALSA world.
64 28-02-2003 As my birthday present, i discovered how the DMA buffer pages really
65 work :-). It was all wrong.
66 12-03-2003 ALSA driver starts working (2 channels).
67 16-03-2003 More srcblock_setupchannel discoveries.
68 12-04-2003 AU8830 playback support. Recording in the works.
69 17-04-2003 vortex_route() and vortex_routes() bug fixes. AU8830 recording
70 works now, but chipn' dale effect is still there.
71 16-05-2003 SrcSetupChannel cleanup. Moved the Src setup stuff entirely
72 into au88x0_pcm.c .
73 06-06-2003 Buffer shifter bugfix. Mixer volume fix.
74 07-12-2003 A3D routing finally fixed. Believed to be OK.
75 25-03-2004 Many thanks to Claudia, for such valuable bug reports.
76
77*/
78
79#include "au88x0.h"
80#include "au88x0_a3d.h"
81#include <linux/delay.h>
82
83/* MIXER (CAsp4Mix.s and CAsp4Mixer.s) */
84
85// FIXME: get rid of this.
86static int mchannels[NR_MIXIN];
87static int rampchs[NR_MIXIN];
88
89static void vortex_mixer_en_sr(vortex_t * vortex, int channel)
90{
91 hwwrite(vortex->mmio, VORTEX_MIXER_SR,
92 hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel));
93}
94static void vortex_mixer_dis_sr(vortex_t * vortex, int channel)
95{
96 hwwrite(vortex->mmio, VORTEX_MIXER_SR,
97 hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel));
98}
99
100#if 0
101static void
102vortex_mix_muteinputgain(vortex_t * vortex, unsigned char mix,
103 unsigned char channel)
104{
105 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel),
106 0x80);
107 hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel),
108 0x80);
109}
110
111static int vortex_mix_getvolume(vortex_t * vortex, unsigned char mix)
112{
113 int a;
114 a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
115 //FP2LinearFrac(a);
116 return (a);
117}
118
119static int
120vortex_mix_getinputvolume(vortex_t * vortex, unsigned char mix,
121 int channel, int *vol)
122{
123 int a;
124 if (!(mchannels[mix] & (1 << channel)))
125 return 0;
126 a = hwread(vortex->mmio,
127 VORTEX_MIX_INVOL_A + (((mix << 5) + channel) << 2));
128 /*
129 if (rampchs[mix] == 0)
130 a = FP2LinearFrac(a);
131 else
132 a = FP2LinearFracWT(a);
133 */
134 *vol = a;
135 return (0);
136}
137
138static unsigned int vortex_mix_boost6db(unsigned char vol)
139{
140 return (vol + 8); /* WOW! what a complex function! */
141}
142
143static void vortex_mix_rampvolume(vortex_t * vortex, int mix)
144{
145 int ch;
146 char a;
147 // This function is intended for ramping down only (see vortex_disableinput()).
148 for (ch = 0; ch < 0x20; ch++) {
149 if (((1 << ch) & rampchs[mix]) == 0)
150 continue;
151 a = hwread(vortex->mmio,
152 VORTEX_MIX_INVOL_B + (((mix << 5) + ch) << 2));
153 if (a > -126) {
154 a -= 2;
155 hwwrite(vortex->mmio,
156 VORTEX_MIX_INVOL_A +
157 (((mix << 5) + ch) << 2), a);
158 hwwrite(vortex->mmio,
159 VORTEX_MIX_INVOL_B +
160 (((mix << 5) + ch) << 2), a);
161 } else
162 vortex_mix_killinput(vortex, mix, ch);
163 }
164}
165
166static int
167vortex_mix_getenablebit(vortex_t * vortex, unsigned char mix, int mixin)
168{
169 int addr, temp;
170 if (mixin >= 0)
171 addr = mixin;
172 else
173 addr = mixin + 3;
174 addr = ((mix << 3) + (addr >> 2)) << 2;
175 temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
176 return ((temp >> (mixin & 3)) & 1);
177}
178#endif
179static void
180vortex_mix_setvolumebyte(vortex_t * vortex, unsigned char mix,
181 unsigned char vol)
182{
183 int temp;
184 hwwrite(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2), vol);
185 if (1) { /*if (this_10) */
186 temp = hwread(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2));
187 if ((temp != 0x80) || (vol == 0x80))
188 return;
189 }
190 hwwrite(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2), vol);
191}
192
193static void
194vortex_mix_setinputvolumebyte(vortex_t * vortex, unsigned char mix,
195 int mixin, unsigned char vol)
196{
197 int temp;
198
199 hwwrite(vortex->mmio,
200 VORTEX_MIX_INVOL_A + (((mix << 5) + mixin) << 2), vol);
201 if (1) { /* this_10, initialized to 1. */
202 temp =
203 hwread(vortex->mmio,
204 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2));
205 if ((temp != 0x80) || (vol == 0x80))
206 return;
207 }
208 hwwrite(vortex->mmio,
209 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), vol);
210}
211
212static void
213vortex_mix_setenablebit(vortex_t * vortex, unsigned char mix, int mixin, int en)
214{
215 int temp, addr;
216
217 if (mixin < 0)
218 addr = (mixin + 3);
219 else
220 addr = mixin;
221 addr = ((mix << 3) + (addr >> 2)) << 2;
222 temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
223 if (en)
224 temp |= (1 << (mixin & 3));
225 else
226 temp &= ~(1 << (mixin & 3));
227 /* Mute input. Astatic void crackling? */
228 hwwrite(vortex->mmio,
229 VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), 0x80);
230 /* Looks like clear buffer. */
231 hwwrite(vortex->mmio, VORTEX_MIX_SMP + (mixin << 2), 0x0);
232 hwwrite(vortex->mmio, VORTEX_MIX_SMP + 4 + (mixin << 2), 0x0);
233 /* Write enable bit. */
234 hwwrite(vortex->mmio, VORTEX_MIX_ENIN + addr, temp);
235}
236
237static void
238vortex_mix_killinput(vortex_t * vortex, unsigned char mix, int mixin)
239{
240 rampchs[mix] &= ~(1 << mixin);
241 vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80);
242 mchannels[mix] &= ~(1 << mixin);
243 vortex_mix_setenablebit(vortex, mix, mixin, 0);
244}
245
246static void
247vortex_mix_enableinput(vortex_t * vortex, unsigned char mix, int mixin)
248{
249 vortex_mix_killinput(vortex, mix, mixin);
250 if ((mchannels[mix] & (1 << mixin)) == 0) {
251 vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80); /*0x80 : mute */
252 mchannels[mix] |= (1 << mixin);
253 }
254 vortex_mix_setenablebit(vortex, mix, mixin, 1);
255}
256
257static void
258vortex_mix_disableinput(vortex_t * vortex, unsigned char mix, int channel,
259 int ramp)
260{
261 if (ramp) {
262 rampchs[mix] |= (1 << channel);
263 // Register callback.
264 //vortex_mix_startrampvolume(vortex);
265 vortex_mix_killinput(vortex, mix, channel);
266 } else
267 vortex_mix_killinput(vortex, mix, channel);
268}
269
270static int
271vortex_mixer_addWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
272{
273 int temp, lifeboat = 0, prev;
274
275 temp = hwread(vortex->mmio, VORTEX_MIXER_SR);
276 if ((temp & (1 << ch)) == 0) {
277 hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), mix);
278 vortex_mixer_en_sr(vortex, ch);
279 return 1;
280 }
281 prev = VORTEX_MIXER_CHNBASE + (ch << 2);
282 temp = hwread(vortex->mmio, prev);
283 while (temp & 0x10) {
284 prev = VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2);
285 temp = hwread(vortex->mmio, prev);
286 //printk(KERN_INFO "vortex: mixAddWTD: while addr=%x, val=%x\n", prev, temp);
287 if ((++lifeboat) > 0xf) {
288 dev_err(vortex->card->dev,
289 "vortex_mixer_addWTD: lifeboat overflow\n");
290 return 0;
291 }
292 }
293 hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2), mix);
294 hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
295 return 1;
296}
297
298static int
299vortex_mixer_delWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
300{
301 int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
302 //int esp1f=edi(while)=src, esp10=ch;
303
304 eax = hwread(vortex->mmio, VORTEX_MIXER_SR);
305 if (((1 << ch) & eax) == 0) {
306 dev_err(vortex->card->dev, "mix ALARM %x\n", eax);
307 return 0;
308 }
309 ebp = VORTEX_MIXER_CHNBASE + (ch << 2);
310 esp18 = hwread(vortex->mmio, ebp);
311 if (esp18 & 0x10) {
312 ebx = (esp18 & 0xf);
313 if (mix == ebx) {
314 ebx = VORTEX_MIXER_RTBASE + (mix << 2);
315 edx = hwread(vortex->mmio, ebx);
316 //7b60
317 hwwrite(vortex->mmio, ebp, edx);
318 hwwrite(vortex->mmio, ebx, 0);
319 } else {
320 //7ad3
321 edx =
322 hwread(vortex->mmio,
323 VORTEX_MIXER_RTBASE + (ebx << 2));
324 //printk(KERN_INFO "vortex: mixdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src);
325 while ((edx & 0xf) != mix) {
326 if ((esi) > 0xf) {
327 dev_err(vortex->card->dev,
328 "mixdelWTD: error lifeboat overflow\n");
329 return 0;
330 }
331 esp14 = ebx;
332 ebx = edx & 0xf;
333 ebp = ebx << 2;
334 edx =
335 hwread(vortex->mmio,
336 VORTEX_MIXER_RTBASE + ebp);
337 //printk(KERN_INFO "vortex: mixdelWTD: while addr=%x, val=%x\n", ebp, edx);
338 esi++;
339 }
340 //7b30
341 ebp = ebx << 2;
342 if (edx & 0x10) { /* Delete entry in between others */
343 ebx = VORTEX_MIXER_RTBASE + ((edx & 0xf) << 2);
344 edx = hwread(vortex->mmio, ebx);
345 //7b60
346 hwwrite(vortex->mmio,
347 VORTEX_MIXER_RTBASE + ebp, edx);
348 hwwrite(vortex->mmio, ebx, 0);
349 //printk(KERN_INFO "vortex mixdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx);
350 } else { /* Delete last entry */
351 //7b83
352 if (esp14 == -1)
353 hwwrite(vortex->mmio,
354 VORTEX_MIXER_CHNBASE +
355 (ch << 2), esp18 & 0xef);
356 else {
357 ebx = (0xffffffe0 & edx) | (0xf & ebx);
358 hwwrite(vortex->mmio,
359 VORTEX_MIXER_RTBASE +
360 (esp14 << 2), ebx);
361 //printk(KERN_INFO "vortex mixdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx);
362 }
363 hwwrite(vortex->mmio,
364 VORTEX_MIXER_RTBASE + ebp, 0);
365 return 1;
366 }
367 }
368 } else {
369 //printk(KERN_INFO "removed last mix\n");
370 //7be0
371 vortex_mixer_dis_sr(vortex, ch);
372 hwwrite(vortex->mmio, ebp, 0);
373 }
374 return 1;
375}
376
377static void vortex_mixer_init(vortex_t * vortex)
378{
379 u32 addr;
380 int x;
381
382 // FIXME: get rid of this crap.
383 memset(mchannels, 0, NR_MIXOUT * sizeof(int));
384 memset(rampchs, 0, NR_MIXOUT * sizeof(int));
385
386 addr = VORTEX_MIX_SMP + 0x17c;
387 for (x = 0x5f; x >= 0; x--) {
388 hwwrite(vortex->mmio, addr, 0);
389 addr -= 4;
390 }
391 addr = VORTEX_MIX_ENIN + 0x1fc;
392 for (x = 0x7f; x >= 0; x--) {
393 hwwrite(vortex->mmio, addr, 0);
394 addr -= 4;
395 }
396 addr = VORTEX_MIX_SMP + 0x17c;
397 for (x = 0x5f; x >= 0; x--) {
398 hwwrite(vortex->mmio, addr, 0);
399 addr -= 4;
400 }
401 addr = VORTEX_MIX_INVOL_A + 0x7fc;
402 for (x = 0x1ff; x >= 0; x--) {
403 hwwrite(vortex->mmio, addr, 0x80);
404 addr -= 4;
405 }
406 addr = VORTEX_MIX_VOL_A + 0x3c;
407 for (x = 0xf; x >= 0; x--) {
408 hwwrite(vortex->mmio, addr, 0x80);
409 addr -= 4;
410 }
411 addr = VORTEX_MIX_INVOL_B + 0x7fc;
412 for (x = 0x1ff; x >= 0; x--) {
413 hwwrite(vortex->mmio, addr, 0x80);
414 addr -= 4;
415 }
416 addr = VORTEX_MIX_VOL_B + 0x3c;
417 for (x = 0xf; x >= 0; x--) {
418 hwwrite(vortex->mmio, addr, 0x80);
419 addr -= 4;
420 }
421 addr = VORTEX_MIXER_RTBASE + (MIXER_RTBASE_SIZE - 1) * 4;
422 for (x = (MIXER_RTBASE_SIZE - 1); x >= 0; x--) {
423 hwwrite(vortex->mmio, addr, 0x0);
424 addr -= 4;
425 }
426 hwwrite(vortex->mmio, VORTEX_MIXER_SR, 0);
427
428 /* Set clipping ceiling (this may be all wrong). */
429 /*
430 for (x = 0; x < 0x80; x++) {
431 hwwrite(vortex->mmio, VORTEX_MIXER_CLIP + (x << 2), 0x3ffff);
432 }
433 */
434 /*
435 call CAsp4Mix__Initialize_CAsp4HwIO____CAsp4Mixer____
436 Register ISR callback for volume smooth fade out.
437 Maybe this avoids clicks when press "stop" ?
438 */
439}
440
441/* SRC (CAsp4Src.s and CAsp4SrcBlock) */
442
443static void vortex_src_en_sr(vortex_t * vortex, int channel)
444{
445 hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
446 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) | (0x1 << channel));
447}
448
449static void vortex_src_dis_sr(vortex_t * vortex, int channel)
450{
451 hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
452 hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) & ~(0x1 << channel));
453}
454
455static void vortex_src_flushbuffers(vortex_t * vortex, unsigned char src)
456{
457 int i;
458
459 for (i = 0x1f; i >= 0; i--)
460 hwwrite(vortex->mmio,
461 VORTEX_SRC_DATA0 + (src << 7) + (i << 2), 0);
462 hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3), 0);
463 hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3) + 4, 0);
464}
465
466static void vortex_src_cleardrift(vortex_t * vortex, unsigned char src)
467{
468 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
469 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT1 + (src << 2), 0);
470 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
471}
472
473static void
474vortex_src_set_throttlesource(vortex_t * vortex, unsigned char src, int en)
475{
476 int temp;
477
478 temp = hwread(vortex->mmio, VORTEX_SRC_SOURCE);
479 if (en)
480 temp |= 1 << src;
481 else
482 temp &= ~(1 << src);
483 hwwrite(vortex->mmio, VORTEX_SRC_SOURCE, temp);
484}
485
486static int
487vortex_src_persist_convratio(vortex_t * vortex, unsigned char src, int ratio)
488{
489 int temp, lifeboat = 0;
490
491 do {
492 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), ratio);
493 temp = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
494 if ((++lifeboat) > 0x9) {
495 dev_err(vortex->card->dev, "Src cvr fail\n");
496 break;
497 }
498 }
499 while (temp != ratio);
500 return temp;
501}
502
503#if 0
504static void vortex_src_slowlock(vortex_t * vortex, unsigned char src)
505{
506 int temp;
507
508 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
509 hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
510 temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
511 if (temp & 0x200)
512 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
513 temp & ~0x200L);
514}
515
516static void
517vortex_src_change_convratio(vortex_t * vortex, unsigned char src, int ratio)
518{
519 int temp, a;
520
521 if ((ratio & 0x10000) && (ratio != 0x10000)) {
522 if (ratio & 0x3fff)
523 a = (0x11 - ((ratio >> 0xe) & 0x3)) - 1;
524 else
525 a = (0x11 - ((ratio >> 0xe) & 0x3)) - 2;
526 } else
527 a = 0xc;
528 temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
529 if (((temp >> 4) & 0xf) != a)
530 hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
531 (temp & 0xf) | ((a & 0xf) << 4));
532
533 vortex_src_persist_convratio(vortex, src, ratio);
534}
535
536static int
537vortex_src_checkratio(vortex_t * vortex, unsigned char src,
538 unsigned int desired_ratio)
539{
540 int hw_ratio, lifeboat = 0;
541
542 hw_ratio = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
543
544 while (hw_ratio != desired_ratio) {
545 hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), desired_ratio);
546
547 if ((lifeboat++) > 15) {
548 pr_err( "Vortex: could not set src-%d from %d to %d\n",
549 src, hw_ratio, desired_ratio);
550 break;
551 }
552 }
553
554 return hw_ratio;
555}
556
557#endif
558/*
559 Objective: Set samplerate for given SRC module.
560 Arguments:
561 card: pointer to vortex_t strcut.
562 src: Integer index of the SRC module.
563 cr: Current sample rate conversion factor.
564 b: unknown 16 bit value.
565 sweep: Enable Samplerate fade from cr toward tr flag.
566 dirplay: 1: playback, 0: recording.
567 sl: Slow Lock flag.
568 tr: Target samplerate conversion.
569 thsource: Throttle source flag (no idea what that means).
570*/
571static void vortex_src_setupchannel(vortex_t * card, unsigned char src,
572 unsigned int cr, unsigned int b, int sweep, int d,
573 int dirplay, int sl, unsigned int tr, int thsource)
574{
575 // noplayback: d=2,4,7,0xa,0xb when using first 2 src's.
576 // c: enables pitch sweep.
577 // looks like g is c related. Maybe g is a sweep parameter ?
578 // g = cvr
579 // dirplay: 0 = recording, 1 = playback
580 // d = src hw index.
581
582 int esi, ebp = 0, esp10;
583
584 vortex_src_flushbuffers(card, src);
585
586 if (sweep) {
587 if ((tr & 0x10000) && (tr != 0x10000)) {
588 tr = 0;
589 esi = 0x7;
590 } else {
591 if ((((short)tr) < 0) && (tr != 0x8000)) {
592 tr = 0;
593 esi = 0x8;
594 } else {
595 tr = 1;
596 esi = 0xc;
597 }
598 }
599 } else {
600 if ((cr & 0x10000) && (cr != 0x10000)) {
601 tr = 0; /*ebx = 0 */
602 esi = 0x11 - ((cr >> 0xe) & 7);
603 if (cr & 0x3fff)
604 esi -= 1;
605 else
606 esi -= 2;
607 } else {
608 tr = 1;
609 esi = 0xc;
610 }
611 }
612 vortex_src_cleardrift(card, src);
613 vortex_src_set_throttlesource(card, src, thsource);
614
615 if ((dirplay == 0) && (sweep == 0)) {
616 if (tr)
617 esp10 = 0xf;
618 else
619 esp10 = 0xc;
620 ebp = 0;
621 } else {
622 if (tr)
623 ebp = 0xf;
624 else
625 ebp = 0xc;
626 esp10 = 0;
627 }
628 hwwrite(card->mmio, VORTEX_SRC_U0 + (src << 2),
629 (sl << 0x9) | (sweep << 0x8) | ((esi & 0xf) << 4) | d);
630 /* 0xc0 esi=0xc c=f=0 d=0 */
631 vortex_src_persist_convratio(card, src, cr);
632 hwwrite(card->mmio, VORTEX_SRC_U1 + (src << 2), b & 0xffff);
633 /* 0 b=0 */
634 hwwrite(card->mmio, VORTEX_SRC_U2 + (src << 2),
635 (tr << 0x11) | (dirplay << 0x10) | (ebp << 0x8) | esp10);
636 /* 0x30f00 e=g=1 esp10=0 ebp=f */
637 //printk(KERN_INFO "vortex: SRC %d, d=0x%x, esi=0x%x, esp10=0x%x, ebp=0x%x\n", src, d, esi, esp10, ebp);
638}
639
640static void vortex_srcblock_init(vortex_t * vortex)
641{
642 u32 addr;
643 int x;
644 hwwrite(vortex->mmio, VORTEX_SRC_SOURCESIZE, 0x1ff);
645 /*
646 for (x=0; x<0x10; x++) {
647 vortex_src_init(&vortex_src[x], x);
648 }
649 */
650 //addr = 0xcc3c;
651 //addr = 0x26c3c;
652 addr = VORTEX_SRC_RTBASE + 0x3c;
653 for (x = 0xf; x >= 0; x--) {
654 hwwrite(vortex->mmio, addr, 0);
655 addr -= 4;
656 }
657 //addr = 0xcc94;
658 //addr = 0x26c94;
659 addr = VORTEX_SRC_CHNBASE + 0x54;
660 for (x = 0x15; x >= 0; x--) {
661 hwwrite(vortex->mmio, addr, 0);
662 addr -= 4;
663 }
664}
665
666static int
667vortex_src_addWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
668{
669 int temp, lifeboat = 0, prev;
670 // esp13 = src
671
672 temp = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
673 if ((temp & (1 << ch)) == 0) {
674 hwwrite(vortex->mmio, VORTEX_SRC_CHNBASE + (ch << 2), src);
675 vortex_src_en_sr(vortex, ch);
676 return 1;
677 }
678 prev = VORTEX_SRC_CHNBASE + (ch << 2); /*ebp */
679 temp = hwread(vortex->mmio, prev);
680 //while (temp & NR_SRC) {
681 while (temp & 0x10) {
682 prev = VORTEX_SRC_RTBASE + ((temp & 0xf) << 2); /*esp12 */
683 //prev = VORTEX_SRC_RTBASE + ((temp & (NR_SRC-1)) << 2); /*esp12*/
684 temp = hwread(vortex->mmio, prev);
685 //printk(KERN_INFO "vortex: srcAddWTD: while addr=%x, val=%x\n", prev, temp);
686 if ((++lifeboat) > 0xf) {
687 dev_err(vortex->card->dev,
688 "vortex_src_addWTD: lifeboat overflow\n");
689 return 0;
690 }
691 }
692 hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ((temp & 0xf) << 2), src);
693 //hwwrite(vortex->mmio, prev, (temp & (NR_SRC-1)) | NR_SRC);
694 hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
695 return 1;
696}
697
698static int
699vortex_src_delWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
700{
701 int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
702 //int esp1f=edi(while)=src, esp10=ch;
703
704 eax = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
705 if (((1 << ch) & eax) == 0) {
706 dev_err(vortex->card->dev, "src alarm\n");
707 return 0;
708 }
709 ebp = VORTEX_SRC_CHNBASE + (ch << 2);
710 esp18 = hwread(vortex->mmio, ebp);
711 if (esp18 & 0x10) {
712 ebx = (esp18 & 0xf);
713 if (src == ebx) {
714 ebx = VORTEX_SRC_RTBASE + (src << 2);
715 edx = hwread(vortex->mmio, ebx);
716 //7b60
717 hwwrite(vortex->mmio, ebp, edx);
718 hwwrite(vortex->mmio, ebx, 0);
719 } else {
720 //7ad3
721 edx =
722 hwread(vortex->mmio,
723 VORTEX_SRC_RTBASE + (ebx << 2));
724 //printk(KERN_INFO "vortex: srcdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src);
725 while ((edx & 0xf) != src) {
726 if ((esi) > 0xf) {
727 dev_warn(vortex->card->dev,
728 "srcdelWTD: error, lifeboat overflow\n");
729 return 0;
730 }
731 esp14 = ebx;
732 ebx = edx & 0xf;
733 ebp = ebx << 2;
734 edx =
735 hwread(vortex->mmio,
736 VORTEX_SRC_RTBASE + ebp);
737 //printk(KERN_INFO "vortex: srcdelWTD: while addr=%x, val=%x\n", ebp, edx);
738 esi++;
739 }
740 //7b30
741 ebp = ebx << 2;
742 if (edx & 0x10) { /* Delete entry in between others */
743 ebx = VORTEX_SRC_RTBASE + ((edx & 0xf) << 2);
744 edx = hwread(vortex->mmio, ebx);
745 //7b60
746 hwwrite(vortex->mmio,
747 VORTEX_SRC_RTBASE + ebp, edx);
748 hwwrite(vortex->mmio, ebx, 0);
749 //printk(KERN_INFO "vortex srcdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx);
750 } else { /* Delete last entry */
751 //7b83
752 if (esp14 == -1)
753 hwwrite(vortex->mmio,
754 VORTEX_SRC_CHNBASE +
755 (ch << 2), esp18 & 0xef);
756 else {
757 ebx = (0xffffffe0 & edx) | (0xf & ebx);
758 hwwrite(vortex->mmio,
759 VORTEX_SRC_RTBASE +
760 (esp14 << 2), ebx);
761 //printk(KERN_INFO"vortex srcdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx);
762 }
763 hwwrite(vortex->mmio,
764 VORTEX_SRC_RTBASE + ebp, 0);
765 return 1;
766 }
767 }
768 } else {
769 //7be0
770 vortex_src_dis_sr(vortex, ch);
771 hwwrite(vortex->mmio, ebp, 0);
772 }
773 return 1;
774}
775
776 /*FIFO*/
777
778static void
779vortex_fifo_clearadbdata(vortex_t * vortex, int fifo, int x)
780{
781 for (x--; x >= 0; x--)
782 hwwrite(vortex->mmio,
783 VORTEX_FIFO_ADBDATA +
784 (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
785}
786
787#if 0
788static void vortex_fifo_adbinitialize(vortex_t * vortex, int fifo, int j)
789{
790 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
791#ifdef CHIP_AU8820
792 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
793 (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
794#else
795 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
796 (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
797#endif
798}
799#endif
800static void vortex_fifo_setadbvalid(vortex_t * vortex, int fifo, int en)
801{
802 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
803 (hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)) &
804 0xffffffef) | ((1 & en) << 4) | FIFO_U1);
805}
806
807static void
808vortex_fifo_setadbctrl(vortex_t * vortex, int fifo, int stereo, int priority,
809 int empty, int valid, int f)
810{
811 int temp, lifeboat = 0;
812 //int this_8[NR_ADB] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; /* position */
813 int this_4 = 0x2;
814 /* f seems priority related.
815 * CAsp4AdbDma::SetPriority is the only place that calls SetAdbCtrl with f set to 1
816 * every where else it is set to 0. It seems, however, that CAsp4AdbDma::SetPriority
817 * is never called, thus the f related bits remain a mystery for now.
818 */
819 do {
820 temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
821 if (lifeboat++ > 0xbb8) {
822 dev_err(vortex->card->dev,
823 "vortex_fifo_setadbctrl fail\n");
824 break;
825 }
826 }
827 while (temp & FIFO_RDONLY);
828
829 // AU8830 semes to take some special care about fifo content (data).
830 // But i'm just to lazy to translate that :)
831 if (valid) {
832 if ((temp & FIFO_VALID) == 0) {
833 //this_8[fifo] = 0;
834 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); // this_4
835#ifdef CHIP_AU8820
836 temp = (this_4 & 0x1f) << 0xb;
837#else
838 temp = (this_4 & 0x3f) << 0xc;
839#endif
840 temp = (temp & 0xfffffffd) | ((stereo & 1) << 1);
841 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
842 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
843 temp |= FIFO_U1;
844 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
845#ifdef CHIP_AU8820
846 temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
847#endif
848#ifdef CHIP_AU8830
849 temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
850 temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
851#endif
852#ifdef CHIP_AU8810
853 temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
854 temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
855#endif
856 }
857 } else {
858 if (temp & FIFO_VALID) {
859#ifdef CHIP_AU8820
860 temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
861#endif
862#ifdef CHIP_AU8830
863 temp =
864 ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
865#endif
866#ifdef CHIP_AU8810
867 temp =
868 ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
869#endif
870 } else
871 /*if (this_8[fifo]) */
872 vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
873 }
874 hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), temp);
875 hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
876}
877
878#ifndef CHIP_AU8810
879static void vortex_fifo_clearwtdata(vortex_t * vortex, int fifo, int x)
880{
881 if (x < 1)
882 return;
883 for (x--; x >= 0; x--)
884 hwwrite(vortex->mmio,
885 VORTEX_FIFO_WTDATA +
886 (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
887}
888
889static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j)
890{
891 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
892#ifdef CHIP_AU8820
893 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
894 (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
895#else
896 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
897 (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
898#endif
899}
900
901static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en)
902{
903 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
904 (hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)) &
905 0xffffffef) | ((en & 1) << 4) | FIFO_U1);
906}
907
908static void
909vortex_fifo_setwtctrl(vortex_t * vortex, int fifo, int ctrl, int priority,
910 int empty, int valid, int f)
911{
912 int temp = 0, lifeboat = 0;
913 int this_4 = 2;
914
915 do {
916 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
917 if (lifeboat++ > 0xbb8) {
918 dev_err(vortex->card->dev,
919 "vortex_fifo_setwtctrl fail\n");
920 break;
921 }
922 }
923 while (temp & FIFO_RDONLY);
924
925 if (valid) {
926 if ((temp & FIFO_VALID) == 0) {
927 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); // this_4
928#ifdef CHIP_AU8820
929 temp = (this_4 & 0x1f) << 0xb;
930#else
931 temp = (this_4 & 0x3f) << 0xc;
932#endif
933 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
934 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
935 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
936 temp |= FIFO_U1;
937 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
938#ifdef CHIP_AU8820
939 temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
940#endif
941#ifdef CHIP_AU8830
942 temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
943 temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
944#endif
945#ifdef CHIP_AU8810
946 temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
947 temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
948#endif
949 }
950 } else {
951 if (temp & FIFO_VALID) {
952#ifdef CHIP_AU8820
953 temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
954#endif
955#ifdef CHIP_AU8830
956 temp =
957 ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
958#endif
959#ifdef CHIP_AU8810
960 temp =
961 ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
962#endif
963 } else
964 /*if (this_8[fifo]) */
965 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
966 }
967 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
968 hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
969
970/*
971 do {
972 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
973 if (lifeboat++ > 0xbb8) {
974 pr_err( "Vortex: vortex_fifo_setwtctrl fail (hanging)\n");
975 break;
976 }
977 } while ((temp & FIFO_RDONLY)&&(temp & FIFO_VALID)&&(temp != 0xFFFFFFFF));
978
979
980 if (valid) {
981 if (temp & FIFO_VALID) {
982 temp = 0x40000;
983 //temp |= 0x08000000;
984 //temp |= 0x10000000;
985 //temp |= 0x04000000;
986 //temp |= 0x00400000;
987 temp |= 0x1c400000;
988 temp &= 0xFFFFFFF3;
989 temp &= 0xFFFFFFEF;
990 temp |= (valid & 1) << 4;
991 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
992 return;
993 } else {
994 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
995 return;
996 }
997 } else {
998 temp &= 0xffffffef;
999 temp |= 0x08000000;
1000 temp |= 0x10000000;
1001 temp |= 0x04000000;
1002 temp |= 0x00400000;
1003 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1004 temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
1005 //((temp >> 6) & 0x3f)
1006
1007 priority = 0;
1008 if (((temp & 0x0fc0) ^ ((temp >> 6) & 0x0fc0)) & 0FFFFFFC0)
1009 vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
1010 valid = 0xfb;
1011 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
1012 temp = (temp & 0xfffdffff) | ((f & 1) << 0x11);
1013 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
1014 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
1015 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
1016 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1017 }
1018
1019 */
1020
1021 /*
1022 temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
1023 temp = (temp & 0xfffdffff) | ((f & 1) << 0x11);
1024 temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
1025 temp = (temp & 0xffffffef) | ((valid & 1) << 4);
1026 temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
1027 #ifdef FIFO_BITS
1028 temp = temp | FIFO_BITS | 40000;
1029 #endif
1030 // 0x1c440010, 0x1c400000
1031 hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
1032 */
1033}
1034
1035#endif
1036static void vortex_fifo_init(vortex_t * vortex)
1037{
1038 int x;
1039 u32 addr;
1040
1041 /* ADB DMA channels fifos. */
1042 addr = VORTEX_FIFO_ADBCTRL + ((NR_ADB - 1) * 4);
1043 for (x = NR_ADB - 1; x >= 0; x--) {
1044 hwwrite(vortex->mmio, addr, (FIFO_U0 | FIFO_U1));
1045 if (hwread(vortex->mmio, addr) != (FIFO_U0 | FIFO_U1))
1046 dev_err(vortex->card->dev, "bad adb fifo reset!\n");
1047 vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE);
1048 addr -= 4;
1049 }
1050
1051#ifndef CHIP_AU8810
1052 /* WT DMA channels fifos. */
1053 addr = VORTEX_FIFO_WTCTRL + ((NR_WT - 1) * 4);
1054 for (x = NR_WT - 1; x >= 0; x--) {
1055 hwwrite(vortex->mmio, addr, FIFO_U0);
1056 if (hwread(vortex->mmio, addr) != FIFO_U0)
1057 dev_err(vortex->card->dev,
1058 "bad wt fifo reset (0x%08x, 0x%08x)!\n",
1059 addr, hwread(vortex->mmio, addr));
1060 vortex_fifo_clearwtdata(vortex, x, FIFO_SIZE);
1061 addr -= 4;
1062 }
1063#endif
1064 /* trigger... */
1065#ifdef CHIP_AU8820
1066 hwwrite(vortex->mmio, 0xf8c0, 0xd03); //0x0843 0xd6b
1067#else
1068#ifdef CHIP_AU8830
1069 hwwrite(vortex->mmio, 0x17000, 0x61); /* wt a */
1070 hwwrite(vortex->mmio, 0x17004, 0x61); /* wt b */
1071#endif
1072 hwwrite(vortex->mmio, 0x17008, 0x61); /* adb */
1073#endif
1074}
1075
1076/* ADBDMA */
1077
1078static void vortex_adbdma_init(vortex_t * vortex)
1079{
1080}
1081
1082static void vortex_adbdma_setfirstbuffer(vortex_t * vortex, int adbdma)
1083{
1084 stream_t *dma = &vortex->dma_adb[adbdma];
1085
1086 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1087 dma->dma_ctrl);
1088}
1089
1090static void vortex_adbdma_setstartbuffer(vortex_t * vortex, int adbdma, int sb)
1091{
1092 stream_t *dma = &vortex->dma_adb[adbdma];
1093 //hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2), sb << (((NR_ADB-1)-((adbdma&0xf)*2))));
1094 hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2),
1095 sb << ((0xf - (adbdma & 0xf)) * 2));
1096 dma->period_real = dma->period_virt = sb;
1097}
1098
1099static void
1100vortex_adbdma_setbuffers(vortex_t * vortex, int adbdma,
1101 int psize, int count)
1102{
1103 stream_t *dma = &vortex->dma_adb[adbdma];
1104
1105 dma->period_bytes = psize;
1106 dma->nr_periods = count;
1107
1108 dma->cfg0 = 0;
1109 dma->cfg1 = 0;
1110 switch (count) {
1111 /* Four or more pages */
1112 default:
1113 case 4:
1114 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize - 1);
1115 hwwrite(vortex->mmio,
1116 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0xc,
1117 snd_pcm_sgbuf_get_addr(dma->substream, psize * 3));
1118 /* 3 pages */
1119 case 3:
1120 dma->cfg0 |= 0x12000000;
1121 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
1122 hwwrite(vortex->mmio,
1123 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x8,
1124 snd_pcm_sgbuf_get_addr(dma->substream, psize * 2));
1125 /* 2 pages */
1126 case 2:
1127 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize - 1);
1128 hwwrite(vortex->mmio,
1129 VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x4,
1130 snd_pcm_sgbuf_get_addr(dma->substream, psize));
1131 /* 1 page */
1132 case 1:
1133 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
1134 hwwrite(vortex->mmio,
1135 VORTEX_ADBDMA_BUFBASE + (adbdma << 4),
1136 snd_pcm_sgbuf_get_addr(dma->substream, 0));
1137 break;
1138 }
1139 /*
1140 pr_debug( "vortex: cfg0 = 0x%x\nvortex: cfg1=0x%x\n",
1141 dma->cfg0, dma->cfg1);
1142 */
1143 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + (adbdma << 3), dma->cfg0);
1144 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG1 + (adbdma << 3), dma->cfg1);
1145
1146 vortex_adbdma_setfirstbuffer(vortex, adbdma);
1147 vortex_adbdma_setstartbuffer(vortex, adbdma, 0);
1148}
1149
1150static void
1151vortex_adbdma_setmode(vortex_t * vortex, int adbdma, int ie, int dir,
1152 int fmt, int stereo, u32 offset)
1153{
1154 stream_t *dma = &vortex->dma_adb[adbdma];
1155
1156 dma->dma_unknown = stereo;
1157 dma->dma_ctrl =
1158 ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1159 /* Enable PCMOUT interrupts. */
1160 dma->dma_ctrl =
1161 (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1162
1163 dma->dma_ctrl =
1164 (dma->dma_ctrl & ~DIR_MASK) | ((dir << DIR_SHIFT) & DIR_MASK);
1165 dma->dma_ctrl =
1166 (dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1167
1168 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1169 dma->dma_ctrl);
1170 hwread(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2));
1171}
1172
1173static int vortex_adbdma_bufshift(vortex_t * vortex, int adbdma)
1174{
1175 stream_t *dma = &vortex->dma_adb[adbdma];
1176 int page, p, pp, delta, i;
1177
1178 page =
1179 (hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)) &
1180 ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT;
1181 if (dma->nr_periods >= 4)
1182 delta = (page - dma->period_real) & 3;
1183 else {
1184 delta = (page - dma->period_real);
1185 if (delta < 0)
1186 delta += dma->nr_periods;
1187 }
1188 if (delta == 0)
1189 return 0;
1190
1191 /* refresh hw page table */
1192 if (dma->nr_periods > 4) {
1193 for (i = 0; i < delta; i++) {
1194 /* p: audio buffer page index */
1195 p = dma->period_virt + i + 4;
1196 if (p >= dma->nr_periods)
1197 p -= dma->nr_periods;
1198 /* pp: hardware DMA page index. */
1199 pp = dma->period_real + i;
1200 if (pp >= 4)
1201 pp -= 4;
1202 //hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE+(((adbdma << 2)+pp) << 2), dma->table[p].addr);
1203 hwwrite(vortex->mmio,
1204 VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2),
1205 snd_pcm_sgbuf_get_addr(dma->substream,
1206 dma->period_bytes * p));
1207 /* Force write thru cache. */
1208 hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE +
1209 (((adbdma << 2) + pp) << 2));
1210 }
1211 }
1212 dma->period_virt += delta;
1213 dma->period_real = page;
1214 if (dma->period_virt >= dma->nr_periods)
1215 dma->period_virt -= dma->nr_periods;
1216 if (delta != 1)
1217 dev_info(vortex->card->dev,
1218 "%d virt=%d, real=%d, delta=%d\n",
1219 adbdma, dma->period_virt, dma->period_real, delta);
1220
1221 return delta;
1222}
1223
1224
1225static void vortex_adbdma_resetup(vortex_t *vortex, int adbdma) {
1226 stream_t *dma = &vortex->dma_adb[adbdma];
1227 int p, pp, i;
1228
1229 /* refresh hw page table */
1230 for (i=0 ; i < 4 && i < dma->nr_periods; i++) {
1231 /* p: audio buffer page index */
1232 p = dma->period_virt + i;
1233 if (p >= dma->nr_periods)
1234 p -= dma->nr_periods;
1235 /* pp: hardware DMA page index. */
1236 pp = dma->period_real + i;
1237 if (dma->nr_periods < 4) {
1238 if (pp >= dma->nr_periods)
1239 pp -= dma->nr_periods;
1240 }
1241 else {
1242 if (pp >= 4)
1243 pp -= 4;
1244 }
1245 hwwrite(vortex->mmio,
1246 VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2),
1247 snd_pcm_sgbuf_get_addr(dma->substream,
1248 dma->period_bytes * p));
1249 /* Force write thru cache. */
1250 hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (((adbdma << 2)+pp) << 2));
1251 }
1252}
1253
1254static inline int vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma)
1255{
1256 stream_t *dma = &vortex->dma_adb[adbdma];
1257 int temp, page, delta;
1258
1259 temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2));
1260 page = (temp & ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT;
1261 if (dma->nr_periods >= 4)
1262 delta = (page - dma->period_real) & 3;
1263 else {
1264 delta = (page - dma->period_real);
1265 if (delta < 0)
1266 delta += dma->nr_periods;
1267 }
1268 return (dma->period_virt + delta) * dma->period_bytes
1269 + (temp & (dma->period_bytes - 1));
1270}
1271
1272static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma)
1273{
1274 int this_8 = 0 /*empty */ , this_4 = 0 /*priority */ ;
1275 stream_t *dma = &vortex->dma_adb[adbdma];
1276
1277 switch (dma->fifo_status) {
1278 case FIFO_START:
1279 vortex_fifo_setadbvalid(vortex, adbdma,
1280 dma->fifo_enabled ? 1 : 0);
1281 break;
1282 case FIFO_STOP:
1283 this_8 = 1;
1284 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1285 dma->dma_ctrl);
1286 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1287 this_4, this_8,
1288 dma->fifo_enabled ? 1 : 0, 0);
1289 break;
1290 case FIFO_PAUSE:
1291 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1292 this_4, this_8,
1293 dma->fifo_enabled ? 1 : 0, 0);
1294 break;
1295 }
1296 dma->fifo_status = FIFO_START;
1297}
1298
1299static void vortex_adbdma_resumefifo(vortex_t * vortex, int adbdma)
1300{
1301 stream_t *dma = &vortex->dma_adb[adbdma];
1302
1303 int this_8 = 1, this_4 = 0;
1304 switch (dma->fifo_status) {
1305 case FIFO_STOP:
1306 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1307 dma->dma_ctrl);
1308 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1309 this_4, this_8,
1310 dma->fifo_enabled ? 1 : 0, 0);
1311 break;
1312 case FIFO_PAUSE:
1313 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1314 this_4, this_8,
1315 dma->fifo_enabled ? 1 : 0, 0);
1316 break;
1317 }
1318 dma->fifo_status = FIFO_START;
1319}
1320
1321static void vortex_adbdma_pausefifo(vortex_t * vortex, int adbdma)
1322{
1323 stream_t *dma = &vortex->dma_adb[adbdma];
1324
1325 int this_8 = 0, this_4 = 0;
1326 switch (dma->fifo_status) {
1327 case FIFO_START:
1328 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1329 this_4, this_8, 0, 0);
1330 break;
1331 case FIFO_STOP:
1332 hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
1333 dma->dma_ctrl);
1334 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1335 this_4, this_8, 0, 0);
1336 break;
1337 }
1338 dma->fifo_status = FIFO_PAUSE;
1339}
1340
1341static void vortex_adbdma_stopfifo(vortex_t * vortex, int adbdma)
1342{
1343 stream_t *dma = &vortex->dma_adb[adbdma];
1344
1345 int this_4 = 0, this_8 = 0;
1346 if (dma->fifo_status == FIFO_START)
1347 vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
1348 this_4, this_8, 0, 0);
1349 else if (dma->fifo_status == FIFO_STOP)
1350 return;
1351 dma->fifo_status = FIFO_STOP;
1352 dma->fifo_enabled = 0;
1353}
1354
1355/* WTDMA */
1356
1357#ifndef CHIP_AU8810
1358static void vortex_wtdma_setfirstbuffer(vortex_t * vortex, int wtdma)
1359{
1360 //int this_7c=dma_ctrl;
1361 stream_t *dma = &vortex->dma_wt[wtdma];
1362
1363 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1364}
1365
1366static void vortex_wtdma_setstartbuffer(vortex_t * vortex, int wtdma, int sb)
1367{
1368 stream_t *dma = &vortex->dma_wt[wtdma];
1369 //hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2), sb << ((0x1f-(wtdma&0xf)*2)));
1370 hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2),
1371 sb << ((0xf - (wtdma & 0xf)) * 2));
1372 dma->period_real = dma->period_virt = sb;
1373}
1374
1375static void
1376vortex_wtdma_setbuffers(vortex_t * vortex, int wtdma,
1377 int psize, int count)
1378{
1379 stream_t *dma = &vortex->dma_wt[wtdma];
1380
1381 dma->period_bytes = psize;
1382 dma->nr_periods = count;
1383
1384 dma->cfg0 = 0;
1385 dma->cfg1 = 0;
1386 switch (count) {
1387 /* Four or more pages */
1388 default:
1389 case 4:
1390 dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize-1);
1391 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0xc,
1392 snd_pcm_sgbuf_get_addr(dma->substream, psize * 3));
1393 /* 3 pages */
1394 case 3:
1395 dma->cfg0 |= 0x12000000;
1396 dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
1397 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x8,
1398 snd_pcm_sgbuf_get_addr(dma->substream, psize * 2));
1399 /* 2 pages */
1400 case 2:
1401 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize-1);
1402 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x4,
1403 snd_pcm_sgbuf_get_addr(dma->substream, psize));
1404 /* 1 page */
1405 case 1:
1406 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
1407 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4),
1408 snd_pcm_sgbuf_get_addr(dma->substream, 0));
1409 break;
1410 }
1411 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0);
1412 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1);
1413
1414 vortex_wtdma_setfirstbuffer(vortex, wtdma);
1415 vortex_wtdma_setstartbuffer(vortex, wtdma, 0);
1416}
1417
1418static void
1419vortex_wtdma_setmode(vortex_t * vortex, int wtdma, int ie, int fmt, int d,
1420 /*int e, */ u32 offset)
1421{
1422 stream_t *dma = &vortex->dma_wt[wtdma];
1423
1424 //dma->this_08 = e;
1425 dma->dma_unknown = d;
1426 dma->dma_ctrl = 0;
1427 dma->dma_ctrl =
1428 ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
1429 /* PCMOUT interrupt */
1430 dma->dma_ctrl =
1431 (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
1432 /* Always playback. */
1433 dma->dma_ctrl |= (1 << DIR_SHIFT);
1434 /* Audio Format */
1435 dma->dma_ctrl =
1436 (dma->dma_ctrl & FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
1437 /* Write into hardware */
1438 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
1439}
1440
1441static int vortex_wtdma_bufshift(vortex_t * vortex, int wtdma)
1442{
1443 stream_t *dma = &vortex->dma_wt[wtdma];
1444 int page, p, pp, delta, i;
1445
1446 page =
1447 (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2))
1448 >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK;
1449 if (dma->nr_periods >= 4)
1450 delta = (page - dma->period_real) & 3;
1451 else {
1452 delta = (page - dma->period_real);
1453 if (delta < 0)
1454 delta += dma->nr_periods;
1455 }
1456 if (delta == 0)
1457 return 0;
1458
1459 /* refresh hw page table */
1460 if (dma->nr_periods > 4) {
1461 for (i = 0; i < delta; i++) {
1462 /* p: audio buffer page index */
1463 p = dma->period_virt + i + 4;
1464 if (p >= dma->nr_periods)
1465 p -= dma->nr_periods;
1466 /* pp: hardware DMA page index. */
1467 pp = dma->period_real + i;
1468 if (pp >= 4)
1469 pp -= 4;
1470 hwwrite(vortex->mmio,
1471 VORTEX_WTDMA_BUFBASE +
1472 (((wtdma << 2) + pp) << 2),
1473 snd_pcm_sgbuf_get_addr(dma->substream,
1474 dma->period_bytes * p));
1475 /* Force write thru cache. */
1476 hwread(vortex->mmio, VORTEX_WTDMA_BUFBASE +
1477 (((wtdma << 2) + pp) << 2));
1478 }
1479 }
1480 dma->period_virt += delta;
1481 if (dma->period_virt >= dma->nr_periods)
1482 dma->period_virt -= dma->nr_periods;
1483 dma->period_real = page;
1484
1485 if (delta != 1)
1486 dev_warn(vortex->card->dev, "wt virt = %d, delta = %d\n",
1487 dma->period_virt, delta);
1488
1489 return delta;
1490}
1491
1492#if 0
1493static void
1494vortex_wtdma_getposition(vortex_t * vortex, int wtdma, int *subbuf, int *pos)
1495{
1496 int temp;
1497 temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
1498 *subbuf = (temp >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK;
1499 *pos = temp & POS_MASK;
1500}
1501
1502static int vortex_wtdma_getcursubuffer(vortex_t * vortex, int wtdma)
1503{
1504 return ((hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >>
1505 POS_SHIFT) & POS_MASK);
1506}
1507#endif
1508static inline int vortex_wtdma_getlinearpos(vortex_t * vortex, int wtdma)
1509{
1510 stream_t *dma = &vortex->dma_wt[wtdma];
1511 int temp;
1512
1513 temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
1514 temp = (dma->period_virt * dma->period_bytes) + (temp & (dma->period_bytes - 1));
1515 return temp;
1516}
1517
1518static void vortex_wtdma_startfifo(vortex_t * vortex, int wtdma)
1519{
1520 stream_t *dma = &vortex->dma_wt[wtdma];
1521 int this_8 = 0, this_4 = 0;
1522
1523 switch (dma->fifo_status) {
1524 case FIFO_START:
1525 vortex_fifo_setwtvalid(vortex, wtdma,
1526 dma->fifo_enabled ? 1 : 0);
1527 break;
1528 case FIFO_STOP:
1529 this_8 = 1;
1530 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1531 dma->dma_ctrl);
1532 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1533 this_4, this_8,
1534 dma->fifo_enabled ? 1 : 0, 0);
1535 break;
1536 case FIFO_PAUSE:
1537 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1538 this_4, this_8,
1539 dma->fifo_enabled ? 1 : 0, 0);
1540 break;
1541 }
1542 dma->fifo_status = FIFO_START;
1543}
1544
1545static void vortex_wtdma_resumefifo(vortex_t * vortex, int wtdma)
1546{
1547 stream_t *dma = &vortex->dma_wt[wtdma];
1548
1549 int this_8 = 0, this_4 = 0;
1550 switch (dma->fifo_status) {
1551 case FIFO_STOP:
1552 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1553 dma->dma_ctrl);
1554 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1555 this_4, this_8,
1556 dma->fifo_enabled ? 1 : 0, 0);
1557 break;
1558 case FIFO_PAUSE:
1559 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1560 this_4, this_8,
1561 dma->fifo_enabled ? 1 : 0, 0);
1562 break;
1563 }
1564 dma->fifo_status = FIFO_START;
1565}
1566
1567static void vortex_wtdma_pausefifo(vortex_t * vortex, int wtdma)
1568{
1569 stream_t *dma = &vortex->dma_wt[wtdma];
1570
1571 int this_8 = 0, this_4 = 0;
1572 switch (dma->fifo_status) {
1573 case FIFO_START:
1574 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1575 this_4, this_8, 0, 0);
1576 break;
1577 case FIFO_STOP:
1578 hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
1579 dma->dma_ctrl);
1580 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1581 this_4, this_8, 0, 0);
1582 break;
1583 }
1584 dma->fifo_status = FIFO_PAUSE;
1585}
1586
1587static void vortex_wtdma_stopfifo(vortex_t * vortex, int wtdma)
1588{
1589 stream_t *dma = &vortex->dma_wt[wtdma];
1590
1591 int this_4 = 0, this_8 = 0;
1592 if (dma->fifo_status == FIFO_START)
1593 vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
1594 this_4, this_8, 0, 0);
1595 else if (dma->fifo_status == FIFO_STOP)
1596 return;
1597 dma->fifo_status = FIFO_STOP;
1598 dma->fifo_enabled = 0;
1599}
1600
1601#endif
1602/* ADB Routes */
1603
1604typedef int ADBRamLink;
1605static void vortex_adb_init(vortex_t * vortex)
1606{
1607 int i;
1608 /* it looks like we are writing more than we need to...
1609 * if we write what we are supposed to it breaks things... */
1610 hwwrite(vortex->mmio, VORTEX_ADB_SR, 0);
1611 for (i = 0; i < VORTEX_ADB_RTBASE_COUNT; i++)
1612 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (i << 2),
1613 hwread(vortex->mmio,
1614 VORTEX_ADB_RTBASE + (i << 2)) | ROUTE_MASK);
1615 for (i = 0; i < VORTEX_ADB_CHNBASE_COUNT; i++) {
1616 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (i << 2),
1617 hwread(vortex->mmio,
1618 VORTEX_ADB_CHNBASE + (i << 2)) | ROUTE_MASK);
1619 }
1620}
1621
1622static void vortex_adb_en_sr(vortex_t * vortex, int channel)
1623{
1624 hwwrite(vortex->mmio, VORTEX_ADB_SR,
1625 hwread(vortex->mmio, VORTEX_ADB_SR) | (0x1 << channel));
1626}
1627
1628static void vortex_adb_dis_sr(vortex_t * vortex, int channel)
1629{
1630 hwwrite(vortex->mmio, VORTEX_ADB_SR,
1631 hwread(vortex->mmio, VORTEX_ADB_SR) & ~(0x1 << channel));
1632}
1633
1634static void
1635vortex_adb_addroutes(vortex_t * vortex, unsigned char channel,
1636 ADBRamLink * route, int rnum)
1637{
1638 int temp, prev, lifeboat = 0;
1639
1640 if ((rnum <= 0) || (route == NULL))
1641 return;
1642 /* Write last routes. */
1643 rnum--;
1644 hwwrite(vortex->mmio,
1645 VORTEX_ADB_RTBASE + ((route[rnum] & ADB_MASK) << 2),
1646 ROUTE_MASK);
1647 while (rnum > 0) {
1648 hwwrite(vortex->mmio,
1649 VORTEX_ADB_RTBASE +
1650 ((route[rnum - 1] & ADB_MASK) << 2), route[rnum]);
1651 rnum--;
1652 }
1653 /* Write first route. */
1654 temp =
1655 hwread(vortex->mmio,
1656 VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
1657 if (temp == ADB_MASK) {
1658 /* First entry on this channel. */
1659 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
1660 route[0]);
1661 vortex_adb_en_sr(vortex, channel);
1662 return;
1663 }
1664 /* Not first entry on this channel. Need to link. */
1665 do {
1666 prev = temp;
1667 temp =
1668 hwread(vortex->mmio,
1669 VORTEX_ADB_RTBASE + (temp << 2)) & ADB_MASK;
1670 if ((lifeboat++) > ADB_MASK) {
1671 dev_err(vortex->card->dev,
1672 "vortex_adb_addroutes: unending route! 0x%x\n",
1673 *route);
1674 return;
1675 }
1676 }
1677 while (temp != ADB_MASK);
1678 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), route[0]);
1679}
1680
1681static void
1682vortex_adb_delroutes(vortex_t * vortex, unsigned char channel,
1683 ADBRamLink route0, ADBRamLink route1)
1684{
1685 int temp, lifeboat = 0, prev;
1686
1687 /* Find route. */
1688 temp =
1689 hwread(vortex->mmio,
1690 VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
1691 if (temp == (route0 & ADB_MASK)) {
1692 temp =
1693 hwread(vortex->mmio,
1694 VORTEX_ADB_RTBASE + ((route1 & ADB_MASK) << 2));
1695 if ((temp & ADB_MASK) == ADB_MASK)
1696 vortex_adb_dis_sr(vortex, channel);
1697 hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
1698 temp);
1699 return;
1700 }
1701 do {
1702 prev = temp;
1703 temp =
1704 hwread(vortex->mmio,
1705 VORTEX_ADB_RTBASE + (prev << 2)) & ADB_MASK;
1706 if (((lifeboat++) > ADB_MASK) || (temp == ADB_MASK)) {
1707 dev_err(vortex->card->dev,
1708 "vortex_adb_delroutes: route not found! 0x%x\n",
1709 route0);
1710 return;
1711 }
1712 }
1713 while (temp != (route0 & ADB_MASK));
1714 temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
1715 if ((temp & ADB_MASK) == route1)
1716 temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
1717 /* Make bridge over deleted route. */
1718 hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), temp);
1719}
1720
1721static void
1722vortex_route(vortex_t * vortex, int en, unsigned char channel,
1723 unsigned char source, unsigned char dest)
1724{
1725 ADBRamLink route;
1726
1727 route = ((source & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1728 if (en) {
1729 vortex_adb_addroutes(vortex, channel, &route, 1);
1730 if ((source < (OFFSET_SRCOUT + NR_SRC))
1731 && (source >= OFFSET_SRCOUT))
1732 vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
1733 channel);
1734 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1735 && (source >= OFFSET_MIXOUT))
1736 vortex_mixer_addWTD(vortex,
1737 (source - OFFSET_MIXOUT), channel);
1738 } else {
1739 vortex_adb_delroutes(vortex, channel, route, route);
1740 if ((source < (OFFSET_SRCOUT + NR_SRC))
1741 && (source >= OFFSET_SRCOUT))
1742 vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
1743 channel);
1744 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1745 && (source >= OFFSET_MIXOUT))
1746 vortex_mixer_delWTD(vortex,
1747 (source - OFFSET_MIXOUT), channel);
1748 }
1749}
1750
1751#if 0
1752static void
1753vortex_routes(vortex_t * vortex, int en, unsigned char channel,
1754 unsigned char source, unsigned char dest0, unsigned char dest1)
1755{
1756 ADBRamLink route[2];
1757
1758 route[0] = ((source & ADB_MASK) << ADB_SHIFT) | (dest0 & ADB_MASK);
1759 route[1] = ((source & ADB_MASK) << ADB_SHIFT) | (dest1 & ADB_MASK);
1760
1761 if (en) {
1762 vortex_adb_addroutes(vortex, channel, route, 2);
1763 if ((source < (OFFSET_SRCOUT + NR_SRC))
1764 && (source >= (OFFSET_SRCOUT)))
1765 vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
1766 channel);
1767 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1768 && (source >= (OFFSET_MIXOUT)))
1769 vortex_mixer_addWTD(vortex,
1770 (source - OFFSET_MIXOUT), channel);
1771 } else {
1772 vortex_adb_delroutes(vortex, channel, route[0], route[1]);
1773 if ((source < (OFFSET_SRCOUT + NR_SRC))
1774 && (source >= (OFFSET_SRCOUT)))
1775 vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
1776 channel);
1777 else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
1778 && (source >= (OFFSET_MIXOUT)))
1779 vortex_mixer_delWTD(vortex,
1780 (source - OFFSET_MIXOUT), channel);
1781 }
1782}
1783
1784#endif
1785/* Route two sources to same target. Sources must be of same class !!! */
1786static void
1787vortex_routeLRT(vortex_t * vortex, int en, unsigned char ch,
1788 unsigned char source0, unsigned char source1,
1789 unsigned char dest)
1790{
1791 ADBRamLink route[2];
1792
1793 route[0] = ((source0 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1794 route[1] = ((source1 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
1795
1796 if (dest < 0x10)
1797 route[1] = (route[1] & ~ADB_MASK) | (dest + 0x20); /* fifo A */
1798
1799 if (en) {
1800 vortex_adb_addroutes(vortex, ch, route, 2);
1801 if ((source0 < (OFFSET_SRCOUT + NR_SRC))
1802 && (source0 >= OFFSET_SRCOUT)) {
1803 vortex_src_addWTD(vortex,
1804 (source0 - OFFSET_SRCOUT), ch);
1805 vortex_src_addWTD(vortex,
1806 (source1 - OFFSET_SRCOUT), ch);
1807 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
1808 && (source0 >= OFFSET_MIXOUT)) {
1809 vortex_mixer_addWTD(vortex,
1810 (source0 - OFFSET_MIXOUT), ch);
1811 vortex_mixer_addWTD(vortex,
1812 (source1 - OFFSET_MIXOUT), ch);
1813 }
1814 } else {
1815 vortex_adb_delroutes(vortex, ch, route[0], route[1]);
1816 if ((source0 < (OFFSET_SRCOUT + NR_SRC))
1817 && (source0 >= OFFSET_SRCOUT)) {
1818 vortex_src_delWTD(vortex,
1819 (source0 - OFFSET_SRCOUT), ch);
1820 vortex_src_delWTD(vortex,
1821 (source1 - OFFSET_SRCOUT), ch);
1822 } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
1823 && (source0 >= OFFSET_MIXOUT)) {
1824 vortex_mixer_delWTD(vortex,
1825 (source0 - OFFSET_MIXOUT), ch);
1826 vortex_mixer_delWTD(vortex,
1827 (source1 - OFFSET_MIXOUT), ch);
1828 }
1829 }
1830}
1831
1832/* Connection stuff */
1833
1834// Connect adbdma to src('s).
1835static void
1836vortex_connection_adbdma_src(vortex_t * vortex, int en, unsigned char ch,
1837 unsigned char adbdma, unsigned char src)
1838{
1839 vortex_route(vortex, en, ch, ADB_DMA(adbdma), ADB_SRCIN(src));
1840}
1841
1842// Connect SRC to mixin.
1843static void
1844vortex_connection_src_mixin(vortex_t * vortex, int en,
1845 unsigned char channel, unsigned char src,
1846 unsigned char mixin)
1847{
1848 vortex_route(vortex, en, channel, ADB_SRCOUT(src), ADB_MIXIN(mixin));
1849}
1850
1851// Connect mixin with mix output.
1852static void
1853vortex_connection_mixin_mix(vortex_t * vortex, int en, unsigned char mixin,
1854 unsigned char mix, int a)
1855{
1856 if (en) {
1857 vortex_mix_enableinput(vortex, mix, mixin);
1858 vortex_mix_setinputvolumebyte(vortex, mix, mixin, MIX_DEFIGAIN); // added to original code.
1859 } else
1860 vortex_mix_disableinput(vortex, mix, mixin, a);
1861}
1862
1863// Connect absolut address to mixin.
1864static void
1865vortex_connection_adb_mixin(vortex_t * vortex, int en,
1866 unsigned char channel, unsigned char source,
1867 unsigned char mixin)
1868{
1869 vortex_route(vortex, en, channel, source, ADB_MIXIN(mixin));
1870}
1871
1872static void
1873vortex_connection_src_adbdma(vortex_t * vortex, int en, unsigned char ch,
1874 unsigned char src, unsigned char adbdma)
1875{
1876 vortex_route(vortex, en, ch, ADB_SRCOUT(src), ADB_DMA(adbdma));
1877}
1878
1879static void
1880vortex_connection_src_src_adbdma(vortex_t * vortex, int en,
1881 unsigned char ch, unsigned char src0,
1882 unsigned char src1, unsigned char adbdma)
1883{
1884
1885 vortex_routeLRT(vortex, en, ch, ADB_SRCOUT(src0), ADB_SRCOUT(src1),
1886 ADB_DMA(adbdma));
1887}
1888
1889// mix to absolut address.
1890static void
1891vortex_connection_mix_adb(vortex_t * vortex, int en, unsigned char ch,
1892 unsigned char mix, unsigned char dest)
1893{
1894 vortex_route(vortex, en, ch, ADB_MIXOUT(mix), dest);
1895 vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code.
1896}
1897
1898// mixer to src.
1899static void
1900vortex_connection_mix_src(vortex_t * vortex, int en, unsigned char ch,
1901 unsigned char mix, unsigned char src)
1902{
1903 vortex_route(vortex, en, ch, ADB_MIXOUT(mix), ADB_SRCIN(src));
1904 vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code.
1905}
1906
1907#if 0
1908static void
1909vortex_connection_adbdma_src_src(vortex_t * vortex, int en,
1910 unsigned char channel,
1911 unsigned char adbdma, unsigned char src0,
1912 unsigned char src1)
1913{
1914 vortex_routes(vortex, en, channel, ADB_DMA(adbdma),
1915 ADB_SRCIN(src0), ADB_SRCIN(src1));
1916}
1917
1918// Connect two mix to AdbDma.
1919static void
1920vortex_connection_mix_mix_adbdma(vortex_t * vortex, int en,
1921 unsigned char ch, unsigned char mix0,
1922 unsigned char mix1, unsigned char adbdma)
1923{
1924
1925 ADBRamLink routes[2];
1926 routes[0] =
1927 (((mix0 +
1928 OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | (adbdma & ADB_MASK);
1929 routes[1] =
1930 (((mix1 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | ((adbdma +
1931 0x20) &
1932 ADB_MASK);
1933 if (en) {
1934 vortex_adb_addroutes(vortex, ch, routes, 0x2);
1935 vortex_mixer_addWTD(vortex, mix0, ch);
1936 vortex_mixer_addWTD(vortex, mix1, ch);
1937 } else {
1938 vortex_adb_delroutes(vortex, ch, routes[0], routes[1]);
1939 vortex_mixer_delWTD(vortex, mix0, ch);
1940 vortex_mixer_delWTD(vortex, mix1, ch);
1941 }
1942}
1943#endif
1944
1945/* CODEC connect. */
1946
1947static void
1948vortex_connect_codecplay(vortex_t * vortex, int en, unsigned char mixers[])
1949{
1950#ifdef CHIP_AU8820
1951 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
1952 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
1953#else
1954#if 1
1955 // Connect front channels through EQ.
1956 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_EQIN(0));
1957 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_EQIN(1));
1958 /* Lower volume, since EQ has some gain. */
1959 vortex_mix_setvolumebyte(vortex, mixers[0], 0);
1960 vortex_mix_setvolumebyte(vortex, mixers[1], 0);
1961 vortex_route(vortex, en, 0x11, ADB_EQOUT(0), ADB_CODECOUT(0));
1962 vortex_route(vortex, en, 0x11, ADB_EQOUT(1), ADB_CODECOUT(1));
1963
1964 /* Check if reg 0x28 has SDAC bit set. */
1965 if (VORTEX_IS_QUAD(vortex)) {
1966 /* Rear channel. Note: ADB_CODECOUT(0+2) and (1+2) is for AC97 modem */
1967 vortex_connection_mix_adb(vortex, en, 0x11, mixers[2],
1968 ADB_CODECOUT(0 + 4));
1969 vortex_connection_mix_adb(vortex, en, 0x11, mixers[3],
1970 ADB_CODECOUT(1 + 4));
1971 /* pr_debug( "SDAC detected "); */
1972 }
1973#else
1974 // Use plain direct output to codec.
1975 vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
1976 vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
1977#endif
1978#endif
1979}
1980
1981static void
1982vortex_connect_codecrec(vortex_t * vortex, int en, unsigned char mixin0,
1983 unsigned char mixin1)
1984{
1985 /*
1986 Enable: 0x1, 0x1
1987 Channel: 0x11, 0x11
1988 ADB Source address: 0x48, 0x49
1989 Destination Asp4Topology_0x9c,0x98
1990 */
1991 vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(0), mixin0);
1992 vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(1), mixin1);
1993}
1994
1995// Higher level ADB audio path (de)allocator.
1996
1997/* Resource manager */
1998static int resnum[VORTEX_RESOURCE_LAST] =
1999 { NR_ADB, NR_SRC, NR_MIXIN, NR_MIXOUT, NR_A3D };
2000/*
2001 Checkout/Checkin resource of given type.
2002 resmap: resource map to be used. If NULL means that we want to allocate
2003 a DMA resource (root of all other resources of a dma channel).
2004 out: Mean checkout if != 0. Else mean Checkin resource.
2005 restype: Indicates type of resource to be checked in or out.
2006*/
2007static char
2008vortex_adb_checkinout(vortex_t * vortex, int resmap[], int out, int restype)
2009{
2010 int i, qty = resnum[restype], resinuse = 0;
2011
2012 if (out) {
2013 /* Gather used resources by all streams. */
2014 for (i = 0; i < NR_ADB; i++) {
2015 resinuse |= vortex->dma_adb[i].resources[restype];
2016 }
2017 resinuse |= vortex->fixed_res[restype];
2018 /* Find and take free resource. */
2019 for (i = 0; i < qty; i++) {
2020 if ((resinuse & (1 << i)) == 0) {
2021 if (resmap != NULL)
2022 resmap[restype] |= (1 << i);
2023 else
2024 vortex->dma_adb[i].resources[restype] |= (1 << i);
2025 /*
2026 pr_debug(
2027 "vortex: ResManager: type %d out %d\n",
2028 restype, i);
2029 */
2030 return i;
2031 }
2032 }
2033 } else {
2034 if (resmap == NULL)
2035 return -EINVAL;
2036 /* Checkin first resource of type restype. */
2037 for (i = 0; i < qty; i++) {
2038 if (resmap[restype] & (1 << i)) {
2039 resmap[restype] &= ~(1 << i);
2040 /*
2041 pr_debug(
2042 "vortex: ResManager: type %d in %d\n",
2043 restype, i);
2044 */
2045 return i;
2046 }
2047 }
2048 }
2049 dev_err(vortex->card->dev,
2050 "FATAL: ResManager: resource type %d exhausted.\n",
2051 restype);
2052 return -ENOMEM;
2053}
2054
2055/* Default Connections */
2056
2057static void vortex_connect_default(vortex_t * vortex, int en)
2058{
2059 // Connect AC97 codec.
2060 vortex->mixplayb[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2061 VORTEX_RESOURCE_MIXOUT);
2062 vortex->mixplayb[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2063 VORTEX_RESOURCE_MIXOUT);
2064 if (VORTEX_IS_QUAD(vortex)) {
2065 vortex->mixplayb[2] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2066 VORTEX_RESOURCE_MIXOUT);
2067 vortex->mixplayb[3] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2068 VORTEX_RESOURCE_MIXOUT);
2069 }
2070 vortex_connect_codecplay(vortex, en, vortex->mixplayb);
2071
2072 vortex->mixcapt[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2073 VORTEX_RESOURCE_MIXIN);
2074 vortex->mixcapt[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2075 VORTEX_RESOURCE_MIXIN);
2076 vortex_connect_codecrec(vortex, en, MIX_CAPT(0), MIX_CAPT(1));
2077
2078 // Connect SPDIF
2079#ifndef CHIP_AU8820
2080 vortex->mixspdif[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2081 VORTEX_RESOURCE_MIXOUT);
2082 vortex->mixspdif[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
2083 VORTEX_RESOURCE_MIXOUT);
2084 vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[0],
2085 ADB_SPDIFOUT(0));
2086 vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[1],
2087 ADB_SPDIFOUT(1));
2088#endif
2089 // Connect WT
2090#ifndef CHIP_AU8810
2091 vortex_wt_connect(vortex, en);
2092#endif
2093 // A3D (crosstalk canceler and A3D slices). AU8810 disabled for now.
2094#ifndef CHIP_AU8820
2095 vortex_Vort3D_connect(vortex, en);
2096#endif
2097 // Connect I2S
2098
2099 // Connect DSP interface for SQ3500 turbo (not here i think...)
2100
2101 // Connect AC98 modem codec
2102
2103}
2104
2105/*
2106 Allocate nr_ch pcm audio routes if dma < 0. If dma >= 0, existing routes
2107 are deallocated.
2108 dma: DMA engine routes to be deallocated when dma >= 0.
2109 nr_ch: Number of channels to be de/allocated.
2110 dir: direction of stream. Uses same values as substream->stream.
2111 type: Type of audio output/source (codec, spdif, i2s, dsp, etc)
2112 Return: Return allocated DMA or same DMA passed as "dma" when dma >= 0.
2113*/
2114static int
2115vortex_adb_allocroute(vortex_t *vortex, int dma, int nr_ch, int dir,
2116 int type, int subdev)
2117{
2118 stream_t *stream;
2119 int i, en;
2120 struct pcm_vol *p;
2121
2122 if (dma >= 0) {
2123 en = 0;
2124 vortex_adb_checkinout(vortex,
2125 vortex->dma_adb[dma].resources, en,
2126 VORTEX_RESOURCE_DMA);
2127 } else {
2128 en = 1;
2129 if ((dma =
2130 vortex_adb_checkinout(vortex, NULL, en,
2131 VORTEX_RESOURCE_DMA)) < 0)
2132 return -EBUSY;
2133 }
2134
2135 stream = &vortex->dma_adb[dma];
2136 stream->dma = dma;
2137 stream->dir = dir;
2138 stream->type = type;
2139
2140 /* PLAYBACK ROUTES. */
2141 if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
2142 int src[4], mix[4], ch_top;
2143#ifndef CHIP_AU8820
2144 int a3d = 0;
2145#endif
2146 /* Get SRC and MIXER hardware resources. */
2147 if (stream->type != VORTEX_PCM_SPDIF) {
2148 for (i = 0; i < nr_ch; i++) {
2149 if ((src[i] = vortex_adb_checkinout(vortex,
2150 stream->resources, en,
2151 VORTEX_RESOURCE_SRC)) < 0) {
2152 memset(stream->resources, 0,
2153 sizeof(stream->resources));
2154 return -EBUSY;
2155 }
2156 if (stream->type != VORTEX_PCM_A3D) {
2157 if ((mix[i] = vortex_adb_checkinout(vortex,
2158 stream->resources,
2159 en,
2160 VORTEX_RESOURCE_MIXIN)) < 0) {
2161 memset(stream->resources,
2162 0,
2163 sizeof(stream->resources));
2164 return -EBUSY;
2165 }
2166 }
2167 }
2168 }
2169#ifndef CHIP_AU8820
2170 if (stream->type == VORTEX_PCM_A3D) {
2171 if ((a3d =
2172 vortex_adb_checkinout(vortex,
2173 stream->resources, en,
2174 VORTEX_RESOURCE_A3D)) < 0) {
2175 memset(stream->resources, 0,
2176 sizeof(stream->resources));
2177 dev_err(vortex->card->dev,
2178 "out of A3D sources. Sorry\n");
2179 return -EBUSY;
2180 }
2181 /* (De)Initialize A3D hardware source. */
2182 vortex_Vort3D_InitializeSource(&vortex->a3d[a3d], en,
2183 vortex);
2184 }
2185 /* Make SPDIF out exclusive to "spdif" device when in use. */
2186 if ((stream->type == VORTEX_PCM_SPDIF) && (en)) {
2187 vortex_route(vortex, 0, 0x14,
2188 ADB_MIXOUT(vortex->mixspdif[0]),
2189 ADB_SPDIFOUT(0));
2190 vortex_route(vortex, 0, 0x14,
2191 ADB_MIXOUT(vortex->mixspdif[1]),
2192 ADB_SPDIFOUT(1));
2193 }
2194#endif
2195 /* Make playback routes. */
2196 for (i = 0; i < nr_ch; i++) {
2197 if (stream->type == VORTEX_PCM_ADB) {
2198 vortex_connection_adbdma_src(vortex, en,
2199 src[nr_ch - 1],
2200 dma,
2201 src[i]);
2202 vortex_connection_src_mixin(vortex, en,
2203 0x11, src[i],
2204 mix[i]);
2205 vortex_connection_mixin_mix(vortex, en,
2206 mix[i],
2207 MIX_PLAYB(i), 0);
2208#ifndef CHIP_AU8820
2209 vortex_connection_mixin_mix(vortex, en,
2210 mix[i],
2211 MIX_SPDIF(i % 2), 0);
2212 vortex_mix_setinputvolumebyte(vortex,
2213 MIX_SPDIF(i % 2),
2214 mix[i],
2215 MIX_DEFIGAIN);
2216#endif
2217 }
2218#ifndef CHIP_AU8820
2219 if (stream->type == VORTEX_PCM_A3D) {
2220 vortex_connection_adbdma_src(vortex, en,
2221 src[nr_ch - 1],
2222 dma,
2223 src[i]);
2224 vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_A3DIN(a3d));
2225 /* XTalk test. */
2226 //vortex_route(vortex, en, 0x11, dma, ADB_XTALKIN(i?9:4));
2227 //vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_XTALKIN(i?4:9));
2228 }
2229 if (stream->type == VORTEX_PCM_SPDIF)
2230 vortex_route(vortex, en, 0x14,
2231 ADB_DMA(stream->dma),
2232 ADB_SPDIFOUT(i));
2233#endif
2234 }
2235 if (stream->type != VORTEX_PCM_SPDIF && stream->type != VORTEX_PCM_A3D) {
2236 ch_top = (VORTEX_IS_QUAD(vortex) ? 4 : 2);
2237 for (i = nr_ch; i < ch_top; i++) {
2238 vortex_connection_mixin_mix(vortex, en,
2239 mix[i % nr_ch],
2240 MIX_PLAYB(i), 0);
2241#ifndef CHIP_AU8820
2242 vortex_connection_mixin_mix(vortex, en,
2243 mix[i % nr_ch],
2244 MIX_SPDIF(i % 2),
2245 0);
2246 vortex_mix_setinputvolumebyte(vortex,
2247 MIX_SPDIF(i % 2),
2248 mix[i % nr_ch],
2249 MIX_DEFIGAIN);
2250#endif
2251 }
2252 if (stream->type == VORTEX_PCM_ADB && en) {
2253 p = &vortex->pcm_vol[subdev];
2254 p->dma = dma;
2255 for (i = 0; i < nr_ch; i++)
2256 p->mixin[i] = mix[i];
2257 for (i = 0; i < ch_top; i++)
2258 p->vol[i] = 0;
2259 }
2260 }
2261#ifndef CHIP_AU8820
2262 else {
2263 if (nr_ch == 1 && stream->type == VORTEX_PCM_SPDIF)
2264 vortex_route(vortex, en, 0x14,
2265 ADB_DMA(stream->dma),
2266 ADB_SPDIFOUT(1));
2267 }
2268 /* Reconnect SPDIF out when "spdif" device is down. */
2269 if ((stream->type == VORTEX_PCM_SPDIF) && (!en)) {
2270 vortex_route(vortex, 1, 0x14,
2271 ADB_MIXOUT(vortex->mixspdif[0]),
2272 ADB_SPDIFOUT(0));
2273 vortex_route(vortex, 1, 0x14,
2274 ADB_MIXOUT(vortex->mixspdif[1]),
2275 ADB_SPDIFOUT(1));
2276 }
2277#endif
2278 /* CAPTURE ROUTES. */
2279 } else {
2280 int src[2], mix[2];
2281
2282 if (nr_ch < 1)
2283 return -EINVAL;
2284
2285 /* Get SRC and MIXER hardware resources. */
2286 for (i = 0; i < nr_ch; i++) {
2287 if ((mix[i] =
2288 vortex_adb_checkinout(vortex,
2289 stream->resources, en,
2290 VORTEX_RESOURCE_MIXOUT))
2291 < 0) {
2292 memset(stream->resources, 0,
2293 sizeof(stream->resources));
2294 return -EBUSY;
2295 }
2296 if ((src[i] =
2297 vortex_adb_checkinout(vortex,
2298 stream->resources, en,
2299 VORTEX_RESOURCE_SRC)) < 0) {
2300 memset(stream->resources, 0,
2301 sizeof(stream->resources));
2302 return -EBUSY;
2303 }
2304 }
2305
2306 /* Make capture routes. */
2307 vortex_connection_mixin_mix(vortex, en, MIX_CAPT(0), mix[0], 0);
2308 vortex_connection_mix_src(vortex, en, 0x11, mix[0], src[0]);
2309 if (nr_ch == 1) {
2310 vortex_connection_mixin_mix(vortex, en,
2311 MIX_CAPT(1), mix[0], 0);
2312 vortex_connection_src_adbdma(vortex, en,
2313 src[0],
2314 src[0], dma);
2315 } else {
2316 vortex_connection_mixin_mix(vortex, en,
2317 MIX_CAPT(1), mix[1], 0);
2318 vortex_connection_mix_src(vortex, en, 0x11, mix[1],
2319 src[1]);
2320 vortex_connection_src_src_adbdma(vortex, en,
2321 src[1], src[0],
2322 src[1], dma);
2323 }
2324 }
2325 vortex->dma_adb[dma].nr_ch = nr_ch;
2326
2327#if 0
2328 /* AC97 Codec channel setup. FIXME: this has no effect on some cards !! */
2329 if (nr_ch < 4) {
2330 /* Copy stereo to rear channel (surround) */
2331 snd_ac97_write_cache(vortex->codec,
2332 AC97_SIGMATEL_DAC2INVERT,
2333 snd_ac97_read(vortex->codec,
2334 AC97_SIGMATEL_DAC2INVERT)
2335 | 4);
2336 } else {
2337 /* Allow separate front and rear channels. */
2338 snd_ac97_write_cache(vortex->codec,
2339 AC97_SIGMATEL_DAC2INVERT,
2340 snd_ac97_read(vortex->codec,
2341 AC97_SIGMATEL_DAC2INVERT)
2342 & ~((u32)
2343 4));
2344 }
2345#endif
2346 return dma;
2347}
2348
2349/*
2350 Set the SampleRate of the SRC's attached to the given DMA engine.
2351 */
2352static void
2353vortex_adb_setsrc(vortex_t * vortex, int adbdma, unsigned int rate, int dir)
2354{
2355 stream_t *stream = &(vortex->dma_adb[adbdma]);
2356 int i, cvrt;
2357
2358 /* dir=1:play ; dir=0:rec */
2359 if (dir)
2360 cvrt = SRC_RATIO(rate, 48000);
2361 else
2362 cvrt = SRC_RATIO(48000, rate);
2363
2364 /* Setup SRC's */
2365 for (i = 0; i < NR_SRC; i++) {
2366 if (stream->resources[VORTEX_RESOURCE_SRC] & (1 << i))
2367 vortex_src_setupchannel(vortex, i, cvrt, 0, 0, i, dir, 1, cvrt, dir);
2368 }
2369}
2370
2371// Timer and ISR functions.
2372
2373static void vortex_settimer(vortex_t * vortex, int period)
2374{
2375 //set the timer period to <period> 48000ths of a second.
2376 hwwrite(vortex->mmio, VORTEX_IRQ_STAT, period);
2377}
2378
2379#if 0
2380static void vortex_enable_timer_int(vortex_t * card)
2381{
2382 hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2383 hwread(card->mmio, VORTEX_IRQ_CTRL) | IRQ_TIMER | 0x60);
2384}
2385
2386static void vortex_disable_timer_int(vortex_t * card)
2387{
2388 hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2389 hwread(card->mmio, VORTEX_IRQ_CTRL) & ~IRQ_TIMER);
2390}
2391
2392#endif
2393static void vortex_enable_int(vortex_t * card)
2394{
2395 // CAsp4ISR__EnableVortexInt_void_
2396 hwwrite(card->mmio, VORTEX_CTRL,
2397 hwread(card->mmio, VORTEX_CTRL) | CTRL_IRQ_ENABLE);
2398 hwwrite(card->mmio, VORTEX_IRQ_CTRL,
2399 (hwread(card->mmio, VORTEX_IRQ_CTRL) & 0xffffefc0) | 0x24);
2400}
2401
2402static void vortex_disable_int(vortex_t * card)
2403{
2404 hwwrite(card->mmio, VORTEX_CTRL,
2405 hwread(card->mmio, VORTEX_CTRL) & ~CTRL_IRQ_ENABLE);
2406}
2407
2408static irqreturn_t vortex_interrupt(int irq, void *dev_id)
2409{
2410 vortex_t *vortex = dev_id;
2411 int i, handled;
2412 u32 source;
2413
2414 //check if the interrupt is ours.
2415 if (!(hwread(vortex->mmio, VORTEX_STAT) & 0x1))
2416 return IRQ_NONE;
2417
2418 // This is the Interrupt Enable flag we set before (consistency check).
2419 if (!(hwread(vortex->mmio, VORTEX_CTRL) & CTRL_IRQ_ENABLE))
2420 return IRQ_NONE;
2421
2422 source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
2423 // Reset IRQ flags.
2424 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, source);
2425 hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
2426 // Is at least one IRQ flag set?
2427 if (source == 0) {
2428 dev_err(vortex->card->dev, "missing irq source\n");
2429 return IRQ_NONE;
2430 }
2431
2432 handled = 0;
2433 // Attend every interrupt source.
2434 if (unlikely(source & IRQ_ERR_MASK)) {
2435 if (source & IRQ_FATAL) {
2436 dev_err(vortex->card->dev, "IRQ fatal error\n");
2437 }
2438 if (source & IRQ_PARITY) {
2439 dev_err(vortex->card->dev, "IRQ parity error\n");
2440 }
2441 if (source & IRQ_REG) {
2442 dev_err(vortex->card->dev, "IRQ reg error\n");
2443 }
2444 if (source & IRQ_FIFO) {
2445 dev_err(vortex->card->dev, "IRQ fifo error\n");
2446 }
2447 if (source & IRQ_DMA) {
2448 dev_err(vortex->card->dev, "IRQ dma error\n");
2449 }
2450 handled = 1;
2451 }
2452 if (source & IRQ_PCMOUT) {
2453 /* ALSA period acknowledge. */
2454 spin_lock(&vortex->lock);
2455 for (i = 0; i < NR_ADB; i++) {
2456 if (vortex->dma_adb[i].fifo_status == FIFO_START) {
2457 if (!vortex_adbdma_bufshift(vortex, i))
2458 continue;
2459 spin_unlock(&vortex->lock);
2460 snd_pcm_period_elapsed(vortex->dma_adb[i].
2461 substream);
2462 spin_lock(&vortex->lock);
2463 }
2464 }
2465#ifndef CHIP_AU8810
2466 for (i = 0; i < NR_WT; i++) {
2467 if (vortex->dma_wt[i].fifo_status == FIFO_START) {
2468 /* FIXME: we ignore the return value from
2469 * vortex_wtdma_bufshift() below as the delta
2470 * calculation seems not working for wavetable
2471 * by some reason
2472 */
2473 vortex_wtdma_bufshift(vortex, i);
2474 spin_unlock(&vortex->lock);
2475 snd_pcm_period_elapsed(vortex->dma_wt[i].
2476 substream);
2477 spin_lock(&vortex->lock);
2478 }
2479 }
2480#endif
2481 spin_unlock(&vortex->lock);
2482 handled = 1;
2483 }
2484 //Acknowledge the Timer interrupt
2485 if (source & IRQ_TIMER) {
2486 hwread(vortex->mmio, VORTEX_IRQ_STAT);
2487 handled = 1;
2488 }
2489 if ((source & IRQ_MIDI) && vortex->rmidi) {
2490 snd_mpu401_uart_interrupt(vortex->irq,
2491 vortex->rmidi->private_data);
2492 handled = 1;
2493 }
2494
2495 if (!handled) {
2496 dev_err(vortex->card->dev, "unknown irq source %x\n", source);
2497 }
2498 return IRQ_RETVAL(handled);
2499}
2500
2501/* Codec */
2502
2503#define POLL_COUNT 1000
2504static void vortex_codec_init(vortex_t * vortex)
2505{
2506 int i;
2507
2508 for (i = 0; i < 32; i++) {
2509 /* the windows driver writes -i, so we write -i */
2510 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), -i);
2511 msleep(2);
2512 }
2513 if (0) {
2514 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x8068);
2515 msleep(1);
2516 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
2517 msleep(1);
2518 } else {
2519 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
2520 msleep(2);
2521 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
2522 msleep(2);
2523 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80e8);
2524 msleep(2);
2525 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
2526 msleep(2);
2527 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
2528 msleep(2);
2529 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
2530 }
2531 for (i = 0; i < 32; i++) {
2532 hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), -i);
2533 msleep(5);
2534 }
2535 hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0xe8);
2536 msleep(1);
2537 /* Enable codec channels 0 and 1. */
2538 hwwrite(vortex->mmio, VORTEX_CODEC_EN,
2539 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_CODEC);
2540}
2541
2542static void
2543vortex_codec_write(struct snd_ac97 * codec, unsigned short addr, unsigned short data)
2544{
2545
2546 vortex_t *card = (vortex_t *) codec->private_data;
2547 unsigned int lifeboat = 0;
2548
2549 /* wait for transactions to clear */
2550 while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
2551 udelay(100);
2552 if (lifeboat++ > POLL_COUNT) {
2553 dev_err(card->card->dev, "ac97 codec stuck busy\n");
2554 return;
2555 }
2556 }
2557 /* write register */
2558 hwwrite(card->mmio, VORTEX_CODEC_IO,
2559 ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) |
2560 ((data << VORTEX_CODEC_DATSHIFT) & VORTEX_CODEC_DATMASK) |
2561 VORTEX_CODEC_WRITE |
2562 (codec->num << VORTEX_CODEC_ID_SHIFT) );
2563
2564 /* Flush Caches. */
2565 hwread(card->mmio, VORTEX_CODEC_IO);
2566}
2567
2568static unsigned short vortex_codec_read(struct snd_ac97 * codec, unsigned short addr)
2569{
2570
2571 vortex_t *card = (vortex_t *) codec->private_data;
2572 u32 read_addr, data;
2573 unsigned lifeboat = 0;
2574
2575 /* wait for transactions to clear */
2576 while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
2577 udelay(100);
2578 if (lifeboat++ > POLL_COUNT) {
2579 dev_err(card->card->dev, "ac97 codec stuck busy\n");
2580 return 0xffff;
2581 }
2582 }
2583 /* set up read address */
2584 read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) |
2585 (codec->num << VORTEX_CODEC_ID_SHIFT) ;
2586 hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr);
2587
2588 /* wait for address */
2589 do {
2590 udelay(100);
2591 data = hwread(card->mmio, VORTEX_CODEC_IO);
2592 if (lifeboat++ > POLL_COUNT) {
2593 dev_err(card->card->dev,
2594 "ac97 address never arrived\n");
2595 return 0xffff;
2596 }
2597 } while ((data & VORTEX_CODEC_ADDMASK) !=
2598 (addr << VORTEX_CODEC_ADDSHIFT));
2599
2600 /* return data. */
2601 return (u16) (data & VORTEX_CODEC_DATMASK);
2602}
2603
2604/* SPDIF support */
2605
2606static void vortex_spdif_init(vortex_t * vortex, int spdif_sr, int spdif_mode)
2607{
2608 int i, this_38 = 0, this_04 = 0, this_08 = 0, this_0c = 0;
2609
2610 /* CAsp4Spdif::InitializeSpdifHardware(void) */
2611 hwwrite(vortex->mmio, VORTEX_SPDIF_FLAGS,
2612 hwread(vortex->mmio, VORTEX_SPDIF_FLAGS) & 0xfff3fffd);
2613 //for (i=0x291D4; i<0x29200; i+=4)
2614 for (i = 0; i < 11; i++)
2615 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1 + (i << 2), 0);
2616 //hwwrite(vortex->mmio, 0x29190, hwread(vortex->mmio, 0x29190) | 0xc0000);
2617 hwwrite(vortex->mmio, VORTEX_CODEC_EN,
2618 hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_SPDIF);
2619
2620 /* CAsp4Spdif::ProgramSRCInHardware(enum SPDIF_SR,enum SPDIFMODE) */
2621 if (this_04 && this_08) {
2622 int edi;
2623
2624 i = (((0x5DC00000 / spdif_sr) + 1) >> 1);
2625 if (i > 0x800) {
2626 if (i < 0x1ffff)
2627 edi = (i >> 1);
2628 else
2629 edi = 0x1ffff;
2630 } else {
2631 edi = 0x800;
2632 }
2633 /* this_04 and this_08 are the CASp4Src's (samplerate converters) */
2634 vortex_src_setupchannel(vortex, this_04, edi, 0, 1,
2635 this_0c, 1, 0, edi, 1);
2636 vortex_src_setupchannel(vortex, this_08, edi, 0, 1,
2637 this_0c, 1, 0, edi, 1);
2638 }
2639
2640 i = spdif_sr;
2641 spdif_sr |= 0x8c;
2642 switch (i) {
2643 case 32000:
2644 this_38 &= 0xFFFFFFFE;
2645 this_38 &= 0xFFFFFFFD;
2646 this_38 &= 0xF3FFFFFF;
2647 this_38 |= 0x03000000; /* set 32khz samplerate */
2648 this_38 &= 0xFFFFFF3F;
2649 spdif_sr &= 0xFFFFFFFD;
2650 spdif_sr |= 1;
2651 break;
2652 case 44100:
2653 this_38 &= 0xFFFFFFFE;
2654 this_38 &= 0xFFFFFFFD;
2655 this_38 &= 0xF0FFFFFF;
2656 this_38 |= 0x03000000;
2657 this_38 &= 0xFFFFFF3F;
2658 spdif_sr &= 0xFFFFFFFC;
2659 break;
2660 case 48000:
2661 if (spdif_mode == 1) {
2662 this_38 &= 0xFFFFFFFE;
2663 this_38 &= 0xFFFFFFFD;
2664 this_38 &= 0xF2FFFFFF;
2665 this_38 |= 0x02000000; /* set 48khz samplerate */
2666 this_38 &= 0xFFFFFF3F;
2667 } else {
2668 /* J. Gordon Wolfe: I think this stuff is for AC3 */
2669 this_38 |= 0x00000003;
2670 this_38 &= 0xFFFFFFBF;
2671 this_38 |= 0x80;
2672 }
2673 spdif_sr |= 2;
2674 spdif_sr &= 0xFFFFFFFE;
2675 break;
2676
2677 }
2678 /* looks like the next 2 lines transfer a 16-bit value into 2 8-bit
2679 registers. seems to be for the standard IEC/SPDIF initialization
2680 stuff */
2681 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG0, this_38 & 0xffff);
2682 hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1, this_38 >> 0x10);
2683 hwwrite(vortex->mmio, VORTEX_SPDIF_SMPRATE, spdif_sr);
2684}
2685
2686/* Initialization */
2687
2688static int vortex_core_init(vortex_t *vortex)
2689{
2690
2691 dev_info(vortex->card->dev, "init started\n");
2692 /* Hardware Init. */
2693 hwwrite(vortex->mmio, VORTEX_CTRL, 0xffffffff);
2694 msleep(5);
2695 hwwrite(vortex->mmio, VORTEX_CTRL,
2696 hwread(vortex->mmio, VORTEX_CTRL) & 0xffdfffff);
2697 msleep(5);
2698 /* Reset IRQ flags */
2699 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffffffff);
2700 hwread(vortex->mmio, VORTEX_IRQ_STAT);
2701
2702 vortex_codec_init(vortex);
2703
2704#ifdef CHIP_AU8830
2705 hwwrite(vortex->mmio, VORTEX_CTRL,
2706 hwread(vortex->mmio, VORTEX_CTRL) | 0x1000000);
2707#endif
2708
2709 /* Init audio engine. */
2710 vortex_adbdma_init(vortex);
2711 hwwrite(vortex->mmio, VORTEX_ENGINE_CTRL, 0x0); //, 0xc83c7e58, 0xc5f93e58
2712 vortex_adb_init(vortex);
2713 /* Init processing blocks. */
2714 vortex_fifo_init(vortex);
2715 vortex_mixer_init(vortex);
2716 vortex_srcblock_init(vortex);
2717#ifndef CHIP_AU8820
2718 vortex_eq_init(vortex);
2719 vortex_spdif_init(vortex, 48000, 1);
2720 vortex_Vort3D_enable(vortex);
2721#endif
2722#ifndef CHIP_AU8810
2723 vortex_wt_init(vortex);
2724#endif
2725 // Moved to au88x0.c
2726 //vortex_connect_default(vortex, 1);
2727
2728 vortex_settimer(vortex, 0x90);
2729 // Enable Interrupts.
2730 // vortex_enable_int() must be first !!
2731 // hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0);
2732 // vortex_enable_int(vortex);
2733 //vortex_enable_timer_int(vortex);
2734 //vortex_disable_timer_int(vortex);
2735
2736 dev_info(vortex->card->dev, "init.... done.\n");
2737 spin_lock_init(&vortex->lock);
2738
2739 return 0;
2740}
2741
2742static int vortex_core_shutdown(vortex_t * vortex)
2743{
2744
2745 dev_info(vortex->card->dev, "shutdown started\n");
2746#ifndef CHIP_AU8820
2747 vortex_eq_free(vortex);
2748 vortex_Vort3D_disable(vortex);
2749#endif
2750 //vortex_disable_timer_int(vortex);
2751 vortex_disable_int(vortex);
2752 vortex_connect_default(vortex, 0);
2753 /* Reset all DMA fifos. */
2754 vortex_fifo_init(vortex);
2755 /* Erase all audio routes. */
2756 vortex_adb_init(vortex);
2757
2758 /* Disable MPU401 */
2759 //hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, hwread(vortex->mmio, VORTEX_IRQ_CTRL) & ~IRQ_MIDI);
2760 //hwwrite(vortex->mmio, VORTEX_CTRL, hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_EN);
2761
2762 hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0);
2763 hwwrite(vortex->mmio, VORTEX_CTRL, 0);
2764 msleep(5);
2765 hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffff);
2766
2767 dev_info(vortex->card->dev, "shutdown.... done.\n");
2768 return 0;
2769}
2770
2771/* Alsa support. */
2772
2773static int vortex_alsafmt_aspfmt(int alsafmt, vortex_t *v)
2774{
2775 int fmt;
2776
2777 switch (alsafmt) {
2778 case SNDRV_PCM_FORMAT_U8:
2779 fmt = 0x1;
2780 break;
2781 case SNDRV_PCM_FORMAT_MU_LAW:
2782 fmt = 0x2;
2783 break;
2784 case SNDRV_PCM_FORMAT_A_LAW:
2785 fmt = 0x3;
2786 break;
2787 case SNDRV_PCM_FORMAT_SPECIAL:
2788 fmt = 0x4; /* guess. */
2789 break;
2790 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
2791 fmt = 0x5; /* guess. */
2792 break;
2793 case SNDRV_PCM_FORMAT_S16_LE:
2794 fmt = 0x8;
2795 break;
2796 case SNDRV_PCM_FORMAT_S16_BE:
2797 fmt = 0x9; /* check this... */
2798 break;
2799 default:
2800 fmt = 0x8;
2801 dev_err(v->card->dev,
2802 "format unsupported %d\n", alsafmt);
2803 break;
2804 }
2805 return fmt;
2806}
2807
2808/* Some not yet useful translations. */
2809#if 0
2810typedef enum {
2811 ASPFMTLINEAR16 = 0, /* 0x8 */
2812 ASPFMTLINEAR8, /* 0x1 */
2813 ASPFMTULAW, /* 0x2 */
2814 ASPFMTALAW, /* 0x3 */
2815 ASPFMTSPORT, /* ? */
2816 ASPFMTSPDIF, /* ? */
2817} ASPENCODING;
2818
2819static int
2820vortex_translateformat(vortex_t * vortex, char bits, char nch, int encod)
2821{
2822 int a, this_194;
2823
2824 if ((bits != 8) && (bits != 16))
2825 return -1;
2826
2827 switch (encod) {
2828 case 0:
2829 if (bits == 0x10)
2830 a = 8; // 16 bit
2831 break;
2832 case 1:
2833 if (bits == 8)
2834 a = 1; // 8 bit
2835 break;
2836 case 2:
2837 a = 2; // U_LAW
2838 break;
2839 case 3:
2840 a = 3; // A_LAW
2841 break;
2842 }
2843 switch (nch) {
2844 case 1:
2845 this_194 = 0;
2846 break;
2847 case 2:
2848 this_194 = 1;
2849 break;
2850 case 4:
2851 this_194 = 1;
2852 break;
2853 case 6:
2854 this_194 = 1;
2855 break;
2856 }
2857 return (a);
2858}
2859
2860static void vortex_cdmacore_setformat(vortex_t * vortex, int bits, int nch)
2861{
2862 short int d, this_148;
2863
2864 d = ((bits >> 3) * nch);
2865 this_148 = 0xbb80 / d;
2866}
2867#endif