1/*
  2 * Copyright 2016 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dce_hwseq.h"
 27#include "reg_helper.h"
 28#include "hw_sequencer.h"
 29#include "core_types.h"
 30
 31#define CTX \
 32	hws->ctx
 33#define REG(reg)\
 34	hws->regs->reg
 35
 36#undef FN
 37#define FN(reg_name, field_name) \
 38	hws->shifts->field_name, hws->masks->field_name
 39
 40void dce_enable_fe_clock(struct dce_hwseq *hws,
 41		unsigned int fe_inst, bool enable)
 42{
 43	REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst],
 44			DCFE_CLOCK_ENABLE, enable);
 45}
 46
 47void dce_pipe_control_lock(struct dc *dc,
 48		struct pipe_ctx *pipe,
 49		bool lock)
 50{
 51	uint32_t lock_val = lock ? 1 : 0;
 52	uint32_t dcp_grph, scl, blnd, update_lock_mode, val;
 53	struct dce_hwseq *hws = dc->hwseq;
 54
 55	/* Not lock pipe when blank */
 56	if (lock && pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
 57		return;
 58
 59	val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],
 60			BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
 61			BLND_SCL_V_UPDATE_LOCK, &scl,
 62			BLND_BLND_V_UPDATE_LOCK, &blnd,
 63			BLND_V_UPDATE_LOCK_MODE, &update_lock_mode);
 64
 65	dcp_grph = lock_val;
 66	scl = lock_val;
 67	blnd = lock_val;
 68	update_lock_mode = lock_val;
 69
 70	REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
 71			BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph,
 72			BLND_SCL_V_UPDATE_LOCK, scl);
 73
 74	if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0)
 75		REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
 76				BLND_BLND_V_UPDATE_LOCK, blnd,
 77				BLND_V_UPDATE_LOCK_MODE, update_lock_mode);
 78
 79	if (hws->wa.blnd_crtc_trigger) {
 80		if (!lock) {
 81			uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);
 82			REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);
 83		}
 84	}
 85}
 86
 87void dce_set_blender_mode(struct dce_hwseq *hws,
 88	unsigned int blnd_inst,
 89	enum blnd_mode mode)
 90{
 91	uint32_t feedthrough = 1;
 92	uint32_t blnd_mode = 0;
 93	uint32_t multiplied_mode = 0;
 94	uint32_t alpha_mode = 2;
 95
 96	switch (mode) {
 97	case BLND_MODE_OTHER_PIPE:
 98		feedthrough = 0;
 99		blnd_mode = 1;
100		alpha_mode = 0;
101		break;
102	case BLND_MODE_BLENDING:
103		feedthrough = 0;
104		blnd_mode = 2;
105		alpha_mode = 0;
106		multiplied_mode = 1;
107		break;
108	case BLND_MODE_CURRENT_PIPE:
109	default:
110		if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||
111				blnd_inst == 0)
112			feedthrough = 0;
113		break;
114	}
115
116	REG_UPDATE(BLND_CONTROL[blnd_inst],
117		BLND_MODE, blnd_mode);
118
119	if (hws->masks->BLND_ALPHA_MODE != 0) {
120		REG_UPDATE_3(BLND_CONTROL[blnd_inst],
121			BLND_FEEDTHROUGH_EN, feedthrough,
122			BLND_ALPHA_MODE, alpha_mode,
123			BLND_MULTIPLIED_MODE, multiplied_mode);
124	}
125}
126
127
128static void dce_disable_sram_shut_down(struct dce_hwseq *hws)
129{
130	if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
131		REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,
132				DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
133}
134
135static void dce_underlay_clock_enable(struct dce_hwseq *hws)
136{
137	/* todo: why do we need this at boot? is dce_enable_fe_clock enough? */
138	if (REG(DCFEV_CLOCK_CONTROL))
139		REG_UPDATE(DCFEV_CLOCK_CONTROL,
140				DCFEV_CLOCK_ENABLE, 1);
141}
142
143static void enable_hw_base_light_sleep(void)
144{
145	/* TODO: implement */
146}
147
148static void disable_sw_manual_control_light_sleep(void)
149{
150	/* TODO: implement */
151}
152
153void dce_clock_gating_power_up(struct dce_hwseq *hws,
154		bool enable)
155{
156	if (enable) {
157		enable_hw_base_light_sleep();
158		disable_sw_manual_control_light_sleep();
159	} else {
160		dce_disable_sram_shut_down(hws);
161		dce_underlay_clock_enable(hws);
162	}
163}
164
165void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
166		struct clock_source *clk_src,
167		unsigned int tg_inst)
168{
169	if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO || clk_src->dp_clk_src) {
170		REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
171				DP_DTO0_ENABLE, 1);
172
173	} else if (clk_src->id >= CLOCK_SOURCE_COMBO_PHY_PLL0) {
174		uint32_t rate_source = clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0;
175
176		REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
177				PHYPLL_PIXEL_RATE_SOURCE, rate_source,
178				PIXEL_RATE_PLL_SOURCE, 0);
179
180		REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
181				DP_DTO0_ENABLE, 0);
182
183	} else if (clk_src->id <= CLOCK_SOURCE_ID_PLL2) {
184		uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0;
185
186		REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
187				PIXEL_RATE_SOURCE, rate_source,
188				DP_DTO0_ENABLE, 0);
189
190		if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
191			REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
192					PIXEL_RATE_PLL_SOURCE, 1);
193	} else {
194		DC_ERR("Unknown clock source. clk_src id: %d, TG_inst: %d",
195		       clk_src->id, tg_inst);
196	}
197}
198
199/* Only use LUT for 8 bit formats */
200bool dce_use_lut(enum surface_pixel_format format)
201{
202	switch (format) {
203	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
204	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
205		return true;
206	default:
207		return false;
208	}
209}