Loading...
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Cadence UART driver (found in Xilinx Zynq)
4 *
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
6 *
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
9 * in the code.
10 */
11
12#include <linux/platform_device.h>
13#include <linux/serial.h>
14#include <linux/console.h>
15#include <linux/serial_core.h>
16#include <linux/slab.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/clk.h>
20#include <linux/irq.h>
21#include <linux/io.h>
22#include <linux/of.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <linux/gpio.h>
26#include <linux/gpio/consumer.h>
27#include <linux/delay.h>
28
29#define CDNS_UART_TTY_NAME "ttyPS"
30#define CDNS_UART_NAME "xuartps"
31#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
32#define CDNS_UART_MINOR 0 /* works best with devtmpfs */
33#define CDNS_UART_NR_PORTS 16
34#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
35#define CDNS_UART_REGISTER_SPACE 0x1000
36#define TX_TIMEOUT 500000
37
38/* Rx Trigger level */
39static int rx_trigger_level = 56;
40module_param(rx_trigger_level, uint, 0444);
41MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
42
43/* Rx Timeout */
44static int rx_timeout = 10;
45module_param(rx_timeout, uint, 0444);
46MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
47
48/* Register offsets for the UART. */
49#define CDNS_UART_CR 0x00 /* Control Register */
50#define CDNS_UART_MR 0x04 /* Mode Register */
51#define CDNS_UART_IER 0x08 /* Interrupt Enable */
52#define CDNS_UART_IDR 0x0C /* Interrupt Disable */
53#define CDNS_UART_IMR 0x10 /* Interrupt Mask */
54#define CDNS_UART_ISR 0x14 /* Interrupt Status */
55#define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
56#define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
57#define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
58#define CDNS_UART_MODEMCR 0x24 /* Modem Control */
59#define CDNS_UART_MODEMSR 0x28 /* Modem Status */
60#define CDNS_UART_SR 0x2C /* Channel Status */
61#define CDNS_UART_FIFO 0x30 /* FIFO */
62#define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
63#define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
64#define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
65#define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
66#define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
67#define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
68
69/* Control Register Bit Definitions */
70#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
71#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
72#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
73#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
74#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
75#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
76#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
77#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
78#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
79#define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
80#define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
81#define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
82
83/*
84 * Mode Register:
85 * The mode register (MR) defines the mode of transfer as well as the data
86 * format. If this register is modified during transmission or reception,
87 * data validity cannot be guaranteed.
88 */
89#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
92#define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
93
94#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
95#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
96
97#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
98#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
99#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
100#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
101#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
102
103#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
104#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
105#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
106
107/*
108 * Interrupt Registers:
109 * Interrupt control logic uses the interrupt enable register (IER) and the
110 * interrupt disable register (IDR) to set the value of the bits in the
111 * interrupt mask register (IMR). The IMR determines whether to pass an
112 * interrupt to the interrupt status register (ISR).
113 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
114 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
115 * Reading either IER or IDR returns 0x00.
116 * All four registers have the same bit definitions.
117 */
118#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
119#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
120#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
121#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
122#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
123#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
124#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
125#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
126#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
127#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
128#define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
129
130 /*
131 * Do not enable parity error interrupt for the following
132 * reason: When parity error interrupt is enabled, each Rx
133 * parity error always results in 2 events. The first one
134 * being parity error interrupt and the second one with a
135 * proper Rx interrupt with the incoming data. Disabling
136 * parity error interrupt ensures better handling of parity
137 * error events. With this change, for a parity error case, we
138 * get a Rx interrupt with parity error set in ISR register
139 * and we still handle parity errors in the desired way.
140 */
141
142#define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
143 CDNS_UART_IXR_OVERRUN | \
144 CDNS_UART_IXR_RXTRIG | \
145 CDNS_UART_IXR_TOUT)
146
147/* Goes in read_status_mask for break detection as the HW doesn't do it*/
148#define CDNS_UART_IXR_BRK 0x00002000
149
150#define CDNS_UART_RXBS_SUPPORT BIT(1)
151/*
152 * Modem Control register:
153 * The read/write Modem Control register controls the interface with the modem
154 * or data set, or a peripheral device emulating a modem.
155 */
156#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
157#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
158#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
159
160/*
161 * Modem Status register:
162 * The read/write Modem Status register reports the interface with the modem
163 * or data set, or a peripheral device emulating a modem.
164 */
165#define CDNS_UART_MODEMSR_DCD BIT(7) /* Data Carrier Detect */
166#define CDNS_UART_MODEMSR_RI BIT(6) /* Ting Indicator */
167#define CDNS_UART_MODEMSR_DSR BIT(5) /* Data Set Ready */
168#define CDNS_UART_MODEMSR_CTS BIT(4) /* Clear To Send */
169
170/*
171 * Channel Status Register:
172 * The channel status register (CSR) is provided to enable the control logic
173 * to monitor the status of bits in the channel interrupt status register,
174 * even if these are masked out by the interrupt mask register.
175 */
176#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
177#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
178#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
179#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
180#define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */
181
182/* baud dividers min/max values */
183#define CDNS_UART_BDIV_MIN 4
184#define CDNS_UART_BDIV_MAX 255
185#define CDNS_UART_CD_MAX 65535
186#define UART_AUTOSUSPEND_TIMEOUT 3000
187
188/**
189 * struct cdns_uart - device data
190 * @port: Pointer to the UART port
191 * @uartclk: Reference clock
192 * @pclk: APB clock
193 * @cdns_uart_driver: Pointer to UART driver
194 * @baud: Current baud rate
195 * @clk_rate_change_nb: Notifier block for clock changes
196 * @quirks: Flags for RXBS support.
197 * @cts_override: Modem control state override
198 * @gpiod_rts: Pointer to the gpio descriptor
199 * @rs485_tx_started: RS485 tx state
200 * @tx_timer: Timer for tx
201 */
202struct cdns_uart {
203 struct uart_port *port;
204 struct clk *uartclk;
205 struct clk *pclk;
206 struct uart_driver *cdns_uart_driver;
207 unsigned int baud;
208 struct notifier_block clk_rate_change_nb;
209 u32 quirks;
210 bool cts_override;
211 struct gpio_desc *gpiod_rts;
212 bool rs485_tx_started;
213 struct hrtimer tx_timer;
214};
215struct cdns_platform_data {
216 u32 quirks;
217};
218
219struct serial_rs485 cdns_rs485_supported = {
220 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
221 SER_RS485_RTS_AFTER_SEND,
222 .delay_rts_before_send = 1,
223 .delay_rts_after_send = 1,
224};
225
226#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
227 clk_rate_change_nb)
228
229/**
230 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
231 * @dev_id: Id of the UART port
232 * @isrstatus: The interrupt status register value as read
233 * Return: None
234 */
235static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
236{
237 struct uart_port *port = (struct uart_port *)dev_id;
238 struct cdns_uart *cdns_uart = port->private_data;
239 unsigned int data;
240 unsigned int rxbs_status = 0;
241 unsigned int status_mask;
242 unsigned int framerrprocessed = 0;
243 char status = TTY_NORMAL;
244 bool is_rxbs_support;
245
246 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
247
248 while ((readl(port->membase + CDNS_UART_SR) &
249 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
250 if (is_rxbs_support)
251 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
252 data = readl(port->membase + CDNS_UART_FIFO);
253 port->icount.rx++;
254 /*
255 * There is no hardware break detection in Zynq, so we interpret
256 * framing error with all-zeros data as a break sequence.
257 * Most of the time, there's another non-zero byte at the
258 * end of the sequence.
259 */
260 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
261 if (!data) {
262 port->read_status_mask |= CDNS_UART_IXR_BRK;
263 framerrprocessed = 1;
264 continue;
265 }
266 }
267 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
268 port->icount.brk++;
269 status = TTY_BREAK;
270 if (uart_handle_break(port))
271 continue;
272 }
273
274 isrstatus &= port->read_status_mask;
275 isrstatus &= ~port->ignore_status_mask;
276 status_mask = port->read_status_mask;
277 status_mask &= ~port->ignore_status_mask;
278
279 if (data &&
280 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
281 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
282 port->icount.brk++;
283 if (uart_handle_break(port))
284 continue;
285 }
286
287 if (uart_handle_sysrq_char(port, data))
288 continue;
289
290 if (is_rxbs_support) {
291 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
292 && (status_mask & CDNS_UART_IXR_PARITY)) {
293 port->icount.parity++;
294 status = TTY_PARITY;
295 }
296 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
297 && (status_mask & CDNS_UART_IXR_PARITY)) {
298 port->icount.frame++;
299 status = TTY_FRAME;
300 }
301 } else {
302 if (isrstatus & CDNS_UART_IXR_PARITY) {
303 port->icount.parity++;
304 status = TTY_PARITY;
305 }
306 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
307 !framerrprocessed) {
308 port->icount.frame++;
309 status = TTY_FRAME;
310 }
311 }
312 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
313 port->icount.overrun++;
314 tty_insert_flip_char(&port->state->port, 0,
315 TTY_OVERRUN);
316 }
317 tty_insert_flip_char(&port->state->port, data, status);
318 isrstatus = 0;
319 }
320
321 tty_flip_buffer_push(&port->state->port);
322}
323
324/**
325 * cdns_rts_gpio_enable - Configure RTS/GPIO to high/low
326 * @cdns_uart: Handle to the cdns_uart
327 * @enable: Value to be set to RTS/GPIO
328 */
329static void cdns_rts_gpio_enable(struct cdns_uart *cdns_uart, bool enable)
330{
331 u32 val;
332
333 if (cdns_uart->gpiod_rts) {
334 gpiod_set_value(cdns_uart->gpiod_rts, enable);
335 } else {
336 val = readl(cdns_uart->port->membase + CDNS_UART_MODEMCR);
337 if (enable)
338 val |= CDNS_UART_MODEMCR_RTS;
339 else
340 val &= ~CDNS_UART_MODEMCR_RTS;
341 writel(val, cdns_uart->port->membase + CDNS_UART_MODEMCR);
342 }
343}
344
345/**
346 * cdns_rs485_tx_setup - Tx setup specific to rs485
347 * @cdns_uart: Handle to the cdns_uart
348 */
349static void cdns_rs485_tx_setup(struct cdns_uart *cdns_uart)
350{
351 bool enable;
352
353 enable = cdns_uart->port->rs485.flags & SER_RS485_RTS_ON_SEND;
354 cdns_rts_gpio_enable(cdns_uart, enable);
355
356 cdns_uart->rs485_tx_started = true;
357}
358
359/**
360 * cdns_rs485_rx_setup - Rx setup specific to rs485
361 * @cdns_uart: Handle to the cdns_uart
362 */
363static void cdns_rs485_rx_setup(struct cdns_uart *cdns_uart)
364{
365 bool enable;
366
367 enable = cdns_uart->port->rs485.flags & SER_RS485_RTS_AFTER_SEND;
368 cdns_rts_gpio_enable(cdns_uart, enable);
369
370 cdns_uart->rs485_tx_started = false;
371}
372
373/**
374 * cdns_uart_tx_empty - Check whether TX is empty
375 * @port: Handle to the uart port structure
376 *
377 * Return: TIOCSER_TEMT on success, 0 otherwise
378 */
379static unsigned int cdns_uart_tx_empty(struct uart_port *port)
380{
381 unsigned int status;
382
383 status = readl(port->membase + CDNS_UART_SR);
384 status &= (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE);
385 return (status == CDNS_UART_SR_TXEMPTY) ? TIOCSER_TEMT : 0;
386}
387
388/**
389 * cdns_rs485_rx_callback - Timer rx callback handler for rs485.
390 * @t: Handle to the hrtimer structure
391 */
392static enum hrtimer_restart cdns_rs485_rx_callback(struct hrtimer *t)
393{
394 struct cdns_uart *cdns_uart = container_of(t, struct cdns_uart, tx_timer);
395
396 /*
397 * Default Rx should be setup, because Rx signaling path
398 * need to enable to receive data.
399 */
400 cdns_rs485_rx_setup(cdns_uart);
401
402 return HRTIMER_NORESTART;
403}
404
405/**
406 * cdns_calc_after_tx_delay - calculate delay required for after tx.
407 * @cdns_uart: Handle to the cdns_uart
408 */
409static u64 cdns_calc_after_tx_delay(struct cdns_uart *cdns_uart)
410{
411 /*
412 * Frame time + stop bit time + rs485.delay_rts_after_send
413 */
414 return cdns_uart->port->frame_time
415 + DIV_ROUND_UP(cdns_uart->port->frame_time, 7)
416 + (u64)cdns_uart->port->rs485.delay_rts_after_send * NSEC_PER_MSEC;
417}
418
419/**
420 * cdns_uart_handle_tx - Handle the bytes to be transmitted.
421 * @dev_id: Id of the UART port
422 * Return: None
423 */
424static void cdns_uart_handle_tx(void *dev_id)
425{
426 struct uart_port *port = (struct uart_port *)dev_id;
427 struct cdns_uart *cdns_uart = port->private_data;
428 struct circ_buf *xmit = &port->state->xmit;
429 unsigned int numbytes;
430
431 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
432 /* Disable the TX Empty interrupt */
433 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
434 return;
435 }
436
437 numbytes = port->fifosize;
438 while (numbytes && !uart_circ_empty(xmit) &&
439 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
440
441 writel(xmit->buf[xmit->tail], port->membase + CDNS_UART_FIFO);
442 uart_xmit_advance(port, 1);
443 numbytes--;
444 }
445
446 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
447 uart_write_wakeup(port);
448
449 /* Enable the TX Empty interrupt */
450 writel(CDNS_UART_IXR_TXEMPTY, cdns_uart->port->membase + CDNS_UART_IER);
451
452 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED &&
453 (uart_circ_empty(xmit) || uart_tx_stopped(port))) {
454 cdns_uart->tx_timer.function = &cdns_rs485_rx_callback;
455 hrtimer_start(&cdns_uart->tx_timer,
456 ns_to_ktime(cdns_calc_after_tx_delay(cdns_uart)), HRTIMER_MODE_REL);
457 }
458}
459
460/**
461 * cdns_uart_isr - Interrupt handler
462 * @irq: Irq number
463 * @dev_id: Id of the port
464 *
465 * Return: IRQHANDLED
466 */
467static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
468{
469 struct uart_port *port = (struct uart_port *)dev_id;
470 unsigned int isrstatus;
471
472 uart_port_lock(port);
473
474 /* Read the interrupt status register to determine which
475 * interrupt(s) is/are active and clear them.
476 */
477 isrstatus = readl(port->membase + CDNS_UART_ISR);
478 writel(isrstatus, port->membase + CDNS_UART_ISR);
479
480 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
481 cdns_uart_handle_tx(dev_id);
482 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
483 }
484
485 isrstatus &= port->read_status_mask;
486 isrstatus &= ~port->ignore_status_mask;
487 /*
488 * Skip RX processing if RX is disabled as RXEMPTY will never be set
489 * as read bytes will not be removed from the FIFO.
490 */
491 if (isrstatus & CDNS_UART_IXR_RXMASK &&
492 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
493 cdns_uart_handle_rx(dev_id, isrstatus);
494
495 uart_port_unlock(port);
496 return IRQ_HANDLED;
497}
498
499/**
500 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
501 * @clk: UART module input clock
502 * @baud: Desired baud rate
503 * @rbdiv: BDIV value (return value)
504 * @rcd: CD value (return value)
505 * @div8: Value for clk_sel bit in mod (return value)
506 * Return: baud rate, requested baud when possible, or actual baud when there
507 * was too much error, zero if no valid divisors are found.
508 *
509 * Formula to obtain baud rate is
510 * baud_tx/rx rate = clk/CD * (BDIV + 1)
511 * input_clk = (Uart User Defined Clock or Apb Clock)
512 * depends on UCLKEN in MR Reg
513 * clk = input_clk or input_clk/8;
514 * depends on CLKS in MR reg
515 * CD and BDIV depends on values in
516 * baud rate generate register
517 * baud rate clock divisor register
518 */
519static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
520 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
521{
522 u32 cd, bdiv;
523 unsigned int calc_baud;
524 unsigned int bestbaud = 0;
525 unsigned int bauderror;
526 unsigned int besterror = ~0;
527
528 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
529 *div8 = 1;
530 clk /= 8;
531 } else {
532 *div8 = 0;
533 }
534
535 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
536 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
537 if (cd < 1 || cd > CDNS_UART_CD_MAX)
538 continue;
539
540 calc_baud = clk / (cd * (bdiv + 1));
541
542 if (baud > calc_baud)
543 bauderror = baud - calc_baud;
544 else
545 bauderror = calc_baud - baud;
546
547 if (besterror > bauderror) {
548 *rbdiv = bdiv;
549 *rcd = cd;
550 bestbaud = calc_baud;
551 besterror = bauderror;
552 }
553 }
554 /* use the values when percent error is acceptable */
555 if (((besterror * 100) / baud) < 3)
556 bestbaud = baud;
557
558 return bestbaud;
559}
560
561/**
562 * cdns_uart_set_baud_rate - Calculate and set the baud rate
563 * @port: Handle to the uart port structure
564 * @baud: Baud rate to set
565 * Return: baud rate, requested baud when possible, or actual baud when there
566 * was too much error, zero if no valid divisors are found.
567 */
568static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
569 unsigned int baud)
570{
571 unsigned int calc_baud;
572 u32 cd = 0, bdiv = 0;
573 u32 mreg;
574 int div8;
575 struct cdns_uart *cdns_uart = port->private_data;
576
577 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
578 &div8);
579
580 /* Write new divisors to hardware */
581 mreg = readl(port->membase + CDNS_UART_MR);
582 if (div8)
583 mreg |= CDNS_UART_MR_CLKSEL;
584 else
585 mreg &= ~CDNS_UART_MR_CLKSEL;
586 writel(mreg, port->membase + CDNS_UART_MR);
587 writel(cd, port->membase + CDNS_UART_BAUDGEN);
588 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
589 cdns_uart->baud = baud;
590
591 return calc_baud;
592}
593
594#ifdef CONFIG_COMMON_CLK
595/**
596 * cdns_uart_clk_notifier_cb - Clock notifier callback
597 * @nb: Notifier block
598 * @event: Notify event
599 * @data: Notifier data
600 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
601 */
602static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
603 unsigned long event, void *data)
604{
605 u32 ctrl_reg;
606 struct uart_port *port;
607 int locked = 0;
608 struct clk_notifier_data *ndata = data;
609 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
610 unsigned long flags;
611
612 port = cdns_uart->port;
613 if (port->suspended)
614 return NOTIFY_OK;
615
616 switch (event) {
617 case PRE_RATE_CHANGE:
618 {
619 u32 bdiv, cd;
620 int div8;
621
622 /*
623 * Find out if current baud-rate can be achieved with new clock
624 * frequency.
625 */
626 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
627 &bdiv, &cd, &div8)) {
628 dev_warn(port->dev, "clock rate change rejected\n");
629 return NOTIFY_BAD;
630 }
631
632 uart_port_lock_irqsave(cdns_uart->port, &flags);
633
634 /* Disable the TX and RX to set baud rate */
635 ctrl_reg = readl(port->membase + CDNS_UART_CR);
636 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
637 writel(ctrl_reg, port->membase + CDNS_UART_CR);
638
639 uart_port_unlock_irqrestore(cdns_uart->port, flags);
640
641 return NOTIFY_OK;
642 }
643 case POST_RATE_CHANGE:
644 /*
645 * Set clk dividers to generate correct baud with new clock
646 * frequency.
647 */
648
649 uart_port_lock_irqsave(cdns_uart->port, &flags);
650
651 locked = 1;
652 port->uartclk = ndata->new_rate;
653
654 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
655 cdns_uart->baud);
656 fallthrough;
657 case ABORT_RATE_CHANGE:
658 if (!locked)
659 uart_port_lock_irqsave(cdns_uart->port, &flags);
660
661 /* Set TX/RX Reset */
662 ctrl_reg = readl(port->membase + CDNS_UART_CR);
663 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
664 writel(ctrl_reg, port->membase + CDNS_UART_CR);
665
666 while (readl(port->membase + CDNS_UART_CR) &
667 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
668 cpu_relax();
669
670 /*
671 * Clear the RX disable and TX disable bits and then set the TX
672 * enable bit and RX enable bit to enable the transmitter and
673 * receiver.
674 */
675 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
676 ctrl_reg = readl(port->membase + CDNS_UART_CR);
677 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
678 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
679 writel(ctrl_reg, port->membase + CDNS_UART_CR);
680
681 uart_port_unlock_irqrestore(cdns_uart->port, flags);
682
683 return NOTIFY_OK;
684 default:
685 return NOTIFY_DONE;
686 }
687}
688#endif
689
690/**
691 * cdns_rs485_tx_callback - Timer tx callback handler for rs485.
692 * @t: Handle to the hrtimer structure
693 */
694static enum hrtimer_restart cdns_rs485_tx_callback(struct hrtimer *t)
695{
696 struct cdns_uart *cdns_uart = container_of(t, struct cdns_uart, tx_timer);
697
698 uart_port_lock(cdns_uart->port);
699 cdns_uart_handle_tx(cdns_uart->port);
700 uart_port_unlock(cdns_uart->port);
701
702 return HRTIMER_NORESTART;
703}
704
705/**
706 * cdns_uart_start_tx - Start transmitting bytes
707 * @port: Handle to the uart port structure
708 */
709static void cdns_uart_start_tx(struct uart_port *port)
710{
711 unsigned int status;
712 struct cdns_uart *cdns_uart = port->private_data;
713
714 if (uart_tx_stopped(port))
715 return;
716
717 /*
718 * Set the TX enable bit and clear the TX disable bit to enable the
719 * transmitter.
720 */
721 status = readl(port->membase + CDNS_UART_CR);
722 status &= ~CDNS_UART_CR_TX_DIS;
723 status |= CDNS_UART_CR_TX_EN;
724 writel(status, port->membase + CDNS_UART_CR);
725
726 if (uart_circ_empty(&port->state->xmit))
727 return;
728
729 /* Clear the TX Empty interrupt */
730 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
731
732 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED) {
733 if (!cdns_uart->rs485_tx_started) {
734 cdns_uart->tx_timer.function = &cdns_rs485_tx_callback;
735 cdns_rs485_tx_setup(cdns_uart);
736 return hrtimer_start(&cdns_uart->tx_timer,
737 ms_to_ktime(port->rs485.delay_rts_before_send),
738 HRTIMER_MODE_REL);
739 }
740 }
741 cdns_uart_handle_tx(port);
742}
743
744/**
745 * cdns_uart_stop_tx - Stop TX
746 * @port: Handle to the uart port structure
747 */
748static void cdns_uart_stop_tx(struct uart_port *port)
749{
750 unsigned int regval;
751 struct cdns_uart *cdns_uart = port->private_data;
752
753 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED)
754 cdns_rs485_rx_setup(cdns_uart);
755
756 regval = readl(port->membase + CDNS_UART_CR);
757 regval |= CDNS_UART_CR_TX_DIS;
758 /* Disable the transmitter */
759 writel(regval, port->membase + CDNS_UART_CR);
760}
761
762/**
763 * cdns_uart_stop_rx - Stop RX
764 * @port: Handle to the uart port structure
765 */
766static void cdns_uart_stop_rx(struct uart_port *port)
767{
768 unsigned int regval;
769
770 /* Disable RX IRQs */
771 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
772
773 /* Disable the receiver */
774 regval = readl(port->membase + CDNS_UART_CR);
775 regval |= CDNS_UART_CR_RX_DIS;
776 writel(regval, port->membase + CDNS_UART_CR);
777}
778
779/**
780 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
781 * transmitting char breaks
782 * @port: Handle to the uart port structure
783 * @ctl: Value based on which start or stop decision is taken
784 */
785static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
786{
787 unsigned int status;
788 unsigned long flags;
789
790 uart_port_lock_irqsave(port, &flags);
791
792 status = readl(port->membase + CDNS_UART_CR);
793
794 if (ctl == -1)
795 writel(CDNS_UART_CR_STARTBRK | (~CDNS_UART_CR_STOPBRK & status),
796 port->membase + CDNS_UART_CR);
797 else {
798 if ((status & CDNS_UART_CR_STOPBRK) == 0)
799 writel(CDNS_UART_CR_STOPBRK | status,
800 port->membase + CDNS_UART_CR);
801 }
802 uart_port_unlock_irqrestore(port, flags);
803}
804
805/**
806 * cdns_uart_set_termios - termios operations, handling data length, parity,
807 * stop bits, flow control, baud rate
808 * @port: Handle to the uart port structure
809 * @termios: Handle to the input termios structure
810 * @old: Values of the previously saved termios structure
811 */
812static void cdns_uart_set_termios(struct uart_port *port,
813 struct ktermios *termios,
814 const struct ktermios *old)
815{
816 u32 cval = 0;
817 unsigned int baud, minbaud, maxbaud;
818 unsigned long flags;
819 unsigned int ctrl_reg, mode_reg;
820
821 uart_port_lock_irqsave(port, &flags);
822
823 /* Disable the TX and RX to set baud rate */
824 ctrl_reg = readl(port->membase + CDNS_UART_CR);
825 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
826 writel(ctrl_reg, port->membase + CDNS_UART_CR);
827
828 /*
829 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
830 * min and max baud should be calculated here based on port->uartclk.
831 * this way we get a valid baud and can safely call set_baud()
832 */
833 minbaud = port->uartclk /
834 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
835 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
836 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
837 baud = cdns_uart_set_baud_rate(port, baud);
838 if (tty_termios_baud_rate(termios))
839 tty_termios_encode_baud_rate(termios, baud, baud);
840
841 /* Update the per-port timeout. */
842 uart_update_timeout(port, termios->c_cflag, baud);
843
844 /* Set TX/RX Reset */
845 ctrl_reg = readl(port->membase + CDNS_UART_CR);
846 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
847 writel(ctrl_reg, port->membase + CDNS_UART_CR);
848
849 while (readl(port->membase + CDNS_UART_CR) &
850 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
851 cpu_relax();
852
853 /*
854 * Clear the RX disable and TX disable bits and then set the TX enable
855 * bit and RX enable bit to enable the transmitter and receiver.
856 */
857 ctrl_reg = readl(port->membase + CDNS_UART_CR);
858 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
859 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
860 writel(ctrl_reg, port->membase + CDNS_UART_CR);
861
862 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
863
864 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
865 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
866 port->ignore_status_mask = 0;
867
868 if (termios->c_iflag & INPCK)
869 port->read_status_mask |= CDNS_UART_IXR_PARITY |
870 CDNS_UART_IXR_FRAMING;
871
872 if (termios->c_iflag & IGNPAR)
873 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
874 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
875
876 /* ignore all characters if CREAD is not set */
877 if ((termios->c_cflag & CREAD) == 0)
878 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
879 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
880 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
881
882 mode_reg = readl(port->membase + CDNS_UART_MR);
883
884 /* Handling Data Size */
885 switch (termios->c_cflag & CSIZE) {
886 case CS6:
887 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
888 break;
889 case CS7:
890 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
891 break;
892 default:
893 case CS8:
894 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
895 termios->c_cflag &= ~CSIZE;
896 termios->c_cflag |= CS8;
897 break;
898 }
899
900 /* Handling Parity and Stop Bits length */
901 if (termios->c_cflag & CSTOPB)
902 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
903 else
904 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
905
906 if (termios->c_cflag & PARENB) {
907 /* Mark or Space parity */
908 if (termios->c_cflag & CMSPAR) {
909 if (termios->c_cflag & PARODD)
910 cval |= CDNS_UART_MR_PARITY_MARK;
911 else
912 cval |= CDNS_UART_MR_PARITY_SPACE;
913 } else {
914 if (termios->c_cflag & PARODD)
915 cval |= CDNS_UART_MR_PARITY_ODD;
916 else
917 cval |= CDNS_UART_MR_PARITY_EVEN;
918 }
919 } else {
920 cval |= CDNS_UART_MR_PARITY_NONE;
921 }
922 cval |= mode_reg & 1;
923 writel(cval, port->membase + CDNS_UART_MR);
924
925 cval = readl(port->membase + CDNS_UART_MODEMCR);
926 if (termios->c_cflag & CRTSCTS)
927 cval |= CDNS_UART_MODEMCR_FCM;
928 else
929 cval &= ~CDNS_UART_MODEMCR_FCM;
930 writel(cval, port->membase + CDNS_UART_MODEMCR);
931
932 uart_port_unlock_irqrestore(port, flags);
933}
934
935/**
936 * cdns_uart_startup - Called when an application opens a cdns_uart port
937 * @port: Handle to the uart port structure
938 *
939 * Return: 0 on success, negative errno otherwise
940 */
941static int cdns_uart_startup(struct uart_port *port)
942{
943 struct cdns_uart *cdns_uart = port->private_data;
944 bool is_brk_support;
945 int ret;
946 unsigned long flags;
947 unsigned int status = 0;
948
949 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
950
951 uart_port_lock_irqsave(port, &flags);
952
953 /* Disable the TX and RX */
954 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
955 port->membase + CDNS_UART_CR);
956
957 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
958 * no break chars.
959 */
960 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
961 port->membase + CDNS_UART_CR);
962
963 while (readl(port->membase + CDNS_UART_CR) &
964 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
965 cpu_relax();
966
967 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED)
968 cdns_rs485_rx_setup(cdns_uart);
969
970 /*
971 * Clear the RX disable bit and then set the RX enable bit to enable
972 * the receiver.
973 */
974 status = readl(port->membase + CDNS_UART_CR);
975 status &= ~CDNS_UART_CR_RX_DIS;
976 status |= CDNS_UART_CR_RX_EN;
977 writel(status, port->membase + CDNS_UART_CR);
978
979 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
980 * no parity.
981 */
982 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
983 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
984 port->membase + CDNS_UART_MR);
985
986 /*
987 * Set the RX FIFO Trigger level to use most of the FIFO, but it
988 * can be tuned with a module parameter
989 */
990 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
991
992 /*
993 * Receive Timeout register is enabled but it
994 * can be tuned with a module parameter
995 */
996 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
997
998 /* Clear out any pending interrupts before enabling them */
999 writel(readl(port->membase + CDNS_UART_ISR),
1000 port->membase + CDNS_UART_ISR);
1001
1002 uart_port_unlock_irqrestore(port, flags);
1003
1004 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
1005 if (ret) {
1006 dev_err(port->dev, "request_irq '%d' failed with %d\n",
1007 port->irq, ret);
1008 return ret;
1009 }
1010
1011 /* Set the Interrupt Registers with desired interrupts */
1012 if (is_brk_support)
1013 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
1014 port->membase + CDNS_UART_IER);
1015 else
1016 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
1017
1018 return 0;
1019}
1020
1021/**
1022 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
1023 * @port: Handle to the uart port structure
1024 */
1025static void cdns_uart_shutdown(struct uart_port *port)
1026{
1027 int status;
1028 unsigned long flags;
1029 struct cdns_uart *cdns_uart = port->private_data;
1030
1031 if (cdns_uart->port->rs485.flags & SER_RS485_ENABLED)
1032 hrtimer_cancel(&cdns_uart->tx_timer);
1033
1034 uart_port_lock_irqsave(port, &flags);
1035
1036 /* Disable interrupts */
1037 status = readl(port->membase + CDNS_UART_IMR);
1038 writel(status, port->membase + CDNS_UART_IDR);
1039 writel(0xffffffff, port->membase + CDNS_UART_ISR);
1040
1041 /* Disable the TX and RX */
1042 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
1043 port->membase + CDNS_UART_CR);
1044
1045 uart_port_unlock_irqrestore(port, flags);
1046
1047 free_irq(port->irq, port);
1048}
1049
1050/**
1051 * cdns_uart_type - Set UART type to cdns_uart port
1052 * @port: Handle to the uart port structure
1053 *
1054 * Return: string on success, NULL otherwise
1055 */
1056static const char *cdns_uart_type(struct uart_port *port)
1057{
1058 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
1059}
1060
1061/**
1062 * cdns_uart_verify_port - Verify the port params
1063 * @port: Handle to the uart port structure
1064 * @ser: Handle to the structure whose members are compared
1065 *
1066 * Return: 0 on success, negative errno otherwise.
1067 */
1068static int cdns_uart_verify_port(struct uart_port *port,
1069 struct serial_struct *ser)
1070{
1071 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
1072 return -EINVAL;
1073 if (port->irq != ser->irq)
1074 return -EINVAL;
1075 if (ser->io_type != UPIO_MEM)
1076 return -EINVAL;
1077 if (port->iobase != ser->port)
1078 return -EINVAL;
1079 if (ser->hub6 != 0)
1080 return -EINVAL;
1081 return 0;
1082}
1083
1084/**
1085 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
1086 * called when the driver adds a cdns_uart port via
1087 * uart_add_one_port()
1088 * @port: Handle to the uart port structure
1089 *
1090 * Return: 0 on success, negative errno otherwise.
1091 */
1092static int cdns_uart_request_port(struct uart_port *port)
1093{
1094 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
1095 CDNS_UART_NAME)) {
1096 return -ENOMEM;
1097 }
1098
1099 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
1100 if (!port->membase) {
1101 dev_err(port->dev, "Unable to map registers\n");
1102 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
1103 return -ENOMEM;
1104 }
1105 return 0;
1106}
1107
1108/**
1109 * cdns_uart_release_port - Release UART port
1110 * @port: Handle to the uart port structure
1111 *
1112 * Release the memory region attached to a cdns_uart port. Called when the
1113 * driver removes a cdns_uart port via uart_remove_one_port().
1114 */
1115static void cdns_uart_release_port(struct uart_port *port)
1116{
1117 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
1118 iounmap(port->membase);
1119 port->membase = NULL;
1120}
1121
1122/**
1123 * cdns_uart_config_port - Configure UART port
1124 * @port: Handle to the uart port structure
1125 * @flags: If any
1126 */
1127static void cdns_uart_config_port(struct uart_port *port, int flags)
1128{
1129 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
1130 port->type = PORT_XUARTPS;
1131}
1132
1133/**
1134 * cdns_uart_get_mctrl - Get the modem control state
1135 * @port: Handle to the uart port structure
1136 *
1137 * Return: the modem control state
1138 */
1139static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1140{
1141 u32 val;
1142 unsigned int mctrl = 0;
1143 struct cdns_uart *cdns_uart_data = port->private_data;
1144
1145 if (cdns_uart_data->cts_override)
1146 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1147
1148 val = readl(port->membase + CDNS_UART_MODEMSR);
1149 if (val & CDNS_UART_MODEMSR_CTS)
1150 mctrl |= TIOCM_CTS;
1151 if (val & CDNS_UART_MODEMSR_DSR)
1152 mctrl |= TIOCM_DSR;
1153 if (val & CDNS_UART_MODEMSR_RI)
1154 mctrl |= TIOCM_RNG;
1155 if (val & CDNS_UART_MODEMSR_DCD)
1156 mctrl |= TIOCM_CAR;
1157
1158 return mctrl;
1159}
1160
1161static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1162{
1163 u32 val;
1164 u32 mode_reg;
1165 struct cdns_uart *cdns_uart_data = port->private_data;
1166
1167 if (cdns_uart_data->cts_override)
1168 return;
1169
1170 val = readl(port->membase + CDNS_UART_MODEMCR);
1171 mode_reg = readl(port->membase + CDNS_UART_MR);
1172
1173 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1174 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1175
1176 if (mctrl & TIOCM_RTS)
1177 val |= CDNS_UART_MODEMCR_RTS;
1178 if (cdns_uart_data->gpiod_rts)
1179 gpiod_set_value(cdns_uart_data->gpiod_rts, !(mctrl & TIOCM_RTS));
1180 if (mctrl & TIOCM_DTR)
1181 val |= CDNS_UART_MODEMCR_DTR;
1182 if (mctrl & TIOCM_LOOP)
1183 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1184 else
1185 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1186
1187 writel(val, port->membase + CDNS_UART_MODEMCR);
1188 writel(mode_reg, port->membase + CDNS_UART_MR);
1189}
1190
1191#ifdef CONFIG_CONSOLE_POLL
1192static int cdns_uart_poll_get_char(struct uart_port *port)
1193{
1194 int c;
1195 unsigned long flags;
1196
1197 uart_port_lock_irqsave(port, &flags);
1198
1199 /* Check if FIFO is empty */
1200 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1201 c = NO_POLL_CHAR;
1202 else /* Read a character */
1203 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1204
1205 uart_port_unlock_irqrestore(port, flags);
1206
1207 return c;
1208}
1209
1210static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1211{
1212 unsigned long flags;
1213
1214 uart_port_lock_irqsave(port, &flags);
1215
1216 /* Wait until FIFO is empty */
1217 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1218 cpu_relax();
1219
1220 /* Write a character */
1221 writel(c, port->membase + CDNS_UART_FIFO);
1222
1223 /* Wait until FIFO is empty */
1224 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1225 cpu_relax();
1226
1227 uart_port_unlock_irqrestore(port, flags);
1228}
1229#endif
1230
1231static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1232 unsigned int oldstate)
1233{
1234 switch (state) {
1235 case UART_PM_STATE_OFF:
1236 pm_runtime_mark_last_busy(port->dev);
1237 pm_runtime_put_autosuspend(port->dev);
1238 break;
1239 default:
1240 pm_runtime_get_sync(port->dev);
1241 break;
1242 }
1243}
1244
1245static const struct uart_ops cdns_uart_ops = {
1246 .set_mctrl = cdns_uart_set_mctrl,
1247 .get_mctrl = cdns_uart_get_mctrl,
1248 .start_tx = cdns_uart_start_tx,
1249 .stop_tx = cdns_uart_stop_tx,
1250 .stop_rx = cdns_uart_stop_rx,
1251 .tx_empty = cdns_uart_tx_empty,
1252 .break_ctl = cdns_uart_break_ctl,
1253 .set_termios = cdns_uart_set_termios,
1254 .startup = cdns_uart_startup,
1255 .shutdown = cdns_uart_shutdown,
1256 .pm = cdns_uart_pm,
1257 .type = cdns_uart_type,
1258 .verify_port = cdns_uart_verify_port,
1259 .request_port = cdns_uart_request_port,
1260 .release_port = cdns_uart_release_port,
1261 .config_port = cdns_uart_config_port,
1262#ifdef CONFIG_CONSOLE_POLL
1263 .poll_get_char = cdns_uart_poll_get_char,
1264 .poll_put_char = cdns_uart_poll_put_char,
1265#endif
1266};
1267
1268static struct uart_driver cdns_uart_uart_driver;
1269
1270#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1271/**
1272 * cdns_uart_console_putchar - write the character to the FIFO buffer
1273 * @port: Handle to the uart port structure
1274 * @ch: Character to be written
1275 */
1276static void cdns_uart_console_putchar(struct uart_port *port, unsigned char ch)
1277{
1278 unsigned int ctrl_reg;
1279 unsigned long timeout;
1280
1281 timeout = jiffies + msecs_to_jiffies(1000);
1282 while (1) {
1283 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1284 if (!(ctrl_reg & CDNS_UART_CR_TX_DIS))
1285 break;
1286 if (time_after(jiffies, timeout)) {
1287 dev_warn(port->dev,
1288 "timeout waiting for Enable\n");
1289 return;
1290 }
1291 cpu_relax();
1292 }
1293
1294 timeout = jiffies + msecs_to_jiffies(1000);
1295 while (1) {
1296 ctrl_reg = readl(port->membase + CDNS_UART_SR);
1297
1298 if (!(ctrl_reg & CDNS_UART_SR_TXFULL))
1299 break;
1300 if (time_after(jiffies, timeout)) {
1301 dev_warn(port->dev,
1302 "timeout waiting for TX fifo\n");
1303 return;
1304 }
1305 cpu_relax();
1306 }
1307 writel(ch, port->membase + CDNS_UART_FIFO);
1308}
1309
1310static void cdns_early_write(struct console *con, const char *s,
1311 unsigned int n)
1312{
1313 struct earlycon_device *dev = con->data;
1314
1315 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1316}
1317
1318static int __init cdns_early_console_setup(struct earlycon_device *device,
1319 const char *opt)
1320{
1321 struct uart_port *port = &device->port;
1322
1323 if (!port->membase)
1324 return -ENODEV;
1325
1326 /* initialise control register */
1327 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1328 port->membase + CDNS_UART_CR);
1329
1330 /* only set baud if specified on command line - otherwise
1331 * assume it has been initialized by a boot loader.
1332 */
1333 if (port->uartclk && device->baud) {
1334 u32 cd = 0, bdiv = 0;
1335 u32 mr;
1336 int div8;
1337
1338 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1339 &bdiv, &cd, &div8);
1340 mr = CDNS_UART_MR_PARITY_NONE;
1341 if (div8)
1342 mr |= CDNS_UART_MR_CLKSEL;
1343
1344 writel(mr, port->membase + CDNS_UART_MR);
1345 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1346 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1347 }
1348
1349 device->con->write = cdns_early_write;
1350
1351 return 0;
1352}
1353OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1354OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1355OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1356OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1357
1358
1359/* Static pointer to console port */
1360static struct uart_port *console_port;
1361
1362/**
1363 * cdns_uart_console_write - perform write operation
1364 * @co: Console handle
1365 * @s: Pointer to character array
1366 * @count: No of characters
1367 */
1368static void cdns_uart_console_write(struct console *co, const char *s,
1369 unsigned int count)
1370{
1371 struct uart_port *port = console_port;
1372 unsigned long flags;
1373 unsigned int imr, ctrl;
1374 int locked = 1;
1375
1376 if (port->sysrq)
1377 locked = 0;
1378 else if (oops_in_progress)
1379 locked = uart_port_trylock_irqsave(port, &flags);
1380 else
1381 uart_port_lock_irqsave(port, &flags);
1382
1383 /* save and disable interrupt */
1384 imr = readl(port->membase + CDNS_UART_IMR);
1385 writel(imr, port->membase + CDNS_UART_IDR);
1386
1387 /*
1388 * Make sure that the tx part is enabled. Set the TX enable bit and
1389 * clear the TX disable bit to enable the transmitter.
1390 */
1391 ctrl = readl(port->membase + CDNS_UART_CR);
1392 ctrl &= ~CDNS_UART_CR_TX_DIS;
1393 ctrl |= CDNS_UART_CR_TX_EN;
1394 writel(ctrl, port->membase + CDNS_UART_CR);
1395
1396 uart_console_write(port, s, count, cdns_uart_console_putchar);
1397 while (cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1398 cpu_relax();
1399
1400 /* restore interrupt state */
1401 writel(imr, port->membase + CDNS_UART_IER);
1402
1403 if (locked)
1404 uart_port_unlock_irqrestore(port, flags);
1405}
1406
1407/**
1408 * cdns_uart_console_setup - Initialize the uart to default config
1409 * @co: Console handle
1410 * @options: Initial settings of uart
1411 *
1412 * Return: 0 on success, negative errno otherwise.
1413 */
1414static int cdns_uart_console_setup(struct console *co, char *options)
1415{
1416 struct uart_port *port = console_port;
1417
1418 int baud = 9600;
1419 int bits = 8;
1420 int parity = 'n';
1421 int flow = 'n';
1422 unsigned long time_out;
1423
1424 if (!port->membase) {
1425 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1426 co->index);
1427 return -ENODEV;
1428 }
1429
1430 if (options)
1431 uart_parse_options(options, &baud, &parity, &bits, &flow);
1432
1433 /* Wait for tx_empty before setting up the console */
1434 time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT);
1435
1436 while (time_before(jiffies, time_out) &&
1437 cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1438 cpu_relax();
1439
1440 return uart_set_options(port, co, baud, parity, bits, flow);
1441}
1442
1443static struct console cdns_uart_console = {
1444 .name = CDNS_UART_TTY_NAME,
1445 .write = cdns_uart_console_write,
1446 .device = uart_console_device,
1447 .setup = cdns_uart_console_setup,
1448 .flags = CON_PRINTBUFFER,
1449 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1450 .data = &cdns_uart_uart_driver,
1451};
1452#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1453
1454#ifdef CONFIG_PM_SLEEP
1455/**
1456 * cdns_uart_suspend - suspend event
1457 * @device: Pointer to the device structure
1458 *
1459 * Return: 0
1460 */
1461static int cdns_uart_suspend(struct device *device)
1462{
1463 struct uart_port *port = dev_get_drvdata(device);
1464 struct cdns_uart *cdns_uart = port->private_data;
1465 int may_wake;
1466
1467 may_wake = device_may_wakeup(device);
1468
1469 if (console_suspend_enabled && uart_console(port) && may_wake) {
1470 unsigned long flags;
1471
1472 uart_port_lock_irqsave(port, &flags);
1473 /* Empty the receive FIFO 1st before making changes */
1474 while (!(readl(port->membase + CDNS_UART_SR) &
1475 CDNS_UART_SR_RXEMPTY))
1476 readl(port->membase + CDNS_UART_FIFO);
1477 /* set RX trigger level to 1 */
1478 writel(1, port->membase + CDNS_UART_RXWM);
1479 /* disable RX timeout interrups */
1480 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1481 uart_port_unlock_irqrestore(port, flags);
1482 }
1483
1484 /*
1485 * Call the API provided in serial_core.c file which handles
1486 * the suspend.
1487 */
1488 return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1489}
1490
1491/**
1492 * cdns_uart_resume - Resume after a previous suspend
1493 * @device: Pointer to the device structure
1494 *
1495 * Return: 0
1496 */
1497static int cdns_uart_resume(struct device *device)
1498{
1499 struct uart_port *port = dev_get_drvdata(device);
1500 struct cdns_uart *cdns_uart = port->private_data;
1501 unsigned long flags;
1502 u32 ctrl_reg;
1503 int may_wake;
1504 int ret;
1505
1506 may_wake = device_may_wakeup(device);
1507
1508 if (console_suspend_enabled && uart_console(port) && !may_wake) {
1509 ret = clk_enable(cdns_uart->pclk);
1510 if (ret)
1511 return ret;
1512
1513 ret = clk_enable(cdns_uart->uartclk);
1514 if (ret) {
1515 clk_disable(cdns_uart->pclk);
1516 return ret;
1517 }
1518
1519 uart_port_lock_irqsave(port, &flags);
1520
1521 /* Set TX/RX Reset */
1522 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1523 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1524 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1525 while (readl(port->membase + CDNS_UART_CR) &
1526 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1527 cpu_relax();
1528
1529 /* restore rx timeout value */
1530 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1531 /* Enable Tx/Rx */
1532 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1533 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1534 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1535 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1536
1537 clk_disable(cdns_uart->uartclk);
1538 clk_disable(cdns_uart->pclk);
1539 uart_port_unlock_irqrestore(port, flags);
1540 } else {
1541 uart_port_lock_irqsave(port, &flags);
1542 /* restore original rx trigger level */
1543 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1544 /* enable RX timeout interrupt */
1545 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1546 uart_port_unlock_irqrestore(port, flags);
1547 }
1548
1549 return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1550}
1551#endif /* ! CONFIG_PM_SLEEP */
1552static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1553{
1554 struct uart_port *port = dev_get_drvdata(dev);
1555 struct cdns_uart *cdns_uart = port->private_data;
1556
1557 clk_disable(cdns_uart->uartclk);
1558 clk_disable(cdns_uart->pclk);
1559 return 0;
1560};
1561
1562static int __maybe_unused cdns_runtime_resume(struct device *dev)
1563{
1564 struct uart_port *port = dev_get_drvdata(dev);
1565 struct cdns_uart *cdns_uart = port->private_data;
1566 int ret;
1567
1568 ret = clk_enable(cdns_uart->pclk);
1569 if (ret)
1570 return ret;
1571
1572 ret = clk_enable(cdns_uart->uartclk);
1573 if (ret) {
1574 clk_disable(cdns_uart->pclk);
1575 return ret;
1576 }
1577 return 0;
1578};
1579
1580static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1581 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1582 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1583 cdns_runtime_resume, NULL)
1584};
1585
1586static const struct cdns_platform_data zynqmp_uart_def = {
1587 .quirks = CDNS_UART_RXBS_SUPPORT, };
1588
1589/* Match table for of_platform binding */
1590static const struct of_device_id cdns_uart_of_match[] = {
1591 { .compatible = "xlnx,xuartps", },
1592 { .compatible = "cdns,uart-r1p8", },
1593 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1594 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1595 {}
1596};
1597MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1598
1599/* Temporary variable for storing number of instances */
1600static int instances;
1601
1602/**
1603 * cdns_rs485_config - Called when an application calls TIOCSRS485 ioctl.
1604 * @port: Pointer to the uart_port structure
1605 * @termios: Pointer to the ktermios structure
1606 * @rs485: Pointer to the serial_rs485 structure
1607 *
1608 * Return: 0
1609 */
1610static int cdns_rs485_config(struct uart_port *port, struct ktermios *termios,
1611 struct serial_rs485 *rs485)
1612{
1613 u32 val;
1614 struct cdns_uart *cdns_uart = port->private_data;
1615
1616 if (rs485->flags & SER_RS485_ENABLED) {
1617 dev_dbg(port->dev, "Setting UART to RS485\n");
1618 /* Make sure auto RTS is disabled */
1619 val = readl(port->membase + CDNS_UART_MODEMCR);
1620 val &= ~CDNS_UART_MODEMCR_FCM;
1621 writel(val, port->membase + CDNS_UART_MODEMCR);
1622
1623 /* Timer setup */
1624 hrtimer_init(&cdns_uart->tx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1625 cdns_uart->tx_timer.function = &cdns_rs485_tx_callback;
1626
1627 /* Disable transmitter and make Rx setup*/
1628 cdns_uart_stop_tx(port);
1629 } else {
1630 hrtimer_cancel(&cdns_uart->tx_timer);
1631 }
1632 return 0;
1633}
1634
1635/**
1636 * cdns_uart_probe - Platform driver probe
1637 * @pdev: Pointer to the platform device structure
1638 *
1639 * Return: 0 on success, negative errno otherwise
1640 */
1641static int cdns_uart_probe(struct platform_device *pdev)
1642{
1643 int rc, id, irq;
1644 struct uart_port *port;
1645 struct resource *res;
1646 struct cdns_uart *cdns_uart_data;
1647 const struct of_device_id *match;
1648
1649 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1650 GFP_KERNEL);
1651 if (!cdns_uart_data)
1652 return -ENOMEM;
1653 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1654 if (!port)
1655 return -ENOMEM;
1656
1657 /* Look for a serialN alias */
1658 id = of_alias_get_id(pdev->dev.of_node, "serial");
1659 if (id < 0)
1660 id = 0;
1661
1662 if (id >= CDNS_UART_NR_PORTS) {
1663 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1664 return -ENODEV;
1665 }
1666
1667 if (!cdns_uart_uart_driver.state) {
1668 cdns_uart_uart_driver.owner = THIS_MODULE;
1669 cdns_uart_uart_driver.driver_name = CDNS_UART_NAME;
1670 cdns_uart_uart_driver.dev_name = CDNS_UART_TTY_NAME;
1671 cdns_uart_uart_driver.major = CDNS_UART_MAJOR;
1672 cdns_uart_uart_driver.minor = CDNS_UART_MINOR;
1673 cdns_uart_uart_driver.nr = CDNS_UART_NR_PORTS;
1674#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1675 cdns_uart_uart_driver.cons = &cdns_uart_console;
1676#endif
1677
1678 rc = uart_register_driver(&cdns_uart_uart_driver);
1679 if (rc < 0) {
1680 dev_err(&pdev->dev, "Failed to register driver\n");
1681 return rc;
1682 }
1683 }
1684
1685 cdns_uart_data->cdns_uart_driver = &cdns_uart_uart_driver;
1686
1687 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1688 if (match && match->data) {
1689 const struct cdns_platform_data *data = match->data;
1690
1691 cdns_uart_data->quirks = data->quirks;
1692 }
1693
1694 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1695 if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1696 rc = PTR_ERR(cdns_uart_data->pclk);
1697 goto err_out_unregister_driver;
1698 }
1699
1700 if (IS_ERR(cdns_uart_data->pclk)) {
1701 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1702 if (IS_ERR(cdns_uart_data->pclk)) {
1703 rc = PTR_ERR(cdns_uart_data->pclk);
1704 goto err_out_unregister_driver;
1705 }
1706 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1707 }
1708
1709 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1710 if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1711 rc = PTR_ERR(cdns_uart_data->uartclk);
1712 goto err_out_unregister_driver;
1713 }
1714
1715 if (IS_ERR(cdns_uart_data->uartclk)) {
1716 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1717 if (IS_ERR(cdns_uart_data->uartclk)) {
1718 rc = PTR_ERR(cdns_uart_data->uartclk);
1719 goto err_out_unregister_driver;
1720 }
1721 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1722 }
1723
1724 rc = clk_prepare_enable(cdns_uart_data->pclk);
1725 if (rc) {
1726 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1727 goto err_out_unregister_driver;
1728 }
1729 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1730 if (rc) {
1731 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1732 goto err_out_clk_dis_pclk;
1733 }
1734
1735 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1736 if (!res) {
1737 rc = -ENODEV;
1738 goto err_out_clk_disable;
1739 }
1740
1741 irq = platform_get_irq(pdev, 0);
1742 if (irq < 0) {
1743 rc = irq;
1744 goto err_out_clk_disable;
1745 }
1746
1747#ifdef CONFIG_COMMON_CLK
1748 cdns_uart_data->clk_rate_change_nb.notifier_call =
1749 cdns_uart_clk_notifier_cb;
1750 if (clk_notifier_register(cdns_uart_data->uartclk,
1751 &cdns_uart_data->clk_rate_change_nb))
1752 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1753#endif
1754
1755 /* At this point, we've got an empty uart_port struct, initialize it */
1756 spin_lock_init(&port->lock);
1757 port->type = PORT_UNKNOWN;
1758 port->iotype = UPIO_MEM32;
1759 port->flags = UPF_BOOT_AUTOCONF;
1760 port->ops = &cdns_uart_ops;
1761 port->fifosize = CDNS_UART_FIFO_SIZE;
1762 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE);
1763 port->line = id;
1764
1765 /*
1766 * Register the port.
1767 * This function also registers this device with the tty layer
1768 * and triggers invocation of the config_port() entry point.
1769 */
1770 port->mapbase = res->start;
1771 port->irq = irq;
1772 port->dev = &pdev->dev;
1773 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1774 port->private_data = cdns_uart_data;
1775 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
1776 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
1777 port->rs485_config = cdns_rs485_config;
1778 port->rs485_supported = cdns_rs485_supported;
1779 cdns_uart_data->port = port;
1780 platform_set_drvdata(pdev, port);
1781
1782 rc = uart_get_rs485_mode(port);
1783 if (rc)
1784 goto err_out_clk_notifier;
1785
1786 cdns_uart_data->gpiod_rts = devm_gpiod_get_optional(&pdev->dev, "rts",
1787 GPIOD_OUT_LOW);
1788 if (IS_ERR(cdns_uart_data->gpiod_rts)) {
1789 rc = PTR_ERR(cdns_uart_data->gpiod_rts);
1790 dev_err(port->dev, "xuartps: devm_gpiod_get_optional failed\n");
1791 goto err_out_clk_notifier;
1792 }
1793
1794 pm_runtime_use_autosuspend(&pdev->dev);
1795 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1796 pm_runtime_set_active(&pdev->dev);
1797 pm_runtime_enable(&pdev->dev);
1798 device_init_wakeup(port->dev, true);
1799
1800#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1801 /*
1802 * If console hasn't been found yet try to assign this port
1803 * because it is required to be assigned for console setup function.
1804 * If register_console() don't assign value, then console_port pointer
1805 * is cleanup.
1806 */
1807 if (!console_port) {
1808 cdns_uart_console.index = id;
1809 console_port = port;
1810 }
1811#endif
1812 if (cdns_uart_data->port->rs485.flags & SER_RS485_ENABLED)
1813 cdns_rs485_rx_setup(cdns_uart_data);
1814
1815 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1816 if (rc) {
1817 dev_err(&pdev->dev,
1818 "uart_add_one_port() failed; err=%i\n", rc);
1819 goto err_out_pm_disable;
1820 }
1821
1822#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1823 /* This is not port which is used for console that's why clean it up */
1824 if (console_port == port &&
1825 !console_is_registered(cdns_uart_uart_driver.cons)) {
1826 console_port = NULL;
1827 cdns_uart_console.index = -1;
1828 }
1829#endif
1830
1831 cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
1832 "cts-override");
1833
1834 instances++;
1835
1836 return 0;
1837
1838err_out_pm_disable:
1839 pm_runtime_disable(&pdev->dev);
1840 pm_runtime_set_suspended(&pdev->dev);
1841 pm_runtime_dont_use_autosuspend(&pdev->dev);
1842err_out_clk_notifier:
1843#ifdef CONFIG_COMMON_CLK
1844 clk_notifier_unregister(cdns_uart_data->uartclk,
1845 &cdns_uart_data->clk_rate_change_nb);
1846#endif
1847err_out_clk_disable:
1848 clk_disable_unprepare(cdns_uart_data->uartclk);
1849err_out_clk_dis_pclk:
1850 clk_disable_unprepare(cdns_uart_data->pclk);
1851err_out_unregister_driver:
1852 if (!instances)
1853 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1854 return rc;
1855}
1856
1857/**
1858 * cdns_uart_remove - called when the platform driver is unregistered
1859 * @pdev: Pointer to the platform device structure
1860 */
1861static void cdns_uart_remove(struct platform_device *pdev)
1862{
1863 struct uart_port *port = platform_get_drvdata(pdev);
1864 struct cdns_uart *cdns_uart_data = port->private_data;
1865
1866 /* Remove the cdns_uart port from the serial core */
1867#ifdef CONFIG_COMMON_CLK
1868 clk_notifier_unregister(cdns_uart_data->uartclk,
1869 &cdns_uart_data->clk_rate_change_nb);
1870#endif
1871 uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1872 port->mapbase = 0;
1873 clk_disable_unprepare(cdns_uart_data->uartclk);
1874 clk_disable_unprepare(cdns_uart_data->pclk);
1875 pm_runtime_disable(&pdev->dev);
1876 pm_runtime_set_suspended(&pdev->dev);
1877 pm_runtime_dont_use_autosuspend(&pdev->dev);
1878 device_init_wakeup(&pdev->dev, false);
1879
1880#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1881 if (console_port == port)
1882 console_port = NULL;
1883#endif
1884
1885 if (!--instances)
1886 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1887}
1888
1889static struct platform_driver cdns_uart_platform_driver = {
1890 .probe = cdns_uart_probe,
1891 .remove_new = cdns_uart_remove,
1892 .driver = {
1893 .name = CDNS_UART_NAME,
1894 .of_match_table = cdns_uart_of_match,
1895 .pm = &cdns_uart_dev_pm_ops,
1896 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1897 },
1898};
1899
1900static int __init cdns_uart_init(void)
1901{
1902 /* Register the platform driver */
1903 return platform_driver_register(&cdns_uart_platform_driver);
1904}
1905
1906static void __exit cdns_uart_exit(void)
1907{
1908 /* Unregister the platform driver */
1909 platform_driver_unregister(&cdns_uart_platform_driver);
1910}
1911
1912arch_initcall(cdns_uart_init);
1913module_exit(cdns_uart_exit);
1914
1915MODULE_DESCRIPTION("Driver for Cadence UART");
1916MODULE_AUTHOR("Xilinx Inc.");
1917MODULE_LICENSE("GPL");
1/*
2 * Cadence UART driver (found in Xilinx Zynq)
3 *
4 * 2011 - 2014 (C) Xilinx Inc.
5 *
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
10 * later version.
11 *
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
14 * in the code.
15 */
16
17#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18#define SUPPORT_SYSRQ
19#endif
20
21#include <linux/platform_device.h>
22#include <linux/serial.h>
23#include <linux/console.h>
24#include <linux/serial_core.h>
25#include <linux/slab.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/clk.h>
29#include <linux/irq.h>
30#include <linux/io.h>
31#include <linux/of.h>
32#include <linux/module.h>
33
34#define CDNS_UART_TTY_NAME "ttyPS"
35#define CDNS_UART_NAME "xuartps"
36#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
37#define CDNS_UART_MINOR 0 /* works best with devtmpfs */
38#define CDNS_UART_NR_PORTS 2
39#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
40#define CDNS_UART_REGISTER_SPACE 0x1000
41
42/* Rx Trigger level */
43static int rx_trigger_level = 56;
44module_param(rx_trigger_level, uint, S_IRUGO);
45MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46
47/* Rx Timeout */
48static int rx_timeout = 10;
49module_param(rx_timeout, uint, S_IRUGO);
50MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
51
52/* Register offsets for the UART. */
53#define CDNS_UART_CR 0x00 /* Control Register */
54#define CDNS_UART_MR 0x04 /* Mode Register */
55#define CDNS_UART_IER 0x08 /* Interrupt Enable */
56#define CDNS_UART_IDR 0x0C /* Interrupt Disable */
57#define CDNS_UART_IMR 0x10 /* Interrupt Mask */
58#define CDNS_UART_ISR 0x14 /* Interrupt Status */
59#define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
60#define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
61#define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
62#define CDNS_UART_MODEMCR 0x24 /* Modem Control */
63#define CDNS_UART_MODEMSR 0x28 /* Modem Status */
64#define CDNS_UART_SR 0x2C /* Channel Status */
65#define CDNS_UART_FIFO 0x30 /* FIFO */
66#define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
67#define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
68#define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
69#define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
70#define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
71#define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
72
73/* Control Register Bit Definitions */
74#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
75#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
76#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
77#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
78#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
79#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
80#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
81#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
82#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
83#define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
84#define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
85#define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
86
87/*
88 * Mode Register:
89 * The mode register (MR) defines the mode of transfer as well as the data
90 * format. If this register is modified during transmission or reception,
91 * data validity cannot be guaranteed.
92 */
93#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
94#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
95#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
96
97#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
98#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
99
100#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
101#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
102#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
103#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
104#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
105
106#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
107#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
108#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
109
110/*
111 * Interrupt Registers:
112 * Interrupt control logic uses the interrupt enable register (IER) and the
113 * interrupt disable register (IDR) to set the value of the bits in the
114 * interrupt mask register (IMR). The IMR determines whether to pass an
115 * interrupt to the interrupt status register (ISR).
116 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
117 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
118 * Reading either IER or IDR returns 0x00.
119 * All four registers have the same bit definitions.
120 */
121#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
122#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
123#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
124#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
125#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
126#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
127#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
128#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
129#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
130#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
131#define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
132
133 /*
134 * Do not enable parity error interrupt for the following
135 * reason: When parity error interrupt is enabled, each Rx
136 * parity error always results in 2 events. The first one
137 * being parity error interrupt and the second one with a
138 * proper Rx interrupt with the incoming data. Disabling
139 * parity error interrupt ensures better handling of parity
140 * error events. With this change, for a parity error case, we
141 * get a Rx interrupt with parity error set in ISR register
142 * and we still handle parity errors in the desired way.
143 */
144
145#define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
146 CDNS_UART_IXR_OVERRUN | \
147 CDNS_UART_IXR_RXTRIG | \
148 CDNS_UART_IXR_TOUT)
149
150/* Goes in read_status_mask for break detection as the HW doesn't do it*/
151#define CDNS_UART_IXR_BRK 0x00002000
152
153#define CDNS_UART_RXBS_SUPPORT BIT(1)
154/*
155 * Modem Control register:
156 * The read/write Modem Control register controls the interface with the modem
157 * or data set, or a peripheral device emulating a modem.
158 */
159#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
160#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
161#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
162
163/*
164 * Channel Status Register:
165 * The channel status register (CSR) is provided to enable the control logic
166 * to monitor the status of bits in the channel interrupt status register,
167 * even if these are masked out by the interrupt mask register.
168 */
169#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
170#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
171#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
172#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
173
174/* baud dividers min/max values */
175#define CDNS_UART_BDIV_MIN 4
176#define CDNS_UART_BDIV_MAX 255
177#define CDNS_UART_CD_MAX 65535
178
179/**
180 * struct cdns_uart - device data
181 * @port: Pointer to the UART port
182 * @uartclk: Reference clock
183 * @pclk: APB clock
184 * @baud: Current baud rate
185 * @clk_rate_change_nb: Notifier block for clock changes
186 */
187struct cdns_uart {
188 struct uart_port *port;
189 struct clk *uartclk;
190 struct clk *pclk;
191 unsigned int baud;
192 struct notifier_block clk_rate_change_nb;
193 u32 quirks;
194};
195struct cdns_platform_data {
196 u32 quirks;
197};
198#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
199 clk_rate_change_nb);
200
201/**
202 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
203 * @dev_id: Id of the UART port
204 * @isrstatus: The interrupt status register value as read
205 * Return: None
206 */
207static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
208{
209 struct uart_port *port = (struct uart_port *)dev_id;
210 struct cdns_uart *cdns_uart = port->private_data;
211 unsigned int data;
212 unsigned int rxbs_status = 0;
213 unsigned int status_mask;
214 unsigned int framerrprocessed = 0;
215 char status = TTY_NORMAL;
216 bool is_rxbs_support;
217
218 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
219
220 while ((readl(port->membase + CDNS_UART_SR) &
221 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
222 if (is_rxbs_support)
223 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
224 data = readl(port->membase + CDNS_UART_FIFO);
225 port->icount.rx++;
226 /*
227 * There is no hardware break detection in Zynq, so we interpret
228 * framing error with all-zeros data as a break sequence.
229 * Most of the time, there's another non-zero byte at the
230 * end of the sequence.
231 */
232 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
233 if (!data) {
234 port->read_status_mask |= CDNS_UART_IXR_BRK;
235 framerrprocessed = 1;
236 continue;
237 }
238 }
239 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
240 port->icount.brk++;
241 status = TTY_BREAK;
242 if (uart_handle_break(port))
243 continue;
244 }
245
246 isrstatus &= port->read_status_mask;
247 isrstatus &= ~port->ignore_status_mask;
248 status_mask = port->read_status_mask;
249 status_mask &= ~port->ignore_status_mask;
250
251 if (data &&
252 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
253 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
254 port->icount.brk++;
255 if (uart_handle_break(port))
256 continue;
257 }
258
259 if (uart_handle_sysrq_char(port, data))
260 continue;
261
262 if (is_rxbs_support) {
263 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
264 && (status_mask & CDNS_UART_IXR_PARITY)) {
265 port->icount.parity++;
266 status = TTY_PARITY;
267 }
268 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
269 && (status_mask & CDNS_UART_IXR_PARITY)) {
270 port->icount.frame++;
271 status = TTY_FRAME;
272 }
273 } else {
274 if (isrstatus & CDNS_UART_IXR_PARITY) {
275 port->icount.parity++;
276 status = TTY_PARITY;
277 }
278 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
279 !framerrprocessed) {
280 port->icount.frame++;
281 status = TTY_FRAME;
282 }
283 }
284 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
285 port->icount.overrun++;
286 tty_insert_flip_char(&port->state->port, 0,
287 TTY_OVERRUN);
288 }
289 tty_insert_flip_char(&port->state->port, data, status);
290 isrstatus = 0;
291 }
292 spin_unlock(&port->lock);
293 tty_flip_buffer_push(&port->state->port);
294 spin_lock(&port->lock);
295}
296
297/**
298 * cdns_uart_handle_tx - Handle the bytes to be Txed.
299 * @dev_id: Id of the UART port
300 * Return: None
301 */
302static void cdns_uart_handle_tx(void *dev_id)
303{
304 struct uart_port *port = (struct uart_port *)dev_id;
305 unsigned int numbytes;
306
307 if (uart_circ_empty(&port->state->xmit)) {
308 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
309 } else {
310 numbytes = port->fifosize;
311 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
312 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
313 /*
314 * Get the data from the UART circular buffer
315 * and write it to the cdns_uart's TX_FIFO
316 * register.
317 */
318 writel(
319 port->state->xmit.buf[port->state->xmit.
320 tail], port->membase + CDNS_UART_FIFO);
321
322 port->icount.tx++;
323
324 /*
325 * Adjust the tail of the UART buffer and wrap
326 * the buffer if it reaches limit.
327 */
328 port->state->xmit.tail =
329 (port->state->xmit.tail + 1) &
330 (UART_XMIT_SIZE - 1);
331
332 numbytes--;
333 }
334
335 if (uart_circ_chars_pending(
336 &port->state->xmit) < WAKEUP_CHARS)
337 uart_write_wakeup(port);
338 }
339}
340
341/**
342 * cdns_uart_isr - Interrupt handler
343 * @irq: Irq number
344 * @dev_id: Id of the port
345 *
346 * Return: IRQHANDLED
347 */
348static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
349{
350 struct uart_port *port = (struct uart_port *)dev_id;
351 unsigned int isrstatus;
352
353 spin_lock(&port->lock);
354
355 /* Read the interrupt status register to determine which
356 * interrupt(s) is/are active and clear them.
357 */
358 isrstatus = readl(port->membase + CDNS_UART_ISR);
359 writel(isrstatus, port->membase + CDNS_UART_ISR);
360
361 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
362 cdns_uart_handle_tx(dev_id);
363 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
364 }
365 if (isrstatus & CDNS_UART_IXR_MASK)
366 cdns_uart_handle_rx(dev_id, isrstatus);
367
368 spin_unlock(&port->lock);
369 return IRQ_HANDLED;
370}
371
372/**
373 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
374 * @clk: UART module input clock
375 * @baud: Desired baud rate
376 * @rbdiv: BDIV value (return value)
377 * @rcd: CD value (return value)
378 * @div8: Value for clk_sel bit in mod (return value)
379 * Return: baud rate, requested baud when possible, or actual baud when there
380 * was too much error, zero if no valid divisors are found.
381 *
382 * Formula to obtain baud rate is
383 * baud_tx/rx rate = clk/CD * (BDIV + 1)
384 * input_clk = (Uart User Defined Clock or Apb Clock)
385 * depends on UCLKEN in MR Reg
386 * clk = input_clk or input_clk/8;
387 * depends on CLKS in MR reg
388 * CD and BDIV depends on values in
389 * baud rate generate register
390 * baud rate clock divisor register
391 */
392static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
393 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
394{
395 u32 cd, bdiv;
396 unsigned int calc_baud;
397 unsigned int bestbaud = 0;
398 unsigned int bauderror;
399 unsigned int besterror = ~0;
400
401 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
402 *div8 = 1;
403 clk /= 8;
404 } else {
405 *div8 = 0;
406 }
407
408 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
409 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
410 if (cd < 1 || cd > CDNS_UART_CD_MAX)
411 continue;
412
413 calc_baud = clk / (cd * (bdiv + 1));
414
415 if (baud > calc_baud)
416 bauderror = baud - calc_baud;
417 else
418 bauderror = calc_baud - baud;
419
420 if (besterror > bauderror) {
421 *rbdiv = bdiv;
422 *rcd = cd;
423 bestbaud = calc_baud;
424 besterror = bauderror;
425 }
426 }
427 /* use the values when percent error is acceptable */
428 if (((besterror * 100) / baud) < 3)
429 bestbaud = baud;
430
431 return bestbaud;
432}
433
434/**
435 * cdns_uart_set_baud_rate - Calculate and set the baud rate
436 * @port: Handle to the uart port structure
437 * @baud: Baud rate to set
438 * Return: baud rate, requested baud when possible, or actual baud when there
439 * was too much error, zero if no valid divisors are found.
440 */
441static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
442 unsigned int baud)
443{
444 unsigned int calc_baud;
445 u32 cd = 0, bdiv = 0;
446 u32 mreg;
447 int div8;
448 struct cdns_uart *cdns_uart = port->private_data;
449
450 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
451 &div8);
452
453 /* Write new divisors to hardware */
454 mreg = readl(port->membase + CDNS_UART_MR);
455 if (div8)
456 mreg |= CDNS_UART_MR_CLKSEL;
457 else
458 mreg &= ~CDNS_UART_MR_CLKSEL;
459 writel(mreg, port->membase + CDNS_UART_MR);
460 writel(cd, port->membase + CDNS_UART_BAUDGEN);
461 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
462 cdns_uart->baud = baud;
463
464 return calc_baud;
465}
466
467#ifdef CONFIG_COMMON_CLK
468/**
469 * cdns_uart_clk_notitifer_cb - Clock notifier callback
470 * @nb: Notifier block
471 * @event: Notify event
472 * @data: Notifier data
473 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
474 */
475static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
476 unsigned long event, void *data)
477{
478 u32 ctrl_reg;
479 struct uart_port *port;
480 int locked = 0;
481 struct clk_notifier_data *ndata = data;
482 unsigned long flags = 0;
483 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
484
485 port = cdns_uart->port;
486 if (port->suspended)
487 return NOTIFY_OK;
488
489 switch (event) {
490 case PRE_RATE_CHANGE:
491 {
492 u32 bdiv, cd;
493 int div8;
494
495 /*
496 * Find out if current baud-rate can be achieved with new clock
497 * frequency.
498 */
499 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
500 &bdiv, &cd, &div8)) {
501 dev_warn(port->dev, "clock rate change rejected\n");
502 return NOTIFY_BAD;
503 }
504
505 spin_lock_irqsave(&cdns_uart->port->lock, flags);
506
507 /* Disable the TX and RX to set baud rate */
508 ctrl_reg = readl(port->membase + CDNS_UART_CR);
509 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
510 writel(ctrl_reg, port->membase + CDNS_UART_CR);
511
512 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
513
514 return NOTIFY_OK;
515 }
516 case POST_RATE_CHANGE:
517 /*
518 * Set clk dividers to generate correct baud with new clock
519 * frequency.
520 */
521
522 spin_lock_irqsave(&cdns_uart->port->lock, flags);
523
524 locked = 1;
525 port->uartclk = ndata->new_rate;
526
527 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
528 cdns_uart->baud);
529 /* fall through */
530 case ABORT_RATE_CHANGE:
531 if (!locked)
532 spin_lock_irqsave(&cdns_uart->port->lock, flags);
533
534 /* Set TX/RX Reset */
535 ctrl_reg = readl(port->membase + CDNS_UART_CR);
536 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
537 writel(ctrl_reg, port->membase + CDNS_UART_CR);
538
539 while (readl(port->membase + CDNS_UART_CR) &
540 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
541 cpu_relax();
542
543 /*
544 * Clear the RX disable and TX disable bits and then set the TX
545 * enable bit and RX enable bit to enable the transmitter and
546 * receiver.
547 */
548 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
549 ctrl_reg = readl(port->membase + CDNS_UART_CR);
550 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
551 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
552 writel(ctrl_reg, port->membase + CDNS_UART_CR);
553
554 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
555
556 return NOTIFY_OK;
557 default:
558 return NOTIFY_DONE;
559 }
560}
561#endif
562
563/**
564 * cdns_uart_start_tx - Start transmitting bytes
565 * @port: Handle to the uart port structure
566 */
567static void cdns_uart_start_tx(struct uart_port *port)
568{
569 unsigned int status;
570
571 if (uart_tx_stopped(port))
572 return;
573
574 /*
575 * Set the TX enable bit and clear the TX disable bit to enable the
576 * transmitter.
577 */
578 status = readl(port->membase + CDNS_UART_CR);
579 status &= ~CDNS_UART_CR_TX_DIS;
580 status |= CDNS_UART_CR_TX_EN;
581 writel(status, port->membase + CDNS_UART_CR);
582
583 if (uart_circ_empty(&port->state->xmit))
584 return;
585
586 cdns_uart_handle_tx(port);
587
588 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
589 /* Enable the TX Empty interrupt */
590 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
591}
592
593/**
594 * cdns_uart_stop_tx - Stop TX
595 * @port: Handle to the uart port structure
596 */
597static void cdns_uart_stop_tx(struct uart_port *port)
598{
599 unsigned int regval;
600
601 regval = readl(port->membase + CDNS_UART_CR);
602 regval |= CDNS_UART_CR_TX_DIS;
603 /* Disable the transmitter */
604 writel(regval, port->membase + CDNS_UART_CR);
605}
606
607/**
608 * cdns_uart_stop_rx - Stop RX
609 * @port: Handle to the uart port structure
610 */
611static void cdns_uart_stop_rx(struct uart_port *port)
612{
613 unsigned int regval;
614
615 /* Disable RX IRQs */
616 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
617
618 /* Disable the receiver */
619 regval = readl(port->membase + CDNS_UART_CR);
620 regval |= CDNS_UART_CR_RX_DIS;
621 writel(regval, port->membase + CDNS_UART_CR);
622}
623
624/**
625 * cdns_uart_tx_empty - Check whether TX is empty
626 * @port: Handle to the uart port structure
627 *
628 * Return: TIOCSER_TEMT on success, 0 otherwise
629 */
630static unsigned int cdns_uart_tx_empty(struct uart_port *port)
631{
632 unsigned int status;
633
634 status = readl(port->membase + CDNS_UART_SR) &
635 CDNS_UART_SR_TXEMPTY;
636 return status ? TIOCSER_TEMT : 0;
637}
638
639/**
640 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
641 * transmitting char breaks
642 * @port: Handle to the uart port structure
643 * @ctl: Value based on which start or stop decision is taken
644 */
645static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
646{
647 unsigned int status;
648 unsigned long flags;
649
650 spin_lock_irqsave(&port->lock, flags);
651
652 status = readl(port->membase + CDNS_UART_CR);
653
654 if (ctl == -1)
655 writel(CDNS_UART_CR_STARTBRK | status,
656 port->membase + CDNS_UART_CR);
657 else {
658 if ((status & CDNS_UART_CR_STOPBRK) == 0)
659 writel(CDNS_UART_CR_STOPBRK | status,
660 port->membase + CDNS_UART_CR);
661 }
662 spin_unlock_irqrestore(&port->lock, flags);
663}
664
665/**
666 * cdns_uart_set_termios - termios operations, handling data length, parity,
667 * stop bits, flow control, baud rate
668 * @port: Handle to the uart port structure
669 * @termios: Handle to the input termios structure
670 * @old: Values of the previously saved termios structure
671 */
672static void cdns_uart_set_termios(struct uart_port *port,
673 struct ktermios *termios, struct ktermios *old)
674{
675 unsigned int cval = 0;
676 unsigned int baud, minbaud, maxbaud;
677 unsigned long flags;
678 unsigned int ctrl_reg, mode_reg;
679
680 spin_lock_irqsave(&port->lock, flags);
681
682 /* Wait for the transmit FIFO to empty before making changes */
683 if (!(readl(port->membase + CDNS_UART_CR) &
684 CDNS_UART_CR_TX_DIS)) {
685 while (!(readl(port->membase + CDNS_UART_SR) &
686 CDNS_UART_SR_TXEMPTY)) {
687 cpu_relax();
688 }
689 }
690
691 /* Disable the TX and RX to set baud rate */
692 ctrl_reg = readl(port->membase + CDNS_UART_CR);
693 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
694 writel(ctrl_reg, port->membase + CDNS_UART_CR);
695
696 /*
697 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
698 * min and max baud should be calculated here based on port->uartclk.
699 * this way we get a valid baud and can safely call set_baud()
700 */
701 minbaud = port->uartclk /
702 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
703 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
704 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
705 baud = cdns_uart_set_baud_rate(port, baud);
706 if (tty_termios_baud_rate(termios))
707 tty_termios_encode_baud_rate(termios, baud, baud);
708
709 /* Update the per-port timeout. */
710 uart_update_timeout(port, termios->c_cflag, baud);
711
712 /* Set TX/RX Reset */
713 ctrl_reg = readl(port->membase + CDNS_UART_CR);
714 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
715 writel(ctrl_reg, port->membase + CDNS_UART_CR);
716
717 while (readl(port->membase + CDNS_UART_CR) &
718 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
719 cpu_relax();
720
721 /*
722 * Clear the RX disable and TX disable bits and then set the TX enable
723 * bit and RX enable bit to enable the transmitter and receiver.
724 */
725 ctrl_reg = readl(port->membase + CDNS_UART_CR);
726 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
727 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
728 writel(ctrl_reg, port->membase + CDNS_UART_CR);
729
730 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
731
732 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
733 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
734 port->ignore_status_mask = 0;
735
736 if (termios->c_iflag & INPCK)
737 port->read_status_mask |= CDNS_UART_IXR_PARITY |
738 CDNS_UART_IXR_FRAMING;
739
740 if (termios->c_iflag & IGNPAR)
741 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
742 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
743
744 /* ignore all characters if CREAD is not set */
745 if ((termios->c_cflag & CREAD) == 0)
746 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
747 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
748 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
749
750 mode_reg = readl(port->membase + CDNS_UART_MR);
751
752 /* Handling Data Size */
753 switch (termios->c_cflag & CSIZE) {
754 case CS6:
755 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
756 break;
757 case CS7:
758 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
759 break;
760 default:
761 case CS8:
762 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
763 termios->c_cflag &= ~CSIZE;
764 termios->c_cflag |= CS8;
765 break;
766 }
767
768 /* Handling Parity and Stop Bits length */
769 if (termios->c_cflag & CSTOPB)
770 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
771 else
772 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
773
774 if (termios->c_cflag & PARENB) {
775 /* Mark or Space parity */
776 if (termios->c_cflag & CMSPAR) {
777 if (termios->c_cflag & PARODD)
778 cval |= CDNS_UART_MR_PARITY_MARK;
779 else
780 cval |= CDNS_UART_MR_PARITY_SPACE;
781 } else {
782 if (termios->c_cflag & PARODD)
783 cval |= CDNS_UART_MR_PARITY_ODD;
784 else
785 cval |= CDNS_UART_MR_PARITY_EVEN;
786 }
787 } else {
788 cval |= CDNS_UART_MR_PARITY_NONE;
789 }
790 cval |= mode_reg & 1;
791 writel(cval, port->membase + CDNS_UART_MR);
792
793 spin_unlock_irqrestore(&port->lock, flags);
794}
795
796/**
797 * cdns_uart_startup - Called when an application opens a cdns_uart port
798 * @port: Handle to the uart port structure
799 *
800 * Return: 0 on success, negative errno otherwise
801 */
802static int cdns_uart_startup(struct uart_port *port)
803{
804 struct cdns_uart *cdns_uart = port->private_data;
805 bool is_brk_support;
806 int ret;
807 unsigned long flags;
808 unsigned int status = 0;
809
810 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
811
812 spin_lock_irqsave(&port->lock, flags);
813
814 /* Disable the TX and RX */
815 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
816 port->membase + CDNS_UART_CR);
817
818 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
819 * no break chars.
820 */
821 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
822 port->membase + CDNS_UART_CR);
823
824 while (readl(port->membase + CDNS_UART_CR) &
825 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
826 cpu_relax();
827
828 /*
829 * Clear the RX disable bit and then set the RX enable bit to enable
830 * the receiver.
831 */
832 status = readl(port->membase + CDNS_UART_CR);
833 status &= CDNS_UART_CR_RX_DIS;
834 status |= CDNS_UART_CR_RX_EN;
835 writel(status, port->membase + CDNS_UART_CR);
836
837 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
838 * no parity.
839 */
840 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
841 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
842 port->membase + CDNS_UART_MR);
843
844 /*
845 * Set the RX FIFO Trigger level to use most of the FIFO, but it
846 * can be tuned with a module parameter
847 */
848 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
849
850 /*
851 * Receive Timeout register is enabled but it
852 * can be tuned with a module parameter
853 */
854 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
855
856 /* Clear out any pending interrupts before enabling them */
857 writel(readl(port->membase + CDNS_UART_ISR),
858 port->membase + CDNS_UART_ISR);
859
860 spin_unlock_irqrestore(&port->lock, flags);
861
862 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
863 if (ret) {
864 dev_err(port->dev, "request_irq '%d' failed with %d\n",
865 port->irq, ret);
866 return ret;
867 }
868
869 /* Set the Interrupt Registers with desired interrupts */
870 if (is_brk_support)
871 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
872 port->membase + CDNS_UART_IER);
873 else
874 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
875
876 return 0;
877}
878
879/**
880 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
881 * @port: Handle to the uart port structure
882 */
883static void cdns_uart_shutdown(struct uart_port *port)
884{
885 int status;
886 unsigned long flags;
887
888 spin_lock_irqsave(&port->lock, flags);
889
890 /* Disable interrupts */
891 status = readl(port->membase + CDNS_UART_IMR);
892 writel(status, port->membase + CDNS_UART_IDR);
893 writel(0xffffffff, port->membase + CDNS_UART_ISR);
894
895 /* Disable the TX and RX */
896 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
897 port->membase + CDNS_UART_CR);
898
899 spin_unlock_irqrestore(&port->lock, flags);
900
901 free_irq(port->irq, port);
902}
903
904/**
905 * cdns_uart_type - Set UART type to cdns_uart port
906 * @port: Handle to the uart port structure
907 *
908 * Return: string on success, NULL otherwise
909 */
910static const char *cdns_uart_type(struct uart_port *port)
911{
912 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
913}
914
915/**
916 * cdns_uart_verify_port - Verify the port params
917 * @port: Handle to the uart port structure
918 * @ser: Handle to the structure whose members are compared
919 *
920 * Return: 0 on success, negative errno otherwise.
921 */
922static int cdns_uart_verify_port(struct uart_port *port,
923 struct serial_struct *ser)
924{
925 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
926 return -EINVAL;
927 if (port->irq != ser->irq)
928 return -EINVAL;
929 if (ser->io_type != UPIO_MEM)
930 return -EINVAL;
931 if (port->iobase != ser->port)
932 return -EINVAL;
933 if (ser->hub6 != 0)
934 return -EINVAL;
935 return 0;
936}
937
938/**
939 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
940 * called when the driver adds a cdns_uart port via
941 * uart_add_one_port()
942 * @port: Handle to the uart port structure
943 *
944 * Return: 0 on success, negative errno otherwise.
945 */
946static int cdns_uart_request_port(struct uart_port *port)
947{
948 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
949 CDNS_UART_NAME)) {
950 return -ENOMEM;
951 }
952
953 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
954 if (!port->membase) {
955 dev_err(port->dev, "Unable to map registers\n");
956 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
957 return -ENOMEM;
958 }
959 return 0;
960}
961
962/**
963 * cdns_uart_release_port - Release UART port
964 * @port: Handle to the uart port structure
965 *
966 * Release the memory region attached to a cdns_uart port. Called when the
967 * driver removes a cdns_uart port via uart_remove_one_port().
968 */
969static void cdns_uart_release_port(struct uart_port *port)
970{
971 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
972 iounmap(port->membase);
973 port->membase = NULL;
974}
975
976/**
977 * cdns_uart_config_port - Configure UART port
978 * @port: Handle to the uart port structure
979 * @flags: If any
980 */
981static void cdns_uart_config_port(struct uart_port *port, int flags)
982{
983 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
984 port->type = PORT_XUARTPS;
985}
986
987/**
988 * cdns_uart_get_mctrl - Get the modem control state
989 * @port: Handle to the uart port structure
990 *
991 * Return: the modem control state
992 */
993static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
994{
995 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
996}
997
998static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
999{
1000 u32 val;
1001
1002 val = readl(port->membase + CDNS_UART_MODEMCR);
1003
1004 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1005
1006 if (mctrl & TIOCM_RTS)
1007 val |= CDNS_UART_MODEMCR_RTS;
1008 if (mctrl & TIOCM_DTR)
1009 val |= CDNS_UART_MODEMCR_DTR;
1010
1011 writel(val, port->membase + CDNS_UART_MODEMCR);
1012}
1013
1014#ifdef CONFIG_CONSOLE_POLL
1015static int cdns_uart_poll_get_char(struct uart_port *port)
1016{
1017 int c;
1018 unsigned long flags;
1019
1020 spin_lock_irqsave(&port->lock, flags);
1021
1022 /* Check if FIFO is empty */
1023 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1024 c = NO_POLL_CHAR;
1025 else /* Read a character */
1026 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1027
1028 spin_unlock_irqrestore(&port->lock, flags);
1029
1030 return c;
1031}
1032
1033static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1034{
1035 unsigned long flags;
1036
1037 spin_lock_irqsave(&port->lock, flags);
1038
1039 /* Wait until FIFO is empty */
1040 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1041 cpu_relax();
1042
1043 /* Write a character */
1044 writel(c, port->membase + CDNS_UART_FIFO);
1045
1046 /* Wait until FIFO is empty */
1047 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1048 cpu_relax();
1049
1050 spin_unlock_irqrestore(&port->lock, flags);
1051
1052 return;
1053}
1054#endif
1055
1056static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1057 unsigned int oldstate)
1058{
1059 struct cdns_uart *cdns_uart = port->private_data;
1060
1061 switch (state) {
1062 case UART_PM_STATE_OFF:
1063 clk_disable(cdns_uart->uartclk);
1064 clk_disable(cdns_uart->pclk);
1065 break;
1066 default:
1067 clk_enable(cdns_uart->pclk);
1068 clk_enable(cdns_uart->uartclk);
1069 break;
1070 }
1071}
1072
1073static const struct uart_ops cdns_uart_ops = {
1074 .set_mctrl = cdns_uart_set_mctrl,
1075 .get_mctrl = cdns_uart_get_mctrl,
1076 .start_tx = cdns_uart_start_tx,
1077 .stop_tx = cdns_uart_stop_tx,
1078 .stop_rx = cdns_uart_stop_rx,
1079 .tx_empty = cdns_uart_tx_empty,
1080 .break_ctl = cdns_uart_break_ctl,
1081 .set_termios = cdns_uart_set_termios,
1082 .startup = cdns_uart_startup,
1083 .shutdown = cdns_uart_shutdown,
1084 .pm = cdns_uart_pm,
1085 .type = cdns_uart_type,
1086 .verify_port = cdns_uart_verify_port,
1087 .request_port = cdns_uart_request_port,
1088 .release_port = cdns_uart_release_port,
1089 .config_port = cdns_uart_config_port,
1090#ifdef CONFIG_CONSOLE_POLL
1091 .poll_get_char = cdns_uart_poll_get_char,
1092 .poll_put_char = cdns_uart_poll_put_char,
1093#endif
1094};
1095
1096static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1097
1098/**
1099 * cdns_uart_get_port - Configure the port from platform device resource info
1100 * @id: Port id
1101 *
1102 * Return: a pointer to a uart_port or NULL for failure
1103 */
1104static struct uart_port *cdns_uart_get_port(int id)
1105{
1106 struct uart_port *port;
1107
1108 /* Try the given port id if failed use default method */
1109 if (cdns_uart_port[id].mapbase != 0) {
1110 /* Find the next unused port */
1111 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1112 if (cdns_uart_port[id].mapbase == 0)
1113 break;
1114 }
1115
1116 if (id >= CDNS_UART_NR_PORTS)
1117 return NULL;
1118
1119 port = &cdns_uart_port[id];
1120
1121 /* At this point, we've got an empty uart_port struct, initialize it */
1122 spin_lock_init(&port->lock);
1123 port->membase = NULL;
1124 port->irq = 0;
1125 port->type = PORT_UNKNOWN;
1126 port->iotype = UPIO_MEM32;
1127 port->flags = UPF_BOOT_AUTOCONF;
1128 port->ops = &cdns_uart_ops;
1129 port->fifosize = CDNS_UART_FIFO_SIZE;
1130 port->line = id;
1131 port->dev = NULL;
1132 return port;
1133}
1134
1135#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1136/**
1137 * cdns_uart_console_wait_tx - Wait for the TX to be full
1138 * @port: Handle to the uart port structure
1139 */
1140static void cdns_uart_console_wait_tx(struct uart_port *port)
1141{
1142 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1143 barrier();
1144}
1145
1146/**
1147 * cdns_uart_console_putchar - write the character to the FIFO buffer
1148 * @port: Handle to the uart port structure
1149 * @ch: Character to be written
1150 */
1151static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1152{
1153 cdns_uart_console_wait_tx(port);
1154 writel(ch, port->membase + CDNS_UART_FIFO);
1155}
1156
1157static void __init cdns_early_write(struct console *con, const char *s,
1158 unsigned n)
1159{
1160 struct earlycon_device *dev = con->data;
1161
1162 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1163}
1164
1165static int __init cdns_early_console_setup(struct earlycon_device *device,
1166 const char *opt)
1167{
1168 struct uart_port *port = &device->port;
1169
1170 if (!port->membase)
1171 return -ENODEV;
1172
1173 /* initialise control register */
1174 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1175 port->membase + CDNS_UART_CR);
1176
1177 /* only set baud if specified on command line - otherwise
1178 * assume it has been initialized by a boot loader.
1179 */
1180 if (device->baud) {
1181 u32 cd = 0, bdiv = 0;
1182 u32 mr;
1183 int div8;
1184
1185 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1186 &bdiv, &cd, &div8);
1187 mr = CDNS_UART_MR_PARITY_NONE;
1188 if (div8)
1189 mr |= CDNS_UART_MR_CLKSEL;
1190
1191 writel(mr, port->membase + CDNS_UART_MR);
1192 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1193 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1194 }
1195
1196 device->con->write = cdns_early_write;
1197
1198 return 0;
1199}
1200OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1201OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1202OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1203OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1204
1205/**
1206 * cdns_uart_console_write - perform write operation
1207 * @co: Console handle
1208 * @s: Pointer to character array
1209 * @count: No of characters
1210 */
1211static void cdns_uart_console_write(struct console *co, const char *s,
1212 unsigned int count)
1213{
1214 struct uart_port *port = &cdns_uart_port[co->index];
1215 unsigned long flags;
1216 unsigned int imr, ctrl;
1217 int locked = 1;
1218
1219 if (port->sysrq)
1220 locked = 0;
1221 else if (oops_in_progress)
1222 locked = spin_trylock_irqsave(&port->lock, flags);
1223 else
1224 spin_lock_irqsave(&port->lock, flags);
1225
1226 /* save and disable interrupt */
1227 imr = readl(port->membase + CDNS_UART_IMR);
1228 writel(imr, port->membase + CDNS_UART_IDR);
1229
1230 /*
1231 * Make sure that the tx part is enabled. Set the TX enable bit and
1232 * clear the TX disable bit to enable the transmitter.
1233 */
1234 ctrl = readl(port->membase + CDNS_UART_CR);
1235 ctrl &= ~CDNS_UART_CR_TX_DIS;
1236 ctrl |= CDNS_UART_CR_TX_EN;
1237 writel(ctrl, port->membase + CDNS_UART_CR);
1238
1239 uart_console_write(port, s, count, cdns_uart_console_putchar);
1240 cdns_uart_console_wait_tx(port);
1241
1242 writel(ctrl, port->membase + CDNS_UART_CR);
1243
1244 /* restore interrupt state */
1245 writel(imr, port->membase + CDNS_UART_IER);
1246
1247 if (locked)
1248 spin_unlock_irqrestore(&port->lock, flags);
1249}
1250
1251/**
1252 * cdns_uart_console_setup - Initialize the uart to default config
1253 * @co: Console handle
1254 * @options: Initial settings of uart
1255 *
1256 * Return: 0 on success, negative errno otherwise.
1257 */
1258static int __init cdns_uart_console_setup(struct console *co, char *options)
1259{
1260 struct uart_port *port = &cdns_uart_port[co->index];
1261 int baud = 9600;
1262 int bits = 8;
1263 int parity = 'n';
1264 int flow = 'n';
1265
1266 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1267 return -EINVAL;
1268
1269 if (!port->membase) {
1270 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1271 co->index);
1272 return -ENODEV;
1273 }
1274
1275 if (options)
1276 uart_parse_options(options, &baud, &parity, &bits, &flow);
1277
1278 return uart_set_options(port, co, baud, parity, bits, flow);
1279}
1280
1281static struct uart_driver cdns_uart_uart_driver;
1282
1283static struct console cdns_uart_console = {
1284 .name = CDNS_UART_TTY_NAME,
1285 .write = cdns_uart_console_write,
1286 .device = uart_console_device,
1287 .setup = cdns_uart_console_setup,
1288 .flags = CON_PRINTBUFFER,
1289 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1290 .data = &cdns_uart_uart_driver,
1291};
1292
1293/**
1294 * cdns_uart_console_init - Initialization call
1295 *
1296 * Return: 0 on success, negative errno otherwise
1297 */
1298static int __init cdns_uart_console_init(void)
1299{
1300 register_console(&cdns_uart_console);
1301 return 0;
1302}
1303
1304console_initcall(cdns_uart_console_init);
1305
1306#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1307
1308static struct uart_driver cdns_uart_uart_driver = {
1309 .owner = THIS_MODULE,
1310 .driver_name = CDNS_UART_NAME,
1311 .dev_name = CDNS_UART_TTY_NAME,
1312 .major = CDNS_UART_MAJOR,
1313 .minor = CDNS_UART_MINOR,
1314 .nr = CDNS_UART_NR_PORTS,
1315#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1316 .cons = &cdns_uart_console,
1317#endif
1318};
1319
1320#ifdef CONFIG_PM_SLEEP
1321/**
1322 * cdns_uart_suspend - suspend event
1323 * @device: Pointer to the device structure
1324 *
1325 * Return: 0
1326 */
1327static int cdns_uart_suspend(struct device *device)
1328{
1329 struct uart_port *port = dev_get_drvdata(device);
1330 struct tty_struct *tty;
1331 struct device *tty_dev;
1332 int may_wake = 0;
1333
1334 /* Get the tty which could be NULL so don't assume it's valid */
1335 tty = tty_port_tty_get(&port->state->port);
1336 if (tty) {
1337 tty_dev = tty->dev;
1338 may_wake = device_may_wakeup(tty_dev);
1339 tty_kref_put(tty);
1340 }
1341
1342 /*
1343 * Call the API provided in serial_core.c file which handles
1344 * the suspend.
1345 */
1346 uart_suspend_port(&cdns_uart_uart_driver, port);
1347 if (console_suspend_enabled && !may_wake) {
1348 struct cdns_uart *cdns_uart = port->private_data;
1349
1350 clk_disable(cdns_uart->uartclk);
1351 clk_disable(cdns_uart->pclk);
1352 } else {
1353 unsigned long flags = 0;
1354
1355 spin_lock_irqsave(&port->lock, flags);
1356 /* Empty the receive FIFO 1st before making changes */
1357 while (!(readl(port->membase + CDNS_UART_SR) &
1358 CDNS_UART_SR_RXEMPTY))
1359 readl(port->membase + CDNS_UART_FIFO);
1360 /* set RX trigger level to 1 */
1361 writel(1, port->membase + CDNS_UART_RXWM);
1362 /* disable RX timeout interrups */
1363 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1364 spin_unlock_irqrestore(&port->lock, flags);
1365 }
1366
1367 return 0;
1368}
1369
1370/**
1371 * cdns_uart_resume - Resume after a previous suspend
1372 * @device: Pointer to the device structure
1373 *
1374 * Return: 0
1375 */
1376static int cdns_uart_resume(struct device *device)
1377{
1378 struct uart_port *port = dev_get_drvdata(device);
1379 unsigned long flags = 0;
1380 u32 ctrl_reg;
1381 struct tty_struct *tty;
1382 struct device *tty_dev;
1383 int may_wake = 0;
1384
1385 /* Get the tty which could be NULL so don't assume it's valid */
1386 tty = tty_port_tty_get(&port->state->port);
1387 if (tty) {
1388 tty_dev = tty->dev;
1389 may_wake = device_may_wakeup(tty_dev);
1390 tty_kref_put(tty);
1391 }
1392
1393 if (console_suspend_enabled && !may_wake) {
1394 struct cdns_uart *cdns_uart = port->private_data;
1395
1396 clk_enable(cdns_uart->pclk);
1397 clk_enable(cdns_uart->uartclk);
1398
1399 spin_lock_irqsave(&port->lock, flags);
1400
1401 /* Set TX/RX Reset */
1402 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1403 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1404 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1405 while (readl(port->membase + CDNS_UART_CR) &
1406 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1407 cpu_relax();
1408
1409 /* restore rx timeout value */
1410 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1411 /* Enable Tx/Rx */
1412 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1413 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1414 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1415 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1416
1417 spin_unlock_irqrestore(&port->lock, flags);
1418 } else {
1419 spin_lock_irqsave(&port->lock, flags);
1420 /* restore original rx trigger level */
1421 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1422 /* enable RX timeout interrupt */
1423 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1424 spin_unlock_irqrestore(&port->lock, flags);
1425 }
1426
1427 return uart_resume_port(&cdns_uart_uart_driver, port);
1428}
1429#endif /* ! CONFIG_PM_SLEEP */
1430
1431static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1432 cdns_uart_resume);
1433
1434static const struct cdns_platform_data zynqmp_uart_def = {
1435 .quirks = CDNS_UART_RXBS_SUPPORT, };
1436
1437/* Match table for of_platform binding */
1438static const struct of_device_id cdns_uart_of_match[] = {
1439 { .compatible = "xlnx,xuartps", },
1440 { .compatible = "cdns,uart-r1p8", },
1441 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1442 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1443 {}
1444};
1445MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1446
1447/**
1448 * cdns_uart_probe - Platform driver probe
1449 * @pdev: Pointer to the platform device structure
1450 *
1451 * Return: 0 on success, negative errno otherwise
1452 */
1453static int cdns_uart_probe(struct platform_device *pdev)
1454{
1455 int rc, id, irq;
1456 struct uart_port *port;
1457 struct resource *res;
1458 struct cdns_uart *cdns_uart_data;
1459 const struct of_device_id *match;
1460
1461 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1462 GFP_KERNEL);
1463 if (!cdns_uart_data)
1464 return -ENOMEM;
1465
1466 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1467 if (match && match->data) {
1468 const struct cdns_platform_data *data = match->data;
1469
1470 cdns_uart_data->quirks = data->quirks;
1471 }
1472
1473 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1474 if (IS_ERR(cdns_uart_data->pclk)) {
1475 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1476 if (!IS_ERR(cdns_uart_data->pclk))
1477 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1478 }
1479 if (IS_ERR(cdns_uart_data->pclk)) {
1480 dev_err(&pdev->dev, "pclk clock not found.\n");
1481 return PTR_ERR(cdns_uart_data->pclk);
1482 }
1483
1484 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1485 if (IS_ERR(cdns_uart_data->uartclk)) {
1486 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1487 if (!IS_ERR(cdns_uart_data->uartclk))
1488 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1489 }
1490 if (IS_ERR(cdns_uart_data->uartclk)) {
1491 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1492 return PTR_ERR(cdns_uart_data->uartclk);
1493 }
1494
1495 rc = clk_prepare(cdns_uart_data->pclk);
1496 if (rc) {
1497 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1498 return rc;
1499 }
1500 rc = clk_prepare(cdns_uart_data->uartclk);
1501 if (rc) {
1502 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1503 goto err_out_clk_dis_pclk;
1504 }
1505
1506 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1507 if (!res) {
1508 rc = -ENODEV;
1509 goto err_out_clk_disable;
1510 }
1511
1512 irq = platform_get_irq(pdev, 0);
1513 if (irq <= 0) {
1514 rc = -ENXIO;
1515 goto err_out_clk_disable;
1516 }
1517
1518#ifdef CONFIG_COMMON_CLK
1519 cdns_uart_data->clk_rate_change_nb.notifier_call =
1520 cdns_uart_clk_notifier_cb;
1521 if (clk_notifier_register(cdns_uart_data->uartclk,
1522 &cdns_uart_data->clk_rate_change_nb))
1523 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1524#endif
1525 /* Look for a serialN alias */
1526 id = of_alias_get_id(pdev->dev.of_node, "serial");
1527 if (id < 0)
1528 id = 0;
1529
1530 /* Initialize the port structure */
1531 port = cdns_uart_get_port(id);
1532
1533 if (!port) {
1534 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1535 rc = -ENODEV;
1536 goto err_out_notif_unreg;
1537 }
1538
1539 /*
1540 * Register the port.
1541 * This function also registers this device with the tty layer
1542 * and triggers invocation of the config_port() entry point.
1543 */
1544 port->mapbase = res->start;
1545 port->irq = irq;
1546 port->dev = &pdev->dev;
1547 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1548 port->private_data = cdns_uart_data;
1549 cdns_uart_data->port = port;
1550 platform_set_drvdata(pdev, port);
1551
1552 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1553 if (rc) {
1554 dev_err(&pdev->dev,
1555 "uart_add_one_port() failed; err=%i\n", rc);
1556 goto err_out_notif_unreg;
1557 }
1558
1559 return 0;
1560
1561err_out_notif_unreg:
1562#ifdef CONFIG_COMMON_CLK
1563 clk_notifier_unregister(cdns_uart_data->uartclk,
1564 &cdns_uart_data->clk_rate_change_nb);
1565#endif
1566err_out_clk_disable:
1567 clk_unprepare(cdns_uart_data->uartclk);
1568err_out_clk_dis_pclk:
1569 clk_unprepare(cdns_uart_data->pclk);
1570
1571 return rc;
1572}
1573
1574/**
1575 * cdns_uart_remove - called when the platform driver is unregistered
1576 * @pdev: Pointer to the platform device structure
1577 *
1578 * Return: 0 on success, negative errno otherwise
1579 */
1580static int cdns_uart_remove(struct platform_device *pdev)
1581{
1582 struct uart_port *port = platform_get_drvdata(pdev);
1583 struct cdns_uart *cdns_uart_data = port->private_data;
1584 int rc;
1585
1586 /* Remove the cdns_uart port from the serial core */
1587#ifdef CONFIG_COMMON_CLK
1588 clk_notifier_unregister(cdns_uart_data->uartclk,
1589 &cdns_uart_data->clk_rate_change_nb);
1590#endif
1591 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1592 port->mapbase = 0;
1593 clk_unprepare(cdns_uart_data->uartclk);
1594 clk_unprepare(cdns_uart_data->pclk);
1595 return rc;
1596}
1597
1598static struct platform_driver cdns_uart_platform_driver = {
1599 .probe = cdns_uart_probe,
1600 .remove = cdns_uart_remove,
1601 .driver = {
1602 .name = CDNS_UART_NAME,
1603 .of_match_table = cdns_uart_of_match,
1604 .pm = &cdns_uart_dev_pm_ops,
1605 },
1606};
1607
1608static int __init cdns_uart_init(void)
1609{
1610 int retval = 0;
1611
1612 /* Register the cdns_uart driver with the serial core */
1613 retval = uart_register_driver(&cdns_uart_uart_driver);
1614 if (retval)
1615 return retval;
1616
1617 /* Register the platform driver */
1618 retval = platform_driver_register(&cdns_uart_platform_driver);
1619 if (retval)
1620 uart_unregister_driver(&cdns_uart_uart_driver);
1621
1622 return retval;
1623}
1624
1625static void __exit cdns_uart_exit(void)
1626{
1627 /* Unregister the platform driver */
1628 platform_driver_unregister(&cdns_uart_platform_driver);
1629
1630 /* Unregister the cdns_uart driver */
1631 uart_unregister_driver(&cdns_uart_uart_driver);
1632}
1633
1634module_init(cdns_uart_init);
1635module_exit(cdns_uart_exit);
1636
1637MODULE_DESCRIPTION("Driver for Cadence UART");
1638MODULE_AUTHOR("Xilinx Inc.");
1639MODULE_LICENSE("GPL");