1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
   4 * Author: Jon Ringle <jringle@gridpoint.com>
   5 *
   6 *  Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
 
 
 
 
 
 
   7 */
   8
   9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11#include <linux/bitops.h>
  12#include <linux/clk.h>
  13#include <linux/delay.h>
  14#include <linux/device.h>
  15#include <linux/gpio/driver.h>
  16#include <linux/i2c.h>
  17#include <linux/mod_devicetable.h>
  18#include <linux/module.h>
  19#include <linux/property.h>
 
  20#include <linux/regmap.h>
  21#include <linux/sched.h>
  22#include <linux/serial_core.h>
  23#include <linux/serial.h>
  24#include <linux/tty.h>
  25#include <linux/tty_flip.h>
  26#include <linux/spi/spi.h>
  27#include <linux/uaccess.h>
  28#include <linux/units.h>
  29
  30#define SC16IS7XX_NAME			"sc16is7xx"
  31#define SC16IS7XX_MAX_DEVS		8
  32#define SC16IS7XX_MAX_PORTS		2 /* Maximum number of UART ports per IC. */
  33
  34/* SC16IS7XX register definitions */
  35#define SC16IS7XX_RHR_REG		(0x00) /* RX FIFO */
  36#define SC16IS7XX_THR_REG		(0x00) /* TX FIFO */
  37#define SC16IS7XX_IER_REG		(0x01) /* Interrupt enable */
  38#define SC16IS7XX_IIR_REG		(0x02) /* Interrupt Identification */
  39#define SC16IS7XX_FCR_REG		(0x02) /* FIFO control */
  40#define SC16IS7XX_LCR_REG		(0x03) /* Line Control */
  41#define SC16IS7XX_MCR_REG		(0x04) /* Modem Control */
  42#define SC16IS7XX_LSR_REG		(0x05) /* Line Status */
  43#define SC16IS7XX_MSR_REG		(0x06) /* Modem Status */
  44#define SC16IS7XX_SPR_REG		(0x07) /* Scratch Pad */
  45#define SC16IS7XX_TXLVL_REG		(0x08) /* TX FIFO level */
  46#define SC16IS7XX_RXLVL_REG		(0x09) /* RX FIFO level */
  47#define SC16IS7XX_IODIR_REG		(0x0a) /* I/O Direction
  48						* - only on 75x/76x
  49						*/
  50#define SC16IS7XX_IOSTATE_REG		(0x0b) /* I/O State
  51						* - only on 75x/76x
  52						*/
  53#define SC16IS7XX_IOINTENA_REG		(0x0c) /* I/O Interrupt Enable
  54						* - only on 75x/76x
  55						*/
  56#define SC16IS7XX_IOCONTROL_REG		(0x0e) /* I/O Control
  57						* - only on 75x/76x
  58						*/
  59#define SC16IS7XX_EFCR_REG		(0x0f) /* Extra Features Control */
  60
  61/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
  62#define SC16IS7XX_TCR_REG		(0x06) /* Transmit control */
  63#define SC16IS7XX_TLR_REG		(0x07) /* Trigger level */
  64
  65/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
  66#define SC16IS7XX_DLL_REG		(0x00) /* Divisor Latch Low */
  67#define SC16IS7XX_DLH_REG		(0x01) /* Divisor Latch High */
  68
  69/* Enhanced Register set: Only if (LCR == 0xBF) */
  70#define SC16IS7XX_EFR_REG		(0x02) /* Enhanced Features */
  71#define SC16IS7XX_XON1_REG		(0x04) /* Xon1 word */
  72#define SC16IS7XX_XON2_REG		(0x05) /* Xon2 word */
  73#define SC16IS7XX_XOFF1_REG		(0x06) /* Xoff1 word */
  74#define SC16IS7XX_XOFF2_REG		(0x07) /* Xoff2 word */
  75
  76/* IER register bits */
  77#define SC16IS7XX_IER_RDI_BIT		(1 << 0) /* Enable RX data interrupt */
  78#define SC16IS7XX_IER_THRI_BIT		(1 << 1) /* Enable TX holding register
  79						  * interrupt */
  80#define SC16IS7XX_IER_RLSI_BIT		(1 << 2) /* Enable RX line status
  81						  * interrupt */
  82#define SC16IS7XX_IER_MSI_BIT		(1 << 3) /* Enable Modem status
  83						  * interrupt */
  84
  85/* IER register bits - write only if (EFR[4] == 1) */
  86#define SC16IS7XX_IER_SLEEP_BIT		(1 << 4) /* Enable Sleep mode */
  87#define SC16IS7XX_IER_XOFFI_BIT		(1 << 5) /* Enable Xoff interrupt */
  88#define SC16IS7XX_IER_RTSI_BIT		(1 << 6) /* Enable nRTS interrupt */
  89#define SC16IS7XX_IER_CTSI_BIT		(1 << 7) /* Enable nCTS interrupt */
  90
  91/* FCR register bits */
  92#define SC16IS7XX_FCR_FIFO_BIT		(1 << 0) /* Enable FIFO */
  93#define SC16IS7XX_FCR_RXRESET_BIT	(1 << 1) /* Reset RX FIFO */
  94#define SC16IS7XX_FCR_TXRESET_BIT	(1 << 2) /* Reset TX FIFO */
  95#define SC16IS7XX_FCR_RXLVLL_BIT	(1 << 6) /* RX Trigger level LSB */
  96#define SC16IS7XX_FCR_RXLVLH_BIT	(1 << 7) /* RX Trigger level MSB */
  97
  98/* FCR register bits - write only if (EFR[4] == 1) */
  99#define SC16IS7XX_FCR_TXLVLL_BIT	(1 << 4) /* TX Trigger level LSB */
 100#define SC16IS7XX_FCR_TXLVLH_BIT	(1 << 5) /* TX Trigger level MSB */
 101
 102/* IIR register bits */
 103#define SC16IS7XX_IIR_NO_INT_BIT	(1 << 0) /* No interrupts pending */
 104#define SC16IS7XX_IIR_ID_MASK		0x3e     /* Mask for the interrupt ID */
 105#define SC16IS7XX_IIR_THRI_SRC		0x02     /* TX holding register empty */
 106#define SC16IS7XX_IIR_RDI_SRC		0x04     /* RX data interrupt */
 107#define SC16IS7XX_IIR_RLSE_SRC		0x06     /* RX line status error */
 108#define SC16IS7XX_IIR_RTOI_SRC		0x0c     /* RX time-out interrupt */
 109#define SC16IS7XX_IIR_MSI_SRC		0x00     /* Modem status interrupt
 110						  * - only on 75x/76x
 111						  */
 112#define SC16IS7XX_IIR_INPIN_SRC		0x30     /* Input pin change of state
 113						  * - only on 75x/76x
 114						  */
 115#define SC16IS7XX_IIR_XOFFI_SRC		0x10     /* Received Xoff */
 116#define SC16IS7XX_IIR_CTSRTS_SRC	0x20     /* nCTS,nRTS change of state
 117						  * from active (LOW)
 118						  * to inactive (HIGH)
 119						  */
 120/* LCR register bits */
 121#define SC16IS7XX_LCR_LENGTH0_BIT	(1 << 0) /* Word length bit 0 */
 122#define SC16IS7XX_LCR_LENGTH1_BIT	(1 << 1) /* Word length bit 1
 123						  *
 124						  * Word length bits table:
 125						  * 00 -> 5 bit words
 126						  * 01 -> 6 bit words
 127						  * 10 -> 7 bit words
 128						  * 11 -> 8 bit words
 129						  */
 130#define SC16IS7XX_LCR_STOPLEN_BIT	(1 << 2) /* STOP length bit
 131						  *
 132						  * STOP length bit table:
 133						  * 0 -> 1 stop bit
 134						  * 1 -> 1-1.5 stop bits if
 135						  *      word length is 5,
 136						  *      2 stop bits otherwise
 137						  */
 138#define SC16IS7XX_LCR_PARITY_BIT	(1 << 3) /* Parity bit enable */
 139#define SC16IS7XX_LCR_EVENPARITY_BIT	(1 << 4) /* Even parity bit enable */
 140#define SC16IS7XX_LCR_FORCEPARITY_BIT	(1 << 5) /* 9-bit multidrop parity */
 141#define SC16IS7XX_LCR_TXBREAK_BIT	(1 << 6) /* TX break enable */
 142#define SC16IS7XX_LCR_DLAB_BIT		(1 << 7) /* Divisor Latch enable */
 143#define SC16IS7XX_LCR_WORD_LEN_5	(0x00)
 144#define SC16IS7XX_LCR_WORD_LEN_6	(0x01)
 145#define SC16IS7XX_LCR_WORD_LEN_7	(0x02)
 146#define SC16IS7XX_LCR_WORD_LEN_8	(0x03)
 147#define SC16IS7XX_LCR_CONF_MODE_A	SC16IS7XX_LCR_DLAB_BIT /* Special
 148								* reg set */
 149#define SC16IS7XX_LCR_CONF_MODE_B	0xBF                   /* Enhanced
 150								* reg set */
 151
 152/* MCR register bits */
 153#define SC16IS7XX_MCR_DTR_BIT		(1 << 0) /* DTR complement
 154						  * - only on 75x/76x
 155						  */
 156#define SC16IS7XX_MCR_RTS_BIT		(1 << 1) /* RTS complement */
 157#define SC16IS7XX_MCR_TCRTLR_BIT	(1 << 2) /* TCR/TLR register enable */
 158#define SC16IS7XX_MCR_LOOP_BIT		(1 << 4) /* Enable loopback test mode */
 159#define SC16IS7XX_MCR_XONANY_BIT	(1 << 5) /* Enable Xon Any
 160						  * - write enabled
 161						  * if (EFR[4] == 1)
 162						  */
 163#define SC16IS7XX_MCR_IRDA_BIT		(1 << 6) /* Enable IrDA mode
 164						  * - write enabled
 165						  * if (EFR[4] == 1)
 166						  */
 167#define SC16IS7XX_MCR_CLKSEL_BIT	(1 << 7) /* Divide clock by 4
 168						  * - write enabled
 169						  * if (EFR[4] == 1)
 170						  */
 171
 172/* LSR register bits */
 173#define SC16IS7XX_LSR_DR_BIT		(1 << 0) /* Receiver data ready */
 174#define SC16IS7XX_LSR_OE_BIT		(1 << 1) /* Overrun Error */
 175#define SC16IS7XX_LSR_PE_BIT		(1 << 2) /* Parity Error */
 176#define SC16IS7XX_LSR_FE_BIT		(1 << 3) /* Frame Error */
 177#define SC16IS7XX_LSR_BI_BIT		(1 << 4) /* Break Interrupt */
 178#define SC16IS7XX_LSR_BRK_ERROR_MASK	0x1E     /* BI, FE, PE, OE bits */
 179#define SC16IS7XX_LSR_THRE_BIT		(1 << 5) /* TX holding register empty */
 180#define SC16IS7XX_LSR_TEMT_BIT		(1 << 6) /* Transmitter empty */
 181#define SC16IS7XX_LSR_FIFOE_BIT		(1 << 7) /* Fifo Error */
 182
 183/* MSR register bits */
 184#define SC16IS7XX_MSR_DCTS_BIT		(1 << 0) /* Delta CTS Clear To Send */
 185#define SC16IS7XX_MSR_DDSR_BIT		(1 << 1) /* Delta DSR Data Set Ready
 186						  * or (IO4)
 187						  * - only on 75x/76x
 188						  */
 189#define SC16IS7XX_MSR_DRI_BIT		(1 << 2) /* Delta RI Ring Indicator
 190						  * or (IO7)
 191						  * - only on 75x/76x
 192						  */
 193#define SC16IS7XX_MSR_DCD_BIT		(1 << 3) /* Delta CD Carrier Detect
 194						  * or (IO6)
 195						  * - only on 75x/76x
 196						  */
 197#define SC16IS7XX_MSR_CTS_BIT		(1 << 4) /* CTS */
 198#define SC16IS7XX_MSR_DSR_BIT		(1 << 5) /* DSR (IO4)
 199						  * - only on 75x/76x
 200						  */
 201#define SC16IS7XX_MSR_RI_BIT		(1 << 6) /* RI (IO7)
 202						  * - only on 75x/76x
 203						  */
 204#define SC16IS7XX_MSR_CD_BIT		(1 << 7) /* CD (IO6)
 205						  * - only on 75x/76x
 206						  */
 207#define SC16IS7XX_MSR_DELTA_MASK	0x0F     /* Any of the delta bits! */
 208
 209/*
 210 * TCR register bits
 211 * TCR trigger levels are available from 0 to 60 characters with a granularity
 212 * of four.
 213 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
 214 * no built-in hardware check to make sure this condition is met. Also, the TCR
 215 * must be programmed with this condition before auto RTS or software flow
 216 * control is enabled to avoid spurious operation of the device.
 217 */
 218#define SC16IS7XX_TCR_RX_HALT(words)	((((words) / 4) & 0x0f) << 0)
 219#define SC16IS7XX_TCR_RX_RESUME(words)	((((words) / 4) & 0x0f) << 4)
 220
 221/*
 222 * TLR register bits
 223 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
 224 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
 225 * trigger levels. Trigger levels from 4 characters to 60 characters are
 226 * available with a granularity of four.
 227 *
 228 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the
 229 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
 230 * the trigger level defined in FCR is discarded. This applies to both transmit
 231 * FIFO and receive FIFO trigger level setting.
 232 *
 233 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
 234 * default state, that is, '00'.
 235 */
 236#define SC16IS7XX_TLR_TX_TRIGGER(words)	((((words) / 4) & 0x0f) << 0)
 237#define SC16IS7XX_TLR_RX_TRIGGER(words)	((((words) / 4) & 0x0f) << 4)
 238
 239/* IOControl register bits (Only 75x/76x) */
 240#define SC16IS7XX_IOCONTROL_LATCH_BIT	(1 << 0) /* Enable input latching */
 241#define SC16IS7XX_IOCONTROL_MODEM_A_BIT	(1 << 1) /* Enable GPIO[7:4] as modem A pins */
 242#define SC16IS7XX_IOCONTROL_MODEM_B_BIT	(1 << 2) /* Enable GPIO[3:0] as modem B pins */
 243#define SC16IS7XX_IOCONTROL_SRESET_BIT	(1 << 3) /* Software Reset */
 244
 245/* EFCR register bits */
 246#define SC16IS7XX_EFCR_9BIT_MODE_BIT	(1 << 0) /* Enable 9-bit or Multidrop
 247						  * mode (RS485) */
 248#define SC16IS7XX_EFCR_RXDISABLE_BIT	(1 << 1) /* Disable receiver */
 249#define SC16IS7XX_EFCR_TXDISABLE_BIT	(1 << 2) /* Disable transmitter */
 250#define SC16IS7XX_EFCR_AUTO_RS485_BIT	(1 << 4) /* Auto RS485 RTS direction */
 251#define SC16IS7XX_EFCR_RTS_INVERT_BIT	(1 << 5) /* RTS output inversion */
 252#define SC16IS7XX_EFCR_IRDA_MODE_BIT	(1 << 7) /* IrDA mode
 253						  * 0 = rate upto 115.2 kbit/s
 254						  *   - Only 75x/76x
 255						  * 1 = rate upto 1.152 Mbit/s
 256						  *   - Only 76x
 257						  */
 258
 259/* EFR register bits */
 260#define SC16IS7XX_EFR_AUTORTS_BIT	(1 << 6) /* Auto RTS flow ctrl enable */
 261#define SC16IS7XX_EFR_AUTOCTS_BIT	(1 << 7) /* Auto CTS flow ctrl enable */
 262#define SC16IS7XX_EFR_XOFF2_DETECT_BIT	(1 << 5) /* Enable Xoff2 detection */
 263#define SC16IS7XX_EFR_ENABLE_BIT	(1 << 4) /* Enable enhanced functions
 264						  * and writing to IER[7:4],
 265						  * FCR[5:4], MCR[7:5]
 266						  */
 267#define SC16IS7XX_EFR_SWFLOW3_BIT	(1 << 3) /* SWFLOW bit 3 */
 268#define SC16IS7XX_EFR_SWFLOW2_BIT	(1 << 2) /* SWFLOW bit 2
 269						  *
 270						  * SWFLOW bits 3 & 2 table:
 271						  * 00 -> no transmitter flow
 272						  *       control
 273						  * 01 -> transmitter generates
 274						  *       XON2 and XOFF2
 275						  * 10 -> transmitter generates
 276						  *       XON1 and XOFF1
 277						  * 11 -> transmitter generates
 278						  *       XON1, XON2, XOFF1 and
 279						  *       XOFF2
 280						  */
 281#define SC16IS7XX_EFR_SWFLOW1_BIT	(1 << 1) /* SWFLOW bit 2 */
 282#define SC16IS7XX_EFR_SWFLOW0_BIT	(1 << 0) /* SWFLOW bit 3
 283						  *
 284						  * SWFLOW bits 3 & 2 table:
 285						  * 00 -> no received flow
 286						  *       control
 287						  * 01 -> receiver compares
 288						  *       XON2 and XOFF2
 289						  * 10 -> receiver compares
 290						  *       XON1 and XOFF1
 291						  * 11 -> receiver compares
 292						  *       XON1, XON2, XOFF1 and
 293						  *       XOFF2
 294						  */
 295#define SC16IS7XX_EFR_FLOWCTRL_BITS	(SC16IS7XX_EFR_AUTORTS_BIT | \
 296					SC16IS7XX_EFR_AUTOCTS_BIT | \
 297					SC16IS7XX_EFR_XOFF2_DETECT_BIT | \
 298					SC16IS7XX_EFR_SWFLOW3_BIT | \
 299					SC16IS7XX_EFR_SWFLOW2_BIT | \
 300					SC16IS7XX_EFR_SWFLOW1_BIT | \
 301					SC16IS7XX_EFR_SWFLOW0_BIT)
 302
 303
 304/* Misc definitions */
 305#define SC16IS7XX_SPI_READ_BIT		BIT(7)
 306#define SC16IS7XX_FIFO_SIZE		(64)
 307#define SC16IS7XX_GPIOS_PER_BANK	4
 308
 309struct sc16is7xx_devtype {
 310	char	name[10];
 311	int	nr_gpio;
 312	int	nr_uart;
 313};
 314
 315#define SC16IS7XX_RECONF_MD		(1 << 0)
 316#define SC16IS7XX_RECONF_IER		(1 << 1)
 317#define SC16IS7XX_RECONF_RS485		(1 << 2)
 318
 319struct sc16is7xx_one_config {
 320	unsigned int			flags;
 321	u8				ier_mask;
 322	u8				ier_val;
 323};
 324
 325struct sc16is7xx_one {
 326	struct uart_port		port;
 327	struct regmap			*regmap;
 328	struct mutex			efr_lock; /* EFR registers access */
 329	struct kthread_work		tx_work;
 330	struct kthread_work		reg_work;
 331	struct kthread_delayed_work	ms_work;
 332	struct sc16is7xx_one_config	config;
 333	unsigned int			old_mctrl;
 334	u8				old_lcr; /* Value before EFR access. */
 335	bool				irda_mode;
 336};
 337
 338struct sc16is7xx_port {
 339	const struct sc16is7xx_devtype	*devtype;
 
 340	struct clk			*clk;
 341#ifdef CONFIG_GPIOLIB
 342	struct gpio_chip		gpio;
 343	unsigned long			gpio_valid_mask;
 344#endif
 345	u8				mctrl_mask;
 346	unsigned char			buf[SC16IS7XX_FIFO_SIZE];
 347	struct kthread_worker		kworker;
 348	struct task_struct		*kworker_task;
 349	struct sc16is7xx_one		p[];
 
 350};
 351
 352static DECLARE_BITMAP(sc16is7xx_lines, SC16IS7XX_MAX_DEVS);
 353
 354static struct uart_driver sc16is7xx_uart = {
 355	.owner		= THIS_MODULE,
 356	.driver_name    = SC16IS7XX_NAME,
 357	.dev_name	= "ttySC",
 358	.nr		= SC16IS7XX_MAX_DEVS,
 359};
 360
 
 361#define to_sc16is7xx_one(p,e)	((container_of((p), struct sc16is7xx_one, e)))
 362
 363static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
 364{
 365	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 
 
 
 
 
 
 
 366	unsigned int val = 0;
 
 367
 368	regmap_read(one->regmap, reg, &val);
 369
 370	return val;
 371}
 372
 373static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
 374{
 375	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 
 376
 377	regmap_write(one->regmap, reg, val);
 378}
 379
 380static void sc16is7xx_fifo_read(struct uart_port *port, u8 *rxbuf, unsigned int rxlen)
 381{
 382	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 
 
 383
 384	regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, rxbuf, rxlen);
 
 
 385}
 386
 387static void sc16is7xx_fifo_write(struct uart_port *port, u8 *txbuf, u8 to_send)
 388{
 389	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 
 
 390
 391	/*
 392	 * Don't send zero-length data, at least on SPI it confuses the chip
 393	 * delivering wrong TXLVL data.
 394	 */
 395	if (unlikely(!to_send))
 396		return;
 397
 398	regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, txbuf, to_send);
 
 
 399}
 400
 401static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
 402				  u8 mask, u8 val)
 403{
 404	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 405
 406	regmap_update_bits(one->regmap, reg, mask, val);
 407}
 408
 409static void sc16is7xx_power(struct uart_port *port, int on)
 410{
 411	sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
 412			      SC16IS7XX_IER_SLEEP_BIT,
 413			      on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
 414}
 415
 416/*
 417 * In an amazing feat of design, the Enhanced Features Register (EFR)
 418 * shares the address of the Interrupt Identification Register (IIR).
 419 * Access to EFR is switched on by writing a magic value (0xbf) to the
 420 * Line Control Register (LCR). Any interrupt firing during this time will
 421 * see the EFR where it expects the IIR to be, leading to
 422 * "Unexpected interrupt" messages.
 423 *
 424 * Prevent this possibility by claiming a mutex while accessing the EFR,
 425 * and claiming the same mutex from within the interrupt handler. This is
 426 * similar to disabling the interrupt, but that doesn't work because the
 427 * bulk of the interrupt processing is run as a workqueue job in thread
 428 * context.
 429 */
 430static void sc16is7xx_efr_lock(struct uart_port *port)
 431{
 432	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 433
 434	mutex_lock(&one->efr_lock);
 435
 436	/* Backup content of LCR. */
 437	one->old_lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
 438
 439	/* Enable access to Enhanced register set */
 440	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_CONF_MODE_B);
 441
 442	/* Disable cache updates when writing to EFR registers */
 443	regcache_cache_bypass(one->regmap, true);
 444}
 445
 446static void sc16is7xx_efr_unlock(struct uart_port *port)
 447{
 448	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 449
 450	/* Re-enable cache updates when writing to normal registers */
 451	regcache_cache_bypass(one->regmap, false);
 452
 453	/* Restore original content of LCR */
 454	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, one->old_lcr);
 455
 456	mutex_unlock(&one->efr_lock);
 457}
 458
 459static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
 460{
 461	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 462	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 463
 464	lockdep_assert_held_once(&port->lock);
 465
 466	one->config.flags |= SC16IS7XX_RECONF_IER;
 467	one->config.ier_mask |= bit;
 468	one->config.ier_val &= ~bit;
 469	kthread_queue_work(&s->kworker, &one->reg_work);
 470}
 471
 472static void sc16is7xx_ier_set(struct uart_port *port, u8 bit)
 473{
 474	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 475	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 476
 477	lockdep_assert_held_once(&port->lock);
 478
 479	one->config.flags |= SC16IS7XX_RECONF_IER;
 480	one->config.ier_mask |= bit;
 481	one->config.ier_val |= bit;
 482	kthread_queue_work(&s->kworker, &one->reg_work);
 483}
 484
 485static void sc16is7xx_stop_tx(struct uart_port *port)
 486{
 487	sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
 488}
 489
 490static void sc16is7xx_stop_rx(struct uart_port *port)
 491{
 492	sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
 
 
 493}
 494
 495static const struct sc16is7xx_devtype sc16is74x_devtype = {
 496	.name		= "SC16IS74X",
 497	.nr_gpio	= 0,
 498	.nr_uart	= 1,
 499};
 500
 501static const struct sc16is7xx_devtype sc16is750_devtype = {
 502	.name		= "SC16IS750",
 503	.nr_gpio	= 8,
 504	.nr_uart	= 1,
 505};
 506
 507static const struct sc16is7xx_devtype sc16is752_devtype = {
 508	.name		= "SC16IS752",
 509	.nr_gpio	= 8,
 510	.nr_uart	= 2,
 511};
 512
 513static const struct sc16is7xx_devtype sc16is760_devtype = {
 514	.name		= "SC16IS760",
 515	.nr_gpio	= 8,
 516	.nr_uart	= 1,
 517};
 518
 519static const struct sc16is7xx_devtype sc16is762_devtype = {
 520	.name		= "SC16IS762",
 521	.nr_gpio	= 8,
 522	.nr_uart	= 2,
 523};
 524
 525static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
 526{
 527	switch (reg) {
 528	case SC16IS7XX_RHR_REG:
 529	case SC16IS7XX_IIR_REG:
 530	case SC16IS7XX_LSR_REG:
 531	case SC16IS7XX_MSR_REG:
 532	case SC16IS7XX_TXLVL_REG:
 533	case SC16IS7XX_RXLVL_REG:
 534	case SC16IS7XX_IOSTATE_REG:
 535	case SC16IS7XX_IOCONTROL_REG:
 536		return true;
 537	default:
 538		return false;
 539	}
 
 
 540}
 541
 542static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
 543{
 544	switch (reg) {
 545	case SC16IS7XX_RHR_REG:
 546		return true;
 547	default:
 548		return false;
 549	}
 550}
 551
 552static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)
 553{
 554	return reg == SC16IS7XX_RHR_REG;
 555}
 556
 557/*
 558 * Configure programmable baud rate generator (divisor) according to the
 559 * desired baud rate.
 560 *
 561 * From the datasheet, the divisor is computed according to:
 562 *
 563 *              XTAL1 input frequency
 564 *             -----------------------
 565 *                    prescaler
 566 * divisor = ---------------------------
 567 *            baud-rate x sampling-rate
 568 */
 569static int sc16is7xx_set_baud(struct uart_port *port, int baud)
 570{
 571	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 572	u8 lcr;
 573	unsigned int prescaler = 1;
 574	unsigned long clk = port->uartclk, div = clk / 16 / baud;
 575
 576	if (div >= BIT(16)) {
 577		prescaler = 4;
 578		div /= prescaler;
 579	}
 580
 
 
 
 
 
 
 581	/* Enable enhanced features */
 582	sc16is7xx_efr_lock(port);
 583	sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
 584			      SC16IS7XX_EFR_ENABLE_BIT,
 585			      SC16IS7XX_EFR_ENABLE_BIT);
 586	sc16is7xx_efr_unlock(port);
 
 
 587
 588	/* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */
 589	sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
 590			      SC16IS7XX_MCR_CLKSEL_BIT,
 591			      prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT);
 592
 593	/* Backup LCR and access special register set (DLL/DLH) */
 594	lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
 595	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
 596			     SC16IS7XX_LCR_CONF_MODE_A);
 597
 598	/* Write the new divisor */
 599	regcache_cache_bypass(one->regmap, true);
 600	sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
 601	sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
 602	regcache_cache_bypass(one->regmap, false);
 603
 604	/* Restore LCR and access to general register set */
 605	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
 606
 607	return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div);
 608}
 609
 610static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
 611				unsigned int iir)
 612{
 613	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 614	unsigned int lsr = 0, bytes_read, i;
 615	bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
 616	u8 ch, flag;
 617
 618	if (unlikely(rxlen >= sizeof(s->buf))) {
 619		dev_warn_ratelimited(port->dev,
 620				     "ttySC%i: Possible RX FIFO overrun: %d\n",
 621				     port->line, rxlen);
 622		port->icount.buf_overrun++;
 623		/* Ensure sanity of RX level */
 624		rxlen = sizeof(s->buf);
 625	}
 626
 627	while (rxlen) {
 628		/* Only read lsr if there are possible errors in FIFO */
 629		if (read_lsr) {
 630			lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
 631			if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
 632				read_lsr = false; /* No errors left in FIFO */
 633		} else
 634			lsr = 0;
 635
 636		if (read_lsr) {
 637			s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
 638			bytes_read = 1;
 639		} else {
 640			sc16is7xx_fifo_read(port, s->buf, rxlen);
 641			bytes_read = rxlen;
 642		}
 643
 644		lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
 645
 646		port->icount.rx++;
 647		flag = TTY_NORMAL;
 648
 649		if (unlikely(lsr)) {
 650			if (lsr & SC16IS7XX_LSR_BI_BIT) {
 651				port->icount.brk++;
 652				if (uart_handle_break(port))
 653					continue;
 654			} else if (lsr & SC16IS7XX_LSR_PE_BIT)
 655				port->icount.parity++;
 656			else if (lsr & SC16IS7XX_LSR_FE_BIT)
 657				port->icount.frame++;
 658			else if (lsr & SC16IS7XX_LSR_OE_BIT)
 659				port->icount.overrun++;
 660
 661			lsr &= port->read_status_mask;
 662			if (lsr & SC16IS7XX_LSR_BI_BIT)
 663				flag = TTY_BREAK;
 664			else if (lsr & SC16IS7XX_LSR_PE_BIT)
 665				flag = TTY_PARITY;
 666			else if (lsr & SC16IS7XX_LSR_FE_BIT)
 667				flag = TTY_FRAME;
 668			else if (lsr & SC16IS7XX_LSR_OE_BIT)
 669				flag = TTY_OVERRUN;
 670		}
 671
 672		for (i = 0; i < bytes_read; ++i) {
 673			ch = s->buf[i];
 674			if (uart_handle_sysrq_char(port, ch))
 675				continue;
 676
 677			if (lsr & port->ignore_status_mask)
 678				continue;
 679
 680			uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
 681					 flag);
 682		}
 683		rxlen -= bytes_read;
 684	}
 685
 686	tty_flip_buffer_push(&port->state->port);
 687}
 688
 689static void sc16is7xx_handle_tx(struct uart_port *port)
 690{
 691	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 692	struct circ_buf *xmit = &port->state->xmit;
 693	unsigned int txlen, to_send, i;
 694	unsigned long flags;
 695
 696	if (unlikely(port->x_char)) {
 697		sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
 698		port->icount.tx++;
 699		port->x_char = 0;
 700		return;
 701	}
 702
 703	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 704		uart_port_lock_irqsave(port, &flags);
 705		sc16is7xx_stop_tx(port);
 706		uart_port_unlock_irqrestore(port, flags);
 707		return;
 708	}
 709
 710	/* Get length of data pending in circular buffer */
 711	to_send = uart_circ_chars_pending(xmit);
 712	if (likely(to_send)) {
 713		/* Limit to space available in TX FIFO */
 714		txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
 715		if (txlen > SC16IS7XX_FIFO_SIZE) {
 716			dev_err_ratelimited(port->dev,
 717				"chip reports %d free bytes in TX fifo, but it only has %d",
 718				txlen, SC16IS7XX_FIFO_SIZE);
 719			txlen = 0;
 720		}
 721		to_send = (to_send > txlen) ? txlen : to_send;
 722
 
 
 
 723		/* Convert to linear buffer */
 724		for (i = 0; i < to_send; ++i) {
 725			s->buf[i] = xmit->buf[xmit->tail];
 726			uart_xmit_advance(port, 1);
 727		}
 728
 729		sc16is7xx_fifo_write(port, s->buf, to_send);
 730	}
 731
 732	uart_port_lock_irqsave(port, &flags);
 733	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 734		uart_write_wakeup(port);
 735
 736	if (uart_circ_empty(xmit))
 737		sc16is7xx_stop_tx(port);
 738	else
 739		sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);
 740	uart_port_unlock_irqrestore(port, flags);
 741}
 742
 743static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port)
 744{
 745	u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
 746	unsigned int mctrl = 0;
 747
 748	mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0;
 749	mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0;
 750	mctrl |= (msr & SC16IS7XX_MSR_CD_BIT)  ? TIOCM_CAR : 0;
 751	mctrl |= (msr & SC16IS7XX_MSR_RI_BIT)  ? TIOCM_RNG : 0;
 752	return mctrl;
 753}
 754
 755static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
 756{
 757	struct uart_port *port = &one->port;
 758	unsigned long flags;
 759	unsigned int status, changed;
 760
 761	lockdep_assert_held_once(&one->efr_lock);
 762
 763	status = sc16is7xx_get_hwmctrl(port);
 764	changed = status ^ one->old_mctrl;
 765
 766	if (changed == 0)
 767		return;
 768
 769	one->old_mctrl = status;
 770
 771	uart_port_lock_irqsave(port, &flags);
 772	if ((changed & TIOCM_RNG) && (status & TIOCM_RNG))
 773		port->icount.rng++;
 774	if (changed & TIOCM_DSR)
 775		port->icount.dsr++;
 776	if (changed & TIOCM_CAR)
 777		uart_handle_dcd_change(port, status & TIOCM_CAR);
 778	if (changed & TIOCM_CTS)
 779		uart_handle_cts_change(port, status & TIOCM_CTS);
 780
 781	wake_up_interruptible(&port->state->port.delta_msr_wait);
 782	uart_port_unlock_irqrestore(port, flags);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 783}
 784
 785static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
 786{
 787	bool rc = true;
 788	unsigned int iir, rxlen;
 789	struct uart_port *port = &s->p[portno].port;
 790	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 791
 792	mutex_lock(&one->efr_lock);
 793
 794	iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
 795	if (iir & SC16IS7XX_IIR_NO_INT_BIT) {
 796		rc = false;
 797		goto out_port_irq;
 798	}
 799
 800	iir &= SC16IS7XX_IIR_ID_MASK;
 801
 802	switch (iir) {
 803	case SC16IS7XX_IIR_RDI_SRC:
 804	case SC16IS7XX_IIR_RLSE_SRC:
 805	case SC16IS7XX_IIR_RTOI_SRC:
 806	case SC16IS7XX_IIR_XOFFI_SRC:
 807		rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
 808
 809		/*
 810		 * There is a silicon bug that makes the chip report a
 811		 * time-out interrupt but no data in the FIFO. This is
 812		 * described in errata section 18.1.4.
 813		 *
 814		 * When this happens, read one byte from the FIFO to
 815		 * clear the interrupt.
 816		 */
 817		if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)
 818			rxlen = 1;
 819
 820		if (rxlen)
 821			sc16is7xx_handle_rx(port, rxlen, iir);
 822		break;
 823		/* CTSRTS interrupt comes only when CTS goes inactive */
 824	case SC16IS7XX_IIR_CTSRTS_SRC:
 825	case SC16IS7XX_IIR_MSI_SRC:
 826		sc16is7xx_update_mlines(one);
 827		break;
 828	case SC16IS7XX_IIR_THRI_SRC:
 829		sc16is7xx_handle_tx(port);
 830		break;
 831	default:
 832		dev_err_ratelimited(port->dev,
 833				    "ttySC%i: Unexpected interrupt: %x",
 834				    port->line, iir);
 835		break;
 836	}
 837
 838out_port_irq:
 839	mutex_unlock(&one->efr_lock);
 840
 841	return rc;
 
 842}
 843
 844static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
 845{
 846	bool keep_polling;
 847
 848	struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
 849
 850	do {
 851		int i;
 852
 853		keep_polling = false;
 854
 855		for (i = 0; i < s->devtype->nr_uart; ++i)
 856			keep_polling |= sc16is7xx_port_irq(s, i);
 857	} while (keep_polling);
 858
 859	return IRQ_HANDLED;
 860}
 861
 862static void sc16is7xx_tx_proc(struct kthread_work *ws)
 863{
 864	struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
 865	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 866
 867	if ((port->rs485.flags & SER_RS485_ENABLED) &&
 868	    (port->rs485.delay_rts_before_send > 0))
 869		msleep(port->rs485.delay_rts_before_send);
 870
 871	mutex_lock(&one->efr_lock);
 872	sc16is7xx_handle_tx(port);
 873	mutex_unlock(&one->efr_lock);
 874}
 875
 876static void sc16is7xx_reconf_rs485(struct uart_port *port)
 877{
 878	const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
 879			 SC16IS7XX_EFCR_RTS_INVERT_BIT;
 880	u32 efcr = 0;
 881	struct serial_rs485 *rs485 = &port->rs485;
 882	unsigned long irqflags;
 883
 884	uart_port_lock_irqsave(port, &irqflags);
 885	if (rs485->flags & SER_RS485_ENABLED) {
 886		efcr |=	SC16IS7XX_EFCR_AUTO_RS485_BIT;
 887
 888		if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
 889			efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
 890	}
 891	uart_port_unlock_irqrestore(port, irqflags);
 892
 893	sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
 894}
 895
 896static void sc16is7xx_reg_proc(struct kthread_work *ws)
 897{
 898	struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
 899	struct sc16is7xx_one_config config;
 900	unsigned long irqflags;
 901
 902	uart_port_lock_irqsave(&one->port, &irqflags);
 903	config = one->config;
 904	memset(&one->config, 0, sizeof(one->config));
 905	uart_port_unlock_irqrestore(&one->port, irqflags);
 906
 907	if (config.flags & SC16IS7XX_RECONF_MD) {
 908		u8 mcr = 0;
 909
 910		/* Device ignores RTS setting when hardware flow is enabled */
 911		if (one->port.mctrl & TIOCM_RTS)
 912			mcr |= SC16IS7XX_MCR_RTS_BIT;
 913
 914		if (one->port.mctrl & TIOCM_DTR)
 915			mcr |= SC16IS7XX_MCR_DTR_BIT;
 916
 917		if (one->port.mctrl & TIOCM_LOOP)
 918			mcr |= SC16IS7XX_MCR_LOOP_BIT;
 919		sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
 920				      SC16IS7XX_MCR_RTS_BIT |
 921				      SC16IS7XX_MCR_DTR_BIT |
 922				      SC16IS7XX_MCR_LOOP_BIT,
 923				      mcr);
 
 
 
 
 
 
 
 
 
 924	}
 925
 926	if (config.flags & SC16IS7XX_RECONF_IER)
 927		sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
 928				      config.ier_mask, config.ier_val);
 929
 930	if (config.flags & SC16IS7XX_RECONF_RS485)
 931		sc16is7xx_reconf_rs485(&one->port);
 932}
 933
 934static void sc16is7xx_ms_proc(struct kthread_work *ws)
 935{
 936	struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work);
 937	struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
 938
 939	if (one->port.state) {
 940		mutex_lock(&one->efr_lock);
 941		sc16is7xx_update_mlines(one);
 942		mutex_unlock(&one->efr_lock);
 943
 944		kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ);
 945	}
 946}
 947
 948static void sc16is7xx_enable_ms(struct uart_port *port)
 949{
 950	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 951	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 
 952
 953	lockdep_assert_held_once(&port->lock);
 954
 955	kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0);
 956}
 957
 958static void sc16is7xx_start_tx(struct uart_port *port)
 959{
 960	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
 961	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
 962
 963	kthread_queue_work(&s->kworker, &one->tx_work);
 964}
 965
 966static void sc16is7xx_throttle(struct uart_port *port)
 967{
 968	unsigned long flags;
 969
 970	/*
 971	 * Hardware flow control is enabled and thus the device ignores RTS
 972	 * value set in MCR register. Stop reading data from RX FIFO so the
 973	 * AutoRTS feature will de-activate RTS output.
 974	 */
 975	uart_port_lock_irqsave(port, &flags);
 976	sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
 977	uart_port_unlock_irqrestore(port, flags);
 978}
 979
 980static void sc16is7xx_unthrottle(struct uart_port *port)
 981{
 982	unsigned long flags;
 
 983
 984	uart_port_lock_irqsave(port, &flags);
 985	sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT);
 986	uart_port_unlock_irqrestore(port, flags);
 987}
 988
 989static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
 990{
 991	unsigned int lsr;
 992
 993	lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
 994
 995	return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
 996}
 997
 998static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
 999{
1000	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1001
1002	/* Called with port lock taken so we can only return cached value */
1003	return one->old_mctrl;
1004}
1005
1006static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
1007{
1008	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1009	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1010
1011	one->config.flags |= SC16IS7XX_RECONF_MD;
1012	kthread_queue_work(&s->kworker, &one->reg_work);
1013}
1014
1015static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
1016{
1017	sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
1018			      SC16IS7XX_LCR_TXBREAK_BIT,
1019			      break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
1020}
1021
1022static void sc16is7xx_set_termios(struct uart_port *port,
1023				  struct ktermios *termios,
1024				  const struct ktermios *old)
1025{
1026	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1027	unsigned int lcr, flow = 0;
1028	int baud;
1029	unsigned long flags;
1030
1031	kthread_cancel_delayed_work_sync(&one->ms_work);
1032
1033	/* Mask termios capabilities we don't support */
1034	termios->c_cflag &= ~CMSPAR;
1035
1036	/* Word size */
1037	switch (termios->c_cflag & CSIZE) {
1038	case CS5:
1039		lcr = SC16IS7XX_LCR_WORD_LEN_5;
1040		break;
1041	case CS6:
1042		lcr = SC16IS7XX_LCR_WORD_LEN_6;
1043		break;
1044	case CS7:
1045		lcr = SC16IS7XX_LCR_WORD_LEN_7;
1046		break;
1047	case CS8:
1048		lcr = SC16IS7XX_LCR_WORD_LEN_8;
1049		break;
1050	default:
1051		lcr = SC16IS7XX_LCR_WORD_LEN_8;
1052		termios->c_cflag &= ~CSIZE;
1053		termios->c_cflag |= CS8;
1054		break;
1055	}
1056
1057	/* Parity */
1058	if (termios->c_cflag & PARENB) {
1059		lcr |= SC16IS7XX_LCR_PARITY_BIT;
1060		if (!(termios->c_cflag & PARODD))
1061			lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
1062	}
1063
1064	/* Stop bits */
1065	if (termios->c_cflag & CSTOPB)
1066		lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
1067
1068	/* Set read status mask */
1069	port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
1070	if (termios->c_iflag & INPCK)
1071		port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
1072					  SC16IS7XX_LSR_FE_BIT;
1073	if (termios->c_iflag & (BRKINT | PARMRK))
1074		port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
1075
1076	/* Set status ignore mask */
1077	port->ignore_status_mask = 0;
1078	if (termios->c_iflag & IGNBRK)
1079		port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
1080	if (!(termios->c_cflag & CREAD))
1081		port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
1082
 
 
 
1083	/* Configure flow control */
1084	port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1085	if (termios->c_cflag & CRTSCTS) {
 
 
1086		flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
1087			SC16IS7XX_EFR_AUTORTS_BIT;
1088		port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1089	}
1090	if (termios->c_iflag & IXON)
1091		flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
1092	if (termios->c_iflag & IXOFF)
1093		flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
1094
 
 
 
1095	/* Update LCR register */
1096	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
1097
1098	/* Update EFR registers */
1099	sc16is7xx_efr_lock(port);
1100	sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
1101	sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
1102	sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1103			      SC16IS7XX_EFR_FLOWCTRL_BITS, flow);
1104	sc16is7xx_efr_unlock(port);
1105
1106	/* Get baud rate generator configuration */
1107	baud = uart_get_baud_rate(port, termios, old,
1108				  port->uartclk / 16 / 4 / 0xffff,
1109				  port->uartclk / 16);
1110
1111	/* Setup baudrate generator */
1112	baud = sc16is7xx_set_baud(port, baud);
1113
1114	uart_port_lock_irqsave(port, &flags);
1115
1116	/* Update timeout according to new baud rate */
1117	uart_update_timeout(port, termios->c_cflag, baud);
1118
1119	if (UART_ENABLE_MS(port, termios->c_cflag))
1120		sc16is7xx_enable_ms(port);
1121
1122	uart_port_unlock_irqrestore(port, flags);
1123}
1124
1125static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios,
1126				  struct serial_rs485 *rs485)
1127{
1128	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1129	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1130
1131	if (rs485->flags & SER_RS485_ENABLED) {
 
 
 
 
 
 
 
 
 
 
1132		/*
1133		 * RTS signal is handled by HW, it's timing can't be influenced.
1134		 * However, it's sometimes useful to delay TX even without RTS
1135		 * control therefore we try to handle .delay_rts_before_send.
1136		 */
1137		if (rs485->delay_rts_after_send)
1138			return -EINVAL;
1139	}
1140
 
1141	one->config.flags |= SC16IS7XX_RECONF_RS485;
1142	kthread_queue_work(&s->kworker, &one->reg_work);
1143
1144	return 0;
1145}
1146
1147static int sc16is7xx_startup(struct uart_port *port)
1148{
1149	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1150	unsigned int val;
1151	unsigned long flags;
1152
1153	sc16is7xx_power(port, 1);
1154
1155	/* Reset FIFOs*/
1156	val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1157	sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1158	udelay(5);
1159	sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1160			     SC16IS7XX_FCR_FIFO_BIT);
1161
1162	/* Enable EFR */
1163	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
1164			     SC16IS7XX_LCR_CONF_MODE_B);
1165
1166	regcache_cache_bypass(one->regmap, true);
1167
1168	/* Enable write access to enhanced features and internal clock div */
1169	sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1170			      SC16IS7XX_EFR_ENABLE_BIT,
1171			      SC16IS7XX_EFR_ENABLE_BIT);
1172
1173	/* Enable TCR/TLR */
1174	sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1175			      SC16IS7XX_MCR_TCRTLR_BIT,
1176			      SC16IS7XX_MCR_TCRTLR_BIT);
1177
1178	/* Configure flow control levels */
1179	/* Flow control halt level 48, resume level 24 */
1180	sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1181			     SC16IS7XX_TCR_RX_RESUME(24) |
1182			     SC16IS7XX_TCR_RX_HALT(48));
1183
1184	regcache_cache_bypass(one->regmap, false);
1185
1186	/* Now, initialize the UART */
1187	sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1188
1189	/* Enable IrDA mode if requested in DT */
1190	/* This bit must be written with LCR[7] = 0 */
1191	sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1192			      SC16IS7XX_MCR_IRDA_BIT,
1193			      one->irda_mode ?
1194				SC16IS7XX_MCR_IRDA_BIT : 0);
1195
1196	/* Enable the Rx and Tx FIFO */
1197	sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1198			      SC16IS7XX_EFCR_RXDISABLE_BIT |
1199			      SC16IS7XX_EFCR_TXDISABLE_BIT,
1200			      0);
1201
1202	/* Enable RX, CTS change and modem lines interrupts */
1203	val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT |
1204	      SC16IS7XX_IER_MSI_BIT;
1205	sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1206
1207	/* Enable modem status polling */
1208	uart_port_lock_irqsave(port, &flags);
1209	sc16is7xx_enable_ms(port);
1210	uart_port_unlock_irqrestore(port, flags);
1211
1212	return 0;
1213}
1214
1215static void sc16is7xx_shutdown(struct uart_port *port)
1216{
1217	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1218	struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1219
1220	kthread_cancel_delayed_work_sync(&one->ms_work);
1221
1222	/* Disable all interrupts */
1223	sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1224	/* Disable TX/RX */
1225	sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1226			      SC16IS7XX_EFCR_RXDISABLE_BIT |
1227			      SC16IS7XX_EFCR_TXDISABLE_BIT,
1228			      SC16IS7XX_EFCR_RXDISABLE_BIT |
1229			      SC16IS7XX_EFCR_TXDISABLE_BIT);
1230
1231	sc16is7xx_power(port, 0);
1232
1233	kthread_flush_worker(&s->kworker);
1234}
1235
1236static const char *sc16is7xx_type(struct uart_port *port)
1237{
1238	struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1239
1240	return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1241}
1242
1243static int sc16is7xx_request_port(struct uart_port *port)
1244{
1245	/* Do nothing */
1246	return 0;
1247}
1248
1249static void sc16is7xx_config_port(struct uart_port *port, int flags)
1250{
1251	if (flags & UART_CONFIG_TYPE)
1252		port->type = PORT_SC16IS7XX;
1253}
1254
1255static int sc16is7xx_verify_port(struct uart_port *port,
1256				 struct serial_struct *s)
1257{
1258	if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1259		return -EINVAL;
1260	if (s->irq != port->irq)
1261		return -EINVAL;
1262
1263	return 0;
1264}
1265
1266static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1267			 unsigned int oldstate)
1268{
1269	sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1270}
1271
1272static void sc16is7xx_null_void(struct uart_port *port)
1273{
1274	/* Do nothing */
1275}
1276
1277static const struct uart_ops sc16is7xx_ops = {
1278	.tx_empty	= sc16is7xx_tx_empty,
1279	.set_mctrl	= sc16is7xx_set_mctrl,
1280	.get_mctrl	= sc16is7xx_get_mctrl,
1281	.stop_tx	= sc16is7xx_stop_tx,
1282	.start_tx	= sc16is7xx_start_tx,
1283	.throttle	= sc16is7xx_throttle,
1284	.unthrottle	= sc16is7xx_unthrottle,
1285	.stop_rx	= sc16is7xx_stop_rx,
1286	.enable_ms	= sc16is7xx_enable_ms,
1287	.break_ctl	= sc16is7xx_break_ctl,
1288	.startup	= sc16is7xx_startup,
1289	.shutdown	= sc16is7xx_shutdown,
1290	.set_termios	= sc16is7xx_set_termios,
1291	.type		= sc16is7xx_type,
1292	.request_port	= sc16is7xx_request_port,
1293	.release_port	= sc16is7xx_null_void,
1294	.config_port	= sc16is7xx_config_port,
1295	.verify_port	= sc16is7xx_verify_port,
1296	.pm		= sc16is7xx_pm,
1297};
1298
1299#ifdef CONFIG_GPIOLIB
1300static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1301{
1302	unsigned int val;
1303	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1304	struct uart_port *port = &s->p[0].port;
1305
1306	val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1307
1308	return !!(val & BIT(offset));
1309}
1310
1311static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1312{
1313	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1314	struct uart_port *port = &s->p[0].port;
1315
1316	sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1317			      val ? BIT(offset) : 0);
1318}
1319
1320static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1321					  unsigned offset)
1322{
1323	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1324	struct uart_port *port = &s->p[0].port;
1325
1326	sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1327
1328	return 0;
1329}
1330
1331static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1332					   unsigned offset, int val)
1333{
1334	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1335	struct uart_port *port = &s->p[0].port;
1336	u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1337
1338	if (val)
1339		state |= BIT(offset);
1340	else
1341		state &= ~BIT(offset);
1342
1343	/*
1344	 * If we write IOSTATE first, and then IODIR, the output value is not
1345	 * transferred to the corresponding I/O pin.
1346	 * The datasheet states that each register bit will be transferred to
1347	 * the corresponding I/O pin programmed as output when writing to
1348	 * IOSTATE. Therefore, configure direction first with IODIR, and then
1349	 * set value after with IOSTATE.
1350	 */
1351	sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1352			      BIT(offset));
1353	sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1354
1355	return 0;
1356}
1357
1358static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip,
1359					  unsigned long *valid_mask,
1360					  unsigned int ngpios)
1361{
1362	struct sc16is7xx_port *s = gpiochip_get_data(chip);
1363
1364	*valid_mask = s->gpio_valid_mask;
1365
1366	return 0;
1367}
1368
1369static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s)
1370{
1371	struct device *dev = s->p[0].port.dev;
1372
1373	if (!s->devtype->nr_gpio)
1374		return 0;
1375
1376	switch (s->mctrl_mask) {
1377	case 0:
1378		s->gpio_valid_mask = GENMASK(7, 0);
1379		break;
1380	case SC16IS7XX_IOCONTROL_MODEM_A_BIT:
1381		s->gpio_valid_mask = GENMASK(3, 0);
1382		break;
1383	case SC16IS7XX_IOCONTROL_MODEM_B_BIT:
1384		s->gpio_valid_mask = GENMASK(7, 4);
1385		break;
1386	default:
1387		break;
1388	}
1389
1390	if (s->gpio_valid_mask == 0)
1391		return 0;
1392
1393	s->gpio.owner		 = THIS_MODULE;
1394	s->gpio.parent		 = dev;
1395	s->gpio.label		 = dev_name(dev);
1396	s->gpio.init_valid_mask	 = sc16is7xx_gpio_init_valid_mask;
1397	s->gpio.direction_input	 = sc16is7xx_gpio_direction_input;
1398	s->gpio.get		 = sc16is7xx_gpio_get;
1399	s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1400	s->gpio.set		 = sc16is7xx_gpio_set;
1401	s->gpio.base		 = -1;
1402	s->gpio.ngpio		 = s->devtype->nr_gpio;
1403	s->gpio.can_sleep	 = 1;
1404
1405	return gpiochip_add_data(&s->gpio, s);
1406}
1407#endif
1408
1409static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s)
1410{
1411	int i;
1412	int ret;
1413	int count;
1414	u32 irda_port[SC16IS7XX_MAX_PORTS];
1415	struct device *dev = s->p[0].port.dev;
1416
1417	count = device_property_count_u32(dev, "irda-mode-ports");
1418	if (count < 0 || count > ARRAY_SIZE(irda_port))
1419		return;
1420
1421	ret = device_property_read_u32_array(dev, "irda-mode-ports",
1422					     irda_port, count);
1423	if (ret)
1424		return;
1425
1426	for (i = 0; i < count; i++) {
1427		if (irda_port[i] < s->devtype->nr_uart)
1428			s->p[irda_port[i]].irda_mode = true;
1429	}
1430}
1431
1432/*
1433 * Configure ports designated to operate as modem control lines.
1434 */
1435static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s,
1436				       struct regmap *regmap)
1437{
1438	int i;
1439	int ret;
1440	int count;
1441	u32 mctrl_port[SC16IS7XX_MAX_PORTS];
1442	struct device *dev = s->p[0].port.dev;
1443
1444	count = device_property_count_u32(dev, "nxp,modem-control-line-ports");
1445	if (count < 0 || count > ARRAY_SIZE(mctrl_port))
1446		return 0;
1447
1448	ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports",
1449					     mctrl_port, count);
1450	if (ret)
1451		return ret;
1452
1453	s->mctrl_mask = 0;
1454
1455	for (i = 0; i < count; i++) {
1456		/* Use GPIO lines as modem control lines */
1457		if (mctrl_port[i] == 0)
1458			s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT;
1459		else if (mctrl_port[i] == 1)
1460			s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT;
1461	}
1462
1463	if (s->mctrl_mask)
1464		regmap_update_bits(
1465			regmap,
1466			SC16IS7XX_IOCONTROL_REG,
1467			SC16IS7XX_IOCONTROL_MODEM_A_BIT |
1468			SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask);
1469
1470	return 0;
1471}
1472
1473static const struct serial_rs485 sc16is7xx_rs485_supported = {
1474	.flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND,
1475	.delay_rts_before_send = 1,
1476	.delay_rts_after_send = 1,	/* Not supported but keep returning -EINVAL */
1477};
1478
1479static int sc16is7xx_probe(struct device *dev,
1480			   const struct sc16is7xx_devtype *devtype,
1481			   struct regmap *regmaps[], int irq)
1482{
1483	unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1484	unsigned int val;
1485	u32 uartclk = 0;
1486	int i, ret;
1487	struct sc16is7xx_port *s;
1488
1489	for (i = 0; i < devtype->nr_uart; i++)
1490		if (IS_ERR(regmaps[i]))
1491			return PTR_ERR(regmaps[i]);
1492
1493	/*
1494	 * This device does not have an identification register that would
1495	 * tell us if we are really connected to the correct device.
1496	 * The best we can do is to check if communication is at all possible.
1497	 *
1498	 * Note: regmap[0] is used in the probe function to access registers
1499	 * common to all channels/ports, as it is guaranteed to be present on
1500	 * all variants.
1501	 */
1502	ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val);
1503	if (ret < 0)
1504		return -EPROBE_DEFER;
1505
1506	/* Alloc port structure */
1507	s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
 
 
1508	if (!s) {
1509		dev_err(dev, "Error allocating port structure\n");
1510		return -ENOMEM;
1511	}
1512
1513	/* Always ask for fixed clock rate from a property. */
1514	device_property_read_u32(dev, "clock-frequency", &uartclk);
1515
1516	s->clk = devm_clk_get_optional(dev, NULL);
1517	if (IS_ERR(s->clk))
1518		return PTR_ERR(s->clk);
1519
1520	ret = clk_prepare_enable(s->clk);
1521	if (ret)
1522		return ret;
1523
1524	freq = clk_get_rate(s->clk);
1525	if (freq == 0) {
1526		if (uartclk)
1527			freq = uartclk;
1528		if (pfreq)
1529			freq = *pfreq;
1530		if (freq)
1531			dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1532		else
1533			return -EINVAL;
 
 
 
1534	}
1535
 
1536	s->devtype = devtype;
1537	dev_set_drvdata(dev, s);
1538
1539	kthread_init_worker(&s->kworker);
 
1540	s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1541				      "sc16is7xx");
1542	if (IS_ERR(s->kworker_task)) {
1543		ret = PTR_ERR(s->kworker_task);
1544		goto out_clk;
1545	}
1546	sched_set_fifo(s->kworker_task);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1547
1548	/* reset device, purging any pending irq / data */
1549	regmap_write(regmaps[0], SC16IS7XX_IOCONTROL_REG,
1550		     SC16IS7XX_IOCONTROL_SRESET_BIT);
1551
1552	for (i = 0; i < devtype->nr_uart; ++i) {
1553		s->p[i].port.line = find_first_zero_bit(sc16is7xx_lines,
1554							SC16IS7XX_MAX_DEVS);
1555		if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1556			ret = -ERANGE;
1557			goto out_ports;
1558		}
1559
1560		/* Initialize port data */
1561		s->p[i].port.dev	= dev;
1562		s->p[i].port.irq	= irq;
1563		s->p[i].port.type	= PORT_SC16IS7XX;
1564		s->p[i].port.fifosize	= SC16IS7XX_FIFO_SIZE;
1565		s->p[i].port.flags	= UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1566		s->p[i].port.iobase	= i;
1567		/*
1568		 * Use all ones as membase to make sure uart_configure_port() in
1569		 * serial_core.c does not abort for SPI/I2C devices where the
1570		 * membase address is not applicable.
1571		 */
1572		s->p[i].port.membase	= (void __iomem *)~0;
1573		s->p[i].port.iotype	= UPIO_PORT;
1574		s->p[i].port.uartclk	= freq;
1575		s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1576		s->p[i].port.rs485_supported = sc16is7xx_rs485_supported;
1577		s->p[i].port.ops	= &sc16is7xx_ops;
1578		s->p[i].old_mctrl	= 0;
1579		s->p[i].regmap		= regmaps[i];
1580
1581		mutex_init(&s->p[i].efr_lock);
1582
1583		ret = uart_get_rs485_mode(&s->p[i].port);
1584		if (ret)
1585			goto out_ports;
 
1586
1587		/* Disable all interrupts */
1588		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1589		/* Disable TX/RX */
1590		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1591				     SC16IS7XX_EFCR_RXDISABLE_BIT |
1592				     SC16IS7XX_EFCR_TXDISABLE_BIT);
1593
1594		/* Initialize kthread work structs */
1595		kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1596		kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1597		kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc);
1598
1599		/* Register port */
1600		ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1601		if (ret)
1602			goto out_ports;
1603
1604		set_bit(s->p[i].port.line, sc16is7xx_lines);
1605
1606		/* Enable EFR */
1607		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1608				     SC16IS7XX_LCR_CONF_MODE_B);
1609
1610		regcache_cache_bypass(regmaps[i], true);
1611
1612		/* Enable write access to enhanced features */
1613		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1614				     SC16IS7XX_EFR_ENABLE_BIT);
1615
1616		regcache_cache_bypass(regmaps[i], false);
1617
1618		/* Restore access to general registers */
1619		sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1620
1621		/* Go to suspend mode */
1622		sc16is7xx_power(&s->p[i].port, 0);
1623	}
1624
1625	sc16is7xx_setup_irda_ports(s);
1626
1627	ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]);
1628	if (ret)
1629		goto out_ports;
1630
1631#ifdef CONFIG_GPIOLIB
1632	ret = sc16is7xx_setup_gpio_chip(s);
1633	if (ret)
1634		goto out_ports;
1635#endif
1636
1637	/*
1638	 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1639	 * If that succeeds, we can allow sharing the interrupt as well.
1640	 * In case the interrupt controller doesn't support that, we fall
1641	 * back to a non-shared falling-edge trigger.
1642	 */
1643	ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1644					IRQF_TRIGGER_LOW | IRQF_SHARED |
1645					IRQF_ONESHOT,
1646					dev_name(dev), s);
1647	if (!ret)
1648		return 0;
1649
1650	ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1651					IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1652					dev_name(dev), s);
1653	if (!ret)
1654		return 0;
1655
1656#ifdef CONFIG_GPIOLIB
1657	if (s->gpio_valid_mask)
1658		gpiochip_remove(&s->gpio);
1659#endif
1660
1661out_ports:
1662	for (i = 0; i < devtype->nr_uart; i++)
1663		if (test_and_clear_bit(s->p[i].port.line, sc16is7xx_lines))
1664			uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1665
 
 
1666	kthread_stop(s->kworker_task);
1667
1668out_clk:
1669	clk_disable_unprepare(s->clk);
 
1670
1671	return ret;
1672}
1673
1674static void sc16is7xx_remove(struct device *dev)
1675{
1676	struct sc16is7xx_port *s = dev_get_drvdata(dev);
1677	int i;
1678
1679#ifdef CONFIG_GPIOLIB
1680	if (s->gpio_valid_mask)
1681		gpiochip_remove(&s->gpio);
1682#endif
1683
1684	for (i = 0; i < s->devtype->nr_uart; i++) {
1685		kthread_cancel_delayed_work_sync(&s->p[i].ms_work);
1686		if (test_and_clear_bit(s->p[i].port.line, sc16is7xx_lines))
1687			uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1688		sc16is7xx_power(&s->p[i].port, 0);
1689	}
1690
1691	kthread_flush_worker(&s->kworker);
1692	kthread_stop(s->kworker_task);
1693
1694	clk_disable_unprepare(s->clk);
 
 
 
1695}
1696
1697static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1698	{ .compatible = "nxp,sc16is740",	.data = &sc16is74x_devtype, },
1699	{ .compatible = "nxp,sc16is741",	.data = &sc16is74x_devtype, },
1700	{ .compatible = "nxp,sc16is750",	.data = &sc16is750_devtype, },
1701	{ .compatible = "nxp,sc16is752",	.data = &sc16is752_devtype, },
1702	{ .compatible = "nxp,sc16is760",	.data = &sc16is760_devtype, },
1703	{ .compatible = "nxp,sc16is762",	.data = &sc16is762_devtype, },
1704	{ }
1705};
1706MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1707
1708static struct regmap_config regcfg = {
1709	.reg_bits = 5,
1710	.pad_bits = 3,
1711	.val_bits = 8,
1712	.cache_type = REGCACHE_RBTREE,
1713	.volatile_reg = sc16is7xx_regmap_volatile,
1714	.precious_reg = sc16is7xx_regmap_precious,
1715	.writeable_noinc_reg = sc16is7xx_regmap_noinc,
1716	.readable_noinc_reg = sc16is7xx_regmap_noinc,
1717	.max_raw_read = SC16IS7XX_FIFO_SIZE,
1718	.max_raw_write = SC16IS7XX_FIFO_SIZE,
1719	.max_register = SC16IS7XX_EFCR_REG,
1720};
1721
1722static const char *sc16is7xx_regmap_name(u8 port_id)
1723{
1724	switch (port_id) {
1725	case 0:	return "port0";
1726	case 1:	return "port1";
1727	default:
1728		WARN_ON(true);
1729		return NULL;
1730	}
1731}
1732
1733static unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id)
1734{
1735	/* CH1,CH0 are at bits 2:1. */
1736	return port_id << 1;
1737}
1738
1739#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1740static int sc16is7xx_spi_probe(struct spi_device *spi)
1741{
1742	const struct sc16is7xx_devtype *devtype;
1743	struct regmap *regmaps[SC16IS7XX_MAX_PORTS];
1744	unsigned int i;
1745	int ret;
1746
1747	/* Setup SPI bus */
1748	spi->bits_per_word	= 8;
1749	/* For all variants, only mode 0 is supported */
1750	if ((spi->mode & SPI_MODE_X_MASK) != SPI_MODE_0)
1751		return dev_err_probe(&spi->dev, -EINVAL, "Unsupported SPI mode\n");
1752
1753	spi->mode		= spi->mode ? : SPI_MODE_0;
1754	spi->max_speed_hz	= spi->max_speed_hz ? : 4 * HZ_PER_MHZ;
1755	ret = spi_setup(spi);
1756	if (ret)
1757		return ret;
1758
1759	devtype = spi_get_device_match_data(spi);
1760	if (!devtype)
1761		return dev_err_probe(&spi->dev, -ENODEV, "Failed to match device\n");
1762
1763	for (i = 0; i < devtype->nr_uart; i++) {
1764		regcfg.name = sc16is7xx_regmap_name(i);
1765		/*
1766		 * If read_flag_mask is 0, the regmap code sets it to a default
1767		 * of 0x80. Since we specify our own mask, we must add the READ
1768		 * bit ourselves:
1769		 */
1770		regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(i) |
1771			SC16IS7XX_SPI_READ_BIT;
1772		regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(i);
1773		regmaps[i] = devm_regmap_init_spi(spi, &regcfg);
1774	}
1775
1776	return sc16is7xx_probe(&spi->dev, devtype, regmaps, spi->irq);
 
 
 
 
1777}
1778
1779static void sc16is7xx_spi_remove(struct spi_device *spi)
1780{
1781	sc16is7xx_remove(&spi->dev);
1782}
1783
1784static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1785	{ "sc16is74x",	(kernel_ulong_t)&sc16is74x_devtype, },
1786	{ "sc16is740",	(kernel_ulong_t)&sc16is74x_devtype, },
1787	{ "sc16is741",	(kernel_ulong_t)&sc16is74x_devtype, },
1788	{ "sc16is750",	(kernel_ulong_t)&sc16is750_devtype, },
1789	{ "sc16is752",	(kernel_ulong_t)&sc16is752_devtype, },
1790	{ "sc16is760",	(kernel_ulong_t)&sc16is760_devtype, },
1791	{ "sc16is762",	(kernel_ulong_t)&sc16is762_devtype, },
1792	{ }
1793};
1794
1795MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1796
1797static struct spi_driver sc16is7xx_spi_uart_driver = {
1798	.driver = {
1799		.name		= SC16IS7XX_NAME,
1800		.of_match_table	= sc16is7xx_dt_ids,
1801	},
1802	.probe		= sc16is7xx_spi_probe,
1803	.remove		= sc16is7xx_spi_remove,
1804	.id_table	= sc16is7xx_spi_id_table,
1805};
 
 
1806#endif
1807
1808#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1809static int sc16is7xx_i2c_probe(struct i2c_client *i2c)
 
1810{
1811	const struct sc16is7xx_devtype *devtype;
1812	struct regmap *regmaps[SC16IS7XX_MAX_PORTS];
1813	unsigned int i;
1814
1815	devtype = i2c_get_match_data(i2c);
1816	if (!devtype)
1817		return dev_err_probe(&i2c->dev, -ENODEV, "Failed to match device\n");
1818
1819	for (i = 0; i < devtype->nr_uart; i++) {
1820		regcfg.name = sc16is7xx_regmap_name(i);
1821		regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(i);
1822		regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(i);
1823		regmaps[i] = devm_regmap_init_i2c(i2c, &regcfg);
 
 
1824	}
1825
1826	return sc16is7xx_probe(&i2c->dev, devtype, regmaps, i2c->irq);
 
 
 
 
1827}
1828
1829static void sc16is7xx_i2c_remove(struct i2c_client *client)
1830{
1831	sc16is7xx_remove(&client->dev);
1832}
1833
1834static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1835	{ "sc16is74x",	(kernel_ulong_t)&sc16is74x_devtype, },
1836	{ "sc16is740",	(kernel_ulong_t)&sc16is74x_devtype, },
1837	{ "sc16is741",	(kernel_ulong_t)&sc16is74x_devtype, },
1838	{ "sc16is750",	(kernel_ulong_t)&sc16is750_devtype, },
1839	{ "sc16is752",	(kernel_ulong_t)&sc16is752_devtype, },
1840	{ "sc16is760",	(kernel_ulong_t)&sc16is760_devtype, },
1841	{ "sc16is762",	(kernel_ulong_t)&sc16is762_devtype, },
1842	{ }
1843};
1844MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1845
1846static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1847	.driver = {
1848		.name		= SC16IS7XX_NAME,
1849		.of_match_table	= sc16is7xx_dt_ids,
1850	},
1851	.probe		= sc16is7xx_i2c_probe,
1852	.remove		= sc16is7xx_i2c_remove,
1853	.id_table	= sc16is7xx_i2c_id_table,
1854};
1855
1856#endif
1857
1858static int __init sc16is7xx_init(void)
1859{
1860	int ret;
1861
1862	ret = uart_register_driver(&sc16is7xx_uart);
1863	if (ret) {
1864		pr_err("Registering UART driver failed\n");
1865		return ret;
1866	}
1867
1868#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1869	ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1870	if (ret < 0) {
1871		pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1872		goto err_i2c;
1873	}
1874#endif
1875
1876#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1877	ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1878	if (ret < 0) {
1879		pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1880		goto err_spi;
1881	}
1882#endif
1883	return ret;
1884
1885#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1886err_spi:
1887#endif
1888#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1889	i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1890err_i2c:
1891#endif
1892	uart_unregister_driver(&sc16is7xx_uart);
1893	return ret;
1894}
1895module_init(sc16is7xx_init);
1896
1897static void __exit sc16is7xx_exit(void)
1898{
1899#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1900	i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1901#endif
1902
1903#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1904	spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1905#endif
1906	uart_unregister_driver(&sc16is7xx_uart);
1907}
1908module_exit(sc16is7xx_exit);
1909
1910MODULE_LICENSE("GPL");
1911MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1912MODULE_DESCRIPTION("SC16IS7XX serial driver");