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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * tw68 functions to handle video data
4 *
5 * Much of this code is derived from the cx88 and sa7134 drivers, which
6 * were in turn derived from the bt87x driver. The original work was by
7 * Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab,
8 * Hans Verkuil, Andy Walls and many others. Their work is gratefully
9 * acknowledged. Full credit goes to them - any problems within this code
10 * are mine.
11 *
12 * Copyright (C) 2009 William M. Brack
13 *
14 * Refactored and updated to the latest v4l core frameworks:
15 *
16 * Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl>
17 */
18
19#include <linux/module.h>
20#include <media/v4l2-common.h>
21#include <media/v4l2-event.h>
22#include <media/videobuf2-dma-sg.h>
23
24#include "tw68.h"
25#include "tw68-reg.h"
26
27/* ------------------------------------------------------------------ */
28/* data structs for video */
29/*
30 * FIXME -
31 * Note that the saa7134 has formats, e.g. YUV420, which are classified
32 * as "planar". These affect overlay mode, and are flagged with a field
33 * ".planar" in the format. Do we need to implement this in this driver?
34 */
35static const struct tw68_format formats[] = {
36 {
37 .fourcc = V4L2_PIX_FMT_RGB555,
38 .depth = 16,
39 .twformat = ColorFormatRGB15,
40 }, {
41 .fourcc = V4L2_PIX_FMT_RGB555X,
42 .depth = 16,
43 .twformat = ColorFormatRGB15 | ColorFormatBSWAP,
44 }, {
45 .fourcc = V4L2_PIX_FMT_RGB565,
46 .depth = 16,
47 .twformat = ColorFormatRGB16,
48 }, {
49 .fourcc = V4L2_PIX_FMT_RGB565X,
50 .depth = 16,
51 .twformat = ColorFormatRGB16 | ColorFormatBSWAP,
52 }, {
53 .fourcc = V4L2_PIX_FMT_BGR24,
54 .depth = 24,
55 .twformat = ColorFormatRGB24,
56 }, {
57 .fourcc = V4L2_PIX_FMT_RGB24,
58 .depth = 24,
59 .twformat = ColorFormatRGB24 | ColorFormatBSWAP,
60 }, {
61 .fourcc = V4L2_PIX_FMT_BGR32,
62 .depth = 32,
63 .twformat = ColorFormatRGB32,
64 }, {
65 .fourcc = V4L2_PIX_FMT_RGB32,
66 .depth = 32,
67 .twformat = ColorFormatRGB32 | ColorFormatBSWAP |
68 ColorFormatWSWAP,
69 }, {
70 .fourcc = V4L2_PIX_FMT_YUYV,
71 .depth = 16,
72 .twformat = ColorFormatYUY2,
73 }, {
74 .fourcc = V4L2_PIX_FMT_UYVY,
75 .depth = 16,
76 .twformat = ColorFormatYUY2 | ColorFormatBSWAP,
77 }
78};
79#define FORMATS ARRAY_SIZE(formats)
80
81#define NORM_625_50 \
82 .h_delay = 3, \
83 .h_delay0 = 133, \
84 .h_start = 0, \
85 .h_stop = 719, \
86 .v_delay = 24, \
87 .vbi_v_start_0 = 7, \
88 .vbi_v_stop_0 = 22, \
89 .video_v_start = 24, \
90 .video_v_stop = 311, \
91 .vbi_v_start_1 = 319
92
93#define NORM_525_60 \
94 .h_delay = 8, \
95 .h_delay0 = 138, \
96 .h_start = 0, \
97 .h_stop = 719, \
98 .v_delay = 22, \
99 .vbi_v_start_0 = 10, \
100 .vbi_v_stop_0 = 21, \
101 .video_v_start = 22, \
102 .video_v_stop = 262, \
103 .vbi_v_start_1 = 273
104
105/*
106 * The following table is searched by tw68_s_std, first for a specific
107 * match, then for an entry which contains the desired id. The table
108 * entries should therefore be ordered in ascending order of specificity.
109 */
110static const struct tw68_tvnorm tvnorms[] = {
111 {
112 .name = "PAL", /* autodetect */
113 .id = V4L2_STD_PAL,
114 NORM_625_50,
115
116 .sync_control = 0x18,
117 .luma_control = 0x40,
118 .chroma_ctrl1 = 0x81,
119 .chroma_gain = 0x2a,
120 .chroma_ctrl2 = 0x06,
121 .vgate_misc = 0x1c,
122 .format = VideoFormatPALBDGHI,
123 }, {
124 .name = "NTSC",
125 .id = V4L2_STD_NTSC,
126 NORM_525_60,
127
128 .sync_control = 0x59,
129 .luma_control = 0x40,
130 .chroma_ctrl1 = 0x89,
131 .chroma_gain = 0x2a,
132 .chroma_ctrl2 = 0x0e,
133 .vgate_misc = 0x18,
134 .format = VideoFormatNTSC,
135 }, {
136 .name = "SECAM",
137 .id = V4L2_STD_SECAM,
138 NORM_625_50,
139
140 .sync_control = 0x18,
141 .luma_control = 0x1b,
142 .chroma_ctrl1 = 0xd1,
143 .chroma_gain = 0x80,
144 .chroma_ctrl2 = 0x00,
145 .vgate_misc = 0x1c,
146 .format = VideoFormatSECAM,
147 }, {
148 .name = "PAL-M",
149 .id = V4L2_STD_PAL_M,
150 NORM_525_60,
151
152 .sync_control = 0x59,
153 .luma_control = 0x40,
154 .chroma_ctrl1 = 0xb9,
155 .chroma_gain = 0x2a,
156 .chroma_ctrl2 = 0x0e,
157 .vgate_misc = 0x18,
158 .format = VideoFormatPALM,
159 }, {
160 .name = "PAL-Nc",
161 .id = V4L2_STD_PAL_Nc,
162 NORM_625_50,
163
164 .sync_control = 0x18,
165 .luma_control = 0x40,
166 .chroma_ctrl1 = 0xa1,
167 .chroma_gain = 0x2a,
168 .chroma_ctrl2 = 0x06,
169 .vgate_misc = 0x1c,
170 .format = VideoFormatPALNC,
171 }, {
172 .name = "PAL-60",
173 .id = V4L2_STD_PAL_60,
174 .h_delay = 186,
175 .h_start = 0,
176 .h_stop = 719,
177 .v_delay = 26,
178 .video_v_start = 23,
179 .video_v_stop = 262,
180 .vbi_v_start_0 = 10,
181 .vbi_v_stop_0 = 21,
182 .vbi_v_start_1 = 273,
183
184 .sync_control = 0x18,
185 .luma_control = 0x40,
186 .chroma_ctrl1 = 0x81,
187 .chroma_gain = 0x2a,
188 .chroma_ctrl2 = 0x06,
189 .vgate_misc = 0x1c,
190 .format = VideoFormatPAL60,
191 }
192};
193#define TVNORMS ARRAY_SIZE(tvnorms)
194
195static const struct tw68_format *format_by_fourcc(unsigned int fourcc)
196{
197 unsigned int i;
198
199 for (i = 0; i < FORMATS; i++)
200 if (formats[i].fourcc == fourcc)
201 return formats+i;
202 return NULL;
203}
204
205
206/* ------------------------------------------------------------------ */
207/*
208 * Note that the cropping rectangles are described in terms of a single
209 * frame, i.e. line positions are only 1/2 the interlaced equivalent
210 */
211static void set_tvnorm(struct tw68_dev *dev, const struct tw68_tvnorm *norm)
212{
213 if (norm != dev->tvnorm) {
214 dev->width = 720;
215 dev->height = (norm->id & V4L2_STD_525_60) ? 480 : 576;
216 dev->tvnorm = norm;
217 tw68_set_tvnorm_hw(dev);
218 }
219}
220
221/*
222 * tw68_set_scale
223 *
224 * Scaling and Cropping for video decoding
225 *
226 * We are working with 3 values for horizontal and vertical - scale,
227 * delay and active.
228 *
229 * HACTIVE represent the actual number of pixels in the "usable" image,
230 * before scaling. HDELAY represents the number of pixels skipped
231 * between the start of the horizontal sync and the start of the image.
232 * HSCALE is calculated using the formula
233 * HSCALE = (HACTIVE / (#pixels desired)) * 256
234 *
235 * The vertical registers are similar, except based upon the total number
236 * of lines in the image, and the first line of the image (i.e. ignoring
237 * vertical sync and VBI).
238 *
239 * Note that the number of bytes reaching the FIFO (and hence needing
240 * to be processed by the DMAP program) is completely dependent upon
241 * these values, especially HSCALE.
242 *
243 * Parameters:
244 * @dev pointer to the device structure, needed for
245 * getting current norm (as well as debug print)
246 * @width actual image width (from user buffer)
247 * @height actual image height
248 * @field indicates Top, Bottom or Interlaced
249 */
250static int tw68_set_scale(struct tw68_dev *dev, unsigned int width,
251 unsigned int height, enum v4l2_field field)
252{
253 const struct tw68_tvnorm *norm = dev->tvnorm;
254 /* set individually for debugging clarity */
255 int hactive, hdelay, hscale;
256 int vactive, vdelay, vscale;
257 int comb;
258
259 if (V4L2_FIELD_HAS_BOTH(field)) /* if field is interlaced */
260 height /= 2; /* we must set for 1-frame */
261
262 pr_debug("%s: width=%d, height=%d, both=%d\n"
263 " tvnorm h_delay=%d, h_start=%d, h_stop=%d, v_delay=%d, v_start=%d, v_stop=%d\n",
264 __func__, width, height, V4L2_FIELD_HAS_BOTH(field),
265 norm->h_delay, norm->h_start, norm->h_stop,
266 norm->v_delay, norm->video_v_start,
267 norm->video_v_stop);
268
269 switch (dev->vdecoder) {
270 case TW6800:
271 hdelay = norm->h_delay0;
272 break;
273 default:
274 hdelay = norm->h_delay;
275 break;
276 }
277
278 hdelay += norm->h_start;
279 hactive = norm->h_stop - norm->h_start + 1;
280
281 hscale = (hactive * 256) / (width);
282
283 vdelay = norm->v_delay;
284 vactive = ((norm->id & V4L2_STD_525_60) ? 524 : 624) / 2 - norm->video_v_start;
285 vscale = (vactive * 256) / height;
286
287 pr_debug("%s: %dx%d [%s%s,%s]\n", __func__,
288 width, height,
289 V4L2_FIELD_HAS_TOP(field) ? "T" : "",
290 V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "",
291 v4l2_norm_to_name(dev->tvnorm->id));
292 pr_debug("%s: hactive=%d, hdelay=%d, hscale=%d; vactive=%d, vdelay=%d, vscale=%d\n",
293 __func__,
294 hactive, hdelay, hscale, vactive, vdelay, vscale);
295
296 comb = ((vdelay & 0x300) >> 2) |
297 ((vactive & 0x300) >> 4) |
298 ((hdelay & 0x300) >> 6) |
299 ((hactive & 0x300) >> 8);
300 pr_debug("%s: setting CROP_HI=%02x, VDELAY_LO=%02x, VACTIVE_LO=%02x, HDELAY_LO=%02x, HACTIVE_LO=%02x\n",
301 __func__, comb, vdelay, vactive, hdelay, hactive);
302 tw_writeb(TW68_CROP_HI, comb);
303 tw_writeb(TW68_VDELAY_LO, vdelay & 0xff);
304 tw_writeb(TW68_VACTIVE_LO, vactive & 0xff);
305 tw_writeb(TW68_HDELAY_LO, hdelay & 0xff);
306 tw_writeb(TW68_HACTIVE_LO, hactive & 0xff);
307
308 comb = ((vscale & 0xf00) >> 4) | ((hscale & 0xf00) >> 8);
309 pr_debug("%s: setting SCALE_HI=%02x, VSCALE_LO=%02x, HSCALE_LO=%02x\n",
310 __func__, comb, vscale, hscale);
311 tw_writeb(TW68_SCALE_HI, comb);
312 tw_writeb(TW68_VSCALE_LO, vscale);
313 tw_writeb(TW68_HSCALE_LO, hscale);
314
315 return 0;
316}
317
318/* ------------------------------------------------------------------ */
319
320int tw68_video_start_dma(struct tw68_dev *dev, struct tw68_buf *buf)
321{
322 /* Set cropping and scaling */
323 tw68_set_scale(dev, dev->width, dev->height, dev->field);
324 /*
325 * Set start address for RISC program. Note that if the DMAP
326 * processor is currently running, it must be stopped before
327 * a new address can be set.
328 */
329 tw_clearl(TW68_DMAC, TW68_DMAP_EN);
330 tw_writel(TW68_DMAP_SA, buf->dma);
331 /* Clear any pending interrupts */
332 tw_writel(TW68_INTSTAT, dev->board_virqmask);
333 /* Enable the risc engine and the fifo */
334 tw_andorl(TW68_DMAC, 0xff, dev->fmt->twformat |
335 ColorFormatGamma | TW68_DMAP_EN | TW68_FIFO_EN);
336 dev->pci_irqmask |= dev->board_virqmask;
337 tw_setl(TW68_INTMASK, dev->pci_irqmask);
338 return 0;
339}
340
341/* ------------------------------------------------------------------ */
342
343/* calc max # of buffers from size (must not exceed the 4MB virtual
344 * address space per DMA channel) */
345static int tw68_buffer_count(unsigned int size, unsigned int count)
346{
347 unsigned int maxcount;
348
349 maxcount = (4 * 1024 * 1024) / roundup(size, PAGE_SIZE);
350 if (count > maxcount)
351 count = maxcount;
352 return count;
353}
354
355/* ------------------------------------------------------------- */
356/* vb2 queue operations */
357
358static int tw68_queue_setup(struct vb2_queue *q,
359 unsigned int *num_buffers, unsigned int *num_planes,
360 unsigned int sizes[], struct device *alloc_devs[])
361{
362 struct tw68_dev *dev = vb2_get_drv_priv(q);
363 unsigned int q_num_bufs = vb2_get_num_buffers(q);
364 unsigned int tot_bufs = q_num_bufs + *num_buffers;
365 unsigned size = (dev->fmt->depth * dev->width * dev->height) >> 3;
366
367 if (tot_bufs < 2)
368 tot_bufs = 2;
369 tot_bufs = tw68_buffer_count(size, tot_bufs);
370 *num_buffers = tot_bufs - q_num_bufs;
371 /*
372 * We allow create_bufs, but only if the sizeimage is >= as the
373 * current sizeimage. The tw68_buffer_count calculation becomes quite
374 * difficult otherwise.
375 */
376 if (*num_planes)
377 return sizes[0] < size ? -EINVAL : 0;
378 *num_planes = 1;
379 sizes[0] = size;
380
381 return 0;
382}
383
384/*
385 * The risc program for each buffers works as follows: it starts with a simple
386 * 'JUMP to addr + 8', which is effectively a NOP. Then the program to DMA the
387 * buffer follows and at the end we have a JUMP back to the start + 8 (skipping
388 * the initial JUMP).
389 *
390 * This is the program of the first buffer to be queued if the active list is
391 * empty and it just keeps DMAing this buffer without generating any interrupts.
392 *
393 * If a new buffer is added then the initial JUMP in the program generates an
394 * interrupt as well which signals that the previous buffer has been DMAed
395 * successfully and that it can be returned to userspace.
396 *
397 * It also sets the final jump of the previous buffer to the start of the new
398 * buffer, thus chaining the new buffer into the DMA chain. This is a single
399 * atomic u32 write, so there is no race condition.
400 *
401 * The end-result of all this that you only get an interrupt when a buffer
402 * is ready, so the control flow is very easy.
403 */
404static void tw68_buf_queue(struct vb2_buffer *vb)
405{
406 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
407 struct vb2_queue *vq = vb->vb2_queue;
408 struct tw68_dev *dev = vb2_get_drv_priv(vq);
409 struct tw68_buf *buf = container_of(vbuf, struct tw68_buf, vb);
410 struct tw68_buf *prev;
411 unsigned long flags;
412
413 spin_lock_irqsave(&dev->slock, flags);
414
415 /* append a 'JUMP to start of buffer' to the buffer risc program */
416 buf->jmp[0] = cpu_to_le32(RISC_JUMP);
417 buf->jmp[1] = cpu_to_le32(buf->dma + 8);
418
419 if (!list_empty(&dev->active)) {
420 prev = list_entry(dev->active.prev, struct tw68_buf, list);
421 buf->cpu[0] |= cpu_to_le32(RISC_INT_BIT);
422 prev->jmp[1] = cpu_to_le32(buf->dma);
423 }
424 list_add_tail(&buf->list, &dev->active);
425 spin_unlock_irqrestore(&dev->slock, flags);
426}
427
428/*
429 * buffer_prepare
430 *
431 * Set the ancillary information into the buffer structure. This
432 * includes generating the necessary risc program if it hasn't already
433 * been done for the current buffer format.
434 * The structure fh contains the details of the format requested by the
435 * user - type, width, height and #fields. This is compared with the
436 * last format set for the current buffer. If they differ, the risc
437 * code (which controls the filling of the buffer) is (re-)generated.
438 */
439static int tw68_buf_prepare(struct vb2_buffer *vb)
440{
441 int ret;
442 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
443 struct vb2_queue *vq = vb->vb2_queue;
444 struct tw68_dev *dev = vb2_get_drv_priv(vq);
445 struct tw68_buf *buf = container_of(vbuf, struct tw68_buf, vb);
446 struct sg_table *dma = vb2_dma_sg_plane_desc(vb, 0);
447 unsigned size, bpl;
448
449 size = (dev->width * dev->height * dev->fmt->depth) >> 3;
450 if (vb2_plane_size(vb, 0) < size)
451 return -EINVAL;
452 vb2_set_plane_payload(vb, 0, size);
453
454 bpl = (dev->width * dev->fmt->depth) >> 3;
455 switch (dev->field) {
456 case V4L2_FIELD_TOP:
457 ret = tw68_risc_buffer(dev->pci, buf, dma->sgl,
458 0, UNSET, bpl, 0, dev->height);
459 break;
460 case V4L2_FIELD_BOTTOM:
461 ret = tw68_risc_buffer(dev->pci, buf, dma->sgl,
462 UNSET, 0, bpl, 0, dev->height);
463 break;
464 case V4L2_FIELD_SEQ_TB:
465 ret = tw68_risc_buffer(dev->pci, buf, dma->sgl,
466 0, bpl * (dev->height >> 1),
467 bpl, 0, dev->height >> 1);
468 break;
469 case V4L2_FIELD_SEQ_BT:
470 ret = tw68_risc_buffer(dev->pci, buf, dma->sgl,
471 bpl * (dev->height >> 1), 0,
472 bpl, 0, dev->height >> 1);
473 break;
474 case V4L2_FIELD_INTERLACED:
475 default:
476 ret = tw68_risc_buffer(dev->pci, buf, dma->sgl,
477 0, bpl, bpl, bpl, dev->height >> 1);
478 break;
479 }
480 return ret;
481}
482
483static void tw68_buf_finish(struct vb2_buffer *vb)
484{
485 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
486 struct vb2_queue *vq = vb->vb2_queue;
487 struct tw68_dev *dev = vb2_get_drv_priv(vq);
488 struct tw68_buf *buf = container_of(vbuf, struct tw68_buf, vb);
489
490 if (buf->cpu)
491 dma_free_coherent(&dev->pci->dev, buf->size, buf->cpu, buf->dma);
492}
493
494static int tw68_start_streaming(struct vb2_queue *q, unsigned int count)
495{
496 struct tw68_dev *dev = vb2_get_drv_priv(q);
497 struct tw68_buf *buf =
498 container_of(dev->active.next, struct tw68_buf, list);
499
500 dev->seqnr = 0;
501 tw68_video_start_dma(dev, buf);
502 return 0;
503}
504
505static void tw68_stop_streaming(struct vb2_queue *q)
506{
507 struct tw68_dev *dev = vb2_get_drv_priv(q);
508
509 /* Stop risc & fifo */
510 tw_clearl(TW68_DMAC, TW68_DMAP_EN | TW68_FIFO_EN);
511 while (!list_empty(&dev->active)) {
512 struct tw68_buf *buf =
513 container_of(dev->active.next, struct tw68_buf, list);
514
515 list_del(&buf->list);
516 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
517 }
518}
519
520static const struct vb2_ops tw68_video_qops = {
521 .queue_setup = tw68_queue_setup,
522 .buf_queue = tw68_buf_queue,
523 .buf_prepare = tw68_buf_prepare,
524 .buf_finish = tw68_buf_finish,
525 .start_streaming = tw68_start_streaming,
526 .stop_streaming = tw68_stop_streaming,
527 .wait_prepare = vb2_ops_wait_prepare,
528 .wait_finish = vb2_ops_wait_finish,
529};
530
531/* ------------------------------------------------------------------ */
532
533static int tw68_s_ctrl(struct v4l2_ctrl *ctrl)
534{
535 struct tw68_dev *dev =
536 container_of(ctrl->handler, struct tw68_dev, hdl);
537
538 switch (ctrl->id) {
539 case V4L2_CID_BRIGHTNESS:
540 tw_writeb(TW68_BRIGHT, ctrl->val);
541 break;
542 case V4L2_CID_HUE:
543 tw_writeb(TW68_HUE, ctrl->val);
544 break;
545 case V4L2_CID_CONTRAST:
546 tw_writeb(TW68_CONTRAST, ctrl->val);
547 break;
548 case V4L2_CID_SATURATION:
549 tw_writeb(TW68_SAT_U, ctrl->val);
550 tw_writeb(TW68_SAT_V, ctrl->val);
551 break;
552 case V4L2_CID_COLOR_KILLER:
553 if (ctrl->val)
554 tw_andorb(TW68_MISC2, 0xe0, 0xe0);
555 else
556 tw_andorb(TW68_MISC2, 0xe0, 0x00);
557 break;
558 case V4L2_CID_CHROMA_AGC:
559 if (ctrl->val)
560 tw_andorb(TW68_LOOP, 0x30, 0x20);
561 else
562 tw_andorb(TW68_LOOP, 0x30, 0x00);
563 break;
564 }
565 return 0;
566}
567
568/* ------------------------------------------------------------------ */
569
570/*
571 * Note that this routine returns what is stored in the fh structure, and
572 * does not interrogate any of the device registers.
573 */
574static int tw68_g_fmt_vid_cap(struct file *file, void *priv,
575 struct v4l2_format *f)
576{
577 struct tw68_dev *dev = video_drvdata(file);
578
579 f->fmt.pix.width = dev->width;
580 f->fmt.pix.height = dev->height;
581 f->fmt.pix.field = dev->field;
582 f->fmt.pix.pixelformat = dev->fmt->fourcc;
583 f->fmt.pix.bytesperline =
584 (f->fmt.pix.width * (dev->fmt->depth)) >> 3;
585 f->fmt.pix.sizeimage =
586 f->fmt.pix.height * f->fmt.pix.bytesperline;
587 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
588 return 0;
589}
590
591static int tw68_try_fmt_vid_cap(struct file *file, void *priv,
592 struct v4l2_format *f)
593{
594 struct tw68_dev *dev = video_drvdata(file);
595 const struct tw68_format *fmt;
596 enum v4l2_field field;
597 unsigned int maxh;
598
599 fmt = format_by_fourcc(f->fmt.pix.pixelformat);
600 if (NULL == fmt)
601 return -EINVAL;
602
603 field = f->fmt.pix.field;
604 maxh = (dev->tvnorm->id & V4L2_STD_525_60) ? 480 : 576;
605
606 switch (field) {
607 case V4L2_FIELD_TOP:
608 case V4L2_FIELD_BOTTOM:
609 break;
610 case V4L2_FIELD_INTERLACED:
611 case V4L2_FIELD_SEQ_BT:
612 case V4L2_FIELD_SEQ_TB:
613 maxh = maxh * 2;
614 break;
615 default:
616 field = (f->fmt.pix.height > maxh / 2)
617 ? V4L2_FIELD_INTERLACED
618 : V4L2_FIELD_BOTTOM;
619 break;
620 }
621
622 f->fmt.pix.field = field;
623 if (f->fmt.pix.width < 48)
624 f->fmt.pix.width = 48;
625 if (f->fmt.pix.height < 32)
626 f->fmt.pix.height = 32;
627 if (f->fmt.pix.width > 720)
628 f->fmt.pix.width = 720;
629 if (f->fmt.pix.height > maxh)
630 f->fmt.pix.height = maxh;
631 f->fmt.pix.width &= ~0x03;
632 f->fmt.pix.bytesperline =
633 (f->fmt.pix.width * (fmt->depth)) >> 3;
634 f->fmt.pix.sizeimage =
635 f->fmt.pix.height * f->fmt.pix.bytesperline;
636 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
637 return 0;
638}
639
640/*
641 * Note that tw68_s_fmt_vid_cap sets the information into the fh structure,
642 * and it will be used for all future new buffers. However, there could be
643 * some number of buffers on the "active" chain which will be filled before
644 * the change takes place.
645 */
646static int tw68_s_fmt_vid_cap(struct file *file, void *priv,
647 struct v4l2_format *f)
648{
649 struct tw68_dev *dev = video_drvdata(file);
650 int err;
651
652 err = tw68_try_fmt_vid_cap(file, priv, f);
653 if (0 != err)
654 return err;
655
656 dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
657 dev->width = f->fmt.pix.width;
658 dev->height = f->fmt.pix.height;
659 dev->field = f->fmt.pix.field;
660 return 0;
661}
662
663static int tw68_enum_input(struct file *file, void *priv,
664 struct v4l2_input *i)
665{
666 struct tw68_dev *dev = video_drvdata(file);
667 unsigned int n;
668
669 n = i->index;
670 if (n >= TW68_INPUT_MAX)
671 return -EINVAL;
672 i->index = n;
673 i->type = V4L2_INPUT_TYPE_CAMERA;
674 snprintf(i->name, sizeof(i->name), "Composite %d", n);
675
676 /* If the query is for the current input, get live data */
677 if (n == dev->input) {
678 int v1 = tw_readb(TW68_STATUS1);
679 int v2 = tw_readb(TW68_MVSN);
680
681 if (0 != (v1 & (1 << 7)))
682 i->status |= V4L2_IN_ST_NO_SYNC;
683 if (0 != (v1 & (1 << 6)))
684 i->status |= V4L2_IN_ST_NO_H_LOCK;
685 if (0 != (v1 & (1 << 2)))
686 i->status |= V4L2_IN_ST_NO_SIGNAL;
687 if (0 != (v1 & 1 << 1))
688 i->status |= V4L2_IN_ST_NO_COLOR;
689 if (0 != (v2 & (1 << 2)))
690 i->status |= V4L2_IN_ST_MACROVISION;
691 }
692 i->std = video_devdata(file)->tvnorms;
693 return 0;
694}
695
696static int tw68_g_input(struct file *file, void *priv, unsigned int *i)
697{
698 struct tw68_dev *dev = video_drvdata(file);
699
700 *i = dev->input;
701 return 0;
702}
703
704static int tw68_s_input(struct file *file, void *priv, unsigned int i)
705{
706 struct tw68_dev *dev = video_drvdata(file);
707
708 if (i >= TW68_INPUT_MAX)
709 return -EINVAL;
710 dev->input = i;
711 tw_andorb(TW68_INFORM, 0x03 << 2, dev->input << 2);
712 return 0;
713}
714
715static int tw68_querycap(struct file *file, void *priv,
716 struct v4l2_capability *cap)
717{
718 strscpy(cap->driver, "tw68", sizeof(cap->driver));
719 strscpy(cap->card, "Techwell Capture Card",
720 sizeof(cap->card));
721 return 0;
722}
723
724static int tw68_s_std(struct file *file, void *priv, v4l2_std_id id)
725{
726 struct tw68_dev *dev = video_drvdata(file);
727 unsigned int i;
728
729 if (vb2_is_busy(&dev->vidq))
730 return -EBUSY;
731
732 /* Look for match on complete norm id (may have mult bits) */
733 for (i = 0; i < TVNORMS; i++) {
734 if (id == tvnorms[i].id)
735 break;
736 }
737
738 /* If no exact match, look for norm which contains this one */
739 if (i == TVNORMS) {
740 for (i = 0; i < TVNORMS; i++)
741 if (id & tvnorms[i].id)
742 break;
743 }
744 /* If still not matched, give up */
745 if (i == TVNORMS)
746 return -EINVAL;
747
748 set_tvnorm(dev, &tvnorms[i]); /* do the actual setting */
749 return 0;
750}
751
752static int tw68_g_std(struct file *file, void *priv, v4l2_std_id *id)
753{
754 struct tw68_dev *dev = video_drvdata(file);
755
756 *id = dev->tvnorm->id;
757 return 0;
758}
759
760static int tw68_enum_fmt_vid_cap(struct file *file, void *priv,
761 struct v4l2_fmtdesc *f)
762{
763 if (f->index >= FORMATS)
764 return -EINVAL;
765
766 f->pixelformat = formats[f->index].fourcc;
767
768 return 0;
769}
770
771/*
772 * Used strictly for internal development and debugging, this routine
773 * prints out the current register contents for the tw68xx device.
774 */
775static void tw68_dump_regs(struct tw68_dev *dev)
776{
777 unsigned char line[80];
778 int i, j, k;
779 unsigned char *cptr;
780
781 pr_info("Full dump of TW68 registers:\n");
782 /* First we do the PCI regs, 8 4-byte regs per line */
783 for (i = 0; i < 0x100; i += 32) {
784 cptr = line;
785 cptr += sprintf(cptr, "%03x ", i);
786 /* j steps through the next 4 words */
787 for (j = i; j < i + 16; j += 4)
788 cptr += sprintf(cptr, "%08x ", tw_readl(j));
789 *cptr++ = ' ';
790 for (; j < i + 32; j += 4)
791 cptr += sprintf(cptr, "%08x ", tw_readl(j));
792 *cptr++ = '\n';
793 *cptr = 0;
794 pr_info("%s", line);
795 }
796 /* Next the control regs, which are single-byte, address mod 4 */
797 while (i < 0x400) {
798 cptr = line;
799 cptr += sprintf(cptr, "%03x ", i);
800 /* Print out 4 groups of 4 bytes */
801 for (j = 0; j < 4; j++) {
802 for (k = 0; k < 4; k++) {
803 cptr += sprintf(cptr, "%02x ",
804 tw_readb(i));
805 i += 4;
806 }
807 *cptr++ = ' ';
808 }
809 *cptr++ = '\n';
810 *cptr = 0;
811 pr_info("%s", line);
812 }
813}
814
815static int vidioc_log_status(struct file *file, void *priv)
816{
817 struct tw68_dev *dev = video_drvdata(file);
818
819 tw68_dump_regs(dev);
820 return v4l2_ctrl_log_status(file, priv);
821}
822
823#ifdef CONFIG_VIDEO_ADV_DEBUG
824static int vidioc_g_register(struct file *file, void *priv,
825 struct v4l2_dbg_register *reg)
826{
827 struct tw68_dev *dev = video_drvdata(file);
828
829 if (reg->size == 1)
830 reg->val = tw_readb(reg->reg);
831 else
832 reg->val = tw_readl(reg->reg);
833 return 0;
834}
835
836static int vidioc_s_register(struct file *file, void *priv,
837 const struct v4l2_dbg_register *reg)
838{
839 struct tw68_dev *dev = video_drvdata(file);
840
841 if (reg->size == 1)
842 tw_writeb(reg->reg, reg->val);
843 else
844 tw_writel(reg->reg & 0xffff, reg->val);
845 return 0;
846}
847#endif
848
849static const struct v4l2_ctrl_ops tw68_ctrl_ops = {
850 .s_ctrl = tw68_s_ctrl,
851};
852
853static const struct v4l2_file_operations video_fops = {
854 .owner = THIS_MODULE,
855 .open = v4l2_fh_open,
856 .release = vb2_fop_release,
857 .read = vb2_fop_read,
858 .poll = vb2_fop_poll,
859 .mmap = vb2_fop_mmap,
860 .unlocked_ioctl = video_ioctl2,
861};
862
863static const struct v4l2_ioctl_ops video_ioctl_ops = {
864 .vidioc_querycap = tw68_querycap,
865 .vidioc_enum_fmt_vid_cap = tw68_enum_fmt_vid_cap,
866 .vidioc_reqbufs = vb2_ioctl_reqbufs,
867 .vidioc_create_bufs = vb2_ioctl_create_bufs,
868 .vidioc_querybuf = vb2_ioctl_querybuf,
869 .vidioc_qbuf = vb2_ioctl_qbuf,
870 .vidioc_dqbuf = vb2_ioctl_dqbuf,
871 .vidioc_s_std = tw68_s_std,
872 .vidioc_g_std = tw68_g_std,
873 .vidioc_enum_input = tw68_enum_input,
874 .vidioc_g_input = tw68_g_input,
875 .vidioc_s_input = tw68_s_input,
876 .vidioc_streamon = vb2_ioctl_streamon,
877 .vidioc_streamoff = vb2_ioctl_streamoff,
878 .vidioc_g_fmt_vid_cap = tw68_g_fmt_vid_cap,
879 .vidioc_try_fmt_vid_cap = tw68_try_fmt_vid_cap,
880 .vidioc_s_fmt_vid_cap = tw68_s_fmt_vid_cap,
881 .vidioc_log_status = vidioc_log_status,
882 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
883 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
884#ifdef CONFIG_VIDEO_ADV_DEBUG
885 .vidioc_g_register = vidioc_g_register,
886 .vidioc_s_register = vidioc_s_register,
887#endif
888};
889
890static const struct video_device tw68_video_template = {
891 .name = "tw68_video",
892 .fops = &video_fops,
893 .ioctl_ops = &video_ioctl_ops,
894 .release = video_device_release_empty,
895 .tvnorms = TW68_NORMS,
896 .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
897 V4L2_CAP_STREAMING,
898};
899
900/* ------------------------------------------------------------------ */
901/* exported stuff */
902void tw68_set_tvnorm_hw(struct tw68_dev *dev)
903{
904 tw_andorb(TW68_SDT, 0x07, dev->tvnorm->format);
905}
906
907int tw68_video_init1(struct tw68_dev *dev)
908{
909 struct v4l2_ctrl_handler *hdl = &dev->hdl;
910
911 v4l2_ctrl_handler_init(hdl, 6);
912 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
913 V4L2_CID_BRIGHTNESS, -128, 127, 1, 20);
914 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
915 V4L2_CID_CONTRAST, 0, 255, 1, 100);
916 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
917 V4L2_CID_SATURATION, 0, 255, 1, 128);
918 /* NTSC only */
919 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
920 V4L2_CID_HUE, -128, 127, 1, 0);
921 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
922 V4L2_CID_COLOR_KILLER, 0, 1, 1, 0);
923 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
924 V4L2_CID_CHROMA_AGC, 0, 1, 1, 1);
925 if (hdl->error) {
926 v4l2_ctrl_handler_free(hdl);
927 return hdl->error;
928 }
929 dev->v4l2_dev.ctrl_handler = hdl;
930 v4l2_ctrl_handler_setup(hdl);
931 return 0;
932}
933
934int tw68_video_init2(struct tw68_dev *dev, int video_nr)
935{
936 int ret;
937
938 set_tvnorm(dev, &tvnorms[0]);
939
940 dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24);
941 dev->width = 720;
942 dev->height = 576;
943 dev->field = V4L2_FIELD_INTERLACED;
944
945 INIT_LIST_HEAD(&dev->active);
946 dev->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
947 dev->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
948 dev->vidq.io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ | VB2_DMABUF;
949 dev->vidq.ops = &tw68_video_qops;
950 dev->vidq.mem_ops = &vb2_dma_sg_memops;
951 dev->vidq.drv_priv = dev;
952 dev->vidq.gfp_flags = __GFP_DMA32 | __GFP_KSWAPD_RECLAIM;
953 dev->vidq.buf_struct_size = sizeof(struct tw68_buf);
954 dev->vidq.lock = &dev->lock;
955 dev->vidq.min_queued_buffers = 2;
956 dev->vidq.dev = &dev->pci->dev;
957 ret = vb2_queue_init(&dev->vidq);
958 if (ret)
959 return ret;
960 dev->vdev = tw68_video_template;
961 dev->vdev.v4l2_dev = &dev->v4l2_dev;
962 dev->vdev.lock = &dev->lock;
963 dev->vdev.queue = &dev->vidq;
964 video_set_drvdata(&dev->vdev, dev);
965 return video_register_device(&dev->vdev, VFL_TYPE_VIDEO, video_nr);
966}
967
968/*
969 * tw68_irq_video_done
970 */
971void tw68_irq_video_done(struct tw68_dev *dev, unsigned long status)
972{
973 __u32 reg;
974
975 /* reset interrupts handled by this routine */
976 tw_writel(TW68_INTSTAT, status);
977 /*
978 * Check most likely first
979 *
980 * DMAPI shows we have reached the end of the risc code
981 * for the current buffer.
982 */
983 if (status & TW68_DMAPI) {
984 struct tw68_buf *buf;
985
986 spin_lock(&dev->slock);
987 buf = list_entry(dev->active.next, struct tw68_buf, list);
988 list_del(&buf->list);
989 spin_unlock(&dev->slock);
990 buf->vb.vb2_buf.timestamp = ktime_get_ns();
991 buf->vb.field = dev->field;
992 buf->vb.sequence = dev->seqnr++;
993 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
994 status &= ~(TW68_DMAPI);
995 if (0 == status)
996 return;
997 }
998 if (status & (TW68_VLOCK | TW68_HLOCK))
999 dev_dbg(&dev->pci->dev, "Lost sync\n");
1000 if (status & TW68_PABORT)
1001 dev_err(&dev->pci->dev, "PABORT interrupt\n");
1002 if (status & TW68_DMAPERR)
1003 dev_err(&dev->pci->dev, "DMAPERR interrupt\n");
1004 /*
1005 * On TW6800, FDMIS is apparently generated if video input is switched
1006 * during operation. Therefore, it is not enabled for that chip.
1007 */
1008 if (status & TW68_FDMIS)
1009 dev_dbg(&dev->pci->dev, "FDMIS interrupt\n");
1010 if (status & TW68_FFOF) {
1011 /* probably a logic error */
1012 reg = tw_readl(TW68_DMAC) & TW68_FIFO_EN;
1013 tw_clearl(TW68_DMAC, TW68_FIFO_EN);
1014 dev_dbg(&dev->pci->dev, "FFOF interrupt\n");
1015 tw_setl(TW68_DMAC, reg);
1016 }
1017 if (status & TW68_FFERR)
1018 dev_dbg(&dev->pci->dev, "FFERR interrupt\n");
1019}
1/*
2 * tw68 functions to handle video data
3 *
4 * Much of this code is derived from the cx88 and sa7134 drivers, which
5 * were in turn derived from the bt87x driver. The original work was by
6 * Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab,
7 * Hans Verkuil, Andy Walls and many others. Their work is gratefully
8 * acknowledged. Full credit goes to them - any problems within this code
9 * are mine.
10 *
11 * Copyright (C) 2009 William M. Brack
12 *
13 * Refactored and updated to the latest v4l core frameworks:
14 *
15 * Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl>
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 */
27
28#include <linux/module.h>
29#include <media/v4l2-common.h>
30#include <media/v4l2-event.h>
31#include <media/videobuf2-dma-sg.h>
32
33#include "tw68.h"
34#include "tw68-reg.h"
35
36/* ------------------------------------------------------------------ */
37/* data structs for video */
38/*
39 * FIXME -
40 * Note that the saa7134 has formats, e.g. YUV420, which are classified
41 * as "planar". These affect overlay mode, and are flagged with a field
42 * ".planar" in the format. Do we need to implement this in this driver?
43 */
44static const struct tw68_format formats[] = {
45 {
46 .name = "15 bpp RGB, le",
47 .fourcc = V4L2_PIX_FMT_RGB555,
48 .depth = 16,
49 .twformat = ColorFormatRGB15,
50 }, {
51 .name = "15 bpp RGB, be",
52 .fourcc = V4L2_PIX_FMT_RGB555X,
53 .depth = 16,
54 .twformat = ColorFormatRGB15 | ColorFormatBSWAP,
55 }, {
56 .name = "16 bpp RGB, le",
57 .fourcc = V4L2_PIX_FMT_RGB565,
58 .depth = 16,
59 .twformat = ColorFormatRGB16,
60 }, {
61 .name = "16 bpp RGB, be",
62 .fourcc = V4L2_PIX_FMT_RGB565X,
63 .depth = 16,
64 .twformat = ColorFormatRGB16 | ColorFormatBSWAP,
65 }, {
66 .name = "24 bpp RGB, le",
67 .fourcc = V4L2_PIX_FMT_BGR24,
68 .depth = 24,
69 .twformat = ColorFormatRGB24,
70 }, {
71 .name = "24 bpp RGB, be",
72 .fourcc = V4L2_PIX_FMT_RGB24,
73 .depth = 24,
74 .twformat = ColorFormatRGB24 | ColorFormatBSWAP,
75 }, {
76 .name = "32 bpp RGB, le",
77 .fourcc = V4L2_PIX_FMT_BGR32,
78 .depth = 32,
79 .twformat = ColorFormatRGB32,
80 }, {
81 .name = "32 bpp RGB, be",
82 .fourcc = V4L2_PIX_FMT_RGB32,
83 .depth = 32,
84 .twformat = ColorFormatRGB32 | ColorFormatBSWAP |
85 ColorFormatWSWAP,
86 }, {
87 .name = "4:2:2 packed, YUYV",
88 .fourcc = V4L2_PIX_FMT_YUYV,
89 .depth = 16,
90 .twformat = ColorFormatYUY2,
91 }, {
92 .name = "4:2:2 packed, UYVY",
93 .fourcc = V4L2_PIX_FMT_UYVY,
94 .depth = 16,
95 .twformat = ColorFormatYUY2 | ColorFormatBSWAP,
96 }
97};
98#define FORMATS ARRAY_SIZE(formats)
99
100#define NORM_625_50 \
101 .h_delay = 3, \
102 .h_delay0 = 133, \
103 .h_start = 0, \
104 .h_stop = 719, \
105 .v_delay = 24, \
106 .vbi_v_start_0 = 7, \
107 .vbi_v_stop_0 = 22, \
108 .video_v_start = 24, \
109 .video_v_stop = 311, \
110 .vbi_v_start_1 = 319
111
112#define NORM_525_60 \
113 .h_delay = 8, \
114 .h_delay0 = 138, \
115 .h_start = 0, \
116 .h_stop = 719, \
117 .v_delay = 22, \
118 .vbi_v_start_0 = 10, \
119 .vbi_v_stop_0 = 21, \
120 .video_v_start = 22, \
121 .video_v_stop = 262, \
122 .vbi_v_start_1 = 273
123
124/*
125 * The following table is searched by tw68_s_std, first for a specific
126 * match, then for an entry which contains the desired id. The table
127 * entries should therefore be ordered in ascending order of specificity.
128 */
129static const struct tw68_tvnorm tvnorms[] = {
130 {
131 .name = "PAL", /* autodetect */
132 .id = V4L2_STD_PAL,
133 NORM_625_50,
134
135 .sync_control = 0x18,
136 .luma_control = 0x40,
137 .chroma_ctrl1 = 0x81,
138 .chroma_gain = 0x2a,
139 .chroma_ctrl2 = 0x06,
140 .vgate_misc = 0x1c,
141 .format = VideoFormatPALBDGHI,
142 }, {
143 .name = "NTSC",
144 .id = V4L2_STD_NTSC,
145 NORM_525_60,
146
147 .sync_control = 0x59,
148 .luma_control = 0x40,
149 .chroma_ctrl1 = 0x89,
150 .chroma_gain = 0x2a,
151 .chroma_ctrl2 = 0x0e,
152 .vgate_misc = 0x18,
153 .format = VideoFormatNTSC,
154 }, {
155 .name = "SECAM",
156 .id = V4L2_STD_SECAM,
157 NORM_625_50,
158
159 .sync_control = 0x18,
160 .luma_control = 0x1b,
161 .chroma_ctrl1 = 0xd1,
162 .chroma_gain = 0x80,
163 .chroma_ctrl2 = 0x00,
164 .vgate_misc = 0x1c,
165 .format = VideoFormatSECAM,
166 }, {
167 .name = "PAL-M",
168 .id = V4L2_STD_PAL_M,
169 NORM_525_60,
170
171 .sync_control = 0x59,
172 .luma_control = 0x40,
173 .chroma_ctrl1 = 0xb9,
174 .chroma_gain = 0x2a,
175 .chroma_ctrl2 = 0x0e,
176 .vgate_misc = 0x18,
177 .format = VideoFormatPALM,
178 }, {
179 .name = "PAL-Nc",
180 .id = V4L2_STD_PAL_Nc,
181 NORM_625_50,
182
183 .sync_control = 0x18,
184 .luma_control = 0x40,
185 .chroma_ctrl1 = 0xa1,
186 .chroma_gain = 0x2a,
187 .chroma_ctrl2 = 0x06,
188 .vgate_misc = 0x1c,
189 .format = VideoFormatPALNC,
190 }, {
191 .name = "PAL-60",
192 .id = V4L2_STD_PAL_60,
193 .h_delay = 186,
194 .h_start = 0,
195 .h_stop = 719,
196 .v_delay = 26,
197 .video_v_start = 23,
198 .video_v_stop = 262,
199 .vbi_v_start_0 = 10,
200 .vbi_v_stop_0 = 21,
201 .vbi_v_start_1 = 273,
202
203 .sync_control = 0x18,
204 .luma_control = 0x40,
205 .chroma_ctrl1 = 0x81,
206 .chroma_gain = 0x2a,
207 .chroma_ctrl2 = 0x06,
208 .vgate_misc = 0x1c,
209 .format = VideoFormatPAL60,
210 }
211};
212#define TVNORMS ARRAY_SIZE(tvnorms)
213
214static const struct tw68_format *format_by_fourcc(unsigned int fourcc)
215{
216 unsigned int i;
217
218 for (i = 0; i < FORMATS; i++)
219 if (formats[i].fourcc == fourcc)
220 return formats+i;
221 return NULL;
222}
223
224
225/* ------------------------------------------------------------------ */
226/*
227 * Note that the cropping rectangles are described in terms of a single
228 * frame, i.e. line positions are only 1/2 the interlaced equivalent
229 */
230static void set_tvnorm(struct tw68_dev *dev, const struct tw68_tvnorm *norm)
231{
232 if (norm != dev->tvnorm) {
233 dev->width = 720;
234 dev->height = (norm->id & V4L2_STD_525_60) ? 480 : 576;
235 dev->tvnorm = norm;
236 tw68_set_tvnorm_hw(dev);
237 }
238}
239
240/*
241 * tw68_set_scale
242 *
243 * Scaling and Cropping for video decoding
244 *
245 * We are working with 3 values for horizontal and vertical - scale,
246 * delay and active.
247 *
248 * HACTIVE represent the actual number of pixels in the "usable" image,
249 * before scaling. HDELAY represents the number of pixels skipped
250 * between the start of the horizontal sync and the start of the image.
251 * HSCALE is calculated using the formula
252 * HSCALE = (HACTIVE / (#pixels desired)) * 256
253 *
254 * The vertical registers are similar, except based upon the total number
255 * of lines in the image, and the first line of the image (i.e. ignoring
256 * vertical sync and VBI).
257 *
258 * Note that the number of bytes reaching the FIFO (and hence needing
259 * to be processed by the DMAP program) is completely dependent upon
260 * these values, especially HSCALE.
261 *
262 * Parameters:
263 * @dev pointer to the device structure, needed for
264 * getting current norm (as well as debug print)
265 * @width actual image width (from user buffer)
266 * @height actual image height
267 * @field indicates Top, Bottom or Interlaced
268 */
269static int tw68_set_scale(struct tw68_dev *dev, unsigned int width,
270 unsigned int height, enum v4l2_field field)
271{
272 const struct tw68_tvnorm *norm = dev->tvnorm;
273 /* set individually for debugging clarity */
274 int hactive, hdelay, hscale;
275 int vactive, vdelay, vscale;
276 int comb;
277
278 if (V4L2_FIELD_HAS_BOTH(field)) /* if field is interlaced */
279 height /= 2; /* we must set for 1-frame */
280
281 pr_debug("%s: width=%d, height=%d, both=%d\n"
282 " tvnorm h_delay=%d, h_start=%d, h_stop=%d, v_delay=%d, v_start=%d, v_stop=%d\n",
283 __func__, width, height, V4L2_FIELD_HAS_BOTH(field),
284 norm->h_delay, norm->h_start, norm->h_stop,
285 norm->v_delay, norm->video_v_start,
286 norm->video_v_stop);
287
288 switch (dev->vdecoder) {
289 case TW6800:
290 hdelay = norm->h_delay0;
291 break;
292 default:
293 hdelay = norm->h_delay;
294 break;
295 }
296
297 hdelay += norm->h_start;
298 hactive = norm->h_stop - norm->h_start + 1;
299
300 hscale = (hactive * 256) / (width);
301
302 vdelay = norm->v_delay;
303 vactive = ((norm->id & V4L2_STD_525_60) ? 524 : 624) / 2 - norm->video_v_start;
304 vscale = (vactive * 256) / height;
305
306 pr_debug("%s: %dx%d [%s%s,%s]\n", __func__,
307 width, height,
308 V4L2_FIELD_HAS_TOP(field) ? "T" : "",
309 V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "",
310 v4l2_norm_to_name(dev->tvnorm->id));
311 pr_debug("%s: hactive=%d, hdelay=%d, hscale=%d; vactive=%d, vdelay=%d, vscale=%d\n",
312 __func__,
313 hactive, hdelay, hscale, vactive, vdelay, vscale);
314
315 comb = ((vdelay & 0x300) >> 2) |
316 ((vactive & 0x300) >> 4) |
317 ((hdelay & 0x300) >> 6) |
318 ((hactive & 0x300) >> 8);
319 pr_debug("%s: setting CROP_HI=%02x, VDELAY_LO=%02x, VACTIVE_LO=%02x, HDELAY_LO=%02x, HACTIVE_LO=%02x\n",
320 __func__, comb, vdelay, vactive, hdelay, hactive);
321 tw_writeb(TW68_CROP_HI, comb);
322 tw_writeb(TW68_VDELAY_LO, vdelay & 0xff);
323 tw_writeb(TW68_VACTIVE_LO, vactive & 0xff);
324 tw_writeb(TW68_HDELAY_LO, hdelay & 0xff);
325 tw_writeb(TW68_HACTIVE_LO, hactive & 0xff);
326
327 comb = ((vscale & 0xf00) >> 4) | ((hscale & 0xf00) >> 8);
328 pr_debug("%s: setting SCALE_HI=%02x, VSCALE_LO=%02x, HSCALE_LO=%02x\n",
329 __func__, comb, vscale, hscale);
330 tw_writeb(TW68_SCALE_HI, comb);
331 tw_writeb(TW68_VSCALE_LO, vscale);
332 tw_writeb(TW68_HSCALE_LO, hscale);
333
334 return 0;
335}
336
337/* ------------------------------------------------------------------ */
338
339int tw68_video_start_dma(struct tw68_dev *dev, struct tw68_buf *buf)
340{
341 /* Set cropping and scaling */
342 tw68_set_scale(dev, dev->width, dev->height, dev->field);
343 /*
344 * Set start address for RISC program. Note that if the DMAP
345 * processor is currently running, it must be stopped before
346 * a new address can be set.
347 */
348 tw_clearl(TW68_DMAC, TW68_DMAP_EN);
349 tw_writel(TW68_DMAP_SA, buf->dma);
350 /* Clear any pending interrupts */
351 tw_writel(TW68_INTSTAT, dev->board_virqmask);
352 /* Enable the risc engine and the fifo */
353 tw_andorl(TW68_DMAC, 0xff, dev->fmt->twformat |
354 ColorFormatGamma | TW68_DMAP_EN | TW68_FIFO_EN);
355 dev->pci_irqmask |= dev->board_virqmask;
356 tw_setl(TW68_INTMASK, dev->pci_irqmask);
357 return 0;
358}
359
360/* ------------------------------------------------------------------ */
361
362/* calc max # of buffers from size (must not exceed the 4MB virtual
363 * address space per DMA channel) */
364static int tw68_buffer_count(unsigned int size, unsigned int count)
365{
366 unsigned int maxcount;
367
368 maxcount = (4 * 1024 * 1024) / roundup(size, PAGE_SIZE);
369 if (count > maxcount)
370 count = maxcount;
371 return count;
372}
373
374/* ------------------------------------------------------------- */
375/* vb2 queue operations */
376
377static int tw68_queue_setup(struct vb2_queue *q,
378 unsigned int *num_buffers, unsigned int *num_planes,
379 unsigned int sizes[], struct device *alloc_devs[])
380{
381 struct tw68_dev *dev = vb2_get_drv_priv(q);
382 unsigned tot_bufs = q->num_buffers + *num_buffers;
383 unsigned size = (dev->fmt->depth * dev->width * dev->height) >> 3;
384
385 if (tot_bufs < 2)
386 tot_bufs = 2;
387 tot_bufs = tw68_buffer_count(size, tot_bufs);
388 *num_buffers = tot_bufs - q->num_buffers;
389 /*
390 * We allow create_bufs, but only if the sizeimage is >= as the
391 * current sizeimage. The tw68_buffer_count calculation becomes quite
392 * difficult otherwise.
393 */
394 if (*num_planes)
395 return sizes[0] < size ? -EINVAL : 0;
396 *num_planes = 1;
397 sizes[0] = size;
398
399 return 0;
400}
401
402/*
403 * The risc program for each buffers works as follows: it starts with a simple
404 * 'JUMP to addr + 8', which is effectively a NOP. Then the program to DMA the
405 * buffer follows and at the end we have a JUMP back to the start + 8 (skipping
406 * the initial JUMP).
407 *
408 * This is the program of the first buffer to be queued if the active list is
409 * empty and it just keeps DMAing this buffer without generating any interrupts.
410 *
411 * If a new buffer is added then the initial JUMP in the program generates an
412 * interrupt as well which signals that the previous buffer has been DMAed
413 * successfully and that it can be returned to userspace.
414 *
415 * It also sets the final jump of the previous buffer to the start of the new
416 * buffer, thus chaining the new buffer into the DMA chain. This is a single
417 * atomic u32 write, so there is no race condition.
418 *
419 * The end-result of all this that you only get an interrupt when a buffer
420 * is ready, so the control flow is very easy.
421 */
422static void tw68_buf_queue(struct vb2_buffer *vb)
423{
424 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
425 struct vb2_queue *vq = vb->vb2_queue;
426 struct tw68_dev *dev = vb2_get_drv_priv(vq);
427 struct tw68_buf *buf = container_of(vbuf, struct tw68_buf, vb);
428 struct tw68_buf *prev;
429 unsigned long flags;
430
431 spin_lock_irqsave(&dev->slock, flags);
432
433 /* append a 'JUMP to start of buffer' to the buffer risc program */
434 buf->jmp[0] = cpu_to_le32(RISC_JUMP);
435 buf->jmp[1] = cpu_to_le32(buf->dma + 8);
436
437 if (!list_empty(&dev->active)) {
438 prev = list_entry(dev->active.prev, struct tw68_buf, list);
439 buf->cpu[0] |= cpu_to_le32(RISC_INT_BIT);
440 prev->jmp[1] = cpu_to_le32(buf->dma);
441 }
442 list_add_tail(&buf->list, &dev->active);
443 spin_unlock_irqrestore(&dev->slock, flags);
444}
445
446/*
447 * buffer_prepare
448 *
449 * Set the ancilliary information into the buffer structure. This
450 * includes generating the necessary risc program if it hasn't already
451 * been done for the current buffer format.
452 * The structure fh contains the details of the format requested by the
453 * user - type, width, height and #fields. This is compared with the
454 * last format set for the current buffer. If they differ, the risc
455 * code (which controls the filling of the buffer) is (re-)generated.
456 */
457static int tw68_buf_prepare(struct vb2_buffer *vb)
458{
459 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
460 struct vb2_queue *vq = vb->vb2_queue;
461 struct tw68_dev *dev = vb2_get_drv_priv(vq);
462 struct tw68_buf *buf = container_of(vbuf, struct tw68_buf, vb);
463 struct sg_table *dma = vb2_dma_sg_plane_desc(vb, 0);
464 unsigned size, bpl;
465
466 size = (dev->width * dev->height * dev->fmt->depth) >> 3;
467 if (vb2_plane_size(vb, 0) < size)
468 return -EINVAL;
469 vb2_set_plane_payload(vb, 0, size);
470
471 bpl = (dev->width * dev->fmt->depth) >> 3;
472 switch (dev->field) {
473 case V4L2_FIELD_TOP:
474 tw68_risc_buffer(dev->pci, buf, dma->sgl,
475 0, UNSET, bpl, 0, dev->height);
476 break;
477 case V4L2_FIELD_BOTTOM:
478 tw68_risc_buffer(dev->pci, buf, dma->sgl,
479 UNSET, 0, bpl, 0, dev->height);
480 break;
481 case V4L2_FIELD_SEQ_TB:
482 tw68_risc_buffer(dev->pci, buf, dma->sgl,
483 0, bpl * (dev->height >> 1),
484 bpl, 0, dev->height >> 1);
485 break;
486 case V4L2_FIELD_SEQ_BT:
487 tw68_risc_buffer(dev->pci, buf, dma->sgl,
488 bpl * (dev->height >> 1), 0,
489 bpl, 0, dev->height >> 1);
490 break;
491 case V4L2_FIELD_INTERLACED:
492 default:
493 tw68_risc_buffer(dev->pci, buf, dma->sgl,
494 0, bpl, bpl, bpl, dev->height >> 1);
495 break;
496 }
497 return 0;
498}
499
500static void tw68_buf_finish(struct vb2_buffer *vb)
501{
502 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
503 struct vb2_queue *vq = vb->vb2_queue;
504 struct tw68_dev *dev = vb2_get_drv_priv(vq);
505 struct tw68_buf *buf = container_of(vbuf, struct tw68_buf, vb);
506
507 pci_free_consistent(dev->pci, buf->size, buf->cpu, buf->dma);
508}
509
510static int tw68_start_streaming(struct vb2_queue *q, unsigned int count)
511{
512 struct tw68_dev *dev = vb2_get_drv_priv(q);
513 struct tw68_buf *buf =
514 container_of(dev->active.next, struct tw68_buf, list);
515
516 dev->seqnr = 0;
517 tw68_video_start_dma(dev, buf);
518 return 0;
519}
520
521static void tw68_stop_streaming(struct vb2_queue *q)
522{
523 struct tw68_dev *dev = vb2_get_drv_priv(q);
524
525 /* Stop risc & fifo */
526 tw_clearl(TW68_DMAC, TW68_DMAP_EN | TW68_FIFO_EN);
527 while (!list_empty(&dev->active)) {
528 struct tw68_buf *buf =
529 container_of(dev->active.next, struct tw68_buf, list);
530
531 list_del(&buf->list);
532 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
533 }
534}
535
536static const struct vb2_ops tw68_video_qops = {
537 .queue_setup = tw68_queue_setup,
538 .buf_queue = tw68_buf_queue,
539 .buf_prepare = tw68_buf_prepare,
540 .buf_finish = tw68_buf_finish,
541 .start_streaming = tw68_start_streaming,
542 .stop_streaming = tw68_stop_streaming,
543 .wait_prepare = vb2_ops_wait_prepare,
544 .wait_finish = vb2_ops_wait_finish,
545};
546
547/* ------------------------------------------------------------------ */
548
549static int tw68_s_ctrl(struct v4l2_ctrl *ctrl)
550{
551 struct tw68_dev *dev =
552 container_of(ctrl->handler, struct tw68_dev, hdl);
553
554 switch (ctrl->id) {
555 case V4L2_CID_BRIGHTNESS:
556 tw_writeb(TW68_BRIGHT, ctrl->val);
557 break;
558 case V4L2_CID_HUE:
559 tw_writeb(TW68_HUE, ctrl->val);
560 break;
561 case V4L2_CID_CONTRAST:
562 tw_writeb(TW68_CONTRAST, ctrl->val);
563 break;
564 case V4L2_CID_SATURATION:
565 tw_writeb(TW68_SAT_U, ctrl->val);
566 tw_writeb(TW68_SAT_V, ctrl->val);
567 break;
568 case V4L2_CID_COLOR_KILLER:
569 if (ctrl->val)
570 tw_andorb(TW68_MISC2, 0xe0, 0xe0);
571 else
572 tw_andorb(TW68_MISC2, 0xe0, 0x00);
573 break;
574 case V4L2_CID_CHROMA_AGC:
575 if (ctrl->val)
576 tw_andorb(TW68_LOOP, 0x30, 0x20);
577 else
578 tw_andorb(TW68_LOOP, 0x30, 0x00);
579 break;
580 }
581 return 0;
582}
583
584/* ------------------------------------------------------------------ */
585
586/*
587 * Note that this routine returns what is stored in the fh structure, and
588 * does not interrogate any of the device registers.
589 */
590static int tw68_g_fmt_vid_cap(struct file *file, void *priv,
591 struct v4l2_format *f)
592{
593 struct tw68_dev *dev = video_drvdata(file);
594
595 f->fmt.pix.width = dev->width;
596 f->fmt.pix.height = dev->height;
597 f->fmt.pix.field = dev->field;
598 f->fmt.pix.pixelformat = dev->fmt->fourcc;
599 f->fmt.pix.bytesperline =
600 (f->fmt.pix.width * (dev->fmt->depth)) >> 3;
601 f->fmt.pix.sizeimage =
602 f->fmt.pix.height * f->fmt.pix.bytesperline;
603 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
604 f->fmt.pix.priv = 0;
605 return 0;
606}
607
608static int tw68_try_fmt_vid_cap(struct file *file, void *priv,
609 struct v4l2_format *f)
610{
611 struct tw68_dev *dev = video_drvdata(file);
612 const struct tw68_format *fmt;
613 enum v4l2_field field;
614 unsigned int maxh;
615
616 fmt = format_by_fourcc(f->fmt.pix.pixelformat);
617 if (NULL == fmt)
618 return -EINVAL;
619
620 field = f->fmt.pix.field;
621 maxh = (dev->tvnorm->id & V4L2_STD_525_60) ? 480 : 576;
622
623 switch (field) {
624 case V4L2_FIELD_TOP:
625 case V4L2_FIELD_BOTTOM:
626 break;
627 case V4L2_FIELD_INTERLACED:
628 case V4L2_FIELD_SEQ_BT:
629 case V4L2_FIELD_SEQ_TB:
630 maxh = maxh * 2;
631 break;
632 default:
633 field = (f->fmt.pix.height > maxh / 2)
634 ? V4L2_FIELD_INTERLACED
635 : V4L2_FIELD_BOTTOM;
636 break;
637 }
638
639 f->fmt.pix.field = field;
640 if (f->fmt.pix.width < 48)
641 f->fmt.pix.width = 48;
642 if (f->fmt.pix.height < 32)
643 f->fmt.pix.height = 32;
644 if (f->fmt.pix.width > 720)
645 f->fmt.pix.width = 720;
646 if (f->fmt.pix.height > maxh)
647 f->fmt.pix.height = maxh;
648 f->fmt.pix.width &= ~0x03;
649 f->fmt.pix.bytesperline =
650 (f->fmt.pix.width * (fmt->depth)) >> 3;
651 f->fmt.pix.sizeimage =
652 f->fmt.pix.height * f->fmt.pix.bytesperline;
653 f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
654 return 0;
655}
656
657/*
658 * Note that tw68_s_fmt_vid_cap sets the information into the fh structure,
659 * and it will be used for all future new buffers. However, there could be
660 * some number of buffers on the "active" chain which will be filled before
661 * the change takes place.
662 */
663static int tw68_s_fmt_vid_cap(struct file *file, void *priv,
664 struct v4l2_format *f)
665{
666 struct tw68_dev *dev = video_drvdata(file);
667 int err;
668
669 err = tw68_try_fmt_vid_cap(file, priv, f);
670 if (0 != err)
671 return err;
672
673 dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
674 dev->width = f->fmt.pix.width;
675 dev->height = f->fmt.pix.height;
676 dev->field = f->fmt.pix.field;
677 return 0;
678}
679
680static int tw68_enum_input(struct file *file, void *priv,
681 struct v4l2_input *i)
682{
683 struct tw68_dev *dev = video_drvdata(file);
684 unsigned int n;
685
686 n = i->index;
687 if (n >= TW68_INPUT_MAX)
688 return -EINVAL;
689 i->index = n;
690 i->type = V4L2_INPUT_TYPE_CAMERA;
691 snprintf(i->name, sizeof(i->name), "Composite %d", n);
692
693 /* If the query is for the current input, get live data */
694 if (n == dev->input) {
695 int v1 = tw_readb(TW68_STATUS1);
696 int v2 = tw_readb(TW68_MVSN);
697
698 if (0 != (v1 & (1 << 7)))
699 i->status |= V4L2_IN_ST_NO_SYNC;
700 if (0 != (v1 & (1 << 6)))
701 i->status |= V4L2_IN_ST_NO_H_LOCK;
702 if (0 != (v1 & (1 << 2)))
703 i->status |= V4L2_IN_ST_NO_SIGNAL;
704 if (0 != (v1 & 1 << 1))
705 i->status |= V4L2_IN_ST_NO_COLOR;
706 if (0 != (v2 & (1 << 2)))
707 i->status |= V4L2_IN_ST_MACROVISION;
708 }
709 i->std = video_devdata(file)->tvnorms;
710 return 0;
711}
712
713static int tw68_g_input(struct file *file, void *priv, unsigned int *i)
714{
715 struct tw68_dev *dev = video_drvdata(file);
716
717 *i = dev->input;
718 return 0;
719}
720
721static int tw68_s_input(struct file *file, void *priv, unsigned int i)
722{
723 struct tw68_dev *dev = video_drvdata(file);
724
725 if (i >= TW68_INPUT_MAX)
726 return -EINVAL;
727 dev->input = i;
728 tw_andorb(TW68_INFORM, 0x03 << 2, dev->input << 2);
729 return 0;
730}
731
732static int tw68_querycap(struct file *file, void *priv,
733 struct v4l2_capability *cap)
734{
735 struct tw68_dev *dev = video_drvdata(file);
736
737 strcpy(cap->driver, "tw68");
738 strlcpy(cap->card, "Techwell Capture Card",
739 sizeof(cap->card));
740 sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci));
741 cap->device_caps =
742 V4L2_CAP_VIDEO_CAPTURE |
743 V4L2_CAP_READWRITE |
744 V4L2_CAP_STREAMING;
745
746 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
747 return 0;
748}
749
750static int tw68_s_std(struct file *file, void *priv, v4l2_std_id id)
751{
752 struct tw68_dev *dev = video_drvdata(file);
753 unsigned int i;
754
755 if (vb2_is_busy(&dev->vidq))
756 return -EBUSY;
757
758 /* Look for match on complete norm id (may have mult bits) */
759 for (i = 0; i < TVNORMS; i++) {
760 if (id == tvnorms[i].id)
761 break;
762 }
763
764 /* If no exact match, look for norm which contains this one */
765 if (i == TVNORMS) {
766 for (i = 0; i < TVNORMS; i++)
767 if (id & tvnorms[i].id)
768 break;
769 }
770 /* If still not matched, give up */
771 if (i == TVNORMS)
772 return -EINVAL;
773
774 set_tvnorm(dev, &tvnorms[i]); /* do the actual setting */
775 return 0;
776}
777
778static int tw68_g_std(struct file *file, void *priv, v4l2_std_id *id)
779{
780 struct tw68_dev *dev = video_drvdata(file);
781
782 *id = dev->tvnorm->id;
783 return 0;
784}
785
786static int tw68_enum_fmt_vid_cap(struct file *file, void *priv,
787 struct v4l2_fmtdesc *f)
788{
789 if (f->index >= FORMATS)
790 return -EINVAL;
791
792 strlcpy(f->description, formats[f->index].name,
793 sizeof(f->description));
794
795 f->pixelformat = formats[f->index].fourcc;
796
797 return 0;
798}
799
800/*
801 * Used strictly for internal development and debugging, this routine
802 * prints out the current register contents for the tw68xx device.
803 */
804static void tw68_dump_regs(struct tw68_dev *dev)
805{
806 unsigned char line[80];
807 int i, j, k;
808 unsigned char *cptr;
809
810 pr_info("Full dump of TW68 registers:\n");
811 /* First we do the PCI regs, 8 4-byte regs per line */
812 for (i = 0; i < 0x100; i += 32) {
813 cptr = line;
814 cptr += sprintf(cptr, "%03x ", i);
815 /* j steps through the next 4 words */
816 for (j = i; j < i + 16; j += 4)
817 cptr += sprintf(cptr, "%08x ", tw_readl(j));
818 *cptr++ = ' ';
819 for (; j < i + 32; j += 4)
820 cptr += sprintf(cptr, "%08x ", tw_readl(j));
821 *cptr++ = '\n';
822 *cptr = 0;
823 pr_info("%s", line);
824 }
825 /* Next the control regs, which are single-byte, address mod 4 */
826 while (i < 0x400) {
827 cptr = line;
828 cptr += sprintf(cptr, "%03x ", i);
829 /* Print out 4 groups of 4 bytes */
830 for (j = 0; j < 4; j++) {
831 for (k = 0; k < 4; k++) {
832 cptr += sprintf(cptr, "%02x ",
833 tw_readb(i));
834 i += 4;
835 }
836 *cptr++ = ' ';
837 }
838 *cptr++ = '\n';
839 *cptr = 0;
840 pr_info("%s", line);
841 }
842}
843
844static int vidioc_log_status(struct file *file, void *priv)
845{
846 struct tw68_dev *dev = video_drvdata(file);
847
848 tw68_dump_regs(dev);
849 return v4l2_ctrl_log_status(file, priv);
850}
851
852#ifdef CONFIG_VIDEO_ADV_DEBUG
853static int vidioc_g_register(struct file *file, void *priv,
854 struct v4l2_dbg_register *reg)
855{
856 struct tw68_dev *dev = video_drvdata(file);
857
858 if (reg->size == 1)
859 reg->val = tw_readb(reg->reg);
860 else
861 reg->val = tw_readl(reg->reg);
862 return 0;
863}
864
865static int vidioc_s_register(struct file *file, void *priv,
866 const struct v4l2_dbg_register *reg)
867{
868 struct tw68_dev *dev = video_drvdata(file);
869
870 if (reg->size == 1)
871 tw_writeb(reg->reg, reg->val);
872 else
873 tw_writel(reg->reg & 0xffff, reg->val);
874 return 0;
875}
876#endif
877
878static const struct v4l2_ctrl_ops tw68_ctrl_ops = {
879 .s_ctrl = tw68_s_ctrl,
880};
881
882static const struct v4l2_file_operations video_fops = {
883 .owner = THIS_MODULE,
884 .open = v4l2_fh_open,
885 .release = vb2_fop_release,
886 .read = vb2_fop_read,
887 .poll = vb2_fop_poll,
888 .mmap = vb2_fop_mmap,
889 .unlocked_ioctl = video_ioctl2,
890};
891
892static const struct v4l2_ioctl_ops video_ioctl_ops = {
893 .vidioc_querycap = tw68_querycap,
894 .vidioc_enum_fmt_vid_cap = tw68_enum_fmt_vid_cap,
895 .vidioc_reqbufs = vb2_ioctl_reqbufs,
896 .vidioc_create_bufs = vb2_ioctl_create_bufs,
897 .vidioc_querybuf = vb2_ioctl_querybuf,
898 .vidioc_qbuf = vb2_ioctl_qbuf,
899 .vidioc_dqbuf = vb2_ioctl_dqbuf,
900 .vidioc_s_std = tw68_s_std,
901 .vidioc_g_std = tw68_g_std,
902 .vidioc_enum_input = tw68_enum_input,
903 .vidioc_g_input = tw68_g_input,
904 .vidioc_s_input = tw68_s_input,
905 .vidioc_streamon = vb2_ioctl_streamon,
906 .vidioc_streamoff = vb2_ioctl_streamoff,
907 .vidioc_g_fmt_vid_cap = tw68_g_fmt_vid_cap,
908 .vidioc_try_fmt_vid_cap = tw68_try_fmt_vid_cap,
909 .vidioc_s_fmt_vid_cap = tw68_s_fmt_vid_cap,
910 .vidioc_log_status = vidioc_log_status,
911 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
912 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
913#ifdef CONFIG_VIDEO_ADV_DEBUG
914 .vidioc_g_register = vidioc_g_register,
915 .vidioc_s_register = vidioc_s_register,
916#endif
917};
918
919static struct video_device tw68_video_template = {
920 .name = "tw68_video",
921 .fops = &video_fops,
922 .ioctl_ops = &video_ioctl_ops,
923 .release = video_device_release_empty,
924 .tvnorms = TW68_NORMS,
925};
926
927/* ------------------------------------------------------------------ */
928/* exported stuff */
929void tw68_set_tvnorm_hw(struct tw68_dev *dev)
930{
931 tw_andorb(TW68_SDT, 0x07, dev->tvnorm->format);
932}
933
934int tw68_video_init1(struct tw68_dev *dev)
935{
936 struct v4l2_ctrl_handler *hdl = &dev->hdl;
937
938 v4l2_ctrl_handler_init(hdl, 6);
939 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
940 V4L2_CID_BRIGHTNESS, -128, 127, 1, 20);
941 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
942 V4L2_CID_CONTRAST, 0, 255, 1, 100);
943 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
944 V4L2_CID_SATURATION, 0, 255, 1, 128);
945 /* NTSC only */
946 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
947 V4L2_CID_HUE, -128, 127, 1, 0);
948 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
949 V4L2_CID_COLOR_KILLER, 0, 1, 1, 0);
950 v4l2_ctrl_new_std(hdl, &tw68_ctrl_ops,
951 V4L2_CID_CHROMA_AGC, 0, 1, 1, 1);
952 if (hdl->error) {
953 v4l2_ctrl_handler_free(hdl);
954 return hdl->error;
955 }
956 dev->v4l2_dev.ctrl_handler = hdl;
957 v4l2_ctrl_handler_setup(hdl);
958 return 0;
959}
960
961int tw68_video_init2(struct tw68_dev *dev, int video_nr)
962{
963 int ret;
964
965 set_tvnorm(dev, &tvnorms[0]);
966
967 dev->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24);
968 dev->width = 720;
969 dev->height = 576;
970 dev->field = V4L2_FIELD_INTERLACED;
971
972 INIT_LIST_HEAD(&dev->active);
973 dev->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
974 dev->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
975 dev->vidq.io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ | VB2_DMABUF;
976 dev->vidq.ops = &tw68_video_qops;
977 dev->vidq.mem_ops = &vb2_dma_sg_memops;
978 dev->vidq.drv_priv = dev;
979 dev->vidq.gfp_flags = __GFP_DMA32 | __GFP_KSWAPD_RECLAIM;
980 dev->vidq.buf_struct_size = sizeof(struct tw68_buf);
981 dev->vidq.lock = &dev->lock;
982 dev->vidq.min_buffers_needed = 2;
983 dev->vidq.dev = &dev->pci->dev;
984 ret = vb2_queue_init(&dev->vidq);
985 if (ret)
986 return ret;
987 dev->vdev = tw68_video_template;
988 dev->vdev.v4l2_dev = &dev->v4l2_dev;
989 dev->vdev.lock = &dev->lock;
990 dev->vdev.queue = &dev->vidq;
991 video_set_drvdata(&dev->vdev, dev);
992 return video_register_device(&dev->vdev, VFL_TYPE_GRABBER, video_nr);
993}
994
995/*
996 * tw68_irq_video_done
997 */
998void tw68_irq_video_done(struct tw68_dev *dev, unsigned long status)
999{
1000 __u32 reg;
1001
1002 /* reset interrupts handled by this routine */
1003 tw_writel(TW68_INTSTAT, status);
1004 /*
1005 * Check most likely first
1006 *
1007 * DMAPI shows we have reached the end of the risc code
1008 * for the current buffer.
1009 */
1010 if (status & TW68_DMAPI) {
1011 struct tw68_buf *buf;
1012
1013 spin_lock(&dev->slock);
1014 buf = list_entry(dev->active.next, struct tw68_buf, list);
1015 list_del(&buf->list);
1016 spin_unlock(&dev->slock);
1017 buf->vb.vb2_buf.timestamp = ktime_get_ns();
1018 buf->vb.field = dev->field;
1019 buf->vb.sequence = dev->seqnr++;
1020 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
1021 status &= ~(TW68_DMAPI);
1022 if (0 == status)
1023 return;
1024 }
1025 if (status & (TW68_VLOCK | TW68_HLOCK))
1026 dev_dbg(&dev->pci->dev, "Lost sync\n");
1027 if (status & TW68_PABORT)
1028 dev_err(&dev->pci->dev, "PABORT interrupt\n");
1029 if (status & TW68_DMAPERR)
1030 dev_err(&dev->pci->dev, "DMAPERR interrupt\n");
1031 /*
1032 * On TW6800, FDMIS is apparently generated if video input is switched
1033 * during operation. Therefore, it is not enabled for that chip.
1034 */
1035 if (status & TW68_FDMIS)
1036 dev_dbg(&dev->pci->dev, "FDMIS interrupt\n");
1037 if (status & TW68_FFOF) {
1038 /* probably a logic error */
1039 reg = tw_readl(TW68_DMAC) & TW68_FIFO_EN;
1040 tw_clearl(TW68_DMAC, TW68_FIFO_EN);
1041 dev_dbg(&dev->pci->dev, "FFOF interrupt\n");
1042 tw_setl(TW68_DMAC, reg);
1043 }
1044 if (status & TW68_FFERR)
1045 dev_dbg(&dev->pci->dev, "FFERR interrupt\n");
1046}