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1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include <linux/slab.h>
30#include <linux/export.h>
31#include <linux/notifier.h>
32#include <linux/reboot.h>
33#include <drm/drmP.h>
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
38#include "intel_drv.h"
39#include <drm/i915_drm.h>
40#include "i915_drv.h"
41
42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
50struct dp_link_dpll {
51 int clock;
52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
56 { 162000,
57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
58 { 270000,
59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
63 { 162000,
64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
65 { 270000,
66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
69static const struct dp_link_dpll vlv_dpll[] = {
70 { 162000,
71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
72 { 270000,
73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
88 { 270000, /* m2_int = 27, m2_fraction = 0 */
89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
90 { 540000, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
93
94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
96static const int skl_rates[] = { 162000, 216000, 270000,
97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
99
100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
112}
113
114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
115{
116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
119}
120
121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
124}
125
126static void intel_dp_link_down(struct intel_dp *intel_dp);
127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
132static void intel_dp_unset_edid(struct intel_dp *intel_dp);
133
134static int
135intel_dp_max_link_bw(struct intel_dp *intel_dp)
136{
137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
138
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
141 case DP_LINK_BW_2_7:
142 case DP_LINK_BW_5_4:
143 break;
144 default:
145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
146 max_link_bw);
147 max_link_bw = DP_LINK_BW_1_62;
148 break;
149 }
150 return max_link_bw;
151}
152
153static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
154{
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
156 u8 source_max, sink_max;
157
158 source_max = intel_dig_port->max_lanes;
159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
160
161 return min(source_max, sink_max);
162}
163
164/*
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
167 *
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 *
170 * 270000 * 1 * 8 / 10 == 216000
171 *
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
176 *
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
179 */
180
181static int
182intel_dp_link_required(int pixel_clock, int bpp)
183{
184 return (pixel_clock * bpp + 9) / 10;
185}
186
187static int
188intel_dp_max_data_rate(int max_link_clock, int max_lanes)
189{
190 return (max_link_clock * max_lanes * 8) / 10;
191}
192
193static int
194intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
195{
196 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
197 struct intel_encoder *encoder = &intel_dig_port->base;
198 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
199 int max_dotclk = dev_priv->max_dotclk_freq;
200 int ds_max_dotclk;
201
202 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
203
204 if (type != DP_DS_PORT_TYPE_VGA)
205 return max_dotclk;
206
207 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
208 intel_dp->downstream_ports);
209
210 if (ds_max_dotclk != 0)
211 max_dotclk = min(max_dotclk, ds_max_dotclk);
212
213 return max_dotclk;
214}
215
216static int
217intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
218{
219 if (intel_dp->num_sink_rates) {
220 *sink_rates = intel_dp->sink_rates;
221 return intel_dp->num_sink_rates;
222 }
223
224 *sink_rates = default_rates;
225
226 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
227}
228
229static int
230intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
231{
232 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
233 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
234 int size;
235
236 if (IS_BROXTON(dev_priv)) {
237 *source_rates = bxt_rates;
238 size = ARRAY_SIZE(bxt_rates);
239 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
240 *source_rates = skl_rates;
241 size = ARRAY_SIZE(skl_rates);
242 } else {
243 *source_rates = default_rates;
244 size = ARRAY_SIZE(default_rates);
245 }
246
247 /* This depends on the fact that 5.4 is last value in the array */
248 if (!intel_dp_source_supports_hbr2(intel_dp))
249 size--;
250
251 return size;
252}
253
254static int intersect_rates(const int *source_rates, int source_len,
255 const int *sink_rates, int sink_len,
256 int *common_rates)
257{
258 int i = 0, j = 0, k = 0;
259
260 while (i < source_len && j < sink_len) {
261 if (source_rates[i] == sink_rates[j]) {
262 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
263 return k;
264 common_rates[k] = source_rates[i];
265 ++k;
266 ++i;
267 ++j;
268 } else if (source_rates[i] < sink_rates[j]) {
269 ++i;
270 } else {
271 ++j;
272 }
273 }
274 return k;
275}
276
277static int intel_dp_common_rates(struct intel_dp *intel_dp,
278 int *common_rates)
279{
280 const int *source_rates, *sink_rates;
281 int source_len, sink_len;
282
283 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
284 source_len = intel_dp_source_rates(intel_dp, &source_rates);
285
286 return intersect_rates(source_rates, source_len,
287 sink_rates, sink_len,
288 common_rates);
289}
290
291static enum drm_mode_status
292intel_dp_mode_valid(struct drm_connector *connector,
293 struct drm_display_mode *mode)
294{
295 struct intel_dp *intel_dp = intel_attached_dp(connector);
296 struct intel_connector *intel_connector = to_intel_connector(connector);
297 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
298 int target_clock = mode->clock;
299 int max_rate, mode_rate, max_lanes, max_link_clock;
300 int max_dotclk;
301
302 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
303
304 if (is_edp(intel_dp) && fixed_mode) {
305 if (mode->hdisplay > fixed_mode->hdisplay)
306 return MODE_PANEL;
307
308 if (mode->vdisplay > fixed_mode->vdisplay)
309 return MODE_PANEL;
310
311 target_clock = fixed_mode->clock;
312 }
313
314 max_link_clock = intel_dp_max_link_rate(intel_dp);
315 max_lanes = intel_dp_max_lane_count(intel_dp);
316
317 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
318 mode_rate = intel_dp_link_required(target_clock, 18);
319
320 if (mode_rate > max_rate || target_clock > max_dotclk)
321 return MODE_CLOCK_HIGH;
322
323 if (mode->clock < 10000)
324 return MODE_CLOCK_LOW;
325
326 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
327 return MODE_H_ILLEGAL;
328
329 return MODE_OK;
330}
331
332uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
333{
334 int i;
335 uint32_t v = 0;
336
337 if (src_bytes > 4)
338 src_bytes = 4;
339 for (i = 0; i < src_bytes; i++)
340 v |= ((uint32_t) src[i]) << ((3-i) * 8);
341 return v;
342}
343
344static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
345{
346 int i;
347 if (dst_bytes > 4)
348 dst_bytes = 4;
349 for (i = 0; i < dst_bytes; i++)
350 dst[i] = src >> ((3-i) * 8);
351}
352
353static void
354intel_dp_init_panel_power_sequencer(struct drm_device *dev,
355 struct intel_dp *intel_dp);
356static void
357intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
358 struct intel_dp *intel_dp,
359 bool force_disable_vdd);
360static void
361intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
362
363static void pps_lock(struct intel_dp *intel_dp)
364{
365 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
366 struct intel_encoder *encoder = &intel_dig_port->base;
367 struct drm_device *dev = encoder->base.dev;
368 struct drm_i915_private *dev_priv = to_i915(dev);
369 enum intel_display_power_domain power_domain;
370
371 /*
372 * See vlv_power_sequencer_reset() why we need
373 * a power domain reference here.
374 */
375 power_domain = intel_display_port_aux_power_domain(encoder);
376 intel_display_power_get(dev_priv, power_domain);
377
378 mutex_lock(&dev_priv->pps_mutex);
379}
380
381static void pps_unlock(struct intel_dp *intel_dp)
382{
383 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
384 struct intel_encoder *encoder = &intel_dig_port->base;
385 struct drm_device *dev = encoder->base.dev;
386 struct drm_i915_private *dev_priv = to_i915(dev);
387 enum intel_display_power_domain power_domain;
388
389 mutex_unlock(&dev_priv->pps_mutex);
390
391 power_domain = intel_display_port_aux_power_domain(encoder);
392 intel_display_power_put(dev_priv, power_domain);
393}
394
395static void
396vlv_power_sequencer_kick(struct intel_dp *intel_dp)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
400 enum pipe pipe = intel_dp->pps_pipe;
401 bool pll_enabled, release_cl_override = false;
402 enum dpio_phy phy = DPIO_PHY(pipe);
403 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
404 uint32_t DP;
405
406 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
407 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
408 pipe_name(pipe), port_name(intel_dig_port->port)))
409 return;
410
411 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
412 pipe_name(pipe), port_name(intel_dig_port->port));
413
414 /* Preserve the BIOS-computed detected bit. This is
415 * supposed to be read-only.
416 */
417 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
418 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
419 DP |= DP_PORT_WIDTH(1);
420 DP |= DP_LINK_TRAIN_PAT_1;
421
422 if (IS_CHERRYVIEW(dev_priv))
423 DP |= DP_PIPE_SELECT_CHV(pipe);
424 else if (pipe == PIPE_B)
425 DP |= DP_PIPEB_SELECT;
426
427 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
428
429 /*
430 * The DPLL for the pipe must be enabled for this to work.
431 * So enable temporarily it if it's not already enabled.
432 */
433 if (!pll_enabled) {
434 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
435 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
436
437 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
438 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
439 DRM_ERROR("Failed to force on pll for pipe %c!\n",
440 pipe_name(pipe));
441 return;
442 }
443 }
444
445 /*
446 * Similar magic as in intel_dp_enable_port().
447 * We _must_ do this port enable + disable trick
448 * to make this power seqeuencer lock onto the port.
449 * Otherwise even VDD force bit won't work.
450 */
451 I915_WRITE(intel_dp->output_reg, DP);
452 POSTING_READ(intel_dp->output_reg);
453
454 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
455 POSTING_READ(intel_dp->output_reg);
456
457 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
458 POSTING_READ(intel_dp->output_reg);
459
460 if (!pll_enabled) {
461 vlv_force_pll_off(dev_priv, pipe);
462
463 if (release_cl_override)
464 chv_phy_powergate_ch(dev_priv, phy, ch, false);
465 }
466}
467
468static enum pipe
469vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
470{
471 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
472 struct drm_device *dev = intel_dig_port->base.base.dev;
473 struct drm_i915_private *dev_priv = to_i915(dev);
474 struct intel_encoder *encoder;
475 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
476 enum pipe pipe;
477
478 lockdep_assert_held(&dev_priv->pps_mutex);
479
480 /* We should never land here with regular DP ports */
481 WARN_ON(!is_edp(intel_dp));
482
483 if (intel_dp->pps_pipe != INVALID_PIPE)
484 return intel_dp->pps_pipe;
485
486 /*
487 * We don't have power sequencer currently.
488 * Pick one that's not used by other ports.
489 */
490 for_each_intel_encoder(dev, encoder) {
491 struct intel_dp *tmp;
492
493 if (encoder->type != INTEL_OUTPUT_EDP)
494 continue;
495
496 tmp = enc_to_intel_dp(&encoder->base);
497
498 if (tmp->pps_pipe != INVALID_PIPE)
499 pipes &= ~(1 << tmp->pps_pipe);
500 }
501
502 /*
503 * Didn't find one. This should not happen since there
504 * are two power sequencers and up to two eDP ports.
505 */
506 if (WARN_ON(pipes == 0))
507 pipe = PIPE_A;
508 else
509 pipe = ffs(pipes) - 1;
510
511 vlv_steal_power_sequencer(dev, pipe);
512 intel_dp->pps_pipe = pipe;
513
514 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
515 pipe_name(intel_dp->pps_pipe),
516 port_name(intel_dig_port->port));
517
518 /* init power sequencer on this pipe and port */
519 intel_dp_init_panel_power_sequencer(dev, intel_dp);
520 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
521
522 /*
523 * Even vdd force doesn't work until we've made
524 * the power sequencer lock in on the port.
525 */
526 vlv_power_sequencer_kick(intel_dp);
527
528 return intel_dp->pps_pipe;
529}
530
531static int
532bxt_power_sequencer_idx(struct intel_dp *intel_dp)
533{
534 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
535 struct drm_device *dev = intel_dig_port->base.base.dev;
536 struct drm_i915_private *dev_priv = to_i915(dev);
537
538 lockdep_assert_held(&dev_priv->pps_mutex);
539
540 /* We should never land here with regular DP ports */
541 WARN_ON(!is_edp(intel_dp));
542
543 /*
544 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
545 * mapping needs to be retrieved from VBT, for now just hard-code to
546 * use instance #0 always.
547 */
548 if (!intel_dp->pps_reset)
549 return 0;
550
551 intel_dp->pps_reset = false;
552
553 /*
554 * Only the HW needs to be reprogrammed, the SW state is fixed and
555 * has been setup during connector init.
556 */
557 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
558
559 return 0;
560}
561
562typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
563 enum pipe pipe);
564
565static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
566 enum pipe pipe)
567{
568 return I915_READ(PP_STATUS(pipe)) & PP_ON;
569}
570
571static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
572 enum pipe pipe)
573{
574 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
575}
576
577static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
578 enum pipe pipe)
579{
580 return true;
581}
582
583static enum pipe
584vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
585 enum port port,
586 vlv_pipe_check pipe_check)
587{
588 enum pipe pipe;
589
590 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
591 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
592 PANEL_PORT_SELECT_MASK;
593
594 if (port_sel != PANEL_PORT_SELECT_VLV(port))
595 continue;
596
597 if (!pipe_check(dev_priv, pipe))
598 continue;
599
600 return pipe;
601 }
602
603 return INVALID_PIPE;
604}
605
606static void
607vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
608{
609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
611 struct drm_i915_private *dev_priv = to_i915(dev);
612 enum port port = intel_dig_port->port;
613
614 lockdep_assert_held(&dev_priv->pps_mutex);
615
616 /* try to find a pipe with this port selected */
617 /* first pick one where the panel is on */
618 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
619 vlv_pipe_has_pp_on);
620 /* didn't find one? pick one where vdd is on */
621 if (intel_dp->pps_pipe == INVALID_PIPE)
622 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
623 vlv_pipe_has_vdd_on);
624 /* didn't find one? pick one with just the correct port */
625 if (intel_dp->pps_pipe == INVALID_PIPE)
626 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
627 vlv_pipe_any);
628
629 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
630 if (intel_dp->pps_pipe == INVALID_PIPE) {
631 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
632 port_name(port));
633 return;
634 }
635
636 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
637 port_name(port), pipe_name(intel_dp->pps_pipe));
638
639 intel_dp_init_panel_power_sequencer(dev, intel_dp);
640 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
641}
642
643void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
644{
645 struct drm_device *dev = &dev_priv->drm;
646 struct intel_encoder *encoder;
647
648 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
649 !IS_BROXTON(dev_priv)))
650 return;
651
652 /*
653 * We can't grab pps_mutex here due to deadlock with power_domain
654 * mutex when power_domain functions are called while holding pps_mutex.
655 * That also means that in order to use pps_pipe the code needs to
656 * hold both a power domain reference and pps_mutex, and the power domain
657 * reference get/put must be done while _not_ holding pps_mutex.
658 * pps_{lock,unlock}() do these steps in the correct order, so one
659 * should use them always.
660 */
661
662 for_each_intel_encoder(dev, encoder) {
663 struct intel_dp *intel_dp;
664
665 if (encoder->type != INTEL_OUTPUT_EDP)
666 continue;
667
668 intel_dp = enc_to_intel_dp(&encoder->base);
669 if (IS_BROXTON(dev_priv))
670 intel_dp->pps_reset = true;
671 else
672 intel_dp->pps_pipe = INVALID_PIPE;
673 }
674}
675
676struct pps_registers {
677 i915_reg_t pp_ctrl;
678 i915_reg_t pp_stat;
679 i915_reg_t pp_on;
680 i915_reg_t pp_off;
681 i915_reg_t pp_div;
682};
683
684static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
685 struct intel_dp *intel_dp,
686 struct pps_registers *regs)
687{
688 int pps_idx = 0;
689
690 memset(regs, 0, sizeof(*regs));
691
692 if (IS_BROXTON(dev_priv))
693 pps_idx = bxt_power_sequencer_idx(intel_dp);
694 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
695 pps_idx = vlv_power_sequencer_pipe(intel_dp);
696
697 regs->pp_ctrl = PP_CONTROL(pps_idx);
698 regs->pp_stat = PP_STATUS(pps_idx);
699 regs->pp_on = PP_ON_DELAYS(pps_idx);
700 regs->pp_off = PP_OFF_DELAYS(pps_idx);
701 if (!IS_BROXTON(dev_priv))
702 regs->pp_div = PP_DIVISOR(pps_idx);
703}
704
705static i915_reg_t
706_pp_ctrl_reg(struct intel_dp *intel_dp)
707{
708 struct pps_registers regs;
709
710 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
711 ®s);
712
713 return regs.pp_ctrl;
714}
715
716static i915_reg_t
717_pp_stat_reg(struct intel_dp *intel_dp)
718{
719 struct pps_registers regs;
720
721 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
722 ®s);
723
724 return regs.pp_stat;
725}
726
727/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
728 This function only applicable when panel PM state is not to be tracked */
729static int edp_notify_handler(struct notifier_block *this, unsigned long code,
730 void *unused)
731{
732 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
733 edp_notifier);
734 struct drm_device *dev = intel_dp_to_dev(intel_dp);
735 struct drm_i915_private *dev_priv = to_i915(dev);
736
737 if (!is_edp(intel_dp) || code != SYS_RESTART)
738 return 0;
739
740 pps_lock(intel_dp);
741
742 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
743 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
744 i915_reg_t pp_ctrl_reg, pp_div_reg;
745 u32 pp_div;
746
747 pp_ctrl_reg = PP_CONTROL(pipe);
748 pp_div_reg = PP_DIVISOR(pipe);
749 pp_div = I915_READ(pp_div_reg);
750 pp_div &= PP_REFERENCE_DIVIDER_MASK;
751
752 /* 0x1F write to PP_DIV_REG sets max cycle delay */
753 I915_WRITE(pp_div_reg, pp_div | 0x1F);
754 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
755 msleep(intel_dp->panel_power_cycle_delay);
756 }
757
758 pps_unlock(intel_dp);
759
760 return 0;
761}
762
763static bool edp_have_panel_power(struct intel_dp *intel_dp)
764{
765 struct drm_device *dev = intel_dp_to_dev(intel_dp);
766 struct drm_i915_private *dev_priv = to_i915(dev);
767
768 lockdep_assert_held(&dev_priv->pps_mutex);
769
770 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
771 intel_dp->pps_pipe == INVALID_PIPE)
772 return false;
773
774 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
775}
776
777static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
778{
779 struct drm_device *dev = intel_dp_to_dev(intel_dp);
780 struct drm_i915_private *dev_priv = to_i915(dev);
781
782 lockdep_assert_held(&dev_priv->pps_mutex);
783
784 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
785 intel_dp->pps_pipe == INVALID_PIPE)
786 return false;
787
788 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
789}
790
791static void
792intel_dp_check_edp(struct intel_dp *intel_dp)
793{
794 struct drm_device *dev = intel_dp_to_dev(intel_dp);
795 struct drm_i915_private *dev_priv = to_i915(dev);
796
797 if (!is_edp(intel_dp))
798 return;
799
800 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
801 WARN(1, "eDP powered off while attempting aux channel communication.\n");
802 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
803 I915_READ(_pp_stat_reg(intel_dp)),
804 I915_READ(_pp_ctrl_reg(intel_dp)));
805 }
806}
807
808static uint32_t
809intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
810{
811 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
812 struct drm_device *dev = intel_dig_port->base.base.dev;
813 struct drm_i915_private *dev_priv = to_i915(dev);
814 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
815 uint32_t status;
816 bool done;
817
818#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
819 if (has_aux_irq)
820 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
821 msecs_to_jiffies_timeout(10));
822 else
823 done = wait_for(C, 10) == 0;
824 if (!done)
825 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
826 has_aux_irq);
827#undef C
828
829 return status;
830}
831
832static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
833{
834 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
835 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
836
837 if (index)
838 return 0;
839
840 /*
841 * The clock divider is based off the hrawclk, and would like to run at
842 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
843 */
844 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
845}
846
847static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
848{
849 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
850 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
851
852 if (index)
853 return 0;
854
855 /*
856 * The clock divider is based off the cdclk or PCH rawclk, and would
857 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
858 * divide by 2000 and use that
859 */
860 if (intel_dig_port->port == PORT_A)
861 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
862 else
863 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
864}
865
866static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
867{
868 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
869 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
870
871 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
872 /* Workaround for non-ULT HSW */
873 switch (index) {
874 case 0: return 63;
875 case 1: return 72;
876 default: return 0;
877 }
878 }
879
880 return ilk_get_aux_clock_divider(intel_dp, index);
881}
882
883static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
884{
885 /*
886 * SKL doesn't need us to program the AUX clock divider (Hardware will
887 * derive the clock from CDCLK automatically). We still implement the
888 * get_aux_clock_divider vfunc to plug-in into the existing code.
889 */
890 return index ? 0 : 1;
891}
892
893static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
894 bool has_aux_irq,
895 int send_bytes,
896 uint32_t aux_clock_divider)
897{
898 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
899 struct drm_i915_private *dev_priv =
900 to_i915(intel_dig_port->base.base.dev);
901 uint32_t precharge, timeout;
902
903 if (IS_GEN6(dev_priv))
904 precharge = 3;
905 else
906 precharge = 5;
907
908 if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
909 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
910 else
911 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
912
913 return DP_AUX_CH_CTL_SEND_BUSY |
914 DP_AUX_CH_CTL_DONE |
915 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
916 DP_AUX_CH_CTL_TIME_OUT_ERROR |
917 timeout |
918 DP_AUX_CH_CTL_RECEIVE_ERROR |
919 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
920 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
921 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
922}
923
924static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
925 bool has_aux_irq,
926 int send_bytes,
927 uint32_t unused)
928{
929 return DP_AUX_CH_CTL_SEND_BUSY |
930 DP_AUX_CH_CTL_DONE |
931 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
932 DP_AUX_CH_CTL_TIME_OUT_ERROR |
933 DP_AUX_CH_CTL_TIME_OUT_1600us |
934 DP_AUX_CH_CTL_RECEIVE_ERROR |
935 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
936 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
937 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
938}
939
940static int
941intel_dp_aux_ch(struct intel_dp *intel_dp,
942 const uint8_t *send, int send_bytes,
943 uint8_t *recv, int recv_size)
944{
945 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
946 struct drm_i915_private *dev_priv =
947 to_i915(intel_dig_port->base.base.dev);
948 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
949 uint32_t aux_clock_divider;
950 int i, ret, recv_bytes;
951 uint32_t status;
952 int try, clock = 0;
953 bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
954 bool vdd;
955
956 pps_lock(intel_dp);
957
958 /*
959 * We will be called with VDD already enabled for dpcd/edid/oui reads.
960 * In such cases we want to leave VDD enabled and it's up to upper layers
961 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
962 * ourselves.
963 */
964 vdd = edp_panel_vdd_on(intel_dp);
965
966 /* dp aux is extremely sensitive to irq latency, hence request the
967 * lowest possible wakeup latency and so prevent the cpu from going into
968 * deep sleep states.
969 */
970 pm_qos_update_request(&dev_priv->pm_qos, 0);
971
972 intel_dp_check_edp(intel_dp);
973
974 /* Try to wait for any previous AUX channel activity */
975 for (try = 0; try < 3; try++) {
976 status = I915_READ_NOTRACE(ch_ctl);
977 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
978 break;
979 msleep(1);
980 }
981
982 if (try == 3) {
983 static u32 last_status = -1;
984 const u32 status = I915_READ(ch_ctl);
985
986 if (status != last_status) {
987 WARN(1, "dp_aux_ch not started status 0x%08x\n",
988 status);
989 last_status = status;
990 }
991
992 ret = -EBUSY;
993 goto out;
994 }
995
996 /* Only 5 data registers! */
997 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
998 ret = -E2BIG;
999 goto out;
1000 }
1001
1002 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1003 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1004 has_aux_irq,
1005 send_bytes,
1006 aux_clock_divider);
1007
1008 /* Must try at least 3 times according to DP spec */
1009 for (try = 0; try < 5; try++) {
1010 /* Load the send data into the aux channel data registers */
1011 for (i = 0; i < send_bytes; i += 4)
1012 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1013 intel_dp_pack_aux(send + i,
1014 send_bytes - i));
1015
1016 /* Send the command and wait for it to complete */
1017 I915_WRITE(ch_ctl, send_ctl);
1018
1019 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1020
1021 /* Clear done status and any errors */
1022 I915_WRITE(ch_ctl,
1023 status |
1024 DP_AUX_CH_CTL_DONE |
1025 DP_AUX_CH_CTL_TIME_OUT_ERROR |
1026 DP_AUX_CH_CTL_RECEIVE_ERROR);
1027
1028 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1029 continue;
1030
1031 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1032 * 400us delay required for errors and timeouts
1033 * Timeout errors from the HW already meet this
1034 * requirement so skip to next iteration
1035 */
1036 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1037 usleep_range(400, 500);
1038 continue;
1039 }
1040 if (status & DP_AUX_CH_CTL_DONE)
1041 goto done;
1042 }
1043 }
1044
1045 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1046 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1047 ret = -EBUSY;
1048 goto out;
1049 }
1050
1051done:
1052 /* Check for timeout or receive error.
1053 * Timeouts occur when the sink is not connected
1054 */
1055 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1056 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1057 ret = -EIO;
1058 goto out;
1059 }
1060
1061 /* Timeouts occur when the device isn't connected, so they're
1062 * "normal" -- don't fill the kernel log with these */
1063 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1064 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1065 ret = -ETIMEDOUT;
1066 goto out;
1067 }
1068
1069 /* Unload any bytes sent back from the other side */
1070 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1071 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1072
1073 /*
1074 * By BSpec: "Message sizes of 0 or >20 are not allowed."
1075 * We have no idea of what happened so we return -EBUSY so
1076 * drm layer takes care for the necessary retries.
1077 */
1078 if (recv_bytes == 0 || recv_bytes > 20) {
1079 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1080 recv_bytes);
1081 /*
1082 * FIXME: This patch was created on top of a series that
1083 * organize the retries at drm level. There EBUSY should
1084 * also take care for 1ms wait before retrying.
1085 * That aux retries re-org is still needed and after that is
1086 * merged we remove this sleep from here.
1087 */
1088 usleep_range(1000, 1500);
1089 ret = -EBUSY;
1090 goto out;
1091 }
1092
1093 if (recv_bytes > recv_size)
1094 recv_bytes = recv_size;
1095
1096 for (i = 0; i < recv_bytes; i += 4)
1097 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1098 recv + i, recv_bytes - i);
1099
1100 ret = recv_bytes;
1101out:
1102 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1103
1104 if (vdd)
1105 edp_panel_vdd_off(intel_dp, false);
1106
1107 pps_unlock(intel_dp);
1108
1109 return ret;
1110}
1111
1112#define BARE_ADDRESS_SIZE 3
1113#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
1114static ssize_t
1115intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1116{
1117 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1118 uint8_t txbuf[20], rxbuf[20];
1119 size_t txsize, rxsize;
1120 int ret;
1121
1122 txbuf[0] = (msg->request << 4) |
1123 ((msg->address >> 16) & 0xf);
1124 txbuf[1] = (msg->address >> 8) & 0xff;
1125 txbuf[2] = msg->address & 0xff;
1126 txbuf[3] = msg->size - 1;
1127
1128 switch (msg->request & ~DP_AUX_I2C_MOT) {
1129 case DP_AUX_NATIVE_WRITE:
1130 case DP_AUX_I2C_WRITE:
1131 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1132 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1133 rxsize = 2; /* 0 or 1 data bytes */
1134
1135 if (WARN_ON(txsize > 20))
1136 return -E2BIG;
1137
1138 WARN_ON(!msg->buffer != !msg->size);
1139
1140 if (msg->buffer)
1141 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1142
1143 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1144 if (ret > 0) {
1145 msg->reply = rxbuf[0] >> 4;
1146
1147 if (ret > 1) {
1148 /* Number of bytes written in a short write. */
1149 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1150 } else {
1151 /* Return payload size. */
1152 ret = msg->size;
1153 }
1154 }
1155 break;
1156
1157 case DP_AUX_NATIVE_READ:
1158 case DP_AUX_I2C_READ:
1159 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1160 rxsize = msg->size + 1;
1161
1162 if (WARN_ON(rxsize > 20))
1163 return -E2BIG;
1164
1165 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1166 if (ret > 0) {
1167 msg->reply = rxbuf[0] >> 4;
1168 /*
1169 * Assume happy day, and copy the data. The caller is
1170 * expected to check msg->reply before touching it.
1171 *
1172 * Return payload size.
1173 */
1174 ret--;
1175 memcpy(msg->buffer, rxbuf + 1, ret);
1176 }
1177 break;
1178
1179 default:
1180 ret = -EINVAL;
1181 break;
1182 }
1183
1184 return ret;
1185}
1186
1187static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1188 enum port port)
1189{
1190 const struct ddi_vbt_port_info *info =
1191 &dev_priv->vbt.ddi_port_info[port];
1192 enum port aux_port;
1193
1194 if (!info->alternate_aux_channel) {
1195 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1196 port_name(port), port_name(port));
1197 return port;
1198 }
1199
1200 switch (info->alternate_aux_channel) {
1201 case DP_AUX_A:
1202 aux_port = PORT_A;
1203 break;
1204 case DP_AUX_B:
1205 aux_port = PORT_B;
1206 break;
1207 case DP_AUX_C:
1208 aux_port = PORT_C;
1209 break;
1210 case DP_AUX_D:
1211 aux_port = PORT_D;
1212 break;
1213 default:
1214 MISSING_CASE(info->alternate_aux_channel);
1215 aux_port = PORT_A;
1216 break;
1217 }
1218
1219 DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1220 port_name(aux_port), port_name(port));
1221
1222 return aux_port;
1223}
1224
1225static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1226 enum port port)
1227{
1228 switch (port) {
1229 case PORT_B:
1230 case PORT_C:
1231 case PORT_D:
1232 return DP_AUX_CH_CTL(port);
1233 default:
1234 MISSING_CASE(port);
1235 return DP_AUX_CH_CTL(PORT_B);
1236 }
1237}
1238
1239static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1240 enum port port, int index)
1241{
1242 switch (port) {
1243 case PORT_B:
1244 case PORT_C:
1245 case PORT_D:
1246 return DP_AUX_CH_DATA(port, index);
1247 default:
1248 MISSING_CASE(port);
1249 return DP_AUX_CH_DATA(PORT_B, index);
1250 }
1251}
1252
1253static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1254 enum port port)
1255{
1256 switch (port) {
1257 case PORT_A:
1258 return DP_AUX_CH_CTL(port);
1259 case PORT_B:
1260 case PORT_C:
1261 case PORT_D:
1262 return PCH_DP_AUX_CH_CTL(port);
1263 default:
1264 MISSING_CASE(port);
1265 return DP_AUX_CH_CTL(PORT_A);
1266 }
1267}
1268
1269static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1270 enum port port, int index)
1271{
1272 switch (port) {
1273 case PORT_A:
1274 return DP_AUX_CH_DATA(port, index);
1275 case PORT_B:
1276 case PORT_C:
1277 case PORT_D:
1278 return PCH_DP_AUX_CH_DATA(port, index);
1279 default:
1280 MISSING_CASE(port);
1281 return DP_AUX_CH_DATA(PORT_A, index);
1282 }
1283}
1284
1285static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1286 enum port port)
1287{
1288 switch (port) {
1289 case PORT_A:
1290 case PORT_B:
1291 case PORT_C:
1292 case PORT_D:
1293 return DP_AUX_CH_CTL(port);
1294 default:
1295 MISSING_CASE(port);
1296 return DP_AUX_CH_CTL(PORT_A);
1297 }
1298}
1299
1300static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1301 enum port port, int index)
1302{
1303 switch (port) {
1304 case PORT_A:
1305 case PORT_B:
1306 case PORT_C:
1307 case PORT_D:
1308 return DP_AUX_CH_DATA(port, index);
1309 default:
1310 MISSING_CASE(port);
1311 return DP_AUX_CH_DATA(PORT_A, index);
1312 }
1313}
1314
1315static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1316 enum port port)
1317{
1318 if (INTEL_INFO(dev_priv)->gen >= 9)
1319 return skl_aux_ctl_reg(dev_priv, port);
1320 else if (HAS_PCH_SPLIT(dev_priv))
1321 return ilk_aux_ctl_reg(dev_priv, port);
1322 else
1323 return g4x_aux_ctl_reg(dev_priv, port);
1324}
1325
1326static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1327 enum port port, int index)
1328{
1329 if (INTEL_INFO(dev_priv)->gen >= 9)
1330 return skl_aux_data_reg(dev_priv, port, index);
1331 else if (HAS_PCH_SPLIT(dev_priv))
1332 return ilk_aux_data_reg(dev_priv, port, index);
1333 else
1334 return g4x_aux_data_reg(dev_priv, port, index);
1335}
1336
1337static void intel_aux_reg_init(struct intel_dp *intel_dp)
1338{
1339 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1340 enum port port = intel_aux_port(dev_priv,
1341 dp_to_dig_port(intel_dp)->port);
1342 int i;
1343
1344 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1345 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1346 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1347}
1348
1349static void
1350intel_dp_aux_fini(struct intel_dp *intel_dp)
1351{
1352 kfree(intel_dp->aux.name);
1353}
1354
1355static void
1356intel_dp_aux_init(struct intel_dp *intel_dp)
1357{
1358 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1359 enum port port = intel_dig_port->port;
1360
1361 intel_aux_reg_init(intel_dp);
1362 drm_dp_aux_init(&intel_dp->aux);
1363
1364 /* Failure to allocate our preferred name is not critical */
1365 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1366 intel_dp->aux.transfer = intel_dp_aux_transfer;
1367}
1368
1369bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1370{
1371 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1372 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1373
1374 if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1375 IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1376 return true;
1377 else
1378 return false;
1379}
1380
1381static void
1382intel_dp_set_clock(struct intel_encoder *encoder,
1383 struct intel_crtc_state *pipe_config)
1384{
1385 struct drm_device *dev = encoder->base.dev;
1386 struct drm_i915_private *dev_priv = to_i915(dev);
1387 const struct dp_link_dpll *divisor = NULL;
1388 int i, count = 0;
1389
1390 if (IS_G4X(dev_priv)) {
1391 divisor = gen4_dpll;
1392 count = ARRAY_SIZE(gen4_dpll);
1393 } else if (HAS_PCH_SPLIT(dev_priv)) {
1394 divisor = pch_dpll;
1395 count = ARRAY_SIZE(pch_dpll);
1396 } else if (IS_CHERRYVIEW(dev_priv)) {
1397 divisor = chv_dpll;
1398 count = ARRAY_SIZE(chv_dpll);
1399 } else if (IS_VALLEYVIEW(dev_priv)) {
1400 divisor = vlv_dpll;
1401 count = ARRAY_SIZE(vlv_dpll);
1402 }
1403
1404 if (divisor && count) {
1405 for (i = 0; i < count; i++) {
1406 if (pipe_config->port_clock == divisor[i].clock) {
1407 pipe_config->dpll = divisor[i].dpll;
1408 pipe_config->clock_set = true;
1409 break;
1410 }
1411 }
1412 }
1413}
1414
1415static void snprintf_int_array(char *str, size_t len,
1416 const int *array, int nelem)
1417{
1418 int i;
1419
1420 str[0] = '\0';
1421
1422 for (i = 0; i < nelem; i++) {
1423 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1424 if (r >= len)
1425 return;
1426 str += r;
1427 len -= r;
1428 }
1429}
1430
1431static void intel_dp_print_rates(struct intel_dp *intel_dp)
1432{
1433 const int *source_rates, *sink_rates;
1434 int source_len, sink_len, common_len;
1435 int common_rates[DP_MAX_SUPPORTED_RATES];
1436 char str[128]; /* FIXME: too big for stack? */
1437
1438 if ((drm_debug & DRM_UT_KMS) == 0)
1439 return;
1440
1441 source_len = intel_dp_source_rates(intel_dp, &source_rates);
1442 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1443 DRM_DEBUG_KMS("source rates: %s\n", str);
1444
1445 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1446 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1447 DRM_DEBUG_KMS("sink rates: %s\n", str);
1448
1449 common_len = intel_dp_common_rates(intel_dp, common_rates);
1450 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1451 DRM_DEBUG_KMS("common rates: %s\n", str);
1452}
1453
1454bool
1455__intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
1456{
1457 u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI :
1458 DP_SINK_OUI;
1459
1460 return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) ==
1461 sizeof(*desc);
1462}
1463
1464bool intel_dp_read_desc(struct intel_dp *intel_dp)
1465{
1466 struct intel_dp_desc *desc = &intel_dp->desc;
1467 bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1468 DP_OUI_SUPPORT;
1469 int dev_id_len;
1470
1471 if (!__intel_dp_read_desc(intel_dp, desc))
1472 return false;
1473
1474 dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
1475 DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n",
1476 drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
1477 (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)",
1478 dev_id_len, desc->device_id,
1479 desc->hw_rev >> 4, desc->hw_rev & 0xf,
1480 desc->sw_major_rev, desc->sw_minor_rev);
1481
1482 return true;
1483}
1484
1485static int rate_to_index(int find, const int *rates)
1486{
1487 int i = 0;
1488
1489 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1490 if (find == rates[i])
1491 break;
1492
1493 return i;
1494}
1495
1496int
1497intel_dp_max_link_rate(struct intel_dp *intel_dp)
1498{
1499 int rates[DP_MAX_SUPPORTED_RATES] = {};
1500 int len;
1501
1502 len = intel_dp_common_rates(intel_dp, rates);
1503 if (WARN_ON(len <= 0))
1504 return 162000;
1505
1506 return rates[len - 1];
1507}
1508
1509int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1510{
1511 return rate_to_index(rate, intel_dp->sink_rates);
1512}
1513
1514void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1515 uint8_t *link_bw, uint8_t *rate_select)
1516{
1517 if (intel_dp->num_sink_rates) {
1518 *link_bw = 0;
1519 *rate_select =
1520 intel_dp_rate_select(intel_dp, port_clock);
1521 } else {
1522 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1523 *rate_select = 0;
1524 }
1525}
1526
1527static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1528 struct intel_crtc_state *pipe_config)
1529{
1530 int bpp, bpc;
1531
1532 bpp = pipe_config->pipe_bpp;
1533 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1534
1535 if (bpc > 0)
1536 bpp = min(bpp, 3*bpc);
1537
1538 return bpp;
1539}
1540
1541bool
1542intel_dp_compute_config(struct intel_encoder *encoder,
1543 struct intel_crtc_state *pipe_config,
1544 struct drm_connector_state *conn_state)
1545{
1546 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1547 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1548 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1549 enum port port = dp_to_dig_port(intel_dp)->port;
1550 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1551 struct intel_connector *intel_connector = intel_dp->attached_connector;
1552 int lane_count, clock;
1553 int min_lane_count = 1;
1554 int max_lane_count = intel_dp_max_lane_count(intel_dp);
1555 /* Conveniently, the link BW constants become indices with a shift...*/
1556 int min_clock = 0;
1557 int max_clock;
1558 int bpp, mode_rate;
1559 int link_avail, link_clock;
1560 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1561 int common_len;
1562 uint8_t link_bw, rate_select;
1563
1564 common_len = intel_dp_common_rates(intel_dp, common_rates);
1565
1566 /* No common link rates between source and sink */
1567 WARN_ON(common_len <= 0);
1568
1569 max_clock = common_len - 1;
1570
1571 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1572 pipe_config->has_pch_encoder = true;
1573
1574 pipe_config->has_drrs = false;
1575 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1576
1577 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1578 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1579 adjusted_mode);
1580
1581 if (INTEL_GEN(dev_priv) >= 9) {
1582 int ret;
1583 ret = skl_update_scaler_crtc(pipe_config);
1584 if (ret)
1585 return ret;
1586 }
1587
1588 if (HAS_GMCH_DISPLAY(dev_priv))
1589 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1590 intel_connector->panel.fitting_mode);
1591 else
1592 intel_pch_panel_fitting(intel_crtc, pipe_config,
1593 intel_connector->panel.fitting_mode);
1594 }
1595
1596 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1597 return false;
1598
1599 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1600 "max bw %d pixel clock %iKHz\n",
1601 max_lane_count, common_rates[max_clock],
1602 adjusted_mode->crtc_clock);
1603
1604 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1605 * bpc in between. */
1606 bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1607 if (is_edp(intel_dp)) {
1608
1609 /* Get bpp from vbt only for panels that dont have bpp in edid */
1610 if (intel_connector->base.display_info.bpc == 0 &&
1611 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1612 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1613 dev_priv->vbt.edp.bpp);
1614 bpp = dev_priv->vbt.edp.bpp;
1615 }
1616
1617 /*
1618 * Use the maximum clock and number of lanes the eDP panel
1619 * advertizes being capable of. The panels are generally
1620 * designed to support only a single clock and lane
1621 * configuration, and typically these values correspond to the
1622 * native resolution of the panel.
1623 */
1624 min_lane_count = max_lane_count;
1625 min_clock = max_clock;
1626 }
1627
1628 for (; bpp >= 6*3; bpp -= 2*3) {
1629 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1630 bpp);
1631
1632 for (clock = min_clock; clock <= max_clock; clock++) {
1633 for (lane_count = min_lane_count;
1634 lane_count <= max_lane_count;
1635 lane_count <<= 1) {
1636
1637 link_clock = common_rates[clock];
1638 link_avail = intel_dp_max_data_rate(link_clock,
1639 lane_count);
1640
1641 if (mode_rate <= link_avail) {
1642 goto found;
1643 }
1644 }
1645 }
1646 }
1647
1648 return false;
1649
1650found:
1651 if (intel_dp->color_range_auto) {
1652 /*
1653 * See:
1654 * CEA-861-E - 5.1 Default Encoding Parameters
1655 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1656 */
1657 pipe_config->limited_color_range =
1658 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1659 } else {
1660 pipe_config->limited_color_range =
1661 intel_dp->limited_color_range;
1662 }
1663
1664 pipe_config->lane_count = lane_count;
1665
1666 pipe_config->pipe_bpp = bpp;
1667 pipe_config->port_clock = common_rates[clock];
1668
1669 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1670 &link_bw, &rate_select);
1671
1672 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1673 link_bw, rate_select, pipe_config->lane_count,
1674 pipe_config->port_clock, bpp);
1675 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1676 mode_rate, link_avail);
1677
1678 intel_link_compute_m_n(bpp, lane_count,
1679 adjusted_mode->crtc_clock,
1680 pipe_config->port_clock,
1681 &pipe_config->dp_m_n);
1682
1683 if (intel_connector->panel.downclock_mode != NULL &&
1684 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1685 pipe_config->has_drrs = true;
1686 intel_link_compute_m_n(bpp, lane_count,
1687 intel_connector->panel.downclock_mode->clock,
1688 pipe_config->port_clock,
1689 &pipe_config->dp_m2_n2);
1690 }
1691
1692 /*
1693 * DPLL0 VCO may need to be adjusted to get the correct
1694 * clock for eDP. This will affect cdclk as well.
1695 */
1696 if (is_edp(intel_dp) &&
1697 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1698 int vco;
1699
1700 switch (pipe_config->port_clock / 2) {
1701 case 108000:
1702 case 216000:
1703 vco = 8640000;
1704 break;
1705 default:
1706 vco = 8100000;
1707 break;
1708 }
1709
1710 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1711 }
1712
1713 if (!HAS_DDI(dev_priv))
1714 intel_dp_set_clock(encoder, pipe_config);
1715
1716 return true;
1717}
1718
1719void intel_dp_set_link_params(struct intel_dp *intel_dp,
1720 int link_rate, uint8_t lane_count,
1721 bool link_mst)
1722{
1723 intel_dp->link_rate = link_rate;
1724 intel_dp->lane_count = lane_count;
1725 intel_dp->link_mst = link_mst;
1726}
1727
1728static void intel_dp_prepare(struct intel_encoder *encoder,
1729 struct intel_crtc_state *pipe_config)
1730{
1731 struct drm_device *dev = encoder->base.dev;
1732 struct drm_i915_private *dev_priv = to_i915(dev);
1733 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1734 enum port port = dp_to_dig_port(intel_dp)->port;
1735 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1736 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1737
1738 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1739 pipe_config->lane_count,
1740 intel_crtc_has_type(pipe_config,
1741 INTEL_OUTPUT_DP_MST));
1742
1743 /*
1744 * There are four kinds of DP registers:
1745 *
1746 * IBX PCH
1747 * SNB CPU
1748 * IVB CPU
1749 * CPT PCH
1750 *
1751 * IBX PCH and CPU are the same for almost everything,
1752 * except that the CPU DP PLL is configured in this
1753 * register
1754 *
1755 * CPT PCH is quite different, having many bits moved
1756 * to the TRANS_DP_CTL register instead. That
1757 * configuration happens (oddly) in ironlake_pch_enable
1758 */
1759
1760 /* Preserve the BIOS-computed detected bit. This is
1761 * supposed to be read-only.
1762 */
1763 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1764
1765 /* Handle DP bits in common between all three register formats */
1766 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1767 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1768
1769 /* Split out the IBX/CPU vs CPT settings */
1770
1771 if (IS_GEN7(dev_priv) && port == PORT_A) {
1772 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1773 intel_dp->DP |= DP_SYNC_HS_HIGH;
1774 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1775 intel_dp->DP |= DP_SYNC_VS_HIGH;
1776 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1777
1778 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1779 intel_dp->DP |= DP_ENHANCED_FRAMING;
1780
1781 intel_dp->DP |= crtc->pipe << 29;
1782 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1783 u32 trans_dp;
1784
1785 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1786
1787 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1788 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1789 trans_dp |= TRANS_DP_ENH_FRAMING;
1790 else
1791 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1792 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1793 } else {
1794 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1795 intel_dp->DP |= DP_COLOR_RANGE_16_235;
1796
1797 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1798 intel_dp->DP |= DP_SYNC_HS_HIGH;
1799 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1800 intel_dp->DP |= DP_SYNC_VS_HIGH;
1801 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1802
1803 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1804 intel_dp->DP |= DP_ENHANCED_FRAMING;
1805
1806 if (IS_CHERRYVIEW(dev_priv))
1807 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1808 else if (crtc->pipe == PIPE_B)
1809 intel_dp->DP |= DP_PIPEB_SELECT;
1810 }
1811}
1812
1813#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1814#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1815
1816#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1817#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
1818
1819#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1820#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1821
1822static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1823 struct intel_dp *intel_dp);
1824
1825static void wait_panel_status(struct intel_dp *intel_dp,
1826 u32 mask,
1827 u32 value)
1828{
1829 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1830 struct drm_i915_private *dev_priv = to_i915(dev);
1831 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1832
1833 lockdep_assert_held(&dev_priv->pps_mutex);
1834
1835 intel_pps_verify_state(dev_priv, intel_dp);
1836
1837 pp_stat_reg = _pp_stat_reg(intel_dp);
1838 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1839
1840 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1841 mask, value,
1842 I915_READ(pp_stat_reg),
1843 I915_READ(pp_ctrl_reg));
1844
1845 if (intel_wait_for_register(dev_priv,
1846 pp_stat_reg, mask, value,
1847 5000))
1848 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1849 I915_READ(pp_stat_reg),
1850 I915_READ(pp_ctrl_reg));
1851
1852 DRM_DEBUG_KMS("Wait complete\n");
1853}
1854
1855static void wait_panel_on(struct intel_dp *intel_dp)
1856{
1857 DRM_DEBUG_KMS("Wait for panel power on\n");
1858 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1859}
1860
1861static void wait_panel_off(struct intel_dp *intel_dp)
1862{
1863 DRM_DEBUG_KMS("Wait for panel power off time\n");
1864 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1865}
1866
1867static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1868{
1869 ktime_t panel_power_on_time;
1870 s64 panel_power_off_duration;
1871
1872 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1873
1874 /* take the difference of currrent time and panel power off time
1875 * and then make panel wait for t11_t12 if needed. */
1876 panel_power_on_time = ktime_get_boottime();
1877 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1878
1879 /* When we disable the VDD override bit last we have to do the manual
1880 * wait. */
1881 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1882 wait_remaining_ms_from_jiffies(jiffies,
1883 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1884
1885 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1886}
1887
1888static void wait_backlight_on(struct intel_dp *intel_dp)
1889{
1890 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1891 intel_dp->backlight_on_delay);
1892}
1893
1894static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1895{
1896 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1897 intel_dp->backlight_off_delay);
1898}
1899
1900/* Read the current pp_control value, unlocking the register if it
1901 * is locked
1902 */
1903
1904static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1905{
1906 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1907 struct drm_i915_private *dev_priv = to_i915(dev);
1908 u32 control;
1909
1910 lockdep_assert_held(&dev_priv->pps_mutex);
1911
1912 control = I915_READ(_pp_ctrl_reg(intel_dp));
1913 if (WARN_ON(!HAS_DDI(dev_priv) &&
1914 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
1915 control &= ~PANEL_UNLOCK_MASK;
1916 control |= PANEL_UNLOCK_REGS;
1917 }
1918 return control;
1919}
1920
1921/*
1922 * Must be paired with edp_panel_vdd_off().
1923 * Must hold pps_mutex around the whole on/off sequence.
1924 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1925 */
1926static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1927{
1928 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1929 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1930 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1931 struct drm_i915_private *dev_priv = to_i915(dev);
1932 enum intel_display_power_domain power_domain;
1933 u32 pp;
1934 i915_reg_t pp_stat_reg, pp_ctrl_reg;
1935 bool need_to_disable = !intel_dp->want_panel_vdd;
1936
1937 lockdep_assert_held(&dev_priv->pps_mutex);
1938
1939 if (!is_edp(intel_dp))
1940 return false;
1941
1942 cancel_delayed_work(&intel_dp->panel_vdd_work);
1943 intel_dp->want_panel_vdd = true;
1944
1945 if (edp_have_panel_vdd(intel_dp))
1946 return need_to_disable;
1947
1948 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1949 intel_display_power_get(dev_priv, power_domain);
1950
1951 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1952 port_name(intel_dig_port->port));
1953
1954 if (!edp_have_panel_power(intel_dp))
1955 wait_panel_power_cycle(intel_dp);
1956
1957 pp = ironlake_get_pp_control(intel_dp);
1958 pp |= EDP_FORCE_VDD;
1959
1960 pp_stat_reg = _pp_stat_reg(intel_dp);
1961 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1962
1963 I915_WRITE(pp_ctrl_reg, pp);
1964 POSTING_READ(pp_ctrl_reg);
1965 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1966 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1967 /*
1968 * If the panel wasn't on, delay before accessing aux channel
1969 */
1970 if (!edp_have_panel_power(intel_dp)) {
1971 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1972 port_name(intel_dig_port->port));
1973 msleep(intel_dp->panel_power_up_delay);
1974 }
1975
1976 return need_to_disable;
1977}
1978
1979/*
1980 * Must be paired with intel_edp_panel_vdd_off() or
1981 * intel_edp_panel_off().
1982 * Nested calls to these functions are not allowed since
1983 * we drop the lock. Caller must use some higher level
1984 * locking to prevent nested calls from other threads.
1985 */
1986void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1987{
1988 bool vdd;
1989
1990 if (!is_edp(intel_dp))
1991 return;
1992
1993 pps_lock(intel_dp);
1994 vdd = edp_panel_vdd_on(intel_dp);
1995 pps_unlock(intel_dp);
1996
1997 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1998 port_name(dp_to_dig_port(intel_dp)->port));
1999}
2000
2001static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2002{
2003 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2004 struct drm_i915_private *dev_priv = to_i915(dev);
2005 struct intel_digital_port *intel_dig_port =
2006 dp_to_dig_port(intel_dp);
2007 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2008 enum intel_display_power_domain power_domain;
2009 u32 pp;
2010 i915_reg_t pp_stat_reg, pp_ctrl_reg;
2011
2012 lockdep_assert_held(&dev_priv->pps_mutex);
2013
2014 WARN_ON(intel_dp->want_panel_vdd);
2015
2016 if (!edp_have_panel_vdd(intel_dp))
2017 return;
2018
2019 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2020 port_name(intel_dig_port->port));
2021
2022 pp = ironlake_get_pp_control(intel_dp);
2023 pp &= ~EDP_FORCE_VDD;
2024
2025 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2026 pp_stat_reg = _pp_stat_reg(intel_dp);
2027
2028 I915_WRITE(pp_ctrl_reg, pp);
2029 POSTING_READ(pp_ctrl_reg);
2030
2031 /* Make sure sequencer is idle before allowing subsequent activity */
2032 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2033 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2034
2035 if ((pp & PANEL_POWER_ON) == 0)
2036 intel_dp->panel_power_off_time = ktime_get_boottime();
2037
2038 power_domain = intel_display_port_aux_power_domain(intel_encoder);
2039 intel_display_power_put(dev_priv, power_domain);
2040}
2041
2042static void edp_panel_vdd_work(struct work_struct *__work)
2043{
2044 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2045 struct intel_dp, panel_vdd_work);
2046
2047 pps_lock(intel_dp);
2048 if (!intel_dp->want_panel_vdd)
2049 edp_panel_vdd_off_sync(intel_dp);
2050 pps_unlock(intel_dp);
2051}
2052
2053static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2054{
2055 unsigned long delay;
2056
2057 /*
2058 * Queue the timer to fire a long time from now (relative to the power
2059 * down delay) to keep the panel power up across a sequence of
2060 * operations.
2061 */
2062 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2063 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2064}
2065
2066/*
2067 * Must be paired with edp_panel_vdd_on().
2068 * Must hold pps_mutex around the whole on/off sequence.
2069 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2070 */
2071static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2072{
2073 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2074
2075 lockdep_assert_held(&dev_priv->pps_mutex);
2076
2077 if (!is_edp(intel_dp))
2078 return;
2079
2080 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2081 port_name(dp_to_dig_port(intel_dp)->port));
2082
2083 intel_dp->want_panel_vdd = false;
2084
2085 if (sync)
2086 edp_panel_vdd_off_sync(intel_dp);
2087 else
2088 edp_panel_vdd_schedule_off(intel_dp);
2089}
2090
2091static void edp_panel_on(struct intel_dp *intel_dp)
2092{
2093 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2094 struct drm_i915_private *dev_priv = to_i915(dev);
2095 u32 pp;
2096 i915_reg_t pp_ctrl_reg;
2097
2098 lockdep_assert_held(&dev_priv->pps_mutex);
2099
2100 if (!is_edp(intel_dp))
2101 return;
2102
2103 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2104 port_name(dp_to_dig_port(intel_dp)->port));
2105
2106 if (WARN(edp_have_panel_power(intel_dp),
2107 "eDP port %c panel power already on\n",
2108 port_name(dp_to_dig_port(intel_dp)->port)))
2109 return;
2110
2111 wait_panel_power_cycle(intel_dp);
2112
2113 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2114 pp = ironlake_get_pp_control(intel_dp);
2115 if (IS_GEN5(dev_priv)) {
2116 /* ILK workaround: disable reset around power sequence */
2117 pp &= ~PANEL_POWER_RESET;
2118 I915_WRITE(pp_ctrl_reg, pp);
2119 POSTING_READ(pp_ctrl_reg);
2120 }
2121
2122 pp |= PANEL_POWER_ON;
2123 if (!IS_GEN5(dev_priv))
2124 pp |= PANEL_POWER_RESET;
2125
2126 I915_WRITE(pp_ctrl_reg, pp);
2127 POSTING_READ(pp_ctrl_reg);
2128
2129 wait_panel_on(intel_dp);
2130 intel_dp->last_power_on = jiffies;
2131
2132 if (IS_GEN5(dev_priv)) {
2133 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2134 I915_WRITE(pp_ctrl_reg, pp);
2135 POSTING_READ(pp_ctrl_reg);
2136 }
2137}
2138
2139void intel_edp_panel_on(struct intel_dp *intel_dp)
2140{
2141 if (!is_edp(intel_dp))
2142 return;
2143
2144 pps_lock(intel_dp);
2145 edp_panel_on(intel_dp);
2146 pps_unlock(intel_dp);
2147}
2148
2149
2150static void edp_panel_off(struct intel_dp *intel_dp)
2151{
2152 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2153 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2154 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2155 struct drm_i915_private *dev_priv = to_i915(dev);
2156 enum intel_display_power_domain power_domain;
2157 u32 pp;
2158 i915_reg_t pp_ctrl_reg;
2159
2160 lockdep_assert_held(&dev_priv->pps_mutex);
2161
2162 if (!is_edp(intel_dp))
2163 return;
2164
2165 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2166 port_name(dp_to_dig_port(intel_dp)->port));
2167
2168 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2169 port_name(dp_to_dig_port(intel_dp)->port));
2170
2171 pp = ironlake_get_pp_control(intel_dp);
2172 /* We need to switch off panel power _and_ force vdd, for otherwise some
2173 * panels get very unhappy and cease to work. */
2174 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2175 EDP_BLC_ENABLE);
2176
2177 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2178
2179 intel_dp->want_panel_vdd = false;
2180
2181 I915_WRITE(pp_ctrl_reg, pp);
2182 POSTING_READ(pp_ctrl_reg);
2183
2184 intel_dp->panel_power_off_time = ktime_get_boottime();
2185 wait_panel_off(intel_dp);
2186
2187 /* We got a reference when we enabled the VDD. */
2188 power_domain = intel_display_port_aux_power_domain(intel_encoder);
2189 intel_display_power_put(dev_priv, power_domain);
2190}
2191
2192void intel_edp_panel_off(struct intel_dp *intel_dp)
2193{
2194 if (!is_edp(intel_dp))
2195 return;
2196
2197 pps_lock(intel_dp);
2198 edp_panel_off(intel_dp);
2199 pps_unlock(intel_dp);
2200}
2201
2202/* Enable backlight in the panel power control. */
2203static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2204{
2205 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2206 struct drm_device *dev = intel_dig_port->base.base.dev;
2207 struct drm_i915_private *dev_priv = to_i915(dev);
2208 u32 pp;
2209 i915_reg_t pp_ctrl_reg;
2210
2211 /*
2212 * If we enable the backlight right away following a panel power
2213 * on, we may see slight flicker as the panel syncs with the eDP
2214 * link. So delay a bit to make sure the image is solid before
2215 * allowing it to appear.
2216 */
2217 wait_backlight_on(intel_dp);
2218
2219 pps_lock(intel_dp);
2220
2221 pp = ironlake_get_pp_control(intel_dp);
2222 pp |= EDP_BLC_ENABLE;
2223
2224 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2225
2226 I915_WRITE(pp_ctrl_reg, pp);
2227 POSTING_READ(pp_ctrl_reg);
2228
2229 pps_unlock(intel_dp);
2230}
2231
2232/* Enable backlight PWM and backlight PP control. */
2233void intel_edp_backlight_on(struct intel_dp *intel_dp)
2234{
2235 if (!is_edp(intel_dp))
2236 return;
2237
2238 DRM_DEBUG_KMS("\n");
2239
2240 intel_panel_enable_backlight(intel_dp->attached_connector);
2241 _intel_edp_backlight_on(intel_dp);
2242}
2243
2244/* Disable backlight in the panel power control. */
2245static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2246{
2247 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2248 struct drm_i915_private *dev_priv = to_i915(dev);
2249 u32 pp;
2250 i915_reg_t pp_ctrl_reg;
2251
2252 if (!is_edp(intel_dp))
2253 return;
2254
2255 pps_lock(intel_dp);
2256
2257 pp = ironlake_get_pp_control(intel_dp);
2258 pp &= ~EDP_BLC_ENABLE;
2259
2260 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2261
2262 I915_WRITE(pp_ctrl_reg, pp);
2263 POSTING_READ(pp_ctrl_reg);
2264
2265 pps_unlock(intel_dp);
2266
2267 intel_dp->last_backlight_off = jiffies;
2268 edp_wait_backlight_off(intel_dp);
2269}
2270
2271/* Disable backlight PP control and backlight PWM. */
2272void intel_edp_backlight_off(struct intel_dp *intel_dp)
2273{
2274 if (!is_edp(intel_dp))
2275 return;
2276
2277 DRM_DEBUG_KMS("\n");
2278
2279 _intel_edp_backlight_off(intel_dp);
2280 intel_panel_disable_backlight(intel_dp->attached_connector);
2281}
2282
2283/*
2284 * Hook for controlling the panel power control backlight through the bl_power
2285 * sysfs attribute. Take care to handle multiple calls.
2286 */
2287static void intel_edp_backlight_power(struct intel_connector *connector,
2288 bool enable)
2289{
2290 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2291 bool is_enabled;
2292
2293 pps_lock(intel_dp);
2294 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2295 pps_unlock(intel_dp);
2296
2297 if (is_enabled == enable)
2298 return;
2299
2300 DRM_DEBUG_KMS("panel power control backlight %s\n",
2301 enable ? "enable" : "disable");
2302
2303 if (enable)
2304 _intel_edp_backlight_on(intel_dp);
2305 else
2306 _intel_edp_backlight_off(intel_dp);
2307}
2308
2309static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2310{
2311 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2312 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2313 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2314
2315 I915_STATE_WARN(cur_state != state,
2316 "DP port %c state assertion failure (expected %s, current %s)\n",
2317 port_name(dig_port->port),
2318 onoff(state), onoff(cur_state));
2319}
2320#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2321
2322static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2323{
2324 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2325
2326 I915_STATE_WARN(cur_state != state,
2327 "eDP PLL state assertion failure (expected %s, current %s)\n",
2328 onoff(state), onoff(cur_state));
2329}
2330#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2331#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2332
2333static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2334 struct intel_crtc_state *pipe_config)
2335{
2336 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2337 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2338
2339 assert_pipe_disabled(dev_priv, crtc->pipe);
2340 assert_dp_port_disabled(intel_dp);
2341 assert_edp_pll_disabled(dev_priv);
2342
2343 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2344 pipe_config->port_clock);
2345
2346 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2347
2348 if (pipe_config->port_clock == 162000)
2349 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2350 else
2351 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2352
2353 I915_WRITE(DP_A, intel_dp->DP);
2354 POSTING_READ(DP_A);
2355 udelay(500);
2356
2357 /*
2358 * [DevILK] Work around required when enabling DP PLL
2359 * while a pipe is enabled going to FDI:
2360 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2361 * 2. Program DP PLL enable
2362 */
2363 if (IS_GEN5(dev_priv))
2364 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2365
2366 intel_dp->DP |= DP_PLL_ENABLE;
2367
2368 I915_WRITE(DP_A, intel_dp->DP);
2369 POSTING_READ(DP_A);
2370 udelay(200);
2371}
2372
2373static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2374{
2375 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2376 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2377 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2378
2379 assert_pipe_disabled(dev_priv, crtc->pipe);
2380 assert_dp_port_disabled(intel_dp);
2381 assert_edp_pll_enabled(dev_priv);
2382
2383 DRM_DEBUG_KMS("disabling eDP PLL\n");
2384
2385 intel_dp->DP &= ~DP_PLL_ENABLE;
2386
2387 I915_WRITE(DP_A, intel_dp->DP);
2388 POSTING_READ(DP_A);
2389 udelay(200);
2390}
2391
2392/* If the sink supports it, try to set the power state appropriately */
2393void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2394{
2395 int ret, i;
2396
2397 /* Should have a valid DPCD by this point */
2398 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2399 return;
2400
2401 if (mode != DRM_MODE_DPMS_ON) {
2402 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2403 DP_SET_POWER_D3);
2404 } else {
2405 /*
2406 * When turning on, we need to retry for 1ms to give the sink
2407 * time to wake up.
2408 */
2409 for (i = 0; i < 3; i++) {
2410 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2411 DP_SET_POWER_D0);
2412 if (ret == 1)
2413 break;
2414 msleep(1);
2415 }
2416 }
2417
2418 if (ret != 1)
2419 DRM_DEBUG_KMS("failed to %s sink power state\n",
2420 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2421}
2422
2423static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2424 enum pipe *pipe)
2425{
2426 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2427 enum port port = dp_to_dig_port(intel_dp)->port;
2428 struct drm_device *dev = encoder->base.dev;
2429 struct drm_i915_private *dev_priv = to_i915(dev);
2430 enum intel_display_power_domain power_domain;
2431 u32 tmp;
2432 bool ret;
2433
2434 power_domain = intel_display_port_power_domain(encoder);
2435 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2436 return false;
2437
2438 ret = false;
2439
2440 tmp = I915_READ(intel_dp->output_reg);
2441
2442 if (!(tmp & DP_PORT_EN))
2443 goto out;
2444
2445 if (IS_GEN7(dev_priv) && port == PORT_A) {
2446 *pipe = PORT_TO_PIPE_CPT(tmp);
2447 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2448 enum pipe p;
2449
2450 for_each_pipe(dev_priv, p) {
2451 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2452 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2453 *pipe = p;
2454 ret = true;
2455
2456 goto out;
2457 }
2458 }
2459
2460 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2461 i915_mmio_reg_offset(intel_dp->output_reg));
2462 } else if (IS_CHERRYVIEW(dev_priv)) {
2463 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2464 } else {
2465 *pipe = PORT_TO_PIPE(tmp);
2466 }
2467
2468 ret = true;
2469
2470out:
2471 intel_display_power_put(dev_priv, power_domain);
2472
2473 return ret;
2474}
2475
2476static void intel_dp_get_config(struct intel_encoder *encoder,
2477 struct intel_crtc_state *pipe_config)
2478{
2479 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2480 u32 tmp, flags = 0;
2481 struct drm_device *dev = encoder->base.dev;
2482 struct drm_i915_private *dev_priv = to_i915(dev);
2483 enum port port = dp_to_dig_port(intel_dp)->port;
2484 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2485
2486 tmp = I915_READ(intel_dp->output_reg);
2487
2488 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2489
2490 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2491 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2492
2493 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2494 flags |= DRM_MODE_FLAG_PHSYNC;
2495 else
2496 flags |= DRM_MODE_FLAG_NHSYNC;
2497
2498 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2499 flags |= DRM_MODE_FLAG_PVSYNC;
2500 else
2501 flags |= DRM_MODE_FLAG_NVSYNC;
2502 } else {
2503 if (tmp & DP_SYNC_HS_HIGH)
2504 flags |= DRM_MODE_FLAG_PHSYNC;
2505 else
2506 flags |= DRM_MODE_FLAG_NHSYNC;
2507
2508 if (tmp & DP_SYNC_VS_HIGH)
2509 flags |= DRM_MODE_FLAG_PVSYNC;
2510 else
2511 flags |= DRM_MODE_FLAG_NVSYNC;
2512 }
2513
2514 pipe_config->base.adjusted_mode.flags |= flags;
2515
2516 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2517 pipe_config->limited_color_range = true;
2518
2519 pipe_config->lane_count =
2520 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2521
2522 intel_dp_get_m_n(crtc, pipe_config);
2523
2524 if (port == PORT_A) {
2525 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2526 pipe_config->port_clock = 162000;
2527 else
2528 pipe_config->port_clock = 270000;
2529 }
2530
2531 pipe_config->base.adjusted_mode.crtc_clock =
2532 intel_dotclock_calculate(pipe_config->port_clock,
2533 &pipe_config->dp_m_n);
2534
2535 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2536 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2537 /*
2538 * This is a big fat ugly hack.
2539 *
2540 * Some machines in UEFI boot mode provide us a VBT that has 18
2541 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2542 * unknown we fail to light up. Yet the same BIOS boots up with
2543 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2544 * max, not what it tells us to use.
2545 *
2546 * Note: This will still be broken if the eDP panel is not lit
2547 * up by the BIOS, and thus we can't get the mode at module
2548 * load.
2549 */
2550 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2551 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2552 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2553 }
2554}
2555
2556static void intel_disable_dp(struct intel_encoder *encoder,
2557 struct intel_crtc_state *old_crtc_state,
2558 struct drm_connector_state *old_conn_state)
2559{
2560 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2561 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2562
2563 if (old_crtc_state->has_audio)
2564 intel_audio_codec_disable(encoder);
2565
2566 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2567 intel_psr_disable(intel_dp);
2568
2569 /* Make sure the panel is off before trying to change the mode. But also
2570 * ensure that we have vdd while we switch off the panel. */
2571 intel_edp_panel_vdd_on(intel_dp);
2572 intel_edp_backlight_off(intel_dp);
2573 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2574 intel_edp_panel_off(intel_dp);
2575
2576 /* disable the port before the pipe on g4x */
2577 if (INTEL_GEN(dev_priv) < 5)
2578 intel_dp_link_down(intel_dp);
2579}
2580
2581static void ilk_post_disable_dp(struct intel_encoder *encoder,
2582 struct intel_crtc_state *old_crtc_state,
2583 struct drm_connector_state *old_conn_state)
2584{
2585 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2586 enum port port = dp_to_dig_port(intel_dp)->port;
2587
2588 intel_dp_link_down(intel_dp);
2589
2590 /* Only ilk+ has port A */
2591 if (port == PORT_A)
2592 ironlake_edp_pll_off(intel_dp);
2593}
2594
2595static void vlv_post_disable_dp(struct intel_encoder *encoder,
2596 struct intel_crtc_state *old_crtc_state,
2597 struct drm_connector_state *old_conn_state)
2598{
2599 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2600
2601 intel_dp_link_down(intel_dp);
2602}
2603
2604static void chv_post_disable_dp(struct intel_encoder *encoder,
2605 struct intel_crtc_state *old_crtc_state,
2606 struct drm_connector_state *old_conn_state)
2607{
2608 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2609 struct drm_device *dev = encoder->base.dev;
2610 struct drm_i915_private *dev_priv = to_i915(dev);
2611
2612 intel_dp_link_down(intel_dp);
2613
2614 mutex_lock(&dev_priv->sb_lock);
2615
2616 /* Assert data lane reset */
2617 chv_data_lane_soft_reset(encoder, true);
2618
2619 mutex_unlock(&dev_priv->sb_lock);
2620}
2621
2622static void
2623_intel_dp_set_link_train(struct intel_dp *intel_dp,
2624 uint32_t *DP,
2625 uint8_t dp_train_pat)
2626{
2627 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2628 struct drm_device *dev = intel_dig_port->base.base.dev;
2629 struct drm_i915_private *dev_priv = to_i915(dev);
2630 enum port port = intel_dig_port->port;
2631
2632 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2633 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2634 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2635
2636 if (HAS_DDI(dev_priv)) {
2637 uint32_t temp = I915_READ(DP_TP_CTL(port));
2638
2639 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2640 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2641 else
2642 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2643
2644 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2645 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2646 case DP_TRAINING_PATTERN_DISABLE:
2647 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2648
2649 break;
2650 case DP_TRAINING_PATTERN_1:
2651 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2652 break;
2653 case DP_TRAINING_PATTERN_2:
2654 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2655 break;
2656 case DP_TRAINING_PATTERN_3:
2657 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2658 break;
2659 }
2660 I915_WRITE(DP_TP_CTL(port), temp);
2661
2662 } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2663 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2664 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2665
2666 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2667 case DP_TRAINING_PATTERN_DISABLE:
2668 *DP |= DP_LINK_TRAIN_OFF_CPT;
2669 break;
2670 case DP_TRAINING_PATTERN_1:
2671 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2672 break;
2673 case DP_TRAINING_PATTERN_2:
2674 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2675 break;
2676 case DP_TRAINING_PATTERN_3:
2677 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2678 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2679 break;
2680 }
2681
2682 } else {
2683 if (IS_CHERRYVIEW(dev_priv))
2684 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2685 else
2686 *DP &= ~DP_LINK_TRAIN_MASK;
2687
2688 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2689 case DP_TRAINING_PATTERN_DISABLE:
2690 *DP |= DP_LINK_TRAIN_OFF;
2691 break;
2692 case DP_TRAINING_PATTERN_1:
2693 *DP |= DP_LINK_TRAIN_PAT_1;
2694 break;
2695 case DP_TRAINING_PATTERN_2:
2696 *DP |= DP_LINK_TRAIN_PAT_2;
2697 break;
2698 case DP_TRAINING_PATTERN_3:
2699 if (IS_CHERRYVIEW(dev_priv)) {
2700 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2701 } else {
2702 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2703 *DP |= DP_LINK_TRAIN_PAT_2;
2704 }
2705 break;
2706 }
2707 }
2708}
2709
2710static void intel_dp_enable_port(struct intel_dp *intel_dp,
2711 struct intel_crtc_state *old_crtc_state)
2712{
2713 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2714 struct drm_i915_private *dev_priv = to_i915(dev);
2715
2716 /* enable with pattern 1 (as per spec) */
2717
2718 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2719
2720 /*
2721 * Magic for VLV/CHV. We _must_ first set up the register
2722 * without actually enabling the port, and then do another
2723 * write to enable the port. Otherwise link training will
2724 * fail when the power sequencer is freshly used for this port.
2725 */
2726 intel_dp->DP |= DP_PORT_EN;
2727 if (old_crtc_state->has_audio)
2728 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2729
2730 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2731 POSTING_READ(intel_dp->output_reg);
2732}
2733
2734static void intel_enable_dp(struct intel_encoder *encoder,
2735 struct intel_crtc_state *pipe_config,
2736 struct drm_connector_state *conn_state)
2737{
2738 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2739 struct drm_device *dev = encoder->base.dev;
2740 struct drm_i915_private *dev_priv = to_i915(dev);
2741 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2742 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2743 enum pipe pipe = crtc->pipe;
2744
2745 if (WARN_ON(dp_reg & DP_PORT_EN))
2746 return;
2747
2748 pps_lock(intel_dp);
2749
2750 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2751 vlv_init_panel_power_sequencer(intel_dp);
2752
2753 intel_dp_enable_port(intel_dp, pipe_config);
2754
2755 edp_panel_vdd_on(intel_dp);
2756 edp_panel_on(intel_dp);
2757 edp_panel_vdd_off(intel_dp, true);
2758
2759 pps_unlock(intel_dp);
2760
2761 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2762 unsigned int lane_mask = 0x0;
2763
2764 if (IS_CHERRYVIEW(dev_priv))
2765 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2766
2767 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2768 lane_mask);
2769 }
2770
2771 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2772 intel_dp_start_link_train(intel_dp);
2773 intel_dp_stop_link_train(intel_dp);
2774
2775 if (pipe_config->has_audio) {
2776 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2777 pipe_name(pipe));
2778 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2779 }
2780}
2781
2782static void g4x_enable_dp(struct intel_encoder *encoder,
2783 struct intel_crtc_state *pipe_config,
2784 struct drm_connector_state *conn_state)
2785{
2786 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2787
2788 intel_enable_dp(encoder, pipe_config, conn_state);
2789 intel_edp_backlight_on(intel_dp);
2790}
2791
2792static void vlv_enable_dp(struct intel_encoder *encoder,
2793 struct intel_crtc_state *pipe_config,
2794 struct drm_connector_state *conn_state)
2795{
2796 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2797
2798 intel_edp_backlight_on(intel_dp);
2799 intel_psr_enable(intel_dp);
2800}
2801
2802static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2803 struct intel_crtc_state *pipe_config,
2804 struct drm_connector_state *conn_state)
2805{
2806 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2807 enum port port = dp_to_dig_port(intel_dp)->port;
2808
2809 intel_dp_prepare(encoder, pipe_config);
2810
2811 /* Only ilk+ has port A */
2812 if (port == PORT_A)
2813 ironlake_edp_pll_on(intel_dp, pipe_config);
2814}
2815
2816static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2817{
2818 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2819 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2820 enum pipe pipe = intel_dp->pps_pipe;
2821 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2822
2823 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2824 return;
2825
2826 edp_panel_vdd_off_sync(intel_dp);
2827
2828 /*
2829 * VLV seems to get confused when multiple power seqeuencers
2830 * have the same port selected (even if only one has power/vdd
2831 * enabled). The failure manifests as vlv_wait_port_ready() failing
2832 * CHV on the other hand doesn't seem to mind having the same port
2833 * selected in multiple power seqeuencers, but let's clear the
2834 * port select always when logically disconnecting a power sequencer
2835 * from a port.
2836 */
2837 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2838 pipe_name(pipe), port_name(intel_dig_port->port));
2839 I915_WRITE(pp_on_reg, 0);
2840 POSTING_READ(pp_on_reg);
2841
2842 intel_dp->pps_pipe = INVALID_PIPE;
2843}
2844
2845static void vlv_steal_power_sequencer(struct drm_device *dev,
2846 enum pipe pipe)
2847{
2848 struct drm_i915_private *dev_priv = to_i915(dev);
2849 struct intel_encoder *encoder;
2850
2851 lockdep_assert_held(&dev_priv->pps_mutex);
2852
2853 for_each_intel_encoder(dev, encoder) {
2854 struct intel_dp *intel_dp;
2855 enum port port;
2856
2857 if (encoder->type != INTEL_OUTPUT_EDP)
2858 continue;
2859
2860 intel_dp = enc_to_intel_dp(&encoder->base);
2861 port = dp_to_dig_port(intel_dp)->port;
2862
2863 if (intel_dp->pps_pipe != pipe)
2864 continue;
2865
2866 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2867 pipe_name(pipe), port_name(port));
2868
2869 WARN(encoder->base.crtc,
2870 "stealing pipe %c power sequencer from active eDP port %c\n",
2871 pipe_name(pipe), port_name(port));
2872
2873 /* make sure vdd is off before we steal it */
2874 vlv_detach_power_sequencer(intel_dp);
2875 }
2876}
2877
2878static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2879{
2880 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2881 struct intel_encoder *encoder = &intel_dig_port->base;
2882 struct drm_device *dev = encoder->base.dev;
2883 struct drm_i915_private *dev_priv = to_i915(dev);
2884 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2885
2886 lockdep_assert_held(&dev_priv->pps_mutex);
2887
2888 if (!is_edp(intel_dp))
2889 return;
2890
2891 if (intel_dp->pps_pipe == crtc->pipe)
2892 return;
2893
2894 /*
2895 * If another power sequencer was being used on this
2896 * port previously make sure to turn off vdd there while
2897 * we still have control of it.
2898 */
2899 if (intel_dp->pps_pipe != INVALID_PIPE)
2900 vlv_detach_power_sequencer(intel_dp);
2901
2902 /*
2903 * We may be stealing the power
2904 * sequencer from another port.
2905 */
2906 vlv_steal_power_sequencer(dev, crtc->pipe);
2907
2908 /* now it's all ours */
2909 intel_dp->pps_pipe = crtc->pipe;
2910
2911 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2912 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2913
2914 /* init power sequencer on this pipe and port */
2915 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2916 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
2917}
2918
2919static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2920 struct intel_crtc_state *pipe_config,
2921 struct drm_connector_state *conn_state)
2922{
2923 vlv_phy_pre_encoder_enable(encoder);
2924
2925 intel_enable_dp(encoder, pipe_config, conn_state);
2926}
2927
2928static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
2929 struct intel_crtc_state *pipe_config,
2930 struct drm_connector_state *conn_state)
2931{
2932 intel_dp_prepare(encoder, pipe_config);
2933
2934 vlv_phy_pre_pll_enable(encoder);
2935}
2936
2937static void chv_pre_enable_dp(struct intel_encoder *encoder,
2938 struct intel_crtc_state *pipe_config,
2939 struct drm_connector_state *conn_state)
2940{
2941 chv_phy_pre_encoder_enable(encoder);
2942
2943 intel_enable_dp(encoder, pipe_config, conn_state);
2944
2945 /* Second common lane will stay alive on its own now */
2946 chv_phy_release_cl2_override(encoder);
2947}
2948
2949static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
2950 struct intel_crtc_state *pipe_config,
2951 struct drm_connector_state *conn_state)
2952{
2953 intel_dp_prepare(encoder, pipe_config);
2954
2955 chv_phy_pre_pll_enable(encoder);
2956}
2957
2958static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
2959 struct intel_crtc_state *pipe_config,
2960 struct drm_connector_state *conn_state)
2961{
2962 chv_phy_post_pll_disable(encoder);
2963}
2964
2965/*
2966 * Fetch AUX CH registers 0x202 - 0x207 which contain
2967 * link status information
2968 */
2969bool
2970intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2971{
2972 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2973 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2974}
2975
2976/* These are source-specific values. */
2977uint8_t
2978intel_dp_voltage_max(struct intel_dp *intel_dp)
2979{
2980 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2981 enum port port = dp_to_dig_port(intel_dp)->port;
2982
2983 if (IS_BROXTON(dev_priv))
2984 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2985 else if (INTEL_GEN(dev_priv) >= 9) {
2986 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
2987 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2988 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2989 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2990 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2991 else if (IS_GEN7(dev_priv) && port == PORT_A)
2992 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2993 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2994 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2995 else
2996 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2997}
2998
2999uint8_t
3000intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3001{
3002 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3003 enum port port = dp_to_dig_port(intel_dp)->port;
3004
3005 if (INTEL_GEN(dev_priv) >= 9) {
3006 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3007 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3008 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3010 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3012 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3014 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3015 default:
3016 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3017 }
3018 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3019 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3020 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3021 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3023 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3024 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3025 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3027 default:
3028 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3029 }
3030 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3031 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3033 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3035 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3037 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3039 default:
3040 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3041 }
3042 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3043 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3044 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3045 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3048 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3049 default:
3050 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3051 }
3052 } else {
3053 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3054 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3055 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3057 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3059 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3061 default:
3062 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3063 }
3064 }
3065}
3066
3067static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3068{
3069 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3070 unsigned long demph_reg_value, preemph_reg_value,
3071 uniqtranscale_reg_value;
3072 uint8_t train_set = intel_dp->train_set[0];
3073
3074 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3075 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3076 preemph_reg_value = 0x0004000;
3077 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3078 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3079 demph_reg_value = 0x2B405555;
3080 uniqtranscale_reg_value = 0x552AB83A;
3081 break;
3082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3083 demph_reg_value = 0x2B404040;
3084 uniqtranscale_reg_value = 0x5548B83A;
3085 break;
3086 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3087 demph_reg_value = 0x2B245555;
3088 uniqtranscale_reg_value = 0x5560B83A;
3089 break;
3090 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3091 demph_reg_value = 0x2B405555;
3092 uniqtranscale_reg_value = 0x5598DA3A;
3093 break;
3094 default:
3095 return 0;
3096 }
3097 break;
3098 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3099 preemph_reg_value = 0x0002000;
3100 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3102 demph_reg_value = 0x2B404040;
3103 uniqtranscale_reg_value = 0x5552B83A;
3104 break;
3105 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3106 demph_reg_value = 0x2B404848;
3107 uniqtranscale_reg_value = 0x5580B83A;
3108 break;
3109 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3110 demph_reg_value = 0x2B404040;
3111 uniqtranscale_reg_value = 0x55ADDA3A;
3112 break;
3113 default:
3114 return 0;
3115 }
3116 break;
3117 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3118 preemph_reg_value = 0x0000000;
3119 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3121 demph_reg_value = 0x2B305555;
3122 uniqtranscale_reg_value = 0x5570B83A;
3123 break;
3124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3125 demph_reg_value = 0x2B2B4040;
3126 uniqtranscale_reg_value = 0x55ADDA3A;
3127 break;
3128 default:
3129 return 0;
3130 }
3131 break;
3132 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3133 preemph_reg_value = 0x0006000;
3134 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3136 demph_reg_value = 0x1B405555;
3137 uniqtranscale_reg_value = 0x55ADDA3A;
3138 break;
3139 default:
3140 return 0;
3141 }
3142 break;
3143 default:
3144 return 0;
3145 }
3146
3147 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3148 uniqtranscale_reg_value, 0);
3149
3150 return 0;
3151}
3152
3153static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3154{
3155 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3156 u32 deemph_reg_value, margin_reg_value;
3157 bool uniq_trans_scale = false;
3158 uint8_t train_set = intel_dp->train_set[0];
3159
3160 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3161 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3162 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3164 deemph_reg_value = 128;
3165 margin_reg_value = 52;
3166 break;
3167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3168 deemph_reg_value = 128;
3169 margin_reg_value = 77;
3170 break;
3171 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3172 deemph_reg_value = 128;
3173 margin_reg_value = 102;
3174 break;
3175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3176 deemph_reg_value = 128;
3177 margin_reg_value = 154;
3178 uniq_trans_scale = true;
3179 break;
3180 default:
3181 return 0;
3182 }
3183 break;
3184 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3185 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3187 deemph_reg_value = 85;
3188 margin_reg_value = 78;
3189 break;
3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3191 deemph_reg_value = 85;
3192 margin_reg_value = 116;
3193 break;
3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3195 deemph_reg_value = 85;
3196 margin_reg_value = 154;
3197 break;
3198 default:
3199 return 0;
3200 }
3201 break;
3202 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3203 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3205 deemph_reg_value = 64;
3206 margin_reg_value = 104;
3207 break;
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3209 deemph_reg_value = 64;
3210 margin_reg_value = 154;
3211 break;
3212 default:
3213 return 0;
3214 }
3215 break;
3216 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3217 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3219 deemph_reg_value = 43;
3220 margin_reg_value = 154;
3221 break;
3222 default:
3223 return 0;
3224 }
3225 break;
3226 default:
3227 return 0;
3228 }
3229
3230 chv_set_phy_signal_level(encoder, deemph_reg_value,
3231 margin_reg_value, uniq_trans_scale);
3232
3233 return 0;
3234}
3235
3236static uint32_t
3237gen4_signal_levels(uint8_t train_set)
3238{
3239 uint32_t signal_levels = 0;
3240
3241 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3243 default:
3244 signal_levels |= DP_VOLTAGE_0_4;
3245 break;
3246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3247 signal_levels |= DP_VOLTAGE_0_6;
3248 break;
3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3250 signal_levels |= DP_VOLTAGE_0_8;
3251 break;
3252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3253 signal_levels |= DP_VOLTAGE_1_2;
3254 break;
3255 }
3256 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3257 case DP_TRAIN_PRE_EMPH_LEVEL_0:
3258 default:
3259 signal_levels |= DP_PRE_EMPHASIS_0;
3260 break;
3261 case DP_TRAIN_PRE_EMPH_LEVEL_1:
3262 signal_levels |= DP_PRE_EMPHASIS_3_5;
3263 break;
3264 case DP_TRAIN_PRE_EMPH_LEVEL_2:
3265 signal_levels |= DP_PRE_EMPHASIS_6;
3266 break;
3267 case DP_TRAIN_PRE_EMPH_LEVEL_3:
3268 signal_levels |= DP_PRE_EMPHASIS_9_5;
3269 break;
3270 }
3271 return signal_levels;
3272}
3273
3274/* Gen6's DP voltage swing and pre-emphasis control */
3275static uint32_t
3276gen6_edp_signal_levels(uint8_t train_set)
3277{
3278 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3279 DP_TRAIN_PRE_EMPHASIS_MASK);
3280 switch (signal_levels) {
3281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3282 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3283 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3284 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3285 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3288 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3291 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3294 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3295 default:
3296 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3297 "0x%x\n", signal_levels);
3298 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3299 }
3300}
3301
3302/* Gen7's DP voltage swing and pre-emphasis control */
3303static uint32_t
3304gen7_edp_signal_levels(uint8_t train_set)
3305{
3306 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3307 DP_TRAIN_PRE_EMPHASIS_MASK);
3308 switch (signal_levels) {
3309 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3310 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3311 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3312 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3314 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3315
3316 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3317 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3318 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3319 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3320
3321 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3322 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3323 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3324 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3325
3326 default:
3327 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3328 "0x%x\n", signal_levels);
3329 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3330 }
3331}
3332
3333void
3334intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3335{
3336 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3337 enum port port = intel_dig_port->port;
3338 struct drm_device *dev = intel_dig_port->base.base.dev;
3339 struct drm_i915_private *dev_priv = to_i915(dev);
3340 uint32_t signal_levels, mask = 0;
3341 uint8_t train_set = intel_dp->train_set[0];
3342
3343 if (HAS_DDI(dev_priv)) {
3344 signal_levels = ddi_signal_levels(intel_dp);
3345
3346 if (IS_BROXTON(dev_priv))
3347 signal_levels = 0;
3348 else
3349 mask = DDI_BUF_EMP_MASK;
3350 } else if (IS_CHERRYVIEW(dev_priv)) {
3351 signal_levels = chv_signal_levels(intel_dp);
3352 } else if (IS_VALLEYVIEW(dev_priv)) {
3353 signal_levels = vlv_signal_levels(intel_dp);
3354 } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3355 signal_levels = gen7_edp_signal_levels(train_set);
3356 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3357 } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3358 signal_levels = gen6_edp_signal_levels(train_set);
3359 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3360 } else {
3361 signal_levels = gen4_signal_levels(train_set);
3362 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3363 }
3364
3365 if (mask)
3366 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3367
3368 DRM_DEBUG_KMS("Using vswing level %d\n",
3369 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3370 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3371 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3372 DP_TRAIN_PRE_EMPHASIS_SHIFT);
3373
3374 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3375
3376 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3377 POSTING_READ(intel_dp->output_reg);
3378}
3379
3380void
3381intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3382 uint8_t dp_train_pat)
3383{
3384 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3385 struct drm_i915_private *dev_priv =
3386 to_i915(intel_dig_port->base.base.dev);
3387
3388 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3389
3390 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3391 POSTING_READ(intel_dp->output_reg);
3392}
3393
3394void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3395{
3396 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3397 struct drm_device *dev = intel_dig_port->base.base.dev;
3398 struct drm_i915_private *dev_priv = to_i915(dev);
3399 enum port port = intel_dig_port->port;
3400 uint32_t val;
3401
3402 if (!HAS_DDI(dev_priv))
3403 return;
3404
3405 val = I915_READ(DP_TP_CTL(port));
3406 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3407 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3408 I915_WRITE(DP_TP_CTL(port), val);
3409
3410 /*
3411 * On PORT_A we can have only eDP in SST mode. There the only reason
3412 * we need to set idle transmission mode is to work around a HW issue
3413 * where we enable the pipe while not in idle link-training mode.
3414 * In this case there is requirement to wait for a minimum number of
3415 * idle patterns to be sent.
3416 */
3417 if (port == PORT_A)
3418 return;
3419
3420 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3421 DP_TP_STATUS_IDLE_DONE,
3422 DP_TP_STATUS_IDLE_DONE,
3423 1))
3424 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3425}
3426
3427static void
3428intel_dp_link_down(struct intel_dp *intel_dp)
3429{
3430 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3431 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3432 enum port port = intel_dig_port->port;
3433 struct drm_device *dev = intel_dig_port->base.base.dev;
3434 struct drm_i915_private *dev_priv = to_i915(dev);
3435 uint32_t DP = intel_dp->DP;
3436
3437 if (WARN_ON(HAS_DDI(dev_priv)))
3438 return;
3439
3440 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3441 return;
3442
3443 DRM_DEBUG_KMS("\n");
3444
3445 if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3446 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3447 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3448 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3449 } else {
3450 if (IS_CHERRYVIEW(dev_priv))
3451 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3452 else
3453 DP &= ~DP_LINK_TRAIN_MASK;
3454 DP |= DP_LINK_TRAIN_PAT_IDLE;
3455 }
3456 I915_WRITE(intel_dp->output_reg, DP);
3457 POSTING_READ(intel_dp->output_reg);
3458
3459 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3460 I915_WRITE(intel_dp->output_reg, DP);
3461 POSTING_READ(intel_dp->output_reg);
3462
3463 /*
3464 * HW workaround for IBX, we need to move the port
3465 * to transcoder A after disabling it to allow the
3466 * matching HDMI port to be enabled on transcoder A.
3467 */
3468 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3469 /*
3470 * We get CPU/PCH FIFO underruns on the other pipe when
3471 * doing the workaround. Sweep them under the rug.
3472 */
3473 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3474 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3475
3476 /* always enable with pattern 1 (as per spec) */
3477 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3478 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3479 I915_WRITE(intel_dp->output_reg, DP);
3480 POSTING_READ(intel_dp->output_reg);
3481
3482 DP &= ~DP_PORT_EN;
3483 I915_WRITE(intel_dp->output_reg, DP);
3484 POSTING_READ(intel_dp->output_reg);
3485
3486 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3487 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3488 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3489 }
3490
3491 msleep(intel_dp->panel_power_down_delay);
3492
3493 intel_dp->DP = DP;
3494}
3495
3496bool
3497intel_dp_read_dpcd(struct intel_dp *intel_dp)
3498{
3499 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3500 sizeof(intel_dp->dpcd)) < 0)
3501 return false; /* aux transfer failed */
3502
3503 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3504
3505 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3506}
3507
3508static bool
3509intel_edp_init_dpcd(struct intel_dp *intel_dp)
3510{
3511 struct drm_i915_private *dev_priv =
3512 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3513
3514 /* this function is meant to be called only once */
3515 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3516
3517 if (!intel_dp_read_dpcd(intel_dp))
3518 return false;
3519
3520 intel_dp_read_desc(intel_dp);
3521
3522 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3523 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3524 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3525
3526 /* Check if the panel supports PSR */
3527 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3528 intel_dp->psr_dpcd,
3529 sizeof(intel_dp->psr_dpcd));
3530 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3531 dev_priv->psr.sink_support = true;
3532 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3533 }
3534
3535 if (INTEL_GEN(dev_priv) >= 9 &&
3536 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3537 uint8_t frame_sync_cap;
3538
3539 dev_priv->psr.sink_support = true;
3540 drm_dp_dpcd_read(&intel_dp->aux,
3541 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3542 &frame_sync_cap, 1);
3543 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3544 /* PSR2 needs frame sync as well */
3545 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3546 DRM_DEBUG_KMS("PSR2 %s on sink",
3547 dev_priv->psr.psr2_support ? "supported" : "not supported");
3548 }
3549
3550 /* Read the eDP Display control capabilities registers */
3551 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3552 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3553 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3554 sizeof(intel_dp->edp_dpcd))
3555 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3556 intel_dp->edp_dpcd);
3557
3558 /* Intermediate frequency support */
3559 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3560 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3561 int i;
3562
3563 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3564 sink_rates, sizeof(sink_rates));
3565
3566 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3567 int val = le16_to_cpu(sink_rates[i]);
3568
3569 if (val == 0)
3570 break;
3571
3572 /* Value read is in kHz while drm clock is saved in deca-kHz */
3573 intel_dp->sink_rates[i] = (val * 200) / 10;
3574 }
3575 intel_dp->num_sink_rates = i;
3576 }
3577
3578 return true;
3579}
3580
3581
3582static bool
3583intel_dp_get_dpcd(struct intel_dp *intel_dp)
3584{
3585 if (!intel_dp_read_dpcd(intel_dp))
3586 return false;
3587
3588 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3589 &intel_dp->sink_count, 1) < 0)
3590 return false;
3591
3592 /*
3593 * Sink count can change between short pulse hpd hence
3594 * a member variable in intel_dp will track any changes
3595 * between short pulse interrupts.
3596 */
3597 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3598
3599 /*
3600 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3601 * a dongle is present but no display. Unless we require to know
3602 * if a dongle is present or not, we don't need to update
3603 * downstream port information. So, an early return here saves
3604 * time from performing other operations which are not required.
3605 */
3606 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3607 return false;
3608
3609 if (!drm_dp_is_branch(intel_dp->dpcd))
3610 return true; /* native DP sink */
3611
3612 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3613 return true; /* no per-port downstream info */
3614
3615 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3616 intel_dp->downstream_ports,
3617 DP_MAX_DOWNSTREAM_PORTS) < 0)
3618 return false; /* downstream port status fetch failed */
3619
3620 return true;
3621}
3622
3623static bool
3624intel_dp_can_mst(struct intel_dp *intel_dp)
3625{
3626 u8 buf[1];
3627
3628 if (!i915.enable_dp_mst)
3629 return false;
3630
3631 if (!intel_dp->can_mst)
3632 return false;
3633
3634 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3635 return false;
3636
3637 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3638 return false;
3639
3640 return buf[0] & DP_MST_CAP;
3641}
3642
3643static void
3644intel_dp_configure_mst(struct intel_dp *intel_dp)
3645{
3646 if (!i915.enable_dp_mst)
3647 return;
3648
3649 if (!intel_dp->can_mst)
3650 return;
3651
3652 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3653
3654 if (intel_dp->is_mst)
3655 DRM_DEBUG_KMS("Sink is MST capable\n");
3656 else
3657 DRM_DEBUG_KMS("Sink is not MST capable\n");
3658
3659 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3660 intel_dp->is_mst);
3661}
3662
3663static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3664{
3665 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3666 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3667 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3668 u8 buf;
3669 int ret = 0;
3670 int count = 0;
3671 int attempts = 10;
3672
3673 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3674 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3675 ret = -EIO;
3676 goto out;
3677 }
3678
3679 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3680 buf & ~DP_TEST_SINK_START) < 0) {
3681 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3682 ret = -EIO;
3683 goto out;
3684 }
3685
3686 do {
3687 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3688
3689 if (drm_dp_dpcd_readb(&intel_dp->aux,
3690 DP_TEST_SINK_MISC, &buf) < 0) {
3691 ret = -EIO;
3692 goto out;
3693 }
3694 count = buf & DP_TEST_COUNT_MASK;
3695 } while (--attempts && count);
3696
3697 if (attempts == 0) {
3698 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3699 ret = -ETIMEDOUT;
3700 }
3701
3702 out:
3703 hsw_enable_ips(intel_crtc);
3704 return ret;
3705}
3706
3707static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3708{
3709 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3710 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3711 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3712 u8 buf;
3713 int ret;
3714
3715 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3716 return -EIO;
3717
3718 if (!(buf & DP_TEST_CRC_SUPPORTED))
3719 return -ENOTTY;
3720
3721 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3722 return -EIO;
3723
3724 if (buf & DP_TEST_SINK_START) {
3725 ret = intel_dp_sink_crc_stop(intel_dp);
3726 if (ret)
3727 return ret;
3728 }
3729
3730 hsw_disable_ips(intel_crtc);
3731
3732 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3733 buf | DP_TEST_SINK_START) < 0) {
3734 hsw_enable_ips(intel_crtc);
3735 return -EIO;
3736 }
3737
3738 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3739 return 0;
3740}
3741
3742int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3743{
3744 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3745 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3746 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3747 u8 buf;
3748 int count, ret;
3749 int attempts = 6;
3750
3751 ret = intel_dp_sink_crc_start(intel_dp);
3752 if (ret)
3753 return ret;
3754
3755 do {
3756 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3757
3758 if (drm_dp_dpcd_readb(&intel_dp->aux,
3759 DP_TEST_SINK_MISC, &buf) < 0) {
3760 ret = -EIO;
3761 goto stop;
3762 }
3763 count = buf & DP_TEST_COUNT_MASK;
3764
3765 } while (--attempts && count == 0);
3766
3767 if (attempts == 0) {
3768 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3769 ret = -ETIMEDOUT;
3770 goto stop;
3771 }
3772
3773 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3774 ret = -EIO;
3775 goto stop;
3776 }
3777
3778stop:
3779 intel_dp_sink_crc_stop(intel_dp);
3780 return ret;
3781}
3782
3783static bool
3784intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3785{
3786 return drm_dp_dpcd_read(&intel_dp->aux,
3787 DP_DEVICE_SERVICE_IRQ_VECTOR,
3788 sink_irq_vector, 1) == 1;
3789}
3790
3791static bool
3792intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3793{
3794 int ret;
3795
3796 ret = drm_dp_dpcd_read(&intel_dp->aux,
3797 DP_SINK_COUNT_ESI,
3798 sink_irq_vector, 14);
3799 if (ret != 14)
3800 return false;
3801
3802 return true;
3803}
3804
3805static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3806{
3807 uint8_t test_result = DP_TEST_ACK;
3808 return test_result;
3809}
3810
3811static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3812{
3813 uint8_t test_result = DP_TEST_NAK;
3814 return test_result;
3815}
3816
3817static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
3818{
3819 uint8_t test_result = DP_TEST_NAK;
3820 struct intel_connector *intel_connector = intel_dp->attached_connector;
3821 struct drm_connector *connector = &intel_connector->base;
3822
3823 if (intel_connector->detect_edid == NULL ||
3824 connector->edid_corrupt ||
3825 intel_dp->aux.i2c_defer_count > 6) {
3826 /* Check EDID read for NACKs, DEFERs and corruption
3827 * (DP CTS 1.2 Core r1.1)
3828 * 4.2.2.4 : Failed EDID read, I2C_NAK
3829 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3830 * 4.2.2.6 : EDID corruption detected
3831 * Use failsafe mode for all cases
3832 */
3833 if (intel_dp->aux.i2c_nack_count > 0 ||
3834 intel_dp->aux.i2c_defer_count > 0)
3835 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3836 intel_dp->aux.i2c_nack_count,
3837 intel_dp->aux.i2c_defer_count);
3838 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3839 } else {
3840 struct edid *block = intel_connector->detect_edid;
3841
3842 /* We have to write the checksum
3843 * of the last block read
3844 */
3845 block += intel_connector->detect_edid->extensions;
3846
3847 if (!drm_dp_dpcd_write(&intel_dp->aux,
3848 DP_TEST_EDID_CHECKSUM,
3849 &block->checksum,
3850 1))
3851 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3852
3853 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3854 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3855 }
3856
3857 /* Set test active flag here so userspace doesn't interrupt things */
3858 intel_dp->compliance_test_active = 1;
3859
3860 return test_result;
3861}
3862
3863static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
3864{
3865 uint8_t test_result = DP_TEST_NAK;
3866 return test_result;
3867}
3868
3869static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3870{
3871 uint8_t response = DP_TEST_NAK;
3872 uint8_t rxdata = 0;
3873 int status = 0;
3874
3875 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3876 if (status <= 0) {
3877 DRM_DEBUG_KMS("Could not read test request from sink\n");
3878 goto update_status;
3879 }
3880
3881 switch (rxdata) {
3882 case DP_TEST_LINK_TRAINING:
3883 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3884 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3885 response = intel_dp_autotest_link_training(intel_dp);
3886 break;
3887 case DP_TEST_LINK_VIDEO_PATTERN:
3888 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3889 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3890 response = intel_dp_autotest_video_pattern(intel_dp);
3891 break;
3892 case DP_TEST_LINK_EDID_READ:
3893 DRM_DEBUG_KMS("EDID test requested\n");
3894 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3895 response = intel_dp_autotest_edid(intel_dp);
3896 break;
3897 case DP_TEST_LINK_PHY_TEST_PATTERN:
3898 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3899 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3900 response = intel_dp_autotest_phy_pattern(intel_dp);
3901 break;
3902 default:
3903 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3904 break;
3905 }
3906
3907update_status:
3908 status = drm_dp_dpcd_write(&intel_dp->aux,
3909 DP_TEST_RESPONSE,
3910 &response, 1);
3911 if (status <= 0)
3912 DRM_DEBUG_KMS("Could not write test response to sink\n");
3913}
3914
3915static int
3916intel_dp_check_mst_status(struct intel_dp *intel_dp)
3917{
3918 bool bret;
3919
3920 if (intel_dp->is_mst) {
3921 u8 esi[16] = { 0 };
3922 int ret = 0;
3923 int retry;
3924 bool handled;
3925 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3926go_again:
3927 if (bret == true) {
3928
3929 /* check link status - esi[10] = 0x200c */
3930 if (intel_dp->active_mst_links &&
3931 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3932 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3933 intel_dp_start_link_train(intel_dp);
3934 intel_dp_stop_link_train(intel_dp);
3935 }
3936
3937 DRM_DEBUG_KMS("got esi %3ph\n", esi);
3938 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3939
3940 if (handled) {
3941 for (retry = 0; retry < 3; retry++) {
3942 int wret;
3943 wret = drm_dp_dpcd_write(&intel_dp->aux,
3944 DP_SINK_COUNT_ESI+1,
3945 &esi[1], 3);
3946 if (wret == 3) {
3947 break;
3948 }
3949 }
3950
3951 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3952 if (bret == true) {
3953 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
3954 goto go_again;
3955 }
3956 } else
3957 ret = 0;
3958
3959 return ret;
3960 } else {
3961 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3962 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3963 intel_dp->is_mst = false;
3964 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3965 /* send a hotplug event */
3966 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3967 }
3968 }
3969 return -EINVAL;
3970}
3971
3972static void
3973intel_dp_retrain_link(struct intel_dp *intel_dp)
3974{
3975 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3976 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3977 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
3978
3979 /* Suppress underruns caused by re-training */
3980 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
3981 if (crtc->config->has_pch_encoder)
3982 intel_set_pch_fifo_underrun_reporting(dev_priv,
3983 intel_crtc_pch_transcoder(crtc), false);
3984
3985 intel_dp_start_link_train(intel_dp);
3986 intel_dp_stop_link_train(intel_dp);
3987
3988 /* Keep underrun reporting disabled until things are stable */
3989 intel_wait_for_vblank(dev_priv, crtc->pipe);
3990
3991 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
3992 if (crtc->config->has_pch_encoder)
3993 intel_set_pch_fifo_underrun_reporting(dev_priv,
3994 intel_crtc_pch_transcoder(crtc), true);
3995}
3996
3997static void
3998intel_dp_check_link_status(struct intel_dp *intel_dp)
3999{
4000 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4001 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4002 u8 link_status[DP_LINK_STATUS_SIZE];
4003
4004 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4005
4006 if (!intel_dp_get_link_status(intel_dp, link_status)) {
4007 DRM_ERROR("Failed to get link status\n");
4008 return;
4009 }
4010
4011 if (!intel_encoder->base.crtc)
4012 return;
4013
4014 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4015 return;
4016
4017 /* FIXME: we need to synchronize this sort of stuff with hardware
4018 * readout. Currently fast link training doesn't work on boot-up. */
4019 if (!intel_dp->lane_count)
4020 return;
4021
4022 /* if link training is requested we should perform it always */
4023 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4024 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4025 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4026 intel_encoder->base.name);
4027
4028 intel_dp_retrain_link(intel_dp);
4029 }
4030}
4031
4032/*
4033 * According to DP spec
4034 * 5.1.2:
4035 * 1. Read DPCD
4036 * 2. Configure link according to Receiver Capabilities
4037 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4038 * 4. Check link status on receipt of hot-plug interrupt
4039 *
4040 * intel_dp_short_pulse - handles short pulse interrupts
4041 * when full detection is not required.
4042 * Returns %true if short pulse is handled and full detection
4043 * is NOT required and %false otherwise.
4044 */
4045static bool
4046intel_dp_short_pulse(struct intel_dp *intel_dp)
4047{
4048 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4049 u8 sink_irq_vector = 0;
4050 u8 old_sink_count = intel_dp->sink_count;
4051 bool ret;
4052
4053 /*
4054 * Clearing compliance test variables to allow capturing
4055 * of values for next automated test request.
4056 */
4057 intel_dp->compliance_test_active = 0;
4058 intel_dp->compliance_test_type = 0;
4059 intel_dp->compliance_test_data = 0;
4060
4061 /*
4062 * Now read the DPCD to see if it's actually running
4063 * If the current value of sink count doesn't match with
4064 * the value that was stored earlier or dpcd read failed
4065 * we need to do full detection
4066 */
4067 ret = intel_dp_get_dpcd(intel_dp);
4068
4069 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4070 /* No need to proceed if we are going to do full detect */
4071 return false;
4072 }
4073
4074 /* Try to read the source of the interrupt */
4075 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4076 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4077 sink_irq_vector != 0) {
4078 /* Clear interrupt source */
4079 drm_dp_dpcd_writeb(&intel_dp->aux,
4080 DP_DEVICE_SERVICE_IRQ_VECTOR,
4081 sink_irq_vector);
4082
4083 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4084 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4085 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4086 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4087 }
4088
4089 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4090 intel_dp_check_link_status(intel_dp);
4091 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4092
4093 return true;
4094}
4095
4096/* XXX this is probably wrong for multiple downstream ports */
4097static enum drm_connector_status
4098intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4099{
4100 uint8_t *dpcd = intel_dp->dpcd;
4101 uint8_t type;
4102
4103 if (!intel_dp_get_dpcd(intel_dp))
4104 return connector_status_disconnected;
4105
4106 if (is_edp(intel_dp))
4107 return connector_status_connected;
4108
4109 /* if there's no downstream port, we're done */
4110 if (!drm_dp_is_branch(dpcd))
4111 return connector_status_connected;
4112
4113 /* If we're HPD-aware, SINK_COUNT changes dynamically */
4114 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4115 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4116
4117 return intel_dp->sink_count ?
4118 connector_status_connected : connector_status_disconnected;
4119 }
4120
4121 if (intel_dp_can_mst(intel_dp))
4122 return connector_status_connected;
4123
4124 /* If no HPD, poke DDC gently */
4125 if (drm_probe_ddc(&intel_dp->aux.ddc))
4126 return connector_status_connected;
4127
4128 /* Well we tried, say unknown for unreliable port types */
4129 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4130 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4131 if (type == DP_DS_PORT_TYPE_VGA ||
4132 type == DP_DS_PORT_TYPE_NON_EDID)
4133 return connector_status_unknown;
4134 } else {
4135 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4136 DP_DWN_STRM_PORT_TYPE_MASK;
4137 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4138 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4139 return connector_status_unknown;
4140 }
4141
4142 /* Anything else is out of spec, warn and ignore */
4143 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4144 return connector_status_disconnected;
4145}
4146
4147static enum drm_connector_status
4148edp_detect(struct intel_dp *intel_dp)
4149{
4150 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4151 enum drm_connector_status status;
4152
4153 status = intel_panel_detect(dev);
4154 if (status == connector_status_unknown)
4155 status = connector_status_connected;
4156
4157 return status;
4158}
4159
4160static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4161 struct intel_digital_port *port)
4162{
4163 u32 bit;
4164
4165 switch (port->port) {
4166 case PORT_A:
4167 return true;
4168 case PORT_B:
4169 bit = SDE_PORTB_HOTPLUG;
4170 break;
4171 case PORT_C:
4172 bit = SDE_PORTC_HOTPLUG;
4173 break;
4174 case PORT_D:
4175 bit = SDE_PORTD_HOTPLUG;
4176 break;
4177 default:
4178 MISSING_CASE(port->port);
4179 return false;
4180 }
4181
4182 return I915_READ(SDEISR) & bit;
4183}
4184
4185static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4186 struct intel_digital_port *port)
4187{
4188 u32 bit;
4189
4190 switch (port->port) {
4191 case PORT_A:
4192 return true;
4193 case PORT_B:
4194 bit = SDE_PORTB_HOTPLUG_CPT;
4195 break;
4196 case PORT_C:
4197 bit = SDE_PORTC_HOTPLUG_CPT;
4198 break;
4199 case PORT_D:
4200 bit = SDE_PORTD_HOTPLUG_CPT;
4201 break;
4202 case PORT_E:
4203 bit = SDE_PORTE_HOTPLUG_SPT;
4204 break;
4205 default:
4206 MISSING_CASE(port->port);
4207 return false;
4208 }
4209
4210 return I915_READ(SDEISR) & bit;
4211}
4212
4213static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4214 struct intel_digital_port *port)
4215{
4216 u32 bit;
4217
4218 switch (port->port) {
4219 case PORT_B:
4220 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4221 break;
4222 case PORT_C:
4223 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4224 break;
4225 case PORT_D:
4226 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4227 break;
4228 default:
4229 MISSING_CASE(port->port);
4230 return false;
4231 }
4232
4233 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4234}
4235
4236static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4237 struct intel_digital_port *port)
4238{
4239 u32 bit;
4240
4241 switch (port->port) {
4242 case PORT_B:
4243 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4244 break;
4245 case PORT_C:
4246 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4247 break;
4248 case PORT_D:
4249 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4250 break;
4251 default:
4252 MISSING_CASE(port->port);
4253 return false;
4254 }
4255
4256 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4257}
4258
4259static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4260 struct intel_digital_port *intel_dig_port)
4261{
4262 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4263 enum port port;
4264 u32 bit;
4265
4266 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4267 switch (port) {
4268 case PORT_A:
4269 bit = BXT_DE_PORT_HP_DDIA;
4270 break;
4271 case PORT_B:
4272 bit = BXT_DE_PORT_HP_DDIB;
4273 break;
4274 case PORT_C:
4275 bit = BXT_DE_PORT_HP_DDIC;
4276 break;
4277 default:
4278 MISSING_CASE(port);
4279 return false;
4280 }
4281
4282 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4283}
4284
4285/*
4286 * intel_digital_port_connected - is the specified port connected?
4287 * @dev_priv: i915 private structure
4288 * @port: the port to test
4289 *
4290 * Return %true if @port is connected, %false otherwise.
4291 */
4292bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4293 struct intel_digital_port *port)
4294{
4295 if (HAS_PCH_IBX(dev_priv))
4296 return ibx_digital_port_connected(dev_priv, port);
4297 else if (HAS_PCH_SPLIT(dev_priv))
4298 return cpt_digital_port_connected(dev_priv, port);
4299 else if (IS_BROXTON(dev_priv))
4300 return bxt_digital_port_connected(dev_priv, port);
4301 else if (IS_GM45(dev_priv))
4302 return gm45_digital_port_connected(dev_priv, port);
4303 else
4304 return g4x_digital_port_connected(dev_priv, port);
4305}
4306
4307static struct edid *
4308intel_dp_get_edid(struct intel_dp *intel_dp)
4309{
4310 struct intel_connector *intel_connector = intel_dp->attached_connector;
4311
4312 /* use cached edid if we have one */
4313 if (intel_connector->edid) {
4314 /* invalid edid */
4315 if (IS_ERR(intel_connector->edid))
4316 return NULL;
4317
4318 return drm_edid_duplicate(intel_connector->edid);
4319 } else
4320 return drm_get_edid(&intel_connector->base,
4321 &intel_dp->aux.ddc);
4322}
4323
4324static void
4325intel_dp_set_edid(struct intel_dp *intel_dp)
4326{
4327 struct intel_connector *intel_connector = intel_dp->attached_connector;
4328 struct edid *edid;
4329
4330 intel_dp_unset_edid(intel_dp);
4331 edid = intel_dp_get_edid(intel_dp);
4332 intel_connector->detect_edid = edid;
4333
4334 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4335 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4336 else
4337 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4338}
4339
4340static void
4341intel_dp_unset_edid(struct intel_dp *intel_dp)
4342{
4343 struct intel_connector *intel_connector = intel_dp->attached_connector;
4344
4345 kfree(intel_connector->detect_edid);
4346 intel_connector->detect_edid = NULL;
4347
4348 intel_dp->has_audio = false;
4349}
4350
4351static enum drm_connector_status
4352intel_dp_long_pulse(struct intel_connector *intel_connector)
4353{
4354 struct drm_connector *connector = &intel_connector->base;
4355 struct intel_dp *intel_dp = intel_attached_dp(connector);
4356 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4357 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4358 struct drm_device *dev = connector->dev;
4359 enum drm_connector_status status;
4360 enum intel_display_power_domain power_domain;
4361 u8 sink_irq_vector = 0;
4362
4363 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4364 intel_display_power_get(to_i915(dev), power_domain);
4365
4366 /* Can't disconnect eDP, but you can close the lid... */
4367 if (is_edp(intel_dp))
4368 status = edp_detect(intel_dp);
4369 else if (intel_digital_port_connected(to_i915(dev),
4370 dp_to_dig_port(intel_dp)))
4371 status = intel_dp_detect_dpcd(intel_dp);
4372 else
4373 status = connector_status_disconnected;
4374
4375 if (status == connector_status_disconnected) {
4376 intel_dp->compliance_test_active = 0;
4377 intel_dp->compliance_test_type = 0;
4378 intel_dp->compliance_test_data = 0;
4379
4380 if (intel_dp->is_mst) {
4381 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4382 intel_dp->is_mst,
4383 intel_dp->mst_mgr.mst_state);
4384 intel_dp->is_mst = false;
4385 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4386 intel_dp->is_mst);
4387 }
4388
4389 goto out;
4390 }
4391
4392 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4393 intel_encoder->type = INTEL_OUTPUT_DP;
4394
4395 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4396 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4397 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4398
4399 intel_dp_print_rates(intel_dp);
4400
4401 intel_dp_read_desc(intel_dp);
4402
4403 intel_dp_configure_mst(intel_dp);
4404
4405 if (intel_dp->is_mst) {
4406 /*
4407 * If we are in MST mode then this connector
4408 * won't appear connected or have anything
4409 * with EDID on it
4410 */
4411 status = connector_status_disconnected;
4412 goto out;
4413 } else if (connector->status == connector_status_connected) {
4414 /*
4415 * If display was connected already and is still connected
4416 * check links status, there has been known issues of
4417 * link loss triggerring long pulse!!!!
4418 */
4419 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4420 intel_dp_check_link_status(intel_dp);
4421 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4422 goto out;
4423 }
4424
4425 /*
4426 * Clearing NACK and defer counts to get their exact values
4427 * while reading EDID which are required by Compliance tests
4428 * 4.2.2.4 and 4.2.2.5
4429 */
4430 intel_dp->aux.i2c_nack_count = 0;
4431 intel_dp->aux.i2c_defer_count = 0;
4432
4433 intel_dp_set_edid(intel_dp);
4434 if (is_edp(intel_dp) || intel_connector->detect_edid)
4435 status = connector_status_connected;
4436 intel_dp->detect_done = true;
4437
4438 /* Try to read the source of the interrupt */
4439 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4440 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4441 sink_irq_vector != 0) {
4442 /* Clear interrupt source */
4443 drm_dp_dpcd_writeb(&intel_dp->aux,
4444 DP_DEVICE_SERVICE_IRQ_VECTOR,
4445 sink_irq_vector);
4446
4447 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4448 intel_dp_handle_test_request(intel_dp);
4449 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4450 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4451 }
4452
4453out:
4454 if (status != connector_status_connected && !intel_dp->is_mst)
4455 intel_dp_unset_edid(intel_dp);
4456
4457 intel_display_power_put(to_i915(dev), power_domain);
4458 return status;
4459}
4460
4461static enum drm_connector_status
4462intel_dp_detect(struct drm_connector *connector, bool force)
4463{
4464 struct intel_dp *intel_dp = intel_attached_dp(connector);
4465 enum drm_connector_status status = connector->status;
4466
4467 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4468 connector->base.id, connector->name);
4469
4470 /* If full detect is not performed yet, do a full detect */
4471 if (!intel_dp->detect_done)
4472 status = intel_dp_long_pulse(intel_dp->attached_connector);
4473
4474 intel_dp->detect_done = false;
4475
4476 return status;
4477}
4478
4479static void
4480intel_dp_force(struct drm_connector *connector)
4481{
4482 struct intel_dp *intel_dp = intel_attached_dp(connector);
4483 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4484 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4485 enum intel_display_power_domain power_domain;
4486
4487 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4488 connector->base.id, connector->name);
4489 intel_dp_unset_edid(intel_dp);
4490
4491 if (connector->status != connector_status_connected)
4492 return;
4493
4494 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4495 intel_display_power_get(dev_priv, power_domain);
4496
4497 intel_dp_set_edid(intel_dp);
4498
4499 intel_display_power_put(dev_priv, power_domain);
4500
4501 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4502 intel_encoder->type = INTEL_OUTPUT_DP;
4503}
4504
4505static int intel_dp_get_modes(struct drm_connector *connector)
4506{
4507 struct intel_connector *intel_connector = to_intel_connector(connector);
4508 struct edid *edid;
4509
4510 edid = intel_connector->detect_edid;
4511 if (edid) {
4512 int ret = intel_connector_update_modes(connector, edid);
4513 if (ret)
4514 return ret;
4515 }
4516
4517 /* if eDP has no EDID, fall back to fixed mode */
4518 if (is_edp(intel_attached_dp(connector)) &&
4519 intel_connector->panel.fixed_mode) {
4520 struct drm_display_mode *mode;
4521
4522 mode = drm_mode_duplicate(connector->dev,
4523 intel_connector->panel.fixed_mode);
4524 if (mode) {
4525 drm_mode_probed_add(connector, mode);
4526 return 1;
4527 }
4528 }
4529
4530 return 0;
4531}
4532
4533static bool
4534intel_dp_detect_audio(struct drm_connector *connector)
4535{
4536 bool has_audio = false;
4537 struct edid *edid;
4538
4539 edid = to_intel_connector(connector)->detect_edid;
4540 if (edid)
4541 has_audio = drm_detect_monitor_audio(edid);
4542
4543 return has_audio;
4544}
4545
4546static int
4547intel_dp_set_property(struct drm_connector *connector,
4548 struct drm_property *property,
4549 uint64_t val)
4550{
4551 struct drm_i915_private *dev_priv = to_i915(connector->dev);
4552 struct intel_connector *intel_connector = to_intel_connector(connector);
4553 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4554 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4555 int ret;
4556
4557 ret = drm_object_property_set_value(&connector->base, property, val);
4558 if (ret)
4559 return ret;
4560
4561 if (property == dev_priv->force_audio_property) {
4562 int i = val;
4563 bool has_audio;
4564
4565 if (i == intel_dp->force_audio)
4566 return 0;
4567
4568 intel_dp->force_audio = i;
4569
4570 if (i == HDMI_AUDIO_AUTO)
4571 has_audio = intel_dp_detect_audio(connector);
4572 else
4573 has_audio = (i == HDMI_AUDIO_ON);
4574
4575 if (has_audio == intel_dp->has_audio)
4576 return 0;
4577
4578 intel_dp->has_audio = has_audio;
4579 goto done;
4580 }
4581
4582 if (property == dev_priv->broadcast_rgb_property) {
4583 bool old_auto = intel_dp->color_range_auto;
4584 bool old_range = intel_dp->limited_color_range;
4585
4586 switch (val) {
4587 case INTEL_BROADCAST_RGB_AUTO:
4588 intel_dp->color_range_auto = true;
4589 break;
4590 case INTEL_BROADCAST_RGB_FULL:
4591 intel_dp->color_range_auto = false;
4592 intel_dp->limited_color_range = false;
4593 break;
4594 case INTEL_BROADCAST_RGB_LIMITED:
4595 intel_dp->color_range_auto = false;
4596 intel_dp->limited_color_range = true;
4597 break;
4598 default:
4599 return -EINVAL;
4600 }
4601
4602 if (old_auto == intel_dp->color_range_auto &&
4603 old_range == intel_dp->limited_color_range)
4604 return 0;
4605
4606 goto done;
4607 }
4608
4609 if (is_edp(intel_dp) &&
4610 property == connector->dev->mode_config.scaling_mode_property) {
4611 if (val == DRM_MODE_SCALE_NONE) {
4612 DRM_DEBUG_KMS("no scaling not supported\n");
4613 return -EINVAL;
4614 }
4615 if (HAS_GMCH_DISPLAY(dev_priv) &&
4616 val == DRM_MODE_SCALE_CENTER) {
4617 DRM_DEBUG_KMS("centering not supported\n");
4618 return -EINVAL;
4619 }
4620
4621 if (intel_connector->panel.fitting_mode == val) {
4622 /* the eDP scaling property is not changed */
4623 return 0;
4624 }
4625 intel_connector->panel.fitting_mode = val;
4626
4627 goto done;
4628 }
4629
4630 return -EINVAL;
4631
4632done:
4633 if (intel_encoder->base.crtc)
4634 intel_crtc_restore_mode(intel_encoder->base.crtc);
4635
4636 return 0;
4637}
4638
4639static int
4640intel_dp_connector_register(struct drm_connector *connector)
4641{
4642 struct intel_dp *intel_dp = intel_attached_dp(connector);
4643 int ret;
4644
4645 ret = intel_connector_register(connector);
4646 if (ret)
4647 return ret;
4648
4649 i915_debugfs_connector_add(connector);
4650
4651 DRM_DEBUG_KMS("registering %s bus for %s\n",
4652 intel_dp->aux.name, connector->kdev->kobj.name);
4653
4654 intel_dp->aux.dev = connector->kdev;
4655 return drm_dp_aux_register(&intel_dp->aux);
4656}
4657
4658static void
4659intel_dp_connector_unregister(struct drm_connector *connector)
4660{
4661 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4662 intel_connector_unregister(connector);
4663}
4664
4665static void
4666intel_dp_connector_destroy(struct drm_connector *connector)
4667{
4668 struct intel_connector *intel_connector = to_intel_connector(connector);
4669
4670 kfree(intel_connector->detect_edid);
4671
4672 if (!IS_ERR_OR_NULL(intel_connector->edid))
4673 kfree(intel_connector->edid);
4674
4675 /* Can't call is_edp() since the encoder may have been destroyed
4676 * already. */
4677 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4678 intel_panel_fini(&intel_connector->panel);
4679
4680 drm_connector_cleanup(connector);
4681 kfree(connector);
4682}
4683
4684void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4685{
4686 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4687 struct intel_dp *intel_dp = &intel_dig_port->dp;
4688
4689 intel_dp_mst_encoder_cleanup(intel_dig_port);
4690 if (is_edp(intel_dp)) {
4691 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4692 /*
4693 * vdd might still be enabled do to the delayed vdd off.
4694 * Make sure vdd is actually turned off here.
4695 */
4696 pps_lock(intel_dp);
4697 edp_panel_vdd_off_sync(intel_dp);
4698 pps_unlock(intel_dp);
4699
4700 if (intel_dp->edp_notifier.notifier_call) {
4701 unregister_reboot_notifier(&intel_dp->edp_notifier);
4702 intel_dp->edp_notifier.notifier_call = NULL;
4703 }
4704 }
4705
4706 intel_dp_aux_fini(intel_dp);
4707
4708 drm_encoder_cleanup(encoder);
4709 kfree(intel_dig_port);
4710}
4711
4712void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4713{
4714 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4715
4716 if (!is_edp(intel_dp))
4717 return;
4718
4719 /*
4720 * vdd might still be enabled do to the delayed vdd off.
4721 * Make sure vdd is actually turned off here.
4722 */
4723 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4724 pps_lock(intel_dp);
4725 edp_panel_vdd_off_sync(intel_dp);
4726 pps_unlock(intel_dp);
4727}
4728
4729static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4730{
4731 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4732 struct drm_device *dev = intel_dig_port->base.base.dev;
4733 struct drm_i915_private *dev_priv = to_i915(dev);
4734 enum intel_display_power_domain power_domain;
4735
4736 lockdep_assert_held(&dev_priv->pps_mutex);
4737
4738 if (!edp_have_panel_vdd(intel_dp))
4739 return;
4740
4741 /*
4742 * The VDD bit needs a power domain reference, so if the bit is
4743 * already enabled when we boot or resume, grab this reference and
4744 * schedule a vdd off, so we don't hold on to the reference
4745 * indefinitely.
4746 */
4747 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4748 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4749 intel_display_power_get(dev_priv, power_domain);
4750
4751 edp_panel_vdd_schedule_off(intel_dp);
4752}
4753
4754void intel_dp_encoder_reset(struct drm_encoder *encoder)
4755{
4756 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4757 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4758 struct intel_lspcon *lspcon = &intel_dig_port->lspcon;
4759 struct intel_dp *intel_dp = &intel_dig_port->dp;
4760
4761 if (!HAS_DDI(dev_priv))
4762 intel_dp->DP = I915_READ(intel_dp->output_reg);
4763
4764 if (IS_GEN9(dev_priv) && lspcon->active)
4765 lspcon_resume(lspcon);
4766
4767 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4768 return;
4769
4770 pps_lock(intel_dp);
4771
4772 /* Reinit the power sequencer, in case BIOS did something with it. */
4773 intel_dp_pps_init(encoder->dev, intel_dp);
4774 intel_edp_panel_vdd_sanitize(intel_dp);
4775
4776 pps_unlock(intel_dp);
4777}
4778
4779static const struct drm_connector_funcs intel_dp_connector_funcs = {
4780 .dpms = drm_atomic_helper_connector_dpms,
4781 .detect = intel_dp_detect,
4782 .force = intel_dp_force,
4783 .fill_modes = drm_helper_probe_single_connector_modes,
4784 .set_property = intel_dp_set_property,
4785 .atomic_get_property = intel_connector_atomic_get_property,
4786 .late_register = intel_dp_connector_register,
4787 .early_unregister = intel_dp_connector_unregister,
4788 .destroy = intel_dp_connector_destroy,
4789 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4790 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4791};
4792
4793static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4794 .get_modes = intel_dp_get_modes,
4795 .mode_valid = intel_dp_mode_valid,
4796};
4797
4798static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4799 .reset = intel_dp_encoder_reset,
4800 .destroy = intel_dp_encoder_destroy,
4801};
4802
4803enum irqreturn
4804intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4805{
4806 struct intel_dp *intel_dp = &intel_dig_port->dp;
4807 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4808 struct drm_device *dev = intel_dig_port->base.base.dev;
4809 struct drm_i915_private *dev_priv = to_i915(dev);
4810 enum intel_display_power_domain power_domain;
4811 enum irqreturn ret = IRQ_NONE;
4812
4813 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4814 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4815 intel_dig_port->base.type = INTEL_OUTPUT_DP;
4816
4817 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4818 /*
4819 * vdd off can generate a long pulse on eDP which
4820 * would require vdd on to handle it, and thus we
4821 * would end up in an endless cycle of
4822 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4823 */
4824 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4825 port_name(intel_dig_port->port));
4826 return IRQ_HANDLED;
4827 }
4828
4829 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4830 port_name(intel_dig_port->port),
4831 long_hpd ? "long" : "short");
4832
4833 if (long_hpd) {
4834 intel_dp->detect_done = false;
4835 return IRQ_NONE;
4836 }
4837
4838 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4839 intel_display_power_get(dev_priv, power_domain);
4840
4841 if (intel_dp->is_mst) {
4842 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4843 /*
4844 * If we were in MST mode, and device is not
4845 * there, get out of MST mode
4846 */
4847 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4848 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4849 intel_dp->is_mst = false;
4850 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4851 intel_dp->is_mst);
4852 intel_dp->detect_done = false;
4853 goto put_power;
4854 }
4855 }
4856
4857 if (!intel_dp->is_mst) {
4858 if (!intel_dp_short_pulse(intel_dp)) {
4859 intel_dp->detect_done = false;
4860 goto put_power;
4861 }
4862 }
4863
4864 ret = IRQ_HANDLED;
4865
4866put_power:
4867 intel_display_power_put(dev_priv, power_domain);
4868
4869 return ret;
4870}
4871
4872/* check the VBT to see whether the eDP is on another port */
4873bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
4874{
4875 /*
4876 * eDP not supported on g4x. so bail out early just
4877 * for a bit extra safety in case the VBT is bonkers.
4878 */
4879 if (INTEL_GEN(dev_priv) < 5)
4880 return false;
4881
4882 if (port == PORT_A)
4883 return true;
4884
4885 return intel_bios_is_port_edp(dev_priv, port);
4886}
4887
4888void
4889intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4890{
4891 struct intel_connector *intel_connector = to_intel_connector(connector);
4892
4893 intel_attach_force_audio_property(connector);
4894 intel_attach_broadcast_rgb_property(connector);
4895 intel_dp->color_range_auto = true;
4896
4897 if (is_edp(intel_dp)) {
4898 drm_mode_create_scaling_mode_property(connector->dev);
4899 drm_object_attach_property(
4900 &connector->base,
4901 connector->dev->mode_config.scaling_mode_property,
4902 DRM_MODE_SCALE_ASPECT);
4903 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4904 }
4905}
4906
4907static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4908{
4909 intel_dp->panel_power_off_time = ktime_get_boottime();
4910 intel_dp->last_power_on = jiffies;
4911 intel_dp->last_backlight_off = jiffies;
4912}
4913
4914static void
4915intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4916 struct intel_dp *intel_dp, struct edp_power_seq *seq)
4917{
4918 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
4919 struct pps_registers regs;
4920
4921 intel_pps_get_registers(dev_priv, intel_dp, ®s);
4922
4923 /* Workaround: Need to write PP_CONTROL with the unlock key as
4924 * the very first thing. */
4925 pp_ctl = ironlake_get_pp_control(intel_dp);
4926
4927 pp_on = I915_READ(regs.pp_on);
4928 pp_off = I915_READ(regs.pp_off);
4929 if (!IS_BROXTON(dev_priv)) {
4930 I915_WRITE(regs.pp_ctrl, pp_ctl);
4931 pp_div = I915_READ(regs.pp_div);
4932 }
4933
4934 /* Pull timing values out of registers */
4935 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4936 PANEL_POWER_UP_DELAY_SHIFT;
4937
4938 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4939 PANEL_LIGHT_ON_DELAY_SHIFT;
4940
4941 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4942 PANEL_LIGHT_OFF_DELAY_SHIFT;
4943
4944 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4945 PANEL_POWER_DOWN_DELAY_SHIFT;
4946
4947 if (IS_BROXTON(dev_priv)) {
4948 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4949 BXT_POWER_CYCLE_DELAY_SHIFT;
4950 if (tmp > 0)
4951 seq->t11_t12 = (tmp - 1) * 1000;
4952 else
4953 seq->t11_t12 = 0;
4954 } else {
4955 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4956 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4957 }
4958}
4959
4960static void
4961intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4962{
4963 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4964 state_name,
4965 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4966}
4967
4968static void
4969intel_pps_verify_state(struct drm_i915_private *dev_priv,
4970 struct intel_dp *intel_dp)
4971{
4972 struct edp_power_seq hw;
4973 struct edp_power_seq *sw = &intel_dp->pps_delays;
4974
4975 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4976
4977 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4978 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4979 DRM_ERROR("PPS state mismatch\n");
4980 intel_pps_dump_state("sw", sw);
4981 intel_pps_dump_state("hw", &hw);
4982 }
4983}
4984
4985static void
4986intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4987 struct intel_dp *intel_dp)
4988{
4989 struct drm_i915_private *dev_priv = to_i915(dev);
4990 struct edp_power_seq cur, vbt, spec,
4991 *final = &intel_dp->pps_delays;
4992
4993 lockdep_assert_held(&dev_priv->pps_mutex);
4994
4995 /* already initialized? */
4996 if (final->t11_t12 != 0)
4997 return;
4998
4999 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5000
5001 intel_pps_dump_state("cur", &cur);
5002
5003 vbt = dev_priv->vbt.edp.pps;
5004
5005 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5006 * our hw here, which are all in 100usec. */
5007 spec.t1_t3 = 210 * 10;
5008 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5009 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5010 spec.t10 = 500 * 10;
5011 /* This one is special and actually in units of 100ms, but zero
5012 * based in the hw (so we need to add 100 ms). But the sw vbt
5013 * table multiplies it with 1000 to make it in units of 100usec,
5014 * too. */
5015 spec.t11_t12 = (510 + 100) * 10;
5016
5017 intel_pps_dump_state("vbt", &vbt);
5018
5019 /* Use the max of the register settings and vbt. If both are
5020 * unset, fall back to the spec limits. */
5021#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
5022 spec.field : \
5023 max(cur.field, vbt.field))
5024 assign_final(t1_t3);
5025 assign_final(t8);
5026 assign_final(t9);
5027 assign_final(t10);
5028 assign_final(t11_t12);
5029#undef assign_final
5030
5031#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
5032 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5033 intel_dp->backlight_on_delay = get_delay(t8);
5034 intel_dp->backlight_off_delay = get_delay(t9);
5035 intel_dp->panel_power_down_delay = get_delay(t10);
5036 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5037#undef get_delay
5038
5039 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5040 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5041 intel_dp->panel_power_cycle_delay);
5042
5043 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5044 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5045
5046 /*
5047 * We override the HW backlight delays to 1 because we do manual waits
5048 * on them. For T8, even BSpec recommends doing it. For T9, if we
5049 * don't do this, we'll end up waiting for the backlight off delay
5050 * twice: once when we do the manual sleep, and once when we disable
5051 * the panel and wait for the PP_STATUS bit to become zero.
5052 */
5053 final->t8 = 1;
5054 final->t9 = 1;
5055}
5056
5057static void
5058intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5059 struct intel_dp *intel_dp,
5060 bool force_disable_vdd)
5061{
5062 struct drm_i915_private *dev_priv = to_i915(dev);
5063 u32 pp_on, pp_off, pp_div, port_sel = 0;
5064 int div = dev_priv->rawclk_freq / 1000;
5065 struct pps_registers regs;
5066 enum port port = dp_to_dig_port(intel_dp)->port;
5067 const struct edp_power_seq *seq = &intel_dp->pps_delays;
5068
5069 lockdep_assert_held(&dev_priv->pps_mutex);
5070
5071 intel_pps_get_registers(dev_priv, intel_dp, ®s);
5072
5073 /*
5074 * On some VLV machines the BIOS can leave the VDD
5075 * enabled even on power seqeuencers which aren't
5076 * hooked up to any port. This would mess up the
5077 * power domain tracking the first time we pick
5078 * one of these power sequencers for use since
5079 * edp_panel_vdd_on() would notice that the VDD was
5080 * already on and therefore wouldn't grab the power
5081 * domain reference. Disable VDD first to avoid this.
5082 * This also avoids spuriously turning the VDD on as
5083 * soon as the new power seqeuencer gets initialized.
5084 */
5085 if (force_disable_vdd) {
5086 u32 pp = ironlake_get_pp_control(intel_dp);
5087
5088 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5089
5090 if (pp & EDP_FORCE_VDD)
5091 DRM_DEBUG_KMS("VDD already on, disabling first\n");
5092
5093 pp &= ~EDP_FORCE_VDD;
5094
5095 I915_WRITE(regs.pp_ctrl, pp);
5096 }
5097
5098 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5099 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5100 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5101 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5102 /* Compute the divisor for the pp clock, simply match the Bspec
5103 * formula. */
5104 if (IS_BROXTON(dev_priv)) {
5105 pp_div = I915_READ(regs.pp_ctrl);
5106 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5107 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5108 << BXT_POWER_CYCLE_DELAY_SHIFT);
5109 } else {
5110 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5111 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5112 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5113 }
5114
5115 /* Haswell doesn't have any port selection bits for the panel
5116 * power sequencer any more. */
5117 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5118 port_sel = PANEL_PORT_SELECT_VLV(port);
5119 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5120 if (port == PORT_A)
5121 port_sel = PANEL_PORT_SELECT_DPA;
5122 else
5123 port_sel = PANEL_PORT_SELECT_DPD;
5124 }
5125
5126 pp_on |= port_sel;
5127
5128 I915_WRITE(regs.pp_on, pp_on);
5129 I915_WRITE(regs.pp_off, pp_off);
5130 if (IS_BROXTON(dev_priv))
5131 I915_WRITE(regs.pp_ctrl, pp_div);
5132 else
5133 I915_WRITE(regs.pp_div, pp_div);
5134
5135 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5136 I915_READ(regs.pp_on),
5137 I915_READ(regs.pp_off),
5138 IS_BROXTON(dev_priv) ?
5139 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5140 I915_READ(regs.pp_div));
5141}
5142
5143static void intel_dp_pps_init(struct drm_device *dev,
5144 struct intel_dp *intel_dp)
5145{
5146 struct drm_i915_private *dev_priv = to_i915(dev);
5147
5148 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5149 vlv_initial_power_sequencer_setup(intel_dp);
5150 } else {
5151 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5152 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5153 }
5154}
5155
5156/**
5157 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5158 * @dev_priv: i915 device
5159 * @crtc_state: a pointer to the active intel_crtc_state
5160 * @refresh_rate: RR to be programmed
5161 *
5162 * This function gets called when refresh rate (RR) has to be changed from
5163 * one frequency to another. Switches can be between high and low RR
5164 * supported by the panel or to any other RR based on media playback (in
5165 * this case, RR value needs to be passed from user space).
5166 *
5167 * The caller of this function needs to take a lock on dev_priv->drrs.
5168 */
5169static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5170 struct intel_crtc_state *crtc_state,
5171 int refresh_rate)
5172{
5173 struct intel_encoder *encoder;
5174 struct intel_digital_port *dig_port = NULL;
5175 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5177 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5178
5179 if (refresh_rate <= 0) {
5180 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5181 return;
5182 }
5183
5184 if (intel_dp == NULL) {
5185 DRM_DEBUG_KMS("DRRS not supported.\n");
5186 return;
5187 }
5188
5189 /*
5190 * FIXME: This needs proper synchronization with psr state for some
5191 * platforms that cannot have PSR and DRRS enabled at the same time.
5192 */
5193
5194 dig_port = dp_to_dig_port(intel_dp);
5195 encoder = &dig_port->base;
5196 intel_crtc = to_intel_crtc(encoder->base.crtc);
5197
5198 if (!intel_crtc) {
5199 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5200 return;
5201 }
5202
5203 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5204 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5205 return;
5206 }
5207
5208 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5209 refresh_rate)
5210 index = DRRS_LOW_RR;
5211
5212 if (index == dev_priv->drrs.refresh_rate_type) {
5213 DRM_DEBUG_KMS(
5214 "DRRS requested for previously set RR...ignoring\n");
5215 return;
5216 }
5217
5218 if (!crtc_state->base.active) {
5219 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5220 return;
5221 }
5222
5223 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5224 switch (index) {
5225 case DRRS_HIGH_RR:
5226 intel_dp_set_m_n(intel_crtc, M1_N1);
5227 break;
5228 case DRRS_LOW_RR:
5229 intel_dp_set_m_n(intel_crtc, M2_N2);
5230 break;
5231 case DRRS_MAX_RR:
5232 default:
5233 DRM_ERROR("Unsupported refreshrate type\n");
5234 }
5235 } else if (INTEL_GEN(dev_priv) > 6) {
5236 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5237 u32 val;
5238
5239 val = I915_READ(reg);
5240 if (index > DRRS_HIGH_RR) {
5241 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5242 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5243 else
5244 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5245 } else {
5246 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5247 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5248 else
5249 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5250 }
5251 I915_WRITE(reg, val);
5252 }
5253
5254 dev_priv->drrs.refresh_rate_type = index;
5255
5256 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5257}
5258
5259/**
5260 * intel_edp_drrs_enable - init drrs struct if supported
5261 * @intel_dp: DP struct
5262 * @crtc_state: A pointer to the active crtc state.
5263 *
5264 * Initializes frontbuffer_bits and drrs.dp
5265 */
5266void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5267 struct intel_crtc_state *crtc_state)
5268{
5269 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5270 struct drm_i915_private *dev_priv = to_i915(dev);
5271
5272 if (!crtc_state->has_drrs) {
5273 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5274 return;
5275 }
5276
5277 mutex_lock(&dev_priv->drrs.mutex);
5278 if (WARN_ON(dev_priv->drrs.dp)) {
5279 DRM_ERROR("DRRS already enabled\n");
5280 goto unlock;
5281 }
5282
5283 dev_priv->drrs.busy_frontbuffer_bits = 0;
5284
5285 dev_priv->drrs.dp = intel_dp;
5286
5287unlock:
5288 mutex_unlock(&dev_priv->drrs.mutex);
5289}
5290
5291/**
5292 * intel_edp_drrs_disable - Disable DRRS
5293 * @intel_dp: DP struct
5294 * @old_crtc_state: Pointer to old crtc_state.
5295 *
5296 */
5297void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5298 struct intel_crtc_state *old_crtc_state)
5299{
5300 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5301 struct drm_i915_private *dev_priv = to_i915(dev);
5302
5303 if (!old_crtc_state->has_drrs)
5304 return;
5305
5306 mutex_lock(&dev_priv->drrs.mutex);
5307 if (!dev_priv->drrs.dp) {
5308 mutex_unlock(&dev_priv->drrs.mutex);
5309 return;
5310 }
5311
5312 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5313 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5314 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5315
5316 dev_priv->drrs.dp = NULL;
5317 mutex_unlock(&dev_priv->drrs.mutex);
5318
5319 cancel_delayed_work_sync(&dev_priv->drrs.work);
5320}
5321
5322static void intel_edp_drrs_downclock_work(struct work_struct *work)
5323{
5324 struct drm_i915_private *dev_priv =
5325 container_of(work, typeof(*dev_priv), drrs.work.work);
5326 struct intel_dp *intel_dp;
5327
5328 mutex_lock(&dev_priv->drrs.mutex);
5329
5330 intel_dp = dev_priv->drrs.dp;
5331
5332 if (!intel_dp)
5333 goto unlock;
5334
5335 /*
5336 * The delayed work can race with an invalidate hence we need to
5337 * recheck.
5338 */
5339
5340 if (dev_priv->drrs.busy_frontbuffer_bits)
5341 goto unlock;
5342
5343 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5344 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5345
5346 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5347 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5348 }
5349
5350unlock:
5351 mutex_unlock(&dev_priv->drrs.mutex);
5352}
5353
5354/**
5355 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5356 * @dev_priv: i915 device
5357 * @frontbuffer_bits: frontbuffer plane tracking bits
5358 *
5359 * This function gets called everytime rendering on the given planes start.
5360 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5361 *
5362 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5363 */
5364void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5365 unsigned int frontbuffer_bits)
5366{
5367 struct drm_crtc *crtc;
5368 enum pipe pipe;
5369
5370 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5371 return;
5372
5373 cancel_delayed_work(&dev_priv->drrs.work);
5374
5375 mutex_lock(&dev_priv->drrs.mutex);
5376 if (!dev_priv->drrs.dp) {
5377 mutex_unlock(&dev_priv->drrs.mutex);
5378 return;
5379 }
5380
5381 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5382 pipe = to_intel_crtc(crtc)->pipe;
5383
5384 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5385 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5386
5387 /* invalidate means busy screen hence upclock */
5388 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5389 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5390 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5391
5392 mutex_unlock(&dev_priv->drrs.mutex);
5393}
5394
5395/**
5396 * intel_edp_drrs_flush - Restart Idleness DRRS
5397 * @dev_priv: i915 device
5398 * @frontbuffer_bits: frontbuffer plane tracking bits
5399 *
5400 * This function gets called every time rendering on the given planes has
5401 * completed or flip on a crtc is completed. So DRRS should be upclocked
5402 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5403 * if no other planes are dirty.
5404 *
5405 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5406 */
5407void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5408 unsigned int frontbuffer_bits)
5409{
5410 struct drm_crtc *crtc;
5411 enum pipe pipe;
5412
5413 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5414 return;
5415
5416 cancel_delayed_work(&dev_priv->drrs.work);
5417
5418 mutex_lock(&dev_priv->drrs.mutex);
5419 if (!dev_priv->drrs.dp) {
5420 mutex_unlock(&dev_priv->drrs.mutex);
5421 return;
5422 }
5423
5424 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5425 pipe = to_intel_crtc(crtc)->pipe;
5426
5427 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5428 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5429
5430 /* flush means busy screen hence upclock */
5431 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5432 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5433 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5434
5435 /*
5436 * flush also means no more activity hence schedule downclock, if all
5437 * other fbs are quiescent too
5438 */
5439 if (!dev_priv->drrs.busy_frontbuffer_bits)
5440 schedule_delayed_work(&dev_priv->drrs.work,
5441 msecs_to_jiffies(1000));
5442 mutex_unlock(&dev_priv->drrs.mutex);
5443}
5444
5445/**
5446 * DOC: Display Refresh Rate Switching (DRRS)
5447 *
5448 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5449 * which enables swtching between low and high refresh rates,
5450 * dynamically, based on the usage scenario. This feature is applicable
5451 * for internal panels.
5452 *
5453 * Indication that the panel supports DRRS is given by the panel EDID, which
5454 * would list multiple refresh rates for one resolution.
5455 *
5456 * DRRS is of 2 types - static and seamless.
5457 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5458 * (may appear as a blink on screen) and is used in dock-undock scenario.
5459 * Seamless DRRS involves changing RR without any visual effect to the user
5460 * and can be used during normal system usage. This is done by programming
5461 * certain registers.
5462 *
5463 * Support for static/seamless DRRS may be indicated in the VBT based on
5464 * inputs from the panel spec.
5465 *
5466 * DRRS saves power by switching to low RR based on usage scenarios.
5467 *
5468 * The implementation is based on frontbuffer tracking implementation. When
5469 * there is a disturbance on the screen triggered by user activity or a periodic
5470 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5471 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5472 * made.
5473 *
5474 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5475 * and intel_edp_drrs_flush() are called.
5476 *
5477 * DRRS can be further extended to support other internal panels and also
5478 * the scenario of video playback wherein RR is set based on the rate
5479 * requested by userspace.
5480 */
5481
5482/**
5483 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5484 * @intel_connector: eDP connector
5485 * @fixed_mode: preferred mode of panel
5486 *
5487 * This function is called only once at driver load to initialize basic
5488 * DRRS stuff.
5489 *
5490 * Returns:
5491 * Downclock mode if panel supports it, else return NULL.
5492 * DRRS support is determined by the presence of downclock mode (apart
5493 * from VBT setting).
5494 */
5495static struct drm_display_mode *
5496intel_dp_drrs_init(struct intel_connector *intel_connector,
5497 struct drm_display_mode *fixed_mode)
5498{
5499 struct drm_connector *connector = &intel_connector->base;
5500 struct drm_device *dev = connector->dev;
5501 struct drm_i915_private *dev_priv = to_i915(dev);
5502 struct drm_display_mode *downclock_mode = NULL;
5503
5504 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5505 mutex_init(&dev_priv->drrs.mutex);
5506
5507 if (INTEL_GEN(dev_priv) <= 6) {
5508 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5509 return NULL;
5510 }
5511
5512 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5513 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5514 return NULL;
5515 }
5516
5517 downclock_mode = intel_find_panel_downclock
5518 (dev, fixed_mode, connector);
5519
5520 if (!downclock_mode) {
5521 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5522 return NULL;
5523 }
5524
5525 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5526
5527 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5528 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5529 return downclock_mode;
5530}
5531
5532static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5533 struct intel_connector *intel_connector)
5534{
5535 struct drm_connector *connector = &intel_connector->base;
5536 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5537 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5538 struct drm_device *dev = intel_encoder->base.dev;
5539 struct drm_i915_private *dev_priv = to_i915(dev);
5540 struct drm_display_mode *fixed_mode = NULL;
5541 struct drm_display_mode *downclock_mode = NULL;
5542 bool has_dpcd;
5543 struct drm_display_mode *scan;
5544 struct edid *edid;
5545 enum pipe pipe = INVALID_PIPE;
5546
5547 if (!is_edp(intel_dp))
5548 return true;
5549
5550 /*
5551 * On IBX/CPT we may get here with LVDS already registered. Since the
5552 * driver uses the only internal power sequencer available for both
5553 * eDP and LVDS bail out early in this case to prevent interfering
5554 * with an already powered-on LVDS power sequencer.
5555 */
5556 if (intel_get_lvds_encoder(dev)) {
5557 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5558 DRM_INFO("LVDS was detected, not registering eDP\n");
5559
5560 return false;
5561 }
5562
5563 pps_lock(intel_dp);
5564
5565 intel_dp_init_panel_power_timestamps(intel_dp);
5566 intel_dp_pps_init(dev, intel_dp);
5567 intel_edp_panel_vdd_sanitize(intel_dp);
5568
5569 pps_unlock(intel_dp);
5570
5571 /* Cache DPCD and EDID for edp. */
5572 has_dpcd = intel_edp_init_dpcd(intel_dp);
5573
5574 if (!has_dpcd) {
5575 /* if this fails, presume the device is a ghost */
5576 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5577 goto out_vdd_off;
5578 }
5579
5580 mutex_lock(&dev->mode_config.mutex);
5581 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5582 if (edid) {
5583 if (drm_add_edid_modes(connector, edid)) {
5584 drm_mode_connector_update_edid_property(connector,
5585 edid);
5586 drm_edid_to_eld(connector, edid);
5587 } else {
5588 kfree(edid);
5589 edid = ERR_PTR(-EINVAL);
5590 }
5591 } else {
5592 edid = ERR_PTR(-ENOENT);
5593 }
5594 intel_connector->edid = edid;
5595
5596 /* prefer fixed mode from EDID if available */
5597 list_for_each_entry(scan, &connector->probed_modes, head) {
5598 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5599 fixed_mode = drm_mode_duplicate(dev, scan);
5600 downclock_mode = intel_dp_drrs_init(
5601 intel_connector, fixed_mode);
5602 break;
5603 }
5604 }
5605
5606 /* fallback to VBT if available for eDP */
5607 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5608 fixed_mode = drm_mode_duplicate(dev,
5609 dev_priv->vbt.lfp_lvds_vbt_mode);
5610 if (fixed_mode) {
5611 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5612 connector->display_info.width_mm = fixed_mode->width_mm;
5613 connector->display_info.height_mm = fixed_mode->height_mm;
5614 }
5615 }
5616 mutex_unlock(&dev->mode_config.mutex);
5617
5618 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5619 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5620 register_reboot_notifier(&intel_dp->edp_notifier);
5621
5622 /*
5623 * Figure out the current pipe for the initial backlight setup.
5624 * If the current pipe isn't valid, try the PPS pipe, and if that
5625 * fails just assume pipe A.
5626 */
5627 if (IS_CHERRYVIEW(dev_priv))
5628 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5629 else
5630 pipe = PORT_TO_PIPE(intel_dp->DP);
5631
5632 if (pipe != PIPE_A && pipe != PIPE_B)
5633 pipe = intel_dp->pps_pipe;
5634
5635 if (pipe != PIPE_A && pipe != PIPE_B)
5636 pipe = PIPE_A;
5637
5638 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5639 pipe_name(pipe));
5640 }
5641
5642 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5643 intel_connector->panel.backlight.power = intel_edp_backlight_power;
5644 intel_panel_setup_backlight(connector, pipe);
5645
5646 return true;
5647
5648out_vdd_off:
5649 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5650 /*
5651 * vdd might still be enabled do to the delayed vdd off.
5652 * Make sure vdd is actually turned off here.
5653 */
5654 pps_lock(intel_dp);
5655 edp_panel_vdd_off_sync(intel_dp);
5656 pps_unlock(intel_dp);
5657
5658 return false;
5659}
5660
5661bool
5662intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5663 struct intel_connector *intel_connector)
5664{
5665 struct drm_connector *connector = &intel_connector->base;
5666 struct intel_dp *intel_dp = &intel_dig_port->dp;
5667 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5668 struct drm_device *dev = intel_encoder->base.dev;
5669 struct drm_i915_private *dev_priv = to_i915(dev);
5670 enum port port = intel_dig_port->port;
5671 int type;
5672
5673 if (WARN(intel_dig_port->max_lanes < 1,
5674 "Not enough lanes (%d) for DP on port %c\n",
5675 intel_dig_port->max_lanes, port_name(port)))
5676 return false;
5677
5678 intel_dp->pps_pipe = INVALID_PIPE;
5679
5680 /* intel_dp vfuncs */
5681 if (INTEL_GEN(dev_priv) >= 9)
5682 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5683 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5684 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5685 else if (HAS_PCH_SPLIT(dev_priv))
5686 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5687 else
5688 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
5689
5690 if (INTEL_GEN(dev_priv) >= 9)
5691 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5692 else
5693 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
5694
5695 if (HAS_DDI(dev_priv))
5696 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5697
5698 /* Preserve the current hw state. */
5699 intel_dp->DP = I915_READ(intel_dp->output_reg);
5700 intel_dp->attached_connector = intel_connector;
5701
5702 if (intel_dp_is_edp(dev_priv, port))
5703 type = DRM_MODE_CONNECTOR_eDP;
5704 else
5705 type = DRM_MODE_CONNECTOR_DisplayPort;
5706
5707 /*
5708 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5709 * for DP the encoder type can be set by the caller to
5710 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5711 */
5712 if (type == DRM_MODE_CONNECTOR_eDP)
5713 intel_encoder->type = INTEL_OUTPUT_EDP;
5714
5715 /* eDP only on port B and/or C on vlv/chv */
5716 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
5717 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5718 return false;
5719
5720 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5721 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5722 port_name(port));
5723
5724 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5725 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5726
5727 connector->interlace_allowed = true;
5728 connector->doublescan_allowed = 0;
5729
5730 intel_dp_aux_init(intel_dp);
5731
5732 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5733 edp_panel_vdd_work);
5734
5735 intel_connector_attach_encoder(intel_connector, intel_encoder);
5736
5737 if (HAS_DDI(dev_priv))
5738 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5739 else
5740 intel_connector->get_hw_state = intel_connector_get_hw_state;
5741
5742 /* Set up the hotplug pin. */
5743 switch (port) {
5744 case PORT_A:
5745 intel_encoder->hpd_pin = HPD_PORT_A;
5746 break;
5747 case PORT_B:
5748 intel_encoder->hpd_pin = HPD_PORT_B;
5749 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
5750 intel_encoder->hpd_pin = HPD_PORT_A;
5751 break;
5752 case PORT_C:
5753 intel_encoder->hpd_pin = HPD_PORT_C;
5754 break;
5755 case PORT_D:
5756 intel_encoder->hpd_pin = HPD_PORT_D;
5757 break;
5758 case PORT_E:
5759 intel_encoder->hpd_pin = HPD_PORT_E;
5760 break;
5761 default:
5762 BUG();
5763 }
5764
5765 /* init MST on ports that can support it */
5766 if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
5767 (port == PORT_B || port == PORT_C || port == PORT_D))
5768 intel_dp_mst_encoder_init(intel_dig_port,
5769 intel_connector->base.base.id);
5770
5771 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5772 intel_dp_aux_fini(intel_dp);
5773 intel_dp_mst_encoder_cleanup(intel_dig_port);
5774 goto fail;
5775 }
5776
5777 intel_dp_add_properties(intel_dp, connector);
5778
5779 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5780 * 0xd. Failure to do so will result in spurious interrupts being
5781 * generated on the port when a cable is not attached.
5782 */
5783 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
5784 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5785 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5786 }
5787
5788 return true;
5789
5790fail:
5791 drm_connector_cleanup(connector);
5792
5793 return false;
5794}
5795
5796bool intel_dp_init(struct drm_device *dev,
5797 i915_reg_t output_reg,
5798 enum port port)
5799{
5800 struct drm_i915_private *dev_priv = to_i915(dev);
5801 struct intel_digital_port *intel_dig_port;
5802 struct intel_encoder *intel_encoder;
5803 struct drm_encoder *encoder;
5804 struct intel_connector *intel_connector;
5805
5806 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5807 if (!intel_dig_port)
5808 return false;
5809
5810 intel_connector = intel_connector_alloc();
5811 if (!intel_connector)
5812 goto err_connector_alloc;
5813
5814 intel_encoder = &intel_dig_port->base;
5815 encoder = &intel_encoder->base;
5816
5817 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5818 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
5819 goto err_encoder_init;
5820
5821 intel_encoder->compute_config = intel_dp_compute_config;
5822 intel_encoder->disable = intel_disable_dp;
5823 intel_encoder->get_hw_state = intel_dp_get_hw_state;
5824 intel_encoder->get_config = intel_dp_get_config;
5825 intel_encoder->suspend = intel_dp_encoder_suspend;
5826 if (IS_CHERRYVIEW(dev_priv)) {
5827 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5828 intel_encoder->pre_enable = chv_pre_enable_dp;
5829 intel_encoder->enable = vlv_enable_dp;
5830 intel_encoder->post_disable = chv_post_disable_dp;
5831 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
5832 } else if (IS_VALLEYVIEW(dev_priv)) {
5833 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5834 intel_encoder->pre_enable = vlv_pre_enable_dp;
5835 intel_encoder->enable = vlv_enable_dp;
5836 intel_encoder->post_disable = vlv_post_disable_dp;
5837 } else {
5838 intel_encoder->pre_enable = g4x_pre_enable_dp;
5839 intel_encoder->enable = g4x_enable_dp;
5840 if (INTEL_GEN(dev_priv) >= 5)
5841 intel_encoder->post_disable = ilk_post_disable_dp;
5842 }
5843
5844 intel_dig_port->port = port;
5845 intel_dig_port->dp.output_reg = output_reg;
5846 intel_dig_port->max_lanes = 4;
5847
5848 intel_encoder->type = INTEL_OUTPUT_DP;
5849 if (IS_CHERRYVIEW(dev_priv)) {
5850 if (port == PORT_D)
5851 intel_encoder->crtc_mask = 1 << 2;
5852 else
5853 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5854 } else {
5855 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5856 }
5857 intel_encoder->cloneable = 0;
5858 intel_encoder->port = port;
5859
5860 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5861 dev_priv->hotplug.irq_port[port] = intel_dig_port;
5862
5863 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5864 goto err_init_connector;
5865
5866 return true;
5867
5868err_init_connector:
5869 drm_encoder_cleanup(encoder);
5870err_encoder_init:
5871 kfree(intel_connector);
5872err_connector_alloc:
5873 kfree(intel_dig_port);
5874 return false;
5875}
5876
5877void intel_dp_mst_suspend(struct drm_device *dev)
5878{
5879 struct drm_i915_private *dev_priv = to_i915(dev);
5880 int i;
5881
5882 /* disable MST */
5883 for (i = 0; i < I915_MAX_PORTS; i++) {
5884 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5885
5886 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5887 continue;
5888
5889 if (intel_dig_port->dp.is_mst)
5890 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5891 }
5892}
5893
5894void intel_dp_mst_resume(struct drm_device *dev)
5895{
5896 struct drm_i915_private *dev_priv = to_i915(dev);
5897 int i;
5898
5899 for (i = 0; i < I915_MAX_PORTS; i++) {
5900 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5901 int ret;
5902
5903 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5904 continue;
5905
5906 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5907 if (ret)
5908 intel_dp_check_mst_status(&intel_dig_port->dp);
5909 }
5910}